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authorArnd Bergmann <arnd@arndb.de>2011-07-21 10:34:00 -0400
committerArnd Bergmann <arnd@arndb.de>2011-07-21 10:34:00 -0400
commit1e09939bad24df95ddeeeca4fbec64fa94b66def (patch)
tree8a4661ed8c4619db28863353858e0171171b7d8a /arch
parent4d09a938861ef16248334d57ae250e109b0004ae (diff)
parente8de616e39ccea3b8d3cf7e68f16d216f183c4bf (diff)
Merge branch 'next-samsung-devel' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/devel
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/common/gic.c6
-rw-r--r--arch/arm/include/asm/hardware/gic.h6
-rw-r--r--arch/arm/mach-exynos4/Kconfig30
-rw-r--r--arch/arm/mach-exynos4/Makefile11
-rw-r--r--arch/arm/mach-exynos4/clock.c238
-rw-r--r--arch/arm/mach-exynos4/cpu.c39
-rw-r--r--arch/arm/mach-exynos4/dev-audio.c2
-rw-r--r--arch/arm/mach-exynos4/dev-dwmci.c82
-rw-r--r--arch/arm/mach-exynos4/hotplug.c13
-rw-r--r--arch/arm/mach-exynos4/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/dwmci.h20
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S11
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h196
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h19
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h10
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h25
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h12
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos4/localtimer.c26
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c753
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c71
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c3
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c121
-rw-r--r--arch/arm/mach-exynos4/mct.c2
-rw-r--r--arch/arm/mach-exynos4/platsmp.c57
-rw-r--r--arch/arm/mach-exynos4/pm.c275
-rw-r--r--arch/arm/mach-exynos4/pmu.c175
-rw-r--r--arch/arm/mach-exynos4/setup-fimd0.c43
-rw-r--r--arch/arm/mach-exynos4/time.c301
-rw-r--r--arch/arm/mach-s3c2410/include/mach/pm-core.h3
-rw-r--r--arch/arm/mach-s3c2412/clock.c36
-rw-r--r--arch/arm/mach-s3c2416/clock.c10
-rw-r--r--arch/arm/mach-s3c2440/clock.c3
-rw-r--r--arch/arm/mach-s3c2443/clock.c16
-rw-r--r--arch/arm/mach-s3c64xx/clock.c86
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pm-core.h19
-rw-r--r--arch/arm/mach-s3c64xx/irq.c12
-rw-r--r--arch/arm/mach-s5p64x0/Makefile2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c74
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c68
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h10
-rw-r--r--arch/arm/mach-s5p64x0/irq-eint.c152
-rw-r--r--arch/arm/mach-s5pc100/clock.c163
-rw-r--r--arch/arm/mach-s5pc100/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5pv210/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/clock.c137
-rw-r--r--arch/arm/mach-s5pv210/cpu.c2
-rw-r--r--arch/arm/mach-s5pv210/dev-audio.c2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/pm-core.h3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c11
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c1
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c4
-rw-r--r--arch/arm/plat-s3c24xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c21
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c39
-rw-r--r--arch/arm/plat-s5p/Kconfig11
-rw-r--r--arch/arm/plat-s5p/Makefile3
-rw-r--r--arch/arm/plat-s5p/dev-fimd0.c67
-rw-r--r--arch/arm/plat-s5p/dev-mfc.c123
-rw-r--r--arch/arm/plat-s5p/include/plat/map-s5p.h5
-rw-r--r--arch/arm/plat-s5p/include/plat/mfc.h27
-rw-r--r--arch/arm/plat-s5p/s5p-time.c9
-rw-r--r--arch/arm/plat-samsung/adc.c84
-rw-r--r--arch/arm/plat-samsung/clock.c98
-rw-r--r--arch/arm/plat-samsung/dev-asocdma.c10
-rw-r--r--arch/arm/plat-samsung/include/plat/audio.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-core.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-adc.h1
-rw-r--r--arch/arm/plat-samsung/irq-uart.c7
-rw-r--r--arch/arm/plat-samsung/pm.c2
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c10
-rw-r--r--arch/arm/plat-samsung/time.c2
84 files changed, 2713 insertions, 1301 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a9bb43957443..54d63f1e9a91 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -684,6 +684,7 @@ config ARCH_S3C2410
684 select GENERIC_GPIO 684 select GENERIC_GPIO
685 select ARCH_HAS_CPUFREQ 685 select ARCH_HAS_CPUFREQ
686 select HAVE_CLK 686 select HAVE_CLK
687 select CLKDEV_LOOKUP
687 select ARCH_USES_GETTIMEOFFSET 688 select ARCH_USES_GETTIMEOFFSET
688 select HAVE_S3C2410_I2C if I2C 689 select HAVE_S3C2410_I2C if I2C
689 help 690 help
@@ -701,6 +702,7 @@ config ARCH_S3C64XX
701 select CPU_V6 702 select CPU_V6
702 select ARM_VIC 703 select ARM_VIC
703 select HAVE_CLK 704 select HAVE_CLK
705 select CLKDEV_LOOKUP
704 select NO_IOPORT 706 select NO_IOPORT
705 select ARCH_USES_GETTIMEOFFSET 707 select ARCH_USES_GETTIMEOFFSET
706 select ARCH_HAS_CPUFREQ 708 select ARCH_HAS_CPUFREQ
@@ -725,6 +727,7 @@ config ARCH_S5P64X0
725 select CPU_V6 727 select CPU_V6
726 select GENERIC_GPIO 728 select GENERIC_GPIO
727 select HAVE_CLK 729 select HAVE_CLK
730 select CLKDEV_LOOKUP
728 select HAVE_S3C2410_WATCHDOG if WATCHDOG 731 select HAVE_S3C2410_WATCHDOG if WATCHDOG
729 select GENERIC_CLOCKEVENTS 732 select GENERIC_CLOCKEVENTS
730 select HAVE_SCHED_CLOCK 733 select HAVE_SCHED_CLOCK
@@ -738,6 +741,7 @@ config ARCH_S5PC100
738 bool "Samsung S5PC100" 741 bool "Samsung S5PC100"
739 select GENERIC_GPIO 742 select GENERIC_GPIO
740 select HAVE_CLK 743 select HAVE_CLK
744 select CLKDEV_LOOKUP
741 select CPU_V7 745 select CPU_V7
742 select ARM_L1_CACHE_SHIFT_6 746 select ARM_L1_CACHE_SHIFT_6
743 select ARCH_USES_GETTIMEOFFSET 747 select ARCH_USES_GETTIMEOFFSET
@@ -751,8 +755,10 @@ config ARCH_S5PV210
751 bool "Samsung S5PV210/S5PC110" 755 bool "Samsung S5PV210/S5PC110"
752 select CPU_V7 756 select CPU_V7
753 select ARCH_SPARSEMEM_ENABLE 757 select ARCH_SPARSEMEM_ENABLE
758 select ARCH_HAS_HOLES_MEMORYMODEL
754 select GENERIC_GPIO 759 select GENERIC_GPIO
755 select HAVE_CLK 760 select HAVE_CLK
761 select CLKDEV_LOOKUP
756 select ARM_L1_CACHE_SHIFT_6 762 select ARM_L1_CACHE_SHIFT_6
757 select ARCH_HAS_CPUFREQ 763 select ARCH_HAS_CPUFREQ
758 select GENERIC_CLOCKEVENTS 764 select GENERIC_CLOCKEVENTS
@@ -767,8 +773,10 @@ config ARCH_EXYNOS4
767 bool "Samsung EXYNOS4" 773 bool "Samsung EXYNOS4"
768 select CPU_V7 774 select CPU_V7
769 select ARCH_SPARSEMEM_ENABLE 775 select ARCH_SPARSEMEM_ENABLE
776 select ARCH_HAS_HOLES_MEMORYMODEL
770 select GENERIC_GPIO 777 select GENERIC_GPIO
771 select HAVE_CLK 778 select HAVE_CLK
779 select CLKDEV_LOOKUP
772 select ARCH_HAS_CPUFREQ 780 select ARCH_HAS_CPUFREQ
773 select GENERIC_CLOCKEVENTS 781 select GENERIC_CLOCKEVENTS
774 select HAVE_S3C_RTC if RTC_CLASS 782 select HAVE_S3C_RTC if RTC_CLASS
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 4ddd0a6ac7ff..23564edbd849 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
38/* Address of GIC 0 CPU interface */ 38/* Address of GIC 0 CPU interface */
39void __iomem *gic_cpu_base_addr __read_mostly; 39void __iomem *gic_cpu_base_addr __read_mostly;
40 40
41struct gic_chip_data {
42 unsigned int irq_offset;
43 void __iomem *dist_base;
44 void __iomem *cpu_base;
45};
46
47/* 41/*
48 * Supported arch specific GIC irq extension. 42 * Supported arch specific GIC irq extension.
49 * Default make them NULL. 43 * Default make them NULL.
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 0691f9dcc500..435d3f86c708 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); 42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
43void gic_enable_ppi(unsigned int); 43void gic_enable_ppi(unsigned int);
44
45struct gic_chip_data {
46 unsigned int irq_offset;
47 void __iomem *dist_base;
48 void __iomem *cpu_base;
49};
44#endif 50#endif
45 51
46#endif 52#endif
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1435fc31c4b2..dd8ae586ac56 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
16 Enable EXYNOS4210 CPU support 16 Enable EXYNOS4210 CPU support
17 17
18config EXYNOS4_MCT 18config EXYNOS4_MCT
19 bool "Kernel timer support by MCT" 19 bool
20 default y
20 help 21 help
21 Use MCT (Multi Core Timer) as kernel timers 22 Use MCT (Multi Core Timer) as kernel timers
22 23
@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
25 help 26 help
26 Compile in platform device definitions for AHCI 27 Compile in platform device definitions for AHCI
27 28
29config EXYNOS4_SETUP_FIMD0
30 bool
31 help
32 Common setup code for FIMD0.
33
28config EXYNOS4_DEV_PD 34config EXYNOS4_DEV_PD
29 bool 35 bool
30 help 36 help
@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
35 help 41 help
36 Common setup code for SYSTEM MMU in EXYNOS4 42 Common setup code for SYSTEM MMU in EXYNOS4
37 43
44config EXYNOS4_DEV_DWMCI
45 bool
46 help
47 Compile in platform device definitions for DWMCI
48
38config EXYNOS4_SETUP_I2C1 49config EXYNOS4_SETUP_I2C1
39 bool 50 bool
40 help 51 help
@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
103config MACH_SMDKC210 114config MACH_SMDKC210
104 bool "SMDKC210" 115 bool "SMDKC210"
105 select CPU_EXYNOS4210 116 select CPU_EXYNOS4210
117 select S5P_DEV_FIMD0
106 select S3C_DEV_RTC 118 select S3C_DEV_RTC
107 select S3C_DEV_WDT 119 select S3C_DEV_WDT
108 select S3C_DEV_I2C1 120 select S3C_DEV_I2C1
@@ -112,6 +124,7 @@ config MACH_SMDKC210
112 select S3C_DEV_HSMMC3 124 select S3C_DEV_HSMMC3
113 select EXYNOS4_DEV_PD 125 select EXYNOS4_DEV_PD
114 select EXYNOS4_DEV_SYSMMU 126 select EXYNOS4_DEV_SYSMMU
127 select EXYNOS4_SETUP_FIMD0
115 select EXYNOS4_SETUP_I2C1 128 select EXYNOS4_SETUP_I2C1
116 select EXYNOS4_SETUP_SDHCI 129 select EXYNOS4_SETUP_SDHCI
117 help 130 help
@@ -120,6 +133,7 @@ config MACH_SMDKC210
120config MACH_SMDKV310 133config MACH_SMDKV310
121 bool "SMDKV310" 134 bool "SMDKV310"
122 select CPU_EXYNOS4210 135 select CPU_EXYNOS4210
136 select S5P_DEV_FIMD0
123 select S3C_DEV_RTC 137 select S3C_DEV_RTC
124 select S3C_DEV_WDT 138 select S3C_DEV_WDT
125 select S3C_DEV_I2C1 139 select S3C_DEV_I2C1
@@ -127,9 +141,11 @@ config MACH_SMDKV310
127 select S3C_DEV_HSMMC1 141 select S3C_DEV_HSMMC1
128 select S3C_DEV_HSMMC2 142 select S3C_DEV_HSMMC2
129 select S3C_DEV_HSMMC3 143 select S3C_DEV_HSMMC3
144 select EXYNOS4_DEV_AHCI
130 select SAMSUNG_DEV_KEYPAD 145 select SAMSUNG_DEV_KEYPAD
131 select EXYNOS4_DEV_PD 146 select EXYNOS4_DEV_PD
132 select EXYNOS4_DEV_SYSMMU 147 select EXYNOS4_DEV_SYSMMU
148 select EXYNOS4_SETUP_FIMD0
133 select EXYNOS4_SETUP_I2C1 149 select EXYNOS4_SETUP_I2C1
134 select EXYNOS4_SETUP_KEYPAD 150 select EXYNOS4_SETUP_KEYPAD
135 select EXYNOS4_SETUP_SDHCI 151 select EXYNOS4_SETUP_SDHCI
@@ -153,13 +169,22 @@ config MACH_ARMLEX4210
153config MACH_UNIVERSAL_C210 169config MACH_UNIVERSAL_C210
154 bool "Mobile UNIVERSAL_C210 Board" 170 bool "Mobile UNIVERSAL_C210 Board"
155 select CPU_EXYNOS4210 171 select CPU_EXYNOS4210
172 select S5P_GPIO_INT
173 select S5P_DEV_FIMC0
174 select S5P_DEV_FIMC1
175 select S5P_DEV_FIMC2
176 select S5P_DEV_FIMC3
156 select S3C_DEV_HSMMC 177 select S3C_DEV_HSMMC
157 select S3C_DEV_HSMMC2 178 select S3C_DEV_HSMMC2
158 select S3C_DEV_HSMMC3 179 select S3C_DEV_HSMMC3
159 select S3C_DEV_I2C1 180 select S3C_DEV_I2C1
181 select S3C_DEV_I2C3
160 select S3C_DEV_I2C5 182 select S3C_DEV_I2C5
183 select S5P_DEV_MFC
161 select S5P_DEV_ONENAND 184 select S5P_DEV_ONENAND
185 select EXYNOS4_DEV_PD
162 select EXYNOS4_SETUP_I2C1 186 select EXYNOS4_SETUP_I2C1
187 select EXYNOS4_SETUP_I2C3
163 select EXYNOS4_SETUP_I2C5 188 select EXYNOS4_SETUP_I2C5
164 select EXYNOS4_SETUP_SDHCI 189 select EXYNOS4_SETUP_SDHCI
165 help 190 help
@@ -176,13 +201,16 @@ config MACH_NURI
176 select S3C_DEV_I2C1 201 select S3C_DEV_I2C1
177 select S3C_DEV_I2C3 202 select S3C_DEV_I2C3
178 select S3C_DEV_I2C5 203 select S3C_DEV_I2C5
204 select S5P_DEV_MFC
179 select S5P_DEV_USB_EHCI 205 select S5P_DEV_USB_EHCI
206 select EXYNOS4_DEV_PD
180 select EXYNOS4_SETUP_I2C1 207 select EXYNOS4_SETUP_I2C1
181 select EXYNOS4_SETUP_I2C3 208 select EXYNOS4_SETUP_I2C3
182 select EXYNOS4_SETUP_I2C5 209 select EXYNOS4_SETUP_I2C5
183 select EXYNOS4_SETUP_SDHCI 210 select EXYNOS4_SETUP_SDHCI
184 select EXYNOS4_SETUP_USB_PHY 211 select EXYNOS4_SETUP_USB_PHY
185 select SAMSUNG_DEV_PWM 212 select SAMSUNG_DEV_PWM
213 select SAMSUNG_DEV_ADC
186 help 214 help
187 Machine support for Samsung Mobile NURI Board. 215 Machine support for Samsung Mobile NURI Board.
188 216
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ecf3599..e8b33aba14d8 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,19 +13,14 @@ obj- :=
13# Core support for EXYNOS4 system 13# Core support for EXYNOS4 system
14 14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o 16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
17obj-$(CONFIG_PM) += pm.o sleep.o 17obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o 18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19obj-$(CONFIG_CPU_IDLE) += cpuidle.o 19obj-$(CONFIG_CPU_IDLE) += cpuidle.o
20 20
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 21obj-$(CONFIG_SMP) += platsmp.o headsmp.o
22 22
23ifeq ($(CONFIG_EXYNOS4_MCT),y) 23obj-$(CONFIG_EXYNOS4_MCT) += mct.o
24obj-y += mct.o
25else
26obj-y += time.o
27obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
28endif
29 24
30obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 25obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
31 26
@@ -43,8 +38,10 @@ obj-y += dev-audio.o
43obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 38obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
44obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 39obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
45obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 40obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
41obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
46 42
47obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 43obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
44obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
48obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 45obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
49obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o 46obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o 47obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d508fde..851dea018578 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -27,24 +27,20 @@
27 27
28static struct clk clk_sclk_hdmi27m = { 28static struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m", 29 .name = "sclk_hdmi27m",
30 .id = -1,
31 .rate = 27000000, 30 .rate = 27000000,
32}; 31};
33 32
34static struct clk clk_sclk_hdmiphy = { 33static struct clk clk_sclk_hdmiphy = {
35 .name = "sclk_hdmiphy", 34 .name = "sclk_hdmiphy",
36 .id = -1,
37}; 35};
38 36
39static struct clk clk_sclk_usbphy0 = { 37static struct clk clk_sclk_usbphy0 = {
40 .name = "sclk_usbphy0", 38 .name = "sclk_usbphy0",
41 .id = -1,
42 .rate = 27000000, 39 .rate = 27000000,
43}; 40};
44 41
45static struct clk clk_sclk_usbphy1 = { 42static struct clk clk_sclk_usbphy1 = {
46 .name = "sclk_usbphy1", 43 .name = "sclk_usbphy1",
47 .id = -1,
48}; 44};
49 45
50static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) 46static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
132static struct clksrc_clk clk_mout_apll = { 128static struct clksrc_clk clk_mout_apll = {
133 .clk = { 129 .clk = {
134 .name = "mout_apll", 130 .name = "mout_apll",
135 .id = -1,
136 }, 131 },
137 .sources = &clk_src_apll, 132 .sources = &clk_src_apll,
138 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
141static struct clksrc_clk clk_sclk_apll = { 136static struct clksrc_clk clk_sclk_apll = {
142 .clk = { 137 .clk = {
143 .name = "sclk_apll", 138 .name = "sclk_apll",
144 .id = -1,
145 .parent = &clk_mout_apll.clk, 139 .parent = &clk_mout_apll.clk,
146 }, 140 },
147 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
150static struct clksrc_clk clk_mout_epll = { 144static struct clksrc_clk clk_mout_epll = {
151 .clk = { 145 .clk = {
152 .name = "mout_epll", 146 .name = "mout_epll",
153 .id = -1,
154 }, 147 },
155 .sources = &clk_src_epll, 148 .sources = &clk_src_epll,
156 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
159static struct clksrc_clk clk_mout_mpll = { 152static struct clksrc_clk clk_mout_mpll = {
160 .clk = { 153 .clk = {
161 .name = "mout_mpll", 154 .name = "mout_mpll",
162 .id = -1,
163 }, 155 },
164 .sources = &clk_src_mpll, 156 .sources = &clk_src_mpll,
165 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, 157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
178static struct clksrc_clk clk_moutcore = { 170static struct clksrc_clk clk_moutcore = {
179 .clk = { 171 .clk = {
180 .name = "moutcore", 172 .name = "moutcore",
181 .id = -1,
182 }, 173 },
183 .sources = &clkset_moutcore, 174 .sources = &clkset_moutcore,
184 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, 175 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
187static struct clksrc_clk clk_coreclk = { 178static struct clksrc_clk clk_coreclk = {
188 .clk = { 179 .clk = {
189 .name = "core_clk", 180 .name = "core_clk",
190 .id = -1,
191 .parent = &clk_moutcore.clk, 181 .parent = &clk_moutcore.clk,
192 }, 182 },
193 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, 183 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
196static struct clksrc_clk clk_armclk = { 186static struct clksrc_clk clk_armclk = {
197 .clk = { 187 .clk = {
198 .name = "armclk", 188 .name = "armclk",
199 .id = -1,
200 .parent = &clk_coreclk.clk, 189 .parent = &clk_coreclk.clk,
201 }, 190 },
202}; 191};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
204static struct clksrc_clk clk_aclk_corem0 = { 193static struct clksrc_clk clk_aclk_corem0 = {
205 .clk = { 194 .clk = {
206 .name = "aclk_corem0", 195 .name = "aclk_corem0",
207 .id = -1,
208 .parent = &clk_coreclk.clk, 196 .parent = &clk_coreclk.clk,
209 }, 197 },
210 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 198 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
213static struct clksrc_clk clk_aclk_cores = { 201static struct clksrc_clk clk_aclk_cores = {
214 .clk = { 202 .clk = {
215 .name = "aclk_cores", 203 .name = "aclk_cores",
216 .id = -1,
217 .parent = &clk_coreclk.clk, 204 .parent = &clk_coreclk.clk,
218 }, 205 },
219 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 206 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
222static struct clksrc_clk clk_aclk_corem1 = { 209static struct clksrc_clk clk_aclk_corem1 = {
223 .clk = { 210 .clk = {
224 .name = "aclk_corem1", 211 .name = "aclk_corem1",
225 .id = -1,
226 .parent = &clk_coreclk.clk, 212 .parent = &clk_coreclk.clk,
227 }, 213 },
228 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, 214 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
231static struct clksrc_clk clk_periphclk = { 217static struct clksrc_clk clk_periphclk = {
232 .clk = { 218 .clk = {
233 .name = "periphclk", 219 .name = "periphclk",
234 .id = -1,
235 .parent = &clk_coreclk.clk, 220 .parent = &clk_coreclk.clk,
236 }, 221 },
237 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 222 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
252static struct clksrc_clk clk_mout_corebus = { 237static struct clksrc_clk clk_mout_corebus = {
253 .clk = { 238 .clk = {
254 .name = "mout_corebus", 239 .name = "mout_corebus",
255 .id = -1,
256 }, 240 },
257 .sources = &clkset_mout_corebus, 241 .sources = &clkset_mout_corebus,
258 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, 242 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
261static struct clksrc_clk clk_sclk_dmc = { 245static struct clksrc_clk clk_sclk_dmc = {
262 .clk = { 246 .clk = {
263 .name = "sclk_dmc", 247 .name = "sclk_dmc",
264 .id = -1,
265 .parent = &clk_mout_corebus.clk, 248 .parent = &clk_mout_corebus.clk,
266 }, 249 },
267 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, 250 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
270static struct clksrc_clk clk_aclk_cored = { 253static struct clksrc_clk clk_aclk_cored = {
271 .clk = { 254 .clk = {
272 .name = "aclk_cored", 255 .name = "aclk_cored",
273 .id = -1,
274 .parent = &clk_sclk_dmc.clk, 256 .parent = &clk_sclk_dmc.clk,
275 }, 257 },
276 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, 258 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
279static struct clksrc_clk clk_aclk_corep = { 261static struct clksrc_clk clk_aclk_corep = {
280 .clk = { 262 .clk = {
281 .name = "aclk_corep", 263 .name = "aclk_corep",
282 .id = -1,
283 .parent = &clk_aclk_cored.clk, 264 .parent = &clk_aclk_cored.clk,
284 }, 265 },
285 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, 266 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
288static struct clksrc_clk clk_aclk_acp = { 269static struct clksrc_clk clk_aclk_acp = {
289 .clk = { 270 .clk = {
290 .name = "aclk_acp", 271 .name = "aclk_acp",
291 .id = -1,
292 .parent = &clk_mout_corebus.clk, 272 .parent = &clk_mout_corebus.clk,
293 }, 273 },
294 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
297static struct clksrc_clk clk_pclk_acp = { 277static struct clksrc_clk clk_pclk_acp = {
298 .clk = { 278 .clk = {
299 .name = "pclk_acp", 279 .name = "pclk_acp",
300 .id = -1,
301 .parent = &clk_aclk_acp.clk, 280 .parent = &clk_aclk_acp.clk,
302 }, 281 },
303 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, 282 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
318static struct clksrc_clk clk_aclk_200 = { 297static struct clksrc_clk clk_aclk_200 = {
319 .clk = { 298 .clk = {
320 .name = "aclk_200", 299 .name = "aclk_200",
321 .id = -1,
322 }, 300 },
323 .sources = &clkset_aclk, 301 .sources = &clkset_aclk,
324 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 302 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
328static struct clksrc_clk clk_aclk_100 = { 306static struct clksrc_clk clk_aclk_100 = {
329 .clk = { 307 .clk = {
330 .name = "aclk_100", 308 .name = "aclk_100",
331 .id = -1,
332 }, 309 },
333 .sources = &clkset_aclk, 310 .sources = &clkset_aclk,
334 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 311 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
338static struct clksrc_clk clk_aclk_160 = { 315static struct clksrc_clk clk_aclk_160 = {
339 .clk = { 316 .clk = {
340 .name = "aclk_160", 317 .name = "aclk_160",
341 .id = -1,
342 }, 318 },
343 .sources = &clkset_aclk, 319 .sources = &clkset_aclk,
344 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 320 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
348static struct clksrc_clk clk_aclk_133 = { 324static struct clksrc_clk clk_aclk_133 = {
349 .clk = { 325 .clk = {
350 .name = "aclk_133", 326 .name = "aclk_133",
351 .id = -1,
352 }, 327 },
353 .sources = &clkset_aclk, 328 .sources = &clkset_aclk,
354 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 329 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
368static struct clksrc_clk clk_vpllsrc = { 343static struct clksrc_clk clk_vpllsrc = {
369 .clk = { 344 .clk = {
370 .name = "vpll_src", 345 .name = "vpll_src",
371 .id = -1,
372 .enable = exynos4_clksrc_mask_top_ctrl, 346 .enable = exynos4_clksrc_mask_top_ctrl,
373 .ctrlbit = (1 << 0), 347 .ctrlbit = (1 << 0),
374 }, 348 },
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
389static struct clksrc_clk clk_sclk_vpll = { 363static struct clksrc_clk clk_sclk_vpll = {
390 .clk = { 364 .clk = {
391 .name = "sclk_vpll", 365 .name = "sclk_vpll",
392 .id = -1,
393 }, 366 },
394 .sources = &clkset_sclk_vpll, 367 .sources = &clkset_sclk_vpll,
395 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 368 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
398static struct clk init_clocks_off[] = { 371static struct clk init_clocks_off[] = {
399 { 372 {
400 .name = "timers", 373 .name = "timers",
401 .id = -1,
402 .parent = &clk_aclk_100.clk, 374 .parent = &clk_aclk_100.clk,
403 .enable = exynos4_clk_ip_peril_ctrl, 375 .enable = exynos4_clk_ip_peril_ctrl,
404 .ctrlbit = (1<<24), 376 .ctrlbit = (1<<24),
405 }, { 377 }, {
406 .name = "csis", 378 .name = "csis",
407 .id = 0, 379 .devname = "s5p-mipi-csis.0",
408 .enable = exynos4_clk_ip_cam_ctrl, 380 .enable = exynos4_clk_ip_cam_ctrl,
409 .ctrlbit = (1 << 4), 381 .ctrlbit = (1 << 4),
410 }, { 382 }, {
411 .name = "csis", 383 .name = "csis",
412 .id = 1, 384 .devname = "s5p-mipi-csis.1",
413 .enable = exynos4_clk_ip_cam_ctrl, 385 .enable = exynos4_clk_ip_cam_ctrl,
414 .ctrlbit = (1 << 5), 386 .ctrlbit = (1 << 5),
415 }, { 387 }, {
416 .name = "fimc", 388 .name = "fimc",
417 .id = 0, 389 .devname = "exynos4-fimc.0",
418 .enable = exynos4_clk_ip_cam_ctrl, 390 .enable = exynos4_clk_ip_cam_ctrl,
419 .ctrlbit = (1 << 0), 391 .ctrlbit = (1 << 0),
420 }, { 392 }, {
421 .name = "fimc", 393 .name = "fimc",
422 .id = 1, 394 .devname = "exynos4-fimc.1",
423 .enable = exynos4_clk_ip_cam_ctrl, 395 .enable = exynos4_clk_ip_cam_ctrl,
424 .ctrlbit = (1 << 1), 396 .ctrlbit = (1 << 1),
425 }, { 397 }, {
426 .name = "fimc", 398 .name = "fimc",
427 .id = 2, 399 .devname = "exynos4-fimc.2",
428 .enable = exynos4_clk_ip_cam_ctrl, 400 .enable = exynos4_clk_ip_cam_ctrl,
429 .ctrlbit = (1 << 2), 401 .ctrlbit = (1 << 2),
430 }, { 402 }, {
431 .name = "fimc", 403 .name = "fimc",
432 .id = 3, 404 .devname = "exynos4-fimc.3",
433 .enable = exynos4_clk_ip_cam_ctrl, 405 .enable = exynos4_clk_ip_cam_ctrl,
434 .ctrlbit = (1 << 3), 406 .ctrlbit = (1 << 3),
435 }, { 407 }, {
436 .name = "fimd", 408 .name = "fimd",
437 .id = 0, 409 .devname = "exynos4-fb.0",
438 .enable = exynos4_clk_ip_lcd0_ctrl, 410 .enable = exynos4_clk_ip_lcd0_ctrl,
439 .ctrlbit = (1 << 0), 411 .ctrlbit = (1 << 0),
440 }, { 412 }, {
441 .name = "fimd", 413 .name = "fimd",
442 .id = 1, 414 .devname = "exynos4-fb.1",
443 .enable = exynos4_clk_ip_lcd1_ctrl, 415 .enable = exynos4_clk_ip_lcd1_ctrl,
444 .ctrlbit = (1 << 0), 416 .ctrlbit = (1 << 0),
445 }, { 417 }, {
446 .name = "sataphy", 418 .name = "sataphy",
447 .id = -1,
448 .parent = &clk_aclk_133.clk, 419 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl, 420 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 3), 421 .ctrlbit = (1 << 3),
451 }, { 422 }, {
452 .name = "hsmmc", 423 .name = "hsmmc",
453 .id = 0, 424 .devname = "s3c-sdhci.0",
454 .parent = &clk_aclk_133.clk, 425 .parent = &clk_aclk_133.clk,
455 .enable = exynos4_clk_ip_fsys_ctrl, 426 .enable = exynos4_clk_ip_fsys_ctrl,
456 .ctrlbit = (1 << 5), 427 .ctrlbit = (1 << 5),
457 }, { 428 }, {
458 .name = "hsmmc", 429 .name = "hsmmc",
459 .id = 1, 430 .devname = "s3c-sdhci.1",
460 .parent = &clk_aclk_133.clk, 431 .parent = &clk_aclk_133.clk,
461 .enable = exynos4_clk_ip_fsys_ctrl, 432 .enable = exynos4_clk_ip_fsys_ctrl,
462 .ctrlbit = (1 << 6), 433 .ctrlbit = (1 << 6),
463 }, { 434 }, {
464 .name = "hsmmc", 435 .name = "hsmmc",
465 .id = 2, 436 .devname = "s3c-sdhci.2",
466 .parent = &clk_aclk_133.clk, 437 .parent = &clk_aclk_133.clk,
467 .enable = exynos4_clk_ip_fsys_ctrl, 438 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 7), 439 .ctrlbit = (1 << 7),
469 }, { 440 }, {
470 .name = "hsmmc", 441 .name = "hsmmc",
471 .id = 3, 442 .devname = "s3c-sdhci.3",
472 .parent = &clk_aclk_133.clk, 443 .parent = &clk_aclk_133.clk,
473 .enable = exynos4_clk_ip_fsys_ctrl, 444 .enable = exynos4_clk_ip_fsys_ctrl,
474 .ctrlbit = (1 << 8), 445 .ctrlbit = (1 << 8),
475 }, { 446 }, {
476 .name = "hsmmc", 447 .name = "dwmmc",
477 .id = 4,
478 .parent = &clk_aclk_133.clk, 448 .parent = &clk_aclk_133.clk,
479 .enable = exynos4_clk_ip_fsys_ctrl, 449 .enable = exynos4_clk_ip_fsys_ctrl,
480 .ctrlbit = (1 << 9), 450 .ctrlbit = (1 << 9),
481 }, { 451 }, {
482 .name = "sata", 452 .name = "sata",
483 .id = -1,
484 .parent = &clk_aclk_133.clk, 453 .parent = &clk_aclk_133.clk,
485 .enable = exynos4_clk_ip_fsys_ctrl, 454 .enable = exynos4_clk_ip_fsys_ctrl,
486 .ctrlbit = (1 << 10), 455 .ctrlbit = (1 << 10),
487 }, { 456 }, {
488 .name = "pdma", 457 .name = "pdma",
489 .id = 0, 458 .devname = "s3c-pl330.0",
490 .enable = exynos4_clk_ip_fsys_ctrl, 459 .enable = exynos4_clk_ip_fsys_ctrl,
491 .ctrlbit = (1 << 0), 460 .ctrlbit = (1 << 0),
492 }, { 461 }, {
493 .name = "pdma", 462 .name = "pdma",
494 .id = 1, 463 .devname = "s3c-pl330.1",
495 .enable = exynos4_clk_ip_fsys_ctrl, 464 .enable = exynos4_clk_ip_fsys_ctrl,
496 .ctrlbit = (1 << 1), 465 .ctrlbit = (1 << 1),
497 }, { 466 }, {
498 .name = "adc", 467 .name = "adc",
499 .id = -1,
500 .enable = exynos4_clk_ip_peril_ctrl, 468 .enable = exynos4_clk_ip_peril_ctrl,
501 .ctrlbit = (1 << 15), 469 .ctrlbit = (1 << 15),
502 }, { 470 }, {
503 .name = "keypad", 471 .name = "keypad",
504 .id = -1,
505 .enable = exynos4_clk_ip_perir_ctrl, 472 .enable = exynos4_clk_ip_perir_ctrl,
506 .ctrlbit = (1 << 16), 473 .ctrlbit = (1 << 16),
507 }, { 474 }, {
508 .name = "rtc", 475 .name = "rtc",
509 .id = -1,
510 .enable = exynos4_clk_ip_perir_ctrl, 476 .enable = exynos4_clk_ip_perir_ctrl,
511 .ctrlbit = (1 << 15), 477 .ctrlbit = (1 << 15),
512 }, { 478 }, {
513 .name = "watchdog", 479 .name = "watchdog",
514 .id = -1,
515 .parent = &clk_aclk_100.clk, 480 .parent = &clk_aclk_100.clk,
516 .enable = exynos4_clk_ip_perir_ctrl, 481 .enable = exynos4_clk_ip_perir_ctrl,
517 .ctrlbit = (1 << 14), 482 .ctrlbit = (1 << 14),
518 }, { 483 }, {
519 .name = "usbhost", 484 .name = "usbhost",
520 .id = -1,
521 .enable = exynos4_clk_ip_fsys_ctrl , 485 .enable = exynos4_clk_ip_fsys_ctrl ,
522 .ctrlbit = (1 << 12), 486 .ctrlbit = (1 << 12),
523 }, { 487 }, {
524 .name = "otg", 488 .name = "otg",
525 .id = -1,
526 .enable = exynos4_clk_ip_fsys_ctrl, 489 .enable = exynos4_clk_ip_fsys_ctrl,
527 .ctrlbit = (1 << 13), 490 .ctrlbit = (1 << 13),
528 }, { 491 }, {
529 .name = "spi", 492 .name = "spi",
530 .id = 0, 493 .devname = "s3c64xx-spi.0",
531 .enable = exynos4_clk_ip_peril_ctrl, 494 .enable = exynos4_clk_ip_peril_ctrl,
532 .ctrlbit = (1 << 16), 495 .ctrlbit = (1 << 16),
533 }, { 496 }, {
534 .name = "spi", 497 .name = "spi",
535 .id = 1, 498 .devname = "s3c64xx-spi.1",
536 .enable = exynos4_clk_ip_peril_ctrl, 499 .enable = exynos4_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 17), 500 .ctrlbit = (1 << 17),
538 }, { 501 }, {
539 .name = "spi", 502 .name = "spi",
540 .id = 2, 503 .devname = "s3c64xx-spi.2",
541 .enable = exynos4_clk_ip_peril_ctrl, 504 .enable = exynos4_clk_ip_peril_ctrl,
542 .ctrlbit = (1 << 18), 505 .ctrlbit = (1 << 18),
543 }, { 506 }, {
544 .name = "iis", 507 .name = "iis",
545 .id = 0, 508 .devname = "samsung-i2s.0",
546 .enable = exynos4_clk_ip_peril_ctrl, 509 .enable = exynos4_clk_ip_peril_ctrl,
547 .ctrlbit = (1 << 19), 510 .ctrlbit = (1 << 19),
548 }, { 511 }, {
549 .name = "iis", 512 .name = "iis",
550 .id = 1, 513 .devname = "samsung-i2s.1",
551 .enable = exynos4_clk_ip_peril_ctrl, 514 .enable = exynos4_clk_ip_peril_ctrl,
552 .ctrlbit = (1 << 20), 515 .ctrlbit = (1 << 20),
553 }, { 516 }, {
554 .name = "iis", 517 .name = "iis",
555 .id = 2, 518 .devname = "samsung-i2s.2",
556 .enable = exynos4_clk_ip_peril_ctrl, 519 .enable = exynos4_clk_ip_peril_ctrl,
557 .ctrlbit = (1 << 21), 520 .ctrlbit = (1 << 21),
558 }, { 521 }, {
@@ -562,125 +525,115 @@ static struct clk init_clocks_off[] = {
562 .ctrlbit = (1 << 27), 525 .ctrlbit = (1 << 27),
563 }, { 526 }, {
564 .name = "fimg2d", 527 .name = "fimg2d",
565 .id = -1,
566 .enable = exynos4_clk_ip_image_ctrl, 528 .enable = exynos4_clk_ip_image_ctrl,
567 .ctrlbit = (1 << 0), 529 .ctrlbit = (1 << 0),
568 }, { 530 }, {
531 .name = "mfc",
532 .devname = "s5p-mfc",
533 .enable = exynos4_clk_ip_mfc_ctrl,
534 .ctrlbit = (1 << 0),
535 }, {
569 .name = "i2c", 536 .name = "i2c",
570 .id = 0, 537 .devname = "s3c2440-i2c.0",
571 .parent = &clk_aclk_100.clk, 538 .parent = &clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_peril_ctrl, 539 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 6), 540 .ctrlbit = (1 << 6),
574 }, { 541 }, {
575 .name = "i2c", 542 .name = "i2c",
576 .id = 1, 543 .devname = "s3c2440-i2c.1",
577 .parent = &clk_aclk_100.clk, 544 .parent = &clk_aclk_100.clk,
578 .enable = exynos4_clk_ip_peril_ctrl, 545 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 7), 546 .ctrlbit = (1 << 7),
580 }, { 547 }, {
581 .name = "i2c", 548 .name = "i2c",
582 .id = 2, 549 .devname = "s3c2440-i2c.2",
583 .parent = &clk_aclk_100.clk, 550 .parent = &clk_aclk_100.clk,
584 .enable = exynos4_clk_ip_peril_ctrl, 551 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 8), 552 .ctrlbit = (1 << 8),
586 }, { 553 }, {
587 .name = "i2c", 554 .name = "i2c",
588 .id = 3, 555 .devname = "s3c2440-i2c.3",
589 .parent = &clk_aclk_100.clk, 556 .parent = &clk_aclk_100.clk,
590 .enable = exynos4_clk_ip_peril_ctrl, 557 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 9), 558 .ctrlbit = (1 << 9),
592 }, { 559 }, {
593 .name = "i2c", 560 .name = "i2c",
594 .id = 4, 561 .devname = "s3c2440-i2c.4",
595 .parent = &clk_aclk_100.clk, 562 .parent = &clk_aclk_100.clk,
596 .enable = exynos4_clk_ip_peril_ctrl, 563 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 10), 564 .ctrlbit = (1 << 10),
598 }, { 565 }, {
599 .name = "i2c", 566 .name = "i2c",
600 .id = 5, 567 .devname = "s3c2440-i2c.5",
601 .parent = &clk_aclk_100.clk, 568 .parent = &clk_aclk_100.clk,
602 .enable = exynos4_clk_ip_peril_ctrl, 569 .enable = exynos4_clk_ip_peril_ctrl,
603 .ctrlbit = (1 << 11), 570 .ctrlbit = (1 << 11),
604 }, { 571 }, {
605 .name = "i2c", 572 .name = "i2c",
606 .id = 6, 573 .devname = "s3c2440-i2c.6",
607 .parent = &clk_aclk_100.clk, 574 .parent = &clk_aclk_100.clk,
608 .enable = exynos4_clk_ip_peril_ctrl, 575 .enable = exynos4_clk_ip_peril_ctrl,
609 .ctrlbit = (1 << 12), 576 .ctrlbit = (1 << 12),
610 }, { 577 }, {
611 .name = "i2c", 578 .name = "i2c",
612 .id = 7, 579 .devname = "s3c2440-i2c.7",
613 .parent = &clk_aclk_100.clk, 580 .parent = &clk_aclk_100.clk,
614 .enable = exynos4_clk_ip_peril_ctrl, 581 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 13), 582 .ctrlbit = (1 << 13),
616 }, { 583 }, {
617 .name = "SYSMMU_MDMA", 584 .name = "SYSMMU_MDMA",
618 .id = -1,
619 .enable = exynos4_clk_ip_image_ctrl, 585 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 5), 586 .ctrlbit = (1 << 5),
621 }, { 587 }, {
622 .name = "SYSMMU_FIMC0", 588 .name = "SYSMMU_FIMC0",
623 .id = -1,
624 .enable = exynos4_clk_ip_cam_ctrl, 589 .enable = exynos4_clk_ip_cam_ctrl,
625 .ctrlbit = (1 << 7), 590 .ctrlbit = (1 << 7),
626 }, { 591 }, {
627 .name = "SYSMMU_FIMC1", 592 .name = "SYSMMU_FIMC1",
628 .id = -1,
629 .enable = exynos4_clk_ip_cam_ctrl, 593 .enable = exynos4_clk_ip_cam_ctrl,
630 .ctrlbit = (1 << 8), 594 .ctrlbit = (1 << 8),
631 }, { 595 }, {
632 .name = "SYSMMU_FIMC2", 596 .name = "SYSMMU_FIMC2",
633 .id = -1,
634 .enable = exynos4_clk_ip_cam_ctrl, 597 .enable = exynos4_clk_ip_cam_ctrl,
635 .ctrlbit = (1 << 9), 598 .ctrlbit = (1 << 9),
636 }, { 599 }, {
637 .name = "SYSMMU_FIMC3", 600 .name = "SYSMMU_FIMC3",
638 .id = -1,
639 .enable = exynos4_clk_ip_cam_ctrl, 601 .enable = exynos4_clk_ip_cam_ctrl,
640 .ctrlbit = (1 << 10), 602 .ctrlbit = (1 << 10),
641 }, { 603 }, {
642 .name = "SYSMMU_JPEG", 604 .name = "SYSMMU_JPEG",
643 .id = -1,
644 .enable = exynos4_clk_ip_cam_ctrl, 605 .enable = exynos4_clk_ip_cam_ctrl,
645 .ctrlbit = (1 << 11), 606 .ctrlbit = (1 << 11),
646 }, { 607 }, {
647 .name = "SYSMMU_FIMD0", 608 .name = "SYSMMU_FIMD0",
648 .id = -1,
649 .enable = exynos4_clk_ip_lcd0_ctrl, 609 .enable = exynos4_clk_ip_lcd0_ctrl,
650 .ctrlbit = (1 << 4), 610 .ctrlbit = (1 << 4),
651 }, { 611 }, {
652 .name = "SYSMMU_FIMD1", 612 .name = "SYSMMU_FIMD1",
653 .id = -1,
654 .enable = exynos4_clk_ip_lcd1_ctrl, 613 .enable = exynos4_clk_ip_lcd1_ctrl,
655 .ctrlbit = (1 << 4), 614 .ctrlbit = (1 << 4),
656 }, { 615 }, {
657 .name = "SYSMMU_PCIe", 616 .name = "SYSMMU_PCIe",
658 .id = -1,
659 .enable = exynos4_clk_ip_fsys_ctrl, 617 .enable = exynos4_clk_ip_fsys_ctrl,
660 .ctrlbit = (1 << 18), 618 .ctrlbit = (1 << 18),
661 }, { 619 }, {
662 .name = "SYSMMU_G2D", 620 .name = "SYSMMU_G2D",
663 .id = -1,
664 .enable = exynos4_clk_ip_image_ctrl, 621 .enable = exynos4_clk_ip_image_ctrl,
665 .ctrlbit = (1 << 3), 622 .ctrlbit = (1 << 3),
666 }, { 623 }, {
667 .name = "SYSMMU_ROTATOR", 624 .name = "SYSMMU_ROTATOR",
668 .id = -1,
669 .enable = exynos4_clk_ip_image_ctrl, 625 .enable = exynos4_clk_ip_image_ctrl,
670 .ctrlbit = (1 << 4), 626 .ctrlbit = (1 << 4),
671 }, { 627 }, {
672 .name = "SYSMMU_TV", 628 .name = "SYSMMU_TV",
673 .id = -1,
674 .enable = exynos4_clk_ip_tv_ctrl, 629 .enable = exynos4_clk_ip_tv_ctrl,
675 .ctrlbit = (1 << 4), 630 .ctrlbit = (1 << 4),
676 }, { 631 }, {
677 .name = "SYSMMU_MFC_L", 632 .name = "SYSMMU_MFC_L",
678 .id = -1,
679 .enable = exynos4_clk_ip_mfc_ctrl, 633 .enable = exynos4_clk_ip_mfc_ctrl,
680 .ctrlbit = (1 << 1), 634 .ctrlbit = (1 << 1),
681 }, { 635 }, {
682 .name = "SYSMMU_MFC_R", 636 .name = "SYSMMU_MFC_R",
683 .id = -1,
684 .enable = exynos4_clk_ip_mfc_ctrl, 637 .enable = exynos4_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 2), 638 .ctrlbit = (1 << 2),
686 } 639 }
@@ -689,32 +642,32 @@ static struct clk init_clocks_off[] = {
689static struct clk init_clocks[] = { 642static struct clk init_clocks[] = {
690 { 643 {
691 .name = "uart", 644 .name = "uart",
692 .id = 0, 645 .devname = "s5pv210-uart.0",
693 .enable = exynos4_clk_ip_peril_ctrl, 646 .enable = exynos4_clk_ip_peril_ctrl,
694 .ctrlbit = (1 << 0), 647 .ctrlbit = (1 << 0),
695 }, { 648 }, {
696 .name = "uart", 649 .name = "uart",
697 .id = 1, 650 .devname = "s5pv210-uart.1",
698 .enable = exynos4_clk_ip_peril_ctrl, 651 .enable = exynos4_clk_ip_peril_ctrl,
699 .ctrlbit = (1 << 1), 652 .ctrlbit = (1 << 1),
700 }, { 653 }, {
701 .name = "uart", 654 .name = "uart",
702 .id = 2, 655 .devname = "s5pv210-uart.2",
703 .enable = exynos4_clk_ip_peril_ctrl, 656 .enable = exynos4_clk_ip_peril_ctrl,
704 .ctrlbit = (1 << 2), 657 .ctrlbit = (1 << 2),
705 }, { 658 }, {
706 .name = "uart", 659 .name = "uart",
707 .id = 3, 660 .devname = "s5pv210-uart.3",
708 .enable = exynos4_clk_ip_peril_ctrl, 661 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 3), 662 .ctrlbit = (1 << 3),
710 }, { 663 }, {
711 .name = "uart", 664 .name = "uart",
712 .id = 4, 665 .devname = "s5pv210-uart.4",
713 .enable = exynos4_clk_ip_peril_ctrl, 666 .enable = exynos4_clk_ip_peril_ctrl,
714 .ctrlbit = (1 << 4), 667 .ctrlbit = (1 << 4),
715 }, { 668 }, {
716 .name = "uart", 669 .name = "uart",
717 .id = 5, 670 .devname = "s5pv210-uart.5",
718 .enable = exynos4_clk_ip_peril_ctrl, 671 .enable = exynos4_clk_ip_peril_ctrl,
719 .ctrlbit = (1 << 5), 672 .ctrlbit = (1 << 5),
720 } 673 }
@@ -750,7 +703,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
750static struct clksrc_clk clk_mout_g2d0 = { 703static struct clksrc_clk clk_mout_g2d0 = {
751 .clk = { 704 .clk = {
752 .name = "mout_g2d0", 705 .name = "mout_g2d0",
753 .id = -1,
754 }, 706 },
755 .sources = &clkset_mout_g2d0, 707 .sources = &clkset_mout_g2d0,
756 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, 708 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +721,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
769static struct clksrc_clk clk_mout_g2d1 = { 721static struct clksrc_clk clk_mout_g2d1 = {
770 .clk = { 722 .clk = {
771 .name = "mout_g2d1", 723 .name = "mout_g2d1",
772 .id = -1,
773 }, 724 },
774 .sources = &clkset_mout_g2d1, 725 .sources = &clkset_mout_g2d1,
775 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, 726 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -785,10 +736,55 @@ static struct clksrc_sources clkset_mout_g2d = {
785 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), 736 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
786}; 737};
787 738
739static struct clk *clkset_mout_mfc0_list[] = {
740 [0] = &clk_mout_mpll.clk,
741 [1] = &clk_sclk_apll.clk,
742};
743
744static struct clksrc_sources clkset_mout_mfc0 = {
745 .sources = clkset_mout_mfc0_list,
746 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
747};
748
749static struct clksrc_clk clk_mout_mfc0 = {
750 .clk = {
751 .name = "mout_mfc0",
752 },
753 .sources = &clkset_mout_mfc0,
754 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
755};
756
757static struct clk *clkset_mout_mfc1_list[] = {
758 [0] = &clk_mout_epll.clk,
759 [1] = &clk_sclk_vpll.clk,
760};
761
762static struct clksrc_sources clkset_mout_mfc1 = {
763 .sources = clkset_mout_mfc1_list,
764 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
765};
766
767static struct clksrc_clk clk_mout_mfc1 = {
768 .clk = {
769 .name = "mout_mfc1",
770 },
771 .sources = &clkset_mout_mfc1,
772 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
773};
774
775static struct clk *clkset_mout_mfc_list[] = {
776 [0] = &clk_mout_mfc0.clk,
777 [1] = &clk_mout_mfc1.clk,
778};
779
780static struct clksrc_sources clkset_mout_mfc = {
781 .sources = clkset_mout_mfc_list,
782 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
783};
784
788static struct clksrc_clk clk_dout_mmc0 = { 785static struct clksrc_clk clk_dout_mmc0 = {
789 .clk = { 786 .clk = {
790 .name = "dout_mmc0", 787 .name = "dout_mmc0",
791 .id = -1,
792 }, 788 },
793 .sources = &clkset_group, 789 .sources = &clkset_group,
794 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, 790 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +794,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
798static struct clksrc_clk clk_dout_mmc1 = { 794static struct clksrc_clk clk_dout_mmc1 = {
799 .clk = { 795 .clk = {
800 .name = "dout_mmc1", 796 .name = "dout_mmc1",
801 .id = -1,
802 }, 797 },
803 .sources = &clkset_group, 798 .sources = &clkset_group,
804 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, 799 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +803,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
808static struct clksrc_clk clk_dout_mmc2 = { 803static struct clksrc_clk clk_dout_mmc2 = {
809 .clk = { 804 .clk = {
810 .name = "dout_mmc2", 805 .name = "dout_mmc2",
811 .id = -1,
812 }, 806 },
813 .sources = &clkset_group, 807 .sources = &clkset_group,
814 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, 808 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +812,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
818static struct clksrc_clk clk_dout_mmc3 = { 812static struct clksrc_clk clk_dout_mmc3 = {
819 .clk = { 813 .clk = {
820 .name = "dout_mmc3", 814 .name = "dout_mmc3",
821 .id = -1,
822 }, 815 },
823 .sources = &clkset_group, 816 .sources = &clkset_group,
824 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, 817 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +821,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
828static struct clksrc_clk clk_dout_mmc4 = { 821static struct clksrc_clk clk_dout_mmc4 = {
829 .clk = { 822 .clk = {
830 .name = "dout_mmc4", 823 .name = "dout_mmc4",
831 .id = -1,
832 }, 824 },
833 .sources = &clkset_group, 825 .sources = &clkset_group,
834 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, 826 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +831,7 @@ static struct clksrc_clk clksrcs[] = {
839 { 831 {
840 .clk = { 832 .clk = {
841 .name = "uclk1", 833 .name = "uclk1",
842 .id = 0, 834 .devname = "s5pv210-uart.0",
843 .enable = exynos4_clksrc_mask_peril0_ctrl, 835 .enable = exynos4_clksrc_mask_peril0_ctrl,
844 .ctrlbit = (1 << 0), 836 .ctrlbit = (1 << 0),
845 }, 837 },
@@ -849,7 +841,7 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 841 }, {
850 .clk = { 842 .clk = {
851 .name = "uclk1", 843 .name = "uclk1",
852 .id = 1, 844 .devname = "s5pv210-uart.1",
853 .enable = exynos4_clksrc_mask_peril0_ctrl, 845 .enable = exynos4_clksrc_mask_peril0_ctrl,
854 .ctrlbit = (1 << 4), 846 .ctrlbit = (1 << 4),
855 }, 847 },
@@ -859,7 +851,7 @@ static struct clksrc_clk clksrcs[] = {
859 }, { 851 }, {
860 .clk = { 852 .clk = {
861 .name = "uclk1", 853 .name = "uclk1",
862 .id = 2, 854 .devname = "s5pv210-uart.2",
863 .enable = exynos4_clksrc_mask_peril0_ctrl, 855 .enable = exynos4_clksrc_mask_peril0_ctrl,
864 .ctrlbit = (1 << 8), 856 .ctrlbit = (1 << 8),
865 }, 857 },
@@ -869,7 +861,7 @@ static struct clksrc_clk clksrcs[] = {
869 }, { 861 }, {
870 .clk = { 862 .clk = {
871 .name = "uclk1", 863 .name = "uclk1",
872 .id = 3, 864 .devname = "s5pv210-uart.3",
873 .enable = exynos4_clksrc_mask_peril0_ctrl, 865 .enable = exynos4_clksrc_mask_peril0_ctrl,
874 .ctrlbit = (1 << 12), 866 .ctrlbit = (1 << 12),
875 }, 867 },
@@ -879,7 +871,6 @@ static struct clksrc_clk clksrcs[] = {
879 }, { 871 }, {
880 .clk = { 872 .clk = {
881 .name = "sclk_pwm", 873 .name = "sclk_pwm",
882 .id = -1,
883 .enable = exynos4_clksrc_mask_peril0_ctrl, 874 .enable = exynos4_clksrc_mask_peril0_ctrl,
884 .ctrlbit = (1 << 24), 875 .ctrlbit = (1 << 24),
885 }, 876 },
@@ -889,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
889 }, { 880 }, {
890 .clk = { 881 .clk = {
891 .name = "sclk_csis", 882 .name = "sclk_csis",
892 .id = 0, 883 .devname = "s5p-mipi-csis.0",
893 .enable = exynos4_clksrc_mask_cam_ctrl, 884 .enable = exynos4_clksrc_mask_cam_ctrl,
894 .ctrlbit = (1 << 24), 885 .ctrlbit = (1 << 24),
895 }, 886 },
@@ -899,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
899 }, { 890 }, {
900 .clk = { 891 .clk = {
901 .name = "sclk_csis", 892 .name = "sclk_csis",
902 .id = 1, 893 .devname = "s5p-mipi-csis.1",
903 .enable = exynos4_clksrc_mask_cam_ctrl, 894 .enable = exynos4_clksrc_mask_cam_ctrl,
904 .ctrlbit = (1 << 28), 895 .ctrlbit = (1 << 28),
905 }, 896 },
@@ -909,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
909 }, { 900 }, {
910 .clk = { 901 .clk = {
911 .name = "sclk_cam", 902 .name = "sclk_cam",
912 .id = 0, 903 .devname = "exynos4-fimc.0",
913 .enable = exynos4_clksrc_mask_cam_ctrl, 904 .enable = exynos4_clksrc_mask_cam_ctrl,
914 .ctrlbit = (1 << 16), 905 .ctrlbit = (1 << 16),
915 }, 906 },
@@ -919,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
919 }, { 910 }, {
920 .clk = { 911 .clk = {
921 .name = "sclk_cam", 912 .name = "sclk_cam",
922 .id = 1, 913 .devname = "exynos4-fimc.1",
923 .enable = exynos4_clksrc_mask_cam_ctrl, 914 .enable = exynos4_clksrc_mask_cam_ctrl,
924 .ctrlbit = (1 << 20), 915 .ctrlbit = (1 << 20),
925 }, 916 },
@@ -929,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
929 }, { 920 }, {
930 .clk = { 921 .clk = {
931 .name = "sclk_fimc", 922 .name = "sclk_fimc",
932 .id = 0, 923 .devname = "exynos4-fimc.0",
933 .enable = exynos4_clksrc_mask_cam_ctrl, 924 .enable = exynos4_clksrc_mask_cam_ctrl,
934 .ctrlbit = (1 << 0), 925 .ctrlbit = (1 << 0),
935 }, 926 },
@@ -939,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
939 }, { 930 }, {
940 .clk = { 931 .clk = {
941 .name = "sclk_fimc", 932 .name = "sclk_fimc",
942 .id = 1, 933 .devname = "exynos4-fimc.1",
943 .enable = exynos4_clksrc_mask_cam_ctrl, 934 .enable = exynos4_clksrc_mask_cam_ctrl,
944 .ctrlbit = (1 << 4), 935 .ctrlbit = (1 << 4),
945 }, 936 },
@@ -949,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
949 }, { 940 }, {
950 .clk = { 941 .clk = {
951 .name = "sclk_fimc", 942 .name = "sclk_fimc",
952 .id = 2, 943 .devname = "exynos4-fimc.2",
953 .enable = exynos4_clksrc_mask_cam_ctrl, 944 .enable = exynos4_clksrc_mask_cam_ctrl,
954 .ctrlbit = (1 << 8), 945 .ctrlbit = (1 << 8),
955 }, 946 },
@@ -959,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
959 }, { 950 }, {
960 .clk = { 951 .clk = {
961 .name = "sclk_fimc", 952 .name = "sclk_fimc",
962 .id = 3, 953 .devname = "exynos4-fimc.3",
963 .enable = exynos4_clksrc_mask_cam_ctrl, 954 .enable = exynos4_clksrc_mask_cam_ctrl,
964 .ctrlbit = (1 << 12), 955 .ctrlbit = (1 << 12),
965 }, 956 },
@@ -969,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
969 }, { 960 }, {
970 .clk = { 961 .clk = {
971 .name = "sclk_fimd", 962 .name = "sclk_fimd",
972 .id = 0, 963 .devname = "exynos4-fb.0",
973 .enable = exynos4_clksrc_mask_lcd0_ctrl, 964 .enable = exynos4_clksrc_mask_lcd0_ctrl,
974 .ctrlbit = (1 << 0), 965 .ctrlbit = (1 << 0),
975 }, 966 },
@@ -979,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
979 }, { 970 }, {
980 .clk = { 971 .clk = {
981 .name = "sclk_fimd", 972 .name = "sclk_fimd",
982 .id = 1, 973 .devname = "exynos4-fb.1",
983 .enable = exynos4_clksrc_mask_lcd1_ctrl, 974 .enable = exynos4_clksrc_mask_lcd1_ctrl,
984 .ctrlbit = (1 << 0), 975 .ctrlbit = (1 << 0),
985 }, 976 },
@@ -989,7 +980,6 @@ static struct clksrc_clk clksrcs[] = {
989 }, { 980 }, {
990 .clk = { 981 .clk = {
991 .name = "sclk_sata", 982 .name = "sclk_sata",
992 .id = -1,
993 .enable = exynos4_clksrc_mask_fsys_ctrl, 983 .enable = exynos4_clksrc_mask_fsys_ctrl,
994 .ctrlbit = (1 << 24), 984 .ctrlbit = (1 << 24),
995 }, 985 },
@@ -999,7 +989,7 @@ static struct clksrc_clk clksrcs[] = {
999 }, { 989 }, {
1000 .clk = { 990 .clk = {
1001 .name = "sclk_spi", 991 .name = "sclk_spi",
1002 .id = 0, 992 .devname = "s3c64xx-spi.0",
1003 .enable = exynos4_clksrc_mask_peril1_ctrl, 993 .enable = exynos4_clksrc_mask_peril1_ctrl,
1004 .ctrlbit = (1 << 16), 994 .ctrlbit = (1 << 16),
1005 }, 995 },
@@ -1009,7 +999,7 @@ static struct clksrc_clk clksrcs[] = {
1009 }, { 999 }, {
1010 .clk = { 1000 .clk = {
1011 .name = "sclk_spi", 1001 .name = "sclk_spi",
1012 .id = 1, 1002 .devname = "s3c64xx-spi.1",
1013 .enable = exynos4_clksrc_mask_peril1_ctrl, 1003 .enable = exynos4_clksrc_mask_peril1_ctrl,
1014 .ctrlbit = (1 << 20), 1004 .ctrlbit = (1 << 20),
1015 }, 1005 },
@@ -1019,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
1019 }, { 1009 }, {
1020 .clk = { 1010 .clk = {
1021 .name = "sclk_spi", 1011 .name = "sclk_spi",
1022 .id = 2, 1012 .devname = "s3c64xx-spi.2",
1023 .enable = exynos4_clksrc_mask_peril1_ctrl, 1013 .enable = exynos4_clksrc_mask_peril1_ctrl,
1024 .ctrlbit = (1 << 24), 1014 .ctrlbit = (1 << 24),
1025 }, 1015 },
@@ -1029,15 +1019,22 @@ static struct clksrc_clk clksrcs[] = {
1029 }, { 1019 }, {
1030 .clk = { 1020 .clk = {
1031 .name = "sclk_fimg2d", 1021 .name = "sclk_fimg2d",
1032 .id = -1,
1033 }, 1022 },
1034 .sources = &clkset_mout_g2d, 1023 .sources = &clkset_mout_g2d,
1035 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, 1024 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1036 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, 1025 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1037 }, { 1026 }, {
1038 .clk = { 1027 .clk = {
1028 .name = "sclk_mfc",
1029 .devname = "s5p-mfc",
1030 },
1031 .sources = &clkset_mout_mfc,
1032 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1033 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1034 }, {
1035 .clk = {
1039 .name = "sclk_mmc", 1036 .name = "sclk_mmc",
1040 .id = 0, 1037 .devname = "s3c-sdhci.0",
1041 .parent = &clk_dout_mmc0.clk, 1038 .parent = &clk_dout_mmc0.clk,
1042 .enable = exynos4_clksrc_mask_fsys_ctrl, 1039 .enable = exynos4_clksrc_mask_fsys_ctrl,
1043 .ctrlbit = (1 << 0), 1040 .ctrlbit = (1 << 0),
@@ -1046,7 +1043,7 @@ static struct clksrc_clk clksrcs[] = {
1046 }, { 1043 }, {
1047 .clk = { 1044 .clk = {
1048 .name = "sclk_mmc", 1045 .name = "sclk_mmc",
1049 .id = 1, 1046 .devname = "s3c-sdhci.1",
1050 .parent = &clk_dout_mmc1.clk, 1047 .parent = &clk_dout_mmc1.clk,
1051 .enable = exynos4_clksrc_mask_fsys_ctrl, 1048 .enable = exynos4_clksrc_mask_fsys_ctrl,
1052 .ctrlbit = (1 << 4), 1049 .ctrlbit = (1 << 4),
@@ -1055,7 +1052,7 @@ static struct clksrc_clk clksrcs[] = {
1055 }, { 1052 }, {
1056 .clk = { 1053 .clk = {
1057 .name = "sclk_mmc", 1054 .name = "sclk_mmc",
1058 .id = 2, 1055 .devname = "s3c-sdhci.2",
1059 .parent = &clk_dout_mmc2.clk, 1056 .parent = &clk_dout_mmc2.clk,
1060 .enable = exynos4_clksrc_mask_fsys_ctrl, 1057 .enable = exynos4_clksrc_mask_fsys_ctrl,
1061 .ctrlbit = (1 << 8), 1058 .ctrlbit = (1 << 8),
@@ -1064,7 +1061,7 @@ static struct clksrc_clk clksrcs[] = {
1064 }, { 1061 }, {
1065 .clk = { 1062 .clk = {
1066 .name = "sclk_mmc", 1063 .name = "sclk_mmc",
1067 .id = 3, 1064 .devname = "s3c-sdhci.3",
1068 .parent = &clk_dout_mmc3.clk, 1065 .parent = &clk_dout_mmc3.clk,
1069 .enable = exynos4_clksrc_mask_fsys_ctrl, 1066 .enable = exynos4_clksrc_mask_fsys_ctrl,
1070 .ctrlbit = (1 << 12), 1067 .ctrlbit = (1 << 12),
@@ -1072,8 +1069,7 @@ static struct clksrc_clk clksrcs[] = {
1072 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1069 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1073 }, { 1070 }, {
1074 .clk = { 1071 .clk = {
1075 .name = "sclk_mmc", 1072 .name = "sclk_dwmmc",
1076 .id = 4,
1077 .parent = &clk_dout_mmc4.clk, 1073 .parent = &clk_dout_mmc4.clk,
1078 .enable = exynos4_clksrc_mask_fsys_ctrl, 1074 .enable = exynos4_clksrc_mask_fsys_ctrl,
1079 .ctrlbit = (1 << 16), 1075 .ctrlbit = (1 << 16),
@@ -1112,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = {
1112 &clk_dout_mmc2, 1108 &clk_dout_mmc2,
1113 &clk_dout_mmc3, 1109 &clk_dout_mmc3,
1114 &clk_dout_mmc4, 1110 &clk_dout_mmc4,
1111 &clk_mout_mfc0,
1112 &clk_mout_mfc1,
1115}; 1113};
1116 1114
1117static int xtal_rate; 1115static int xtal_rate;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index bfd621460abf..2d8a40c9e6e5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -16,12 +16,16 @@
16 16
17#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h> 18#include <asm/hardware/cache-l2x0.h>
19#include <asm/hardware/gic.h>
19 20
20#include <plat/cpu.h> 21#include <plat/cpu.h>
21#include <plat/clock.h> 22#include <plat/clock.h>
23#include <plat/devs.h>
22#include <plat/exynos4.h> 24#include <plat/exynos4.h>
25#include <plat/adc-core.h>
23#include <plat/sdhci.h> 26#include <plat/sdhci.h>
24#include <plat/devs.h> 27#include <plat/devs.h>
28#include <plat/fb-core.h>
25#include <plat/fimc-core.h> 29#include <plat/fimc-core.h>
26#include <plat/iic-core.h> 30#include <plat/iic-core.h>
27 31
@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
103 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), 107 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
104 .length = SZ_4K, 108 .length = SZ_4K,
105 .type = MT_DEVICE, 109 .type = MT_DEVICE,
106 } 110 }, {
111 .virtual = (unsigned long)S5P_VA_GIC_CPU,
112 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
113 .length = SZ_64K,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (unsigned long)S5P_VA_GIC_DIST,
117 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
118 .length = SZ_64K,
119 .type = MT_DEVICE,
120 },
107}; 121};
108 122
109static void exynos4_idle(void) 123static void exynos4_idle(void)
@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
129 exynos4_default_sdhci2(); 143 exynos4_default_sdhci2();
130 exynos4_default_sdhci3(); 144 exynos4_default_sdhci3();
131 145
146 s3c_adc_setname("samsung-adc-v3");
147
132 s3c_fimc_setname(0, "exynos4-fimc"); 148 s3c_fimc_setname(0, "exynos4-fimc");
133 s3c_fimc_setname(1, "exynos4-fimc"); 149 s3c_fimc_setname(1, "exynos4-fimc");
134 s3c_fimc_setname(2, "exynos4-fimc"); 150 s3c_fimc_setname(2, "exynos4-fimc");
@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
138 s3c_i2c0_setname("s3c2440-i2c"); 154 s3c_i2c0_setname("s3c2440-i2c");
139 s3c_i2c1_setname("s3c2440-i2c"); 155 s3c_i2c1_setname("s3c2440-i2c");
140 s3c_i2c2_setname("s3c2440-i2c"); 156 s3c_i2c2_setname("s3c2440-i2c");
157
158 s5p_fb_setname(0, "exynos4-fb");
141} 159}
142 160
143void __init exynos4_init_clocks(int xtal) 161void __init exynos4_init_clocks(int xtal)
@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
150 exynos4_setup_clocks(); 168 exynos4_setup_clocks();
151} 169}
152 170
171static void exynos4_gic_irq_eoi(struct irq_data *d)
172{
173 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
174
175 gic_data->cpu_base = S5P_VA_GIC_CPU +
176 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
177}
178
153void __init exynos4_init_irq(void) 179void __init exynos4_init_irq(void)
154{ 180{
155 int irq; 181 int irq;
156 182
157 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 183 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
184 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
158 185
159 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 186 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
160 187
161 /*
162 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
163 * connected to the interrupt combiner. These irqs
164 * should be initialized to support cascade interrupt.
165 */
166 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
167 continue;
168
169 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 188 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
170 COMBINER_IRQ(irq, 0)); 189 COMBINER_IRQ(irq, 0));
171 combiner_cascade_irq(irq, IRQ_SPI(irq)); 190 combiner_cascade_irq(irq, IRQ_SPI(irq));
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 983069a53239..5a9f9c2e53bf 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -21,6 +21,7 @@
21#include <mach/map.h> 21#include <mach/map.h>
22#include <mach/dma.h> 22#include <mach/dma.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/regs-audss.h>
24 25
25static const char *rclksrc[] = { 26static const char *rclksrc[] = {
26 [0] = "busclk", 27 [0] = "busclk",
@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
55 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI 56 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
56 | QUIRK_NEED_RSTCLR, 57 | QUIRK_NEED_RSTCLR,
57 .src_clk = rclksrc, 58 .src_clk = rclksrc,
59 .idma_addr = EXYNOS4_AUDSS_INT_MEM,
58 }, 60 },
59 }, 61 },
60}; 62};
diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos4/dev-dwmci.c
new file mode 100644
index 000000000000..b025db4bf602
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-dwmci.c
@@ -0,0 +1,82 @@
1/*
2 * linux/arch/arm/mach-exynos4/dev-dwmci.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Platform device for Synopsys DesignWare Mobile Storage IP
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18#include <linux/interrupt.h>
19#include <linux/mmc/dw_mmc.h>
20
21#include <plat/devs.h>
22
23#include <mach/map.h>
24
25static int exynos4_dwmci_get_bus_wd(u32 slot_id)
26{
27 return 4;
28}
29
30static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
31{
32 return 0;
33}
34
35static struct resource exynos4_dwmci_resource[] = {
36 [0] = {
37 .start = EXYNOS4_PA_DWMCI,
38 .end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 [1] = {
42 .start = IRQ_DWMCI,
43 .end = IRQ_DWMCI,
44 .flags = IORESOURCE_IRQ,
45 }
46};
47
48static struct dw_mci_board exynos4_dwci_pdata = {
49 .num_slots = 1,
50 .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
51 .bus_hz = 80 * 1000 * 1000,
52 .detect_delay_ms = 200,
53 .init = exynos4_dwmci_init,
54 .get_bus_wd = exynos4_dwmci_get_bus_wd,
55};
56
57static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
58
59struct platform_device exynos4_device_dwmci = {
60 .name = "dw_mmc",
61 .id = -1,
62 .num_resources = ARRAY_SIZE(exynos4_dwmci_resource),
63 .resource = exynos4_dwmci_resource,
64 .dev = {
65 .dma_mask = &exynos4_dwmci_dmamask,
66 .coherent_dma_mask = DMA_BIT_MASK(32),
67 .platform_data = &exynos4_dwci_pdata,
68 },
69};
70
71void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
72{
73 struct dw_mci_board *npd;
74
75 npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
76 &exynos4_device_dwmci);
77
78 if (!npd->init)
79 npd->init = exynos4_dwmci_init;
80 if (!npd->get_bus_wd)
81 npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
82}
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index 2b5909e2ccd3..7490789784c9 100644
--- a/arch/arm/mach-exynos4/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -13,9 +13,12 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/smp.h> 15#include <linux/smp.h>
16#include <linux/io.h>
16 17
17#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
18 19
20#include <mach/regs-pmu.h>
21
19extern volatile int pen_release; 22extern volatile int pen_release;
20 23
21static inline void cpu_enter_lowpower(void) 24static inline void cpu_enter_lowpower(void)
@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
58 61
59static inline void platform_do_lowpower(unsigned int cpu, int *spurious) 62static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
60{ 63{
61 /*
62 * there is no power-control hardware on this platform, so all
63 * we can do is put the core into WFI; this is safe as the calling
64 * code will have already disabled interrupts
65 */
66 for (;;) { 64 for (;;) {
65
66 /* make cpu1 to be turned off at next WFI command */
67 if (cpu == 1)
68 __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
69
67 /* 70 /*
68 * here's the WFI 71 * here's the WFI
69 */ 72 */
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h
new file mode 100644
index 000000000000..7ce657459cc0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/dwmci.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Synopsys DesignWare Mobile Storage for EXYNOS4210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARM_ARCH_DWMCI_H
14#define __ASM_ARM_ARCH_DWMCI_H __FILE__
15
16#include <linux/mmc/dw_mmc.h>
17
18extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
19
20#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2e5654..d7a1e281ce7a 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -10,6 +10,7 @@
10*/ 10*/
11 11
12#include <mach/hardware.h> 12#include <mach/hardware.h>
13#include <mach/map.h>
13#include <asm/hardware/gic.h> 14#include <asm/hardware/gic.h>
14 15
15 .macro disable_fiq 16 .macro disable_fiq
@@ -18,6 +19,10 @@
18 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
19 ldr \base, =gic_cpu_base_addr 20 ldr \base, =gic_cpu_base_addr
20 ldr \base, [\base] 21 ldr \base, [\base]
22 mrc p15, 0, \tmp, c0, c0, 5
23 and \tmp, \tmp, #3
24 cmp \tmp, #1
25 addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
21 .endm 26 .endm
22 27
23 .macro arch_ret_to_user, tmp1, tmp2 28 .macro arch_ret_to_user, tmp1, tmp2
@@ -75,10 +80,4 @@
75 /* As above, this assumes that irqstat and base are preserved.. */ 80 /* As above, this assumes that irqstat and base are preserved.. */
76 81
77 .macro test_for_ltirq, irqnr, irqstat, base, tmp 82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
78 bic \irqnr, \irqstat, #0x1c00
79 mov \tmp, #0
80 cmp \irqnr, #29
81 moveq \tmp, #1
82 streq \irqstat, [\base, #GIC_CPU_EOI]
83 cmp \tmp, #0
84 .endm 83 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d037301d21a..934d2a493982 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,40 +19,105 @@
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
21 21
22#define IRQ_LOCALTIMER IRQ_PPI(13)
23
24/* SPI: Shared Peripheral Interrupt */ 22/* SPI: Shared Peripheral Interrupt */
25 23
26#define IRQ_SPI(x) S5P_IRQ(x+32) 24#define IRQ_SPI(x) S5P_IRQ(x+32)
27 25
28#define IRQ_MCT1 IRQ_SPI(35) 26#define IRQ_EINT0 IRQ_SPI(16)
29 27#define IRQ_EINT1 IRQ_SPI(17)
30#define IRQ_EINT0 IRQ_SPI(40) 28#define IRQ_EINT2 IRQ_SPI(18)
31#define IRQ_EINT1 IRQ_SPI(41) 29#define IRQ_EINT3 IRQ_SPI(19)
32#define IRQ_EINT2 IRQ_SPI(42) 30#define IRQ_EINT4 IRQ_SPI(20)
33#define IRQ_EINT3 IRQ_SPI(43) 31#define IRQ_EINT5 IRQ_SPI(21)
34#define IRQ_USB_HSOTG IRQ_SPI(44) 32#define IRQ_EINT6 IRQ_SPI(22)
35#define IRQ_USB_HOST IRQ_SPI(45) 33#define IRQ_EINT7 IRQ_SPI(23)
36#define IRQ_MODEM_IF IRQ_SPI(46) 34#define IRQ_EINT8 IRQ_SPI(24)
37#define IRQ_ROTATOR IRQ_SPI(47) 35#define IRQ_EINT9 IRQ_SPI(25)
38#define IRQ_JPEG IRQ_SPI(48) 36#define IRQ_EINT10 IRQ_SPI(26)
39#define IRQ_2D IRQ_SPI(49) 37#define IRQ_EINT11 IRQ_SPI(27)
40#define IRQ_PCIE IRQ_SPI(50) 38#define IRQ_EINT12 IRQ_SPI(28)
41#define IRQ_MCT0 IRQ_SPI(51) 39#define IRQ_EINT13 IRQ_SPI(29)
42#define IRQ_MFC IRQ_SPI(52) 40#define IRQ_EINT14 IRQ_SPI(30)
43#define IRQ_AUDIO_SS IRQ_SPI(54) 41#define IRQ_EINT15 IRQ_SPI(31)
44#define IRQ_AC97 IRQ_SPI(55) 42#define IRQ_EINT16_31 IRQ_SPI(32)
45#define IRQ_SPDIF IRQ_SPI(56) 43
46#define IRQ_KEYPAD IRQ_SPI(57) 44#define IRQ_PDMA0 IRQ_SPI(35)
47#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58) 45#define IRQ_PDMA1 IRQ_SPI(36)
48#define IRQ_SLIMBUS IRQ_SPI(59) 46#define IRQ_TIMER0_VIC IRQ_SPI(37)
49#define IRQ_PMU IRQ_SPI(60) 47#define IRQ_TIMER1_VIC IRQ_SPI(38)
50#define IRQ_TSI IRQ_SPI(61) 48#define IRQ_TIMER2_VIC IRQ_SPI(39)
51#define IRQ_SATA IRQ_SPI(62) 49#define IRQ_TIMER3_VIC IRQ_SPI(40)
52#define IRQ_GPS IRQ_SPI(63) 50#define IRQ_TIMER4_VIC IRQ_SPI(41)
51#define IRQ_MCT_L0 IRQ_SPI(42)
52#define IRQ_WDT IRQ_SPI(43)
53#define IRQ_RTC_ALARM IRQ_SPI(44)
54#define IRQ_RTC_TIC IRQ_SPI(45)
55#define IRQ_GPIO_XB IRQ_SPI(46)
56#define IRQ_GPIO_XA IRQ_SPI(47)
57#define IRQ_MCT_L1 IRQ_SPI(48)
58
59#define IRQ_UART0 IRQ_SPI(52)
60#define IRQ_UART1 IRQ_SPI(53)
61#define IRQ_UART2 IRQ_SPI(54)
62#define IRQ_UART3 IRQ_SPI(55)
63#define IRQ_UART4 IRQ_SPI(56)
64#define IRQ_MCT_G0 IRQ_SPI(57)
65#define IRQ_IIC IRQ_SPI(58)
66#define IRQ_IIC1 IRQ_SPI(59)
67#define IRQ_IIC2 IRQ_SPI(60)
68#define IRQ_IIC3 IRQ_SPI(61)
69#define IRQ_IIC4 IRQ_SPI(62)
70#define IRQ_IIC5 IRQ_SPI(63)
71#define IRQ_IIC6 IRQ_SPI(64)
72#define IRQ_IIC7 IRQ_SPI(65)
73
74#define IRQ_USB_HOST IRQ_SPI(70)
75#define IRQ_USB_HSOTG IRQ_SPI(71)
76#define IRQ_MODEM_IF IRQ_SPI(72)
77#define IRQ_HSMMC0 IRQ_SPI(73)
78#define IRQ_HSMMC1 IRQ_SPI(74)
79#define IRQ_HSMMC2 IRQ_SPI(75)
80#define IRQ_HSMMC3 IRQ_SPI(76)
81#define IRQ_DWMCI IRQ_SPI(77)
82
83#define IRQ_MIPICSI0 IRQ_SPI(78)
84
85#define IRQ_MIPICSI1 IRQ_SPI(80)
86
87#define IRQ_ONENAND_AUDI IRQ_SPI(82)
88#define IRQ_ROTATOR IRQ_SPI(83)
89#define IRQ_FIMC0 IRQ_SPI(84)
90#define IRQ_FIMC1 IRQ_SPI(85)
91#define IRQ_FIMC2 IRQ_SPI(86)
92#define IRQ_FIMC3 IRQ_SPI(87)
93#define IRQ_JPEG IRQ_SPI(88)
94#define IRQ_2D IRQ_SPI(89)
95#define IRQ_PCIE IRQ_SPI(90)
96
97#define IRQ_MFC IRQ_SPI(94)
98
99#define IRQ_AUDIO_SS IRQ_SPI(96)
100#define IRQ_I2S0 IRQ_SPI(97)
101#define IRQ_I2S1 IRQ_SPI(98)
102#define IRQ_I2S2 IRQ_SPI(99)
103#define IRQ_AC97 IRQ_SPI(100)
104
105#define IRQ_SPDIF IRQ_SPI(104)
106#define IRQ_ADC0 IRQ_SPI(105)
107#define IRQ_PEN0 IRQ_SPI(106)
108#define IRQ_ADC1 IRQ_SPI(107)
109#define IRQ_PEN1 IRQ_SPI(108)
110#define IRQ_KEYPAD IRQ_SPI(109)
111#define IRQ_PMU IRQ_SPI(110)
112#define IRQ_GPS IRQ_SPI(111)
113#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
114#define IRQ_SLIMBUS IRQ_SPI(113)
115
116#define IRQ_TSI IRQ_SPI(115)
117#define IRQ_SATA IRQ_SPI(116)
53 118
54#define MAX_IRQ_IN_COMBINER 8 119#define MAX_IRQ_IN_COMBINER 8
55#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) 120#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
56#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 121#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
57 122
58#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 123#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
@@ -73,75 +138,14 @@
73#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 138#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
74#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 139#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
75 140
76#define IRQ_PDMA0 COMBINER_IRQ(21, 0) 141#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
77#define IRQ_PDMA1 COMBINER_IRQ(21, 1) 142#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
78 143#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
79#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
80#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
81#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
82#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
83#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
84
85#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
86#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
87
88#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
89#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
90
91#define IRQ_UART0 COMBINER_IRQ(26, 0)
92#define IRQ_UART1 COMBINER_IRQ(26, 1)
93#define IRQ_UART2 COMBINER_IRQ(26, 2)
94#define IRQ_UART3 COMBINER_IRQ(26, 3)
95#define IRQ_UART4 COMBINER_IRQ(26, 4)
96
97#define IRQ_IIC COMBINER_IRQ(27, 0)
98#define IRQ_IIC1 COMBINER_IRQ(27, 1)
99#define IRQ_IIC2 COMBINER_IRQ(27, 2)
100#define IRQ_IIC3 COMBINER_IRQ(27, 3)
101#define IRQ_IIC4 COMBINER_IRQ(27, 4)
102#define IRQ_IIC5 COMBINER_IRQ(27, 5)
103#define IRQ_IIC6 COMBINER_IRQ(27, 6)
104#define IRQ_IIC7 COMBINER_IRQ(27, 7)
105
106#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
107#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
108#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
109#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
110
111#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
112#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
113
114#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
115#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
116#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
117#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
118
119#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
120
121#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
122
123#define IRQ_EINT4 COMBINER_IRQ(37, 0)
124#define IRQ_EINT5 COMBINER_IRQ(37, 1)
125#define IRQ_EINT6 COMBINER_IRQ(37, 2)
126#define IRQ_EINT7 COMBINER_IRQ(37, 3)
127#define IRQ_EINT8 COMBINER_IRQ(38, 0)
128
129#define IRQ_EINT9 COMBINER_IRQ(38, 1)
130#define IRQ_EINT10 COMBINER_IRQ(38, 2)
131#define IRQ_EINT11 COMBINER_IRQ(38, 3)
132#define IRQ_EINT12 COMBINER_IRQ(38, 4)
133#define IRQ_EINT13 COMBINER_IRQ(38, 5)
134#define IRQ_EINT14 COMBINER_IRQ(38, 6)
135#define IRQ_EINT15 COMBINER_IRQ(38, 7)
136
137#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
138
139#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
140 144
141#define IRQ_WDT COMBINER_IRQ(53, 0) 145#define MAX_COMBINER_NR 16
142#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
143 146
144#define MAX_COMBINER_NR 54 147#define IRQ_ADC IRQ_ADC0
148#define IRQ_TC IRQ_PEN0
145 149
146#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 150#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
147 151
@@ -155,6 +159,6 @@
155#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 159#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
156 160
157/* Set the default NR_IRQS */ 161/* Set the default NR_IRQS */
158#define NR_IRQS (IRQ_GPIO_END) 162#define NR_IRQS (IRQ_GPIO_END + 64)
159 163
160#endif /* __ASM_ARCH_IRQS_H */ 164#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 0009e77a05fc..d32296dc65e2 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -57,12 +57,14 @@
57 57
58#define EXYNOS4_PA_DMC0 0x10400000 58#define EXYNOS4_PA_DMC0 0x10400000
59 59
60#define EXYNOS4_PA_COMBINER 0x10448000 60#define EXYNOS4_PA_COMBINER 0x10440000
61
62#define EXYNOS4_PA_GIC_CPU 0x10480000
63#define EXYNOS4_PA_GIC_DIST 0x10490000
64#define EXYNOS4_GIC_BANK_OFFSET 0x8000
61 65
62#define EXYNOS4_PA_COREPERI 0x10500000 66#define EXYNOS4_PA_COREPERI 0x10500000
63#define EXYNOS4_PA_GIC_CPU 0x10500100
64#define EXYNOS4_PA_TWD 0x10500600 67#define EXYNOS4_PA_TWD 0x10500600
65#define EXYNOS4_PA_GIC_DIST 0x10501000
66#define EXYNOS4_PA_L2CC 0x10502000 68#define EXYNOS4_PA_L2CC 0x10502000
67 69
68#define EXYNOS4_PA_MDMA 0x10810000 70#define EXYNOS4_PA_MDMA 0x10810000
@@ -93,7 +95,10 @@
93#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 95#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
94#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 96#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
95 97
98#define EXYNOS4_PA_FIMD0 0x11C00000
99
96#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 100#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
101#define EXYNOS4_PA_DWMCI 0x12550000
97 102
98#define EXYNOS4_PA_SATA 0x12560000 103#define EXYNOS4_PA_SATA 0x12560000
99#define EXYNOS4_PA_SATAPHY 0x125D0000 104#define EXYNOS4_PA_SATAPHY 0x125D0000
@@ -103,11 +108,15 @@
103 108
104#define EXYNOS4_PA_EHCI 0x12580000 109#define EXYNOS4_PA_EHCI 0x12580000
105#define EXYNOS4_PA_HSPHY 0x125B0000 110#define EXYNOS4_PA_HSPHY 0x125B0000
111#define EXYNOS4_PA_MFC 0x13400000
106 112
107#define EXYNOS4_PA_UART 0x13800000 113#define EXYNOS4_PA_UART 0x13800000
108 114
109#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 115#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
110 116
117#define EXYNOS4_PA_ADC 0x13910000
118#define EXYNOS4_PA_ADC1 0x13911000
119
111#define EXYNOS4_PA_AC97 0x139A0000 120#define EXYNOS4_PA_AC97 0x139A0000
112 121
113#define EXYNOS4_PA_SPDIF 0x139B0000 122#define EXYNOS4_PA_SPDIF 0x139B0000
@@ -130,6 +139,8 @@
130#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) 139#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
131#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) 140#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
132#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 141#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
142#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
143#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
133#define S3C_PA_RTC EXYNOS4_PA_RTC 144#define S3C_PA_RTC EXYNOS4_PA_RTC
134#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 145#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
135 146
@@ -140,10 +151,12 @@
140#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 151#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
141#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 152#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
142#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 153#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
154#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
143#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND 155#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
144#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 156#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
145#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 157#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
146#define S5P_PA_SROMC EXYNOS4_PA_SROMC 158#define S5P_PA_SROMC EXYNOS4_PA_SROMC
159#define S5P_PA_MFC EXYNOS4_PA_MFC
147#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON 160#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
148#define S5P_PA_TIMER EXYNOS4_PA_TIMER 161#define S5P_PA_TIMER EXYNOS4_PA_TIMER
149#define S5P_PA_EHCI EXYNOS4_PA_EHCI 162#define S5P_PA_EHCI EXYNOS4_PA_EHCI
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index f26e46bc06ca..1df3b81f96e8 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
47{ 47{
48 /* nothing here yet */ 48 /* nothing here yet */
49} 49}
50
51static inline void s3c_pm_restored_gpios(void)
52{
53 /* nothing here yet */
54}
55
56static inline void s3c_pm_saved_gpios(void)
57{
58 /* nothing here yet */
59}
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 000000000000..a952904b010e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4210 - PMU(Power Management Unit) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_PMU_H
14#define __ASM_ARCH_PMU_H __FILE__
15
16enum sys_powerdown {
17 SYS_AFTR,
18 SYS_LPA,
19 SYS_SLEEP,
20 NUM_SYS_POWERDOWN,
21};
22
23extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
24
25#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h
new file mode 100644
index 000000000000..ca5a8b64218a
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-exynos4/include/mach/regs-audss.h
2 *
3 * Copyright (c) 2011 Samsung Electronics
4 * http://www.samsung.com
5 *
6 * Exynos4 Audio SubSystem clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_AUDSS_H
14#define __PLAT_REGS_AUDSS_H __FILE__
15
16#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
17
18#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1157f5..d493fdb422ff 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) 26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
27 27
28#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
29#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
30
28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 31#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 32#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 33#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -33,7 +36,9 @@
33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 36#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 37#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 38#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
39#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
36#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) 40#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
41#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
37#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 42#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
38#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 43#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
39#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 44#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@@ -61,6 +66,7 @@
61#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) 66#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
62#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 67#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
63#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 68#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
69#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
64 70
65#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 71#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
66#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 72#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
@@ -120,6 +126,12 @@
120#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) 126#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
121#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) 127#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
122 128
129#define S5P_EPLLCON0_ENABLE_SHIFT (31)
130#define S5P_EPLLCON0_LOCKED_SHIFT (29)
131
132#define S5P_VPLLCON0_ENABLE_SHIFT (31)
133#define S5P_VPLLCON0_LOCKED_SHIFT (29)
134
123#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) 135#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
124#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) 136#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
125 137
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index a9643371f8e7..fa49bbb8e7b0 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -158,6 +158,7 @@
158#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) 158#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
159 159
160#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 160#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
161#define S5P_CORE_LOCAL_PWR_EN 0x3
161#define S5P_INT_LOCAL_PWR_EN 0x7 162#define S5P_INT_LOCAL_PWR_EN 0x7
162 163
163#define S5P_CHECK_SLEEP 0x00000BAD 164#define S5P_CHECK_SLEEP 0x00000BAD
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
deleted file mode 100644
index 6bf3d0ab9627..000000000000
--- a/arch/arm/mach-exynos4/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-exynos4/localtimer.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/localtimer.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/clockchips.h>
14
15#include <asm/irq.h>
16#include <asm/localtimer.h>
17
18/*
19 * Setup the local clock events for a CPU.
20 */
21int __cpuinit local_timer_setup(struct clock_event_device *evt)
22{
23 evt->irq = IRQ_LOCALTIMER;
24 twd_timer_setup(evt);
25 return 0;
26}
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 642702bb5b12..43be71b799cb 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -13,10 +13,15 @@
13#include <linux/input.h> 13#include <linux/input.h>
14#include <linux/i2c.h> 14#include <linux/i2c.h>
15#include <linux/i2c/atmel_mxt_ts.h> 15#include <linux/i2c/atmel_mxt_ts.h>
16#include <linux/i2c-gpio.h>
16#include <linux/gpio_keys.h> 17#include <linux/gpio_keys.h>
17#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/power/max8903_charger.h>
20#include <linux/power/max17042_battery.h>
18#include <linux/regulator/machine.h> 21#include <linux/regulator/machine.h>
19#include <linux/regulator/fixed.h> 22#include <linux/regulator/fixed.h>
23#include <linux/mfd/max8997.h>
24#include <linux/mfd/max8997-private.h>
20#include <linux/mmc/host.h> 25#include <linux/mmc/host.h>
21#include <linux/fb.h> 26#include <linux/fb.h>
22#include <linux/pwm_backlight.h> 27#include <linux/pwm_backlight.h>
@@ -26,6 +31,7 @@
26#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
27#include <asm/mach-types.h> 32#include <asm/mach-types.h>
28 33
34#include <plat/adc.h>
29#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
30#include <plat/exynos4.h> 36#include <plat/exynos4.h>
31#include <plat/cpu.h> 37#include <plat/cpu.h>
@@ -35,6 +41,8 @@
35#include <plat/clock.h> 41#include <plat/clock.h>
36#include <plat/gpio-cfg.h> 42#include <plat/gpio-cfg.h>
37#include <plat/iic.h> 43#include <plat/iic.h>
44#include <plat/mfc.h>
45#include <plat/pd.h>
38 46
39#include <mach/map.h> 47#include <mach/map.h>
40 48
@@ -54,6 +62,7 @@
54 62
55enum fixed_regulator_id { 63enum fixed_regulator_id {
56 FIXED_REG_ID_MMC = 0, 64 FIXED_REG_ID_MMC = 0,
65 FIXED_REG_ID_MAX8903,
57}; 66};
58 67
59static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { 68static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -344,10 +353,730 @@ static void __init nuri_tsp_init(void)
344 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 353 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
345} 354}
346 355
356static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
357 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
358};
359static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
360 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
361};
362static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
363 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
364};
365static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
366 REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
367};
368static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
369 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
370};
371static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
372 REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
373 REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
374};
375static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
376 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
377};
378static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
379 REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
380};
381static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
382 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
383};
384static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
385 REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
386};
387static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
388 REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
389};
390static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
391 REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
392};
393static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
394 REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
395};
396static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
397 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
398};
399static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
400 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
401};
402static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
403 REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
404};
405static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
406 REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
407};
408static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
409 REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
410};
411static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
412 REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
413};
414static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
415 REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
416};
417
418static struct regulator_consumer_supply __initdata max8997_charger_[] = {
419 REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
420};
421static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
422 REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
423};
424
425static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
426 REGULATOR_SUPPLY("gps_clk", "bcm4751"),
427 REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
428 REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
429};
430
431static struct regulator_init_data __initdata max8997_ldo1_data = {
432 .constraints = {
433 .name = "VADC_3.3V_C210",
434 .min_uV = 3300000,
435 .max_uV = 3300000,
436 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
437 .apply_uV = 1,
438 .state_mem = {
439 .disabled = 1,
440 },
441 },
442 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_),
443 .consumer_supplies = max8997_ldo1_,
444};
445
446static struct regulator_init_data __initdata max8997_ldo2_data = {
447 .constraints = {
448 .name = "VALIVE_1.1V_C210",
449 .min_uV = 1100000,
450 .max_uV = 1100000,
451 .apply_uV = 1,
452 .always_on = 1,
453 .state_mem = {
454 .enabled = 1,
455 },
456 },
457};
458
459static struct regulator_init_data __initdata max8997_ldo3_data = {
460 .constraints = {
461 .name = "VUSB_1.1V_C210",
462 .min_uV = 1100000,
463 .max_uV = 1100000,
464 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
465 .apply_uV = 1,
466 .state_mem = {
467 .disabled = 1,
468 },
469 },
470 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_),
471 .consumer_supplies = max8997_ldo3_,
472};
473
474static struct regulator_init_data __initdata max8997_ldo4_data = {
475 .constraints = {
476 .name = "VMIPI_1.8V",
477 .min_uV = 1800000,
478 .max_uV = 1800000,
479 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
480 .apply_uV = 1,
481 .state_mem = {
482 .disabled = 1,
483 },
484 },
485 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_),
486 .consumer_supplies = max8997_ldo4_,
487};
488
489static struct regulator_init_data __initdata max8997_ldo5_data = {
490 .constraints = {
491 .name = "VHSIC_1.2V_C210",
492 .min_uV = 1200000,
493 .max_uV = 1200000,
494 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
495 .apply_uV = 1,
496 .state_mem = {
497 .disabled = 1,
498 },
499 },
500 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_),
501 .consumer_supplies = max8997_ldo5_,
502};
503
504static struct regulator_init_data __initdata max8997_ldo6_data = {
505 .constraints = {
506 .name = "VCC_1.8V_PDA",
507 .min_uV = 1800000,
508 .max_uV = 1800000,
509 .apply_uV = 1,
510 .always_on = 1,
511 .state_mem = {
512 .enabled = 1,
513 },
514 },
515};
516
517static struct regulator_init_data __initdata max8997_ldo7_data = {
518 .constraints = {
519 .name = "CAM_ISP_1.8V",
520 .min_uV = 1800000,
521 .max_uV = 1800000,
522 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
523 .apply_uV = 1,
524 .state_mem = {
525 .disabled = 1,
526 },
527 },
528 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_),
529 .consumer_supplies = max8997_ldo7_,
530};
531
532static struct regulator_init_data __initdata max8997_ldo8_data = {
533 .constraints = {
534 .name = "VUSB/VDAC_3.3V_C210",
535 .min_uV = 3300000,
536 .max_uV = 3300000,
537 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
538 .apply_uV = 1,
539 .state_mem = {
540 .disabled = 1,
541 },
542 },
543 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_),
544 .consumer_supplies = max8997_ldo8_,
545};
546
547static struct regulator_init_data __initdata max8997_ldo9_data = {
548 .constraints = {
549 .name = "VCC_2.8V_PDA",
550 .min_uV = 2800000,
551 .max_uV = 2800000,
552 .apply_uV = 1,
553 .always_on = 1,
554 .state_mem = {
555 .enabled = 1,
556 },
557 },
558};
559
560static struct regulator_init_data __initdata max8997_ldo10_data = {
561 .constraints = {
562 .name = "VPLL_1.1V_C210",
563 .min_uV = 1100000,
564 .max_uV = 1100000,
565 .apply_uV = 1,
566 .always_on = 1,
567 .state_mem = {
568 .disabled = 1,
569 },
570 },
571};
572
573static struct regulator_init_data __initdata max8997_ldo11_data = {
574 .constraints = {
575 .name = "LVDS_VDD3.3V",
576 .min_uV = 3300000,
577 .max_uV = 3300000,
578 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
579 .apply_uV = 1,
580 .boot_on = 1,
581 .state_mem = {
582 .disabled = 1,
583 },
584 },
585 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_),
586 .consumer_supplies = max8997_ldo11_,
587};
588
589static struct regulator_init_data __initdata max8997_ldo12_data = {
590 .constraints = {
591 .name = "VT_CAM_1.8V",
592 .min_uV = 1800000,
593 .max_uV = 1800000,
594 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
595 .apply_uV = 1,
596 .state_mem = {
597 .disabled = 1,
598 },
599 },
600 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_),
601 .consumer_supplies = max8997_ldo12_,
602};
603
604static struct regulator_init_data __initdata max8997_ldo13_data = {
605 .constraints = {
606 .name = "VTF_2.8V",
607 .min_uV = 2800000,
608 .max_uV = 2800000,
609 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
610 .apply_uV = 1,
611 .state_mem = {
612 .disabled = 1,
613 },
614 },
615 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_),
616 .consumer_supplies = max8997_ldo13_,
617};
618
619static struct regulator_init_data __initdata max8997_ldo14_data = {
620 .constraints = {
621 .name = "VCC_3.0V_MOTOR",
622 .min_uV = 3000000,
623 .max_uV = 3000000,
624 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
625 .apply_uV = 1,
626 .state_mem = {
627 .disabled = 1,
628 },
629 },
630 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_),
631 .consumer_supplies = max8997_ldo14_,
632};
633
634static struct regulator_init_data __initdata max8997_ldo15_data = {
635 .constraints = {
636 .name = "VTOUCH_ADVV2.8V",
637 .min_uV = 2800000,
638 .max_uV = 2800000,
639 .apply_uV = 1,
640 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
641 .state_mem = {
642 .disabled = 1,
643 },
644 },
645 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_),
646 .consumer_supplies = max8997_ldo15_,
647};
648
649static struct regulator_init_data __initdata max8997_ldo16_data = {
650 .constraints = {
651 .name = "CAM_SENSOR_IO_1.8V",
652 .min_uV = 1800000,
653 .max_uV = 1800000,
654 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
655 .apply_uV = 1,
656 .state_mem = {
657 .disabled = 1,
658 },
659 },
660 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_),
661 .consumer_supplies = max8997_ldo16_,
662};
663
664static struct regulator_init_data __initdata max8997_ldo18_data = {
665 .constraints = {
666 .name = "VTOUCH_VDD2.8V",
667 .min_uV = 2800000,
668 .max_uV = 2800000,
669 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
670 .apply_uV = 1,
671 .state_mem = {
672 .disabled = 1,
673 },
674 },
675 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_),
676 .consumer_supplies = max8997_ldo18_,
677};
678
679static struct regulator_init_data __initdata max8997_ldo21_data = {
680 .constraints = {
681 .name = "VDDQ_M1M2_1.2V",
682 .min_uV = 1200000,
683 .max_uV = 1200000,
684 .apply_uV = 1,
685 .always_on = 1,
686 .state_mem = {
687 .disabled = 1,
688 },
689 },
690};
691
692static struct regulator_init_data __initdata max8997_buck1_data = {
693 .constraints = {
694 .name = "VARM_1.2V_C210",
695 .min_uV = 900000,
696 .max_uV = 1350000,
697 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
698 .always_on = 1,
699 .state_mem = {
700 .disabled = 1,
701 },
702 },
703 .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
704 .consumer_supplies = max8997_buck1_,
705};
706
707static struct regulator_init_data __initdata max8997_buck2_data = {
708 .constraints = {
709 .name = "VINT_1.1V_C210",
710 .min_uV = 900000,
711 .max_uV = 1100000,
712 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
713 .always_on = 1,
714 .state_mem = {
715 .disabled = 1,
716 },
717 },
718 .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
719 .consumer_supplies = max8997_buck2_,
720};
721
722static struct regulator_init_data __initdata max8997_buck3_data = {
723 .constraints = {
724 .name = "VG3D_1.1V_C210",
725 .min_uV = 900000,
726 .max_uV = 1100000,
727 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
728 REGULATOR_CHANGE_STATUS,
729 .state_mem = {
730 .disabled = 1,
731 },
732 },
733 .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
734 .consumer_supplies = max8997_buck3_,
735};
736
737static struct regulator_init_data __initdata max8997_buck4_data = {
738 .constraints = {
739 .name = "CAM_ISP_CORE_1.2V",
740 .min_uV = 1200000,
741 .max_uV = 1200000,
742 .apply_uV = 1,
743 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
744 .state_mem = {
745 .disabled = 1,
746 },
747 },
748 .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
749 .consumer_supplies = max8997_buck4_,
750};
751
752static struct regulator_init_data __initdata max8997_buck5_data = {
753 .constraints = {
754 .name = "VMEM_1.2V_C210",
755 .min_uV = 1200000,
756 .max_uV = 1200000,
757 .apply_uV = 1,
758 .always_on = 1,
759 .state_mem = {
760 .enabled = 1,
761 },
762 },
763};
764
765static struct regulator_init_data __initdata max8997_buck6_data = {
766 .constraints = {
767 .name = "CAM_AF_2.8V",
768 .min_uV = 2800000,
769 .max_uV = 2800000,
770 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
771 .state_mem = {
772 .disabled = 1,
773 },
774 },
775 .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
776 .consumer_supplies = max8997_buck6_,
777};
778
779static struct regulator_init_data __initdata max8997_buck7_data = {
780 .constraints = {
781 .name = "VCC_SUB_2.0V",
782 .min_uV = 2000000,
783 .max_uV = 2000000,
784 .apply_uV = 1,
785 .always_on = 1,
786 .state_mem = {
787 .enabled = 1,
788 },
789 },
790};
791
792static struct regulator_init_data __initdata max8997_32khz_ap_data = {
793 .constraints = {
794 .name = "32KHz AP",
795 .always_on = 1,
796 .state_mem = {
797 .enabled = 1,
798 },
799 },
800 .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
801 .consumer_supplies = max8997_32khz_ap_,
802};
803
804static struct regulator_init_data __initdata max8997_32khz_cp_data = {
805 .constraints = {
806 .name = "32KHz CP",
807 .state_mem = {
808 .disabled = 1,
809 },
810 },
811};
812
813static struct regulator_init_data __initdata max8997_vichg_data = {
814 .constraints = {
815 .name = "VICHG",
816 .state_mem = {
817 .disabled = 1,
818 },
819 },
820};
821
822static struct regulator_init_data __initdata max8997_esafeout1_data = {
823 .constraints = {
824 .name = "SAFEOUT1",
825 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
826 .state_mem = {
827 .disabled = 1,
828 },
829 },
830 .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_),
831 .consumer_supplies = max8997_esafeout1_,
832};
833
834static struct regulator_init_data __initdata max8997_esafeout2_data = {
835 .constraints = {
836 .name = "SAFEOUT2",
837 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
838 .state_mem = {
839 .disabled = 1,
840 },
841 },
842 .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_),
843 .consumer_supplies = max8997_esafeout2_,
844};
845
846static struct regulator_init_data __initdata max8997_charger_cv_data = {
847 .constraints = {
848 .name = "CHARGER_CV",
849 .min_uV = 4200000,
850 .max_uV = 4200000,
851 .apply_uV = 1,
852 },
853};
854
855static struct regulator_init_data __initdata max8997_charger_data = {
856 .constraints = {
857 .name = "CHARGER",
858 .min_uA = 200000,
859 .max_uA = 950000,
860 .boot_on = 1,
861 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
862 REGULATOR_CHANGE_CURRENT,
863 },
864 .num_consumer_supplies = ARRAY_SIZE(max8997_charger_),
865 .consumer_supplies = max8997_charger_,
866};
867
868static struct regulator_init_data __initdata max8997_charger_topoff_data = {
869 .constraints = {
870 .name = "CHARGER TOPOFF",
871 .min_uA = 50000,
872 .max_uA = 200000,
873 .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
874 },
875 .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_),
876 .consumer_supplies = max8997_chg_toff_,
877};
878
879static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
880 { MAX8997_LDO1, &max8997_ldo1_data },
881 { MAX8997_LDO2, &max8997_ldo2_data },
882 { MAX8997_LDO3, &max8997_ldo3_data },
883 { MAX8997_LDO4, &max8997_ldo4_data },
884 { MAX8997_LDO5, &max8997_ldo5_data },
885 { MAX8997_LDO6, &max8997_ldo6_data },
886 { MAX8997_LDO7, &max8997_ldo7_data },
887 { MAX8997_LDO8, &max8997_ldo8_data },
888 { MAX8997_LDO9, &max8997_ldo9_data },
889 { MAX8997_LDO10, &max8997_ldo10_data },
890 { MAX8997_LDO11, &max8997_ldo11_data },
891 { MAX8997_LDO12, &max8997_ldo12_data },
892 { MAX8997_LDO13, &max8997_ldo13_data },
893 { MAX8997_LDO14, &max8997_ldo14_data },
894 { MAX8997_LDO15, &max8997_ldo15_data },
895 { MAX8997_LDO16, &max8997_ldo16_data },
896
897 { MAX8997_LDO18, &max8997_ldo18_data },
898 { MAX8997_LDO21, &max8997_ldo21_data },
899
900 { MAX8997_BUCK1, &max8997_buck1_data },
901 { MAX8997_BUCK2, &max8997_buck2_data },
902 { MAX8997_BUCK3, &max8997_buck3_data },
903 { MAX8997_BUCK4, &max8997_buck4_data },
904 { MAX8997_BUCK5, &max8997_buck5_data },
905 { MAX8997_BUCK6, &max8997_buck6_data },
906 { MAX8997_BUCK7, &max8997_buck7_data },
907
908 { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
909 { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
910
911 { MAX8997_ENVICHG, &max8997_vichg_data },
912 { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
913 { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
914 { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
915 { MAX8997_CHARGER, &max8997_charger_data },
916 { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
917};
918
919static struct max8997_platform_data __initdata nuri_max8997_pdata = {
920 .wakeup = 1,
921
922 .num_regulators = ARRAY_SIZE(nuri_max8997_regulators),
923 .regulators = nuri_max8997_regulators,
924
925 .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
926 .buck2_gpiodvs = true,
927
928 .buck1_voltage[0] = 1350000, /* 1.35V */
929 .buck1_voltage[1] = 1300000, /* 1.3V */
930 .buck1_voltage[2] = 1250000, /* 1.25V */
931 .buck1_voltage[3] = 1200000, /* 1.2V */
932 .buck1_voltage[4] = 1150000, /* 1.15V */
933 .buck1_voltage[5] = 1100000, /* 1.1V */
934 .buck1_voltage[6] = 1000000, /* 1.0V */
935 .buck1_voltage[7] = 950000, /* 0.95V */
936
937 .buck2_voltage[0] = 1100000, /* 1.1V */
938 .buck2_voltage[1] = 1000000, /* 1.0V */
939 .buck2_voltage[2] = 950000, /* 0.95V */
940 .buck2_voltage[3] = 900000, /* 0.9V */
941 .buck2_voltage[4] = 1100000, /* 1.1V */
942 .buck2_voltage[5] = 1000000, /* 1.0V */
943 .buck2_voltage[6] = 950000, /* 0.95V */
944 .buck2_voltage[7] = 900000, /* 0.9V */
945
946 .buck5_voltage[0] = 1200000, /* 1.2V */
947 .buck5_voltage[1] = 1200000, /* 1.2V */
948 .buck5_voltage[2] = 1200000, /* 1.2V */
949 .buck5_voltage[3] = 1200000, /* 1.2V */
950 .buck5_voltage[4] = 1200000, /* 1.2V */
951 .buck5_voltage[5] = 1200000, /* 1.2V */
952 .buck5_voltage[6] = 1200000, /* 1.2V */
953 .buck5_voltage[7] = 1200000, /* 1.2V */
954};
955
347/* GPIO I2C 5 (PMIC) */ 956/* GPIO I2C 5 (PMIC) */
957enum { I2C5_MAX8997 };
348static struct i2c_board_info i2c5_devs[] __initdata = { 958static struct i2c_board_info i2c5_devs[] __initdata = {
349 /* max8997, To be updated */ 959 [I2C5_MAX8997] = {
960 I2C_BOARD_INFO("max8997", 0xCC >> 1),
961 .platform_data = &nuri_max8997_pdata,
962 },
963};
964
965static struct max17042_platform_data nuri_battery_platform_data = {
966};
967
968/* GPIO I2C 9 (Fuel Gauge) */
969static struct i2c_gpio_platform_data i2c9_gpio_data = {
970 .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */
971 .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */
972};
973static struct platform_device i2c9_gpio = {
974 .name = "i2c-gpio",
975 .id = 9,
976 .dev = {
977 .platform_data = &i2c9_gpio_data,
978 },
350}; 979};
980enum { I2C9_MAX17042};
981static struct i2c_board_info i2c9_devs[] __initdata = {
982 [I2C9_MAX17042] = {
983 I2C_BOARD_INFO("max17042", 0x36),
984 .platform_data = &nuri_battery_platform_data,
985 },
986};
987
988/* MAX8903 Secondary Charger */
989static struct regulator_consumer_supply supplies_max8903[] = {
990 REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
991};
992
993static struct regulator_init_data max8903_charger_en_data = {
994 .constraints = {
995 .name = "VOUT_CHARGER",
996 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
997 .boot_on = 1,
998 },
999 .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
1000 .consumer_supplies = supplies_max8903,
1001};
1002
1003static struct fixed_voltage_config max8903_charger_en = {
1004 .supply_name = "VOUT_CHARGER",
1005 .microvolts = 5000000, /* Assume 5VDC */
1006 .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
1007 .enable_high = 0, /* Enable = Low */
1008 .enabled_at_boot = 1,
1009 .init_data = &max8903_charger_en_data,
1010};
1011
1012static struct platform_device max8903_fixed_reg_dev = {
1013 .name = "reg-fixed-voltage",
1014 .id = FIXED_REG_ID_MAX8903,
1015 .dev = { .platform_data = &max8903_charger_en },
1016};
1017
1018static struct max8903_pdata nuri_max8903 = {
1019 /*
1020 * cen: don't control with the driver, let it be
1021 * controlled by regulator above
1022 */
1023 .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
1024 /* uok, usus: not connected */
1025 .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
1026 /* flt: vcc_1.8V_pda */
1027 .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
1028
1029 .dc_valid = true,
1030 .usb_valid = false, /* USB is not wired to MAX8903 */
1031};
1032
1033static struct platform_device nuri_max8903_device = {
1034 .name = "max8903-charger",
1035 .dev = {
1036 .platform_data = &nuri_max8903,
1037 },
1038};
1039
1040static struct device *nuri_cm_devices[] = {
1041 &s3c_device_i2c5.dev,
1042 &s3c_device_adc.dev,
1043 NULL, /* Reserved for UART */
1044 NULL,
1045};
1046
1047static void __init nuri_power_init(void)
1048{
1049 int gpio;
1050 int irq_base = IRQ_GPIO_END + 1;
1051 int ta_en = 0;
1052
1053 nuri_max8997_pdata.irq_base = irq_base;
1054 irq_base += MAX8997_IRQ_NR;
1055
1056 gpio = EXYNOS4_GPX0(7);
1057 gpio_request(gpio, "AP_PMIC_IRQ");
1058 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1059 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1060
1061 gpio = EXYNOS4_GPX2(3);
1062 gpio_request(gpio, "FUEL_ALERT");
1063 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1064 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1065
1066 gpio = nuri_max8903.dok;
1067 gpio_request(gpio, "TA_nCONNECTED");
1068 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1069 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1070 ta_en = gpio_get_value(gpio) ? 0 : 1;
1071
1072 gpio = nuri_max8903.chg;
1073 gpio_request(gpio, "TA_nCHG");
1074 gpio_direction_input(gpio);
1075
1076 gpio = nuri_max8903.dcm;
1077 gpio_request(gpio, "CURR_ADJ");
1078 gpio_direction_output(gpio, ta_en);
1079}
351 1080
352/* USB EHCI */ 1081/* USB EHCI */
353static struct s5p_ehci_platdata nuri_ehci_pdata; 1082static struct s5p_ehci_platdata nuri_ehci_pdata;
@@ -361,6 +1090,7 @@ static void __init nuri_ehci_init(void)
361 1090
362static struct platform_device *nuri_devices[] __initdata = { 1091static struct platform_device *nuri_devices[] __initdata = {
363 /* Samsung Platform Devices */ 1092 /* Samsung Platform Devices */
1093 &s3c_device_i2c5, /* PMIC should initialize first */
364 &emmc_fixed_voltage, 1094 &emmc_fixed_voltage,
365 &s3c_device_hsmmc0, 1095 &s3c_device_hsmmc0,
366 &s3c_device_hsmmc2, 1096 &s3c_device_hsmmc2,
@@ -369,11 +1099,20 @@ static struct platform_device *nuri_devices[] __initdata = {
369 &s3c_device_timer[0], 1099 &s3c_device_timer[0],
370 &s5p_device_ehci, 1100 &s5p_device_ehci,
371 &s3c_device_i2c3, 1101 &s3c_device_i2c3,
1102 &i2c9_gpio,
1103 &s3c_device_adc,
1104 &s3c_device_rtc,
1105 &s5p_device_mfc,
1106 &s5p_device_mfc_l,
1107 &s5p_device_mfc_r,
1108 &exynos4_device_pd[PD_MFC],
372 1109
373 /* NURI Devices */ 1110 /* NURI Devices */
374 &nuri_gpio_keys, 1111 &nuri_gpio_keys,
375 &nuri_lcd_device, 1112 &nuri_lcd_device,
376 &nuri_backlight_device, 1113 &nuri_backlight_device,
1114 &max8903_fixed_reg_dev,
1115 &nuri_max8903_device,
377}; 1116};
378 1117
379static void __init nuri_map_io(void) 1118static void __init nuri_map_io(void)
@@ -383,21 +1122,32 @@ static void __init nuri_map_io(void)
383 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1122 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
384} 1123}
385 1124
1125static void __init nuri_reserve(void)
1126{
1127 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1128}
1129
386static void __init nuri_machine_init(void) 1130static void __init nuri_machine_init(void)
387{ 1131{
388 nuri_sdhci_init(); 1132 nuri_sdhci_init();
389 nuri_tsp_init(); 1133 nuri_tsp_init();
1134 nuri_power_init();
390 1135
391 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 1136 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
392 s3c_i2c3_set_platdata(&i2c3_data); 1137 s3c_i2c3_set_platdata(&i2c3_data);
393 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); 1138 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1139 s3c_i2c5_set_platdata(NULL);
1140 i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
394 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); 1141 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1142 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
1143 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
395 1144
396 nuri_ehci_init(); 1145 nuri_ehci_init();
397 clk_xusbxti.rate = 24000000; 1146 clk_xusbxti.rate = 24000000;
398 1147
399 /* Last */ 1148 /* Last */
400 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); 1149 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
1150 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
401} 1151}
402 1152
403MACHINE_START(NURI, "NURI") 1153MACHINE_START(NURI, "NURI")
@@ -407,4 +1157,5 @@ MACHINE_START(NURI, "NURI")
407 .map_io = nuri_map_io, 1157 .map_io = nuri_map_io,
408 .init_machine = nuri_machine_init, 1158 .init_machine = nuri_machine_init,
409 .timer = &exynos4_timer, 1159 .timer = &exynos4_timer,
1160 .reserve = &nuri_reserve,
410MACHINE_END 1161MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index e645f7a955f0..31cfcd64a20a 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -9,7 +9,9 @@
9*/ 9*/
10 10
11#include <linux/serial_core.h> 11#include <linux/serial_core.h>
12#include <linux/delay.h>
12#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/lcd.h>
13#include <linux/mmc/host.h> 15#include <linux/mmc/host.h>
14#include <linux/platform_device.h> 16#include <linux/platform_device.h>
15#include <linux/smsc911x.h> 17#include <linux/smsc911x.h>
@@ -19,11 +21,15 @@
19#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
20#include <asm/mach-types.h> 22#include <asm/mach-types.h>
21 23
24#include <video/platform_lcd.h>
25
22#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
23#include <plat/regs-srom.h> 27#include <plat/regs-srom.h>
28#include <plat/regs-fb-v4.h>
24#include <plat/exynos4.h> 29#include <plat/exynos4.h>
25#include <plat/cpu.h> 30#include <plat/cpu.h>
26#include <plat/devs.h> 31#include <plat/devs.h>
32#include <plat/fb.h>
27#include <plat/sdhci.h> 33#include <plat/sdhci.h>
28#include <plat/iic.h> 34#include <plat/iic.h>
29#include <plat/pd.h> 35#include <plat/pd.h>
@@ -111,6 +117,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 117 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112}; 118};
113 119
120static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
121 unsigned int power)
122{
123 if (power) {
124#if !defined(CONFIG_BACKLIGHT_PWM)
125 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
126 gpio_free(EXYNOS4_GPD0(1));
127#endif
128 /* fire nRESET on power up */
129 gpio_request(EXYNOS4_GPX0(6), "GPX0");
130
131 gpio_direction_output(EXYNOS4_GPX0(6), 1);
132 mdelay(100);
133
134 gpio_set_value(EXYNOS4_GPX0(6), 0);
135 mdelay(10);
136
137 gpio_set_value(EXYNOS4_GPX0(6), 1);
138 mdelay(10);
139
140 gpio_free(EXYNOS4_GPX0(6));
141 } else {
142#if !defined(CONFIG_BACKLIGHT_PWM)
143 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
144 gpio_free(EXYNOS4_GPD0(1));
145#endif
146 }
147}
148
149static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
150 .set_power = lcd_lte480wv_set_power,
151};
152
153static struct platform_device smdkc210_lcd_lte480wv = {
154 .name = "platform-lcd",
155 .dev.parent = &s5p_device_fimd0.dev,
156 .dev.platform_data = &smdkc210_lcd_lte480wv_data,
157};
158
159static struct s3c_fb_pd_win smdkc210_fb_win0 = {
160 .win_mode = {
161 .left_margin = 13,
162 .right_margin = 8,
163 .upper_margin = 7,
164 .lower_margin = 5,
165 .hsync_len = 3,
166 .vsync_len = 1,
167 .xres = 800,
168 .yres = 480,
169 },
170 .max_bpp = 32,
171 .default_bpp = 24,
172};
173
174static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
175 .win[0] = &smdkc210_fb_win0,
176 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
177 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
178 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
179};
180
114static struct resource smdkc210_smsc911x_resources[] = { 181static struct resource smdkc210_smsc911x_resources[] = {
115 [0] = { 182 [0] = {
116 .start = EXYNOS4_PA_SROM_BANK(1), 183 .start = EXYNOS4_PA_SROM_BANK(1),
@@ -165,6 +232,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
165 &exynos4_device_pd[PD_GPS], 232 &exynos4_device_pd[PD_GPS],
166 &exynos4_device_sysmmu, 233 &exynos4_device_sysmmu,
167 &samsung_asoc_dma, 234 &samsung_asoc_dma,
235 &s5p_device_fimd0,
236 &smdkc210_lcd_lte480wv,
168 &smdkc210_smsc911x, 237 &smdkc210_smsc911x,
169}; 238};
170 239
@@ -210,6 +279,8 @@ static void __init smdkc210_machine_init(void)
210 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); 279 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); 280 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
212 281
282 s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
283
213 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); 284 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
214} 285}
215 286
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index edd814110da8..ccc8fa11b541 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -181,9 +181,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
181 &exynos4_device_pd[PD_CAM], 181 &exynos4_device_pd[PD_CAM],
182 &exynos4_device_pd[PD_TV], 182 &exynos4_device_pd[PD_TV],
183 &exynos4_device_pd[PD_GPS], 183 &exynos4_device_pd[PD_GPS],
184 &exynos4_device_spdif,
184 &exynos4_device_sysmmu, 185 &exynos4_device_sysmmu,
185 &samsung_asoc_dma, 186 &samsung_asoc_dma,
187 &samsung_asoc_idma,
186 &smdkv310_smsc911x, 188 &smdkv310_smsc911x,
189 &exynos4_device_ahci,
187}; 190};
188 191
189static void __init smdkv310_smsc911x_init(void) 192static void __init smdkv310_smsc911x_init(void)
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 97d329fff2cf..0e280d12301e 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -18,6 +18,9 @@
18#include <linux/regulator/fixed.h> 18#include <linux/regulator/fixed.h>
19#include <linux/regulator/max8952.h> 19#include <linux/regulator/max8952.h>
20#include <linux/mmc/host.h> 20#include <linux/mmc/host.h>
21#include <linux/i2c-gpio.h>
22#include <linux/i2c/mcs.h>
23#include <linux/i2c/atmel_mxt_ts.h>
21 24
22#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
23#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -27,7 +30,10 @@
27#include <plat/cpu.h> 30#include <plat/cpu.h>
28#include <plat/devs.h> 31#include <plat/devs.h>
29#include <plat/iic.h> 32#include <plat/iic.h>
33#include <plat/gpio-cfg.h>
34#include <plat/mfc.h>
30#include <plat/sdhci.h> 35#include <plat/sdhci.h>
36#include <plat/pd.h>
31 37
32#include <mach/map.h> 38#include <mach/map.h>
33 39
@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
477 }, 483 },
478}; 484};
479 485
486/* I2C3 (TSP) */
487static struct mxt_platform_data qt602240_platform_data = {
488 .x_line = 19,
489 .y_line = 11,
490 .x_size = 800,
491 .y_size = 480,
492 .blen = 0x11,
493 .threshold = 0x28,
494 .voltage = 2800000, /* 2.8V */
495 .orient = MXT_DIAGONAL,
496};
497
498static struct i2c_board_info i2c3_devs[] __initdata = {
499 {
500 I2C_BOARD_INFO("qt602240_ts", 0x4a),
501 .platform_data = &qt602240_platform_data,
502 },
503};
504
505static void __init universal_tsp_init(void)
506{
507 int gpio;
508
509 /* TSP_LDO_ON: XMDMADDR_11 */
510 gpio = EXYNOS4_GPE2(3);
511 gpio_request(gpio, "TSP_LDO_ON");
512 gpio_direction_output(gpio, 1);
513 gpio_export(gpio, 0);
514
515 /* TSP_INT: XMDMADDR_7 */
516 gpio = EXYNOS4_GPE1(7);
517 gpio_request(gpio, "TSP_INT");
518
519 s5p_register_gpio_interrupt(gpio);
520 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
521 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
522 i2c3_devs[0].irq = gpio_to_irq(gpio);
523}
524
525
526/* GPIO I2C 12 (3 Touchkey) */
527static uint32_t touchkey_keymap[] = {
528 /* MCS_KEY_MAP(value, keycode) */
529 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
530 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
531};
532
533static struct mcs_platform_data touchkey_data = {
534 .keymap = touchkey_keymap,
535 .keymap_size = ARRAY_SIZE(touchkey_keymap),
536 .key_maxval = 2,
537};
538
539/* GPIO I2C 3_TOUCH 2.8V */
540#define I2C_GPIO_BUS_12 12
541static struct i2c_gpio_platform_data i2c_gpio12_data = {
542 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
543 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
544};
545
546static struct platform_device i2c_gpio12 = {
547 .name = "i2c-gpio",
548 .id = I2C_GPIO_BUS_12,
549 .dev = {
550 .platform_data = &i2c_gpio12_data,
551 },
552};
553
554static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
555 {
556 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
557 .platform_data = &touchkey_data,
558 },
559};
560
561static void __init universal_touchkey_init(void)
562{
563 int gpio;
564
565 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
566 gpio_request(gpio, "3_TOUCH_INT");
567 s5p_register_gpio_interrupt(gpio);
568 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
569 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
570
571 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
572 gpio_request(gpio, "3_TOUCH_EN");
573 gpio_direction_output(gpio, 1);
574}
575
480/* GPIO KEYS */ 576/* GPIO KEYS */
481static struct gpio_keys_button universal_gpio_keys_tables[] = { 577static struct gpio_keys_button universal_gpio_keys_tables[] = {
482 { 578 {
@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
608 704
609static struct platform_device *universal_devices[] __initdata = { 705static struct platform_device *universal_devices[] __initdata = {
610 /* Samsung Platform Devices */ 706 /* Samsung Platform Devices */
707 &s5p_device_fimc0,
708 &s5p_device_fimc1,
709 &s5p_device_fimc2,
710 &s5p_device_fimc3,
611 &mmc0_fixed_voltage, 711 &mmc0_fixed_voltage,
612 &s3c_device_hsmmc0, 712 &s3c_device_hsmmc0,
613 &s3c_device_hsmmc2, 713 &s3c_device_hsmmc2,
614 &s3c_device_hsmmc3, 714 &s3c_device_hsmmc3,
715 &s3c_device_i2c3,
615 &s3c_device_i2c5, 716 &s3c_device_i2c5,
616 717
617 /* Universal Devices */ 718 /* Universal Devices */
719 &i2c_gpio12,
618 &universal_gpio_keys, 720 &universal_gpio_keys,
619 &s5p_device_onenand, 721 &s5p_device_onenand,
722 &s5p_device_mfc,
723 &s5p_device_mfc_l,
724 &s5p_device_mfc_r,
725 &exynos4_device_pd[PD_MFC],
620}; 726};
621 727
622static void __init universal_map_io(void) 728static void __init universal_map_io(void)
@@ -626,6 +732,11 @@ static void __init universal_map_io(void)
626 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 732 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
627} 733}
628 734
735static void __init universal_reserve(void)
736{
737 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
738}
739
629static void __init universal_machine_init(void) 740static void __init universal_machine_init(void)
630{ 741{
631 universal_sdhci_init(); 742 universal_sdhci_init();
@@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
633 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); 744 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
634 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 745 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
635 746
747 universal_tsp_init();
748 s3c_i2c3_set_platdata(NULL);
749 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
750
636 s3c_i2c5_set_platdata(NULL); 751 s3c_i2c5_set_platdata(NULL);
637 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); 752 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
638 753
754 universal_touchkey_init();
755 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
756 ARRAY_SIZE(i2c_gpio12_devs));
757
639 /* Last */ 758 /* Last */
640 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); 759 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
760 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
641} 761}
642 762
643MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 763MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
647 .map_io = universal_map_io, 767 .map_io = universal_map_io,
648 .init_machine = universal_machine_init, 768 .init_machine = universal_machine_init,
649 .timer = &exynos4_timer, 769 .timer = &exynos4_timer,
770 .reserve = &universal_reserve,
650MACHINE_END 771MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 14ac10b7ec02..1ae059b7ad7b 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
384 } else { 384 } else {
385 mct_tick1_event_irq.dev_id = &mct_tick[cpu]; 385 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
386 irq_set_affinity(IRQ_MCT1, cpumask_of(1));
387 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); 386 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
387 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
388 } 388 }
389} 389}
390 390
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index c5e65a02be8d..a7f312c12893 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h>
31 32
32extern void exynos4_secondary_startup(void); 33extern void exynos4_secondary_startup(void);
33 34
35#define CPU1_BOOT_REG S5P_VA_SYSRAM
36
34/* 37/*
35 * control for which core is the next to come out of the secondary 38 * control for which core is the next to come out of the secondary
36 * boot "holding pen" 39 * boot "holding pen"
@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
58 61
59static DEFINE_SPINLOCK(boot_lock); 62static DEFINE_SPINLOCK(boot_lock);
60 63
64static void __cpuinit exynos4_gic_secondary_init(void)
65{
66 void __iomem *dist_base = S5P_VA_GIC_DIST +
67 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
68 void __iomem *cpu_base = S5P_VA_GIC_CPU +
69 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
70 int i;
71
72 /*
73 * Deal with the banked PPI and SGI interrupts - disable all
74 * PPI interrupts, ensure all SGI interrupts are enabled.
75 */
76 __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
77 __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
78
79 /*
80 * Set priority on PPI and SGI interrupts
81 */
82 for (i = 0; i < 32; i += 4)
83 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
84
85 __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
86 __raw_writel(1, cpu_base + GIC_CPU_CTRL);
87}
88
61void __cpuinit platform_secondary_init(unsigned int cpu) 89void __cpuinit platform_secondary_init(unsigned int cpu)
62{ 90{
63 /* 91 /*
@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
65 * core (e.g. timer irq), then they will not have been enabled 93 * core (e.g. timer irq), then they will not have been enabled
66 * for us: do so 94 * for us: do so
67 */ 95 */
68 gic_secondary_init(0); 96 exynos4_gic_secondary_init();
69 97
70 /* 98 /*
71 * let the primary processor know we're out of the 99 * let the primary processor know we're out of the
@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
100 */ 128 */
101 write_pen_release(cpu); 129 write_pen_release(cpu);
102 130
131 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
132 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
133 S5P_ARM_CORE1_CONFIGURATION);
134
135 timeout = 10;
136
137 /* wait max 10 ms until cpu1 is on */
138 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
139 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
140 if (timeout-- == 0)
141 break;
142
143 mdelay(1);
144 }
145
146 if (timeout == 0) {
147 printk(KERN_ERR "cpu1 power enable failed");
148 spin_unlock(&boot_lock);
149 return -ETIMEDOUT;
150 }
151 }
103 /* 152 /*
104 * Send the secondary CPU a soft interrupt, thereby causing 153 * Send the secondary CPU a soft interrupt, thereby causing
105 * the boot monitor to read the system wide flags register, 154 * the boot monitor to read the system wide flags register,
106 * and branch to the address found there. 155 * and branch to the address found there.
107 */ 156 */
108 gic_raise_softirq(cpumask_of(cpu), 1);
109 157
110 timeout = jiffies + (1 * HZ); 158 timeout = jiffies + (1 * HZ);
111 while (time_before(jiffies, timeout)) { 159 while (time_before(jiffies, timeout)) {
112 smp_rmb(); 160 smp_rmb();
161
162 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
163 CPU1_BOOT_REG);
164 gic_raise_softirq(cpumask_of(cpu), 1);
165
113 if (pen_release == -1) 166 if (pen_release == -1)
114 break; 167 break;
115 168
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 8755ca8dd48d..9ef2e99fb8b6 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,92 +18,23 @@
18#include <linux/suspend.h> 18#include <linux/suspend.h>
19#include <linux/syscore_ops.h> 19#include <linux/syscore_ops.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/err.h>
22#include <linux/clk.h>
21 23
22#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
23#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
24 26
25#include <plat/cpu.h> 27#include <plat/cpu.h>
26#include <plat/pm.h> 28#include <plat/pm.h>
29#include <plat/pll.h>
30#include <plat/regs-srom.h>
27 31
28#include <mach/regs-irq.h> 32#include <mach/regs-irq.h>
29#include <mach/regs-gpio.h> 33#include <mach/regs-gpio.h>
30#include <mach/regs-clock.h> 34#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 35#include <mach/regs-pmu.h>
32#include <mach/pm-core.h> 36#include <mach/pm-core.h>
33 37#include <mach/pmu.h>
34static struct sleep_save exynos4_sleep[] = {
35 { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
36 { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
37 { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
38 { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
39 { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
40 { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
41 { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
42 { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
43 { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
44 { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
45 { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
46 { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
47 { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
48 { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
49 { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
50 { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
51 { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
52 { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
53 { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
54 { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
55 { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
56 { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
57 { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
58 { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
59 { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
60 { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
61 { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
62 { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
63 { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
64 { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
65 { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
66 { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
67 { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
68 { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
69 { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
70 { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
71 { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
72 { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
73 { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
74 { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
75 { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
76 { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
77 { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
78 { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
79 { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
80 { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
81 { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
82 { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
83 { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
84 { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
85 { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
86 { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
87 { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
88 { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
89 { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
90 { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
91 { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
92 { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
93 { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
94 { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
95 { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
96 { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
97 { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
98 { .reg = S5P_TV_LOWPWR , .val = 0x0, },
99 { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
100 { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
101 { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
102 { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
103 { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
104 { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
105 { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
106};
107 38
108static struct sleep_save exynos4_set_clksrc[] = { 39static struct sleep_save exynos4_set_clksrc[] = {
109 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, 40 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
118 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, 49 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
119}; 50};
120 51
52static struct sleep_save exynos4_epll_save[] = {
53 SAVE_ITEM(S5P_EPLL_CON0),
54 SAVE_ITEM(S5P_EPLL_CON1),
55};
56
57static struct sleep_save exynos4_vpll_save[] = {
58 SAVE_ITEM(S5P_VPLL_CON0),
59 SAVE_ITEM(S5P_VPLL_CON1),
60};
61
121static struct sleep_save exynos4_core_save[] = { 62static struct sleep_save exynos4_core_save[] = {
122 /* CMU side */ 63 /* CMU side */
123 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 64 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
124 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 65 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
125 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), 66 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
126 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), 67 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
127 SAVE_ITEM(S5P_EPLL_CON0),
128 SAVE_ITEM(S5P_EPLL_CON1),
129 SAVE_ITEM(S5P_VPLL_CON0),
130 SAVE_ITEM(S5P_VPLL_CON1),
131 SAVE_ITEM(S5P_CLKSRC_TOP0), 68 SAVE_ITEM(S5P_CLKSRC_TOP0),
132 SAVE_ITEM(S5P_CLKSRC_TOP1), 69 SAVE_ITEM(S5P_CLKSRC_TOP1),
133 SAVE_ITEM(S5P_CLKSRC_CAM), 70 SAVE_ITEM(S5P_CLKSRC_CAM),
71 SAVE_ITEM(S5P_CLKSRC_TV),
134 SAVE_ITEM(S5P_CLKSRC_MFC), 72 SAVE_ITEM(S5P_CLKSRC_MFC),
73 SAVE_ITEM(S5P_CLKSRC_G3D),
135 SAVE_ITEM(S5P_CLKSRC_IMAGE), 74 SAVE_ITEM(S5P_CLKSRC_IMAGE),
136 SAVE_ITEM(S5P_CLKSRC_LCD0), 75 SAVE_ITEM(S5P_CLKSRC_LCD0),
137 SAVE_ITEM(S5P_CLKSRC_LCD1), 76 SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
158 SAVE_ITEM(S5P_CLKDIV_PERIL4), 97 SAVE_ITEM(S5P_CLKDIV_PERIL4),
159 SAVE_ITEM(S5P_CLKDIV_PERIL5), 98 SAVE_ITEM(S5P_CLKDIV_PERIL5),
160 SAVE_ITEM(S5P_CLKDIV_TOP), 99 SAVE_ITEM(S5P_CLKDIV_TOP),
100 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
161 SAVE_ITEM(S5P_CLKSRC_MASK_CAM), 101 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
162 SAVE_ITEM(S5P_CLKSRC_MASK_TV), 102 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
163 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), 103 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
166 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), 106 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
167 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), 107 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
168 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), 108 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
109 SAVE_ITEM(S5P_CLKDIV2_RATIO),
169 SAVE_ITEM(S5P_CLKGATE_SCLKCAM), 110 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
170 SAVE_ITEM(S5P_CLKGATE_IP_CAM), 111 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
171 SAVE_ITEM(S5P_CLKGATE_IP_TV), 112 SAVE_ITEM(S5P_CLKGATE_IP_TV),
@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
186 SAVE_ITEM(S5P_CLKGATE_IP_DMC), 127 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
187 SAVE_ITEM(S5P_CLKSRC_CPU), 128 SAVE_ITEM(S5P_CLKSRC_CPU),
188 SAVE_ITEM(S5P_CLKDIV_CPU), 129 SAVE_ITEM(S5P_CLKDIV_CPU),
130 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
189 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 131 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
190 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 132 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
133
191 /* GIC side */ 134 /* GIC side */
192 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), 135 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
193 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), 136 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
270 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), 213 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
271 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), 214 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
272 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), 215 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
216
217 /* SROM side */
218 SAVE_ITEM(S5P_SROM_BW),
219 SAVE_ITEM(S5P_SROM_BC0),
220 SAVE_ITEM(S5P_SROM_BC1),
221 SAVE_ITEM(S5P_SROM_BC2),
222 SAVE_ITEM(S5P_SROM_BC3),
273}; 223};
274 224
275static struct sleep_save exynos4_l2cc_save[] = { 225static struct sleep_save exynos4_l2cc_save[] = {
@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
280 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), 230 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
281}; 231};
282 232
283void exynos4_cpu_suspend(void) 233/* For Cortex-A9 Diagnostic and Power control register */
284{ 234static unsigned int save_arm_register[2];
285 unsigned long tmp;
286 unsigned long mask = 0xFFFFFFFF;
287
288 /* Setting Central Sequence Register for power down mode */
289
290 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
291 tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
292 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
293
294 /* Setting Central Sequence option Register */
295
296 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
297 tmp &= ~(S5P_USE_MASK);
298 tmp |= S5P_USE_STANDBY_WFI0;
299 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
300
301 /* Clear all interrupt pending to avoid early wakeup */
302
303 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
304 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
305 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
306
307 /* Disable all interrupt */
308
309 __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
310 __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
311 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
312 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
313 235
236void exynos4_cpu_suspend(unsigned long arg)
237{
314 outer_flush_all(); 238 outer_flush_all();
315 239
316 /* issue the standby signal into the pm unit. */ 240 /* issue the standby signal into the pm unit. */
@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
326 250
327 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 251 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
328 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 252 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
253 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
254 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
329 255
330 tmp = __raw_readl(S5P_INFORM1); 256 tmp = __raw_readl(S5P_INFORM1);
331 257
332 /* Set value of power down register for sleep mode */ 258 /* Set value of power down register for sleep mode */
333 259
334 s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep)); 260 exynos4_sys_powerdown_conf(SYS_SLEEP);
335 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 261 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
336 262
337 /* ensure at least INFORM0 has the resume address */ 263 /* ensure at least INFORM0 has the resume address */
@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
373 flush_cache_all(); 299 flush_cache_all();
374} 300}
375 301
302static unsigned long pll_base_rate;
303
304static void exynos4_restore_pll(void)
305{
306 unsigned long pll_con, locktime, lockcnt;
307 unsigned long pll_in_rate;
308 unsigned int p_div, epll_wait = 0, vpll_wait = 0;
309
310 if (pll_base_rate == 0)
311 return;
312
313 pll_in_rate = pll_base_rate;
314
315 /* EPLL */
316 pll_con = exynos4_epll_save[0].val;
317
318 if (pll_con & (1 << 31)) {
319 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
320 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
321
322 pll_in_rate /= 1000000;
323
324 locktime = (3000 / pll_in_rate) * p_div;
325 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
326
327 __raw_writel(lockcnt, S5P_EPLL_LOCK);
328
329 s3c_pm_do_restore_core(exynos4_epll_save,
330 ARRAY_SIZE(exynos4_epll_save));
331 epll_wait = 1;
332 }
333
334 pll_in_rate = pll_base_rate;
335
336 /* VPLL */
337 pll_con = exynos4_vpll_save[0].val;
338
339 if (pll_con & (1 << 31)) {
340 pll_in_rate /= 1000000;
341 /* 750us */
342 locktime = 750;
343 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
344
345 __raw_writel(lockcnt, S5P_VPLL_LOCK);
346
347 s3c_pm_do_restore_core(exynos4_vpll_save,
348 ARRAY_SIZE(exynos4_vpll_save));
349 vpll_wait = 1;
350 }
351
352 /* Wait PLL locking */
353
354 do {
355 if (epll_wait) {
356 pll_con = __raw_readl(S5P_EPLL_CON0);
357 if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
358 epll_wait = 0;
359 }
360
361 if (vpll_wait) {
362 pll_con = __raw_readl(S5P_VPLL_CON0);
363 if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
364 vpll_wait = 0;
365 }
366 } while (epll_wait || vpll_wait);
367}
368
376static struct sysdev_driver exynos4_pm_driver = { 369static struct sysdev_driver exynos4_pm_driver = {
377 .add = exynos4_pm_add, 370 .add = exynos4_pm_add,
378}; 371};
379 372
380static __init int exynos4_pm_drvinit(void) 373static __init int exynos4_pm_drvinit(void)
381{ 374{
375 struct clk *pll_base;
382 unsigned int tmp; 376 unsigned int tmp;
383 377
384 s3c_pm_init(); 378 s3c_pm_init();
@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
389 tmp |= ((0xFF << 8) | (0x1F << 1)); 383 tmp |= ((0xFF << 8) | (0x1F << 1));
390 __raw_writel(tmp, S5P_WAKEUP_MASK); 384 __raw_writel(tmp, S5P_WAKEUP_MASK);
391 385
386 pll_base = clk_get(NULL, "xtal");
387
388 if (!IS_ERR(pll_base)) {
389 pll_base_rate = clk_get_rate(pll_base);
390 clk_put(pll_base);
391 }
392
392 return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); 393 return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
393} 394}
394arch_initcall(exynos4_pm_drvinit); 395arch_initcall(exynos4_pm_drvinit);
395 396
397static int exynos4_pm_suspend(void)
398{
399 unsigned long tmp;
400
401 /* Setting Central Sequence Register for power down mode */
402
403 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
404 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
405 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
406
407 /* Save Power control register */
408 asm ("mrc p15, 0, %0, c15, c0, 0"
409 : "=r" (tmp) : : "cc");
410 save_arm_register[0] = tmp;
411
412 /* Save Diagnostic register */
413 asm ("mrc p15, 0, %0, c15, c0, 1"
414 : "=r" (tmp) : : "cc");
415 save_arm_register[1] = tmp;
416
417 return 0;
418}
419
396static void exynos4_pm_resume(void) 420static void exynos4_pm_resume(void)
397{ 421{
422 unsigned long tmp;
423
424 /*
425 * If PMU failed while entering sleep mode, WFI will be
426 * ignored by PMU and then exiting cpu_do_idle().
427 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
428 * in this situation.
429 */
430 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
431 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
432 tmp |= S5P_CENTRAL_LOWPWR_CFG;
433 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
434 /* No need to perform below restore code */
435 goto early_wakeup;
436 }
437 /* Restore Power control register */
438 tmp = save_arm_register[0];
439 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
440 : : "r" (tmp)
441 : "cc");
442
443 /* Restore Diagnostic register */
444 tmp = save_arm_register[1];
445 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
446 : : "r" (tmp)
447 : "cc");
448
398 /* For release retention */ 449 /* For release retention */
399 450
400 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 451 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
407 458
408 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 459 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
409 460
461 exynos4_restore_pll();
462
410 exynos4_scu_enable(S5P_VA_SCU); 463 exynos4_scu_enable(S5P_VA_SCU);
411 464
412#ifdef CONFIG_CACHE_L2X0 465#ifdef CONFIG_CACHE_L2X0
@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
415 /* enable L2X0*/ 468 /* enable L2X0*/
416 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); 469 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
417#endif 470#endif
471
472early_wakeup:
473 return;
418} 474}
419 475
420static struct syscore_ops exynos4_pm_syscore_ops = { 476static struct syscore_ops exynos4_pm_syscore_ops = {
477 .suspend = exynos4_pm_suspend,
421 .resume = exynos4_pm_resume, 478 .resume = exynos4_pm_resume,
422}; 479};
423 480
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 000000000000..7ea9eb2a20d2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
1/* linux/arch/arm/mach-exynos4/pmu.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4210 - CPU PMU(Power Management Unit) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15
16#include <mach/regs-clock.h>
17#include <mach/pmu.h>
18
19static void __iomem *sys_powerdown_reg[] = {
20 S5P_ARM_CORE0_LOWPWR,
21 S5P_DIS_IRQ_CORE0,
22 S5P_DIS_IRQ_CENTRAL0,
23 S5P_ARM_CORE1_LOWPWR,
24 S5P_DIS_IRQ_CORE1,
25 S5P_DIS_IRQ_CENTRAL1,
26 S5P_ARM_COMMON_LOWPWR,
27 S5P_L2_0_LOWPWR,
28 S5P_L2_1_LOWPWR,
29 S5P_CMU_ACLKSTOP_LOWPWR,
30 S5P_CMU_SCLKSTOP_LOWPWR,
31 S5P_CMU_RESET_LOWPWR,
32 S5P_APLL_SYSCLK_LOWPWR,
33 S5P_MPLL_SYSCLK_LOWPWR,
34 S5P_VPLL_SYSCLK_LOWPWR,
35 S5P_EPLL_SYSCLK_LOWPWR,
36 S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
37 S5P_CMU_RESET_GPSALIVE_LOWPWR,
38 S5P_CMU_CLKSTOP_CAM_LOWPWR,
39 S5P_CMU_CLKSTOP_TV_LOWPWR,
40 S5P_CMU_CLKSTOP_MFC_LOWPWR,
41 S5P_CMU_CLKSTOP_G3D_LOWPWR,
42 S5P_CMU_CLKSTOP_LCD0_LOWPWR,
43 S5P_CMU_CLKSTOP_LCD1_LOWPWR,
44 S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
45 S5P_CMU_CLKSTOP_GPS_LOWPWR,
46 S5P_CMU_RESET_CAM_LOWPWR,
47 S5P_CMU_RESET_TV_LOWPWR,
48 S5P_CMU_RESET_MFC_LOWPWR,
49 S5P_CMU_RESET_G3D_LOWPWR,
50 S5P_CMU_RESET_LCD0_LOWPWR,
51 S5P_CMU_RESET_LCD1_LOWPWR,
52 S5P_CMU_RESET_MAUDIO_LOWPWR,
53 S5P_CMU_RESET_GPS_LOWPWR,
54 S5P_TOP_BUS_LOWPWR,
55 S5P_TOP_RETENTION_LOWPWR,
56 S5P_TOP_PWR_LOWPWR,
57 S5P_LOGIC_RESET_LOWPWR,
58 S5P_ONENAND_MEM_LOWPWR,
59 S5P_MODIMIF_MEM_LOWPWR,
60 S5P_G2D_ACP_MEM_LOWPWR,
61 S5P_USBOTG_MEM_LOWPWR,
62 S5P_HSMMC_MEM_LOWPWR,
63 S5P_CSSYS_MEM_LOWPWR,
64 S5P_SECSS_MEM_LOWPWR,
65 S5P_PCIE_MEM_LOWPWR,
66 S5P_SATA_MEM_LOWPWR,
67 S5P_PAD_RETENTION_DRAM_LOWPWR,
68 S5P_PAD_RETENTION_MAUDIO_LOWPWR,
69 S5P_PAD_RETENTION_GPIO_LOWPWR,
70 S5P_PAD_RETENTION_UART_LOWPWR,
71 S5P_PAD_RETENTION_MMCA_LOWPWR,
72 S5P_PAD_RETENTION_MMCB_LOWPWR,
73 S5P_PAD_RETENTION_EBIA_LOWPWR,
74 S5P_PAD_RETENTION_EBIB_LOWPWR,
75 S5P_PAD_RETENTION_ISOLATION_LOWPWR,
76 S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
77 S5P_XUSBXTI_LOWPWR,
78 S5P_XXTI_LOWPWR,
79 S5P_EXT_REGULATOR_LOWPWR,
80 S5P_GPIO_MODE_LOWPWR,
81 S5P_GPIO_MODE_MAUDIO_LOWPWR,
82 S5P_CAM_LOWPWR,
83 S5P_TV_LOWPWR,
84 S5P_MFC_LOWPWR,
85 S5P_G3D_LOWPWR,
86 S5P_LCD0_LOWPWR,
87 S5P_LCD1_LOWPWR,
88 S5P_MAUDIO_LOWPWR,
89 S5P_GPS_LOWPWR,
90 S5P_GPS_ALIVE_LOWPWR,
91};
92
93static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
94 /* { AFTR, LPA, SLEEP }*/
95 { 0, 0, 2 }, /* ARM_CORE0 */
96 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
97 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
98 { 0, 0, 2 }, /* ARM_CORE1 */
99 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
100 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
101 { 0, 0, 2 }, /* ARM_COMMON */
102 { 2, 2, 3 }, /* ARM_CPU_L2_0 */
103 { 2, 2, 3 }, /* ARM_CPU_L2_1 */
104 { 1, 0, 0 }, /* CMU_ACLKSTOP */
105 { 1, 0, 0 }, /* CMU_SCLKSTOP */
106 { 1, 1, 0 }, /* CMU_RESET */
107 { 1, 0, 0 }, /* APLL_SYSCLK */
108 { 1, 0, 0 }, /* MPLL_SYSCLK */
109 { 1, 0, 0 }, /* VPLL_SYSCLK */
110 { 1, 1, 0 }, /* EPLL_SYSCLK */
111 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
112 { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
113 { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
114 { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
115 { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
116 { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
117 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
118 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
119 { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
120 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
121 { 1, 1, 0 }, /* CMU_RESET_CAM */
122 { 1, 1, 0 }, /* CMU_RESET_TV */
123 { 1, 1, 0 }, /* CMU_RESET_MFC */
124 { 1, 1, 0 }, /* CMU_RESET_G3D */
125 { 1, 1, 0 }, /* CMU_RESET_LCD0 */
126 { 1, 1, 0 }, /* CMU_RESET_LCD1 */
127 { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
128 { 1, 1, 0 }, /* CMU_RESET_GPS */
129 { 3, 0, 0 }, /* TOP_BUS */
130 { 1, 0, 1 }, /* TOP_RETENTION */
131 { 3, 0, 3 }, /* TOP_PWR */
132 { 1, 1, 0 }, /* LOGIC_RESET */
133 { 3, 0, 0 }, /* ONENAND_MEM */
134 { 3, 0, 0 }, /* MODIMIF_MEM */
135 { 3, 0, 0 }, /* G2D_ACP_MEM */
136 { 3, 0, 0 }, /* USBOTG_MEM */
137 { 3, 0, 0 }, /* HSMMC_MEM */
138 { 3, 0, 0 }, /* CSSYS_MEM */
139 { 3, 0, 0 }, /* SECSS_MEM */
140 { 3, 0, 0 }, /* PCIE_MEM */
141 { 3, 0, 0 }, /* SATA_MEM */
142 { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
143 { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
144 { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
145 { 1, 0, 0 }, /* PAD_RETENTION_UART */
146 { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
147 { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
148 { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
149 { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
150 { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
151 { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
152 { 1, 1, 0 }, /* XUSBXTI */
153 { 1, 1, 0 }, /* XXTI */
154 { 1, 1, 0 }, /* EXT_REGULATOR */
155 { 1, 0, 0 }, /* GPIO_MODE */
156 { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
157 { 7, 0, 0 }, /* CAM */
158 { 7, 0, 0 }, /* TV */
159 { 7, 0, 0 }, /* MFC */
160 { 7, 0, 0 }, /* G3D */
161 { 7, 0, 0 }, /* LCD0 */
162 { 7, 0, 0 }, /* LCD1 */
163 { 7, 7, 0 }, /* MAUDIO */
164 { 7, 0, 0 }, /* GPS */
165 { 7, 0, 0 }, /* GPS_ALIVE */
166};
167
168void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
169{
170 unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
171
172 for (; count > 0; count--)
173 __raw_writel(sys_powerdown_val[count - 1][mode],
174 sys_powerdown_reg[count - 1]);
175}
diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos4/setup-fimd0.c
new file mode 100644
index 000000000000..07a6dbeecdd0
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-fimd0.c
@@ -0,0 +1,43 @@
1/* linux/arch/arm/mach-exynos4/setup-fimd0.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base Exynos4 FIMD 0 configuration
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/fb.h>
14#include <linux/gpio.h>
15
16#include <plat/gpio-cfg.h>
17#include <plat/regs-fb-v4.h>
18
19#include <mach/map.h>
20
21void exynos4_fimd0_gpio_setup_24bpp(void)
22{
23 unsigned int reg;
24
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
26 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
28 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
29
30 /*
31 * Set DISPLAY_CONTROL register for Display path selection.
32 *
33 * DISPLAY_CONTROL[1:0]
34 * ---------------------
35 * 00 | MIE
36 * 01 | MDINE
37 * 10 | FIMD : selected
38 * 11 | FIMD
39 */
40 reg = __raw_readl(S3C_VA_SYS + 0x0210);
41 reg |= (1 << 1);
42 __raw_writel(reg, S3C_VA_SYS + 0x0210);
43}
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
deleted file mode 100644
index ebb8f38d5405..000000000000
--- a/arch/arm/mach-exynos4/time.c
+++ /dev/null
@@ -1,301 +0,0 @@
1/* linux/arch/arm/mach-exynos4/time.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 (and compatible) HRT support
7 * PWM 2/4 is used for this feature
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/clockchips.h>
20#include <linux/platform_device.h>
21
22#include <asm/smp_twd.h>
23
24#include <mach/map.h>
25#include <plat/regs-timer.h>
26#include <asm/mach/time.h>
27
28static unsigned long clock_count_per_tick;
29
30static struct clk *tin2;
31static struct clk *tin4;
32static struct clk *tdiv2;
33static struct clk *tdiv4;
34static struct clk *timerclk;
35
36static void exynos4_pwm_stop(unsigned int pwm_id)
37{
38 unsigned long tcon;
39
40 tcon = __raw_readl(S3C2410_TCON);
41
42 switch (pwm_id) {
43 case 2:
44 tcon &= ~S3C2410_TCON_T2START;
45 break;
46 case 4:
47 tcon &= ~S3C2410_TCON_T4START;
48 break;
49 default:
50 break;
51 }
52 __raw_writel(tcon, S3C2410_TCON);
53}
54
55static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
56{
57 unsigned long tcon;
58
59 tcon = __raw_readl(S3C2410_TCON);
60
61 /* timers reload after counting zero, so reduce the count by 1 */
62 tcnt--;
63
64 /* ensure timer is stopped... */
65 switch (pwm_id) {
66 case 2:
67 tcon &= ~(0xf<<12);
68 tcon |= S3C2410_TCON_T2MANUALUPD;
69
70 __raw_writel(tcnt, S3C2410_TCNTB(2));
71 __raw_writel(tcnt, S3C2410_TCMPB(2));
72 __raw_writel(tcon, S3C2410_TCON);
73
74 break;
75 case 4:
76 tcon &= ~(7<<20);
77 tcon |= S3C2410_TCON_T4MANUALUPD;
78
79 __raw_writel(tcnt, S3C2410_TCNTB(4));
80 __raw_writel(tcnt, S3C2410_TCMPB(4));
81 __raw_writel(tcon, S3C2410_TCON);
82
83 break;
84 default:
85 break;
86 }
87}
88
89static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
90{
91 unsigned long tcon;
92
93 tcon = __raw_readl(S3C2410_TCON);
94
95 switch (pwm_id) {
96 case 2:
97 tcon |= S3C2410_TCON_T2START;
98 tcon &= ~S3C2410_TCON_T2MANUALUPD;
99
100 if (periodic)
101 tcon |= S3C2410_TCON_T2RELOAD;
102 else
103 tcon &= ~S3C2410_TCON_T2RELOAD;
104 break;
105 case 4:
106 tcon |= S3C2410_TCON_T4START;
107 tcon &= ~S3C2410_TCON_T4MANUALUPD;
108
109 if (periodic)
110 tcon |= S3C2410_TCON_T4RELOAD;
111 else
112 tcon &= ~S3C2410_TCON_T4RELOAD;
113 break;
114 default:
115 break;
116 }
117 __raw_writel(tcon, S3C2410_TCON);
118}
119
120static int exynos4_pwm_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt)
122{
123 exynos4_pwm_init(2, cycles);
124 exynos4_pwm_start(2, 0);
125 return 0;
126}
127
128static void exynos4_pwm_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
130{
131 exynos4_pwm_stop(2);
132
133 switch (mode) {
134 case CLOCK_EVT_MODE_PERIODIC:
135 exynos4_pwm_init(2, clock_count_per_tick);
136 exynos4_pwm_start(2, 1);
137 break;
138 case CLOCK_EVT_MODE_ONESHOT:
139 break;
140 case CLOCK_EVT_MODE_UNUSED:
141 case CLOCK_EVT_MODE_SHUTDOWN:
142 case CLOCK_EVT_MODE_RESUME:
143 break;
144 }
145}
146
147static struct clock_event_device pwm_event_device = {
148 .name = "pwm_timer2",
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .rating = 200,
151 .shift = 32,
152 .set_next_event = exynos4_pwm_set_next_event,
153 .set_mode = exynos4_pwm_set_mode,
154};
155
156irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
157{
158 struct clock_event_device *evt = &pwm_event_device;
159
160 evt->event_handler(evt);
161
162 return IRQ_HANDLED;
163}
164
165static struct irqaction exynos4_clock_event_irq = {
166 .name = "pwm_timer2_irq",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = exynos4_clock_event_isr,
169};
170
171static void __init exynos4_clockevent_init(void)
172{
173 unsigned long pclk;
174 unsigned long clock_rate;
175 struct clk *tscaler;
176
177 pclk = clk_get_rate(timerclk);
178
179 /* configure clock tick */
180
181 tscaler = clk_get_parent(tdiv2);
182
183 clk_set_rate(tscaler, pclk / 2);
184 clk_set_rate(tdiv2, pclk / 2);
185 clk_set_parent(tin2, tdiv2);
186
187 clock_rate = clk_get_rate(tin2);
188
189 clock_count_per_tick = clock_rate / HZ;
190
191 pwm_event_device.mult =
192 div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
193 pwm_event_device.max_delta_ns =
194 clockevent_delta2ns(-1, &pwm_event_device);
195 pwm_event_device.min_delta_ns =
196 clockevent_delta2ns(1, &pwm_event_device);
197
198 pwm_event_device.cpumask = cpumask_of(0);
199 clockevents_register_device(&pwm_event_device);
200
201 setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
202}
203
204static cycle_t exynos4_pwm4_read(struct clocksource *cs)
205{
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207}
208
209#ifdef CONFIG_PM
210static void exynos4_pwm4_resume(struct clocksource *cs)
211{
212 unsigned long pclk;
213
214 pclk = clk_get_rate(timerclk);
215
216 clk_set_rate(tdiv4, pclk / 2);
217 clk_set_parent(tin4, tdiv4);
218
219 exynos4_pwm_init(4, ~0);
220 exynos4_pwm_start(4, 1);
221}
222#endif
223
224struct clocksource pwm_clocksource = {
225 .name = "pwm_timer4",
226 .rating = 250,
227 .read = exynos4_pwm4_read,
228 .mask = CLOCKSOURCE_MASK(32),
229 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
230#ifdef CONFIG_PM
231 .resume = exynos4_pwm4_resume,
232#endif
233};
234
235static void __init exynos4_clocksource_init(void)
236{
237 unsigned long pclk;
238 unsigned long clock_rate;
239
240 pclk = clk_get_rate(timerclk);
241
242 clk_set_rate(tdiv4, pclk / 2);
243 clk_set_parent(tin4, tdiv4);
244
245 clock_rate = clk_get_rate(tin4);
246
247 exynos4_pwm_init(4, ~0);
248 exynos4_pwm_start(4, 1);
249
250 if (clocksource_register_hz(&pwm_clocksource, clock_rate))
251 panic("%s: can't register clocksource\n", pwm_clocksource.name);
252}
253
254static void __init exynos4_timer_resources(void)
255{
256 struct platform_device tmpdev;
257
258 tmpdev.dev.bus = &platform_bus_type;
259
260 timerclk = clk_get(NULL, "timers");
261 if (IS_ERR(timerclk))
262 panic("failed to get timers clock for system timer");
263
264 clk_enable(timerclk);
265
266 tmpdev.id = 2;
267 tin2 = clk_get(&tmpdev.dev, "pwm-tin");
268 if (IS_ERR(tin2))
269 panic("failed to get pwm-tin2 clock for system timer");
270
271 tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
272 if (IS_ERR(tdiv2))
273 panic("failed to get pwm-tdiv2 clock for system timer");
274 clk_enable(tin2);
275
276 tmpdev.id = 4;
277 tin4 = clk_get(&tmpdev.dev, "pwm-tin");
278 if (IS_ERR(tin4))
279 panic("failed to get pwm-tin4 clock for system timer");
280
281 tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
282 if (IS_ERR(tdiv4))
283 panic("failed to get pwm-tdiv4 clock for system timer");
284
285 clk_enable(tin4);
286}
287
288static void __init exynos4_timer_init(void)
289{
290#ifdef CONFIG_LOCAL_TIMERS
291 twd_base = S5P_VA_TWD;
292#endif
293
294 exynos4_timer_resources();
295 exynos4_clockevent_init();
296 exynos4_clocksource_init();
297}
298
299struct sys_timer exynos4_timer = {
300 .init = exynos4_timer_init,
301};
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h
index 70a83b209e25..45eea5210c87 100644
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h
@@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
62 struct pm_uart_save *save) 62 struct pm_uart_save *save)
63{ 63{
64} 64}
65
66static inline void s3c_pm_restored_gpios(void) { }
67static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 0c0505b025cb..140711db6c89 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
95 95
96static struct clk clk_erefclk = { 96static struct clk clk_erefclk = {
97 .name = "erefclk", 97 .name = "erefclk",
98 .id = -1,
99}; 98};
100 99
101static struct clk clk_urefclk = { 100static struct clk clk_urefclk = {
102 .name = "urefclk", 101 .name = "urefclk",
103 .id = -1,
104}; 102};
105 103
106static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) 104static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
122 120
123static struct clk clk_usysclk = { 121static struct clk clk_usysclk = {
124 .name = "usysclk", 122 .name = "usysclk",
125 .id = -1,
126 .parent = &clk_xtal, 123 .parent = &clk_xtal,
127 .ops = &(struct clk_ops) { 124 .ops = &(struct clk_ops) {
128 .set_parent = s3c2412_setparent_usysclk, 125 .set_parent = s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
132static struct clk clk_mrefclk = { 129static struct clk clk_mrefclk = {
133 .name = "mrefclk", 130 .name = "mrefclk",
134 .parent = &clk_xtal, 131 .parent = &clk_xtal,
135 .id = -1,
136}; 132};
137 133
138static struct clk clk_mdivclk = { 134static struct clk clk_mdivclk = {
139 .name = "mdivclk", 135 .name = "mdivclk",
140 .parent = &clk_xtal, 136 .parent = &clk_xtal,
141 .id = -1,
142}; 137};
143 138
144static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) 139static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
200 195
201static struct clk clk_usbsrc = { 196static struct clk clk_usbsrc = {
202 .name = "usbsrc", 197 .name = "usbsrc",
203 .id = -1,
204 .ops = &(struct clk_ops) { 198 .ops = &(struct clk_ops) {
205 .get_rate = s3c2412_getrate_usbsrc, 199 .get_rate = s3c2412_getrate_usbsrc,
206 .set_rate = s3c2412_setrate_usbsrc, 200 .set_rate = s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
228 222
229static struct clk clk_msysclk = { 223static struct clk clk_msysclk = {
230 .name = "msysclk", 224 .name = "msysclk",
231 .id = -1,
232 .ops = &(struct clk_ops) { 225 .ops = &(struct clk_ops) {
233 .set_parent = s3c2412_setparent_msysclk, 226 .set_parent = s3c2412_setparent_msysclk,
234 }, 227 },
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
268 261
269static struct clk clk_armclk = { 262static struct clk clk_armclk = {
270 .name = "armclk", 263 .name = "armclk",
271 .id = -1,
272 .parent = &clk_msysclk, 264 .parent = &clk_msysclk,
273 .ops = &(struct clk_ops) { 265 .ops = &(struct clk_ops) {
274 .set_parent = s3c2412_setparent_armclk, 266 .set_parent = s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
344 336
345static struct clk clk_uart = { 337static struct clk clk_uart = {
346 .name = "uartclk", 338 .name = "uartclk",
347 .id = -1,
348 .ops = &(struct clk_ops) { 339 .ops = &(struct clk_ops) {
349 .get_rate = s3c2412_getrate_uart, 340 .get_rate = s3c2412_getrate_uart,
350 .set_rate = s3c2412_setrate_uart, 341 .set_rate = s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
397 388
398static struct clk clk_i2s = { 389static struct clk clk_i2s = {
399 .name = "i2sclk", 390 .name = "i2sclk",
400 .id = -1,
401 .ops = &(struct clk_ops) { 391 .ops = &(struct clk_ops) {
402 .get_rate = s3c2412_getrate_i2s, 392 .get_rate = s3c2412_getrate_i2s,
403 .set_rate = s3c2412_setrate_i2s, 393 .set_rate = s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
449 439
450static struct clk clk_cam = { 440static struct clk clk_cam = {
451 .name = "camif-upll", /* same as 2440 name */ 441 .name = "camif-upll", /* same as 2440 name */
452 .id = -1,
453 .ops = &(struct clk_ops) { 442 .ops = &(struct clk_ops) {
454 .get_rate = s3c2412_getrate_cam, 443 .get_rate = s3c2412_getrate_cam,
455 .set_rate = s3c2412_setrate_cam, 444 .set_rate = s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = {
463static struct clk init_clocks_disable[] = { 452static struct clk init_clocks_disable[] = {
464 { 453 {
465 .name = "nand", 454 .name = "nand",
466 .id = -1,
467 .parent = &clk_h, 455 .parent = &clk_h,
468 .enable = s3c2412_clkcon_enable, 456 .enable = s3c2412_clkcon_enable,
469 .ctrlbit = S3C2412_CLKCON_NAND, 457 .ctrlbit = S3C2412_CLKCON_NAND,
470 }, { 458 }, {
471 .name = "sdi", 459 .name = "sdi",
472 .id = -1,
473 .parent = &clk_p, 460 .parent = &clk_p,
474 .enable = s3c2412_clkcon_enable, 461 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_SDI, 462 .ctrlbit = S3C2412_CLKCON_SDI,
476 }, { 463 }, {
477 .name = "adc", 464 .name = "adc",
478 .id = -1,
479 .parent = &clk_p, 465 .parent = &clk_p,
480 .enable = s3c2412_clkcon_enable, 466 .enable = s3c2412_clkcon_enable,
481 .ctrlbit = S3C2412_CLKCON_ADC, 467 .ctrlbit = S3C2412_CLKCON_ADC,
482 }, { 468 }, {
483 .name = "i2c", 469 .name = "i2c",
484 .id = -1,
485 .parent = &clk_p, 470 .parent = &clk_p,
486 .enable = s3c2412_clkcon_enable, 471 .enable = s3c2412_clkcon_enable,
487 .ctrlbit = S3C2412_CLKCON_IIC, 472 .ctrlbit = S3C2412_CLKCON_IIC,
488 }, { 473 }, {
489 .name = "iis", 474 .name = "iis",
490 .id = -1,
491 .parent = &clk_p, 475 .parent = &clk_p,
492 .enable = s3c2412_clkcon_enable, 476 .enable = s3c2412_clkcon_enable,
493 .ctrlbit = S3C2412_CLKCON_IIS, 477 .ctrlbit = S3C2412_CLKCON_IIS,
494 }, { 478 }, {
495 .name = "spi", 479 .name = "spi",
496 .id = -1,
497 .parent = &clk_p, 480 .parent = &clk_p,
498 .enable = s3c2412_clkcon_enable, 481 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_SPI, 482 .ctrlbit = S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
503static struct clk init_clocks[] = { 486static struct clk init_clocks[] = {
504 { 487 {
505 .name = "dma", 488 .name = "dma",
506 .id = 0,
507 .parent = &clk_h, 489 .parent = &clk_h,
508 .enable = s3c2412_clkcon_enable, 490 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_DMA0, 491 .ctrlbit = S3C2412_CLKCON_DMA0,
510 }, { 492 }, {
511 .name = "dma", 493 .name = "dma",
512 .id = 1,
513 .parent = &clk_h, 494 .parent = &clk_h,
514 .enable = s3c2412_clkcon_enable, 495 .enable = s3c2412_clkcon_enable,
515 .ctrlbit = S3C2412_CLKCON_DMA1, 496 .ctrlbit = S3C2412_CLKCON_DMA1,
516 }, { 497 }, {
517 .name = "dma", 498 .name = "dma",
518 .id = 2,
519 .parent = &clk_h, 499 .parent = &clk_h,
520 .enable = s3c2412_clkcon_enable, 500 .enable = s3c2412_clkcon_enable,
521 .ctrlbit = S3C2412_CLKCON_DMA2, 501 .ctrlbit = S3C2412_CLKCON_DMA2,
522 }, { 502 }, {
523 .name = "dma", 503 .name = "dma",
524 .id = 3,
525 .parent = &clk_h, 504 .parent = &clk_h,
526 .enable = s3c2412_clkcon_enable, 505 .enable = s3c2412_clkcon_enable,
527 .ctrlbit = S3C2412_CLKCON_DMA3, 506 .ctrlbit = S3C2412_CLKCON_DMA3,
528 }, { 507 }, {
529 .name = "lcd", 508 .name = "lcd",
530 .id = -1,
531 .parent = &clk_h, 509 .parent = &clk_h,
532 .enable = s3c2412_clkcon_enable, 510 .enable = s3c2412_clkcon_enable,
533 .ctrlbit = S3C2412_CLKCON_LCDC, 511 .ctrlbit = S3C2412_CLKCON_LCDC,
534 }, { 512 }, {
535 .name = "gpio", 513 .name = "gpio",
536 .id = -1,
537 .parent = &clk_p, 514 .parent = &clk_p,
538 .enable = s3c2412_clkcon_enable, 515 .enable = s3c2412_clkcon_enable,
539 .ctrlbit = S3C2412_CLKCON_GPIO, 516 .ctrlbit = S3C2412_CLKCON_GPIO,
540 }, { 517 }, {
541 .name = "usb-host", 518 .name = "usb-host",
542 .id = -1,
543 .parent = &clk_h, 519 .parent = &clk_h,
544 .enable = s3c2412_clkcon_enable, 520 .enable = s3c2412_clkcon_enable,
545 .ctrlbit = S3C2412_CLKCON_USBH, 521 .ctrlbit = S3C2412_CLKCON_USBH,
546 }, { 522 }, {
547 .name = "usb-device", 523 .name = "usb-device",
548 .id = -1,
549 .parent = &clk_h, 524 .parent = &clk_h,
550 .enable = s3c2412_clkcon_enable, 525 .enable = s3c2412_clkcon_enable,
551 .ctrlbit = S3C2412_CLKCON_USBD, 526 .ctrlbit = S3C2412_CLKCON_USBD,
552 }, { 527 }, {
553 .name = "timers", 528 .name = "timers",
554 .id = -1,
555 .parent = &clk_p, 529 .parent = &clk_p,
556 .enable = s3c2412_clkcon_enable, 530 .enable = s3c2412_clkcon_enable,
557 .ctrlbit = S3C2412_CLKCON_PWMT, 531 .ctrlbit = S3C2412_CLKCON_PWMT,
558 }, { 532 }, {
559 .name = "uart", 533 .name = "uart",
560 .id = 0, 534 .devname = "s3c2412-uart.0",
561 .parent = &clk_p, 535 .parent = &clk_p,
562 .enable = s3c2412_clkcon_enable, 536 .enable = s3c2412_clkcon_enable,
563 .ctrlbit = S3C2412_CLKCON_UART0, 537 .ctrlbit = S3C2412_CLKCON_UART0,
564 }, { 538 }, {
565 .name = "uart", 539 .name = "uart",
566 .id = 1, 540 .devname = "s3c2412-uart.1",
567 .parent = &clk_p, 541 .parent = &clk_p,
568 .enable = s3c2412_clkcon_enable, 542 .enable = s3c2412_clkcon_enable,
569 .ctrlbit = S3C2412_CLKCON_UART1, 543 .ctrlbit = S3C2412_CLKCON_UART1,
570 }, { 544 }, {
571 .name = "uart", 545 .name = "uart",
572 .id = 2, 546 .devname = "s3c2412-uart.2",
573 .parent = &clk_p, 547 .parent = &clk_p,
574 .enable = s3c2412_clkcon_enable, 548 .enable = s3c2412_clkcon_enable,
575 .ctrlbit = S3C2412_CLKCON_UART2, 549 .ctrlbit = S3C2412_CLKCON_UART2,
576 }, { 550 }, {
577 .name = "rtc", 551 .name = "rtc",
578 .id = -1,
579 .parent = &clk_p, 552 .parent = &clk_p,
580 .enable = s3c2412_clkcon_enable, 553 .enable = s3c2412_clkcon_enable,
581 .ctrlbit = S3C2412_CLKCON_RTC, 554 .ctrlbit = S3C2412_CLKCON_RTC,
582 }, { 555 }, {
583 .name = "watchdog", 556 .name = "watchdog",
584 .id = -1,
585 .parent = &clk_p, 557 .parent = &clk_p,
586 .ctrlbit = 0, 558 .ctrlbit = 0,
587 }, { 559 }, {
588 .name = "usb-bus-gadget", 560 .name = "usb-bus-gadget",
589 .id = -1,
590 .parent = &clk_usb_bus, 561 .parent = &clk_usb_bus,
591 .enable = s3c2412_clkcon_enable, 562 .enable = s3c2412_clkcon_enable,
592 .ctrlbit = S3C2412_CLKCON_USB_DEV48, 563 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
593 }, { 564 }, {
594 .name = "usb-bus-host", 565 .name = "usb-bus-host",
595 .id = -1,
596 .parent = &clk_usb_bus, 566 .parent = &clk_usb_bus,
597 .enable = s3c2412_clkcon_enable, 567 .enable = s3c2412_clkcon_enable,
598 .ctrlbit = S3C2412_CLKCON_USB_HOST48, 568 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 3b02d8506e25..21a5e81f0ab5 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
42 [0] = { 42 [0] = {
43 .clk = { 43 .clk = {
44 .name = "hsmmc-div", 44 .name = "hsmmc-div",
45 .id = 0, 45 .devname = "s3c-sdhci.0",
46 .parent = &clk_esysclk.clk, 46 .parent = &clk_esysclk.clk,
47 }, 47 },
48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, 48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
50 [1] = { 50 [1] = {
51 .clk = { 51 .clk = {
52 .name = "hsmmc-div", 52 .name = "hsmmc-div",
53 .id = 1, 53 .devname = "s3c-sdhci.1",
54 .parent = &clk_esysclk.clk, 54 .parent = &clk_esysclk.clk,
55 }, 55 },
56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, 56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
60static struct clksrc_clk hsmmc_mux[] = { 60static struct clksrc_clk hsmmc_mux[] = {
61 [0] = { 61 [0] = {
62 .clk = { 62 .clk = {
63 .id = 0,
64 .name = "hsmmc-if", 63 .name = "hsmmc-if",
64 .devname = "s3c-sdhci.0",
65 .ctrlbit = (1 << 6), 65 .ctrlbit = (1 << 6),
66 .enable = s3c2443_clkcon_enable_s, 66 .enable = s3c2443_clkcon_enable_s,
67 }, 67 },
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
76 }, 76 },
77 [1] = { 77 [1] = {
78 .clk = { 78 .clk = {
79 .id = 1,
80 .name = "hsmmc-if", 79 .name = "hsmmc-if",
80 .devname = "s3c-sdhci.1",
81 .ctrlbit = (1 << 12), 81 .ctrlbit = (1 << 12),
82 .enable = s3c2443_clkcon_enable_s, 82 .enable = s3c2443_clkcon_enable_s,
83 }, 83 },
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
94 94
95static struct clk hsmmc0_clk = { 95static struct clk hsmmc0_clk = {
96 .name = "hsmmc", 96 .name = "hsmmc",
97 .id = 0, 97 .devname = "s3c-sdhci.0",
98 .parent = &clk_h, 98 .parent = &clk_h,
99 .enable = s3c2443_clkcon_enable_h, 99 .enable = s3c2443_clkcon_enable_h,
100 .ctrlbit = S3C2416_HCLKCON_HSMMC0, 100 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 3dc2426e2345..554e0d3ec70b 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
90 90
91static struct clk s3c2440_clk_cam = { 91static struct clk s3c2440_clk_cam = {
92 .name = "camif", 92 .name = "camif",
93 .id = -1,
94 .enable = s3c2410_clkcon_enable, 93 .enable = s3c2410_clkcon_enable,
95 .ctrlbit = S3C2440_CLKCON_CAMERA, 94 .ctrlbit = S3C2440_CLKCON_CAMERA,
96}; 95};
97 96
98static struct clk s3c2440_clk_cam_upll = { 97static struct clk s3c2440_clk_cam_upll = {
99 .name = "camif-upll", 98 .name = "camif-upll",
100 .id = -1,
101 .ops = &(struct clk_ops) { 99 .ops = &(struct clk_ops) {
102 .set_rate = s3c2440_camif_upll_setrate, 100 .set_rate = s3c2440_camif_upll_setrate,
103 .round_rate = s3c2440_camif_upll_round, 101 .round_rate = s3c2440_camif_upll_round,
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
106 104
107static struct clk s3c2440_clk_ac97 = { 105static struct clk s3c2440_clk_ac97 = {
108 .name = "ac97", 106 .name = "ac97",
109 .id = -1,
110 .enable = s3c2410_clkcon_enable, 107 .enable = s3c2410_clkcon_enable,
111 .ctrlbit = S3C2440_CLKCON_CAMERA, 108 .ctrlbit = S3C2440_CLKCON_CAMERA,
112}; 109};
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index f4ec6d5715c8..a1a7176675b9 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -59,7 +59,6 @@
59 59
60static struct clk clk_i2s_ext = { 60static struct clk clk_i2s_ext = {
61 .name = "i2s-ext", 61 .name = "i2s-ext",
62 .id = -1,
63}; 62};
64 63
65/* armdiv 64/* armdiv
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
139 138
140static struct clk clk_armdiv = { 139static struct clk clk_armdiv = {
141 .name = "armdiv", 140 .name = "armdiv",
142 .id = -1,
143 .parent = &clk_msysclk.clk, 141 .parent = &clk_msysclk.clk,
144 .ops = &(struct clk_ops) { 142 .ops = &(struct clk_ops) {
145 .round_rate = s3c2443_armclk_roundrate, 143 .round_rate = s3c2443_armclk_roundrate,
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
160static struct clksrc_clk clk_arm = { 158static struct clksrc_clk clk_arm = {
161 .clk = { 159 .clk = {
162 .name = "armclk", 160 .name = "armclk",
163 .id = -1,
164 }, 161 },
165 .sources = &(struct clksrc_sources) { 162 .sources = &(struct clksrc_sources) {
166 .sources = clk_arm_sources, 163 .sources = clk_arm_sources,
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
177static struct clksrc_clk clk_hsspi = { 174static struct clksrc_clk clk_hsspi = {
178 .clk = { 175 .clk = {
179 .name = "hsspi", 176 .name = "hsspi",
180 .id = -1,
181 .parent = &clk_esysclk.clk, 177 .parent = &clk_esysclk.clk,
182 .ctrlbit = S3C2443_SCLKCON_HSSPICLK, 178 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
183 .enable = s3c2443_clkcon_enable_s, 179 .enable = s3c2443_clkcon_enable_s,
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
196static struct clksrc_clk clk_hsmmc_div = { 192static struct clksrc_clk clk_hsmmc_div = {
197 .clk = { 193 .clk = {
198 .name = "hsmmc-div", 194 .name = "hsmmc-div",
199 .id = 1, 195 .devname = "s3c-sdhci.1",
200 .parent = &clk_esysclk.clk, 196 .parent = &clk_esysclk.clk,
201 }, 197 },
202 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, 198 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
231 227
232static struct clk clk_hsmmc = { 228static struct clk clk_hsmmc = {
233 .name = "hsmmc-if", 229 .name = "hsmmc-if",
234 .id = 1, 230 .devname = "s3c-sdhci.1",
235 .parent = &clk_hsmmc_div.clk, 231 .parent = &clk_hsmmc_div.clk,
236 .enable = s3c2443_enable_hsmmc, 232 .enable = s3c2443_enable_hsmmc,
237 .ops = &(struct clk_ops) { 233 .ops = &(struct clk_ops) {
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
248static struct clksrc_clk clk_i2s_eplldiv = { 244static struct clksrc_clk clk_i2s_eplldiv = {
249 .clk = { 245 .clk = {
250 .name = "i2s-eplldiv", 246 .name = "i2s-eplldiv",
251 .id = -1,
252 .parent = &clk_esysclk.clk, 247 .parent = &clk_esysclk.clk,
253 }, 248 },
254 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, 249 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
271static struct clksrc_clk clk_i2s = { 266static struct clksrc_clk clk_i2s = {
272 .clk = { 267 .clk = {
273 .name = "i2s-if", 268 .name = "i2s-if",
274 .id = -1,
275 .ctrlbit = S3C2443_SCLKCON_I2SCLK, 269 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
276 .enable = s3c2443_clkcon_enable_s, 270 .enable = s3c2443_clkcon_enable_s,
277 271
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
288static struct clk init_clocks_off[] = { 282static struct clk init_clocks_off[] = {
289 { 283 {
290 .name = "sdi", 284 .name = "sdi",
291 .id = -1,
292 .parent = &clk_p, 285 .parent = &clk_p,
293 .enable = s3c2443_clkcon_enable_p, 286 .enable = s3c2443_clkcon_enable_p,
294 .ctrlbit = S3C2443_PCLKCON_SDI, 287 .ctrlbit = S3C2443_PCLKCON_SDI,
295 }, { 288 }, {
296 .name = "iis", 289 .name = "iis",
297 .id = -1,
298 .parent = &clk_p, 290 .parent = &clk_p,
299 .enable = s3c2443_clkcon_enable_p, 291 .enable = s3c2443_clkcon_enable_p,
300 .ctrlbit = S3C2443_PCLKCON_IIS, 292 .ctrlbit = S3C2443_PCLKCON_IIS,
301 }, { 293 }, {
302 .name = "spi", 294 .name = "spi",
303 .id = 0, 295 .devname = "s3c2410-spi.0",
304 .parent = &clk_p, 296 .parent = &clk_p,
305 .enable = s3c2443_clkcon_enable_p, 297 .enable = s3c2443_clkcon_enable_p,
306 .ctrlbit = S3C2443_PCLKCON_SPI0, 298 .ctrlbit = S3C2443_PCLKCON_SPI0,
307 }, { 299 }, {
308 .name = "spi", 300 .name = "spi",
309 .id = 1, 301 .devname = "s3c2410-spi.1",
310 .parent = &clk_p, 302 .parent = &clk_p,
311 .enable = s3c2443_clkcon_enable_p, 303 .enable = s3c2443_clkcon_enable_p,
312 .ctrlbit = S3C2443_PCLKCON_SPI1, 304 .ctrlbit = S3C2443_PCLKCON_SPI1,
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5e37a1..8cf39e33579e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -39,7 +39,6 @@
39 39
40static struct clk clk_ext_xtal_mux = { 40static struct clk clk_ext_xtal_mux = {
41 .name = "ext_xtal", 41 .name = "ext_xtal",
42 .id = -1,
43}; 42};
44 43
45#define clk_fin_apll clk_ext_xtal_mux 44#define clk_fin_apll clk_ext_xtal_mux
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
51 50
52struct clk clk_h2 = { 51struct clk clk_h2 = {
53 .name = "hclk2", 52 .name = "hclk2",
54 .id = -1,
55 .rate = 0, 53 .rate = 0,
56}; 54};
57 55
58struct clk clk_27m = { 56struct clk clk_27m = {
59 .name = "clk_27m", 57 .name = "clk_27m",
60 .id = -1,
61 .rate = 27000000, 58 .rate = 27000000,
62}; 59};
63 60
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
83 80
84struct clk clk_48m = { 81struct clk clk_48m = {
85 .name = "clk_48m", 82 .name = "clk_48m",
86 .id = -1,
87 .rate = 48000000, 83 .rate = 48000000,
88 .enable = clk_48m_ctrl, 84 .enable = clk_48m_ctrl,
89}; 85};
90 86
91struct clk clk_xusbxti = { 87struct clk clk_xusbxti = {
92 .name = "xusbxti", 88 .name = "xusbxti",
93 .id = -1,
94 .rate = 48000000, 89 .rate = 48000000,
95}; 90};
96 91
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
130static struct clk init_clocks_off[] = { 125static struct clk init_clocks_off[] = {
131 { 126 {
132 .name = "nand", 127 .name = "nand",
133 .id = -1,
134 .parent = &clk_h, 128 .parent = &clk_h,
135 }, { 129 }, {
136 .name = "rtc", 130 .name = "rtc",
137 .id = -1,
138 .parent = &clk_p, 131 .parent = &clk_p,
139 .enable = s3c64xx_pclk_ctrl, 132 .enable = s3c64xx_pclk_ctrl,
140 .ctrlbit = S3C_CLKCON_PCLK_RTC, 133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
141 }, { 134 }, {
142 .name = "adc", 135 .name = "adc",
143 .id = -1,
144 .parent = &clk_p, 136 .parent = &clk_p,
145 .enable = s3c64xx_pclk_ctrl, 137 .enable = s3c64xx_pclk_ctrl,
146 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
147 }, { 139 }, {
148 .name = "i2c", 140 .name = "i2c",
149 .id = -1,
150 .parent = &clk_p, 141 .parent = &clk_p,
151 .enable = s3c64xx_pclk_ctrl, 142 .enable = s3c64xx_pclk_ctrl,
152 .ctrlbit = S3C_CLKCON_PCLK_IIC, 143 .ctrlbit = S3C_CLKCON_PCLK_IIC,
153 }, { 144 }, {
154 .name = "i2c", 145 .name = "i2c",
155 .id = 1, 146 .devname = "s3c2440-i2c.1",
156 .parent = &clk_p, 147 .parent = &clk_p,
157 .enable = s3c64xx_pclk_ctrl, 148 .enable = s3c64xx_pclk_ctrl,
158 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, 149 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
159 }, { 150 }, {
160 .name = "iis", 151 .name = "iis",
161 .id = 0, 152 .devname = "samsung-i2s.0",
162 .parent = &clk_p, 153 .parent = &clk_p,
163 .enable = s3c64xx_pclk_ctrl, 154 .enable = s3c64xx_pclk_ctrl,
164 .ctrlbit = S3C_CLKCON_PCLK_IIS0, 155 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
165 }, { 156 }, {
166 .name = "iis", 157 .name = "iis",
167 .id = 1, 158 .devname = "samsung-i2s.1",
168 .parent = &clk_p, 159 .parent = &clk_p,
169 .enable = s3c64xx_pclk_ctrl, 160 .enable = s3c64xx_pclk_ctrl,
170 .ctrlbit = S3C_CLKCON_PCLK_IIS1, 161 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
171 }, { 162 }, {
172#ifdef CONFIG_CPU_S3C6410 163#ifdef CONFIG_CPU_S3C6410
173 .name = "iis", 164 .name = "iis",
174 .id = -1, /* There's only one IISv4 port */
175 .parent = &clk_p, 165 .parent = &clk_p,
176 .enable = s3c64xx_pclk_ctrl, 166 .enable = s3c64xx_pclk_ctrl,
177 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, 167 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
178 }, { 168 }, {
179#endif 169#endif
180 .name = "keypad", 170 .name = "keypad",
181 .id = -1,
182 .parent = &clk_p, 171 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 172 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 173 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
185 }, { 174 }, {
186 .name = "spi", 175 .name = "spi",
187 .id = 0, 176 .devname = "s3c64xx-spi.0",
188 .parent = &clk_p, 177 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 178 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 179 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
191 }, { 180 }, {
192 .name = "spi", 181 .name = "spi",
193 .id = 1, 182 .devname = "s3c64xx-spi.1",
194 .parent = &clk_p, 183 .parent = &clk_p,
195 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
196 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
197 }, { 186 }, {
198 .name = "spi_48m", 187 .name = "spi_48m",
199 .id = 0, 188 .devname = "s3c64xx-spi.0",
200 .parent = &clk_48m, 189 .parent = &clk_48m,
201 .enable = s3c64xx_sclk_ctrl, 190 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
203 }, { 192 }, {
204 .name = "spi_48m", 193 .name = "spi_48m",
205 .id = 1, 194 .devname = "s3c64xx-spi.1",
206 .parent = &clk_48m, 195 .parent = &clk_48m,
207 .enable = s3c64xx_sclk_ctrl, 196 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
209 }, { 198 }, {
210 .name = "48m", 199 .name = "48m",
211 .id = 0, 200 .devname = "s3c-sdhci.0",
212 .parent = &clk_48m, 201 .parent = &clk_48m,
213 .enable = s3c64xx_sclk_ctrl, 202 .enable = s3c64xx_sclk_ctrl,
214 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, 203 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
215 }, { 204 }, {
216 .name = "48m", 205 .name = "48m",
217 .id = 1, 206 .devname = "s3c-sdhci.1",
218 .parent = &clk_48m, 207 .parent = &clk_48m,
219 .enable = s3c64xx_sclk_ctrl, 208 .enable = s3c64xx_sclk_ctrl,
220 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, 209 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
221 }, { 210 }, {
222 .name = "48m", 211 .name = "48m",
223 .id = 2, 212 .devname = "s3c-sdhci.2",
224 .parent = &clk_48m, 213 .parent = &clk_48m,
225 .enable = s3c64xx_sclk_ctrl, 214 .enable = s3c64xx_sclk_ctrl,
226 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, 215 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
227 }, { 216 }, {
228 .name = "dma0", 217 .name = "dma0",
229 .id = -1,
230 .parent = &clk_h, 218 .parent = &clk_h,
231 .enable = s3c64xx_hclk_ctrl, 219 .enable = s3c64xx_hclk_ctrl,
232 .ctrlbit = S3C_CLKCON_HCLK_DMA0, 220 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
233 }, { 221 }, {
234 .name = "dma1", 222 .name = "dma1",
235 .id = -1,
236 .parent = &clk_h, 223 .parent = &clk_h,
237 .enable = s3c64xx_hclk_ctrl, 224 .enable = s3c64xx_hclk_ctrl,
238 .ctrlbit = S3C_CLKCON_HCLK_DMA1, 225 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
242static struct clk init_clocks[] = { 229static struct clk init_clocks[] = {
243 { 230 {
244 .name = "lcd", 231 .name = "lcd",
245 .id = -1,
246 .parent = &clk_h, 232 .parent = &clk_h,
247 .enable = s3c64xx_hclk_ctrl, 233 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_LCD, 234 .ctrlbit = S3C_CLKCON_HCLK_LCD,
249 }, { 235 }, {
250 .name = "gpio", 236 .name = "gpio",
251 .id = -1,
252 .parent = &clk_p, 237 .parent = &clk_p,
253 .enable = s3c64xx_pclk_ctrl, 238 .enable = s3c64xx_pclk_ctrl,
254 .ctrlbit = S3C_CLKCON_PCLK_GPIO, 239 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
255 }, { 240 }, {
256 .name = "usb-host", 241 .name = "usb-host",
257 .id = -1,
258 .parent = &clk_h, 242 .parent = &clk_h,
259 .enable = s3c64xx_hclk_ctrl, 243 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 244 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
261 }, { 245 }, {
262 .name = "hsmmc", 246 .name = "hsmmc",
263 .id = 0, 247 .devname = "s3c-sdhci.0",
264 .parent = &clk_h, 248 .parent = &clk_h,
265 .enable = s3c64xx_hclk_ctrl, 249 .enable = s3c64xx_hclk_ctrl,
266 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, 250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
267 }, { 251 }, {
268 .name = "hsmmc", 252 .name = "hsmmc",
269 .id = 1, 253 .devname = "s3c-sdhci.1",
270 .parent = &clk_h, 254 .parent = &clk_h,
271 .enable = s3c64xx_hclk_ctrl, 255 .enable = s3c64xx_hclk_ctrl,
272 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, 256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
273 }, { 257 }, {
274 .name = "hsmmc", 258 .name = "hsmmc",
275 .id = 2, 259 .devname = "s3c-sdhci.2",
276 .parent = &clk_h, 260 .parent = &clk_h,
277 .enable = s3c64xx_hclk_ctrl, 261 .enable = s3c64xx_hclk_ctrl,
278 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, 262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
279 }, { 263 }, {
280 .name = "otg", 264 .name = "otg",
281 .id = -1,
282 .parent = &clk_h, 265 .parent = &clk_h,
283 .enable = s3c64xx_hclk_ctrl, 266 .enable = s3c64xx_hclk_ctrl,
284 .ctrlbit = S3C_CLKCON_HCLK_USB, 267 .ctrlbit = S3C_CLKCON_HCLK_USB,
285 }, { 268 }, {
286 .name = "timers", 269 .name = "timers",
287 .id = -1,
288 .parent = &clk_p, 270 .parent = &clk_p,
289 .enable = s3c64xx_pclk_ctrl, 271 .enable = s3c64xx_pclk_ctrl,
290 .ctrlbit = S3C_CLKCON_PCLK_PWM, 272 .ctrlbit = S3C_CLKCON_PCLK_PWM,
291 }, { 273 }, {
292 .name = "uart", 274 .name = "uart",
293 .id = 0, 275 .devname = "s3c6400-uart.0",
294 .parent = &clk_p, 276 .parent = &clk_p,
295 .enable = s3c64xx_pclk_ctrl, 277 .enable = s3c64xx_pclk_ctrl,
296 .ctrlbit = S3C_CLKCON_PCLK_UART0, 278 .ctrlbit = S3C_CLKCON_PCLK_UART0,
297 }, { 279 }, {
298 .name = "uart", 280 .name = "uart",
299 .id = 1, 281 .devname = "s3c6400-uart.1",
300 .parent = &clk_p, 282 .parent = &clk_p,
301 .enable = s3c64xx_pclk_ctrl, 283 .enable = s3c64xx_pclk_ctrl,
302 .ctrlbit = S3C_CLKCON_PCLK_UART1, 284 .ctrlbit = S3C_CLKCON_PCLK_UART1,
303 }, { 285 }, {
304 .name = "uart", 286 .name = "uart",
305 .id = 2, 287 .devname = "s3c6400-uart.2",
306 .parent = &clk_p, 288 .parent = &clk_p,
307 .enable = s3c64xx_pclk_ctrl, 289 .enable = s3c64xx_pclk_ctrl,
308 .ctrlbit = S3C_CLKCON_PCLK_UART2, 290 .ctrlbit = S3C_CLKCON_PCLK_UART2,
309 }, { 291 }, {
310 .name = "uart", 292 .name = "uart",
311 .id = 3, 293 .devname = "s3c6400-uart.3",
312 .parent = &clk_p, 294 .parent = &clk_p,
313 .enable = s3c64xx_pclk_ctrl, 295 .enable = s3c64xx_pclk_ctrl,
314 .ctrlbit = S3C_CLKCON_PCLK_UART3, 296 .ctrlbit = S3C_CLKCON_PCLK_UART3,
315 }, { 297 }, {
316 .name = "watchdog", 298 .name = "watchdog",
317 .id = -1,
318 .parent = &clk_p, 299 .parent = &clk_p,
319 .ctrlbit = S3C_CLKCON_PCLK_WDT, 300 .ctrlbit = S3C_CLKCON_PCLK_WDT,
320 }, { 301 }, {
321 .name = "ac97", 302 .name = "ac97",
322 .id = -1,
323 .parent = &clk_p, 303 .parent = &clk_p,
324 .ctrlbit = S3C_CLKCON_PCLK_AC97, 304 .ctrlbit = S3C_CLKCON_PCLK_AC97,
325 }, { 305 }, {
326 .name = "cfcon", 306 .name = "cfcon",
327 .id = -1,
328 .parent = &clk_h, 307 .parent = &clk_h,
329 .enable = s3c64xx_hclk_ctrl, 308 .enable = s3c64xx_hclk_ctrl,
330 .ctrlbit = S3C_CLKCON_HCLK_IHOST, 309 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
334 313
335static struct clk clk_fout_apll = { 314static struct clk clk_fout_apll = {
336 .name = "fout_apll", 315 .name = "fout_apll",
337 .id = -1,
338}; 316};
339 317
340static struct clk *clk_src_apll_list[] = { 318static struct clk *clk_src_apll_list[] = {
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
350static struct clksrc_clk clk_mout_apll = { 328static struct clksrc_clk clk_mout_apll = {
351 .clk = { 329 .clk = {
352 .name = "mout_apll", 330 .name = "mout_apll",
353 .id = -1,
354 }, 331 },
355 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, 332 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
356 .sources = &clk_src_apll, 333 .sources = &clk_src_apll,
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
369static struct clksrc_clk clk_mout_epll = { 346static struct clksrc_clk clk_mout_epll = {
370 .clk = { 347 .clk = {
371 .name = "mout_epll", 348 .name = "mout_epll",
372 .id = -1,
373 }, 349 },
374 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, 350 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
375 .sources = &clk_src_epll, 351 .sources = &clk_src_epll,
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
388static struct clksrc_clk clk_mout_mpll = { 364static struct clksrc_clk clk_mout_mpll = {
389 .clk = { 365 .clk = {
390 .name = "mout_mpll", 366 .name = "mout_mpll",
391 .id = -1,
392 }, 367 },
393 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, 368 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
394 .sources = &clk_src_mpll, 369 .sources = &clk_src_mpll,
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
446 421
447static struct clk clk_arm = { 422static struct clk clk_arm = {
448 .name = "armclk", 423 .name = "armclk",
449 .id = -1,
450 .parent = &clk_mout_apll.clk, 424 .parent = &clk_mout_apll.clk,
451 .ops = &(struct clk_ops) { 425 .ops = &(struct clk_ops) {
452 .get_rate = s3c64xx_clk_arm_get_rate, 426 .get_rate = s3c64xx_clk_arm_get_rate,
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
473 447
474static struct clk clk_dout_mpll = { 448static struct clk clk_dout_mpll = {
475 .name = "dout_mpll", 449 .name = "dout_mpll",
476 .id = -1,
477 .parent = &clk_mout_mpll.clk, 450 .parent = &clk_mout_mpll.clk,
478 .ops = &clk_dout_ops, 451 .ops = &clk_dout_ops,
479}; 452};
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
540 513
541static struct clk clk_iis_cd0 = { 514static struct clk clk_iis_cd0 = {
542 .name = "iis_cdclk0", 515 .name = "iis_cdclk0",
543 .id = -1,
544}; 516};
545 517
546static struct clk clk_iis_cd1 = { 518static struct clk clk_iis_cd1 = {
547 .name = "iis_cdclk1", 519 .name = "iis_cdclk1",
548 .id = -1,
549}; 520};
550 521
551static struct clk clk_iisv4_cd = { 522static struct clk clk_iisv4_cd = {
552 .name = "iis_cdclk_v4", 523 .name = "iis_cdclk_v4",
553 .id = -1,
554}; 524};
555 525
556static struct clk clk_pcm_cd = { 526static struct clk clk_pcm_cd = {
557 .name = "pcm_cdclk", 527 .name = "pcm_cdclk",
558 .id = -1,
559}; 528};
560 529
561static struct clk *clkset_audio0_list[] = { 530static struct clk *clkset_audio0_list[] = {
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
610 { 579 {
611 .clk = { 580 .clk = {
612 .name = "mmc_bus", 581 .name = "mmc_bus",
613 .id = 0, 582 .devname = "s3c-sdhci.0",
614 .ctrlbit = S3C_CLKCON_SCLK_MMC0, 583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
615 .enable = s3c64xx_sclk_ctrl, 584 .enable = s3c64xx_sclk_ctrl,
616 }, 585 },
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
620 }, { 589 }, {
621 .clk = { 590 .clk = {
622 .name = "mmc_bus", 591 .name = "mmc_bus",
623 .id = 1, 592 .devname = "s3c-sdhci.1",
624 .ctrlbit = S3C_CLKCON_SCLK_MMC1, 593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
625 .enable = s3c64xx_sclk_ctrl, 594 .enable = s3c64xx_sclk_ctrl,
626 }, 595 },
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
630 }, { 599 }, {
631 .clk = { 600 .clk = {
632 .name = "mmc_bus", 601 .name = "mmc_bus",
633 .id = 2, 602 .devname = "s3c-sdhci.2",
634 .ctrlbit = S3C_CLKCON_SCLK_MMC2, 603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
635 .enable = s3c64xx_sclk_ctrl, 604 .enable = s3c64xx_sclk_ctrl,
636 }, 605 },
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
640 }, { 609 }, {
641 .clk = { 610 .clk = {
642 .name = "usb-bus-host", 611 .name = "usb-bus-host",
643 .id = -1,
644 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 612 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
645 .enable = s3c64xx_sclk_ctrl, 613 .enable = s3c64xx_sclk_ctrl,
646 }, 614 },
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
650 }, { 618 }, {
651 .clk = { 619 .clk = {
652 .name = "uclk1", 620 .name = "uclk1",
653 .id = -1,
654 .ctrlbit = S3C_CLKCON_SCLK_UART, 621 .ctrlbit = S3C_CLKCON_SCLK_UART,
655 .enable = s3c64xx_sclk_ctrl, 622 .enable = s3c64xx_sclk_ctrl,
656 }, 623 },
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
661/* Where does UCLK0 come from? */ 628/* Where does UCLK0 come from? */
662 .clk = { 629 .clk = {
663 .name = "spi-bus", 630 .name = "spi-bus",
664 .id = 0, 631 .devname = "s3c64xx-spi.0",
665 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 632 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
666 .enable = s3c64xx_sclk_ctrl, 633 .enable = s3c64xx_sclk_ctrl,
667 }, 634 },
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
671 }, { 638 }, {
672 .clk = { 639 .clk = {
673 .name = "spi-bus", 640 .name = "spi-bus",
674 .id = 1, 641 .devname = "s3c64xx-spi.1",
675 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
676 .enable = s3c64xx_sclk_ctrl, 642 .enable = s3c64xx_sclk_ctrl,
677 }, 643 },
678 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, 644 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
681 }, { 647 }, {
682 .clk = { 648 .clk = {
683 .name = "audio-bus", 649 .name = "audio-bus",
684 .id = 0, 650 .devname = "samsung-i2s.0",
685 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 651 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
686 .enable = s3c64xx_sclk_ctrl, 652 .enable = s3c64xx_sclk_ctrl,
687 }, 653 },
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
691 }, { 657 }, {
692 .clk = { 658 .clk = {
693 .name = "audio-bus", 659 .name = "audio-bus",
694 .id = 1, 660 .devname = "samsung-i2s.1",
695 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, 661 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
696 .enable = s3c64xx_sclk_ctrl, 662 .enable = s3c64xx_sclk_ctrl,
697 }, 663 },
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
701 }, { 667 }, {
702 .clk = { 668 .clk = {
703 .name = "audio-bus", 669 .name = "audio-bus",
704 .id = 2, 670 .devname = "samsung-i2s.2",
705 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, 671 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
706 .enable = s3c64xx_sclk_ctrl, 672 .enable = s3c64xx_sclk_ctrl,
707 }, 673 },
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
711 }, { 677 }, {
712 .clk = { 678 .clk = {
713 .name = "irda-bus", 679 .name = "irda-bus",
714 .id = 0,
715 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 680 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
716 .enable = s3c64xx_sclk_ctrl, 681 .enable = s3c64xx_sclk_ctrl,
717 }, 682 },
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
721 }, { 686 }, {
722 .clk = { 687 .clk = {
723 .name = "camera", 688 .name = "camera",
724 .id = -1,
725 .ctrlbit = S3C_CLKCON_SCLK_CAM, 689 .ctrlbit = S3C_CLKCON_SCLK_CAM,
726 .enable = s3c64xx_sclk_ctrl, 690 .enable = s3c64xx_sclk_ctrl,
727 }, 691 },
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 8e2df26cf14a..bf7cc82ea6d0 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -215,6 +215,7 @@
215/* Compatibility */ 215/* Compatibility */
216 216
217#define IRQ_ONENAND IRQ_ONENAND0 217#define IRQ_ONENAND IRQ_ONENAND0
218#define IRQ_I2S0 IRQ_S3C6410_IIS
218 219
219#endif /* __ASM_MACH_S3C64XX_IRQS_H */ 220#endif /* __ASM_MACH_S3C64XX_IRQS_H */
220 221
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 1e9f20f0bb7b..38659bebe4b1 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
53 * the IRQ wake controls depending on the CPU we are running on */ 53 * the IRQ wake controls depending on the CPU we are running on */
54 54
55#define s3c_irqwake_eintallow ((1 << 28) - 1) 55#define s3c_irqwake_eintallow ((1 << 28) - 1)
56#define s3c_irqwake_intallow (0) 56#define s3c_irqwake_intallow (~0)
57 57
58static inline void s3c_pm_arch_update_uart(void __iomem *regs, 58static inline void s3c_pm_arch_update_uart(void __iomem *regs,
59 struct pm_uart_save *save) 59 struct pm_uart_save *save)
@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
96 save->ucon = new_ucon; 96 save->ucon = new_ucon;
97 } 97 }
98} 98}
99
100static inline void s3c_pm_restored_gpios(void)
101{
102 /* ensure sleep mode has been cleared from the system */
103
104 __raw_writel(0, S3C64XX_SLPEN);
105}
106
107static inline void s3c_pm_saved_gpios(void)
108{
109 /* turn on the sleep mode and keep it there, as it seems that during
110 * suspend the xCON registers get re-set and thus you can end up with
111 * problems between going to sleep and resuming.
112 */
113
114 __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
115}
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 97660c8141ae..75d9a0e49193 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
48 }, 48 },
49}; 49};
50 50
51/* setup the sources the vic should advertise resume for, even though it
52 * is not doing the wake (set_irq_wake needs to be valid) */
53#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
54#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
55 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
56 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
57 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
58 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
51 59
52void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) 60void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
53{ 61{
54 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 62 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
55 63
56 /* initialise the pair of VICs */ 64 /* initialise the pair of VICs */
57 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); 65 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
58 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); 66 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
59 67
60 /* add the timer sub-irqs */ 68 /* add the timer sub-irqs */
61 s3c_init_vic_timer_irq(5, IRQ_TIMER0); 69 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index ae6bf6feba89..5f6afdf067ed 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -13,7 +13,7 @@ obj- :=
13# Core support for S5P64X0 system 13# Core support for S5P64X0 system
14 14
15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o 15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o 16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o 17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o 18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
19 19
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2ebf416..0e9cd3092dd2 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
95static struct clksrc_clk clk_hclk = { 95static struct clksrc_clk clk_hclk = {
96 .clk = { 96 .clk = {
97 .name = "clk_hclk", 97 .name = "clk_hclk",
98 .id = -1,
99 .parent = &clk_armclk.clk, 98 .parent = &clk_armclk.clk,
100 }, 99 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, 100 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
104static struct clksrc_clk clk_pclk = { 103static struct clksrc_clk clk_pclk = {
105 .clk = { 104 .clk = {
106 .name = "clk_pclk", 105 .name = "clk_pclk",
107 .id = -1,
108 .parent = &clk_hclk.clk, 106 .parent = &clk_hclk.clk,
109 }, 107 },
110 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, 108 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
112static struct clksrc_clk clk_hclk_low = { 110static struct clksrc_clk clk_hclk_low = {
113 .clk = { 111 .clk = {
114 .name = "clk_hclk_low", 112 .name = "clk_hclk_low",
115 .id = -1,
116 }, 113 },
117 .sources = &clkset_hclk_low, 114 .sources = &clkset_hclk_low,
118 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, 115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
122static struct clksrc_clk clk_pclk_low = { 119static struct clksrc_clk clk_pclk_low = {
123 .clk = { 120 .clk = {
124 .name = "clk_pclk_low", 121 .name = "clk_pclk_low",
125 .id = -1,
126 .parent = &clk_hclk_low.clk, 122 .parent = &clk_hclk_low.clk,
127 }, 123 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, 124 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
136static struct clk init_clocks_off[] = { 132static struct clk init_clocks_off[] = {
137 { 133 {
138 .name = "nand", 134 .name = "nand",
139 .id = -1,
140 .parent = &clk_hclk.clk, 135 .parent = &clk_hclk.clk,
141 .enable = s5p64x0_mem_ctrl, 136 .enable = s5p64x0_mem_ctrl,
142 .ctrlbit = (1 << 2), 137 .ctrlbit = (1 << 2),
143 }, { 138 }, {
144 .name = "post", 139 .name = "post",
145 .id = -1,
146 .parent = &clk_hclk_low.clk, 140 .parent = &clk_hclk_low.clk,
147 .enable = s5p64x0_hclk0_ctrl, 141 .enable = s5p64x0_hclk0_ctrl,
148 .ctrlbit = (1 << 5) 142 .ctrlbit = (1 << 5)
149 }, { 143 }, {
150 .name = "2d", 144 .name = "2d",
151 .id = -1,
152 .parent = &clk_hclk.clk, 145 .parent = &clk_hclk.clk,
153 .enable = s5p64x0_hclk0_ctrl, 146 .enable = s5p64x0_hclk0_ctrl,
154 .ctrlbit = (1 << 8), 147 .ctrlbit = (1 << 8),
155 }, { 148 }, {
156 .name = "pdma", 149 .name = "pdma",
157 .id = -1,
158 .parent = &clk_hclk_low.clk, 150 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl, 151 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 12), 152 .ctrlbit = (1 << 12),
161 }, { 153 }, {
162 .name = "hsmmc", 154 .name = "hsmmc",
163 .id = 0, 155 .devname = "s3c-sdhci.0",
164 .parent = &clk_hclk_low.clk, 156 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl, 157 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 17), 158 .ctrlbit = (1 << 17),
167 }, { 159 }, {
168 .name = "hsmmc", 160 .name = "hsmmc",
169 .id = 1, 161 .devname = "s3c-sdhci.1",
170 .parent = &clk_hclk_low.clk, 162 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl, 163 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 18), 164 .ctrlbit = (1 << 18),
173 }, { 165 }, {
174 .name = "hsmmc", 166 .name = "hsmmc",
175 .id = 2, 167 .devname = "s3c-sdhci.2",
176 .parent = &clk_hclk_low.clk, 168 .parent = &clk_hclk_low.clk,
177 .enable = s5p64x0_hclk0_ctrl, 169 .enable = s5p64x0_hclk0_ctrl,
178 .ctrlbit = (1 << 19), 170 .ctrlbit = (1 << 19),
179 }, { 171 }, {
180 .name = "otg", 172 .name = "otg",
181 .id = -1,
182 .parent = &clk_hclk_low.clk, 173 .parent = &clk_hclk_low.clk,
183 .enable = s5p64x0_hclk0_ctrl, 174 .enable = s5p64x0_hclk0_ctrl,
184 .ctrlbit = (1 << 20) 175 .ctrlbit = (1 << 20)
185 }, { 176 }, {
186 .name = "irom", 177 .name = "irom",
187 .id = -1,
188 .parent = &clk_hclk.clk, 178 .parent = &clk_hclk.clk,
189 .enable = s5p64x0_hclk0_ctrl, 179 .enable = s5p64x0_hclk0_ctrl,
190 .ctrlbit = (1 << 25), 180 .ctrlbit = (1 << 25),
191 }, { 181 }, {
192 .name = "lcd", 182 .name = "lcd",
193 .id = -1,
194 .parent = &clk_hclk_low.clk, 183 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk1_ctrl, 184 .enable = s5p64x0_hclk1_ctrl,
196 .ctrlbit = (1 << 1), 185 .ctrlbit = (1 << 1),
197 }, { 186 }, {
198 .name = "hclk_fimgvg", 187 .name = "hclk_fimgvg",
199 .id = -1,
200 .parent = &clk_hclk.clk, 188 .parent = &clk_hclk.clk,
201 .enable = s5p64x0_hclk1_ctrl, 189 .enable = s5p64x0_hclk1_ctrl,
202 .ctrlbit = (1 << 2), 190 .ctrlbit = (1 << 2),
203 }, { 191 }, {
204 .name = "tsi", 192 .name = "tsi",
205 .id = -1,
206 .parent = &clk_hclk_low.clk, 193 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk1_ctrl, 194 .enable = s5p64x0_hclk1_ctrl,
208 .ctrlbit = (1 << 0), 195 .ctrlbit = (1 << 0),
209 }, { 196 }, {
210 .name = "watchdog", 197 .name = "watchdog",
211 .id = -1,
212 .parent = &clk_pclk_low.clk, 198 .parent = &clk_pclk_low.clk,
213 .enable = s5p64x0_pclk_ctrl, 199 .enable = s5p64x0_pclk_ctrl,
214 .ctrlbit = (1 << 5), 200 .ctrlbit = (1 << 5),
215 }, { 201 }, {
216 .name = "rtc", 202 .name = "rtc",
217 .id = -1,
218 .parent = &clk_pclk_low.clk, 203 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl, 204 .enable = s5p64x0_pclk_ctrl,
220 .ctrlbit = (1 << 6), 205 .ctrlbit = (1 << 6),
221 }, { 206 }, {
222 .name = "timers", 207 .name = "timers",
223 .id = -1,
224 .parent = &clk_pclk_low.clk, 208 .parent = &clk_pclk_low.clk,
225 .enable = s5p64x0_pclk_ctrl, 209 .enable = s5p64x0_pclk_ctrl,
226 .ctrlbit = (1 << 7), 210 .ctrlbit = (1 << 7),
227 }, { 211 }, {
228 .name = "pcm", 212 .name = "pcm",
229 .id = -1,
230 .parent = &clk_pclk_low.clk, 213 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl, 214 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 8), 215 .ctrlbit = (1 << 8),
233 }, { 216 }, {
234 .name = "adc", 217 .name = "adc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk, 218 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl, 219 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 12), 220 .ctrlbit = (1 << 12),
239 }, { 221 }, {
240 .name = "i2c", 222 .name = "i2c",
241 .id = -1,
242 .parent = &clk_pclk_low.clk, 223 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl, 224 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 17), 225 .ctrlbit = (1 << 17),
245 }, { 226 }, {
246 .name = "spi", 227 .name = "spi",
247 .id = 0, 228 .devname = "s3c64xx-spi.0",
248 .parent = &clk_pclk_low.clk, 229 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl, 230 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 21), 231 .ctrlbit = (1 << 21),
251 }, { 232 }, {
252 .name = "spi", 233 .name = "spi",
253 .id = 1, 234 .devname = "s3c64xx-spi.1",
254 .parent = &clk_pclk_low.clk, 235 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl, 236 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 22), 237 .ctrlbit = (1 << 22),
257 }, { 238 }, {
258 .name = "gps", 239 .name = "gps",
259 .id = -1,
260 .parent = &clk_pclk_low.clk, 240 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl, 241 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 25), 242 .ctrlbit = (1 << 25),
263 }, { 243 }, {
264 .name = "iis", 244 .name = "iis",
265 .id = 0, 245 .devname = "samsung-i2s.0",
266 .parent = &clk_pclk_low.clk, 246 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl, 247 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26), 248 .ctrlbit = (1 << 26),
269 }, { 249 }, {
270 .name = "dsim", 250 .name = "dsim",
271 .id = -1,
272 .parent = &clk_pclk_low.clk, 251 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl, 252 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 28), 253 .ctrlbit = (1 << 28),
275 }, { 254 }, {
276 .name = "etm", 255 .name = "etm",
277 .id = -1,
278 .parent = &clk_pclk.clk, 256 .parent = &clk_pclk.clk,
279 .enable = s5p64x0_pclk_ctrl, 257 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 29), 258 .ctrlbit = (1 << 29),
281 }, { 259 }, {
282 .name = "dmc0", 260 .name = "dmc0",
283 .id = -1,
284 .parent = &clk_pclk.clk, 261 .parent = &clk_pclk.clk,
285 .enable = s5p64x0_pclk_ctrl, 262 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 30), 263 .ctrlbit = (1 << 30),
287 }, { 264 }, {
288 .name = "pclk_fimgvg", 265 .name = "pclk_fimgvg",
289 .id = -1,
290 .parent = &clk_pclk.clk, 266 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl, 267 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 31), 268 .ctrlbit = (1 << 31),
293 }, { 269 }, {
294 .name = "sclk_spi_48", 270 .name = "sclk_spi_48",
295 .id = 0, 271 .devname = "s3c64xx-spi.0",
296 .parent = &clk_48m, 272 .parent = &clk_48m,
297 .enable = s5p64x0_sclk_ctrl, 273 .enable = s5p64x0_sclk_ctrl,
298 .ctrlbit = (1 << 22), 274 .ctrlbit = (1 << 22),
299 }, { 275 }, {
300 .name = "sclk_spi_48", 276 .name = "sclk_spi_48",
301 .id = 1, 277 .devname = "s3c64xx-spi.1",
302 .parent = &clk_48m, 278 .parent = &clk_48m,
303 .enable = s5p64x0_sclk_ctrl, 279 .enable = s5p64x0_sclk_ctrl,
304 .ctrlbit = (1 << 23), 280 .ctrlbit = (1 << 23),
305 }, { 281 }, {
306 .name = "mmc_48m", 282 .name = "mmc_48m",
307 .id = 0, 283 .devname = "s3c-sdhci.0",
308 .parent = &clk_48m, 284 .parent = &clk_48m,
309 .enable = s5p64x0_sclk_ctrl, 285 .enable = s5p64x0_sclk_ctrl,
310 .ctrlbit = (1 << 27), 286 .ctrlbit = (1 << 27),
311 }, { 287 }, {
312 .name = "mmc_48m", 288 .name = "mmc_48m",
313 .id = 1, 289 .devname = "s3c-sdhci.1",
314 .parent = &clk_48m, 290 .parent = &clk_48m,
315 .enable = s5p64x0_sclk_ctrl, 291 .enable = s5p64x0_sclk_ctrl,
316 .ctrlbit = (1 << 28), 292 .ctrlbit = (1 << 28),
317 }, { 293 }, {
318 .name = "mmc_48m", 294 .name = "mmc_48m",
319 .id = 2, 295 .devname = "s3c-sdhci.2",
320 .parent = &clk_48m, 296 .parent = &clk_48m,
321 .enable = s5p64x0_sclk_ctrl, 297 .enable = s5p64x0_sclk_ctrl,
322 .ctrlbit = (1 << 29), 298 .ctrlbit = (1 << 29),
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
329static struct clk init_clocks[] = { 305static struct clk init_clocks[] = {
330 { 306 {
331 .name = "intc", 307 .name = "intc",
332 .id = -1,
333 .parent = &clk_hclk.clk, 308 .parent = &clk_hclk.clk,
334 .enable = s5p64x0_hclk0_ctrl, 309 .enable = s5p64x0_hclk0_ctrl,
335 .ctrlbit = (1 << 1), 310 .ctrlbit = (1 << 1),
336 }, { 311 }, {
337 .name = "mem", 312 .name = "mem",
338 .id = -1,
339 .parent = &clk_hclk.clk, 313 .parent = &clk_hclk.clk,
340 .enable = s5p64x0_hclk0_ctrl, 314 .enable = s5p64x0_hclk0_ctrl,
341 .ctrlbit = (1 << 21), 315 .ctrlbit = (1 << 21),
342 }, { 316 }, {
343 .name = "uart", 317 .name = "uart",
344 .id = 0, 318 .devname = "s3c6400-uart.0",
345 .parent = &clk_pclk_low.clk, 319 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl, 320 .enable = s5p64x0_pclk_ctrl,
347 .ctrlbit = (1 << 1), 321 .ctrlbit = (1 << 1),
348 }, { 322 }, {
349 .name = "uart", 323 .name = "uart",
350 .id = 1, 324 .devname = "s3c6400-uart.1",
351 .parent = &clk_pclk_low.clk, 325 .parent = &clk_pclk_low.clk,
352 .enable = s5p64x0_pclk_ctrl, 326 .enable = s5p64x0_pclk_ctrl,
353 .ctrlbit = (1 << 2), 327 .ctrlbit = (1 << 2),
354 }, { 328 }, {
355 .name = "uart", 329 .name = "uart",
356 .id = 2, 330 .devname = "s3c6400-uart.2",
357 .parent = &clk_pclk_low.clk, 331 .parent = &clk_pclk_low.clk,
358 .enable = s5p64x0_pclk_ctrl, 332 .enable = s5p64x0_pclk_ctrl,
359 .ctrlbit = (1 << 3), 333 .ctrlbit = (1 << 3),
360 }, { 334 }, {
361 .name = "uart", 335 .name = "uart",
362 .id = 3, 336 .devname = "s3c6400-uart.3",
363 .parent = &clk_pclk_low.clk, 337 .parent = &clk_pclk_low.clk,
364 .enable = s5p64x0_pclk_ctrl, 338 .enable = s5p64x0_pclk_ctrl,
365 .ctrlbit = (1 << 4), 339 .ctrlbit = (1 << 4),
366 }, { 340 }, {
367 .name = "gpio", 341 .name = "gpio",
368 .id = -1,
369 .parent = &clk_pclk_low.clk, 342 .parent = &clk_pclk_low.clk,
370 .enable = s5p64x0_pclk_ctrl, 343 .enable = s5p64x0_pclk_ctrl,
371 .ctrlbit = (1 << 18), 344 .ctrlbit = (1 << 18),
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
374 347
375static struct clk clk_iis_cd_v40 = { 348static struct clk clk_iis_cd_v40 = {
376 .name = "iis_cdclk_v40", 349 .name = "iis_cdclk_v40",
377 .id = -1,
378}; 350};
379 351
380static struct clk clk_pcm_cd = { 352static struct clk clk_pcm_cd = {
381 .name = "pcm_cdclk", 353 .name = "pcm_cdclk",
382 .id = -1,
383}; 354};
384 355
385static struct clk *clkset_group1_list[] = { 356static struct clk *clkset_group1_list[] = {
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
420 { 391 {
421 .clk = { 392 .clk = {
422 .name = "sclk_mmc", 393 .name = "sclk_mmc",
423 .id = 0, 394 .devname = "s3c-sdhci.0",
424 .ctrlbit = (1 << 24), 395 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl, 396 .enable = s5p64x0_sclk_ctrl,
426 }, 397 },
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
430 }, { 401 }, {
431 .clk = { 402 .clk = {
432 .name = "sclk_mmc", 403 .name = "sclk_mmc",
433 .id = 1, 404 .devname = "s3c-sdhci.1",
434 .ctrlbit = (1 << 25), 405 .ctrlbit = (1 << 25),
435 .enable = s5p64x0_sclk_ctrl, 406 .enable = s5p64x0_sclk_ctrl,
436 }, 407 },
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
440 }, { 411 }, {
441 .clk = { 412 .clk = {
442 .name = "sclk_mmc", 413 .name = "sclk_mmc",
443 .id = 2, 414 .devname = "s3c-sdhci.2",
444 .ctrlbit = (1 << 26), 415 .ctrlbit = (1 << 26),
445 .enable = s5p64x0_sclk_ctrl, 416 .enable = s5p64x0_sclk_ctrl,
446 }, 417 },
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
450 }, { 421 }, {
451 .clk = { 422 .clk = {
452 .name = "uclk1", 423 .name = "uclk1",
453 .id = -1,
454 .ctrlbit = (1 << 5), 424 .ctrlbit = (1 << 5),
455 .enable = s5p64x0_sclk_ctrl, 425 .enable = s5p64x0_sclk_ctrl,
456 }, 426 },
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
460 }, { 430 }, {
461 .clk = { 431 .clk = {
462 .name = "sclk_spi", 432 .name = "sclk_spi",
463 .id = 0, 433 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20), 434 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl, 435 .enable = s5p64x0_sclk_ctrl,
466 }, 436 },
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
470 }, { 440 }, {
471 .clk = { 441 .clk = {
472 .name = "sclk_spi", 442 .name = "sclk_spi",
473 .id = 1, 443 .devname = "s3c64xx-spi.1",
474 .ctrlbit = (1 << 21), 444 .ctrlbit = (1 << 21),
475 .enable = s5p64x0_sclk_ctrl, 445 .enable = s5p64x0_sclk_ctrl,
476 }, 446 },
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
480 }, { 450 }, {
481 .clk = { 451 .clk = {
482 .name = "sclk_post", 452 .name = "sclk_post",
483 .id = -1,
484 .ctrlbit = (1 << 10), 453 .ctrlbit = (1 << 10),
485 .enable = s5p64x0_sclk_ctrl, 454 .enable = s5p64x0_sclk_ctrl,
486 }, 455 },
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
490 }, { 459 }, {
491 .clk = { 460 .clk = {
492 .name = "sclk_dispcon", 461 .name = "sclk_dispcon",
493 .id = -1,
494 .ctrlbit = (1 << 1), 462 .ctrlbit = (1 << 1),
495 .enable = s5p64x0_sclk1_ctrl, 463 .enable = s5p64x0_sclk1_ctrl,
496 }, 464 },
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
500 }, { 468 }, {
501 .clk = { 469 .clk = {
502 .name = "sclk_fimgvg", 470 .name = "sclk_fimgvg",
503 .id = -1,
504 .ctrlbit = (1 << 2), 471 .ctrlbit = (1 << 2),
505 .enable = s5p64x0_sclk1_ctrl, 472 .enable = s5p64x0_sclk1_ctrl,
506 }, 473 },
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
510 }, { 477 }, {
511 .clk = { 478 .clk = {
512 .name = "sclk_audio2", 479 .name = "sclk_audio2",
513 .id = -1,
514 .ctrlbit = (1 << 11), 480 .ctrlbit = (1 << 11),
515 .enable = s5p64x0_sclk_ctrl, 481 .enable = s5p64x0_sclk_ctrl,
516 }, 482 },
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 4eec457ddccc..d9dc16cde109 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -36,7 +36,6 @@
36static struct clksrc_clk clk_mout_dpll = { 36static struct clksrc_clk clk_mout_dpll = {
37 .clk = { 37 .clk = {
38 .name = "mout_dpll", 38 .name = "mout_dpll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_dpll, 40 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, 41 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
@@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = {
96static struct clksrc_clk clk_dout_epll = { 95static struct clksrc_clk clk_dout_epll = {
97 .clk = { 96 .clk = {
98 .name = "dout_epll", 97 .name = "dout_epll",
99 .id = -1,
100 .parent = &clk_mout_epll.clk, 98 .parent = &clk_mout_epll.clk,
101 }, 99 },
102 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, 100 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
@@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = {
105static struct clksrc_clk clk_mout_hclk_sel = { 103static struct clksrc_clk clk_mout_hclk_sel = {
106 .clk = { 104 .clk = {
107 .name = "mout_hclk_sel", 105 .name = "mout_hclk_sel",
108 .id = -1,
109 }, 106 },
110 .sources = &clkset_hclk_low, 107 .sources = &clkset_hclk_low,
111 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, 108 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
@@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = {
124static struct clksrc_clk clk_hclk = { 121static struct clksrc_clk clk_hclk = {
125 .clk = { 122 .clk = {
126 .name = "clk_hclk", 123 .name = "clk_hclk",
127 .id = -1,
128 }, 124 },
129 .sources = &clkset_hclk, 125 .sources = &clkset_hclk,
130 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, 126 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
@@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = {
134static struct clksrc_clk clk_pclk = { 130static struct clksrc_clk clk_pclk = {
135 .clk = { 131 .clk = {
136 .name = "clk_pclk", 132 .name = "clk_pclk",
137 .id = -1,
138 .parent = &clk_hclk.clk, 133 .parent = &clk_hclk.clk,
139 }, 134 },
140 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, 135 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = {
142static struct clksrc_clk clk_dout_pwm_ratio0 = { 137static struct clksrc_clk clk_dout_pwm_ratio0 = {
143 .clk = { 138 .clk = {
144 .name = "clk_dout_pwm_ratio0", 139 .name = "clk_dout_pwm_ratio0",
145 .id = -1,
146 .parent = &clk_mout_hclk_sel.clk, 140 .parent = &clk_mout_hclk_sel.clk,
147 }, 141 },
148 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, 142 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
@@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = {
151static struct clksrc_clk clk_pclk_to_wdt_pwm = { 145static struct clksrc_clk clk_pclk_to_wdt_pwm = {
152 .clk = { 146 .clk = {
153 .name = "clk_pclk_to_wdt_pwm", 147 .name = "clk_pclk_to_wdt_pwm",
154 .id = -1,
155 .parent = &clk_dout_pwm_ratio0.clk, 148 .parent = &clk_dout_pwm_ratio0.clk,
156 }, 149 },
157 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, 150 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
@@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = {
160static struct clksrc_clk clk_hclk_low = { 153static struct clksrc_clk clk_hclk_low = {
161 .clk = { 154 .clk = {
162 .name = "clk_hclk_low", 155 .name = "clk_hclk_low",
163 .id = -1,
164 }, 156 },
165 .sources = &clkset_hclk_low, 157 .sources = &clkset_hclk_low,
166 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, 158 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
@@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = {
170static struct clksrc_clk clk_pclk_low = { 162static struct clksrc_clk clk_pclk_low = {
171 .clk = { 163 .clk = {
172 .name = "clk_pclk_low", 164 .name = "clk_pclk_low",
173 .id = -1,
174 .parent = &clk_hclk_low.clk, 165 .parent = &clk_hclk_low.clk,
175 }, 166 },
176 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, 167 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = {
184static struct clk init_clocks_off[] = { 175static struct clk init_clocks_off[] = {
185 { 176 {
186 .name = "usbhost", 177 .name = "usbhost",
187 .id = -1,
188 .parent = &clk_hclk_low.clk, 178 .parent = &clk_hclk_low.clk,
189 .enable = s5p64x0_hclk0_ctrl, 179 .enable = s5p64x0_hclk0_ctrl,
190 .ctrlbit = (1 << 3), 180 .ctrlbit = (1 << 3),
191 }, { 181 }, {
192 .name = "pdma", 182 .name = "pdma",
193 .id = -1,
194 .parent = &clk_hclk_low.clk, 183 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk0_ctrl, 184 .enable = s5p64x0_hclk0_ctrl,
196 .ctrlbit = (1 << 12), 185 .ctrlbit = (1 << 12),
197 }, { 186 }, {
198 .name = "hsmmc", 187 .name = "hsmmc",
199 .id = 0, 188 .devname = "s3c-sdhci.0",
200 .parent = &clk_hclk_low.clk, 189 .parent = &clk_hclk_low.clk,
201 .enable = s5p64x0_hclk0_ctrl, 190 .enable = s5p64x0_hclk0_ctrl,
202 .ctrlbit = (1 << 17), 191 .ctrlbit = (1 << 17),
203 }, { 192 }, {
204 .name = "hsmmc", 193 .name = "hsmmc",
205 .id = 1, 194 .devname = "s3c-sdhci.1",
206 .parent = &clk_hclk_low.clk, 195 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk0_ctrl, 196 .enable = s5p64x0_hclk0_ctrl,
208 .ctrlbit = (1 << 18), 197 .ctrlbit = (1 << 18),
209 }, { 198 }, {
210 .name = "hsmmc", 199 .name = "hsmmc",
211 .id = 2, 200 .devname = "s3c-sdhci.2",
212 .parent = &clk_hclk_low.clk, 201 .parent = &clk_hclk_low.clk,
213 .enable = s5p64x0_hclk0_ctrl, 202 .enable = s5p64x0_hclk0_ctrl,
214 .ctrlbit = (1 << 19), 203 .ctrlbit = (1 << 19),
215 }, { 204 }, {
216 .name = "usbotg", 205 .name = "usbotg",
217 .id = -1,
218 .parent = &clk_hclk_low.clk, 206 .parent = &clk_hclk_low.clk,
219 .enable = s5p64x0_hclk0_ctrl, 207 .enable = s5p64x0_hclk0_ctrl,
220 .ctrlbit = (1 << 20), 208 .ctrlbit = (1 << 20),
221 }, { 209 }, {
222 .name = "lcd", 210 .name = "lcd",
223 .id = -1,
224 .parent = &clk_h, 211 .parent = &clk_h,
225 .enable = s5p64x0_hclk1_ctrl, 212 .enable = s5p64x0_hclk1_ctrl,
226 .ctrlbit = (1 << 1), 213 .ctrlbit = (1 << 1),
227 }, { 214 }, {
228 .name = "watchdog", 215 .name = "watchdog",
229 .id = -1,
230 .parent = &clk_pclk_low.clk, 216 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl, 217 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 5), 218 .ctrlbit = (1 << 5),
233 }, { 219 }, {
234 .name = "rtc", 220 .name = "rtc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk, 221 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl, 222 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 6), 223 .ctrlbit = (1 << 6),
239 }, { 224 }, {
240 .name = "adc", 225 .name = "adc",
241 .id = -1,
242 .parent = &clk_pclk_low.clk, 226 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl, 227 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 12), 228 .ctrlbit = (1 << 12),
245 }, { 229 }, {
246 .name = "i2c", 230 .name = "i2c",
247 .id = 0, 231 .devname = "s3c2440-i2c.0",
248 .parent = &clk_pclk_low.clk, 232 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl, 233 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 17), 234 .ctrlbit = (1 << 17),
251 }, { 235 }, {
252 .name = "spi", 236 .name = "spi",
253 .id = 0, 237 .devname = "s3c64xx-spi.0",
254 .parent = &clk_pclk_low.clk, 238 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl, 239 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 21), 240 .ctrlbit = (1 << 21),
257 }, { 241 }, {
258 .name = "spi", 242 .name = "spi",
259 .id = 1, 243 .devname = "s3c64xx-spi.1",
260 .parent = &clk_pclk_low.clk, 244 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl, 245 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 22), 246 .ctrlbit = (1 << 22),
263 }, { 247 }, {
264 .name = "iis", 248 .name = "iis",
265 .id = 0, 249 .devname = "samsung-i2s.0",
266 .parent = &clk_pclk_low.clk, 250 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl, 251 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26), 252 .ctrlbit = (1 << 26),
269 }, { 253 }, {
270 .name = "iis", 254 .name = "iis",
271 .id = 1, 255 .devname = "samsung-i2s.1",
272 .parent = &clk_pclk_low.clk, 256 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl, 257 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 15), 258 .ctrlbit = (1 << 15),
275 }, { 259 }, {
276 .name = "iis", 260 .name = "iis",
277 .id = 2, 261 .devname = "samsung-i2s.2",
278 .parent = &clk_pclk_low.clk, 262 .parent = &clk_pclk_low.clk,
279 .enable = s5p64x0_pclk_ctrl, 263 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 16), 264 .ctrlbit = (1 << 16),
281 }, { 265 }, {
282 .name = "i2c", 266 .name = "i2c",
283 .id = 1, 267 .devname = "s3c2440-i2c.1",
284 .parent = &clk_pclk_low.clk, 268 .parent = &clk_pclk_low.clk,
285 .enable = s5p64x0_pclk_ctrl, 269 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 27), 270 .ctrlbit = (1 << 27),
287 }, { 271 }, {
288 .name = "dmc0", 272 .name = "dmc0",
289 .id = -1,
290 .parent = &clk_pclk.clk, 273 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl, 274 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 30), 275 .ctrlbit = (1 << 30),
@@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = {
299static struct clk init_clocks[] = { 282static struct clk init_clocks[] = {
300 { 283 {
301 .name = "intc", 284 .name = "intc",
302 .id = -1,
303 .parent = &clk_hclk.clk, 285 .parent = &clk_hclk.clk,
304 .enable = s5p64x0_hclk0_ctrl, 286 .enable = s5p64x0_hclk0_ctrl,
305 .ctrlbit = (1 << 1), 287 .ctrlbit = (1 << 1),
306 }, { 288 }, {
307 .name = "mem", 289 .name = "mem",
308 .id = -1,
309 .parent = &clk_hclk.clk, 290 .parent = &clk_hclk.clk,
310 .enable = s5p64x0_hclk0_ctrl, 291 .enable = s5p64x0_hclk0_ctrl,
311 .ctrlbit = (1 << 21), 292 .ctrlbit = (1 << 21),
312 }, { 293 }, {
313 .name = "uart", 294 .name = "uart",
314 .id = 0, 295 .devname = "s3c6400-uart.0",
315 .parent = &clk_pclk_low.clk, 296 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl, 297 .enable = s5p64x0_pclk_ctrl,
317 .ctrlbit = (1 << 1), 298 .ctrlbit = (1 << 1),
318 }, { 299 }, {
319 .name = "uart", 300 .name = "uart",
320 .id = 1, 301 .devname = "s3c6400-uart.1",
321 .parent = &clk_pclk_low.clk, 302 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl, 303 .enable = s5p64x0_pclk_ctrl,
323 .ctrlbit = (1 << 2), 304 .ctrlbit = (1 << 2),
324 }, { 305 }, {
325 .name = "uart", 306 .name = "uart",
326 .id = 2, 307 .devname = "s3c6400-uart.2",
327 .parent = &clk_pclk_low.clk, 308 .parent = &clk_pclk_low.clk,
328 .enable = s5p64x0_pclk_ctrl, 309 .enable = s5p64x0_pclk_ctrl,
329 .ctrlbit = (1 << 3), 310 .ctrlbit = (1 << 3),
330 }, { 311 }, {
331 .name = "uart", 312 .name = "uart",
332 .id = 3, 313 .devname = "s3c6400-uart.3",
333 .parent = &clk_pclk_low.clk, 314 .parent = &clk_pclk_low.clk,
334 .enable = s5p64x0_pclk_ctrl, 315 .enable = s5p64x0_pclk_ctrl,
335 .ctrlbit = (1 << 4), 316 .ctrlbit = (1 << 4),
336 }, { 317 }, {
337 .name = "timers", 318 .name = "timers",
338 .id = -1,
339 .parent = &clk_pclk_to_wdt_pwm.clk, 319 .parent = &clk_pclk_to_wdt_pwm.clk,
340 .enable = s5p64x0_pclk_ctrl, 320 .enable = s5p64x0_pclk_ctrl,
341 .ctrlbit = (1 << 7), 321 .ctrlbit = (1 << 7),
342 }, { 322 }, {
343 .name = "gpio", 323 .name = "gpio",
344 .id = -1,
345 .parent = &clk_pclk_low.clk, 324 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl, 325 .enable = s5p64x0_pclk_ctrl,
347 .ctrlbit = (1 << 18), 326 .ctrlbit = (1 << 18),
@@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = {
421static struct clksrc_clk clk_sclk_audio0 = { 400static struct clksrc_clk clk_sclk_audio0 = {
422 .clk = { 401 .clk = {
423 .name = "audio-bus", 402 .name = "audio-bus",
424 .id = -1,
425 .enable = s5p64x0_sclk_ctrl, 403 .enable = s5p64x0_sclk_ctrl,
426 .ctrlbit = (1 << 8), 404 .ctrlbit = (1 << 8),
427 .parent = &clk_dout_epll.clk, 405 .parent = &clk_dout_epll.clk,
@@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = {
435 { 413 {
436 .clk = { 414 .clk = {
437 .name = "sclk_mmc", 415 .name = "sclk_mmc",
438 .id = 0, 416 .devname = "s3c-sdhci.0",
439 .ctrlbit = (1 << 24), 417 .ctrlbit = (1 << 24),
440 .enable = s5p64x0_sclk_ctrl, 418 .enable = s5p64x0_sclk_ctrl,
441 }, 419 },
@@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = {
445 }, { 423 }, {
446 .clk = { 424 .clk = {
447 .name = "sclk_mmc", 425 .name = "sclk_mmc",
448 .id = 1, 426 .devname = "s3c-sdhci.1",
449 .ctrlbit = (1 << 25), 427 .ctrlbit = (1 << 25),
450 .enable = s5p64x0_sclk_ctrl, 428 .enable = s5p64x0_sclk_ctrl,
451 }, 429 },
@@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = {
455 }, { 433 }, {
456 .clk = { 434 .clk = {
457 .name = "sclk_mmc", 435 .name = "sclk_mmc",
458 .id = 2, 436 .devname = "s3c-sdhci.2",
459 .ctrlbit = (1 << 26), 437 .ctrlbit = (1 << 26),
460 .enable = s5p64x0_sclk_ctrl, 438 .enable = s5p64x0_sclk_ctrl,
461 }, 439 },
@@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = {
465 }, { 443 }, {
466 .clk = { 444 .clk = {
467 .name = "uclk1", 445 .name = "uclk1",
468 .id = -1,
469 .ctrlbit = (1 << 5), 446 .ctrlbit = (1 << 5),
470 .enable = s5p64x0_sclk_ctrl, 447 .enable = s5p64x0_sclk_ctrl,
471 }, 448 },
@@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = {
475 }, { 452 }, {
476 .clk = { 453 .clk = {
477 .name = "sclk_spi", 454 .name = "sclk_spi",
478 .id = 0, 455 .devname = "s3c64xx-spi.0",
479 .ctrlbit = (1 << 20), 456 .ctrlbit = (1 << 20),
480 .enable = s5p64x0_sclk_ctrl, 457 .enable = s5p64x0_sclk_ctrl,
481 }, 458 },
@@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = {
485 }, { 462 }, {
486 .clk = { 463 .clk = {
487 .name = "sclk_spi", 464 .name = "sclk_spi",
488 .id = 1, 465 .devname = "s3c64xx-spi.1",
489 .ctrlbit = (1 << 21), 466 .ctrlbit = (1 << 21),
490 .enable = s5p64x0_sclk_ctrl, 467 .enable = s5p64x0_sclk_ctrl,
491 }, 468 },
@@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = {
495 }, { 472 }, {
496 .clk = { 473 .clk = {
497 .name = "sclk_fimc", 474 .name = "sclk_fimc",
498 .id = -1,
499 .ctrlbit = (1 << 10), 475 .ctrlbit = (1 << 10),
500 .enable = s5p64x0_sclk_ctrl, 476 .enable = s5p64x0_sclk_ctrl,
501 }, 477 },
@@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = {
505 }, { 481 }, {
506 .clk = { 482 .clk = {
507 .name = "aclk_mali", 483 .name = "aclk_mali",
508 .id = -1,
509 .ctrlbit = (1 << 2), 484 .ctrlbit = (1 << 2),
510 .enable = s5p64x0_sclk1_ctrl, 485 .enable = s5p64x0_sclk1_ctrl,
511 }, 486 },
@@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = {
515 }, { 490 }, {
516 .clk = { 491 .clk = {
517 .name = "sclk_2d", 492 .name = "sclk_2d",
518 .id = -1,
519 .ctrlbit = (1 << 12), 493 .ctrlbit = (1 << 12),
520 .enable = s5p64x0_sclk_ctrl, 494 .enable = s5p64x0_sclk_ctrl,
521 }, 495 },
@@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = {
525 }, { 499 }, {
526 .clk = { 500 .clk = {
527 .name = "sclk_usi", 501 .name = "sclk_usi",
528 .id = -1,
529 .ctrlbit = (1 << 7), 502 .ctrlbit = (1 << 7),
530 .enable = s5p64x0_sclk_ctrl, 503 .enable = s5p64x0_sclk_ctrl,
531 }, 504 },
@@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = {
535 }, { 508 }, {
536 .clk = { 509 .clk = {
537 .name = "sclk_camif", 510 .name = "sclk_camif",
538 .id = -1,
539 .ctrlbit = (1 << 6), 511 .ctrlbit = (1 << 6),
540 .enable = s5p64x0_sclk_ctrl, 512 .enable = s5p64x0_sclk_ctrl,
541 }, 513 },
@@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = {
545 }, { 517 }, {
546 .clk = { 518 .clk = {
547 .name = "sclk_dispcon", 519 .name = "sclk_dispcon",
548 .id = -1,
549 .ctrlbit = (1 << 1), 520 .ctrlbit = (1 << 1),
550 .enable = s5p64x0_sclk1_ctrl, 521 .enable = s5p64x0_sclk1_ctrl,
551 }, 522 },
@@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = {
555 }, { 526 }, {
556 .clk = { 527 .clk = {
557 .name = "sclk_hsmmc44", 528 .name = "sclk_hsmmc44",
558 .id = -1,
559 .ctrlbit = (1 << 30), 529 .ctrlbit = (1 << 30),
560 .enable = s5p64x0_sclk_ctrl, 530 .enable = s5p64x0_sclk_ctrl,
561 }, 531 },
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 513abffc7604..5837a36ece8d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -85,6 +85,8 @@
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4 85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5 86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87 87
88#define IRQ_I2S0 IRQ_I2SV40
89
88/* S5P6450 EINT feature will be added */ 90/* S5P6450 EINT feature will be added */
89 91
90/* 92/*
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 0953ef6b1c77..6ce254729f3b 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,4 +34,14 @@
34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) 34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) 35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
36 36
37/* External interrupt control registers for group0 */
38
39#define EINT0CON0_OFFSET (0x900)
40#define EINT0MASK_OFFSET (0x920)
41#define EINT0PEND_OFFSET (0x924)
42
43#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
44#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
45#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
46
37#endif /* __ASM_ARCH_REGS_GPIO_H */ 47#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
new file mode 100644
index 000000000000..69ed4545112b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -0,0 +1,152 @@
1/* arch/arm/mach-s5p64x0/irq-eint.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd
4 * http://www.samsung.com/
5 *
6 * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
7 *
8 * S5P64X0 - Interrupt handling for External Interrupts.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/gpio.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19
20#include <plat/regs-irqtype.h>
21#include <plat/gpio-cfg.h>
22
23#include <mach/regs-gpio.h>
24#include <mach/regs-clock.h>
25
26#define eint_offset(irq) ((irq) - IRQ_EINT(0))
27
28static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
29{
30 int offs = eint_offset(data->irq);
31 int shift;
32 u32 ctrl, mask;
33 u32 newvalue = 0;
34
35 if (offs > 15)
36 return -EINVAL;
37
38 switch (type) {
39 case IRQ_TYPE_NONE:
40 printk(KERN_WARNING "No edge setting!\n");
41 break;
42 case IRQ_TYPE_EDGE_RISING:
43 newvalue = S3C2410_EXTINT_RISEEDGE;
44 break;
45 case IRQ_TYPE_EDGE_FALLING:
46 newvalue = S3C2410_EXTINT_FALLEDGE;
47 break;
48 case IRQ_TYPE_EDGE_BOTH:
49 newvalue = S3C2410_EXTINT_BOTHEDGE;
50 break;
51 case IRQ_TYPE_LEVEL_LOW:
52 newvalue = S3C2410_EXTINT_LOWLEV;
53 break;
54 case IRQ_TYPE_LEVEL_HIGH:
55 newvalue = S3C2410_EXTINT_HILEV;
56 break;
57 default:
58 printk(KERN_ERR "No such irq type %d", type);
59 return -EINVAL;
60 }
61
62 shift = (offs / 2) * 4;
63 mask = 0x7 << shift;
64
65 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
66 ctrl |= newvalue << shift;
67 __raw_writel(ctrl, S5P64X0_EINT0CON0);
68
69 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
70 if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
71 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
72 else
73 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
74
75 return 0;
76}
77
78/*
79 * s5p64x0_irq_demux_eint
80 *
81 * This function demuxes the IRQ from the group0 external interrupts,
82 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
83 * the specific handlers s5p64x0_irq_demux_eintX_Y.
84 */
85static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
86{
87 u32 status = __raw_readl(S5P64X0_EINT0PEND);
88 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
89 unsigned int irq;
90
91 status &= ~mask;
92 status >>= start;
93 status &= (1 << (end - start + 1)) - 1;
94
95 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
96 if (status & 1)
97 generic_handle_irq(irq);
98 status >>= 1;
99 }
100}
101
102static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
103{
104 s5p64x0_irq_demux_eint(0, 3);
105}
106
107static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
108{
109 s5p64x0_irq_demux_eint(4, 11);
110}
111
112static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
113 struct irq_desc *desc)
114{
115 s5p64x0_irq_demux_eint(12, 15);
116}
117
118static int s5p64x0_alloc_gc(void)
119{
120 struct irq_chip_generic *gc;
121 struct irq_chip_type *ct;
122
123 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
124 S5P_VA_GPIO, handle_level_irq);
125 if (!gc) {
126 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
127 "external interrupts failed\n", __func__);
128 return -EINVAL;
129 }
130
131 ct = gc->chip_types;
132 ct->chip.irq_ack = irq_gc_ack;
133 ct->chip.irq_mask = irq_gc_mask_set_bit;
134 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
135 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
136 ct->regs.ack = EINT0PEND_OFFSET;
137 ct->regs.mask = EINT0MASK_OFFSET;
138 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
139 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
140 return 0;
141}
142
143static int __init s5p64x0_init_irq_eint(void)
144{
145 int ret = s5p64x0_alloc_gc();
146 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
147 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
148 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
149
150 return ret;
151}
152arch_initcall(s5p64x0_init_irq_eint);
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 0305e9b8282d..cd248e681377 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -31,7 +31,6 @@
31 31
32static struct clk s5p_clk_otgphy = { 32static struct clk s5p_clk_otgphy = {
33 .name = "otg_phy", 33 .name = "otg_phy",
34 .id = -1,
35}; 34};
36 35
37static struct clk *clk_src_mout_href_list[] = { 36static struct clk *clk_src_mout_href_list[] = {
@@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
47static struct clksrc_clk clk_mout_href = { 46static struct clksrc_clk clk_mout_href = {
48 .clk = { 47 .clk = {
49 .name = "mout_href", 48 .name = "mout_href",
50 .id = -1,
51 }, 49 },
52 .sources = &clk_src_mout_href, 50 .sources = &clk_src_mout_href,
53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
66static struct clksrc_clk clk_mout_48m = { 64static struct clksrc_clk clk_mout_48m = {
67 .clk = { 65 .clk = {
68 .name = "mout_48m", 66 .name = "mout_48m",
69 .id = -1,
70 }, 67 },
71 .sources = &clk_src_mout_48m, 68 .sources = &clk_src_mout_48m,
72 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, 69 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
75static struct clksrc_clk clk_mout_mpll = { 72static struct clksrc_clk clk_mout_mpll = {
76 .clk = { 73 .clk = {
77 .name = "mout_mpll", 74 .name = "mout_mpll",
78 .id = -1,
79 }, 75 },
80 .sources = &clk_src_mpll, 76 .sources = &clk_src_mpll,
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
85static struct clksrc_clk clk_mout_apll = { 81static struct clksrc_clk clk_mout_apll = {
86 .clk = { 82 .clk = {
87 .name = "mout_apll", 83 .name = "mout_apll",
88 .id = -1,
89 }, 84 },
90 .sources = &clk_src_apll, 85 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 86 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
94static struct clksrc_clk clk_mout_epll = { 89static struct clksrc_clk clk_mout_epll = {
95 .clk = { 90 .clk = {
96 .name = "mout_epll", 91 .name = "mout_epll",
97 .id = -1,
98 }, 92 },
99 .sources = &clk_src_epll, 93 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 94 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
112static struct clksrc_clk clk_mout_hpll = { 106static struct clksrc_clk clk_mout_hpll = {
113 .clk = { 107 .clk = {
114 .name = "mout_hpll", 108 .name = "mout_hpll",
115 .id = -1,
116 }, 109 },
117 .sources = &clk_src_mout_hpll, 110 .sources = &clk_src_mout_hpll,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 111 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
121static struct clksrc_clk clk_div_apll = { 114static struct clksrc_clk clk_div_apll = {
122 .clk = { 115 .clk = {
123 .name = "div_apll", 116 .name = "div_apll",
124 .id = -1,
125 .parent = &clk_mout_apll.clk, 117 .parent = &clk_mout_apll.clk,
126 }, 118 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, 119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
130static struct clksrc_clk clk_div_arm = { 122static struct clksrc_clk clk_div_arm = {
131 .clk = { 123 .clk = {
132 .name = "div_arm", 124 .name = "div_arm",
133 .id = -1,
134 .parent = &clk_div_apll.clk, 125 .parent = &clk_div_apll.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
139static struct clksrc_clk clk_div_d0_bus = { 130static struct clksrc_clk clk_div_d0_bus = {
140 .clk = { 131 .clk = {
141 .name = "div_d0_bus", 132 .name = "div_d0_bus",
142 .id = -1,
143 .parent = &clk_div_arm.clk, 133 .parent = &clk_div_arm.clk,
144 }, 134 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 135 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
148static struct clksrc_clk clk_div_pclkd0 = { 138static struct clksrc_clk clk_div_pclkd0 = {
149 .clk = { 139 .clk = {
150 .name = "div_pclkd0", 140 .name = "div_pclkd0",
151 .id = -1,
152 .parent = &clk_div_d0_bus.clk, 141 .parent = &clk_div_d0_bus.clk,
153 }, 142 },
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 143 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
157static struct clksrc_clk clk_div_secss = { 146static struct clksrc_clk clk_div_secss = {
158 .clk = { 147 .clk = {
159 .name = "div_secss", 148 .name = "div_secss",
160 .id = -1,
161 .parent = &clk_div_d0_bus.clk, 149 .parent = &clk_div_d0_bus.clk,
162 }, 150 },
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, 151 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
166static struct clksrc_clk clk_div_apll2 = { 154static struct clksrc_clk clk_div_apll2 = {
167 .clk = { 155 .clk = {
168 .name = "div_apll2", 156 .name = "div_apll2",
169 .id = -1,
170 .parent = &clk_mout_apll.clk, 157 .parent = &clk_mout_apll.clk,
171 }, 158 },
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, 159 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
185static struct clksrc_clk clk_mout_am = { 172static struct clksrc_clk clk_mout_am = {
186 .clk = { 173 .clk = {
187 .name = "mout_am", 174 .name = "mout_am",
188 .id = -1,
189 }, 175 },
190 .sources = &clk_src_mout_am, 176 .sources = &clk_src_mout_am,
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 177 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
194static struct clksrc_clk clk_div_d1_bus = { 180static struct clksrc_clk clk_div_d1_bus = {
195 .clk = { 181 .clk = {
196 .name = "div_d1_bus", 182 .name = "div_d1_bus",
197 .id = -1,
198 .parent = &clk_mout_am.clk, 183 .parent = &clk_mout_am.clk,
199 }, 184 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, 185 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
203static struct clksrc_clk clk_div_mpll2 = { 188static struct clksrc_clk clk_div_mpll2 = {
204 .clk = { 189 .clk = {
205 .name = "div_mpll2", 190 .name = "div_mpll2",
206 .id = -1,
207 .parent = &clk_mout_am.clk, 191 .parent = &clk_mout_am.clk,
208 }, 192 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, 193 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
212static struct clksrc_clk clk_div_mpll = { 196static struct clksrc_clk clk_div_mpll = {
213 .clk = { 197 .clk = {
214 .name = "div_mpll", 198 .name = "div_mpll",
215 .id = -1,
216 .parent = &clk_mout_am.clk, 199 .parent = &clk_mout_am.clk,
217 }, 200 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, 201 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
231static struct clksrc_clk clk_mout_onenand = { 214static struct clksrc_clk clk_mout_onenand = {
232 .clk = { 215 .clk = {
233 .name = "mout_onenand", 216 .name = "mout_onenand",
234 .id = -1,
235 }, 217 },
236 .sources = &clk_src_mout_onenand, 218 .sources = &clk_src_mout_onenand,
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 219 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
240static struct clksrc_clk clk_div_onenand = { 222static struct clksrc_clk clk_div_onenand = {
241 .clk = { 223 .clk = {
242 .name = "div_onenand", 224 .name = "div_onenand",
243 .id = -1,
244 .parent = &clk_mout_onenand.clk, 225 .parent = &clk_mout_onenand.clk,
245 }, 226 },
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, 227 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
249static struct clksrc_clk clk_div_pclkd1 = { 230static struct clksrc_clk clk_div_pclkd1 = {
250 .clk = { 231 .clk = {
251 .name = "div_pclkd1", 232 .name = "div_pclkd1",
252 .id = -1,
253 .parent = &clk_div_d1_bus.clk, 233 .parent = &clk_div_d1_bus.clk,
254 }, 234 },
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, 235 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
258static struct clksrc_clk clk_div_cam = { 238static struct clksrc_clk clk_div_cam = {
259 .clk = { 239 .clk = {
260 .name = "div_cam", 240 .name = "div_cam",
261 .id = -1,
262 .parent = &clk_div_mpll2.clk, 241 .parent = &clk_div_mpll2.clk,
263 }, 242 },
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, 243 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
267static struct clksrc_clk clk_div_hdmi = { 246static struct clksrc_clk clk_div_hdmi = {
268 .clk = { 247 .clk = {
269 .name = "div_hdmi", 248 .name = "div_hdmi",
270 .id = -1,
271 .parent = &clk_mout_hpll.clk, 249 .parent = &clk_mout_hpll.clk,
272 }, 250 },
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, 251 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
399static struct clk init_clocks_off[] = { 377static struct clk init_clocks_off[] = {
400 { 378 {
401 .name = "cssys", 379 .name = "cssys",
402 .id = -1,
403 .parent = &clk_div_d0_bus.clk, 380 .parent = &clk_div_d0_bus.clk,
404 .enable = s5pc100_d0_0_ctrl, 381 .enable = s5pc100_d0_0_ctrl,
405 .ctrlbit = (1 << 6), 382 .ctrlbit = (1 << 6),
406 }, { 383 }, {
407 .name = "secss", 384 .name = "secss",
408 .id = -1,
409 .parent = &clk_div_d0_bus.clk, 385 .parent = &clk_div_d0_bus.clk,
410 .enable = s5pc100_d0_0_ctrl, 386 .enable = s5pc100_d0_0_ctrl,
411 .ctrlbit = (1 << 5), 387 .ctrlbit = (1 << 5),
412 }, { 388 }, {
413 .name = "g2d", 389 .name = "g2d",
414 .id = -1,
415 .parent = &clk_div_d0_bus.clk, 390 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_0_ctrl, 391 .enable = s5pc100_d0_0_ctrl,
417 .ctrlbit = (1 << 4), 392 .ctrlbit = (1 << 4),
418 }, { 393 }, {
419 .name = "mdma", 394 .name = "mdma",
420 .id = -1,
421 .parent = &clk_div_d0_bus.clk, 395 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_0_ctrl, 396 .enable = s5pc100_d0_0_ctrl,
423 .ctrlbit = (1 << 3), 397 .ctrlbit = (1 << 3),
424 }, { 398 }, {
425 .name = "cfcon", 399 .name = "cfcon",
426 .id = -1,
427 .parent = &clk_div_d0_bus.clk, 400 .parent = &clk_div_d0_bus.clk,
428 .enable = s5pc100_d0_0_ctrl, 401 .enable = s5pc100_d0_0_ctrl,
429 .ctrlbit = (1 << 2), 402 .ctrlbit = (1 << 2),
430 }, { 403 }, {
431 .name = "nfcon", 404 .name = "nfcon",
432 .id = -1,
433 .parent = &clk_div_d0_bus.clk, 405 .parent = &clk_div_d0_bus.clk,
434 .enable = s5pc100_d0_1_ctrl, 406 .enable = s5pc100_d0_1_ctrl,
435 .ctrlbit = (1 << 3), 407 .ctrlbit = (1 << 3),
436 }, { 408 }, {
437 .name = "onenandc", 409 .name = "onenandc",
438 .id = -1,
439 .parent = &clk_div_d0_bus.clk, 410 .parent = &clk_div_d0_bus.clk,
440 .enable = s5pc100_d0_1_ctrl, 411 .enable = s5pc100_d0_1_ctrl,
441 .ctrlbit = (1 << 2), 412 .ctrlbit = (1 << 2),
442 }, { 413 }, {
443 .name = "sdm", 414 .name = "sdm",
444 .id = -1,
445 .parent = &clk_div_d0_bus.clk, 415 .parent = &clk_div_d0_bus.clk,
446 .enable = s5pc100_d0_2_ctrl, 416 .enable = s5pc100_d0_2_ctrl,
447 .ctrlbit = (1 << 2), 417 .ctrlbit = (1 << 2),
448 }, { 418 }, {
449 .name = "seckey", 419 .name = "seckey",
450 .id = -1,
451 .parent = &clk_div_d0_bus.clk, 420 .parent = &clk_div_d0_bus.clk,
452 .enable = s5pc100_d0_2_ctrl, 421 .enable = s5pc100_d0_2_ctrl,
453 .ctrlbit = (1 << 1), 422 .ctrlbit = (1 << 1),
454 }, { 423 }, {
455 .name = "hsmmc", 424 .name = "hsmmc",
456 .id = 2, 425 .devname = "s3c-sdhci.2",
457 .parent = &clk_div_d1_bus.clk, 426 .parent = &clk_div_d1_bus.clk,
458 .enable = s5pc100_d1_0_ctrl, 427 .enable = s5pc100_d1_0_ctrl,
459 .ctrlbit = (1 << 7), 428 .ctrlbit = (1 << 7),
460 }, { 429 }, {
461 .name = "hsmmc", 430 .name = "hsmmc",
462 .id = 1, 431 .devname = "s3c-sdhci.1",
463 .parent = &clk_div_d1_bus.clk, 432 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_0_ctrl, 433 .enable = s5pc100_d1_0_ctrl,
465 .ctrlbit = (1 << 6), 434 .ctrlbit = (1 << 6),
466 }, { 435 }, {
467 .name = "hsmmc", 436 .name = "hsmmc",
468 .id = 0, 437 .devname = "s3c-sdhci.0",
469 .parent = &clk_div_d1_bus.clk, 438 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_0_ctrl, 439 .enable = s5pc100_d1_0_ctrl,
471 .ctrlbit = (1 << 5), 440 .ctrlbit = (1 << 5),
472 }, { 441 }, {
473 .name = "modemif", 442 .name = "modemif",
474 .id = -1,
475 .parent = &clk_div_d1_bus.clk, 443 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_0_ctrl, 444 .enable = s5pc100_d1_0_ctrl,
477 .ctrlbit = (1 << 4), 445 .ctrlbit = (1 << 4),
478 }, { 446 }, {
479 .name = "otg", 447 .name = "otg",
480 .id = -1,
481 .parent = &clk_div_d1_bus.clk, 448 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_0_ctrl, 449 .enable = s5pc100_d1_0_ctrl,
483 .ctrlbit = (1 << 3), 450 .ctrlbit = (1 << 3),
484 }, { 451 }, {
485 .name = "usbhost", 452 .name = "usbhost",
486 .id = -1,
487 .parent = &clk_div_d1_bus.clk, 453 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_0_ctrl, 454 .enable = s5pc100_d1_0_ctrl,
489 .ctrlbit = (1 << 2), 455 .ctrlbit = (1 << 2),
490 }, { 456 }, {
491 .name = "pdma", 457 .name = "pdma",
492 .id = 1, 458 .devname = "s3c-pl330.1",
493 .parent = &clk_div_d1_bus.clk, 459 .parent = &clk_div_d1_bus.clk,
494 .enable = s5pc100_d1_0_ctrl, 460 .enable = s5pc100_d1_0_ctrl,
495 .ctrlbit = (1 << 1), 461 .ctrlbit = (1 << 1),
496 }, { 462 }, {
497 .name = "pdma", 463 .name = "pdma",
498 .id = 0, 464 .devname = "s3c-pl330.0",
499 .parent = &clk_div_d1_bus.clk, 465 .parent = &clk_div_d1_bus.clk,
500 .enable = s5pc100_d1_0_ctrl, 466 .enable = s5pc100_d1_0_ctrl,
501 .ctrlbit = (1 << 0), 467 .ctrlbit = (1 << 0),
502 }, { 468 }, {
503 .name = "lcd", 469 .name = "lcd",
504 .id = -1,
505 .parent = &clk_div_d1_bus.clk, 470 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_1_ctrl, 471 .enable = s5pc100_d1_1_ctrl,
507 .ctrlbit = (1 << 0), 472 .ctrlbit = (1 << 0),
508 }, { 473 }, {
509 .name = "rotator", 474 .name = "rotator",
510 .id = -1,
511 .parent = &clk_div_d1_bus.clk, 475 .parent = &clk_div_d1_bus.clk,
512 .enable = s5pc100_d1_1_ctrl, 476 .enable = s5pc100_d1_1_ctrl,
513 .ctrlbit = (1 << 1), 477 .ctrlbit = (1 << 1),
514 }, { 478 }, {
515 .name = "fimc", 479 .name = "fimc",
516 .id = 0, 480 .devname = "s5p-fimc.0",
517 .parent = &clk_div_d1_bus.clk, 481 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_1_ctrl, 482 .enable = s5pc100_d1_1_ctrl,
519 .ctrlbit = (1 << 2), 483 .ctrlbit = (1 << 2),
520 }, { 484 }, {
521 .name = "fimc", 485 .name = "fimc",
522 .id = 1, 486 .devname = "s5p-fimc.1",
523 .parent = &clk_div_d1_bus.clk, 487 .parent = &clk_div_d1_bus.clk,
524 .enable = s5pc100_d1_1_ctrl, 488 .enable = s5pc100_d1_1_ctrl,
525 .ctrlbit = (1 << 3), 489 .ctrlbit = (1 << 3),
526 }, { 490 }, {
527 .name = "fimc", 491 .name = "fimc",
528 .id = 2, 492 .devname = "s5p-fimc.2",
529 .parent = &clk_div_d1_bus.clk,
530 .enable = s5pc100_d1_1_ctrl, 493 .enable = s5pc100_d1_1_ctrl,
531 .ctrlbit = (1 << 4), 494 .ctrlbit = (1 << 4),
532 }, { 495 }, {
533 .name = "jpeg", 496 .name = "jpeg",
534 .id = -1,
535 .parent = &clk_div_d1_bus.clk, 497 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_1_ctrl, 498 .enable = s5pc100_d1_1_ctrl,
537 .ctrlbit = (1 << 5), 499 .ctrlbit = (1 << 5),
538 }, { 500 }, {
539 .name = "mipi-dsim", 501 .name = "mipi-dsim",
540 .id = -1,
541 .parent = &clk_div_d1_bus.clk, 502 .parent = &clk_div_d1_bus.clk,
542 .enable = s5pc100_d1_1_ctrl, 503 .enable = s5pc100_d1_1_ctrl,
543 .ctrlbit = (1 << 6), 504 .ctrlbit = (1 << 6),
544 }, { 505 }, {
545 .name = "mipi-csis", 506 .name = "mipi-csis",
546 .id = -1,
547 .parent = &clk_div_d1_bus.clk, 507 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_1_ctrl, 508 .enable = s5pc100_d1_1_ctrl,
549 .ctrlbit = (1 << 7), 509 .ctrlbit = (1 << 7),
550 }, { 510 }, {
551 .name = "g3d", 511 .name = "g3d",
552 .id = 0,
553 .parent = &clk_div_d1_bus.clk, 512 .parent = &clk_div_d1_bus.clk,
554 .enable = s5pc100_d1_0_ctrl, 513 .enable = s5pc100_d1_0_ctrl,
555 .ctrlbit = (1 << 8), 514 .ctrlbit = (1 << 8),
556 }, { 515 }, {
557 .name = "tv", 516 .name = "tv",
558 .id = -1,
559 .parent = &clk_div_d1_bus.clk, 517 .parent = &clk_div_d1_bus.clk,
560 .enable = s5pc100_d1_2_ctrl, 518 .enable = s5pc100_d1_2_ctrl,
561 .ctrlbit = (1 << 0), 519 .ctrlbit = (1 << 0),
562 }, { 520 }, {
563 .name = "vp", 521 .name = "vp",
564 .id = -1,
565 .parent = &clk_div_d1_bus.clk, 522 .parent = &clk_div_d1_bus.clk,
566 .enable = s5pc100_d1_2_ctrl, 523 .enable = s5pc100_d1_2_ctrl,
567 .ctrlbit = (1 << 1), 524 .ctrlbit = (1 << 1),
568 }, { 525 }, {
569 .name = "mixer", 526 .name = "mixer",
570 .id = -1,
571 .parent = &clk_div_d1_bus.clk, 527 .parent = &clk_div_d1_bus.clk,
572 .enable = s5pc100_d1_2_ctrl, 528 .enable = s5pc100_d1_2_ctrl,
573 .ctrlbit = (1 << 2), 529 .ctrlbit = (1 << 2),
574 }, { 530 }, {
575 .name = "hdmi", 531 .name = "hdmi",
576 .id = -1,
577 .parent = &clk_div_d1_bus.clk, 532 .parent = &clk_div_d1_bus.clk,
578 .enable = s5pc100_d1_2_ctrl, 533 .enable = s5pc100_d1_2_ctrl,
579 .ctrlbit = (1 << 3), 534 .ctrlbit = (1 << 3),
580 }, { 535 }, {
581 .name = "mfc", 536 .name = "mfc",
582 .id = -1,
583 .parent = &clk_div_d1_bus.clk, 537 .parent = &clk_div_d1_bus.clk,
584 .enable = s5pc100_d1_2_ctrl, 538 .enable = s5pc100_d1_2_ctrl,
585 .ctrlbit = (1 << 4), 539 .ctrlbit = (1 << 4),
586 }, { 540 }, {
587 .name = "apc", 541 .name = "apc",
588 .id = -1,
589 .parent = &clk_div_d1_bus.clk, 542 .parent = &clk_div_d1_bus.clk,
590 .enable = s5pc100_d1_3_ctrl, 543 .enable = s5pc100_d1_3_ctrl,
591 .ctrlbit = (1 << 2), 544 .ctrlbit = (1 << 2),
592 }, { 545 }, {
593 .name = "iec", 546 .name = "iec",
594 .id = -1,
595 .parent = &clk_div_d1_bus.clk, 547 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_3_ctrl, 548 .enable = s5pc100_d1_3_ctrl,
597 .ctrlbit = (1 << 3), 549 .ctrlbit = (1 << 3),
598 }, { 550 }, {
599 .name = "systimer", 551 .name = "systimer",
600 .id = -1,
601 .parent = &clk_div_d1_bus.clk, 552 .parent = &clk_div_d1_bus.clk,
602 .enable = s5pc100_d1_3_ctrl, 553 .enable = s5pc100_d1_3_ctrl,
603 .ctrlbit = (1 << 7), 554 .ctrlbit = (1 << 7),
604 }, { 555 }, {
605 .name = "watchdog", 556 .name = "watchdog",
606 .id = -1,
607 .parent = &clk_div_d1_bus.clk, 557 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_3_ctrl, 558 .enable = s5pc100_d1_3_ctrl,
609 .ctrlbit = (1 << 8), 559 .ctrlbit = (1 << 8),
610 }, { 560 }, {
611 .name = "rtc", 561 .name = "rtc",
612 .id = -1,
613 .parent = &clk_div_d1_bus.clk, 562 .parent = &clk_div_d1_bus.clk,
614 .enable = s5pc100_d1_3_ctrl, 563 .enable = s5pc100_d1_3_ctrl,
615 .ctrlbit = (1 << 9), 564 .ctrlbit = (1 << 9),
616 }, { 565 }, {
617 .name = "i2c", 566 .name = "i2c",
618 .id = 0, 567 .devname = "s3c2440-i2c.0",
619 .parent = &clk_div_d1_bus.clk, 568 .parent = &clk_div_d1_bus.clk,
620 .enable = s5pc100_d1_4_ctrl, 569 .enable = s5pc100_d1_4_ctrl,
621 .ctrlbit = (1 << 4), 570 .ctrlbit = (1 << 4),
622 }, { 571 }, {
623 .name = "i2c", 572 .name = "i2c",
624 .id = 1, 573 .devname = "s3c2440-i2c.1",
625 .parent = &clk_div_d1_bus.clk, 574 .parent = &clk_div_d1_bus.clk,
626 .enable = s5pc100_d1_4_ctrl, 575 .enable = s5pc100_d1_4_ctrl,
627 .ctrlbit = (1 << 5), 576 .ctrlbit = (1 << 5),
628 }, { 577 }, {
629 .name = "spi", 578 .name = "spi",
630 .id = 0, 579 .devname = "s3c64xx-spi.0",
631 .parent = &clk_div_d1_bus.clk, 580 .parent = &clk_div_d1_bus.clk,
632 .enable = s5pc100_d1_4_ctrl, 581 .enable = s5pc100_d1_4_ctrl,
633 .ctrlbit = (1 << 6), 582 .ctrlbit = (1 << 6),
634 }, { 583 }, {
635 .name = "spi", 584 .name = "spi",
636 .id = 1, 585 .devname = "s3c64xx-spi.1",
637 .parent = &clk_div_d1_bus.clk, 586 .parent = &clk_div_d1_bus.clk,
638 .enable = s5pc100_d1_4_ctrl, 587 .enable = s5pc100_d1_4_ctrl,
639 .ctrlbit = (1 << 7), 588 .ctrlbit = (1 << 7),
640 }, { 589 }, {
641 .name = "spi", 590 .name = "spi",
642 .id = 2, 591 .devname = "s3c64xx-spi.2",
643 .parent = &clk_div_d1_bus.clk, 592 .parent = &clk_div_d1_bus.clk,
644 .enable = s5pc100_d1_4_ctrl, 593 .enable = s5pc100_d1_4_ctrl,
645 .ctrlbit = (1 << 8), 594 .ctrlbit = (1 << 8),
646 }, { 595 }, {
647 .name = "irda", 596 .name = "irda",
648 .id = -1,
649 .parent = &clk_div_d1_bus.clk, 597 .parent = &clk_div_d1_bus.clk,
650 .enable = s5pc100_d1_4_ctrl, 598 .enable = s5pc100_d1_4_ctrl,
651 .ctrlbit = (1 << 9), 599 .ctrlbit = (1 << 9),
652 }, { 600 }, {
653 .name = "ccan", 601 .name = "ccan",
654 .id = 0,
655 .parent = &clk_div_d1_bus.clk, 602 .parent = &clk_div_d1_bus.clk,
656 .enable = s5pc100_d1_4_ctrl, 603 .enable = s5pc100_d1_4_ctrl,
657 .ctrlbit = (1 << 10), 604 .ctrlbit = (1 << 10),
658 }, { 605 }, {
659 .name = "ccan", 606 .name = "ccan",
660 .id = 1,
661 .parent = &clk_div_d1_bus.clk, 607 .parent = &clk_div_d1_bus.clk,
662 .enable = s5pc100_d1_4_ctrl, 608 .enable = s5pc100_d1_4_ctrl,
663 .ctrlbit = (1 << 11), 609 .ctrlbit = (1 << 11),
664 }, { 610 }, {
665 .name = "hsitx", 611 .name = "hsitx",
666 .id = -1,
667 .parent = &clk_div_d1_bus.clk, 612 .parent = &clk_div_d1_bus.clk,
668 .enable = s5pc100_d1_4_ctrl, 613 .enable = s5pc100_d1_4_ctrl,
669 .ctrlbit = (1 << 12), 614 .ctrlbit = (1 << 12),
670 }, { 615 }, {
671 .name = "hsirx", 616 .name = "hsirx",
672 .id = -1,
673 .parent = &clk_div_d1_bus.clk, 617 .parent = &clk_div_d1_bus.clk,
674 .enable = s5pc100_d1_4_ctrl, 618 .enable = s5pc100_d1_4_ctrl,
675 .ctrlbit = (1 << 13), 619 .ctrlbit = (1 << 13),
676 }, { 620 }, {
677 .name = "iis", 621 .name = "iis",
678 .id = 0, 622 .devname = "samsung-i2s.0",
679 .parent = &clk_div_pclkd1.clk, 623 .parent = &clk_div_pclkd1.clk,
680 .enable = s5pc100_d1_5_ctrl, 624 .enable = s5pc100_d1_5_ctrl,
681 .ctrlbit = (1 << 0), 625 .ctrlbit = (1 << 0),
682 }, { 626 }, {
683 .name = "iis", 627 .name = "iis",
684 .id = 1, 628 .devname = "samsung-i2s.1",
685 .parent = &clk_div_pclkd1.clk, 629 .parent = &clk_div_pclkd1.clk,
686 .enable = s5pc100_d1_5_ctrl, 630 .enable = s5pc100_d1_5_ctrl,
687 .ctrlbit = (1 << 1), 631 .ctrlbit = (1 << 1),
688 }, { 632 }, {
689 .name = "iis", 633 .name = "iis",
690 .id = 2, 634 .devname = "samsung-i2s.2",
691 .parent = &clk_div_pclkd1.clk, 635 .parent = &clk_div_pclkd1.clk,
692 .enable = s5pc100_d1_5_ctrl, 636 .enable = s5pc100_d1_5_ctrl,
693 .ctrlbit = (1 << 2), 637 .ctrlbit = (1 << 2),
694 }, { 638 }, {
695 .name = "ac97", 639 .name = "ac97",
696 .id = -1,
697 .parent = &clk_div_pclkd1.clk, 640 .parent = &clk_div_pclkd1.clk,
698 .enable = s5pc100_d1_5_ctrl, 641 .enable = s5pc100_d1_5_ctrl,
699 .ctrlbit = (1 << 3), 642 .ctrlbit = (1 << 3),
700 }, { 643 }, {
701 .name = "pcm", 644 .name = "pcm",
702 .id = 0, 645 .devname = "samsung-pcm.0",
703 .parent = &clk_div_pclkd1.clk, 646 .parent = &clk_div_pclkd1.clk,
704 .enable = s5pc100_d1_5_ctrl, 647 .enable = s5pc100_d1_5_ctrl,
705 .ctrlbit = (1 << 4), 648 .ctrlbit = (1 << 4),
706 }, { 649 }, {
707 .name = "pcm", 650 .name = "pcm",
708 .id = 1, 651 .devname = "samsung-pcm.1",
709 .parent = &clk_div_pclkd1.clk, 652 .parent = &clk_div_pclkd1.clk,
710 .enable = s5pc100_d1_5_ctrl, 653 .enable = s5pc100_d1_5_ctrl,
711 .ctrlbit = (1 << 5), 654 .ctrlbit = (1 << 5),
712 }, { 655 }, {
713 .name = "spdif", 656 .name = "spdif",
714 .id = -1,
715 .parent = &clk_div_pclkd1.clk, 657 .parent = &clk_div_pclkd1.clk,
716 .enable = s5pc100_d1_5_ctrl, 658 .enable = s5pc100_d1_5_ctrl,
717 .ctrlbit = (1 << 6), 659 .ctrlbit = (1 << 6),
718 }, { 660 }, {
719 .name = "adc", 661 .name = "adc",
720 .id = -1,
721 .parent = &clk_div_pclkd1.clk, 662 .parent = &clk_div_pclkd1.clk,
722 .enable = s5pc100_d1_5_ctrl, 663 .enable = s5pc100_d1_5_ctrl,
723 .ctrlbit = (1 << 7), 664 .ctrlbit = (1 << 7),
724 }, { 665 }, {
725 .name = "keypad", 666 .name = "keypad",
726 .id = -1,
727 .parent = &clk_div_pclkd1.clk, 667 .parent = &clk_div_pclkd1.clk,
728 .enable = s5pc100_d1_5_ctrl, 668 .enable = s5pc100_d1_5_ctrl,
729 .ctrlbit = (1 << 8), 669 .ctrlbit = (1 << 8),
730 }, { 670 }, {
731 .name = "spi_48m", 671 .name = "spi_48m",
732 .id = 0, 672 .devname = "s3c64xx-spi.0",
733 .parent = &clk_mout_48m.clk, 673 .parent = &clk_mout_48m.clk,
734 .enable = s5pc100_sclk0_ctrl, 674 .enable = s5pc100_sclk0_ctrl,
735 .ctrlbit = (1 << 7), 675 .ctrlbit = (1 << 7),
736 }, { 676 }, {
737 .name = "spi_48m", 677 .name = "spi_48m",
738 .id = 1, 678 .devname = "s3c64xx-spi.1",
739 .parent = &clk_mout_48m.clk, 679 .parent = &clk_mout_48m.clk,
740 .enable = s5pc100_sclk0_ctrl, 680 .enable = s5pc100_sclk0_ctrl,
741 .ctrlbit = (1 << 8), 681 .ctrlbit = (1 << 8),
742 }, { 682 }, {
743 .name = "spi_48m", 683 .name = "spi_48m",
744 .id = 2, 684 .devname = "s3c64xx-spi.2",
745 .parent = &clk_mout_48m.clk, 685 .parent = &clk_mout_48m.clk,
746 .enable = s5pc100_sclk0_ctrl, 686 .enable = s5pc100_sclk0_ctrl,
747 .ctrlbit = (1 << 9), 687 .ctrlbit = (1 << 9),
748 }, { 688 }, {
749 .name = "mmc_48m", 689 .name = "mmc_48m",
750 .id = 0, 690 .devname = "s3c-sdhci.0",
751 .parent = &clk_mout_48m.clk, 691 .parent = &clk_mout_48m.clk,
752 .enable = s5pc100_sclk0_ctrl, 692 .enable = s5pc100_sclk0_ctrl,
753 .ctrlbit = (1 << 15), 693 .ctrlbit = (1 << 15),
754 }, { 694 }, {
755 .name = "mmc_48m", 695 .name = "mmc_48m",
756 .id = 1, 696 .devname = "s3c-sdhci.1",
757 .parent = &clk_mout_48m.clk, 697 .parent = &clk_mout_48m.clk,
758 .enable = s5pc100_sclk0_ctrl, 698 .enable = s5pc100_sclk0_ctrl,
759 .ctrlbit = (1 << 16), 699 .ctrlbit = (1 << 16),
760 }, { 700 }, {
761 .name = "mmc_48m", 701 .name = "mmc_48m",
762 .id = 2, 702 .devname = "s3c-sdhci.2",
763 .parent = &clk_mout_48m.clk, 703 .parent = &clk_mout_48m.clk,
764 .enable = s5pc100_sclk0_ctrl, 704 .enable = s5pc100_sclk0_ctrl,
765 .ctrlbit = (1 << 17), 705 .ctrlbit = (1 << 17),
@@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
768 708
769static struct clk clk_vclk54m = { 709static struct clk clk_vclk54m = {
770 .name = "vclk_54m", 710 .name = "vclk_54m",
771 .id = -1,
772 .rate = 54000000, 711 .rate = 54000000,
773}; 712};
774 713
775static struct clk clk_i2scdclk0 = { 714static struct clk clk_i2scdclk0 = {
776 .name = "i2s_cdclk0", 715 .name = "i2s_cdclk0",
777 .id = -1,
778}; 716};
779 717
780static struct clk clk_i2scdclk1 = { 718static struct clk clk_i2scdclk1 = {
781 .name = "i2s_cdclk1", 719 .name = "i2s_cdclk1",
782 .id = -1,
783}; 720};
784 721
785static struct clk clk_i2scdclk2 = { 722static struct clk clk_i2scdclk2 = {
786 .name = "i2s_cdclk2", 723 .name = "i2s_cdclk2",
787 .id = -1,
788}; 724};
789 725
790static struct clk clk_pcmcdclk0 = { 726static struct clk clk_pcmcdclk0 = {
791 .name = "pcm_cdclk0", 727 .name = "pcm_cdclk0",
792 .id = -1,
793}; 728};
794 729
795static struct clk clk_pcmcdclk1 = { 730static struct clk clk_pcmcdclk1 = {
796 .name = "pcm_cdclk1", 731 .name = "pcm_cdclk1",
797 .id = -1,
798}; 732};
799 733
800static struct clk *clk_src_group1_list[] = { 734static struct clk *clk_src_group1_list[] = {
@@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
836static struct clksrc_clk clk_sclk_audio0 = { 770static struct clksrc_clk clk_sclk_audio0 = {
837 .clk = { 771 .clk = {
838 .name = "sclk_audio", 772 .name = "sclk_audio",
839 .id = 0, 773 .devname = "samsung-pcm.0",
840 .ctrlbit = (1 << 8), 774 .ctrlbit = (1 << 8),
841 .enable = s5pc100_sclk1_ctrl, 775 .enable = s5pc100_sclk1_ctrl,
842 }, 776 },
@@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
862static struct clksrc_clk clk_sclk_audio1 = { 796static struct clksrc_clk clk_sclk_audio1 = {
863 .clk = { 797 .clk = {
864 .name = "sclk_audio", 798 .name = "sclk_audio",
865 .id = 1, 799 .devname = "samsung-pcm.1",
866 .ctrlbit = (1 << 9), 800 .ctrlbit = (1 << 9),
867 .enable = s5pc100_sclk1_ctrl, 801 .enable = s5pc100_sclk1_ctrl,
868 }, 802 },
@@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
887static struct clksrc_clk clk_sclk_audio2 = { 821static struct clksrc_clk clk_sclk_audio2 = {
888 .clk = { 822 .clk = {
889 .name = "sclk_audio", 823 .name = "sclk_audio",
890 .id = 2, 824 .devname = "samsung-pcm.2",
891 .ctrlbit = (1 << 10), 825 .ctrlbit = (1 << 10),
892 .enable = s5pc100_sclk1_ctrl, 826 .enable = s5pc100_sclk1_ctrl,
893 }, 827 },
@@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = {
1014static struct clksrc_clk clk_sclk_spdif = { 948static struct clksrc_clk clk_sclk_spdif = {
1015 .clk = { 949 .clk = {
1016 .name = "sclk_spdif", 950 .name = "sclk_spdif",
1017 .id = -1,
1018 .ctrlbit = (1 << 11), 951 .ctrlbit = (1 << 11),
1019 .enable = s5pc100_sclk1_ctrl, 952 .enable = s5pc100_sclk1_ctrl,
1020 .ops = &s5pc100_sclk_spdif_ops, 953 .ops = &s5pc100_sclk_spdif_ops,
@@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
1027 { 960 {
1028 .clk = { 961 .clk = {
1029 .name = "sclk_spi", 962 .name = "sclk_spi",
1030 .id = 0, 963 .devname = "s3c64xx-spi.0",
1031 .ctrlbit = (1 << 4), 964 .ctrlbit = (1 << 4),
1032 .enable = s5pc100_sclk0_ctrl, 965 .enable = s5pc100_sclk0_ctrl,
1033 966
@@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = {
1038 }, { 971 }, {
1039 .clk = { 972 .clk = {
1040 .name = "sclk_spi", 973 .name = "sclk_spi",
1041 .id = 1, 974 .devname = "s3c64xx-spi.1",
1042 .ctrlbit = (1 << 5), 975 .ctrlbit = (1 << 5),
1043 .enable = s5pc100_sclk0_ctrl, 976 .enable = s5pc100_sclk0_ctrl,
1044 977
@@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
1049 }, { 982 }, {
1050 .clk = { 983 .clk = {
1051 .name = "sclk_spi", 984 .name = "sclk_spi",
1052 .id = 2, 985 .devname = "s3c64xx-spi.2",
1053 .ctrlbit = (1 << 6), 986 .ctrlbit = (1 << 6),
1054 .enable = s5pc100_sclk0_ctrl, 987 .enable = s5pc100_sclk0_ctrl,
1055 988
@@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = {
1060 }, { 993 }, {
1061 .clk = { 994 .clk = {
1062 .name = "uclk1", 995 .name = "uclk1",
1063 .id = -1,
1064 .ctrlbit = (1 << 3), 996 .ctrlbit = (1 << 3),
1065 .enable = s5pc100_sclk0_ctrl, 997 .enable = s5pc100_sclk0_ctrl,
1066 998
@@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = {
1071 }, { 1003 }, {
1072 .clk = { 1004 .clk = {
1073 .name = "sclk_mixer", 1005 .name = "sclk_mixer",
1074 .id = -1,
1075 .ctrlbit = (1 << 6), 1006 .ctrlbit = (1 << 6),
1076 .enable = s5pc100_sclk0_ctrl, 1007 .enable = s5pc100_sclk0_ctrl,
1077 1008
@@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = {
1081 }, { 1012 }, {
1082 .clk = { 1013 .clk = {
1083 .name = "sclk_lcd", 1014 .name = "sclk_lcd",
1084 .id = -1,
1085 .ctrlbit = (1 << 0), 1015 .ctrlbit = (1 << 0),
1086 .enable = s5pc100_sclk1_ctrl, 1016 .enable = s5pc100_sclk1_ctrl,
1087 1017
@@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = {
1092 }, { 1022 }, {
1093 .clk = { 1023 .clk = {
1094 .name = "sclk_fimc", 1024 .name = "sclk_fimc",
1095 .id = 0, 1025 .devname = "s5p-fimc.0",
1096 .ctrlbit = (1 << 1), 1026 .ctrlbit = (1 << 1),
1097 .enable = s5pc100_sclk1_ctrl, 1027 .enable = s5pc100_sclk1_ctrl,
1098 1028
@@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = {
1103 }, { 1033 }, {
1104 .clk = { 1034 .clk = {
1105 .name = "sclk_fimc", 1035 .name = "sclk_fimc",
1106 .id = 1, 1036 .devname = "s5p-fimc.1",
1107 .ctrlbit = (1 << 2), 1037 .ctrlbit = (1 << 2),
1108 .enable = s5pc100_sclk1_ctrl, 1038 .enable = s5pc100_sclk1_ctrl,
1109 1039
@@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
1114 }, { 1044 }, {
1115 .clk = { 1045 .clk = {
1116 .name = "sclk_fimc", 1046 .name = "sclk_fimc",
1117 .id = 2, 1047 .devname = "s5p-fimc.2",
1118 .ctrlbit = (1 << 3), 1048 .ctrlbit = (1 << 3),
1119 .enable = s5pc100_sclk1_ctrl, 1049 .enable = s5pc100_sclk1_ctrl,
1120 1050
@@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = {
1125 }, { 1055 }, {
1126 .clk = { 1056 .clk = {
1127 .name = "sclk_mmc", 1057 .name = "sclk_mmc",
1128 .id = 0, 1058 .devname = "s3c-sdhci.0",
1129 .ctrlbit = (1 << 12), 1059 .ctrlbit = (1 << 12),
1130 .enable = s5pc100_sclk1_ctrl, 1060 .enable = s5pc100_sclk1_ctrl,
1131 1061
@@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
1136 }, { 1066 }, {
1137 .clk = { 1067 .clk = {
1138 .name = "sclk_mmc", 1068 .name = "sclk_mmc",
1139 .id = 1, 1069 .devname = "s3c-sdhci.1",
1140 .ctrlbit = (1 << 13), 1070 .ctrlbit = (1 << 13),
1141 .enable = s5pc100_sclk1_ctrl, 1071 .enable = s5pc100_sclk1_ctrl,
1142 1072
@@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = {
1147 }, { 1077 }, {
1148 .clk = { 1078 .clk = {
1149 .name = "sclk_mmc", 1079 .name = "sclk_mmc",
1150 .id = 2, 1080 .devname = "s3c-sdhci.2",
1151 .ctrlbit = (1 << 14), 1081 .ctrlbit = (1 << 14),
1152 .enable = s5pc100_sclk1_ctrl, 1082 .enable = s5pc100_sclk1_ctrl,
1153 1083
@@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = {
1158 }, { 1088 }, {
1159 .clk = { 1089 .clk = {
1160 .name = "sclk_irda", 1090 .name = "sclk_irda",
1161 .id = 2,
1162 .ctrlbit = (1 << 10), 1091 .ctrlbit = (1 << 10),
1163 .enable = s5pc100_sclk0_ctrl, 1092 .enable = s5pc100_sclk0_ctrl,
1164 1093
@@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = {
1169 }, { 1098 }, {
1170 .clk = { 1099 .clk = {
1171 .name = "sclk_irda", 1100 .name = "sclk_irda",
1172 .id = -1,
1173 .ctrlbit = (1 << 10), 1101 .ctrlbit = (1 << 10),
1174 .enable = s5pc100_sclk0_ctrl, 1102 .enable = s5pc100_sclk0_ctrl,
1175 1103
@@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = {
1180 }, { 1108 }, {
1181 .clk = { 1109 .clk = {
1182 .name = "sclk_pwi", 1110 .name = "sclk_pwi",
1183 .id = -1,
1184 .ctrlbit = (1 << 1), 1111 .ctrlbit = (1 << 1),
1185 .enable = s5pc100_sclk0_ctrl, 1112 .enable = s5pc100_sclk0_ctrl,
1186 1113
@@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = {
1191 }, { 1118 }, {
1192 .clk = { 1119 .clk = {
1193 .name = "sclk_uhost", 1120 .name = "sclk_uhost",
1194 .id = -1,
1195 .ctrlbit = (1 << 11), 1121 .ctrlbit = (1 << 11),
1196 .enable = s5pc100_sclk0_ctrl, 1122 .enable = s5pc100_sclk0_ctrl,
1197 1123
@@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1291static struct clk init_clocks[] = { 1217static struct clk init_clocks[] = {
1292 { 1218 {
1293 .name = "tzic", 1219 .name = "tzic",
1294 .id = -1,
1295 .parent = &clk_div_d0_bus.clk, 1220 .parent = &clk_div_d0_bus.clk,
1296 .enable = s5pc100_d0_0_ctrl, 1221 .enable = s5pc100_d0_0_ctrl,
1297 .ctrlbit = (1 << 1), 1222 .ctrlbit = (1 << 1),
1298 }, { 1223 }, {
1299 .name = "intc", 1224 .name = "intc",
1300 .id = -1,
1301 .parent = &clk_div_d0_bus.clk, 1225 .parent = &clk_div_d0_bus.clk,
1302 .enable = s5pc100_d0_0_ctrl, 1226 .enable = s5pc100_d0_0_ctrl,
1303 .ctrlbit = (1 << 0), 1227 .ctrlbit = (1 << 0),
1304 }, { 1228 }, {
1305 .name = "ebi", 1229 .name = "ebi",
1306 .id = -1,
1307 .parent = &clk_div_d0_bus.clk, 1230 .parent = &clk_div_d0_bus.clk,
1308 .enable = s5pc100_d0_1_ctrl, 1231 .enable = s5pc100_d0_1_ctrl,
1309 .ctrlbit = (1 << 5), 1232 .ctrlbit = (1 << 5),
1310 }, { 1233 }, {
1311 .name = "intmem", 1234 .name = "intmem",
1312 .id = -1,
1313 .parent = &clk_div_d0_bus.clk, 1235 .parent = &clk_div_d0_bus.clk,
1314 .enable = s5pc100_d0_1_ctrl, 1236 .enable = s5pc100_d0_1_ctrl,
1315 .ctrlbit = (1 << 4), 1237 .ctrlbit = (1 << 4),
1316 }, { 1238 }, {
1317 .name = "sromc", 1239 .name = "sromc",
1318 .id = -1,
1319 .parent = &clk_div_d0_bus.clk, 1240 .parent = &clk_div_d0_bus.clk,
1320 .enable = s5pc100_d0_1_ctrl, 1241 .enable = s5pc100_d0_1_ctrl,
1321 .ctrlbit = (1 << 1), 1242 .ctrlbit = (1 << 1),
1322 }, { 1243 }, {
1323 .name = "dmc", 1244 .name = "dmc",
1324 .id = -1,
1325 .parent = &clk_div_d0_bus.clk, 1245 .parent = &clk_div_d0_bus.clk,
1326 .enable = s5pc100_d0_1_ctrl, 1246 .enable = s5pc100_d0_1_ctrl,
1327 .ctrlbit = (1 << 0), 1247 .ctrlbit = (1 << 0),
1328 }, { 1248 }, {
1329 .name = "chipid", 1249 .name = "chipid",
1330 .id = -1,
1331 .parent = &clk_div_d0_bus.clk, 1250 .parent = &clk_div_d0_bus.clk,
1332 .enable = s5pc100_d0_1_ctrl, 1251 .enable = s5pc100_d0_1_ctrl,
1333 .ctrlbit = (1 << 0), 1252 .ctrlbit = (1 << 0),
1334 }, { 1253 }, {
1335 .name = "gpio", 1254 .name = "gpio",
1336 .id = -1,
1337 .parent = &clk_div_d1_bus.clk, 1255 .parent = &clk_div_d1_bus.clk,
1338 .enable = s5pc100_d1_3_ctrl, 1256 .enable = s5pc100_d1_3_ctrl,
1339 .ctrlbit = (1 << 1), 1257 .ctrlbit = (1 << 1),
1340 }, { 1258 }, {
1341 .name = "uart", 1259 .name = "uart",
1342 .id = 0, 1260 .devname = "s3c6400-uart.0",
1343 .parent = &clk_div_d1_bus.clk, 1261 .parent = &clk_div_d1_bus.clk,
1344 .enable = s5pc100_d1_4_ctrl, 1262 .enable = s5pc100_d1_4_ctrl,
1345 .ctrlbit = (1 << 0), 1263 .ctrlbit = (1 << 0),
1346 }, { 1264 }, {
1347 .name = "uart", 1265 .name = "uart",
1348 .id = 1, 1266 .devname = "s3c6400-uart.1",
1349 .parent = &clk_div_d1_bus.clk, 1267 .parent = &clk_div_d1_bus.clk,
1350 .enable = s5pc100_d1_4_ctrl, 1268 .enable = s5pc100_d1_4_ctrl,
1351 .ctrlbit = (1 << 1), 1269 .ctrlbit = (1 << 1),
1352 }, { 1270 }, {
1353 .name = "uart", 1271 .name = "uart",
1354 .id = 2, 1272 .devname = "s3c6400-uart.2",
1355 .parent = &clk_div_d1_bus.clk, 1273 .parent = &clk_div_d1_bus.clk,
1356 .enable = s5pc100_d1_4_ctrl, 1274 .enable = s5pc100_d1_4_ctrl,
1357 .ctrlbit = (1 << 2), 1275 .ctrlbit = (1 << 2),
1358 }, { 1276 }, {
1359 .name = "uart", 1277 .name = "uart",
1360 .id = 3, 1278 .devname = "s3c6400-uart.3",
1361 .parent = &clk_div_d1_bus.clk, 1279 .parent = &clk_div_d1_bus.clk,
1362 .enable = s5pc100_d1_4_ctrl, 1280 .enable = s5pc100_d1_4_ctrl,
1363 .ctrlbit = (1 << 3), 1281 .ctrlbit = (1 << 3),
1364 }, { 1282 }, {
1365 .name = "timers", 1283 .name = "timers",
1366 .id = -1,
1367 .parent = &clk_div_d1_bus.clk, 1284 .parent = &clk_div_d1_bus.clk,
1368 .enable = s5pc100_d1_3_ctrl, 1285 .enable = s5pc100_d1_3_ctrl,
1369 .ctrlbit = (1 << 6), 1286 .ctrlbit = (1 << 6),
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 37b5a97594a5..a06acce7b731 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -90,6 +90,7 @@ config MACH_GONI
90 select S3C_DEV_HSMMC2 90 select S3C_DEV_HSMMC2
91 select S3C_DEV_I2C1 91 select S3C_DEV_I2C1
92 select S3C_DEV_I2C2 92 select S3C_DEV_I2C2
93 select S5P_DEV_MFC
93 select S3C_DEV_USB_HSOTG 94 select S3C_DEV_USB_HSOTG
94 select S5P_DEV_ONENAND 95 select S5P_DEV_ONENAND
95 select SAMSUNG_DEV_KEYPAD 96 select SAMSUNG_DEV_KEYPAD
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d599499cefe..1404a4c43770 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
36static struct clksrc_clk clk_mout_apll = { 36static struct clksrc_clk clk_mout_apll = {
37 .clk = { 37 .clk = {
38 .name = "mout_apll", 38 .name = "mout_apll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_apll, 40 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
45static struct clksrc_clk clk_mout_epll = { 44static struct clksrc_clk clk_mout_epll = {
46 .clk = { 45 .clk = {
47 .name = "mout_epll", 46 .name = "mout_epll",
48 .id = -1,
49 }, 47 },
50 .sources = &clk_src_epll, 48 .sources = &clk_src_epll,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
54static struct clksrc_clk clk_mout_mpll = { 52static struct clksrc_clk clk_mout_mpll = {
55 .clk = { 53 .clk = {
56 .name = "mout_mpll", 54 .name = "mout_mpll",
57 .id = -1,
58 }, 55 },
59 .sources = &clk_src_mpll, 56 .sources = &clk_src_mpll,
60 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
73static struct clksrc_clk clk_armclk = { 70static struct clksrc_clk clk_armclk = {
74 .clk = { 71 .clk = {
75 .name = "armclk", 72 .name = "armclk",
76 .id = -1,
77 }, 73 },
78 .sources = &clkset_armclk, 74 .sources = &clkset_armclk,
79 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
83static struct clksrc_clk clk_hclk_msys = { 79static struct clksrc_clk clk_hclk_msys = {
84 .clk = { 80 .clk = {
85 .name = "hclk_msys", 81 .name = "hclk_msys",
86 .id = -1,
87 .parent = &clk_armclk.clk, 82 .parent = &clk_armclk.clk,
88 }, 83 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
92static struct clksrc_clk clk_pclk_msys = { 87static struct clksrc_clk clk_pclk_msys = {
93 .clk = { 88 .clk = {
94 .name = "pclk_msys", 89 .name = "pclk_msys",
95 .id = -1,
96 .parent = &clk_hclk_msys.clk, 90 .parent = &clk_hclk_msys.clk,
97 }, 91 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
101static struct clksrc_clk clk_sclk_a2m = { 95static struct clksrc_clk clk_sclk_a2m = {
102 .clk = { 96 .clk = {
103 .name = "sclk_a2m", 97 .name = "sclk_a2m",
104 .id = -1,
105 .parent = &clk_mout_apll.clk, 98 .parent = &clk_mout_apll.clk,
106 }, 99 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
120static struct clksrc_clk clk_hclk_dsys = { 113static struct clksrc_clk clk_hclk_dsys = {
121 .clk = { 114 .clk = {
122 .name = "hclk_dsys", 115 .name = "hclk_dsys",
123 .id = -1,
124 }, 116 },
125 .sources = &clkset_hclk_sys, 117 .sources = &clkset_hclk_sys,
126 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
130static struct clksrc_clk clk_pclk_dsys = { 122static struct clksrc_clk clk_pclk_dsys = {
131 .clk = { 123 .clk = {
132 .name = "pclk_dsys", 124 .name = "pclk_dsys",
133 .id = -1,
134 .parent = &clk_hclk_dsys.clk, 125 .parent = &clk_hclk_dsys.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
139static struct clksrc_clk clk_hclk_psys = { 130static struct clksrc_clk clk_hclk_psys = {
140 .clk = { 131 .clk = {
141 .name = "hclk_psys", 132 .name = "hclk_psys",
142 .id = -1,
143 }, 133 },
144 .sources = &clkset_hclk_sys, 134 .sources = &clkset_hclk_sys,
145 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
149static struct clksrc_clk clk_pclk_psys = { 139static struct clksrc_clk clk_pclk_psys = {
150 .clk = { 140 .clk = {
151 .name = "pclk_psys", 141 .name = "pclk_psys",
152 .id = -1,
153 .parent = &clk_hclk_psys.clk, 142 .parent = &clk_hclk_psys.clk,
154 }, 143 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187 176
188static struct clk clk_sclk_hdmi27m = { 177static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m", 178 .name = "sclk_hdmi27m",
190 .id = -1,
191 .rate = 27000000, 179 .rate = 27000000,
192}; 180};
193 181
194static struct clk clk_sclk_hdmiphy = { 182static struct clk clk_sclk_hdmiphy = {
195 .name = "sclk_hdmiphy", 183 .name = "sclk_hdmiphy",
196 .id = -1,
197}; 184};
198 185
199static struct clk clk_sclk_usbphy0 = { 186static struct clk clk_sclk_usbphy0 = {
200 .name = "sclk_usbphy0", 187 .name = "sclk_usbphy0",
201 .id = -1,
202}; 188};
203 189
204static struct clk clk_sclk_usbphy1 = { 190static struct clk clk_sclk_usbphy1 = {
205 .name = "sclk_usbphy1", 191 .name = "sclk_usbphy1",
206 .id = -1,
207}; 192};
208 193
209static struct clk clk_pcmcdclk0 = { 194static struct clk clk_pcmcdclk0 = {
210 .name = "pcmcdclk", 195 .name = "pcmcdclk",
211 .id = -1,
212}; 196};
213 197
214static struct clk clk_pcmcdclk1 = { 198static struct clk clk_pcmcdclk1 = {
215 .name = "pcmcdclk", 199 .name = "pcmcdclk",
216 .id = -1,
217}; 200};
218 201
219static struct clk clk_pcmcdclk2 = { 202static struct clk clk_pcmcdclk2 = {
220 .name = "pcmcdclk", 203 .name = "pcmcdclk",
221 .id = -1,
222}; 204};
223 205
224static struct clk *clkset_vpllsrc_list[] = { 206static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
234static struct clksrc_clk clk_vpllsrc = { 216static struct clksrc_clk clk_vpllsrc = {
235 .clk = { 217 .clk = {
236 .name = "vpll_src", 218 .name = "vpll_src",
237 .id = -1,
238 .enable = s5pv210_clk_mask0_ctrl, 219 .enable = s5pv210_clk_mask0_ctrl,
239 .ctrlbit = (1 << 7), 220 .ctrlbit = (1 << 7),
240 }, 221 },
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
255static struct clksrc_clk clk_sclk_vpll = { 236static struct clksrc_clk clk_sclk_vpll = {
256 .clk = { 237 .clk = {
257 .name = "sclk_vpll", 238 .name = "sclk_vpll",
258 .id = -1,
259 }, 239 },
260 .sources = &clkset_sclk_vpll, 240 .sources = &clkset_sclk_vpll,
261 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 241 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
276static struct clksrc_clk clk_mout_dmc0 = { 256static struct clksrc_clk clk_mout_dmc0 = {
277 .clk = { 257 .clk = {
278 .name = "mout_dmc0", 258 .name = "mout_dmc0",
279 .id = -1,
280 }, 259 },
281 .sources = &clkset_moutdmc0src, 260 .sources = &clkset_moutdmc0src,
282 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 261 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
285static struct clksrc_clk clk_sclk_dmc0 = { 264static struct clksrc_clk clk_sclk_dmc0 = {
286 .clk = { 265 .clk = {
287 .name = "sclk_dmc0", 266 .name = "sclk_dmc0",
288 .id = -1,
289 .parent = &clk_mout_dmc0.clk, 267 .parent = &clk_mout_dmc0.clk,
290 }, 268 },
291 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, 269 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,175 @@ static struct clk_ops clk_fout_apll_ops = {
312static struct clk init_clocks_off[] = { 290static struct clk init_clocks_off[] = {
313 { 291 {
314 .name = "pdma", 292 .name = "pdma",
315 .id = 0, 293 .devname = "s3c-pl330.0",
316 .parent = &clk_hclk_psys.clk, 294 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip0_ctrl, 295 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 3), 296 .ctrlbit = (1 << 3),
319 }, { 297 }, {
320 .name = "pdma", 298 .name = "pdma",
321 .id = 1, 299 .devname = "s3c-pl330.1",
322 .parent = &clk_hclk_psys.clk, 300 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip0_ctrl, 301 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 4), 302 .ctrlbit = (1 << 4),
325 }, { 303 }, {
326 .name = "rot", 304 .name = "rot",
327 .id = -1,
328 .parent = &clk_hclk_dsys.clk, 305 .parent = &clk_hclk_dsys.clk,
329 .enable = s5pv210_clk_ip0_ctrl, 306 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1<<29), 307 .ctrlbit = (1<<29),
331 }, { 308 }, {
332 .name = "fimc", 309 .name = "fimc",
333 .id = 0, 310 .devname = "s5pv210-fimc.0",
334 .parent = &clk_hclk_dsys.clk, 311 .parent = &clk_hclk_dsys.clk,
335 .enable = s5pv210_clk_ip0_ctrl, 312 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 24), 313 .ctrlbit = (1 << 24),
337 }, { 314 }, {
338 .name = "fimc", 315 .name = "fimc",
339 .id = 1, 316 .devname = "s5pv210-fimc.1",
340 .parent = &clk_hclk_dsys.clk, 317 .parent = &clk_hclk_dsys.clk,
341 .enable = s5pv210_clk_ip0_ctrl, 318 .enable = s5pv210_clk_ip0_ctrl,
342 .ctrlbit = (1 << 25), 319 .ctrlbit = (1 << 25),
343 }, { 320 }, {
344 .name = "fimc", 321 .name = "fimc",
345 .id = 2, 322 .devname = "s5pv210-fimc.2",
346 .parent = &clk_hclk_dsys.clk, 323 .parent = &clk_hclk_dsys.clk,
347 .enable = s5pv210_clk_ip0_ctrl, 324 .enable = s5pv210_clk_ip0_ctrl,
348 .ctrlbit = (1 << 26), 325 .ctrlbit = (1 << 26),
349 }, { 326 }, {
327 .name = "mfc",
328 .devname = "s5p-mfc",
329 .parent = &clk_pclk_psys.clk,
330 .enable = s5pv210_clk_ip0_ctrl,
331 .ctrlbit = (1 << 16),
332 }, {
350 .name = "otg", 333 .name = "otg",
351 .id = -1,
352 .parent = &clk_hclk_psys.clk, 334 .parent = &clk_hclk_psys.clk,
353 .enable = s5pv210_clk_ip1_ctrl, 335 .enable = s5pv210_clk_ip1_ctrl,
354 .ctrlbit = (1<<16), 336 .ctrlbit = (1<<16),
355 }, { 337 }, {
356 .name = "usb-host", 338 .name = "usb-host",
357 .id = -1,
358 .parent = &clk_hclk_psys.clk, 339 .parent = &clk_hclk_psys.clk,
359 .enable = s5pv210_clk_ip1_ctrl, 340 .enable = s5pv210_clk_ip1_ctrl,
360 .ctrlbit = (1<<17), 341 .ctrlbit = (1<<17),
361 }, { 342 }, {
362 .name = "lcd", 343 .name = "lcd",
363 .id = -1,
364 .parent = &clk_hclk_dsys.clk, 344 .parent = &clk_hclk_dsys.clk,
365 .enable = s5pv210_clk_ip1_ctrl, 345 .enable = s5pv210_clk_ip1_ctrl,
366 .ctrlbit = (1<<0), 346 .ctrlbit = (1<<0),
367 }, { 347 }, {
368 .name = "cfcon", 348 .name = "cfcon",
369 .id = 0,
370 .parent = &clk_hclk_psys.clk, 349 .parent = &clk_hclk_psys.clk,
371 .enable = s5pv210_clk_ip1_ctrl, 350 .enable = s5pv210_clk_ip1_ctrl,
372 .ctrlbit = (1<<25), 351 .ctrlbit = (1<<25),
373 }, { 352 }, {
374 .name = "hsmmc", 353 .name = "hsmmc",
375 .id = 0, 354 .devname = "s3c-sdhci.0",
376 .parent = &clk_hclk_psys.clk, 355 .parent = &clk_hclk_psys.clk,
377 .enable = s5pv210_clk_ip2_ctrl, 356 .enable = s5pv210_clk_ip2_ctrl,
378 .ctrlbit = (1<<16), 357 .ctrlbit = (1<<16),
379 }, { 358 }, {
380 .name = "hsmmc", 359 .name = "hsmmc",
381 .id = 1, 360 .devname = "s3c-sdhci.1",
382 .parent = &clk_hclk_psys.clk, 361 .parent = &clk_hclk_psys.clk,
383 .enable = s5pv210_clk_ip2_ctrl, 362 .enable = s5pv210_clk_ip2_ctrl,
384 .ctrlbit = (1<<17), 363 .ctrlbit = (1<<17),
385 }, { 364 }, {
386 .name = "hsmmc", 365 .name = "hsmmc",
387 .id = 2, 366 .devname = "s3c-sdhci.2",
388 .parent = &clk_hclk_psys.clk, 367 .parent = &clk_hclk_psys.clk,
389 .enable = s5pv210_clk_ip2_ctrl, 368 .enable = s5pv210_clk_ip2_ctrl,
390 .ctrlbit = (1<<18), 369 .ctrlbit = (1<<18),
391 }, { 370 }, {
392 .name = "hsmmc", 371 .name = "hsmmc",
393 .id = 3, 372 .devname = "s3c-sdhci.3",
394 .parent = &clk_hclk_psys.clk, 373 .parent = &clk_hclk_psys.clk,
395 .enable = s5pv210_clk_ip2_ctrl, 374 .enable = s5pv210_clk_ip2_ctrl,
396 .ctrlbit = (1<<19), 375 .ctrlbit = (1<<19),
397 }, { 376 }, {
398 .name = "systimer", 377 .name = "systimer",
399 .id = -1,
400 .parent = &clk_pclk_psys.clk, 378 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl, 379 .enable = s5pv210_clk_ip3_ctrl,
402 .ctrlbit = (1<<16), 380 .ctrlbit = (1<<16),
403 }, { 381 }, {
404 .name = "watchdog", 382 .name = "watchdog",
405 .id = -1,
406 .parent = &clk_pclk_psys.clk, 383 .parent = &clk_pclk_psys.clk,
407 .enable = s5pv210_clk_ip3_ctrl, 384 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<22), 385 .ctrlbit = (1<<22),
409 }, { 386 }, {
410 .name = "rtc", 387 .name = "rtc",
411 .id = -1,
412 .parent = &clk_pclk_psys.clk, 388 .parent = &clk_pclk_psys.clk,
413 .enable = s5pv210_clk_ip3_ctrl, 389 .enable = s5pv210_clk_ip3_ctrl,
414 .ctrlbit = (1<<15), 390 .ctrlbit = (1<<15),
415 }, { 391 }, {
416 .name = "i2c", 392 .name = "i2c",
417 .id = 0, 393 .devname = "s3c2440-i2c.0",
418 .parent = &clk_pclk_psys.clk, 394 .parent = &clk_pclk_psys.clk,
419 .enable = s5pv210_clk_ip3_ctrl, 395 .enable = s5pv210_clk_ip3_ctrl,
420 .ctrlbit = (1<<7), 396 .ctrlbit = (1<<7),
421 }, { 397 }, {
422 .name = "i2c", 398 .name = "i2c",
423 .id = 1, 399 .devname = "s3c2440-i2c.1",
424 .parent = &clk_pclk_psys.clk, 400 .parent = &clk_pclk_psys.clk,
425 .enable = s5pv210_clk_ip3_ctrl, 401 .enable = s5pv210_clk_ip3_ctrl,
426 .ctrlbit = (1 << 10), 402 .ctrlbit = (1 << 10),
427 }, { 403 }, {
428 .name = "i2c", 404 .name = "i2c",
429 .id = 2, 405 .devname = "s3c2440-i2c.2",
430 .parent = &clk_pclk_psys.clk, 406 .parent = &clk_pclk_psys.clk,
431 .enable = s5pv210_clk_ip3_ctrl, 407 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<9), 408 .ctrlbit = (1<<9),
433 }, { 409 }, {
434 .name = "spi", 410 .name = "spi",
435 .id = 0, 411 .devname = "s3c64xx-spi.0",
436 .parent = &clk_pclk_psys.clk, 412 .parent = &clk_pclk_psys.clk,
437 .enable = s5pv210_clk_ip3_ctrl, 413 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<12), 414 .ctrlbit = (1<<12),
439 }, { 415 }, {
440 .name = "spi", 416 .name = "spi",
441 .id = 1, 417 .devname = "s3c64xx-spi.1",
442 .parent = &clk_pclk_psys.clk, 418 .parent = &clk_pclk_psys.clk,
443 .enable = s5pv210_clk_ip3_ctrl, 419 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<13), 420 .ctrlbit = (1<<13),
445 }, { 421 }, {
446 .name = "spi", 422 .name = "spi",
447 .id = 2, 423 .devname = "s3c64xx-spi.2",
448 .parent = &clk_pclk_psys.clk, 424 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl, 425 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<14), 426 .ctrlbit = (1<<14),
451 }, { 427 }, {
452 .name = "timers", 428 .name = "timers",
453 .id = -1,
454 .parent = &clk_pclk_psys.clk, 429 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl, 430 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<23), 431 .ctrlbit = (1<<23),
457 }, { 432 }, {
458 .name = "adc", 433 .name = "adc",
459 .id = -1,
460 .parent = &clk_pclk_psys.clk, 434 .parent = &clk_pclk_psys.clk,
461 .enable = s5pv210_clk_ip3_ctrl, 435 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1<<24), 436 .ctrlbit = (1<<24),
463 }, { 437 }, {
464 .name = "keypad", 438 .name = "keypad",
465 .id = -1,
466 .parent = &clk_pclk_psys.clk, 439 .parent = &clk_pclk_psys.clk,
467 .enable = s5pv210_clk_ip3_ctrl, 440 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21), 441 .ctrlbit = (1<<21),
469 }, { 442 }, {
470 .name = "iis", 443 .name = "iis",
471 .id = 0, 444 .devname = "samsung-i2s.0",
472 .parent = &clk_p, 445 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl, 446 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4), 447 .ctrlbit = (1<<4),
475 }, { 448 }, {
476 .name = "iis", 449 .name = "iis",
477 .id = 1, 450 .devname = "samsung-i2s.1",
478 .parent = &clk_p, 451 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl, 452 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 5), 453 .ctrlbit = (1 << 5),
481 }, { 454 }, {
482 .name = "iis", 455 .name = "iis",
483 .id = 2, 456 .devname = "samsung-i2s.2",
484 .parent = &clk_p, 457 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl, 458 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 6), 459 .ctrlbit = (1 << 6),
487 }, { 460 }, {
488 .name = "spdif", 461 .name = "spdif",
489 .id = -1,
490 .parent = &clk_p, 462 .parent = &clk_p,
491 .enable = s5pv210_clk_ip3_ctrl, 463 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 0), 464 .ctrlbit = (1 << 0),
@@ -496,38 +468,36 @@ static struct clk init_clocks_off[] = {
496static struct clk init_clocks[] = { 468static struct clk init_clocks[] = {
497 { 469 {
498 .name = "hclk_imem", 470 .name = "hclk_imem",
499 .id = -1,
500 .parent = &clk_hclk_msys.clk, 471 .parent = &clk_hclk_msys.clk,
501 .ctrlbit = (1 << 5), 472 .ctrlbit = (1 << 5),
502 .enable = s5pv210_clk_ip0_ctrl, 473 .enable = s5pv210_clk_ip0_ctrl,
503 .ops = &clk_hclk_imem_ops, 474 .ops = &clk_hclk_imem_ops,
504 }, { 475 }, {
505 .name = "uart", 476 .name = "uart",
506 .id = 0, 477 .devname = "s5pv210-uart.0",
507 .parent = &clk_pclk_psys.clk, 478 .parent = &clk_pclk_psys.clk,
508 .enable = s5pv210_clk_ip3_ctrl, 479 .enable = s5pv210_clk_ip3_ctrl,
509 .ctrlbit = (1 << 17), 480 .ctrlbit = (1 << 17),
510 }, { 481 }, {
511 .name = "uart", 482 .name = "uart",
512 .id = 1, 483 .devname = "s5pv210-uart.1",
513 .parent = &clk_pclk_psys.clk, 484 .parent = &clk_pclk_psys.clk,
514 .enable = s5pv210_clk_ip3_ctrl, 485 .enable = s5pv210_clk_ip3_ctrl,
515 .ctrlbit = (1 << 18), 486 .ctrlbit = (1 << 18),
516 }, { 487 }, {
517 .name = "uart", 488 .name = "uart",
518 .id = 2, 489 .devname = "s5pv210-uart.2",
519 .parent = &clk_pclk_psys.clk, 490 .parent = &clk_pclk_psys.clk,
520 .enable = s5pv210_clk_ip3_ctrl, 491 .enable = s5pv210_clk_ip3_ctrl,
521 .ctrlbit = (1 << 19), 492 .ctrlbit = (1 << 19),
522 }, { 493 }, {
523 .name = "uart", 494 .name = "uart",
524 .id = 3, 495 .devname = "s5pv210-uart.3",
525 .parent = &clk_pclk_psys.clk, 496 .parent = &clk_pclk_psys.clk,
526 .enable = s5pv210_clk_ip3_ctrl, 497 .enable = s5pv210_clk_ip3_ctrl,
527 .ctrlbit = (1 << 20), 498 .ctrlbit = (1 << 20),
528 }, { 499 }, {
529 .name = "sromc", 500 .name = "sromc",
530 .id = -1,
531 .parent = &clk_hclk_psys.clk, 501 .parent = &clk_hclk_psys.clk,
532 .enable = s5pv210_clk_ip1_ctrl, 502 .enable = s5pv210_clk_ip1_ctrl,
533 .ctrlbit = (1 << 26), 503 .ctrlbit = (1 << 26),
@@ -579,7 +549,6 @@ static struct clksrc_sources clkset_sclk_dac = {
579static struct clksrc_clk clk_sclk_dac = { 549static struct clksrc_clk clk_sclk_dac = {
580 .clk = { 550 .clk = {
581 .name = "sclk_dac", 551 .name = "sclk_dac",
582 .id = -1,
583 .enable = s5pv210_clk_mask0_ctrl, 552 .enable = s5pv210_clk_mask0_ctrl,
584 .ctrlbit = (1 << 2), 553 .ctrlbit = (1 << 2),
585 }, 554 },
@@ -590,7 +559,6 @@ static struct clksrc_clk clk_sclk_dac = {
590static struct clksrc_clk clk_sclk_pixel = { 559static struct clksrc_clk clk_sclk_pixel = {
591 .clk = { 560 .clk = {
592 .name = "sclk_pixel", 561 .name = "sclk_pixel",
593 .id = -1,
594 .parent = &clk_sclk_vpll.clk, 562 .parent = &clk_sclk_vpll.clk,
595 }, 563 },
596 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, 564 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +577,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
609static struct clksrc_clk clk_sclk_hdmi = { 577static struct clksrc_clk clk_sclk_hdmi = {
610 .clk = { 578 .clk = {
611 .name = "sclk_hdmi", 579 .name = "sclk_hdmi",
612 .id = -1,
613 .enable = s5pv210_clk_mask0_ctrl, 580 .enable = s5pv210_clk_mask0_ctrl,
614 .ctrlbit = (1 << 0), 581 .ctrlbit = (1 << 0),
615 }, 582 },
@@ -647,7 +614,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
647static struct clksrc_clk clk_sclk_audio0 = { 614static struct clksrc_clk clk_sclk_audio0 = {
648 .clk = { 615 .clk = {
649 .name = "sclk_audio", 616 .name = "sclk_audio",
650 .id = 0, 617 .devname = "soc-audio.0",
651 .enable = s5pv210_clk_mask0_ctrl, 618 .enable = s5pv210_clk_mask0_ctrl,
652 .ctrlbit = (1 << 24), 619 .ctrlbit = (1 << 24),
653 }, 620 },
@@ -676,7 +643,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
676static struct clksrc_clk clk_sclk_audio1 = { 643static struct clksrc_clk clk_sclk_audio1 = {
677 .clk = { 644 .clk = {
678 .name = "sclk_audio", 645 .name = "sclk_audio",
679 .id = 1, 646 .devname = "soc-audio.1",
680 .enable = s5pv210_clk_mask0_ctrl, 647 .enable = s5pv210_clk_mask0_ctrl,
681 .ctrlbit = (1 << 25), 648 .ctrlbit = (1 << 25),
682 }, 649 },
@@ -705,7 +672,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
705static struct clksrc_clk clk_sclk_audio2 = { 672static struct clksrc_clk clk_sclk_audio2 = {
706 .clk = { 673 .clk = {
707 .name = "sclk_audio", 674 .name = "sclk_audio",
708 .id = 2, 675 .devname = "soc-audio.2",
709 .enable = s5pv210_clk_mask0_ctrl, 676 .enable = s5pv210_clk_mask0_ctrl,
710 .ctrlbit = (1 << 26), 677 .ctrlbit = (1 << 26),
711 }, 678 },
@@ -763,7 +730,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
763static struct clksrc_clk clk_sclk_spdif = { 730static struct clksrc_clk clk_sclk_spdif = {
764 .clk = { 731 .clk = {
765 .name = "sclk_spdif", 732 .name = "sclk_spdif",
766 .id = -1,
767 .enable = s5pv210_clk_mask0_ctrl, 733 .enable = s5pv210_clk_mask0_ctrl,
768 .ctrlbit = (1 << 27), 734 .ctrlbit = (1 << 27),
769 .ops = &s5pv210_sclk_spdif_ops, 735 .ops = &s5pv210_sclk_spdif_ops,
@@ -793,7 +759,6 @@ static struct clksrc_clk clksrcs[] = {
793 { 759 {
794 .clk = { 760 .clk = {
795 .name = "sclk_dmc", 761 .name = "sclk_dmc",
796 .id = -1,
797 }, 762 },
798 .sources = &clkset_group1, 763 .sources = &clkset_group1,
799 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 764 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +766,6 @@ static struct clksrc_clk clksrcs[] = {
801 }, { 766 }, {
802 .clk = { 767 .clk = {
803 .name = "sclk_onenand", 768 .name = "sclk_onenand",
804 .id = -1,
805 }, 769 },
806 .sources = &clkset_sclk_onenand, 770 .sources = &clkset_sclk_onenand,
807 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, 771 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +773,7 @@ static struct clksrc_clk clksrcs[] = {
809 }, { 773 }, {
810 .clk = { 774 .clk = {
811 .name = "uclk1", 775 .name = "uclk1",
812 .id = 0, 776 .devname = "s5pv210-uart.0",
813 .enable = s5pv210_clk_mask0_ctrl, 777 .enable = s5pv210_clk_mask0_ctrl,
814 .ctrlbit = (1 << 12), 778 .ctrlbit = (1 << 12),
815 }, 779 },
@@ -819,7 +783,7 @@ static struct clksrc_clk clksrcs[] = {
819 }, { 783 }, {
820 .clk = { 784 .clk = {
821 .name = "uclk1", 785 .name = "uclk1",
822 .id = 1, 786 .devname = "s5pv210-uart.1",
823 .enable = s5pv210_clk_mask0_ctrl, 787 .enable = s5pv210_clk_mask0_ctrl,
824 .ctrlbit = (1 << 13), 788 .ctrlbit = (1 << 13),
825 }, 789 },
@@ -829,7 +793,7 @@ static struct clksrc_clk clksrcs[] = {
829 }, { 793 }, {
830 .clk = { 794 .clk = {
831 .name = "uclk1", 795 .name = "uclk1",
832 .id = 2, 796 .devname = "s5pv210-uart.2",
833 .enable = s5pv210_clk_mask0_ctrl, 797 .enable = s5pv210_clk_mask0_ctrl,
834 .ctrlbit = (1 << 14), 798 .ctrlbit = (1 << 14),
835 }, 799 },
@@ -839,7 +803,7 @@ static struct clksrc_clk clksrcs[] = {
839 }, { 803 }, {
840 .clk = { 804 .clk = {
841 .name = "uclk1", 805 .name = "uclk1",
842 .id = 3, 806 .devname = "s5pv210-uart.3",
843 .enable = s5pv210_clk_mask0_ctrl, 807 .enable = s5pv210_clk_mask0_ctrl,
844 .ctrlbit = (1 << 15), 808 .ctrlbit = (1 << 15),
845 }, 809 },
@@ -849,7 +813,6 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 813 }, {
850 .clk = { 814 .clk = {
851 .name = "sclk_mixer", 815 .name = "sclk_mixer",
852 .id = -1,
853 .enable = s5pv210_clk_mask0_ctrl, 816 .enable = s5pv210_clk_mask0_ctrl,
854 .ctrlbit = (1 << 1), 817 .ctrlbit = (1 << 1),
855 }, 818 },
@@ -858,7 +821,7 @@ static struct clksrc_clk clksrcs[] = {
858 }, { 821 }, {
859 .clk = { 822 .clk = {
860 .name = "sclk_fimc", 823 .name = "sclk_fimc",
861 .id = 0, 824 .devname = "s5pv210-fimc.0",
862 .enable = s5pv210_clk_mask1_ctrl, 825 .enable = s5pv210_clk_mask1_ctrl,
863 .ctrlbit = (1 << 2), 826 .ctrlbit = (1 << 2),
864 }, 827 },
@@ -868,7 +831,7 @@ static struct clksrc_clk clksrcs[] = {
868 }, { 831 }, {
869 .clk = { 832 .clk = {
870 .name = "sclk_fimc", 833 .name = "sclk_fimc",
871 .id = 1, 834 .devname = "s5pv210-fimc.1",
872 .enable = s5pv210_clk_mask1_ctrl, 835 .enable = s5pv210_clk_mask1_ctrl,
873 .ctrlbit = (1 << 3), 836 .ctrlbit = (1 << 3),
874 }, 837 },
@@ -878,7 +841,7 @@ static struct clksrc_clk clksrcs[] = {
878 }, { 841 }, {
879 .clk = { 842 .clk = {
880 .name = "sclk_fimc", 843 .name = "sclk_fimc",
881 .id = 2, 844 .devname = "s5pv210-fimc.2",
882 .enable = s5pv210_clk_mask1_ctrl, 845 .enable = s5pv210_clk_mask1_ctrl,
883 .ctrlbit = (1 << 4), 846 .ctrlbit = (1 << 4),
884 }, 847 },
@@ -888,7 +851,7 @@ static struct clksrc_clk clksrcs[] = {
888 }, { 851 }, {
889 .clk = { 852 .clk = {
890 .name = "sclk_cam", 853 .name = "sclk_cam",
891 .id = 0, 854 .devname = "s5pv210-fimc.0",
892 .enable = s5pv210_clk_mask0_ctrl, 855 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 3), 856 .ctrlbit = (1 << 3),
894 }, 857 },
@@ -898,7 +861,7 @@ static struct clksrc_clk clksrcs[] = {
898 }, { 861 }, {
899 .clk = { 862 .clk = {
900 .name = "sclk_cam", 863 .name = "sclk_cam",
901 .id = 1, 864 .devname = "s5pv210-fimc.1",
902 .enable = s5pv210_clk_mask0_ctrl, 865 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 4), 866 .ctrlbit = (1 << 4),
904 }, 867 },
@@ -908,7 +871,6 @@ static struct clksrc_clk clksrcs[] = {
908 }, { 871 }, {
909 .clk = { 872 .clk = {
910 .name = "sclk_fimd", 873 .name = "sclk_fimd",
911 .id = -1,
912 .enable = s5pv210_clk_mask0_ctrl, 874 .enable = s5pv210_clk_mask0_ctrl,
913 .ctrlbit = (1 << 5), 875 .ctrlbit = (1 << 5),
914 }, 876 },
@@ -918,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
918 }, { 880 }, {
919 .clk = { 881 .clk = {
920 .name = "sclk_mmc", 882 .name = "sclk_mmc",
921 .id = 0, 883 .devname = "s3c-sdhci.0",
922 .enable = s5pv210_clk_mask0_ctrl, 884 .enable = s5pv210_clk_mask0_ctrl,
923 .ctrlbit = (1 << 8), 885 .ctrlbit = (1 << 8),
924 }, 886 },
@@ -928,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
928 }, { 890 }, {
929 .clk = { 891 .clk = {
930 .name = "sclk_mmc", 892 .name = "sclk_mmc",
931 .id = 1, 893 .devname = "s3c-sdhci.1",
932 .enable = s5pv210_clk_mask0_ctrl, 894 .enable = s5pv210_clk_mask0_ctrl,
933 .ctrlbit = (1 << 9), 895 .ctrlbit = (1 << 9),
934 }, 896 },
@@ -938,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
938 }, { 900 }, {
939 .clk = { 901 .clk = {
940 .name = "sclk_mmc", 902 .name = "sclk_mmc",
941 .id = 2, 903 .devname = "s3c-sdhci.2",
942 .enable = s5pv210_clk_mask0_ctrl, 904 .enable = s5pv210_clk_mask0_ctrl,
943 .ctrlbit = (1 << 10), 905 .ctrlbit = (1 << 10),
944 }, 906 },
@@ -948,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
948 }, { 910 }, {
949 .clk = { 911 .clk = {
950 .name = "sclk_mmc", 912 .name = "sclk_mmc",
951 .id = 3, 913 .devname = "s3c-sdhci.3",
952 .enable = s5pv210_clk_mask0_ctrl, 914 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 11), 915 .ctrlbit = (1 << 11),
954 }, 916 },
@@ -958,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
958 }, { 920 }, {
959 .clk = { 921 .clk = {
960 .name = "sclk_mfc", 922 .name = "sclk_mfc",
961 .id = -1, 923 .devname = "s5p-mfc",
962 .enable = s5pv210_clk_ip0_ctrl, 924 .enable = s5pv210_clk_ip0_ctrl,
963 .ctrlbit = (1 << 16), 925 .ctrlbit = (1 << 16),
964 }, 926 },
@@ -968,7 +930,6 @@ static struct clksrc_clk clksrcs[] = {
968 }, { 930 }, {
969 .clk = { 931 .clk = {
970 .name = "sclk_g2d", 932 .name = "sclk_g2d",
971 .id = -1,
972 .enable = s5pv210_clk_ip0_ctrl, 933 .enable = s5pv210_clk_ip0_ctrl,
973 .ctrlbit = (1 << 12), 934 .ctrlbit = (1 << 12),
974 }, 935 },
@@ -978,7 +939,6 @@ static struct clksrc_clk clksrcs[] = {
978 }, { 939 }, {
979 .clk = { 940 .clk = {
980 .name = "sclk_g3d", 941 .name = "sclk_g3d",
981 .id = -1,
982 .enable = s5pv210_clk_ip0_ctrl, 942 .enable = s5pv210_clk_ip0_ctrl,
983 .ctrlbit = (1 << 8), 943 .ctrlbit = (1 << 8),
984 }, 944 },
@@ -988,7 +948,6 @@ static struct clksrc_clk clksrcs[] = {
988 }, { 948 }, {
989 .clk = { 949 .clk = {
990 .name = "sclk_csis", 950 .name = "sclk_csis",
991 .id = -1,
992 .enable = s5pv210_clk_mask0_ctrl, 951 .enable = s5pv210_clk_mask0_ctrl,
993 .ctrlbit = (1 << 6), 952 .ctrlbit = (1 << 6),
994 }, 953 },
@@ -998,7 +957,7 @@ static struct clksrc_clk clksrcs[] = {
998 }, { 957 }, {
999 .clk = { 958 .clk = {
1000 .name = "sclk_spi", 959 .name = "sclk_spi",
1001 .id = 0, 960 .devname = "s3c64xx-spi.0",
1002 .enable = s5pv210_clk_mask0_ctrl, 961 .enable = s5pv210_clk_mask0_ctrl,
1003 .ctrlbit = (1 << 16), 962 .ctrlbit = (1 << 16),
1004 }, 963 },
@@ -1008,7 +967,7 @@ static struct clksrc_clk clksrcs[] = {
1008 }, { 967 }, {
1009 .clk = { 968 .clk = {
1010 .name = "sclk_spi", 969 .name = "sclk_spi",
1011 .id = 1, 970 .devname = "s3c64xx-spi.1",
1012 .enable = s5pv210_clk_mask0_ctrl, 971 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 17), 972 .ctrlbit = (1 << 17),
1014 }, 973 },
@@ -1018,7 +977,6 @@ static struct clksrc_clk clksrcs[] = {
1018 }, { 977 }, {
1019 .clk = { 978 .clk = {
1020 .name = "sclk_pwi", 979 .name = "sclk_pwi",
1021 .id = -1,
1022 .enable = s5pv210_clk_mask0_ctrl, 980 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 29), 981 .ctrlbit = (1 << 29),
1024 }, 982 },
@@ -1028,7 +986,6 @@ static struct clksrc_clk clksrcs[] = {
1028 }, { 986 }, {
1029 .clk = { 987 .clk = {
1030 .name = "sclk_pwm", 988 .name = "sclk_pwm",
1031 .id = -1,
1032 .enable = s5pv210_clk_mask0_ctrl, 989 .enable = s5pv210_clk_mask0_ctrl,
1033 .ctrlbit = (1 << 19), 990 .ctrlbit = (1 << 19),
1034 }, 991 },
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 61e6c24b90ac..79907ec78d43 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
126 s5pv210_default_sdhci2(); 126 s5pv210_default_sdhci2();
127 s5pv210_default_sdhci3(); 127 s5pv210_default_sdhci3();
128 128
129 s3c_adc_setname("s3c64xx-adc"); 129 s3c_adc_setname("samsung-adc-v3");
130 130
131 s3c_cfcon_setname("s5pv210-pata"); 131 s3c_cfcon_setname("s5pv210-pata");
132 132
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 8d58f1926241..63f5d82004b5 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -18,6 +18,7 @@
18#include <mach/map.h> 18#include <mach/map.h>
19#include <mach/dma.h> 19#include <mach/dma.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21#include <mach/regs-audss.h>
21 22
22static const char *rclksrc[] = { 23static const char *rclksrc[] = {
23 [0] = "busclk", 24 [0] = "busclk",
@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI 53 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
53 | QUIRK_NEED_RSTCLR, 54 | QUIRK_NEED_RSTCLR,
54 .src_clk = rclksrc, 55 .src_clk = rclksrc,
56 .idma_addr = S5PV210_AUDSS_INT_MEM,
55 }, 57 },
56 }, 58 },
57}; 59};
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 1dd58836fd4f..aac343c180b2 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -59,6 +59,8 @@
59 59
60#define S5PV210_PA_CFCON 0xE8200000 60#define S5PV210_PA_CFCON 0xE8200000
61 61
62#define S5PV210_PA_MFC 0xF1700000
63
62#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 64#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
63 65
64#define S5PV210_PA_HSOTG 0xEC000000 66#define S5PV210_PA_HSOTG 0xEC000000
@@ -107,6 +109,7 @@
107#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 109#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
108#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 110#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
109#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS 111#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
112#define S5P_PA_MFC S5PV210_PA_MFC
110#define S5P_PA_ONENAND S5PC110_PA_ONENAND 113#define S5P_PA_ONENAND S5PC110_PA_ONENAND
111#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 114#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
112#define S5P_PA_SDRAM S5PV210_PA_SDRAM 115#define S5P_PA_SDRAM S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index e8d394f8b057..3e22109e1b7b 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
41{ 41{
42 /* nothing here yet */ 42 /* nothing here yet */
43} 43}
44
45static inline void s3c_pm_restored_gpios(void) { }
46static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
new file mode 100644
index 000000000000..eacc1f790807
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
2 *
3 * Copyright (c) 2011 Samsung Electronics
4 * http://www.samsung.com
5 *
6 * S5PV210 Audio SubSystem clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_AUDSS_H
14#define __PLAT_REGS_AUDSS_H __FILE__
15
16#define S5PV210_AUDSS_INT_MEM (0xC0000000)
17
18#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 31d5aa769753..e9b1406cb566 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -47,6 +47,8 @@
47#include <plat/sdhci.h> 47#include <plat/sdhci.h>
48#include <plat/clock.h> 48#include <plat/clock.h>
49#include <plat/s5p-time.h> 49#include <plat/s5p-time.h>
50#include <plat/mfc.h>
51#include <plat/regs-fb-v4.h>
50 52
51/* Following are default values for UCON, ULCON and UFCON UART registers */ 53/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 54#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -808,6 +810,9 @@ static struct platform_device *goni_devices[] __initdata = {
808 &goni_i2c_gpio5, 810 &goni_i2c_gpio5,
809 &mmc2_fixed_voltage, 811 &mmc2_fixed_voltage,
810 &goni_device_gpiokeys, 812 &goni_device_gpiokeys,
813 &s5p_device_mfc,
814 &s5p_device_mfc_l,
815 &s5p_device_mfc_r,
811 &s3c_device_i2c0, 816 &s3c_device_i2c0,
812 &s5p_device_fimc0, 817 &s5p_device_fimc0,
813 &s5p_device_fimc1, 818 &s5p_device_fimc1,
@@ -841,6 +846,11 @@ static void __init goni_map_io(void)
841 s5p_set_timer_source(S5P_PWM3, S5P_PWM4); 846 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
842} 847}
843 848
849static void __init goni_reserve(void)
850{
851 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
852}
853
844static void __init goni_machine_init(void) 854static void __init goni_machine_init(void)
845{ 855{
846 /* Radio: call before I2C 1 registeration */ 856 /* Radio: call before I2C 1 registeration */
@@ -893,4 +903,5 @@ MACHINE_START(GONI, "GONI")
893 .map_io = goni_map_io, 903 .map_io = goni_map_io,
894 .init_machine = goni_machine_init, 904 .init_machine = goni_machine_init,
895 .timer = &s5p_timer, 905 .timer = &s5p_timer,
906 .reserve = &goni_reserve,
896MACHINE_END 907MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index c6a9e86c2d5c..c6900f8bf3ce 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -267,6 +267,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
267 &s5pv210_device_iis0, 267 &s5pv210_device_iis0,
268 &s5pv210_device_spdif, 268 &s5pv210_device_spdif,
269 &samsung_asoc_dma, 269 &samsung_asoc_dma,
270 &samsung_asoc_idma,
270 &samsung_device_keypad, 271 &samsung_device_keypad,
271 &smdkv210_dm9000, 272 &smdkv210_dm9000,
272 &smdkv210_lcd_lte480wv, 273 &smdkv210_lcd_lte480wv,
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index cf97caafe56b..f95d3268ae1f 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
169 169
170struct clk s3c24xx_dclk0 = { 170struct clk s3c24xx_dclk0 = {
171 .name = "dclk0", 171 .name = "dclk0",
172 .id = -1,
173 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 172 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
174 .enable = s3c24xx_dclk_enable, 173 .enable = s3c24xx_dclk_enable,
175 .ops = &dclk_ops, 174 .ops = &dclk_ops,
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
177 176
178struct clk s3c24xx_dclk1 = { 177struct clk s3c24xx_dclk1 = {
179 .name = "dclk1", 178 .name = "dclk1",
180 .id = -1,
181 .ctrlbit = S3C2410_DCLKCON_DCLK1EN, 179 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
182 .enable = s3c24xx_dclk_enable, 180 .enable = s3c24xx_dclk_enable,
183 .ops = &dclk_ops, 181 .ops = &dclk_ops,
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
189 187
190struct clk s3c24xx_clkout0 = { 188struct clk s3c24xx_clkout0 = {
191 .name = "clkout0", 189 .name = "clkout0",
192 .id = -1,
193 .ops = &clkout_ops, 190 .ops = &clkout_ops,
194}; 191};
195 192
196struct clk s3c24xx_clkout1 = { 193struct clk s3c24xx_clkout1 = {
197 .name = "clkout1", 194 .name = "clkout1",
198 .id = -1,
199 .ops = &clkout_ops, 195 .ops = &clkout_ops,
200}; 196};
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 9ecc5d913679..def76aa3825a 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
90static struct clk init_clocks_off[] = { 90static struct clk init_clocks_off[] = {
91 { 91 {
92 .name = "nand", 92 .name = "nand",
93 .id = -1,
94 .parent = &clk_h, 93 .parent = &clk_h,
95 .enable = s3c2410_clkcon_enable, 94 .enable = s3c2410_clkcon_enable,
96 .ctrlbit = S3C2410_CLKCON_NAND, 95 .ctrlbit = S3C2410_CLKCON_NAND,
97 }, { 96 }, {
98 .name = "sdi", 97 .name = "sdi",
99 .id = -1,
100 .parent = &clk_p, 98 .parent = &clk_p,
101 .enable = s3c2410_clkcon_enable, 99 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_SDI, 100 .ctrlbit = S3C2410_CLKCON_SDI,
103 }, { 101 }, {
104 .name = "adc", 102 .name = "adc",
105 .id = -1,
106 .parent = &clk_p, 103 .parent = &clk_p,
107 .enable = s3c2410_clkcon_enable, 104 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2410_CLKCON_ADC, 105 .ctrlbit = S3C2410_CLKCON_ADC,
109 }, { 106 }, {
110 .name = "i2c", 107 .name = "i2c",
111 .id = -1,
112 .parent = &clk_p, 108 .parent = &clk_p,
113 .enable = s3c2410_clkcon_enable, 109 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIC, 110 .ctrlbit = S3C2410_CLKCON_IIC,
115 }, { 111 }, {
116 .name = "iis", 112 .name = "iis",
117 .id = -1,
118 .parent = &clk_p, 113 .parent = &clk_p,
119 .enable = s3c2410_clkcon_enable, 114 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS, 115 .ctrlbit = S3C2410_CLKCON_IIS,
121 }, { 116 }, {
122 .name = "spi", 117 .name = "spi",
123 .id = -1,
124 .parent = &clk_p, 118 .parent = &clk_p,
125 .enable = s3c2410_clkcon_enable, 119 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI, 120 .ctrlbit = S3C2410_CLKCON_SPI,
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
130static struct clk init_clocks[] = { 124static struct clk init_clocks[] = {
131 { 125 {
132 .name = "lcd", 126 .name = "lcd",
133 .id = -1,
134 .parent = &clk_h, 127 .parent = &clk_h,
135 .enable = s3c2410_clkcon_enable, 128 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC, 129 .ctrlbit = S3C2410_CLKCON_LCDC,
137 }, { 130 }, {
138 .name = "gpio", 131 .name = "gpio",
139 .id = -1,
140 .parent = &clk_p, 132 .parent = &clk_p,
141 .enable = s3c2410_clkcon_enable, 133 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO, 134 .ctrlbit = S3C2410_CLKCON_GPIO,
143 }, { 135 }, {
144 .name = "usb-host", 136 .name = "usb-host",
145 .id = -1,
146 .parent = &clk_h, 137 .parent = &clk_h,
147 .enable = s3c2410_clkcon_enable, 138 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH, 139 .ctrlbit = S3C2410_CLKCON_USBH,
149 }, { 140 }, {
150 .name = "usb-device", 141 .name = "usb-device",
151 .id = -1,
152 .parent = &clk_h, 142 .parent = &clk_h,
153 .enable = s3c2410_clkcon_enable, 143 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD, 144 .ctrlbit = S3C2410_CLKCON_USBD,
155 }, { 145 }, {
156 .name = "timers", 146 .name = "timers",
157 .id = -1,
158 .parent = &clk_p, 147 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable, 148 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT, 149 .ctrlbit = S3C2410_CLKCON_PWMT,
161 }, { 150 }, {
162 .name = "uart", 151 .name = "uart",
163 .id = 0, 152 .devname = "s3c2410-uart.0",
164 .parent = &clk_p, 153 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable, 154 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0, 155 .ctrlbit = S3C2410_CLKCON_UART0,
167 }, { 156 }, {
168 .name = "uart", 157 .name = "uart",
169 .id = 1, 158 .devname = "s3c2410-uart.1",
170 .parent = &clk_p, 159 .parent = &clk_p,
171 .enable = s3c2410_clkcon_enable, 160 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1, 161 .ctrlbit = S3C2410_CLKCON_UART1,
173 }, { 162 }, {
174 .name = "uart", 163 .name = "uart",
175 .id = 2, 164 .devname = "s3c2410-uart.2",
176 .parent = &clk_p, 165 .parent = &clk_p,
177 .enable = s3c2410_clkcon_enable, 166 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2, 167 .ctrlbit = S3C2410_CLKCON_UART2,
179 }, { 168 }, {
180 .name = "rtc", 169 .name = "rtc",
181 .id = -1,
182 .parent = &clk_p, 170 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable, 171 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC, 172 .ctrlbit = S3C2410_CLKCON_RTC,
185 }, { 173 }, {
186 .name = "watchdog", 174 .name = "watchdog",
187 .id = -1,
188 .parent = &clk_p, 175 .parent = &clk_p,
189 .ctrlbit = 0, 176 .ctrlbit = 0,
190 }, { 177 }, {
191 .name = "usb-bus-host", 178 .name = "usb-bus-host",
192 .id = -1,
193 .parent = &clk_usb_bus, 179 .parent = &clk_usb_bus,
194 }, { 180 }, {
195 .name = "usb-bus-gadget", 181 .name = "usb-bus-gadget",
196 .id = -1,
197 .parent = &clk_usb_bus, 182 .parent = &clk_usb_bus,
198 }, 183 },
199}; 184};
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 82f2d4a39291..59552c0ea5fb 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
56struct clk clk_mpllref = { 56struct clk clk_mpllref = {
57 .name = "mpllref", 57 .name = "mpllref",
58 .parent = &clk_xtal, 58 .parent = &clk_xtal,
59 .id = -1,
60}; 59};
61 60
62static struct clk *clk_epllref_sources[] = { 61static struct clk *clk_epllref_sources[] = {
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
69struct clksrc_clk clk_epllref = { 68struct clksrc_clk clk_epllref = {
70 .clk = { 69 .clk = {
71 .name = "epllref", 70 .name = "epllref",
72 .id = -1,
73 }, 71 },
74 .sources = &(struct clksrc_sources) { 72 .sources = &(struct clksrc_sources) {
75 .sources = clk_epllref_sources, 73 .sources = clk_epllref_sources,
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
92 .clk = { 90 .clk = {
93 .name = "esysclk", 91 .name = "esysclk",
94 .parent = &clk_epll, 92 .parent = &clk_epll,
95 .id = -1,
96 }, 93 },
97 .sources = &(struct clksrc_sources) { 94 .sources = &(struct clksrc_sources) {
98 .sources = clk_sysclk_sources, 95 .sources = clk_sysclk_sources,
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
115static struct clk clk_mdivclk = { 112static struct clk clk_mdivclk = {
116 .name = "mdivclk", 113 .name = "mdivclk",
117 .parent = &clk_mpllref, 114 .parent = &clk_mpllref,
118 .id = -1,
119 .ops = &(struct clk_ops) { 115 .ops = &(struct clk_ops) {
120 .get_rate = s3c2443_getrate_mdivclk, 116 .get_rate = s3c2443_getrate_mdivclk,
121 }, 117 },
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
132 .clk = { 128 .clk = {
133 .name = "msysclk", 129 .name = "msysclk",
134 .parent = &clk_xtal, 130 .parent = &clk_xtal,
135 .id = -1,
136 }, 131 },
137 .sources = &(struct clksrc_sources) { 132 .sources = &(struct clksrc_sources) {
138 .sources = clk_msysclk_sources, 133 .sources = clk_msysclk_sources,
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
159 154
160static struct clk clk_prediv = { 155static struct clk clk_prediv = {
161 .name = "prediv", 156 .name = "prediv",
162 .id = -1,
163 .parent = &clk_msysclk.clk, 157 .parent = &clk_msysclk.clk,
164 .ops = &(struct clk_ops) { 158 .ops = &(struct clk_ops) {
165 .get_rate = s3c2443_prediv_getrate, 159 .get_rate = s3c2443_prediv_getrate,
@@ -174,7 +168,6 @@ static struct clk clk_prediv = {
174static struct clksrc_clk clk_usb_bus_host = { 168static struct clksrc_clk clk_usb_bus_host = {
175 .clk = { 169 .clk = {
176 .name = "usb-bus-host-parent", 170 .name = "usb-bus-host-parent",
177 .id = -1,
178 .parent = &clk_esysclk.clk, 171 .parent = &clk_esysclk.clk,
179 .ctrlbit = S3C2443_SCLKCON_USBHOST, 172 .ctrlbit = S3C2443_SCLKCON_USBHOST,
180 .enable = s3c2443_clkcon_enable_s, 173 .enable = s3c2443_clkcon_enable_s,
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
189 /* ART baud-rate clock sourced from esysclk via a divisor */ 182 /* ART baud-rate clock sourced from esysclk via a divisor */
190 .clk = { 183 .clk = {
191 .name = "uartclk", 184 .name = "uartclk",
192 .id = -1,
193 .parent = &clk_esysclk.clk, 185 .parent = &clk_esysclk.clk,
194 }, 186 },
195 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, 187 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
197 /* camera interface bus-clock, divided down from esysclk */ 189 /* camera interface bus-clock, divided down from esysclk */
198 .clk = { 190 .clk = {
199 .name = "camif-upll", /* same as 2440 name */ 191 .name = "camif-upll", /* same as 2440 name */
200 .id = -1,
201 .parent = &clk_esysclk.clk, 192 .parent = &clk_esysclk.clk,
202 .ctrlbit = S3C2443_SCLKCON_CAMCLK, 193 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
203 .enable = s3c2443_clkcon_enable_s, 194 .enable = s3c2443_clkcon_enable_s,
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
206 }, { 197 }, {
207 .clk = { 198 .clk = {
208 .name = "display-if", 199 .name = "display-if",
209 .id = -1,
210 .parent = &clk_esysclk.clk, 200 .parent = &clk_esysclk.clk,
211 .ctrlbit = S3C2443_SCLKCON_DISPCLK, 201 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
212 .enable = s3c2443_clkcon_enable_s, 202 .enable = s3c2443_clkcon_enable_s,
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
219static struct clk init_clocks_off[] = { 209static struct clk init_clocks_off[] = {
220 { 210 {
221 .name = "adc", 211 .name = "adc",
222 .id = -1,
223 .parent = &clk_p, 212 .parent = &clk_p,
224 .enable = s3c2443_clkcon_enable_p, 213 .enable = s3c2443_clkcon_enable_p,
225 .ctrlbit = S3C2443_PCLKCON_ADC, 214 .ctrlbit = S3C2443_PCLKCON_ADC,
226 }, { 215 }, {
227 .name = "i2c", 216 .name = "i2c",
228 .id = -1,
229 .parent = &clk_p, 217 .parent = &clk_p,
230 .enable = s3c2443_clkcon_enable_p, 218 .enable = s3c2443_clkcon_enable_p,
231 .ctrlbit = S3C2443_PCLKCON_IIC, 219 .ctrlbit = S3C2443_PCLKCON_IIC,
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
235static struct clk init_clocks[] = { 223static struct clk init_clocks[] = {
236 { 224 {
237 .name = "dma", 225 .name = "dma",
238 .id = 0,
239 .parent = &clk_h, 226 .parent = &clk_h,
240 .enable = s3c2443_clkcon_enable_h, 227 .enable = s3c2443_clkcon_enable_h,
241 .ctrlbit = S3C2443_HCLKCON_DMA0, 228 .ctrlbit = S3C2443_HCLKCON_DMA0,
242 }, { 229 }, {
243 .name = "dma", 230 .name = "dma",
244 .id = 1,
245 .parent = &clk_h, 231 .parent = &clk_h,
246 .enable = s3c2443_clkcon_enable_h, 232 .enable = s3c2443_clkcon_enable_h,
247 .ctrlbit = S3C2443_HCLKCON_DMA1, 233 .ctrlbit = S3C2443_HCLKCON_DMA1,
248 }, { 234 }, {
249 .name = "dma", 235 .name = "dma",
250 .id = 2,
251 .parent = &clk_h, 236 .parent = &clk_h,
252 .enable = s3c2443_clkcon_enable_h, 237 .enable = s3c2443_clkcon_enable_h,
253 .ctrlbit = S3C2443_HCLKCON_DMA2, 238 .ctrlbit = S3C2443_HCLKCON_DMA2,
254 }, { 239 }, {
255 .name = "dma", 240 .name = "dma",
256 .id = 3,
257 .parent = &clk_h, 241 .parent = &clk_h,
258 .enable = s3c2443_clkcon_enable_h, 242 .enable = s3c2443_clkcon_enable_h,
259 .ctrlbit = S3C2443_HCLKCON_DMA3, 243 .ctrlbit = S3C2443_HCLKCON_DMA3,
260 }, { 244 }, {
261 .name = "dma", 245 .name = "dma",
262 .id = 4,
263 .parent = &clk_h, 246 .parent = &clk_h,
264 .enable = s3c2443_clkcon_enable_h, 247 .enable = s3c2443_clkcon_enable_h,
265 .ctrlbit = S3C2443_HCLKCON_DMA4, 248 .ctrlbit = S3C2443_HCLKCON_DMA4,
266 }, { 249 }, {
267 .name = "dma", 250 .name = "dma",
268 .id = 5,
269 .parent = &clk_h, 251 .parent = &clk_h,
270 .enable = s3c2443_clkcon_enable_h, 252 .enable = s3c2443_clkcon_enable_h,
271 .ctrlbit = S3C2443_HCLKCON_DMA5, 253 .ctrlbit = S3C2443_HCLKCON_DMA5,
272 }, { 254 }, {
273 .name = "hsmmc", 255 .name = "hsmmc",
274 .id = 1,
275 .parent = &clk_h, 256 .parent = &clk_h,
276 .enable = s3c2443_clkcon_enable_h, 257 .enable = s3c2443_clkcon_enable_h,
277 .ctrlbit = S3C2443_HCLKCON_HSMMC, 258 .ctrlbit = S3C2443_HCLKCON_HSMMC,
278 }, { 259 }, {
279 .name = "gpio", 260 .name = "gpio",
280 .id = -1,
281 .parent = &clk_p, 261 .parent = &clk_p,
282 .enable = s3c2443_clkcon_enable_p, 262 .enable = s3c2443_clkcon_enable_p,
283 .ctrlbit = S3C2443_PCLKCON_GPIO, 263 .ctrlbit = S3C2443_PCLKCON_GPIO,
284 }, { 264 }, {
285 .name = "usb-host", 265 .name = "usb-host",
286 .id = -1,
287 .parent = &clk_h, 266 .parent = &clk_h,
288 .enable = s3c2443_clkcon_enable_h, 267 .enable = s3c2443_clkcon_enable_h,
289 .ctrlbit = S3C2443_HCLKCON_USBH, 268 .ctrlbit = S3C2443_HCLKCON_USBH,
290 }, { 269 }, {
291 .name = "usb-device", 270 .name = "usb-device",
292 .id = -1,
293 .parent = &clk_h, 271 .parent = &clk_h,
294 .enable = s3c2443_clkcon_enable_h, 272 .enable = s3c2443_clkcon_enable_h,
295 .ctrlbit = S3C2443_HCLKCON_USBD, 273 .ctrlbit = S3C2443_HCLKCON_USBD,
296 }, { 274 }, {
297 .name = "lcd", 275 .name = "lcd",
298 .id = -1,
299 .parent = &clk_h, 276 .parent = &clk_h,
300 .enable = s3c2443_clkcon_enable_h, 277 .enable = s3c2443_clkcon_enable_h,
301 .ctrlbit = S3C2443_HCLKCON_LCDC, 278 .ctrlbit = S3C2443_HCLKCON_LCDC,
302 279
303 }, { 280 }, {
304 .name = "timers", 281 .name = "timers",
305 .id = -1,
306 .parent = &clk_p, 282 .parent = &clk_p,
307 .enable = s3c2443_clkcon_enable_p, 283 .enable = s3c2443_clkcon_enable_p,
308 .ctrlbit = S3C2443_PCLKCON_PWMT, 284 .ctrlbit = S3C2443_PCLKCON_PWMT,
309 }, { 285 }, {
310 .name = "cfc", 286 .name = "cfc",
311 .id = -1,
312 .parent = &clk_h, 287 .parent = &clk_h,
313 .enable = s3c2443_clkcon_enable_h, 288 .enable = s3c2443_clkcon_enable_h,
314 .ctrlbit = S3C2443_HCLKCON_CFC, 289 .ctrlbit = S3C2443_HCLKCON_CFC,
315 }, { 290 }, {
316 .name = "ssmc", 291 .name = "ssmc",
317 .id = -1,
318 .parent = &clk_h, 292 .parent = &clk_h,
319 .enable = s3c2443_clkcon_enable_h, 293 .enable = s3c2443_clkcon_enable_h,
320 .ctrlbit = S3C2443_HCLKCON_SSMC, 294 .ctrlbit = S3C2443_HCLKCON_SSMC,
321 }, { 295 }, {
322 .name = "uart", 296 .name = "uart",
323 .id = 0, 297 .devname = "s3c2440-uart.0",
324 .parent = &clk_p, 298 .parent = &clk_p,
325 .enable = s3c2443_clkcon_enable_p, 299 .enable = s3c2443_clkcon_enable_p,
326 .ctrlbit = S3C2443_PCLKCON_UART0, 300 .ctrlbit = S3C2443_PCLKCON_UART0,
327 }, { 301 }, {
328 .name = "uart", 302 .name = "uart",
329 .id = 1, 303 .devname = "s3c2440-uart.1",
330 .parent = &clk_p, 304 .parent = &clk_p,
331 .enable = s3c2443_clkcon_enable_p, 305 .enable = s3c2443_clkcon_enable_p,
332 .ctrlbit = S3C2443_PCLKCON_UART1, 306 .ctrlbit = S3C2443_PCLKCON_UART1,
333 }, { 307 }, {
334 .name = "uart", 308 .name = "uart",
335 .id = 2, 309 .devname = "s3c2440-uart.2",
336 .parent = &clk_p, 310 .parent = &clk_p,
337 .enable = s3c2443_clkcon_enable_p, 311 .enable = s3c2443_clkcon_enable_p,
338 .ctrlbit = S3C2443_PCLKCON_UART2, 312 .ctrlbit = S3C2443_PCLKCON_UART2,
339 }, { 313 }, {
340 .name = "uart", 314 .name = "uart",
341 .id = 3, 315 .devname = "s3c2440-uart.3",
342 .parent = &clk_p, 316 .parent = &clk_p,
343 .enable = s3c2443_clkcon_enable_p, 317 .enable = s3c2443_clkcon_enable_p,
344 .ctrlbit = S3C2443_PCLKCON_UART3, 318 .ctrlbit = S3C2443_PCLKCON_UART3,
345 }, { 319 }, {
346 .name = "rtc", 320 .name = "rtc",
347 .id = -1,
348 .parent = &clk_p, 321 .parent = &clk_p,
349 .enable = s3c2443_clkcon_enable_p, 322 .enable = s3c2443_clkcon_enable_p,
350 .ctrlbit = S3C2443_PCLKCON_RTC, 323 .ctrlbit = S3C2443_PCLKCON_RTC,
351 }, { 324 }, {
352 .name = "watchdog", 325 .name = "watchdog",
353 .id = -1,
354 .parent = &clk_p, 326 .parent = &clk_p,
355 .ctrlbit = S3C2443_PCLKCON_WDT, 327 .ctrlbit = S3C2443_PCLKCON_WDT,
356 }, { 328 }, {
357 .name = "ac97", 329 .name = "ac97",
358 .id = -1,
359 .parent = &clk_p, 330 .parent = &clk_p,
360 .ctrlbit = S3C2443_PCLKCON_AC97, 331 .ctrlbit = S3C2443_PCLKCON_AC97,
361 }, { 332 }, {
362 .name = "nand", 333 .name = "nand",
363 .id = -1,
364 .parent = &clk_h, 334 .parent = &clk_h,
365 }, { 335 }, {
366 .name = "usb-bus-host", 336 .name = "usb-bus-host",
367 .id = -1,
368 .parent = &clk_usb_bus_host.clk, 337 .parent = &clk_usb_bus_host.clk,
369 } 338 }
370}; 339};
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index e98f5c5c7879..9843c954c042 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -39,6 +39,7 @@ config S5P_GPIO_INT
39 39
40config S5P_HRT 40config S5P_HRT
41 bool 41 bool
42 select SAMSUNG_DEV_PWM
42 help 43 help
43 Use the High Resolution timer support 44 Use the High Resolution timer support
44 45
@@ -70,6 +71,16 @@ config S5P_DEV_FIMC3
70 help 71 help
71 Compile in platform device definitions for FIMC controller 3 72 Compile in platform device definitions for FIMC controller 3
72 73
74config S5P_DEV_FIMD0
75 bool
76 help
77 Compile in platform device definitions for FIMD controller 0
78
79config S5P_DEV_MFC
80 bool
81 help
82 Compile in platform device definitions for MFC
83
73config S5P_DEV_ONENAND 84config S5P_DEV_ONENAND
74 bool 85 bool
75 help 86 help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index e234cc4d49a0..4b53e04eeca4 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -25,11 +25,12 @@ obj-$(CONFIG_PM) += irq-pm.o
25obj-$(CONFIG_S5P_HRT) += s5p-time.o 25obj-$(CONFIG_S5P_HRT) += s5p-time.o
26 26
27# devices 27# devices
28 28obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
29obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o 29obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
30obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o 30obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
31obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o 31obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
32obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o 32obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o
33obj-$(CONFIG_S5P_DEV_FIMD0) += dev-fimd0.o
33obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o 34obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
34obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o 35obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
35obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o 36obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c
new file mode 100644
index 000000000000..f728bb5abcef
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimd0.c
@@ -0,0 +1,67 @@
1/* linux/arch/arm/plat-s5p/dev-fimd0.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Core file for Samsung Display Controller (FIMD) driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/platform_device.h>
16#include <linux/fb.h>
17#include <linux/gfp.h>
18#include <linux/dma-mapping.h>
19
20#include <mach/irqs.h>
21#include <mach/map.h>
22
23#include <plat/fb.h>
24#include <plat/devs.h>
25#include <plat/cpu.h>
26
27static struct resource s5p_fimd0_resource[] = {
28 [0] = {
29 .start = S5P_PA_FIMD0,
30 .end = S5P_PA_FIMD0 + SZ_32K - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_FIMD0_VSYNC,
35 .end = IRQ_FIMD0_VSYNC,
36 .flags = IORESOURCE_IRQ,
37 },
38 [2] = {
39 .start = IRQ_FIMD0_FIFO,
40 .end = IRQ_FIMD0_FIFO,
41 .flags = IORESOURCE_IRQ,
42 },
43 [3] = {
44 .start = IRQ_FIMD0_SYSTEM,
45 .end = IRQ_FIMD0_SYSTEM,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static u64 fimd0_dmamask = DMA_BIT_MASK(32);
51
52struct platform_device s5p_device_fimd0 = {
53 .name = "s5p-fb",
54 .id = 0,
55 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
56 .resource = s5p_fimd0_resource,
57 .dev = {
58 .dma_mask = &fimd0_dmamask,
59 .coherent_dma_mask = DMA_BIT_MASK(32),
60 },
61};
62
63void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
64{
65 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
66 &s5p_device_fimd0);
67}
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c
new file mode 100644
index 000000000000..94226a0010f7
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-mfc.c
@@ -0,0 +1,123 @@
1/* linux/arch/arm/plat-s5p/dev-mfc.c
2 *
3 * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
4 *
5 * Base S5P MFC resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/memblock.h>
18#include <linux/ioport.h>
19
20#include <mach/map.h>
21#include <plat/devs.h>
22#include <plat/irqs.h>
23#include <plat/mfc.h>
24
25static struct resource s5p_mfc_resource[] = {
26 [0] = {
27 .start = S5P_PA_MFC,
28 .end = S5P_PA_MFC + SZ_64K - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_MFC,
33 .end = IRQ_MFC,
34 .flags = IORESOURCE_IRQ,
35 }
36};
37
38struct platform_device s5p_device_mfc = {
39 .name = "s5p-mfc",
40 .id = -1,
41 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
42 .resource = s5p_mfc_resource,
43};
44
45/*
46 * MFC hardware has 2 memory interfaces which are modelled as two separate
47 * platform devices to let dma-mapping distinguish between them.
48 *
49 * MFC parent device (s5p_device_mfc) must be registered before memory
50 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
51 */
52
53static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
54
55struct platform_device s5p_device_mfc_l = {
56 .name = "s5p-mfc-l",
57 .id = -1,
58 .dev = {
59 .parent = &s5p_device_mfc.dev,
60 .dma_mask = &s5p_mfc_dma_mask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 },
63};
64
65struct platform_device s5p_device_mfc_r = {
66 .name = "s5p-mfc-r",
67 .id = -1,
68 .dev = {
69 .parent = &s5p_device_mfc.dev,
70 .dma_mask = &s5p_mfc_dma_mask,
71 .coherent_dma_mask = DMA_BIT_MASK(32),
72 },
73};
74
75struct s5p_mfc_reserved_mem {
76 phys_addr_t base;
77 unsigned long size;
78 struct device *dev;
79};
80
81static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
82
83void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
84 phys_addr_t lbase, unsigned int lsize)
85{
86 int i;
87
88 s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
89 s5p_mfc_mem[0].base = rbase;
90 s5p_mfc_mem[0].size = rsize;
91
92 s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
93 s5p_mfc_mem[1].base = lbase;
94 s5p_mfc_mem[1].size = lsize;
95
96 for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
97 struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
98 if (memblock_remove(area->base, area->size)) {
99 printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
100 area->size, (unsigned long) area->base);
101 area->base = 0;
102 }
103 }
104}
105
106static int __init s5p_mfc_memory_init(void)
107{
108 int i;
109
110 for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
111 struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
112 if (!area->base)
113 continue;
114
115 if (dma_declare_coherent_memory(area->dev, area->base,
116 area->base, area->size,
117 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
118 printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
119 area->size, (unsigned long) area->base);
120 }
121 return 0;
122}
123device_initcall(s5p_mfc_memory_init);
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index d973d39666a3..36d3551173b2 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -35,9 +35,10 @@
35#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) 35#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
36#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) 36#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
37#define S5P_VA_SCU S5P_VA_COREPERI(0x0) 37#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
38#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100)
39#define S5P_VA_TWD S5P_VA_COREPERI(0x600) 38#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
40#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) 39
40#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
41#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
41 42
42#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) 43#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
43 44
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h
new file mode 100644
index 000000000000..6697f8cb2949
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mfc.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_S5P_MFC_H
11#define __PLAT_S5P_MFC_H
12
13/**
14 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
15 * @rbase: base address for MFC 'right' memory interface
16 * @rsize: size of the memory reserved for MFC 'right' interface
17 * @lbase: base address for MFC 'left' memory interface
18 * @lsize: size of the memory reserved for MFC 'left' interface
19 *
20 * This function reserves system memory for both MFC device memory
21 * interfaces and registers it to respective struct device entries as
22 * coherent memory.
23 */
24void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
25 phys_addr_t lbase, unsigned int lsize);
26
27#endif /* __PLAT_S5P_MFC_H */
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 612934c48b0d..7c82f06baf57 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -384,6 +384,7 @@ static void __init s5p_timer_resources(void)
384 384
385 unsigned long event_id = timer_source.event_id; 385 unsigned long event_id = timer_source.event_id;
386 unsigned long source_id = timer_source.source_id; 386 unsigned long source_id = timer_source.source_id;
387 char devname[15];
387 388
388 timerclk = clk_get(NULL, "timers"); 389 timerclk = clk_get(NULL, "timers");
389 if (IS_ERR(timerclk)) 390 if (IS_ERR(timerclk))
@@ -391,6 +392,10 @@ static void __init s5p_timer_resources(void)
391 392
392 clk_enable(timerclk); 393 clk_enable(timerclk);
393 394
395 sprintf(devname, "s3c24xx-pwm.%lu", event_id);
396 s3c_device_timer[event_id].id = event_id;
397 s3c_device_timer[event_id].dev.init_name = devname;
398
394 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); 399 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
395 if (IS_ERR(tin_event)) 400 if (IS_ERR(tin_event))
396 panic("failed to get pwm-tin clock for event timer"); 401 panic("failed to get pwm-tin clock for event timer");
@@ -401,6 +406,10 @@ static void __init s5p_timer_resources(void)
401 406
402 clk_enable(tin_event); 407 clk_enable(tin_event);
403 408
409 sprintf(devname, "s3c24xx-pwm.%lu", source_id);
410 s3c_device_timer[source_id].id = source_id;
411 s3c_device_timer[source_id].dev.init_name = devname;
412
404 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); 413 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
405 if (IS_ERR(tin_source)) 414 if (IS_ERR(tin_source))
406 panic("failed to get pwm-tin clock for source timer"); 415 panic("failed to get pwm-tin clock for source timer");
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index e8f2be2d67f2..ee8deef19481 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -21,6 +21,7 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/regulator/consumer.h>
24 25
25#include <plat/regs-adc.h> 26#include <plat/regs-adc.h>
26#include <plat/adc.h> 27#include <plat/adc.h>
@@ -39,8 +40,9 @@
39 */ 40 */
40 41
41enum s3c_cpu_type { 42enum s3c_cpu_type {
42 TYPE_S3C24XX, 43 TYPE_ADCV1, /* S3C24XX */
43 TYPE_S3C64XX 44 TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
45 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
44}; 46};
45 47
46struct s3c_adc_client { 48struct s3c_adc_client {
@@ -71,6 +73,7 @@ struct adc_device {
71 unsigned int prescale; 73 unsigned int prescale;
72 74
73 int irq; 75 int irq;
76 struct regulator *vdd;
74}; 77};
75 78
76static struct adc_device *adc_dev; 79static struct adc_device *adc_dev;
@@ -91,6 +94,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
91 struct s3c_adc_client *client) 94 struct s3c_adc_client *client)
92{ 95{
93 unsigned con = readl(adc->regs + S3C2410_ADCCON); 96 unsigned con = readl(adc->regs + S3C2410_ADCCON);
97 enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
94 98
95 client->select_cb(client, 1); 99 client->select_cb(client, 1);
96 100
@@ -98,8 +102,12 @@ static inline void s3c_adc_select(struct adc_device *adc,
98 con &= ~S3C2410_ADCCON_STDBM; 102 con &= ~S3C2410_ADCCON_STDBM;
99 con &= ~S3C2410_ADCCON_STARTMASK; 103 con &= ~S3C2410_ADCCON_STARTMASK;
100 104
101 if (!client->is_ts) 105 if (!client->is_ts) {
102 con |= S3C2410_ADCCON_SELMUX(client->channel); 106 if (cpu == TYPE_ADCV3)
107 writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
108 else
109 con |= S3C2410_ADCCON_SELMUX(client->channel);
110 }
103 111
104 writel(con, adc->regs + S3C2410_ADCCON); 112 writel(con, adc->regs + S3C2410_ADCCON);
105} 113}
@@ -285,8 +293,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
285 293
286 client->nr_samples--; 294 client->nr_samples--;
287 295
288 if (cpu == TYPE_S3C64XX) { 296 if (cpu != TYPE_ADCV1) {
289 /* S3C64XX ADC resolution is 12-bit */ 297 /* S3C64XX/S5P ADC resolution is 12-bit */
290 data0 &= 0xfff; 298 data0 &= 0xfff;
291 data1 &= 0xfff; 299 data1 &= 0xfff;
292 } else { 300 } else {
@@ -312,7 +320,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
312 } 320 }
313 321
314exit: 322exit:
315 if (cpu == TYPE_S3C64XX) { 323 if (cpu != TYPE_ADCV1) {
316 /* Clear ADC interrupt */ 324 /* Clear ADC interrupt */
317 writel(0, adc->regs + S3C64XX_ADCCLRINT); 325 writel(0, adc->regs + S3C64XX_ADCCLRINT);
318 } 326 }
@@ -338,17 +346,24 @@ static int s3c_adc_probe(struct platform_device *pdev)
338 adc->pdev = pdev; 346 adc->pdev = pdev;
339 adc->prescale = S3C2410_ADCCON_PRSCVL(49); 347 adc->prescale = S3C2410_ADCCON_PRSCVL(49);
340 348
349 adc->vdd = regulator_get(dev, "vdd");
350 if (IS_ERR(adc->vdd)) {
351 dev_err(dev, "operating without regulator \"vdd\" .\n");
352 ret = PTR_ERR(adc->vdd);
353 goto err_alloc;
354 }
355
341 adc->irq = platform_get_irq(pdev, 1); 356 adc->irq = platform_get_irq(pdev, 1);
342 if (adc->irq <= 0) { 357 if (adc->irq <= 0) {
343 dev_err(dev, "failed to get adc irq\n"); 358 dev_err(dev, "failed to get adc irq\n");
344 ret = -ENOENT; 359 ret = -ENOENT;
345 goto err_alloc; 360 goto err_reg;
346 } 361 }
347 362
348 ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); 363 ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
349 if (ret < 0) { 364 if (ret < 0) {
350 dev_err(dev, "failed to attach adc irq\n"); 365 dev_err(dev, "failed to attach adc irq\n");
351 goto err_alloc; 366 goto err_reg;
352 } 367 }
353 368
354 adc->clk = clk_get(dev, "adc"); 369 adc->clk = clk_get(dev, "adc");
@@ -372,10 +387,14 @@ static int s3c_adc_probe(struct platform_device *pdev)
372 goto err_clk; 387 goto err_clk;
373 } 388 }
374 389
390 ret = regulator_enable(adc->vdd);
391 if (ret)
392 goto err_ioremap;
393
375 clk_enable(adc->clk); 394 clk_enable(adc->clk);
376 395
377 tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; 396 tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
378 if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) { 397 if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
379 /* Enable 12-bit ADC resolution */ 398 /* Enable 12-bit ADC resolution */
380 tmp |= S3C64XX_ADCCON_RESSEL; 399 tmp |= S3C64XX_ADCCON_RESSEL;
381 } 400 }
@@ -388,12 +407,15 @@ static int s3c_adc_probe(struct platform_device *pdev)
388 407
389 return 0; 408 return 0;
390 409
410 err_ioremap:
411 iounmap(adc->regs);
391 err_clk: 412 err_clk:
392 clk_put(adc->clk); 413 clk_put(adc->clk);
393 414
394 err_irq: 415 err_irq:
395 free_irq(adc->irq, adc); 416 free_irq(adc->irq, adc);
396 417 err_reg:
418 regulator_put(adc->vdd);
397 err_alloc: 419 err_alloc:
398 kfree(adc); 420 kfree(adc);
399 return ret; 421 return ret;
@@ -406,6 +428,8 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
406 iounmap(adc->regs); 428 iounmap(adc->regs);
407 free_irq(adc->irq, adc); 429 free_irq(adc->irq, adc);
408 clk_disable(adc->clk); 430 clk_disable(adc->clk);
431 regulator_disable(adc->vdd);
432 regulator_put(adc->vdd);
409 clk_put(adc->clk); 433 clk_put(adc->clk);
410 kfree(adc); 434 kfree(adc);
411 435
@@ -413,8 +437,10 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
413} 437}
414 438
415#ifdef CONFIG_PM 439#ifdef CONFIG_PM
416static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) 440static int s3c_adc_suspend(struct device *dev)
417{ 441{
442 struct platform_device *pdev = container_of(dev,
443 struct platform_device, dev);
418 struct adc_device *adc = platform_get_drvdata(pdev); 444 struct adc_device *adc = platform_get_drvdata(pdev);
419 unsigned long flags; 445 unsigned long flags;
420 u32 con; 446 u32 con;
@@ -428,19 +454,30 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
428 disable_irq(adc->irq); 454 disable_irq(adc->irq);
429 spin_unlock_irqrestore(&adc->lock, flags); 455 spin_unlock_irqrestore(&adc->lock, flags);
430 clk_disable(adc->clk); 456 clk_disable(adc->clk);
457 regulator_disable(adc->vdd);
431 458
432 return 0; 459 return 0;
433} 460}
434 461
435static int s3c_adc_resume(struct platform_device *pdev) 462static int s3c_adc_resume(struct device *dev)
436{ 463{
464 struct platform_device *pdev = container_of(dev,
465 struct platform_device, dev);
437 struct adc_device *adc = platform_get_drvdata(pdev); 466 struct adc_device *adc = platform_get_drvdata(pdev);
467 int ret;
468 unsigned long tmp;
438 469
470 ret = regulator_enable(adc->vdd);
471 if (ret)
472 return ret;
439 clk_enable(adc->clk); 473 clk_enable(adc->clk);
440 enable_irq(adc->irq); 474 enable_irq(adc->irq);
441 475
442 writel(adc->prescale | S3C2410_ADCCON_PRSCEN, 476 tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
443 adc->regs + S3C2410_ADCCON); 477 /* Enable 12-bit ADC resolution */
478 if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
479 tmp |= S3C64XX_ADCCON_RESSEL;
480 writel(tmp, adc->regs + S3C2410_ADCCON);
444 481
445 return 0; 482 return 0;
446} 483}
@@ -453,25 +490,32 @@ static int s3c_adc_resume(struct platform_device *pdev)
453static struct platform_device_id s3c_adc_driver_ids[] = { 490static struct platform_device_id s3c_adc_driver_ids[] = {
454 { 491 {
455 .name = "s3c24xx-adc", 492 .name = "s3c24xx-adc",
456 .driver_data = TYPE_S3C24XX, 493 .driver_data = TYPE_ADCV1,
457 }, { 494 }, {
458 .name = "s3c64xx-adc", 495 .name = "s3c64xx-adc",
459 .driver_data = TYPE_S3C64XX, 496 .driver_data = TYPE_ADCV2,
497 }, {
498 .name = "samsung-adc-v3",
499 .driver_data = TYPE_ADCV3,
460 }, 500 },
461 { } 501 { }
462}; 502};
463MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); 503MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
464 504
505static const struct dev_pm_ops adc_pm_ops = {
506 .suspend = s3c_adc_suspend,
507 .resume = s3c_adc_resume,
508};
509
465static struct platform_driver s3c_adc_driver = { 510static struct platform_driver s3c_adc_driver = {
466 .id_table = s3c_adc_driver_ids, 511 .id_table = s3c_adc_driver_ids,
467 .driver = { 512 .driver = {
468 .name = "s3c-adc", 513 .name = "s3c-adc",
469 .owner = THIS_MODULE, 514 .owner = THIS_MODULE,
515 .pm = &adc_pm_ops,
470 }, 516 },
471 .probe = s3c_adc_probe, 517 .probe = s3c_adc_probe,
472 .remove = __devexit_p(s3c_adc_remove), 518 .remove = __devexit_p(s3c_adc_remove),
473 .suspend = s3c_adc_suspend,
474 .resume = s3c_adc_resume,
475}; 519};
476 520
477static int __init adc_init(void) 521static int __init adc_init(void)
@@ -485,4 +529,4 @@ static int __init adc_init(void)
485 return ret; 529 return ret;
486} 530}
487 531
488arch_initcall(adc_init); 532module_init(adc_init);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 772892826ffc..aecf9e90d4fc 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
71 return 0; 71 return 0;
72} 72}
73 73
74static int dev_is_s3c_uart(struct device *dev)
75{
76 struct platform_device **pdev = s3c24xx_uart_devs;
77 int i;
78 for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
79 if (*pdev && dev == &(*pdev)->dev)
80 return 1;
81 return 0;
82}
83
84/*
85 * Serial drivers call get_clock() very early, before platform bus
86 * has been set up, this requires a special check to let them get
87 * a proper clock
88 */
89
90static int dev_is_platform_device(struct device *dev)
91{
92 return dev->bus == &platform_bus_type ||
93 (dev->bus == NULL && dev_is_s3c_uart(dev));
94}
95
96/* Clock API calls */
97
98struct clk *clk_get(struct device *dev, const char *id)
99{
100 struct clk *p;
101 struct clk *clk = ERR_PTR(-ENOENT);
102 int idno;
103
104 if (dev == NULL || !dev_is_platform_device(dev))
105 idno = -1;
106 else
107 idno = to_platform_device(dev)->id;
108
109 spin_lock(&clocks_lock);
110
111 list_for_each_entry(p, &clocks, list) {
112 if (p->id == idno &&
113 strcmp(id, p->name) == 0 &&
114 try_module_get(p->owner)) {
115 clk = p;
116 break;
117 }
118 }
119
120 /* check for the case where a device was supplied, but the
121 * clock that was being searched for is not device specific */
122
123 if (IS_ERR(clk)) {
124 list_for_each_entry(p, &clocks, list) {
125 if (p->id == -1 && strcmp(id, p->name) == 0 &&
126 try_module_get(p->owner)) {
127 clk = p;
128 break;
129 }
130 }
131 }
132
133 spin_unlock(&clocks_lock);
134 return clk;
135}
136
137void clk_put(struct clk *clk)
138{
139 module_put(clk->owner);
140}
141
142int clk_enable(struct clk *clk) 74int clk_enable(struct clk *clk)
143{ 75{
144 if (IS_ERR(clk) || clk == NULL) 76 if (IS_ERR(clk) || clk == NULL)
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
241 return ret; 173 return ret;
242} 174}
243 175
244EXPORT_SYMBOL(clk_get);
245EXPORT_SYMBOL(clk_put);
246EXPORT_SYMBOL(clk_enable); 176EXPORT_SYMBOL(clk_enable);
247EXPORT_SYMBOL(clk_disable); 177EXPORT_SYMBOL(clk_disable);
248EXPORT_SYMBOL(clk_get_rate); 178EXPORT_SYMBOL(clk_get_rate);
@@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
265 195
266struct clk clk_xtal = { 196struct clk clk_xtal = {
267 .name = "xtal", 197 .name = "xtal",
268 .id = -1,
269 .rate = 0, 198 .rate = 0,
270 .parent = NULL, 199 .parent = NULL,
271 .ctrlbit = 0, 200 .ctrlbit = 0,
@@ -273,30 +202,25 @@ struct clk clk_xtal = {
273 202
274struct clk clk_ext = { 203struct clk clk_ext = {
275 .name = "ext", 204 .name = "ext",
276 .id = -1,
277}; 205};
278 206
279struct clk clk_epll = { 207struct clk clk_epll = {
280 .name = "epll", 208 .name = "epll",
281 .id = -1,
282}; 209};
283 210
284struct clk clk_mpll = { 211struct clk clk_mpll = {
285 .name = "mpll", 212 .name = "mpll",
286 .id = -1,
287 .ops = &clk_ops_def_setrate, 213 .ops = &clk_ops_def_setrate,
288}; 214};
289 215
290struct clk clk_upll = { 216struct clk clk_upll = {
291 .name = "upll", 217 .name = "upll",
292 .id = -1,
293 .parent = NULL, 218 .parent = NULL,
294 .ctrlbit = 0, 219 .ctrlbit = 0,
295}; 220};
296 221
297struct clk clk_f = { 222struct clk clk_f = {
298 .name = "fclk", 223 .name = "fclk",
299 .id = -1,
300 .rate = 0, 224 .rate = 0,
301 .parent = &clk_mpll, 225 .parent = &clk_mpll,
302 .ctrlbit = 0, 226 .ctrlbit = 0,
@@ -304,7 +228,6 @@ struct clk clk_f = {
304 228
305struct clk clk_h = { 229struct clk clk_h = {
306 .name = "hclk", 230 .name = "hclk",
307 .id = -1,
308 .rate = 0, 231 .rate = 0,
309 .parent = NULL, 232 .parent = NULL,
310 .ctrlbit = 0, 233 .ctrlbit = 0,
@@ -313,7 +236,6 @@ struct clk clk_h = {
313 236
314struct clk clk_p = { 237struct clk clk_p = {
315 .name = "pclk", 238 .name = "pclk",
316 .id = -1,
317 .rate = 0, 239 .rate = 0,
318 .parent = NULL, 240 .parent = NULL,
319 .ctrlbit = 0, 241 .ctrlbit = 0,
@@ -322,7 +244,6 @@ struct clk clk_p = {
322 244
323struct clk clk_usb_bus = { 245struct clk clk_usb_bus = {
324 .name = "usb-bus", 246 .name = "usb-bus",
325 .id = -1,
326 .rate = 0, 247 .rate = 0,
327 .parent = &clk_upll, 248 .parent = &clk_upll,
328}; 249};
@@ -330,7 +251,6 @@ struct clk clk_usb_bus = {
330 251
331struct clk s3c24xx_uclk = { 252struct clk s3c24xx_uclk = {
332 .name = "uclk", 253 .name = "uclk",
333 .id = -1,
334}; 254};
335 255
336/* initialise the clock system */ 256/* initialise the clock system */
@@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk)
346 if (clk->enable == NULL) 266 if (clk->enable == NULL)
347 clk->enable = clk_null_enable; 267 clk->enable = clk_null_enable;
348 268
349 /* add to the list of available clocks */ 269 /* fill up the clk_lookup structure and register it*/
350 270 clk->lookup.dev_id = clk->devname;
351 /* Quick check to see if this clock has already been registered. */ 271 clk->lookup.con_id = clk->name;
352 BUG_ON(clk->list.prev != clk->list.next); 272 clk->lookup.clk = clk;
353 273 clkdev_add(&clk->lookup);
354 spin_lock(&clocks_lock);
355 list_add(&clk->list, &clocks);
356 spin_unlock(&clocks_lock);
357 274
358 return 0; 275 return 0;
359} 276}
@@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c)
463 char s[255]; 380 char s[255];
464 char *p = s; 381 char *p = s;
465 382
466 p += sprintf(p, "%s", c->name); 383 p += sprintf(p, "%s", c->devname);
467
468 if (c->id >= 0)
469 sprintf(p, ":%d", c->id);
470 384
471 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); 385 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
472 if (!d) 386 if (!d)
diff --git a/arch/arm/plat-samsung/dev-asocdma.c b/arch/arm/plat-samsung/dev-asocdma.c
index a068c4f42d56..97e35d3c064d 100644
--- a/arch/arm/plat-samsung/dev-asocdma.c
+++ b/arch/arm/plat-samsung/dev-asocdma.c
@@ -23,3 +23,13 @@ struct platform_device samsung_asoc_dma = {
23 } 23 }
24}; 24};
25EXPORT_SYMBOL(samsung_asoc_dma); 25EXPORT_SYMBOL(samsung_asoc_dma);
26
27struct platform_device samsung_asoc_idma = {
28 .name = "samsung-idma",
29 .id = -1,
30 .dev = {
31 .dma_mask = &audio_dmamask,
32 .coherent_dma_mask = DMA_BIT_MASK(32),
33 }
34};
35EXPORT_SYMBOL(samsung_asoc_idma);
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
index a0826ed2f9fe..aa9875f77c40 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -44,6 +44,7 @@ struct samsung_i2s {
44 * Also corresponds to clocks of I2SMOD[10] 44 * Also corresponds to clocks of I2SMOD[10]
45 */ 45 */
46 const char **src_clk; 46 const char **src_clk;
47 dma_addr_t idma_addr;
47}; 48};
48 49
49/** 50/**
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 983c578b8276..87d5b38a86fb 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -10,6 +10,7 @@
10*/ 10*/
11 11
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/clkdev.h>
13 14
14struct clk; 15struct clk;
15 16
@@ -40,6 +41,7 @@ struct clk {
40 struct module *owner; 41 struct module *owner;
41 struct clk *parent; 42 struct clk *parent;
42 const char *name; 43 const char *name;
44 const char *devname;
43 int id; 45 int id;
44 int usage; 46 int usage;
45 unsigned long rate; 47 unsigned long rate;
@@ -47,6 +49,7 @@ struct clk {
47 49
48 struct clk_ops *ops; 50 struct clk_ops *ops;
49 int (*enable)(struct clk *, int enable); 51 int (*enable)(struct clk *, int enable);
52 struct clk_lookup lookup;
50#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 53#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
51 struct dentry *dent; /* For visible tree hierarchy */ 54 struct dentry *dent; /* For visible tree hierarchy */
52#endif 55#endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e3b31c26ac3e..24ebb1e1de41 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -40,6 +40,7 @@ extern struct platform_device s3c64xx_device_spi0;
40extern struct platform_device s3c64xx_device_spi1; 40extern struct platform_device s3c64xx_device_spi1;
41 41
42extern struct platform_device samsung_asoc_dma; 42extern struct platform_device samsung_asoc_dma;
43extern struct platform_device samsung_asoc_idma;
43 44
44extern struct platform_device s3c64xx_device_pcm0; 45extern struct platform_device s3c64xx_device_pcm0;
45extern struct platform_device s3c64xx_device_pcm1; 46extern struct platform_device s3c64xx_device_pcm1;
@@ -49,6 +50,7 @@ extern struct platform_device s3c64xx_device_ac97;
49extern struct platform_device s3c_device_ts; 50extern struct platform_device s3c_device_ts;
50 51
51extern struct platform_device s3c_device_fb; 52extern struct platform_device s3c_device_fb;
53extern struct platform_device s5p_device_fimd0;
52extern struct platform_device s3c_device_ohci; 54extern struct platform_device s3c_device_ohci;
53extern struct platform_device s3c_device_lcd; 55extern struct platform_device s3c_device_lcd;
54extern struct platform_device s3c_device_wdt; 56extern struct platform_device s3c_device_wdt;
@@ -112,6 +114,7 @@ extern struct platform_device exynos4_device_i2s2;
112extern struct platform_device exynos4_device_spdif; 114extern struct platform_device exynos4_device_spdif;
113extern struct platform_device exynos4_device_pd[]; 115extern struct platform_device exynos4_device_pd[];
114extern struct platform_device exynos4_device_ahci; 116extern struct platform_device exynos4_device_ahci;
117extern struct platform_device exynos4_device_dwmci;
115 118
116extern struct platform_device s5p6440_device_pcm; 119extern struct platform_device s5p6440_device_pcm;
117extern struct platform_device s5p6440_device_iis; 120extern struct platform_device s5p6440_device_iis;
@@ -136,6 +139,9 @@ extern struct platform_device s5p_device_fimc1;
136extern struct platform_device s5p_device_fimc2; 139extern struct platform_device s5p_device_fimc2;
137extern struct platform_device s5p_device_fimc3; 140extern struct platform_device s5p_device_fimc3;
138 141
142extern struct platform_device s5p_device_mfc;
143extern struct platform_device s5p_device_mfc_l;
144extern struct platform_device s5p_device_mfc_r;
139extern struct platform_device s5p_device_mipi_csis0; 145extern struct platform_device s5p_device_mipi_csis0;
140extern struct platform_device s5p_device_mipi_csis1; 146extern struct platform_device s5p_device_mipi_csis1;
141 147
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index bca383efcf6d..6abcbf139cee 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,4 +26,19 @@ static inline void s3c_fb_setname(char *name)
26#endif 26#endif
27} 27}
28 28
29/* Re-define device name depending on support. */
30static inline void s5p_fb_setname(int id, char *name)
31{
32 switch (id) {
33#ifdef CONFIG_S5P_DEV_FIMD0
34 case 0:
35 s5p_device_fimd0.name = name;
36 break;
37#endif
38 default:
39 printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
40 break;
41 }
42}
43
29#endif /* __ASM_PLAT_FB_CORE_H */ 44#endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index cb3ca3adc685..01f10e4d00c7 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -74,6 +74,14 @@ struct s3c_fb_platdata {
74extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); 74extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
75 75
76/** 76/**
77 * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
78 * @pd: The platform data to set. The data is copied from the passed structure
79 * so the machine data can mark the data __initdata so that any unused
80 * machines will end up dumping their data at runtime.
81 */
82extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
83
84/**
77 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD 85 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
78 * 86 *
79 * Initialise the GPIO for an 24bpp LCD display on the RGB interface. 87 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
@@ -94,4 +102,11 @@ extern void s5pc100_fb_gpio_setup_24bpp(void);
94 */ 102 */
95extern void s5pv210_fb_gpio_setup_24bpp(void); 103extern void s5pv210_fb_gpio_setup_24bpp(void);
96 104
105/**
106 * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
107 *
108 * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
109 */
110extern void exynos4_fimd0_gpio_setup_24bpp(void);
111
97#endif /* __PLAT_S3C_FB_H */ 112#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 7554c4fcddb9..035e8c38d69c 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -21,6 +21,7 @@
21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) 21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) 22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) 23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
24#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
24#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) 25#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
25 26
26 27
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 32582c0958e3..8960eaf8bb22 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -19,6 +19,8 @@
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/mach/irq.h>
23
22#include <mach/map.h> 24#include <mach/map.h>
23#include <plat/irq-uart.h> 25#include <plat/irq-uart.h>
24#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
@@ -30,9 +32,12 @@
30static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) 32static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
31{ 33{
32 struct s3c_uart_irq *uirq = desc->irq_data.handler_data; 34 struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
35 struct irq_chip *chip = irq_get_chip(irq);
33 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); 36 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
34 int base = uirq->base_irq; 37 int base = uirq->base_irq;
35 38
39 chained_irq_enter(chip, desc);
40
36 if (pend & (1 << 0)) 41 if (pend & (1 << 0))
37 generic_handle_irq(base); 42 generic_handle_irq(base);
38 if (pend & (1 << 1)) 43 if (pend & (1 << 1))
@@ -41,6 +46,8 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
41 generic_handle_irq(base + 2); 46 generic_handle_irq(base + 2);
42 if (pend & (1 << 3)) 47 if (pend & (1 << 3))
43 generic_handle_irq(base + 3); 48 generic_handle_irq(base + 3);
49
50 chained_irq_exit(chip, desc);
44} 51}
45 52
46static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) 53static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5c0a440d6e16..4f9a9515beae 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -268,6 +268,7 @@ static int s3c_pm_enter(suspend_state_t state)
268 /* save all necessary core registers not covered by the drivers */ 268 /* save all necessary core registers not covered by the drivers */
269 269
270 s3c_pm_save_gpios(); 270 s3c_pm_save_gpios();
271 s3c_pm_saved_gpios();
271 s3c_pm_save_uarts(); 272 s3c_pm_save_uarts();
272 s3c_pm_save_core(); 273 s3c_pm_save_core();
273 274
@@ -309,6 +310,7 @@ static int s3c_pm_enter(suspend_state_t state)
309 s3c_pm_restore_core(); 310 s3c_pm_restore_core();
310 s3c_pm_restore_uarts(); 311 s3c_pm_restore_uarts();
311 s3c_pm_restore_gpios(); 312 s3c_pm_restore_gpios();
313 s3c_pm_restored_gpios();
312 314
313 s3c_pm_debug_init(); 315 s3c_pm_debug_init();
314 316
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index 46c9381e083b..f1bba88ed2f5 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
268 [0] = { 268 [0] = {
269 .clk = { 269 .clk = {
270 .name = "pwm-tdiv", 270 .name = "pwm-tdiv",
271 .devname = "s3c24xx-pwm.0",
271 .ops = &clk_tdiv_ops, 272 .ops = &clk_tdiv_ops,
272 .parent = &clk_timer_scaler[0], 273 .parent = &clk_timer_scaler[0],
273 }, 274 },
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
275 [1] = { 276 [1] = {
276 .clk = { 277 .clk = {
277 .name = "pwm-tdiv", 278 .name = "pwm-tdiv",
279 .devname = "s3c24xx-pwm.1",
278 .ops = &clk_tdiv_ops, 280 .ops = &clk_tdiv_ops,
279 .parent = &clk_timer_scaler[0], 281 .parent = &clk_timer_scaler[0],
280 } 282 }
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
282 [2] = { 284 [2] = {
283 .clk = { 285 .clk = {
284 .name = "pwm-tdiv", 286 .name = "pwm-tdiv",
287 .devname = "s3c24xx-pwm.2",
285 .ops = &clk_tdiv_ops, 288 .ops = &clk_tdiv_ops,
286 .parent = &clk_timer_scaler[1], 289 .parent = &clk_timer_scaler[1],
287 }, 290 },
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
289 [3] = { 292 [3] = {
290 .clk = { 293 .clk = {
291 .name = "pwm-tdiv", 294 .name = "pwm-tdiv",
295 .devname = "s3c24xx-pwm.3",
292 .ops = &clk_tdiv_ops, 296 .ops = &clk_tdiv_ops,
293 .parent = &clk_timer_scaler[1], 297 .parent = &clk_timer_scaler[1],
294 }, 298 },
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
296 [4] = { 300 [4] = {
297 .clk = { 301 .clk = {
298 .name = "pwm-tdiv", 302 .name = "pwm-tdiv",
303 .devname = "s3c24xx-pwm.4",
299 .ops = &clk_tdiv_ops, 304 .ops = &clk_tdiv_ops,
300 .parent = &clk_timer_scaler[1], 305 .parent = &clk_timer_scaler[1],
301 }, 306 },
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
361static struct clk clk_tin[] = { 366static struct clk clk_tin[] = {
362 [0] = { 367 [0] = {
363 .name = "pwm-tin", 368 .name = "pwm-tin",
369 .devname = "s3c24xx-pwm.0",
364 .id = 0, 370 .id = 0,
365 .ops = &clk_tin_ops, 371 .ops = &clk_tin_ops,
366 }, 372 },
367 [1] = { 373 [1] = {
368 .name = "pwm-tin", 374 .name = "pwm-tin",
375 .devname = "s3c24xx-pwm.1",
369 .id = 1, 376 .id = 1,
370 .ops = &clk_tin_ops, 377 .ops = &clk_tin_ops,
371 }, 378 },
372 [2] = { 379 [2] = {
373 .name = "pwm-tin", 380 .name = "pwm-tin",
381 .devname = "s3c24xx-pwm.2",
374 .id = 2, 382 .id = 2,
375 .ops = &clk_tin_ops, 383 .ops = &clk_tin_ops,
376 }, 384 },
377 [3] = { 385 [3] = {
378 .name = "pwm-tin", 386 .name = "pwm-tin",
387 .devname = "s3c24xx-pwm.3",
379 .id = 3, 388 .id = 3,
380 .ops = &clk_tin_ops, 389 .ops = &clk_tin_ops,
381 }, 390 },
382 [4] = { 391 [4] = {
383 .name = "pwm-tin", 392 .name = "pwm-tin",
393 .devname = "s3c24xx-pwm.4",
384 .id = 4, 394 .id = 4,
385 .ops = &clk_tin_ops, 395 .ops = &clk_tin_ops,
386 }, 396 },
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 2231d80ad817..e3bb806bbafe 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
259 clk_enable(timerclk); 259 clk_enable(timerclk);
260 260
261 if (!use_tclk1_12()) { 261 if (!use_tclk1_12()) {
262 tmpdev.id = 4;
263 tmpdev.dev.init_name = "s3c24xx-pwm.4";
262 tin = clk_get(&tmpdev.dev, "pwm-tin"); 264 tin = clk_get(&tmpdev.dev, "pwm-tin");
263 if (IS_ERR(tin)) 265 if (IS_ERR(tin))
264 panic("failed to get pwm-tin clock for system timer"); 266 panic("failed to get pwm-tin clock for system timer");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 05:26:21 -0500