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authorKelvin Cheung <keguang.zhang@gmail.com>2012-07-25 10:17:24 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-25 10:17:24 -0400
commitca585cf9fb818bfcfcac6968c2b242dcd0693b08 (patch)
treedd0d228367155b704e150bbfbbd56f7a6a6a00d1 /arch
parent2fa36399e63c911134f28b6878aada9b395c4209 (diff)
MIPS: Loongson 1B: Add board support
Adds basic platform devices for Loongson 1B, including serial port, ethernet, USB, RTC and interrupt handler. The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is built around a Synopsys IP Core. Use normal instead of enhanced descriptors. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4133/ Patchwork: https://patchwork.linux-mips.org/patch/4134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig30
-rw-r--r--arch/mips/include/asm/mach-loongson1/irq.h73
-rw-r--r--arch/mips/include/asm/mach-loongson1/loongson1.h44
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h23
-rw-r--r--arch/mips/include/asm/mach-loongson1/prom.h24
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h33
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-wdt.h22
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h25
-rw-r--r--arch/mips/loongson1/Kconfig21
-rw-r--r--arch/mips/loongson1/Makefile11
-rw-r--r--arch/mips/loongson1/Platform7
-rw-r--r--arch/mips/loongson1/common/Makefile5
-rw-r--r--arch/mips/loongson1/common/clock.c165
-rw-r--r--arch/mips/loongson1/common/irq.c147
-rw-r--r--arch/mips/loongson1/common/platform.c124
-rw-r--r--arch/mips/loongson1/common/prom.c87
-rw-r--r--arch/mips/loongson1/common/reset.c45
-rw-r--r--arch/mips/loongson1/common/setup.c29
-rw-r--r--arch/mips/loongson1/ls1b/Makefile5
-rw-r--r--arch/mips/loongson1/ls1b/board.c33
21 files changed, 954 insertions, 0 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029f558b..d64786d5e2f3 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
14platforms += lantiq 14platforms += lantiq
15platforms += lasat 15platforms += lasat
16platforms += loongson 16platforms += loongson
17platforms += loongson1
17platforms += mipssim 18platforms += mipssim
18platforms += mti-malta 19platforms += mti-malta
19platforms += netlogic 20platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3e10fdd3898..73457d18506a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -264,6 +264,16 @@ config MACH_LOONGSON
264 Chinese Academy of Sciences (CAS) in the People's Republic 264 Chinese Academy of Sciences (CAS) in the People's Republic
265 of China. The chief architect is Professor Weiwu Hu. 265 of China. The chief architect is Professor Weiwu Hu.
266 266
267config MACH_LOONGSON1
268 bool "Loongson 1 family of machines"
269 select SYS_SUPPORTS_ZBOOT
270 help
271 This enables support for the Loongson 1 based machines.
272
273 Loongson 1 is a family of 32-bit MIPS-compatible SoCs developed by
274 the ICT (Institute of Computing Technology) and the Chinese Academy
275 of Sciences.
276
267config MIPS_MALTA 277config MIPS_MALTA
268 bool "MIPS Malta board" 278 bool "MIPS Malta board"
269 select ARCH_MAY_HAVE_PC_FDC 279 select ARCH_MAY_HAVE_PC_FDC
@@ -836,6 +846,7 @@ source "arch/mips/txx9/Kconfig"
836source "arch/mips/vr41xx/Kconfig" 846source "arch/mips/vr41xx/Kconfig"
837source "arch/mips/cavium-octeon/Kconfig" 847source "arch/mips/cavium-octeon/Kconfig"
838source "arch/mips/loongson/Kconfig" 848source "arch/mips/loongson/Kconfig"
849source "arch/mips/loongson1/Kconfig"
839source "arch/mips/netlogic/Kconfig" 850source "arch/mips/netlogic/Kconfig"
840 851
841endmenu 852endmenu
@@ -1217,6 +1228,14 @@ config CPU_LOONGSON2F
1217 have a similar programming interface with FPGA northbridge used in 1228 have a similar programming interface with FPGA northbridge used in
1218 Loongson2E. 1229 Loongson2E.
1219 1230
1231config CPU_LOONGSON1B
1232 bool "Loongson 1B"
1233 depends on SYS_HAS_CPU_LOONGSON1B
1234 select CPU_LOONGSON1
1235 help
1236 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1237 release 2 instruction set.
1238
1220config CPU_MIPS32_R1 1239config CPU_MIPS32_R1
1221 bool "MIPS32 Release 1" 1240 bool "MIPS32 Release 1"
1222 depends on SYS_HAS_CPU_MIPS32_R1 1241 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1544,6 +1563,14 @@ config CPU_LOONGSON2
1544 select CPU_SUPPORTS_64BIT_KERNEL 1563 select CPU_SUPPORTS_64BIT_KERNEL
1545 select CPU_SUPPORTS_HIGHMEM 1564 select CPU_SUPPORTS_HIGHMEM
1546 1565
1566config CPU_LOONGSON1
1567 bool
1568 select CPU_MIPS32
1569 select CPU_MIPSR2
1570 select CPU_HAS_PREFETCH
1571 select CPU_SUPPORTS_32BIT_KERNEL
1572 select CPU_SUPPORTS_HIGHMEM
1573
1547config CPU_BMIPS 1574config CPU_BMIPS
1548 bool 1575 bool
1549 select CPU_MIPS32 1576 select CPU_MIPS32
@@ -1562,6 +1589,9 @@ config SYS_HAS_CPU_LOONGSON2F
1562 select CPU_SUPPORTS_ADDRWINCFG if 64BIT 1589 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1563 select CPU_SUPPORTS_UNCACHED_ACCELERATED 1590 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1564 1591
1592config SYS_HAS_CPU_LOONGSON1B
1593 bool
1594
1565config SYS_HAS_CPU_MIPS32_R1 1595config SYS_HAS_CPU_MIPS32_R1
1566 bool 1596 bool
1567 1597
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000000000000..da96ed42f733
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * IRQ mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_IRQ_H
14#define __ASM_MACH_LOONGSON1_IRQ_H
15
16/*
17 * CPU core Interrupt Numbers
18 */
19#define MIPS_CPU_IRQ_BASE 0
20#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
21
22#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
23#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
24#define INT0_IRQ MIPS_CPU_IRQ(2)
25#define INT1_IRQ MIPS_CPU_IRQ(3)
26#define INT2_IRQ MIPS_CPU_IRQ(4)
27#define INT3_IRQ MIPS_CPU_IRQ(5)
28#define INT4_IRQ MIPS_CPU_IRQ(6)
29#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
30
31#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
32
33/*
34 * INT0~3 Interrupt Numbers
35 */
36#define LS1X_IRQ_BASE MIPS_CPU_IRQS
37#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
38
39#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
40#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
41#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
42#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
43#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
44#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
45#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
46#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
47#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
48#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
49#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
50#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
51#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
52#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
53#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
54#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
55#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
56#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
57#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
58#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
59#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
60#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
61#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
62#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
63
64#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
65#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
66#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
67#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
68
69#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
70
71#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
72
73#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
new file mode 100644
index 000000000000..4e18e88cebbf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Register mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
14#define __ASM_MACH_LOONGSON1_LOONGSON1_H
15
16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17
18/* Loongson 1 Register Bases */
19#define LS1X_INTC_BASE 0x1fd01040
20#define LS1X_EHCI_BASE 0x1fe00000
21#define LS1X_OHCI_BASE 0x1fe08000
22#define LS1X_GMAC0_BASE 0x1fe10000
23#define LS1X_GMAC1_BASE 0x1fe20000
24
25#define LS1X_UART0_BASE 0x1fe40000
26#define LS1X_UART1_BASE 0x1fe44000
27#define LS1X_UART2_BASE 0x1fe48000
28#define LS1X_UART3_BASE 0x1fe4c000
29#define LS1X_CAN0_BASE 0x1fe50000
30#define LS1X_CAN1_BASE 0x1fe54000
31#define LS1X_I2C0_BASE 0x1fe58000
32#define LS1X_I2C1_BASE 0x1fe68000
33#define LS1X_I2C2_BASE 0x1fe70000
34#define LS1X_PWM_BASE 0x1fe5c000
35#define LS1X_WDT_BASE 0x1fe5c060
36#define LS1X_RTC_BASE 0x1fe64000
37#define LS1X_AC97_BASE 0x1fe74000
38#define LS1X_NAND_BASE 0x1fe78000
39#define LS1X_CLK_BASE 0x1fe78030
40
41#include <regs-clk.h>
42#include <regs-wdt.h>
43
44#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
new file mode 100644
index 000000000000..2f171617bade
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10
11#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
12#define __ASM_MACH_LOONGSON1_PLATFORM_H
13
14#include <linux/platform_device.h>
15
16extern struct platform_device ls1x_uart_device;
17extern struct platform_device ls1x_eth0_device;
18extern struct platform_device ls1x_ehci_device;
19extern struct platform_device ls1x_rtc_device;
20
21void ls1x_serial_setup(void);
22
23#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
new file mode 100644
index 000000000000..b871dc41b8d9
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __ASM_MACH_LOONGSON1_PROM_H
11#define __ASM_MACH_LOONGSON1_PROM_H
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16
17/* environment arguments from bootloader */
18extern unsigned long memsize, highmemsize;
19
20/* loongson-specific command line, env and memory initialization */
21extern char *prom_getenv(char *name);
22extern void __init prom_init_cmdline(void);
23
24#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 000000000000..8efa7fb9f73a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 Clock Register Definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
13#define __ASM_MACH_LOONGSON1_REGS_CLK_H
14
15#define LS1X_CLK_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
17
18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20
21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC (0x1f << 26)
24#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU (0x1f << 20)
26#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR (0x1f << 14)
28
29#define DIV_DC_SHIFT 26
30#define DIV_CPU_SHIFT 20
31#define DIV_DDR_SHIFT 14
32
33#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 000000000000..f897de68c527
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 watchdog register definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
13#define __ASM_MACH_LOONGSON1_REGS_WDT_H
14
15#define LS1X_WDT_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
17
18#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
19#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
20#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
21
22#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
new file mode 100644
index 000000000000..e3680a8fb349
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_LOONGSON1_WAR_H
9#define __ASM_MACH_LOONGSON1_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 000000000000..237fa214de9f
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
1if MACH_LOONGSON1
2
3choice
4 prompt "Machine Type"
5
6config LOONGSON1_LS1B
7 bool "Loongson LS1B board"
8 select CEVT_R4K
9 select CSRC_R4K
10 select SYS_HAS_CPU_LOONGSON1B
11 select DMA_NONCOHERENT
12 select BOOT_ELF32
13 select IRQ_CPU
14 select SYS_SUPPORTS_32BIT_KERNEL
15 select SYS_SUPPORTS_LITTLE_ENDIAN
16 select SYS_SUPPORTS_HIGHMEM
17 select SYS_HAS_EARLY_PRINTK
18
19endchoice
20
21endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 000000000000..9719c75886f5
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
1#
2# Common code for all Loongson 1 based systems
3#
4
5obj-$(CONFIG_MACH_LOONGSON1) += common/
6
7#
8# Loongson LS1B board
9#
10
11obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 000000000000..99bdefe627af
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
1cflags-$(CONFIG_CPU_LOONGSON1) += \
2 $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
3 -Wa,-mips32r2 -Wa,--trap
4
5platform-$(CONFIG_MACH_LOONGSON1) += loongson1/
6cflags-$(CONFIG_MACH_LOONGSON1) += -I$(srctree)/arch/mips/include/asm/mach-loongson1
7load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000
diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile
new file mode 100644
index 000000000000..b2797709ef5b
--- /dev/null
+++ b/arch/mips/loongson1/common/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for common code of loongson1 based machines.
3#
4
5obj-y += clock.o irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c
new file mode 100644
index 000000000000..2d98fb030596
--- /dev/null
+++ b/arch/mips/loongson1/common/clock.c
@@ -0,0 +1,165 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/module.h>
11#include <linux/list.h>
12#include <linux/mutex.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <asm/clock.h>
16#include <asm/time.h>
17
18#include <loongson1.h>
19
20static LIST_HEAD(clocks);
21static DEFINE_MUTEX(clocks_mutex);
22
23struct clk *clk_get(struct device *dev, const char *name)
24{
25 struct clk *c;
26 struct clk *ret = NULL;
27
28 mutex_lock(&clocks_mutex);
29 list_for_each_entry(c, &clocks, node) {
30 if (!strcmp(c->name, name)) {
31 ret = c;
32 break;
33 }
34 }
35 mutex_unlock(&clocks_mutex);
36
37 return ret;
38}
39EXPORT_SYMBOL(clk_get);
40
41unsigned long clk_get_rate(struct clk *clk)
42{
43 return clk->rate;
44}
45EXPORT_SYMBOL(clk_get_rate);
46
47static void pll_clk_init(struct clk *clk)
48{
49 u32 pll;
50
51 pll = __raw_readl(LS1X_CLK_PLL_FREQ);
52 clk->rate = (12 + (pll & 0x3f)) * 33 / 2
53 + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
54 clk->rate *= 1000000;
55}
56
57static void cpu_clk_init(struct clk *clk)
58{
59 u32 pll, ctrl;
60
61 pll = clk_get_rate(clk->parent);
62 ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
63 clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
64}
65
66static void ddr_clk_init(struct clk *clk)
67{
68 u32 pll, ctrl;
69
70 pll = clk_get_rate(clk->parent);
71 ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
72 clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
73}
74
75static void dc_clk_init(struct clk *clk)
76{
77 u32 pll, ctrl;
78
79 pll = clk_get_rate(clk->parent);
80 ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
81 clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
82}
83
84static struct clk_ops pll_clk_ops = {
85 .init = pll_clk_init,
86};
87
88static struct clk_ops cpu_clk_ops = {
89 .init = cpu_clk_init,
90};
91
92static struct clk_ops ddr_clk_ops = {
93 .init = ddr_clk_init,
94};
95
96static struct clk_ops dc_clk_ops = {
97 .init = dc_clk_init,
98};
99
100static struct clk pll_clk = {
101 .name = "pll",
102 .ops = &pll_clk_ops,
103};
104
105static struct clk cpu_clk = {
106 .name = "cpu",
107 .parent = &pll_clk,
108 .ops = &cpu_clk_ops,
109};
110
111static struct clk ddr_clk = {
112 .name = "ddr",
113 .parent = &pll_clk,
114 .ops = &ddr_clk_ops,
115};
116
117static struct clk dc_clk = {
118 .name = "dc",
119 .parent = &pll_clk,
120 .ops = &dc_clk_ops,
121};
122
123int clk_register(struct clk *clk)
124{
125 mutex_lock(&clocks_mutex);
126 list_add(&clk->node, &clocks);
127 if (clk->ops->init)
128 clk->ops->init(clk);
129 mutex_unlock(&clocks_mutex);
130
131 return 0;
132}
133EXPORT_SYMBOL(clk_register);
134
135static struct clk *ls1x_clks[] = {
136 &pll_clk,
137 &cpu_clk,
138 &ddr_clk,
139 &dc_clk,
140};
141
142int __init ls1x_clock_init(void)
143{
144 int i;
145
146 for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++)
147 clk_register(ls1x_clks[i]);
148
149 return 0;
150}
151
152void __init plat_time_init(void)
153{
154 struct clk *clk;
155
156 /* Initialize LS1X clocks */
157 ls1x_clock_init();
158
159 /* setup mips r4k timer */
160 clk = clk_get(NULL, "cpu");
161 if (IS_ERR(clk))
162 panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
163
164 mips_hpt_frequency = clk_get_rate(clk) / 2;
165}
diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c
new file mode 100644
index 000000000000..41bc8ffe7bba
--- /dev/null
+++ b/arch/mips/loongson1/common/irq.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <asm/irq_cpu.h>
13
14#include <loongson1.h>
15#include <irq.h>
16
17#define LS1X_INTC_REG(n, x) \
18 ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
19
20#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
21#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
22#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
23#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
24#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
25#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
26
27static void ls1x_irq_ack(struct irq_data *d)
28{
29 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
30 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
31
32 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
33 | (1 << bit), LS1X_INTC_INTCLR(n));
34}
35
36static void ls1x_irq_mask(struct irq_data *d)
37{
38 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
39 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
40
41 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
42 & ~(1 << bit), LS1X_INTC_INTIEN(n));
43}
44
45static void ls1x_irq_mask_ack(struct irq_data *d)
46{
47 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
48 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
49
50 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
51 & ~(1 << bit), LS1X_INTC_INTIEN(n));
52 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
53 | (1 << bit), LS1X_INTC_INTCLR(n));
54}
55
56static void ls1x_irq_unmask(struct irq_data *d)
57{
58 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
59 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
60
61 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
62 | (1 << bit), LS1X_INTC_INTIEN(n));
63}
64
65static struct irq_chip ls1x_irq_chip = {
66 .name = "LS1X-INTC",
67 .irq_ack = ls1x_irq_ack,
68 .irq_mask = ls1x_irq_mask,
69 .irq_mask_ack = ls1x_irq_mask_ack,
70 .irq_unmask = ls1x_irq_unmask,
71};
72
73static void ls1x_irq_dispatch(int n)
74{
75 u32 int_status, irq;
76
77 /* Get pending sources, masked by current enables */
78 int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
79 __raw_readl(LS1X_INTC_INTIEN(n));
80
81 if (int_status) {
82 irq = LS1X_IRQ(n, __ffs(int_status));
83 do_IRQ(irq);
84 }
85}
86
87asmlinkage void plat_irq_dispatch(void)
88{
89 unsigned int pending;
90
91 pending = read_c0_cause() & read_c0_status() & ST0_IM;
92
93 if (pending & CAUSEF_IP7)
94 do_IRQ(TIMER_IRQ);
95 else if (pending & CAUSEF_IP2)
96 ls1x_irq_dispatch(0); /* INT0 */
97 else if (pending & CAUSEF_IP3)
98 ls1x_irq_dispatch(1); /* INT1 */
99 else if (pending & CAUSEF_IP4)
100 ls1x_irq_dispatch(2); /* INT2 */
101 else if (pending & CAUSEF_IP5)
102 ls1x_irq_dispatch(3); /* INT3 */
103 else if (pending & CAUSEF_IP6)
104 ls1x_irq_dispatch(4); /* INT4 */
105 else
106 spurious_interrupt();
107
108}
109
110struct irqaction cascade_irqaction = {
111 .handler = no_action,
112 .name = "cascade",
113 .flags = IRQF_NO_THREAD,
114};
115
116static void __init ls1x_irq_init(int base)
117{
118 int n;
119
120 /* Disable interrupts and clear pending,
121 * setup all IRQs as high level triggered
122 */
123 for (n = 0; n < 4; n++) {
124 __raw_writel(0x0, LS1X_INTC_INTIEN(n));
125 __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
126 __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
127 /* set DMA0, DMA1 and DMA2 to edge trigger */
128 __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
129 }
130
131
132 for (n = base; n < LS1X_IRQS; n++) {
133 irq_set_chip_and_handler(n, &ls1x_irq_chip,
134 handle_level_irq);
135 }
136
137 setup_irq(INT0_IRQ, &cascade_irqaction);
138 setup_irq(INT1_IRQ, &cascade_irqaction);
139 setup_irq(INT2_IRQ, &cascade_irqaction);
140 setup_irq(INT3_IRQ, &cascade_irqaction);
141}
142
143void __init arch_init_irq(void)
144{
145 mips_cpu_irq_init();
146 ls1x_irq_init(LS1X_IRQ_BASE);
147}
diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c
new file mode 100644
index 000000000000..e92d59c4bd78
--- /dev/null
+++ b/arch/mips/loongson1/common/platform.c
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/phy.h>
14#include <linux/serial_8250.h>
15#include <linux/stmmac.h>
16#include <asm-generic/sizes.h>
17
18#include <loongson1.h>
19
20#define LS1X_UART(_id) \
21 { \
22 .mapbase = LS1X_UART ## _id ## _BASE, \
23 .irq = LS1X_UART ## _id ## _IRQ, \
24 .iotype = UPIO_MEM, \
25 .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
26 .type = PORT_16550A, \
27 }
28
29static struct plat_serial8250_port ls1x_serial8250_port[] = {
30 LS1X_UART(0),
31 LS1X_UART(1),
32 LS1X_UART(2),
33 LS1X_UART(3),
34 {},
35};
36
37struct platform_device ls1x_uart_device = {
38 .name = "serial8250",
39 .id = PLAT8250_DEV_PLATFORM,
40 .dev = {
41 .platform_data = ls1x_serial8250_port,
42 },
43};
44
45void __init ls1x_serial_setup(void)
46{
47 struct clk *clk;
48 struct plat_serial8250_port *p;
49
50 clk = clk_get(NULL, "dc");
51 if (IS_ERR(clk))
52 panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
53
54 for (p = ls1x_serial8250_port; p->flags != 0; ++p)
55 p->uartclk = clk_get_rate(clk);
56}
57
58/* Synopsys Ethernet GMAC */
59static struct resource ls1x_eth0_resources[] = {
60 [0] = {
61 .start = LS1X_GMAC0_BASE,
62 .end = LS1X_GMAC0_BASE + SZ_64K - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .name = "macirq",
67 .start = LS1X_GMAC0_IRQ,
68 .flags = IORESOURCE_IRQ,
69 },
70};
71
72static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
73 .bus_id = 0,
74 .phy_mask = 0,
75};
76
77static struct plat_stmmacenet_data ls1x_eth_data = {
78 .bus_id = 0,
79 .phy_addr = -1,
80 .mdio_bus_data = &ls1x_mdio_bus_data,
81 .has_gmac = 1,
82 .tx_coe = 1,
83};
84
85struct platform_device ls1x_eth0_device = {
86 .name = "stmmaceth",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(ls1x_eth0_resources),
89 .resource = ls1x_eth0_resources,
90 .dev = {
91 .platform_data = &ls1x_eth_data,
92 },
93};
94
95/* USB EHCI */
96static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
97
98static struct resource ls1x_ehci_resources[] = {
99 [0] = {
100 .start = LS1X_EHCI_BASE,
101 .end = LS1X_EHCI_BASE + SZ_32K - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = LS1X_EHCI_IRQ,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110struct platform_device ls1x_ehci_device = {
111 .name = "ls1x-ehci",
112 .id = -1,
113 .num_resources = ARRAY_SIZE(ls1x_ehci_resources),
114 .resource = ls1x_ehci_resources,
115 .dev = {
116 .dma_mask = &ls1x_ehci_dmamask,
117 },
118};
119
120/* Real Time Clock */
121struct platform_device ls1x_rtc_device = {
122 .name = "ls1x-rtc",
123 .id = -1,
124};
diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c
new file mode 100644
index 000000000000..1f8e49f9886d
--- /dev/null
+++ b/arch/mips/loongson1/common/prom.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Modified from arch/mips/pnx833x/common/prom.c.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/serial_reg.h>
13#include <asm/bootinfo.h>
14
15#include <loongson1.h>
16#include <prom.h>
17
18int prom_argc;
19char **prom_argv, **prom_envp;
20unsigned long memsize, highmemsize;
21
22char *prom_getenv(char *envname)
23{
24 char **env = prom_envp;
25 int i;
26
27 i = strlen(envname);
28
29 while (*env) {
30 if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
31 return *env + i + 1;
32 env++;
33 }
34
35 return 0;
36}
37
38static inline unsigned long env_or_default(char *env, unsigned long dfl)
39{
40 char *str = prom_getenv(env);
41 return str ? simple_strtol(str, 0, 0) : dfl;
42}
43
44void __init prom_init_cmdline(void)
45{
46 char *c = &(arcs_cmdline[0]);
47 int i;
48
49 for (i = 1; i < prom_argc; i++) {
50 strcpy(c, prom_argv[i]);
51 c += strlen(prom_argv[i]);
52 if (i < prom_argc-1)
53 *c++ = ' ';
54 }
55 *c = 0;
56}
57
58void __init prom_init(void)
59{
60 prom_argc = fw_arg0;
61 prom_argv = (char **)fw_arg1;
62 prom_envp = (char **)fw_arg2;
63
64 prom_init_cmdline();
65
66 memsize = env_or_default("memsize", DEFAULT_MEMSIZE);
67 highmemsize = env_or_default("highmemsize", 0x0);
68}
69
70void __init prom_free_prom_memory(void)
71{
72}
73
74#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset))
75
76void __init prom_putchar(char c)
77{
78 int timeout;
79
80 timeout = 1024;
81
82 while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0)
83 && (timeout-- > 0))
84 ;
85
86 writeb(c, PORT(UART_TX));
87}
diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c
new file mode 100644
index 000000000000..fb979a784eca
--- /dev/null
+++ b/arch/mips/loongson1/common/reset.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/io.h>
11#include <linux/pm.h>
12#include <asm/reboot.h>
13
14#include <loongson1.h>
15
16static void ls1x_restart(char *command)
17{
18 __raw_writel(0x1, LS1X_WDT_EN);
19 __raw_writel(0x5000000, LS1X_WDT_TIMER);
20 __raw_writel(0x1, LS1X_WDT_SET);
21}
22
23static void ls1x_halt(void)
24{
25 while (1) {
26 if (cpu_wait)
27 cpu_wait();
28 }
29}
30
31static void ls1x_power_off(void)
32{
33 ls1x_halt();
34}
35
36static int __init ls1x_reboot_setup(void)
37{
38 _machine_restart = ls1x_restart;
39 _machine_halt = ls1x_halt;
40 pm_power_off = ls1x_power_off;
41
42 return 0;
43}
44
45arch_initcall(ls1x_reboot_setup);
diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c
new file mode 100644
index 000000000000..62128cc27e68
--- /dev/null
+++ b/arch/mips/loongson1/common/setup.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <asm/bootinfo.h>
11
12#include <prom.h>
13
14void __init plat_mem_setup(void)
15{
16 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
17}
18
19const char *get_system_type(void)
20{
21 unsigned int processor_id = (&current_cpu_data)->processor_id;
22
23 switch (processor_id & PRID_REV_MASK) {
24 case PRID_REV_LOONGSON1B:
25 return "LOONGSON LS1B";
26 default:
27 return "LOONGSON (unknown)";
28 }
29}
diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile
new file mode 100644
index 000000000000..891eac482b82
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for loongson1B based machines.
3#
4
5obj-y += board.o
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
new file mode 100644
index 000000000000..295b1be893e3
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <platform.h>
11
12#include <linux/serial_8250.h>
13#include <loongson1.h>
14
15static struct platform_device *ls1b_platform_devices[] __initdata = {
16 &ls1x_uart_device,
17 &ls1x_eth0_device,
18 &ls1x_ehci_device,
19 &ls1x_rtc_device,
20};
21
22static int __init ls1b_platform_init(void)
23{
24 int err;
25
26 ls1x_serial_setup();
27
28 err = platform_add_devices(ls1b_platform_devices,
29 ARRAY_SIZE(ls1b_platform_devices));
30 return err;
31}
32
33arch_initcall(ls1b_platform_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 22:54:42 -0500