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authorIngo Molnar <mingo@elte.hu>2010-03-04 05:47:50 -0500
committerIngo Molnar <mingo@elte.hu>2010-03-04 05:47:52 -0500
commit4f16d4e0c9a4b20d9f0db365587b96d6001efd7d (patch)
treefa25dcf285b26f1fac2bf267d0d1cd2c4eba90b8 /arch
parent1e259e0a9982078896f3404240096cbea01daca4 (diff)
parent6630125419ef37ff8781713c5e9d416f2a4ba357 (diff)
Merge branch 'perf/core' into perf/urgent
Merge reason: Switch from pre-merge topical split to the post-merge urgent track Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/Kconfig18
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/include/asm/cacheflush.h3
-rw-r--r--arch/arm/kernel/setup.c1
-rw-r--r--arch/arm/mach-gemini/gpio.c4
-rw-r--r--arch/arm/mach-mx25/clock.c58
-rw-r--r--arch/arm/mach-mx25/mx25pdk.c2
-rw-r--r--arch/arm/mach-mx3/mx31ads.c4
-rw-r--r--arch/arm/mach-omap2/gpmc.c5
-rw-r--r--arch/arm/mach-omap2/irq.c4
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c7
-rw-r--r--arch/arm/mach-omap2/mux.c10
-rw-r--r--arch/arm/mach-omap2/mux34xx.c47
-rw-r--r--arch/arm/mach-omap2/serial.c11
-rw-r--r--arch/arm/mach-realview/realview_pbx.c4
-rw-r--r--arch/arm/mm/alignment.c3
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c137
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h5
-rw-r--r--arch/arm/plat-omap/clock.c4
-rw-r--r--arch/arm/plat-omap/gpio.c4
-rw-r--r--arch/arm/plat-omap/omap_device.c10
-rw-r--r--arch/arm/tools/mach-types46
-rw-r--r--arch/arm/vfp/vfpmodule.c5
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c15
-rw-r--r--arch/ia64/include/asm/acpi.h1
-rw-r--r--arch/ia64/include/asm/elf.h4
-rw-r--r--arch/ia64/kernel/kprobes.c2
-rw-r--r--arch/ia64/sn/kernel/setup.c2
-rw-r--r--arch/microblaze/configs/mmu_defconfig112
-rw-r--r--arch/microblaze/configs/nommu_defconfig101
-rw-r--r--arch/microblaze/include/asm/io.h2
-rw-r--r--arch/microblaze/kernel/cpu/cache.c27
-rw-r--r--arch/microblaze/kernel/entry-nommu.S10
-rw-r--r--arch/microblaze/kernel/setup.c1
-rw-r--r--arch/mips/bcm47xx/prom.c8
-rw-r--r--arch/mips/configs/ip27_defconfig917
-rw-r--r--arch/mips/kernel/cpu-probe.c4
-rw-r--r--arch/mips/kernel/traps.c1
-rw-r--r--arch/mips/mm/c-octeon.c4
-rw-r--r--arch/mips/mm/cache.c2
-rw-r--r--arch/mips/mm/highmem.c1
-rw-r--r--arch/mips/sni/rm200.c2
-rw-r--r--arch/parisc/Kconfig1
-rw-r--r--arch/parisc/kernel/pci.c7
-rw-r--r--arch/parisc/kernel/signal.c4
-rw-r--r--arch/powerpc/kernel/perf_callchain.c3
-rw-r--r--arch/powerpc/kernel/perf_event.c10
-rw-r--r--arch/powerpc/mm/tlb_hash64.c12
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c3
-rw-r--r--arch/powerpc/platforms/85xx/smp.c21
-rw-r--r--arch/powerpc/platforms/pseries/xics.c14
-rw-r--r--arch/s390/include/asm/lowcore.h4
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S3
-rw-r--r--arch/sh/kernel/dwarf.c20
-rw-r--r--arch/sh/kernel/entry-common.S8
-rw-r--r--arch/sh/kernel/perf_callchain.c3
-rw-r--r--arch/sh/kernel/ptrace_64.c11
-rw-r--r--arch/sh/kernel/signal_64.c4
-rw-r--r--arch/sparc/include/asm/stat.h4
-rw-r--r--arch/sparc/kernel/kstack.h4
-rw-r--r--arch/sparc/kernel/of_device_32.c2
-rw-r--r--arch/sparc/kernel/pci.c7
-rw-r--r--arch/sparc/kernel/perf_event.c10
-rw-r--r--arch/sparc/kernel/process_32.c2
-rw-r--r--arch/sparc/kernel/process_64.c8
-rw-r--r--arch/sparc/kernel/signal32.c10
-rw-r--r--arch/sparc/kernel/signal_32.c6
-rw-r--r--arch/sparc/kernel/signal_64.c8
-rw-r--r--arch/sparc/kernel/tsb.S6
-rw-r--r--arch/x86/include/asm/alternative.h5
-rw-r--r--arch/x86/include/asm/debugreg.h3
-rw-r--r--arch/x86/include/asm/elf.h5
-rw-r--r--arch/x86/include/asm/hw_breakpoint.h1
-rw-r--r--arch/x86/include/asm/nmi.h1
-rw-r--r--arch/x86/include/asm/perf_event.h30
-rw-r--r--arch/x86/include/asm/ptrace.h4
-rw-r--r--arch/x86/include/asm/stacktrace.h2
-rw-r--r--arch/x86/include/asm/system.h4
-rw-r--r--arch/x86/kernel/acpi/boot.c13
-rw-r--r--arch/x86/kernel/alternative.c18
-rw-r--r--arch/x86/kernel/apic/apic.c17
-rw-r--r--arch/x86/kernel/apic/probe_32.c29
-rw-r--r--arch/x86/kernel/apic/probe_64.c2
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.c3
-rw-r--r--arch/x86/kernel/cpu/perf_event.c1868
-rw-r--r--arch/x86/kernel/cpu/perf_event_amd.c416
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel.c982
-rw-r--r--arch/x86/kernel/cpu/perf_event_p6.c157
-rw-r--r--arch/x86/kernel/cpu/perfctr-watchdog.c13
-rw-r--r--arch/x86/kernel/dumpstack_32.c5
-rw-r--r--arch/x86/kernel/dumpstack_64.c5
-rw-r--r--arch/x86/kernel/hw_breakpoint.c17
-rw-r--r--arch/x86/kernel/kprobes.c5
-rw-r--r--arch/x86/kernel/mpparse.c7
-rw-r--r--arch/x86/kernel/process_64.c1
-rw-r--r--arch/x86/kernel/ptrace.c24
-rw-r--r--arch/x86/kernel/smpboot.c2
-rw-r--r--arch/x86/kernel/traps.c3
-rw-r--r--arch/x86/kvm/i8254.c3
-rw-r--r--arch/x86/kvm/x86.c7
-rw-r--r--arch/x86/mm/gup.c2
-rw-r--r--arch/x86/oprofile/nmi_int.c17
-rw-r--r--arch/x86/oprofile/op_model_amd.c261
-rw-r--r--arch/x86/oprofile/op_model_p4.c6
-rw-r--r--arch/x86/oprofile/op_model_ppro.c21
-rw-r--r--arch/x86/oprofile/op_x86_model.h20
111 files changed, 3831 insertions, 1962 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 9d055b4f0585..06a13729c8df 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -3,11 +3,9 @@
3# 3#
4 4
5config OPROFILE 5config OPROFILE
6 tristate "OProfile system profiling (EXPERIMENTAL)" 6 tristate "OProfile system profiling"
7 depends on PROFILING 7 depends on PROFILING
8 depends on HAVE_OPROFILE 8 depends on HAVE_OPROFILE
9 depends on TRACING_SUPPORT
10 select TRACING
11 select RING_BUFFER 9 select RING_BUFFER
12 select RING_BUFFER_ALLOW_SWAP 10 select RING_BUFFER_ALLOW_SWAP
13 help 11 help
@@ -17,20 +15,6 @@ config OPROFILE
17 15
18 If unsure, say N. 16 If unsure, say N.
19 17
20config OPROFILE_IBS
21 bool "OProfile AMD IBS support (EXPERIMENTAL)"
22 default n
23 depends on OPROFILE && SMP && X86
24 help
25 Instruction-Based Sampling (IBS) is a new profiling
26 technique that provides rich, precise program performance
27 information. IBS is introduced by AMD Family10h processors
28 (AMD Opteron Quad-Core processor "Barcelona") to overcome
29 the limitations of conventional performance counter
30 sampling.
31
32 If unsure, say N.
33
34config OPROFILE_EVENT_MULTIPLEX 18config OPROFILE_EVENT_MULTIPLEX
35 bool "OProfile multiplexing support (EXPERIMENTAL)" 19 bool "OProfile multiplexing support (EXPERIMENTAL)"
36 default n 20 default n
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4c33ca82f9b1..184a6bd54825 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -702,6 +702,7 @@ config ARCH_OMAP
702 select ARCH_HAS_CPUFREQ 702 select ARCH_HAS_CPUFREQ
703 select GENERIC_TIME 703 select GENERIC_TIME
704 select GENERIC_CLOCKEVENTS 704 select GENERIC_CLOCKEVENTS
705 select ARCH_HAS_HOLES_MEMORYMODEL
705 help 706 help
706 Support for TI's OMAP platform (OMAP1 and OMAP2). 707 Support for TI's OMAP platform (OMAP1 and OMAP2).
707 708
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9e7582572741..356d702c0808 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -94,7 +94,7 @@ CFLAGS_ABI +=-funwind-tables
94endif 94endif
95 95
96ifeq ($(CONFIG_THUMB2_KERNEL),y) 96ifeq ($(CONFIG_THUMB2_KERNEL),y)
97AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it) 97AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
98AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W) 98AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
99CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN) 99CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
100AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb 100AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index c77d2fa1f6e5..8113bb5fb66e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -42,7 +42,8 @@
42#endif 42#endif
43 43
44#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ 44#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
45 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) 45 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
46 defined(CONFIG_CPU_ARM1026)
46# define MULTI_CACHE 1 47# define MULTI_CACHE 1
47#endif 48#endif
48 49
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c6c57b640b6b..621acad8ea43 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -102,6 +102,7 @@ struct cpu_cache_fns cpu_cache;
102#endif 102#endif
103#ifdef CONFIG_OUTER_CACHE 103#ifdef CONFIG_OUTER_CACHE
104struct outer_cache_fns outer_cache; 104struct outer_cache_fns outer_cache;
105EXPORT_SYMBOL(outer_cache);
105#endif 106#endif
106 107
107struct stack { 108struct stack {
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index e7263854bc7b..fe3bd5ac8b10 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -86,7 +86,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
86 unsigned int reg_both, reg_level, reg_type; 86 unsigned int reg_both, reg_level, reg_type;
87 87
88 reg_type = __raw_readl(base + GPIO_INT_TYPE); 88 reg_type = __raw_readl(base + GPIO_INT_TYPE);
89 reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE); 89 reg_level = __raw_readl(base + GPIO_INT_LEVEL);
90 reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE); 90 reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
91 91
92 switch (type) { 92 switch (type) {
@@ -117,7 +117,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
117 } 117 }
118 118
119 __raw_writel(reg_type, base + GPIO_INT_TYPE); 119 __raw_writel(reg_type, base + GPIO_INT_TYPE);
120 __raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE); 120 __raw_writel(reg_level, base + GPIO_INT_LEVEL);
121 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); 121 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
122 122
123 gpio_ack_irq(irq); 123 gpio_ack_irq(irq);
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 6e838b857712..6acc88bcdc40 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -119,6 +119,11 @@ static unsigned long get_rate_nfc(struct clk *clk)
119 return get_rate_per(8); 119 return get_rate_per(8);
120} 120}
121 121
122static unsigned long get_rate_gpt(struct clk *clk)
123{
124 return get_rate_per(5);
125}
126
122static unsigned long get_rate_otg(struct clk *clk) 127static unsigned long get_rate_otg(struct clk *clk)
123{ 128{
124 return 48000000; /* FIXME */ 129 return 48000000; /* FIXME */
@@ -144,7 +149,7 @@ static void clk_cgcr_disable(struct clk *clk)
144 __raw_writel(reg, clk->enable_reg); 149 __raw_writel(reg, clk->enable_reg);
145} 150}
146 151
147#define DEFINE_CLOCK(name, i, er, es, gr, sr) \ 152#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
148 static struct clk name = { \ 153 static struct clk name = { \
149 .id = i, \ 154 .id = i, \
150 .enable_reg = CRM_BASE + er, \ 155 .enable_reg = CRM_BASE + er, \
@@ -153,27 +158,30 @@ static void clk_cgcr_disable(struct clk *clk)
153 .set_rate = sr, \ 158 .set_rate = sr, \
154 .enable = clk_cgcr_enable, \ 159 .enable = clk_cgcr_enable, \
155 .disable = clk_cgcr_disable, \ 160 .disable = clk_cgcr_disable, \
161 .secondary = s, \
156 } 162 }
157 163
158DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_ipg, NULL); 164DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
159DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL); 165DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
160DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL); 166DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
161DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL); 167DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
162DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL); 168DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
163DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL); 169DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
164DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL); 170DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
165DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL); 171DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
166DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL); 172DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
167DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL); 173DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
168DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL); 174DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
169DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL); 175DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
170DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL); 176DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
171DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL); 177DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
172DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL); 178DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
173DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL); 179DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
174DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL); 180DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
175DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL); 181DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
176DEFINE_CLOCK(fec_clk, 0, CCM_CGCR0, 23, get_rate_ipg, NULL); 182DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
183DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
184DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
177 185
178#define _REGISTER_CLOCK(d, n, c) \ 186#define _REGISTER_CLOCK(d, n, c) \
179 { \ 187 { \
@@ -208,13 +216,21 @@ static struct clk_lookup lookups[] = {
208 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 216 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
209}; 217};
210 218
211int __init mx25_clocks_init(unsigned long fref) 219int __init mx25_clocks_init(void)
212{ 220{
213 int i; 221 int i;
214 222
215 for (i = 0; i < ARRAY_SIZE(lookups); i++) 223 for (i = 0; i < ARRAY_SIZE(lookups); i++)
216 clkdev_add(&lookups[i]); 224 clkdev_add(&lookups[i]);
217 225
226 /* Turn off all clocks except the ones we need to survive, namely:
227 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
228 * SCC
229 */
230 __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
231 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
232 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
233
218 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 234 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
219 235
220 return 0; 236 return 0;
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
index 921bc99ea231..6f06089246eb 100644
--- a/arch/arm/mach-mx25/mx25pdk.c
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -91,7 +91,7 @@ static void __init mx25pdk_init(void)
91 91
92static void __init mx25pdk_timer_init(void) 92static void __init mx25pdk_timer_init(void)
93{ 93{
94 mx25_clocks_init(26000000); 94 mx25_clocks_init();
95} 95}
96 96
97static struct sys_timer mx25pdk_timer = { 97static struct sys_timer mx25pdk_timer = {
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 3e7bafa2ddbb..938c549767dc 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -173,6 +173,7 @@ static void expio_unmask_irq(u32 irq)
173} 173}
174 174
175static struct irq_chip expio_irq_chip = { 175static struct irq_chip expio_irq_chip = {
176 .name = "EXPIO(CPLD)",
176 .ack = expio_ack_irq, 177 .ack = expio_ack_irq,
177 .mask = expio_mask_irq, 178 .mask = expio_mask_irq,
178 .unmask = expio_unmask_irq, 179 .unmask = expio_unmask_irq,
@@ -302,6 +303,7 @@ static struct regulator_init_data ldo1_data = {
302 .min_uV = 2800000, 303 .min_uV = 2800000,
303 .max_uV = 2800000, 304 .max_uV = 2800000,
304 .valid_modes_mask = REGULATOR_MODE_NORMAL, 305 .valid_modes_mask = REGULATOR_MODE_NORMAL,
306 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
305 .apply_uV = 1, 307 .apply_uV = 1,
306 }, 308 },
307}; 309};
@@ -322,6 +324,7 @@ static struct regulator_init_data ldo2_data = {
322 .min_uV = 3300000, 324 .min_uV = 3300000,
323 .max_uV = 3300000, 325 .max_uV = 3300000,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL, 326 .valid_modes_mask = REGULATOR_MODE_NORMAL,
327 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
325 .apply_uV = 1, 328 .apply_uV = 1,
326 }, 329 },
327 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), 330 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
@@ -459,6 +462,7 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
459 462
460static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { 463static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
461 .init = mx31_wm8350_init, 464 .init = mx31_wm8350_init,
465 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
462}; 466};
463#endif 467#endif
464 468
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 3f1334f62e7a..7027cdc1ba49 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -505,7 +505,7 @@ static void __init gpmc_mem_init(void)
505void __init gpmc_init(void) 505void __init gpmc_init(void)
506{ 506{
507 u32 l; 507 u32 l;
508 char *ck; 508 char *ck = NULL;
509 509
510 if (cpu_is_omap24xx()) { 510 if (cpu_is_omap24xx()) {
511 ck = "core_l3_ck"; 511 ck = "core_l3_ck";
@@ -521,6 +521,9 @@ void __init gpmc_init(void)
521 l = OMAP44XX_GPMC_BASE; 521 l = OMAP44XX_GPMC_BASE;
522 } 522 }
523 523
524 if (WARN_ON(!ck))
525 return;
526
524 gpmc_l3_clk = clk_get(NULL, ck); 527 gpmc_l3_clk = clk_get(NULL, ck);
525 if (IS_ERR(gpmc_l3_clk)) { 528 if (IS_ERR(gpmc_l3_clk)) {
526 printk(KERN_ERR "Could not get GPMC clock %s\n", ck); 529 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 27054025da2b..26aeef560aa3 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -194,7 +194,7 @@ void __init omap_init_irq(void)
194 int i; 194 int i;
195 195
196 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 196 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
197 unsigned long base; 197 unsigned long base = 0;
198 struct omap_irq_bank *bank = irq_banks + i; 198 struct omap_irq_bank *bank = irq_banks + i;
199 199
200 if (cpu_is_omap24xx()) 200 if (cpu_is_omap24xx())
@@ -202,6 +202,8 @@ void __init omap_init_irq(void)
202 else if (cpu_is_omap34xx()) 202 else if (cpu_is_omap34xx())
203 base = OMAP34XX_IC_BASE; 203 base = OMAP34XX_IC_BASE;
204 204
205 BUG_ON(!base);
206
205 /* Static mapping, never released */ 207 /* Static mapping, never released */
206 bank->base_reg = ioremap(base, SZ_4K); 208 bank->base_reg = ioremap(base, SZ_4K);
207 if (!bank->base_reg) { 209 if (!bank->base_reg) {
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 0c3c72d934bf..8afe9dd3f150 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -408,6 +408,7 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
408{ 408{
409 struct twl4030_hsmmc_info *c; 409 struct twl4030_hsmmc_info *c;
410 int nr_hsmmc = ARRAY_SIZE(hsmmc_data); 410 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
411 int i;
411 412
412 if (cpu_is_omap2430()) { 413 if (cpu_is_omap2430()) {
413 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 414 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
@@ -434,7 +435,7 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
434 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); 435 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
435 if (!mmc) { 436 if (!mmc) {
436 pr_err("Cannot allocate memory for mmc device!\n"); 437 pr_err("Cannot allocate memory for mmc device!\n");
437 return; 438 goto done;
438 } 439 }
439 440
440 if (c->name) 441 if (c->name)
@@ -532,6 +533,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
532 continue; 533 continue;
533 c->dev = mmc->dev; 534 c->dev = mmc->dev;
534 } 535 }
536
537done:
538 for (i = 0; i < nr_hsmmc; i++)
539 kfree(hsmmc_data[i]);
535} 540}
536 541
537#endif 542#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 3f59bd12cbbf..5fef73f4743d 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,7 +486,7 @@ int __init omap_mux_init_signal(char *muxname, int val)
486static inline void omap_mux_decode(struct seq_file *s, u16 val) 486static inline void omap_mux_decode(struct seq_file *s, u16 val)
487{ 487{
488 char *flags[OMAP_MUX_MAX_NR_FLAGS]; 488 char *flags[OMAP_MUX_MAX_NR_FLAGS];
489 char mode[14]; 489 char mode[sizeof("OMAP_MUX_MODE") + 1];
490 int i = -1; 490 int i = -1;
491 491
492 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7); 492 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
@@ -553,6 +553,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
553 if (!m0_name) 553 if (!m0_name)
554 continue; 554 continue;
555 555
556 /* REVISIT: Needs to be updated if mode0 names get longer */
556 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) { 557 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
557 if (m0_name[i] == '\0') { 558 if (m0_name[i] == '\0') {
558 m0_def[i] = m0_name[i]; 559 m0_def[i] = m0_name[i];
@@ -960,7 +961,12 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
960 while (superset->reg_offset != OMAP_MUX_TERMINATOR) { 961 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
961 struct omap_mux *entry; 962 struct omap_mux *entry;
962 963
963#ifndef CONFIG_OMAP_MUX 964#ifdef CONFIG_OMAP_MUX
965 if (!superset->muxnames || !superset->muxnames[0]) {
966 superset++;
967 continue;
968 }
969#else
964 /* Skip pins that are not muxed as GPIO by bootloader */ 970 /* Skip pins that are not muxed as GPIO by bootloader */
965 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { 971 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
966 superset++; 972 superset++;
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 68e0a595f9a1..07aa7b3c95f7 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -649,6 +649,53 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166, 649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650 "uart3_tx_irtx", NULL, NULL, NULL, 650 "uart3_tx_irtx", NULL, NULL, NULL,
651 "gpio_166", NULL, NULL, "safe_mode"), 651 "gpio_166", NULL, NULL, "safe_mode"),
652
653 /* Only on 3630, see omap36xx_cbp_subset for the signals */
654 _OMAP3_MUXENTRY(GPMC_A11, 0,
655 NULL, NULL, NULL, NULL,
656 NULL, NULL, NULL, NULL),
657 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
658 NULL, NULL, NULL, NULL,
659 NULL, NULL, NULL, NULL),
660 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL),
663 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
664 NULL, NULL, NULL, NULL,
665 NULL, NULL, NULL, NULL),
666 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
667 NULL, NULL, NULL, NULL,
668 NULL, NULL, NULL, NULL),
669 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
670 NULL, NULL, NULL, NULL,
671 NULL, NULL, NULL, NULL),
672 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL),
675 _OMAP3_MUXENTRY(GPMC_A11, 0,
676 NULL, NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL),
678 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
679 NULL, NULL, NULL, NULL,
680 NULL, NULL, NULL, NULL),
681 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
682 NULL, NULL, NULL, NULL,
683 NULL, NULL, NULL, NULL),
684 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL),
687 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL),
690 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
691 NULL, NULL, NULL, NULL,
692 NULL, NULL, NULL, NULL),
693 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
694 NULL, NULL, NULL, NULL,
695 NULL, NULL, NULL, NULL),
696 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
697 NULL, NULL, NULL, NULL,
698 NULL, NULL, NULL, NULL),
652 { .reg_offset = OMAP_MUX_TERMINATOR }, 699 { .reg_offset = OMAP_MUX_TERMINATOR },
653}; 700};
654 701
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 8c964bec8159..e10a02df6e1d 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -36,7 +36,13 @@
36#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 36#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
37#define UART_OMAP_WER 0x17 /* Wake-up enable register */ 37#define UART_OMAP_WER 0x17 /* Wake-up enable register */
38 38
39#define DEFAULT_TIMEOUT (5 * HZ) 39/*
40 * NOTE: By default the serial timeout is disabled as it causes lost characters
41 * over the serial ports. This means that the UART clocks will stay on until
42 * disabled via sysfs. This also causes that any deeper omap sleep states are
43 * blocked.
44 */
45#define DEFAULT_TIMEOUT 0
40 46
41struct omap_uart_state { 47struct omap_uart_state {
42 int num; 48 int num;
@@ -422,7 +428,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
422 uart->timeout = DEFAULT_TIMEOUT; 428 uart->timeout = DEFAULT_TIMEOUT;
423 setup_timer(&uart->timer, omap_uart_idle_timer, 429 setup_timer(&uart->timer, omap_uart_idle_timer,
424 (unsigned long) uart); 430 (unsigned long) uart);
425 mod_timer(&uart->timer, jiffies + uart->timeout); 431 if (uart->timeout)
432 mod_timer(&uart->timer, jiffies + uart->timeout);
426 omap_uart_smart_idle_enable(uart, 0); 433 omap_uart_smart_idle_enable(uart, 0);
427 434
428 if (cpu_is_omap34xx()) { 435 if (cpu_is_omap34xx()) {
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index a21a4b395f73..d94857eb0690 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -334,8 +334,8 @@ static void realview_pbx_reset(char mode)
334 * in the system FPGA 334 * in the system FPGA
335 */ 335 */
336 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); 336 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
337 __raw_writel(0x0000, reset_ctrl); 337 __raw_writel(0x00F0, reset_ctrl);
338 __raw_writel(0x0004, reset_ctrl); 338 __raw_writel(0x00F4, reset_ctrl);
339} 339}
340 340
341static void __init realview_pbx_init(void) 341static void __init realview_pbx_init(void)
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index b270d6228fe2..62820eda84d9 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -11,6 +11,7 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/moduleparam.h>
14#include <linux/compiler.h> 15#include <linux/compiler.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/errno.h> 17#include <linux/errno.h>
@@ -77,6 +78,8 @@ static unsigned long ai_dword;
77static unsigned long ai_multi; 78static unsigned long ai_multi;
78static int ai_usermode; 79static int ai_usermode;
79 80
81core_param(alignment, ai_usermode, int, 0600);
82
80#define UM_WARN (1 << 0) 83#define UM_WARN (1 << 0)
81#define UM_FIXUP (1 << 1) 84#define UM_FIXUP (1 << 1)
82#define UM_SIGNAL (1 << 2) 85#define UM_SIGNAL (1 << 2)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 3f9cd3d8f6d5..795dc615f43b 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
41ENTRY(cpu_arm7_data_abort) 41ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r0] @ read arm instruction 44 ldr r8, [r2] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write? 45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes. 46 orreq r1, r1, #1 << 11 @ yes.
47 and r7, r8, #15 << 24 47 and r7, r8, #15 << 24
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 6f21096086fd..b06954a84436 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -23,6 +23,7 @@
23#include <linux/err.h> 23#include <linux/err.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/debugfs.h>
26#include <mach/audmux.h> 27#include <mach/audmux.h>
27#include <mach/hardware.h> 28#include <mach/hardware.h>
28 29
@@ -32,6 +33,140 @@ static void __iomem *audmux_base;
32#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8) 33#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
33#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4) 34#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
34 35
36#ifdef CONFIG_DEBUG_FS
37static struct dentry *audmux_debugfs_root;
38
39static int audmux_open_file(struct inode *inode, struct file *file)
40{
41 file->private_data = inode->i_private;
42 return 0;
43}
44
45/* There is an annoying discontinuity in the SSI numbering with regard
46 * to the Linux number of the devices */
47static const char *audmux_port_string(int port)
48{
49 switch (port) {
50 case MX31_AUDMUX_PORT1_SSI0:
51 return "imx-ssi.0";
52 case MX31_AUDMUX_PORT2_SSI1:
53 return "imx-ssi.1";
54 case MX31_AUDMUX_PORT3_SSI_PINS_3:
55 return "SSI3";
56 case MX31_AUDMUX_PORT4_SSI_PINS_4:
57 return "SSI4";
58 case MX31_AUDMUX_PORT5_SSI_PINS_5:
59 return "SSI5";
60 case MX31_AUDMUX_PORT6_SSI_PINS_6:
61 return "SSI6";
62 default:
63 return "UNKNOWN";
64 }
65}
66
67static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
68 size_t count, loff_t *ppos)
69{
70 ssize_t ret;
71 char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
72 int port = (int)file->private_data;
73 u32 pdcr, ptcr;
74
75 if (!buf)
76 return -ENOMEM;
77
78 if (audmux_clk)
79 clk_enable(audmux_clk);
80
81 ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
82 pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
83
84 if (audmux_clk)
85 clk_disable(audmux_clk);
86
87 ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
88 pdcr, ptcr);
89
90 if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
91 ret += snprintf(buf + ret, PAGE_SIZE - ret,
92 "TxFS output from %s, ",
93 audmux_port_string((ptcr >> 27) & 0x7));
94 else
95 ret += snprintf(buf + ret, PAGE_SIZE - ret,
96 "TxFS input, ");
97
98 if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
99 ret += snprintf(buf + ret, PAGE_SIZE - ret,
100 "TxClk output from %s",
101 audmux_port_string((ptcr >> 22) & 0x7));
102 else
103 ret += snprintf(buf + ret, PAGE_SIZE - ret,
104 "TxClk input");
105
106 ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
107
108 if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
109 ret += snprintf(buf + ret, PAGE_SIZE - ret,
110 "Port is symmetric");
111 } else {
112 if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
113 ret += snprintf(buf + ret, PAGE_SIZE - ret,
114 "RxFS output from %s, ",
115 audmux_port_string((ptcr >> 17) & 0x7));
116 else
117 ret += snprintf(buf + ret, PAGE_SIZE - ret,
118 "RxFS input, ");
119
120 if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
121 ret += snprintf(buf + ret, PAGE_SIZE - ret,
122 "RxClk output from %s",
123 audmux_port_string((ptcr >> 12) & 0x7));
124 else
125 ret += snprintf(buf + ret, PAGE_SIZE - ret,
126 "RxClk input");
127 }
128
129 ret += snprintf(buf + ret, PAGE_SIZE - ret,
130 "\nData received from %s\n",
131 audmux_port_string((pdcr >> 13) & 0x7));
132
133 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
134
135 kfree(buf);
136
137 return ret;
138}
139
140static const struct file_operations audmux_debugfs_fops = {
141 .open = audmux_open_file,
142 .read = audmux_read_file,
143};
144
145static void audmux_debugfs_init(void)
146{
147 int i;
148 char buf[20];
149
150 audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
151 if (!audmux_debugfs_root) {
152 pr_warning("Failed to create AUDMUX debugfs root\n");
153 return;
154 }
155
156 for (i = 1; i < 8; i++) {
157 snprintf(buf, sizeof(buf), "ssi%d", i);
158 if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
159 (void *)i, &audmux_debugfs_fops))
160 pr_warning("Failed to create AUDMUX port %d debugfs file\n",
161 i);
162 }
163}
164#else
165static inline void audmux_debugfs_init(void)
166{
167}
168#endif
169
35int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, 170int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
36 unsigned int pdcr) 171 unsigned int pdcr)
37{ 172{
@@ -68,6 +203,8 @@ static int mxc_audmux_v2_init(void)
68 if (cpu_is_mx31() || cpu_is_mx35()) 203 if (cpu_is_mx31() || cpu_is_mx35())
69 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); 204 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
70 205
206 audmux_debugfs_init();
207
71 return 0; 208 return 0;
72} 209}
73 210
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 0184b638c268..2b2da0367578 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -25,7 +25,7 @@
25 25
26#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
27 27
28enum mx31lilly_boards { 28enum mx31lite_boards {
29 MX31LITE_NOBOARD = 0, 29 MX31LITE_NOBOARD = 0,
30 MX31LITE_DB = 1, 30 MX31LITE_DB = 1,
31}; 31};
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 286cb9b0a25b..4bf1068ffad9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,7 +32,7 @@ extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
33extern int mx1_clocks_init(unsigned long fref); 33extern int mx1_clocks_init(unsigned long fref);
34extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 34extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
35extern int mx25_clocks_init(unsigned long fref); 35extern int mx25_clocks_init(void);
36extern int mx27_clocks_init(unsigned long fref); 36extern int mx27_clocks_init(unsigned long fref);
37extern int mx31_clocks_init(unsigned long fref); 37extern int mx31_clocks_init(unsigned long fref);
38extern int mx35_clocks_init(void); 38extern int mx35_clocks_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 00b0ac1db225..c88d40795f7a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -671,7 +671,7 @@
671#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) 671#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
672 672
673#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) 673#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
674#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL) 674#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
675#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) 675#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
676 676
677#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) 677#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ead9d592168d..0cb347645db4 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -37,7 +37,12 @@
37 * within sensible limits. 37 * within sensible limits.
38 */ 38 */
39#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) 39#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
40
41#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
42#define MXC_BOARD_IRQS 80
43#else
40#define MXC_BOARD_IRQS 16 44#define MXC_BOARD_IRQS 16
45#endif
41 46
42#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) 47#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
43 48
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index d9f8c844c385..4becbdd1935c 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -391,7 +391,7 @@ static struct dentry *clk_debugfs_root;
391static int clk_debugfs_register_one(struct clk *c) 391static int clk_debugfs_register_one(struct clk *c)
392{ 392{
393 int err; 393 int err;
394 struct dentry *d, *child; 394 struct dentry *d, *child, *child_tmp;
395 struct clk *pa = c->parent; 395 struct clk *pa = c->parent;
396 char s[255]; 396 char s[255];
397 char *p = s; 397 char *p = s;
@@ -423,7 +423,7 @@ static int clk_debugfs_register_one(struct clk *c)
423 423
424err_out: 424err_out:
425 d = c->dent; 425 d = c->dent;
426 list_for_each_entry(child, &d->d_subdirs, d_u.d_child) 426 list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
427 debugfs_remove(child); 427 debugfs_remove(child);
428 debugfs_remove(c->dent); 428 debugfs_remove(c->dent);
429 return err; 429 return err;
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index d17620c50c28..d2422c766cca 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -750,6 +750,7 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
750} 750}
751#endif 751#endif
752 752
753#ifdef CONFIG_ARCH_OMAP1
753/* 754/*
754 * This only applies to chips that can't do both rising and falling edge 755 * This only applies to chips that can't do both rising and falling edge
755 * detection at once. For all other chips, this function is a noop. 756 * detection at once. For all other chips, this function is a noop.
@@ -760,11 +761,9 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
760 u32 l = 0; 761 u32 l = 0;
761 762
762 switch (bank->method) { 763 switch (bank->method) {
763#ifdef CONFIG_ARCH_OMAP1
764 case METHOD_MPUIO: 764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_INT_EDGE; 765 reg += OMAP_MPUIO_GPIO_INT_EDGE;
766 break; 766 break;
767#endif
768#ifdef CONFIG_ARCH_OMAP15XX 767#ifdef CONFIG_ARCH_OMAP15XX
769 case METHOD_GPIO_1510: 768 case METHOD_GPIO_1510:
770 reg += OMAP1510_GPIO_INT_CONTROL; 769 reg += OMAP1510_GPIO_INT_CONTROL;
@@ -787,6 +786,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
787 786
788 __raw_writel(l, reg); 787 __raw_writel(l, reg);
789} 788}
789#endif
790 790
791static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 791static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
792{ 792{
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 1e5648d3e3d8..2ed72013c2e2 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -89,16 +89,6 @@
89#define USE_WAKEUP_LAT 0 89#define USE_WAKEUP_LAT 0
90#define IGNORE_WAKEUP_LAT 1 90#define IGNORE_WAKEUP_LAT 1
91 91
92/* XXX this should be moved into a separate file */
93#if defined(CONFIG_ARCH_OMAP2420)
94# define OMAP_32KSYNCT_BASE 0x48004000
95#elif defined(CONFIG_ARCH_OMAP2430)
96# define OMAP_32KSYNCT_BASE 0x49020000
97#elif defined(CONFIG_ARCH_OMAP3430)
98# define OMAP_32KSYNCT_BASE 0x48320000
99#else
100# error Unknown OMAP device
101#endif
102 92
103/* Private functions */ 93/* Private functions */
104 94
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 5a79fc6ee818..31c2f4c30a95 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Thu Jan 28 22:15:54 2010 15# Last update: Sat Feb 20 14:16:15 2010
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -2257,7 +2257,7 @@ oratisalog MACH_ORATISALOG ORATISALOG 2268
2257oratismadi MACH_ORATISMADI ORATISMADI 2269 2257oratismadi MACH_ORATISMADI ORATISMADI 2269
2258oratisot16 MACH_ORATISOT16 ORATISOT16 2270 2258oratisot16 MACH_ORATISOT16 ORATISOT16 2270
2259oratisdesk MACH_ORATISDESK ORATISDESK 2271 2259oratisdesk MACH_ORATISDESK ORATISDESK 2271
2260v2_ca9 MACH_V2P_CA9 V2P_CA9 2272 2260vexpress MACH_VEXPRESS VEXPRESS 2272
2261sintexo MACH_SINTEXO SINTEXO 2273 2261sintexo MACH_SINTEXO SINTEXO 2273
2262cm3389 MACH_CM3389 CM3389 2274 2262cm3389 MACH_CM3389 CM3389 2274
2263omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 2263omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275
@@ -2636,3 +2636,45 @@ hw90240 MACH_HW90240 HW90240 2648
2636dm365_leopard MACH_DM365_LEOPARD DM365_LEOPARD 2649 2636dm365_leopard MACH_DM365_LEOPARD DM365_LEOPARD 2649
2637mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650 2637mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650
2638scat110 MACH_SCAT110 SCAT110 2651 2638scat110 MACH_SCAT110 SCAT110 2651
2639acer_a1 MACH_ACER_A1 ACER_A1 2652
2640cmcontrol MACH_CMCONTROL CMCONTROL 2653
2641pelco_lamar MACH_PELCO_LAMAR PELCO_LAMAR 2654
2642rfp43 MACH_RFP43 RFP43 2655
2643sk86r0301 MACH_SK86R0301 SK86R0301 2656
2644ctpxa MACH_CTPXA CTPXA 2657
2645epb_arm9_a MACH_EPB_ARM9_A EPB_ARM9_A 2658
2646guruplug MACH_GURUPLUG GURUPLUG 2659
2647spear310 MACH_SPEAR310 SPEAR310 2660
2648spear320 MACH_SPEAR320 SPEAR320 2661
2649robotx MACH_ROBOTX ROBOTX 2662
2650lsxhl MACH_LSXHL LSXHL 2663
2651smartlite MACH_SMARTLITE SMARTLITE 2664
2652cws2 MACH_CWS2 CWS2 2665
2653m619 MACH_M619 M619 2666
2654smartview MACH_SMARTVIEW SMARTVIEW 2667
2655lsa_salsa MACH_LSA_SALSA LSA_SALSA 2668
2656kizbox MACH_KIZBOX KIZBOX 2669
2657htccharmer MACH_HTCCHARMER HTCCHARMER 2670
2658guf_neso_lt MACH_GUF_NESO_LT GUF_NESO_LT 2671
2659pm9g45 MACH_PM9G45 PM9G45 2672
2660htcpanther MACH_HTCPANTHER HTCPANTHER 2673
2661htcpanther_cdma MACH_HTCPANTHER_CDMA HTCPANTHER_CDMA 2674
2662reb01 MACH_REB01 REB01 2675
2663aquila MACH_AQUILA AQUILA 2676
2664spark_sls_hw2 MACH_SPARK_SLS_HW2 SPARK_SLS_HW2 2677
2665sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
2666surf7x30 MACH_SURF7X30 SURF7X30 2679
2667micro2440 MACH_MICRO2440 MICRO2440 2680
2668am2440 MACH_AM2440 AM2440 2681
2669tq2440 MACH_TQ2440 TQ2440 2682
2670lpc2478oem MACH_LPC2478OEM LPC2478OEM 2683
2671ak880x MACH_AK880X AK880X 2684
2672cobra3530 MACH_COBRA3530 COBRA3530 2685
2673pmppb MACH_PMPPB PMPPB 2686
2674u6715 MACH_U6715 U6715 2687
2675axar1500_sender MACH_AXAR1500_SENDER AXAR1500_SENDER 2688
2676g30_dvb MACH_G30_DVB G30_DVB 2689
2677vc088x MACH_VC088X VC088X 2690
2678mioa702 MACH_MIOA702 MIOA702 2691
2679hpmin MACH_HPMIN HPMIN 2692
2680ak880xak MACH_AK880XAK AK880XAK 2693
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index f60a5400a25b..a63c4be99b36 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -197,10 +197,13 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
197 } 197 }
198 198
199 /* 199 /*
200 * Update the FPSCR with the additional exception flags. 200 * If any of the status flags are set, update the FPSCR.
201 * Comparison instructions always return at least one of 201 * Comparison instructions always return at least one of
202 * these flags set. 202 * these flags set.
203 */ 203 */
204 if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
205 fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
206
204 fpscr |= exceptions; 207 fpscr |= exceptions;
205 208
206 fmxr(FPSCR, fpscr); 209 fmxr(FPSCR, fpscr);
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 1aa1ea5e9212..b13d1879e51b 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1325,7 +1325,7 @@ struct platform_device *__init
1325at32_add_device_mci(unsigned int id, struct mci_platform_data *data) 1325at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1326{ 1326{
1327 struct platform_device *pdev; 1327 struct platform_device *pdev;
1328 struct mci_dma_slave *slave; 1328 struct mci_dma_data *slave;
1329 u32 pioa_mask; 1329 u32 pioa_mask;
1330 u32 piob_mask; 1330 u32 piob_mask;
1331 1331
@@ -1344,7 +1344,9 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1344 ARRAY_SIZE(atmel_mci0_resource))) 1344 ARRAY_SIZE(atmel_mci0_resource)))
1345 goto fail; 1345 goto fail;
1346 1346
1347 slave = kzalloc(sizeof(struct mci_dma_slave), GFP_KERNEL); 1347 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1348 if (!slave)
1349 goto fail;
1348 1350
1349 slave->sdata.dma_dev = &dw_dmac0_device.dev; 1351 slave->sdata.dma_dev = &dw_dmac0_device.dev;
1350 slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT; 1352 slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
@@ -1357,7 +1359,7 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1357 1359
1358 if (platform_device_add_data(pdev, data, 1360 if (platform_device_add_data(pdev, data,
1359 sizeof(struct mci_platform_data))) 1361 sizeof(struct mci_platform_data)))
1360 goto fail; 1362 goto fail_free;
1361 1363
1362 /* CLK line is common to both slots */ 1364 /* CLK line is common to both slots */
1363 pioa_mask = 1 << 10; 1365 pioa_mask = 1 << 10;
@@ -1381,7 +1383,7 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1381 /* Slot is unused */ 1383 /* Slot is unused */
1382 break; 1384 break;
1383 default: 1385 default:
1384 goto fail; 1386 goto fail_free;
1385 } 1387 }
1386 1388
1387 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0); 1389 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
@@ -1408,7 +1410,7 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1408 break; 1410 break;
1409 default: 1411 default:
1410 if (!data->slot[0].bus_width) 1412 if (!data->slot[0].bus_width)
1411 goto fail; 1413 goto fail_free;
1412 1414
1413 data->slot[1].bus_width = 0; 1415 data->slot[1].bus_width = 0;
1414 break; 1416 break;
@@ -1419,9 +1421,10 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1419 platform_device_add(pdev); 1421 platform_device_add(pdev);
1420 return pdev; 1422 return pdev;
1421 1423
1424fail_free:
1425 kfree(slave);
1422fail: 1426fail:
1423 data->dma_slave = NULL; 1427 data->dma_slave = NULL;
1424 kfree(slave);
1425 platform_device_put(pdev); 1428 platform_device_put(pdev);
1426 return NULL; 1429 return NULL;
1427} 1430}
diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
index 7ae58892ba8d..e97b255d97bc 100644
--- a/arch/ia64/include/asm/acpi.h
+++ b/arch/ia64/include/asm/acpi.h
@@ -94,6 +94,7 @@ ia64_acpi_release_global_lock (unsigned int *lock)
94#define acpi_noirq 0 /* ACPI always enabled on IA64 */ 94#define acpi_noirq 0 /* ACPI always enabled on IA64 */
95#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */ 95#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
96#define acpi_strict 1 /* no ACPI spec workarounds on IA64 */ 96#define acpi_strict 1 /* no ACPI spec workarounds on IA64 */
97#define acpi_ht 0 /* no HT-only mode on IA64 */
97#endif 98#endif
98#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ 99#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
99static inline void disable_acpi(void) { } 100static inline void disable_acpi(void) { }
diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h
index e14108b19c09..4c41656ede87 100644
--- a/arch/ia64/include/asm/elf.h
+++ b/arch/ia64/include/asm/elf.h
@@ -201,7 +201,9 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
201 relevant until we have real hardware to play with... */ 201 relevant until we have real hardware to play with... */
202#define ELF_PLATFORM NULL 202#define ELF_PLATFORM NULL
203 203
204#define SET_PERSONALITY(ex) set_personality(PER_LINUX) 204#define SET_PERSONALITY(ex) \
205 set_personality((current->personality & ~PER_MASK) | PER_LINUX)
206
205#define elf_read_implies_exec(ex, executable_stack) \ 207#define elf_read_implies_exec(ex, executable_stack) \
206 ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0) 208 ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0)
207 209
diff --git a/arch/ia64/kernel/kprobes.c b/arch/ia64/kernel/kprobes.c
index 9adac441ac9b..7026b29e277a 100644
--- a/arch/ia64/kernel/kprobes.c
+++ b/arch/ia64/kernel/kprobes.c
@@ -870,7 +870,7 @@ static int __kprobes pre_kprobes_handler(struct die_args *args)
870 return 1; 870 return 1;
871 871
872ss_probe: 872ss_probe:
873#if !defined(CONFIG_PREEMPT) || defined(CONFIG_FREEZER) 873#if !defined(CONFIG_PREEMPT)
874 if (p->ainsn.inst_flag == INST_FLAG_BOOSTABLE && !p->post_handler) { 874 if (p->ainsn.inst_flag == INST_FLAG_BOOSTABLE && !p->post_handler) {
875 /* Boost up -- we can execute copied instructions directly */ 875 /* Boost up -- we can execute copied instructions directly */
876 ia64_psr(regs)->ri = p->ainsn.slot; 876 ia64_psr(regs)->ri = p->ainsn.slot;
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index ece1bf994499..e456f062f241 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -71,7 +71,7 @@ EXPORT_SYMBOL(sn_rtc_cycles_per_second);
71DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info); 71DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
72EXPORT_PER_CPU_SYMBOL(__sn_hub_info); 72EXPORT_PER_CPU_SYMBOL(__sn_hub_info);
73 73
74DEFINE_PER_CPU(short [MAX_COMPACT_NODES], __sn_cnodeid_to_nasid); 74DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
75EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid); 75EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
76 76
77DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda); 77DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig
index bb7c374713ad..6fced1fe3bf0 100644
--- a/arch/microblaze/configs/mmu_defconfig
+++ b/arch/microblaze/configs/mmu_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31 3# Linux kernel version: 2.6.33-rc6
4# Thu Sep 24 10:28:50 2009 4# Wed Feb 3 10:02:59 2010
5# 5#
6CONFIG_MICROBLAZE=y 6CONFIG_MICROBLAZE=y
7# CONFIG_SWAP is not set 7# CONFIG_SWAP is not set
@@ -19,8 +19,12 @@ CONFIG_GENERIC_CLOCKEVENTS=y
19CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 19CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
20CONFIG_GENERIC_GPIO=y 20CONFIG_GENERIC_GPIO=y
21CONFIG_GENERIC_CSUM=y 21CONFIG_GENERIC_CSUM=y
22CONFIG_STACKTRACE_SUPPORT=y
23CONFIG_LOCKDEP_SUPPORT=y
24CONFIG_HAVE_LATENCYTOP_SUPPORT=y
22# CONFIG_PCI is not set 25# CONFIG_PCI is not set
23CONFIG_NO_DMA=y 26CONFIG_NO_DMA=y
27CONFIG_DTC=y
24CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
25CONFIG_CONSTRUCTORS=y 29CONFIG_CONSTRUCTORS=y
26 30
@@ -44,6 +48,7 @@ CONFIG_SYSVIPC_SYSCTL=y
44# 48#
45CONFIG_TREE_RCU=y 49CONFIG_TREE_RCU=y
46# CONFIG_TREE_PREEMPT_RCU is not set 50# CONFIG_TREE_PREEMPT_RCU is not set
51# CONFIG_TINY_RCU is not set
47# CONFIG_RCU_TRACE is not set 52# CONFIG_RCU_TRACE is not set
48CONFIG_RCU_FANOUT=32 53CONFIG_RCU_FANOUT=32
49# CONFIG_RCU_FANOUT_EXACT is not set 54# CONFIG_RCU_FANOUT_EXACT is not set
@@ -64,10 +69,12 @@ CONFIG_INITRAMFS_ROOT_GID=0
64CONFIG_RD_GZIP=y 69CONFIG_RD_GZIP=y
65# CONFIG_RD_BZIP2 is not set 70# CONFIG_RD_BZIP2 is not set
66# CONFIG_RD_LZMA is not set 71# CONFIG_RD_LZMA is not set
72# CONFIG_RD_LZO is not set
67# CONFIG_INITRAMFS_COMPRESSION_NONE is not set 73# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
68CONFIG_INITRAMFS_COMPRESSION_GZIP=y 74CONFIG_INITRAMFS_COMPRESSION_GZIP=y
69# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set 75# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
70# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set 76# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
77# CONFIG_INITRAMFS_COMPRESSION_LZO is not set
71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 78# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
72CONFIG_SYSCTL=y 79CONFIG_SYSCTL=y
73CONFIG_ANON_INODES=y 80CONFIG_ANON_INODES=y
@@ -90,21 +97,20 @@ CONFIG_EVENTFD=y
90CONFIG_AIO=y 97CONFIG_AIO=y
91 98
92# 99#
93# Performance Counters 100# Kernel Performance Events And Counters
94# 101#
95CONFIG_VM_EVENT_COUNTERS=y 102CONFIG_VM_EVENT_COUNTERS=y
96# CONFIG_STRIP_ASM_SYMS is not set
97CONFIG_COMPAT_BRK=y 103CONFIG_COMPAT_BRK=y
98CONFIG_SLAB=y 104CONFIG_SLAB=y
99# CONFIG_SLUB is not set 105# CONFIG_SLUB is not set
100# CONFIG_SLOB is not set 106# CONFIG_SLOB is not set
101# CONFIG_PROFILING is not set 107# CONFIG_PROFILING is not set
102# CONFIG_MARKERS is not set 108CONFIG_HAVE_OPROFILE=y
103 109
104# 110#
105# GCOV-based kernel profiling 111# GCOV-based kernel profiling
106# 112#
107# CONFIG_SLOW_WORK is not set 113CONFIG_SLOW_WORK=y
108# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 114# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
109CONFIG_SLABINFO=y 115CONFIG_SLABINFO=y
110CONFIG_BASE_SMALL=1 116CONFIG_BASE_SMALL=1
@@ -123,14 +129,41 @@ CONFIG_LBDAF=y
123# IO Schedulers 129# IO Schedulers
124# 130#
125CONFIG_IOSCHED_NOOP=y 131CONFIG_IOSCHED_NOOP=y
126CONFIG_IOSCHED_AS=y
127CONFIG_IOSCHED_DEADLINE=y 132CONFIG_IOSCHED_DEADLINE=y
128CONFIG_IOSCHED_CFQ=y 133CONFIG_IOSCHED_CFQ=y
129# CONFIG_DEFAULT_AS is not set
130# CONFIG_DEFAULT_DEADLINE is not set 134# CONFIG_DEFAULT_DEADLINE is not set
131CONFIG_DEFAULT_CFQ=y 135CONFIG_DEFAULT_CFQ=y
132# CONFIG_DEFAULT_NOOP is not set 136# CONFIG_DEFAULT_NOOP is not set
133CONFIG_DEFAULT_IOSCHED="cfq" 137CONFIG_DEFAULT_IOSCHED="cfq"
138# CONFIG_INLINE_SPIN_TRYLOCK is not set
139# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
140# CONFIG_INLINE_SPIN_LOCK is not set
141# CONFIG_INLINE_SPIN_LOCK_BH is not set
142# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
143# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
144# CONFIG_INLINE_SPIN_UNLOCK is not set
145# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
146# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
147# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
148# CONFIG_INLINE_READ_TRYLOCK is not set
149# CONFIG_INLINE_READ_LOCK is not set
150# CONFIG_INLINE_READ_LOCK_BH is not set
151# CONFIG_INLINE_READ_LOCK_IRQ is not set
152# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
153# CONFIG_INLINE_READ_UNLOCK is not set
154# CONFIG_INLINE_READ_UNLOCK_BH is not set
155# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
156# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
157# CONFIG_INLINE_WRITE_TRYLOCK is not set
158# CONFIG_INLINE_WRITE_LOCK is not set
159# CONFIG_INLINE_WRITE_LOCK_BH is not set
160# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
161# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
162# CONFIG_INLINE_WRITE_UNLOCK is not set
163# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
164# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
165# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
166# CONFIG_MUTEX_SPIN_ON_OWNER is not set
134# CONFIG_FREEZER is not set 167# CONFIG_FREEZER is not set
135 168
136# 169#
@@ -139,11 +172,6 @@ CONFIG_DEFAULT_IOSCHED="cfq"
139CONFIG_PLATFORM_GENERIC=y 172CONFIG_PLATFORM_GENERIC=y
140CONFIG_OPT_LIB_FUNCTION=y 173CONFIG_OPT_LIB_FUNCTION=y
141CONFIG_OPT_LIB_ASM=y 174CONFIG_OPT_LIB_ASM=y
142CONFIG_ALLOW_EDIT_AUTO=y
143
144#
145# Automatic platform settings from Kconfig.auto
146#
147 175
148# 176#
149# Definitions for MICROBLAZE0 177# Definitions for MICROBLAZE0
@@ -203,12 +231,11 @@ CONFIG_FLATMEM_MANUAL=y
203CONFIG_FLATMEM=y 231CONFIG_FLATMEM=y
204CONFIG_FLAT_NODE_MEM_MAP=y 232CONFIG_FLAT_NODE_MEM_MAP=y
205CONFIG_PAGEFLAGS_EXTENDED=y 233CONFIG_PAGEFLAGS_EXTENDED=y
206CONFIG_SPLIT_PTLOCK_CPUS=4 234CONFIG_SPLIT_PTLOCK_CPUS=999999
207# CONFIG_PHYS_ADDR_T_64BIT is not set 235# CONFIG_PHYS_ADDR_T_64BIT is not set
208CONFIG_ZONE_DMA_FLAG=0 236CONFIG_ZONE_DMA_FLAG=0
209CONFIG_VIRT_TO_BUS=y 237CONFIG_VIRT_TO_BUS=y
210CONFIG_HAVE_MLOCK=y 238# CONFIG_KSM is not set
211CONFIG_HAVE_MLOCKED_PAGE_BIT=y
212CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 239CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
213 240
214# 241#
@@ -289,7 +316,13 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
289# CONFIG_IRDA is not set 316# CONFIG_IRDA is not set
290# CONFIG_BT is not set 317# CONFIG_BT is not set
291# CONFIG_AF_RXRPC is not set 318# CONFIG_AF_RXRPC is not set
292# CONFIG_WIRELESS is not set 319CONFIG_WIRELESS=y
320# CONFIG_CFG80211 is not set
321# CONFIG_LIB80211 is not set
322
323#
324# CFG80211 needs to be enabled for MAC80211
325#
293# CONFIG_WIMAX is not set 326# CONFIG_WIMAX is not set
294# CONFIG_RFKILL is not set 327# CONFIG_RFKILL is not set
295# CONFIG_NET_9P is not set 328# CONFIG_NET_9P is not set
@@ -313,6 +346,10 @@ CONFIG_OF_DEVICE=y
313CONFIG_BLK_DEV=y 346CONFIG_BLK_DEV=y
314# CONFIG_BLK_DEV_COW_COMMON is not set 347# CONFIG_BLK_DEV_COW_COMMON is not set
315# CONFIG_BLK_DEV_LOOP is not set 348# CONFIG_BLK_DEV_LOOP is not set
349
350#
351# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
352#
316# CONFIG_BLK_DEV_NBD is not set 353# CONFIG_BLK_DEV_NBD is not set
317CONFIG_BLK_DEV_RAM=y 354CONFIG_BLK_DEV_RAM=y
318CONFIG_BLK_DEV_RAM_COUNT=16 355CONFIG_BLK_DEV_RAM_COUNT=16
@@ -349,7 +386,6 @@ CONFIG_NETDEVICES=y
349# CONFIG_PHYLIB is not set 386# CONFIG_PHYLIB is not set
350CONFIG_NET_ETHERNET=y 387CONFIG_NET_ETHERNET=y
351# CONFIG_MII is not set 388# CONFIG_MII is not set
352# CONFIG_ETHOC is not set
353# CONFIG_DNET is not set 389# CONFIG_DNET is not set
354# CONFIG_IBM_NEW_EMAC_ZMII is not set 390# CONFIG_IBM_NEW_EMAC_ZMII is not set
355# CONFIG_IBM_NEW_EMAC_RGMII is not set 391# CONFIG_IBM_NEW_EMAC_RGMII is not set
@@ -359,12 +395,12 @@ CONFIG_NET_ETHERNET=y
359# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set 395# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
360# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set 396# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
361# CONFIG_KS8842 is not set 397# CONFIG_KS8842 is not set
398# CONFIG_KS8851_MLL is not set
362CONFIG_XILINX_EMACLITE=y 399CONFIG_XILINX_EMACLITE=y
363CONFIG_NETDEV_1000=y 400CONFIG_NETDEV_1000=y
364CONFIG_NETDEV_10000=y 401CONFIG_NETDEV_10000=y
365CONFIG_WLAN=y 402CONFIG_WLAN=y
366# CONFIG_WLAN_PRE80211 is not set 403# CONFIG_HOSTAP is not set
367# CONFIG_WLAN_80211 is not set
368 404
369# 405#
370# Enable WiMAX (Networking options) to see the WiMAX drivers 406# Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -408,6 +444,7 @@ CONFIG_SERIAL_UARTLITE=y
408CONFIG_SERIAL_UARTLITE_CONSOLE=y 444CONFIG_SERIAL_UARTLITE_CONSOLE=y
409CONFIG_SERIAL_CORE=y 445CONFIG_SERIAL_CORE=y
410CONFIG_SERIAL_CORE_CONSOLE=y 446CONFIG_SERIAL_CORE_CONSOLE=y
447# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
411CONFIG_UNIX98_PTYS=y 448CONFIG_UNIX98_PTYS=y
412# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 449# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
413CONFIG_LEGACY_PTYS=y 450CONFIG_LEGACY_PTYS=y
@@ -433,7 +470,6 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
433# CONFIG_POWER_SUPPLY is not set 470# CONFIG_POWER_SUPPLY is not set
434# CONFIG_HWMON is not set 471# CONFIG_HWMON is not set
435# CONFIG_THERMAL is not set 472# CONFIG_THERMAL is not set
436# CONFIG_THERMAL_HWMON is not set
437# CONFIG_WATCHDOG is not set 473# CONFIG_WATCHDOG is not set
438 474
439# 475#
@@ -526,8 +562,6 @@ CONFIG_PROC_FS=y
526CONFIG_PROC_SYSCTL=y 562CONFIG_PROC_SYSCTL=y
527CONFIG_PROC_PAGE_MONITOR=y 563CONFIG_PROC_PAGE_MONITOR=y
528CONFIG_SYSFS=y 564CONFIG_SYSFS=y
529CONFIG_TMPFS=y
530# CONFIG_TMPFS_POSIX_ACL is not set
531# CONFIG_HUGETLB_PAGE is not set 565# CONFIG_HUGETLB_PAGE is not set
532# CONFIG_CONFIGFS_FS is not set 566# CONFIG_CONFIGFS_FS is not set
533CONFIG_MISC_FILESYSTEMS=y 567CONFIG_MISC_FILESYSTEMS=y
@@ -638,11 +672,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
638# 672#
639# Kernel hacking 673# Kernel hacking
640# 674#
675CONFIG_TRACE_IRQFLAGS_SUPPORT=y
641# CONFIG_PRINTK_TIME is not set 676# CONFIG_PRINTK_TIME is not set
642CONFIG_ENABLE_WARN_DEPRECATED=y 677CONFIG_ENABLE_WARN_DEPRECATED=y
643CONFIG_ENABLE_MUST_CHECK=y 678CONFIG_ENABLE_MUST_CHECK=y
644CONFIG_FRAME_WARN=1024 679CONFIG_FRAME_WARN=1024
645# CONFIG_MAGIC_SYSRQ is not set 680# CONFIG_MAGIC_SYSRQ is not set
681# CONFIG_STRIP_ASM_SYMS is not set
646# CONFIG_UNUSED_SYMBOLS is not set 682# CONFIG_UNUSED_SYMBOLS is not set
647# CONFIG_DEBUG_FS is not set 683# CONFIG_DEBUG_FS is not set
648# CONFIG_HEADERS_CHECK is not set 684# CONFIG_HEADERS_CHECK is not set
@@ -662,6 +698,9 @@ CONFIG_DEBUG_SLAB=y
662# CONFIG_DEBUG_SLAB_LEAK is not set 698# CONFIG_DEBUG_SLAB_LEAK is not set
663CONFIG_DEBUG_SPINLOCK=y 699CONFIG_DEBUG_SPINLOCK=y
664# CONFIG_DEBUG_MUTEXES is not set 700# CONFIG_DEBUG_MUTEXES is not set
701# CONFIG_DEBUG_LOCK_ALLOC is not set
702# CONFIG_PROVE_LOCKING is not set
703# CONFIG_LOCK_STAT is not set
665# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 704# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
666# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 705# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
667# CONFIG_DEBUG_KOBJECT is not set 706# CONFIG_DEBUG_KOBJECT is not set
@@ -680,10 +719,29 @@ CONFIG_DEBUG_INFO=y
680# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 719# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
681# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 720# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
682# CONFIG_FAULT_INJECTION is not set 721# CONFIG_FAULT_INJECTION is not set
722# CONFIG_LATENCYTOP is not set
683# CONFIG_SYSCTL_SYSCALL_CHECK is not set 723# CONFIG_SYSCTL_SYSCALL_CHECK is not set
684# CONFIG_PAGE_POISONING is not set 724# CONFIG_PAGE_POISONING is not set
725CONFIG_HAVE_FUNCTION_TRACER=y
726CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
727CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
728CONFIG_HAVE_DYNAMIC_FTRACE=y
729CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
730CONFIG_TRACING_SUPPORT=y
731CONFIG_FTRACE=y
732# CONFIG_FUNCTION_TRACER is not set
733# CONFIG_IRQSOFF_TRACER is not set
734# CONFIG_SCHED_TRACER is not set
735# CONFIG_ENABLE_DEFAULT_TRACERS is not set
736# CONFIG_BOOT_TRACER is not set
737CONFIG_BRANCH_PROFILE_NONE=y
738# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
739# CONFIG_PROFILE_ALL_BRANCHES is not set
740# CONFIG_STACK_TRACER is not set
741# CONFIG_KMEMTRACE is not set
742# CONFIG_WORKQUEUE_TRACER is not set
743# CONFIG_BLK_DEV_IO_TRACE is not set
685# CONFIG_SAMPLES is not set 744# CONFIG_SAMPLES is not set
686# CONFIG_KMEMCHECK is not set
687CONFIG_EARLY_PRINTK=y 745CONFIG_EARLY_PRINTK=y
688# CONFIG_HEART_BEAT is not set 746# CONFIG_HEART_BEAT is not set
689CONFIG_DEBUG_BOOTMEM=y 747CONFIG_DEBUG_BOOTMEM=y
@@ -694,7 +752,11 @@ CONFIG_DEBUG_BOOTMEM=y
694# CONFIG_KEYS is not set 752# CONFIG_KEYS is not set
695# CONFIG_SECURITY is not set 753# CONFIG_SECURITY is not set
696# CONFIG_SECURITYFS is not set 754# CONFIG_SECURITYFS is not set
697# CONFIG_SECURITY_FILE_CAPABILITIES is not set 755# CONFIG_DEFAULT_SECURITY_SELINUX is not set
756# CONFIG_DEFAULT_SECURITY_SMACK is not set
757# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
758CONFIG_DEFAULT_SECURITY_DAC=y
759CONFIG_DEFAULT_SECURITY=""
698CONFIG_CRYPTO=y 760CONFIG_CRYPTO=y
699 761
700# 762#
diff --git a/arch/microblaze/configs/nommu_defconfig b/arch/microblaze/configs/nommu_defconfig
index adb839bab704..ce2da535246a 100644
--- a/arch/microblaze/configs/nommu_defconfig
+++ b/arch/microblaze/configs/nommu_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31 3# Linux kernel version: 2.6.33-rc6
4# Thu Sep 24 10:29:43 2009 4# Wed Feb 3 10:03:21 2010
5# 5#
6CONFIG_MICROBLAZE=y 6CONFIG_MICROBLAZE=y
7# CONFIG_SWAP is not set 7# CONFIG_SWAP is not set
@@ -19,8 +19,12 @@ CONFIG_GENERIC_CLOCKEVENTS=y
19CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 19CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
20CONFIG_GENERIC_GPIO=y 20CONFIG_GENERIC_GPIO=y
21CONFIG_GENERIC_CSUM=y 21CONFIG_GENERIC_CSUM=y
22CONFIG_STACKTRACE_SUPPORT=y
23CONFIG_LOCKDEP_SUPPORT=y
24CONFIG_HAVE_LATENCYTOP_SUPPORT=y
22# CONFIG_PCI is not set 25# CONFIG_PCI is not set
23CONFIG_NO_DMA=y 26CONFIG_NO_DMA=y
27CONFIG_DTC=y
24CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
25CONFIG_CONSTRUCTORS=y 29CONFIG_CONSTRUCTORS=y
26 30
@@ -46,6 +50,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
46# 50#
47CONFIG_TREE_RCU=y 51CONFIG_TREE_RCU=y
48# CONFIG_TREE_PREEMPT_RCU is not set 52# CONFIG_TREE_PREEMPT_RCU is not set
53# CONFIG_TINY_RCU is not set
49# CONFIG_RCU_TRACE is not set 54# CONFIG_RCU_TRACE is not set
50CONFIG_RCU_FANOUT=32 55CONFIG_RCU_FANOUT=32
51# CONFIG_RCU_FANOUT_EXACT is not set 56# CONFIG_RCU_FANOUT_EXACT is not set
@@ -81,16 +86,16 @@ CONFIG_EVENTFD=y
81CONFIG_AIO=y 86CONFIG_AIO=y
82 87
83# 88#
84# Performance Counters 89# Kernel Performance Events And Counters
85# 90#
86CONFIG_VM_EVENT_COUNTERS=y 91CONFIG_VM_EVENT_COUNTERS=y
87# CONFIG_STRIP_ASM_SYMS is not set
88CONFIG_COMPAT_BRK=y 92CONFIG_COMPAT_BRK=y
89CONFIG_SLAB=y 93CONFIG_SLAB=y
90# CONFIG_SLUB is not set 94# CONFIG_SLUB is not set
91# CONFIG_SLOB is not set 95# CONFIG_SLOB is not set
96# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set
92# CONFIG_PROFILING is not set 97# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set 98CONFIG_HAVE_OPROFILE=y
94 99
95# 100#
96# GCOV-based kernel profiling 101# GCOV-based kernel profiling
@@ -116,14 +121,41 @@ CONFIG_LBDAF=y
116# IO Schedulers 121# IO Schedulers
117# 122#
118CONFIG_IOSCHED_NOOP=y 123CONFIG_IOSCHED_NOOP=y
119CONFIG_IOSCHED_AS=y
120CONFIG_IOSCHED_DEADLINE=y 124CONFIG_IOSCHED_DEADLINE=y
121CONFIG_IOSCHED_CFQ=y 125CONFIG_IOSCHED_CFQ=y
122# CONFIG_DEFAULT_AS is not set
123# CONFIG_DEFAULT_DEADLINE is not set 126# CONFIG_DEFAULT_DEADLINE is not set
124CONFIG_DEFAULT_CFQ=y 127CONFIG_DEFAULT_CFQ=y
125# CONFIG_DEFAULT_NOOP is not set 128# CONFIG_DEFAULT_NOOP is not set
126CONFIG_DEFAULT_IOSCHED="cfq" 129CONFIG_DEFAULT_IOSCHED="cfq"
130# CONFIG_INLINE_SPIN_TRYLOCK is not set
131# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
132# CONFIG_INLINE_SPIN_LOCK is not set
133# CONFIG_INLINE_SPIN_LOCK_BH is not set
134# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
135# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
136CONFIG_INLINE_SPIN_UNLOCK=y
137# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
138CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
139# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
140# CONFIG_INLINE_READ_TRYLOCK is not set
141# CONFIG_INLINE_READ_LOCK is not set
142# CONFIG_INLINE_READ_LOCK_BH is not set
143# CONFIG_INLINE_READ_LOCK_IRQ is not set
144# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
145CONFIG_INLINE_READ_UNLOCK=y
146# CONFIG_INLINE_READ_UNLOCK_BH is not set
147CONFIG_INLINE_READ_UNLOCK_IRQ=y
148# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
149# CONFIG_INLINE_WRITE_TRYLOCK is not set
150# CONFIG_INLINE_WRITE_LOCK is not set
151# CONFIG_INLINE_WRITE_LOCK_BH is not set
152# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
153# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
154CONFIG_INLINE_WRITE_UNLOCK=y
155# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
156CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
157# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
158# CONFIG_MUTEX_SPIN_ON_OWNER is not set
127# CONFIG_FREEZER is not set 159# CONFIG_FREEZER is not set
128 160
129# 161#
@@ -132,7 +164,10 @@ CONFIG_DEFAULT_IOSCHED="cfq"
132CONFIG_PLATFORM_GENERIC=y 164CONFIG_PLATFORM_GENERIC=y
133# CONFIG_SELFMOD is not set 165# CONFIG_SELFMOD is not set
134# CONFIG_OPT_LIB_FUNCTION is not set 166# CONFIG_OPT_LIB_FUNCTION is not set
135# CONFIG_ALLOW_EDIT_AUTO is not set 167
168#
169# Definitions for MICROBLAZE0
170#
136CONFIG_KERNEL_BASE_ADDR=0x90000000 171CONFIG_KERNEL_BASE_ADDR=0x90000000
137CONFIG_XILINX_MICROBLAZE0_FAMILY="virtex5" 172CONFIG_XILINX_MICROBLAZE0_FAMILY="virtex5"
138CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 173CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
@@ -190,7 +225,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
190# CONFIG_PHYS_ADDR_T_64BIT is not set 225# CONFIG_PHYS_ADDR_T_64BIT is not set
191CONFIG_ZONE_DMA_FLAG=0 226CONFIG_ZONE_DMA_FLAG=0
192CONFIG_VIRT_TO_BUS=y 227CONFIG_VIRT_TO_BUS=y
193CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
194CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1 228CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1
195 229
196# 230#
@@ -274,9 +308,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
274# CONFIG_AF_RXRPC is not set 308# CONFIG_AF_RXRPC is not set
275CONFIG_WIRELESS=y 309CONFIG_WIRELESS=y
276# CONFIG_CFG80211 is not set 310# CONFIG_CFG80211 is not set
277CONFIG_CFG80211_DEFAULT_PS_VALUE=0
278CONFIG_WIRELESS_OLD_REGULATORY=y
279# CONFIG_WIRELESS_EXT is not set
280# CONFIG_LIB80211 is not set 311# CONFIG_LIB80211 is not set
281 312
282# 313#
@@ -301,9 +332,9 @@ CONFIG_STANDALONE=y
301# CONFIG_CONNECTOR is not set 332# CONFIG_CONNECTOR is not set
302CONFIG_MTD=y 333CONFIG_MTD=y
303# CONFIG_MTD_DEBUG is not set 334# CONFIG_MTD_DEBUG is not set
335# CONFIG_MTD_TESTS is not set
304CONFIG_MTD_CONCAT=y 336CONFIG_MTD_CONCAT=y
305CONFIG_MTD_PARTITIONS=y 337CONFIG_MTD_PARTITIONS=y
306# CONFIG_MTD_TESTS is not set
307# CONFIG_MTD_REDBOOT_PARTS is not set 338# CONFIG_MTD_REDBOOT_PARTS is not set
308CONFIG_MTD_CMDLINE_PARTS=y 339CONFIG_MTD_CMDLINE_PARTS=y
309# CONFIG_MTD_OF_PARTS is not set 340# CONFIG_MTD_OF_PARTS is not set
@@ -387,6 +418,10 @@ CONFIG_OF_DEVICE=y
387CONFIG_BLK_DEV=y 418CONFIG_BLK_DEV=y
388# CONFIG_BLK_DEV_COW_COMMON is not set 419# CONFIG_BLK_DEV_COW_COMMON is not set
389# CONFIG_BLK_DEV_LOOP is not set 420# CONFIG_BLK_DEV_LOOP is not set
421
422#
423# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
424#
390CONFIG_BLK_DEV_NBD=y 425CONFIG_BLK_DEV_NBD=y
391CONFIG_BLK_DEV_RAM=y 426CONFIG_BLK_DEV_RAM=y
392CONFIG_BLK_DEV_RAM_COUNT=16 427CONFIG_BLK_DEV_RAM_COUNT=16
@@ -423,7 +458,6 @@ CONFIG_NETDEVICES=y
423# CONFIG_PHYLIB is not set 458# CONFIG_PHYLIB is not set
424CONFIG_NET_ETHERNET=y 459CONFIG_NET_ETHERNET=y
425# CONFIG_MII is not set 460# CONFIG_MII is not set
426# CONFIG_ETHOC is not set
427# CONFIG_DNET is not set 461# CONFIG_DNET is not set
428# CONFIG_IBM_NEW_EMAC_ZMII is not set 462# CONFIG_IBM_NEW_EMAC_ZMII is not set
429# CONFIG_IBM_NEW_EMAC_RGMII is not set 463# CONFIG_IBM_NEW_EMAC_RGMII is not set
@@ -433,12 +467,12 @@ CONFIG_NET_ETHERNET=y
433# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set 467# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
434# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set 468# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
435# CONFIG_KS8842 is not set 469# CONFIG_KS8842 is not set
470# CONFIG_KS8851_MLL is not set
436# CONFIG_XILINX_EMACLITE is not set 471# CONFIG_XILINX_EMACLITE is not set
437CONFIG_NETDEV_1000=y 472CONFIG_NETDEV_1000=y
438CONFIG_NETDEV_10000=y 473CONFIG_NETDEV_10000=y
439CONFIG_WLAN=y 474CONFIG_WLAN=y
440# CONFIG_WLAN_PRE80211 is not set 475# CONFIG_HOSTAP is not set
441# CONFIG_WLAN_80211 is not set
442 476
443# 477#
444# Enable WiMAX (Networking options) to see the WiMAX drivers 478# Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -482,6 +516,7 @@ CONFIG_SERIAL_UARTLITE=y
482CONFIG_SERIAL_UARTLITE_CONSOLE=y 516CONFIG_SERIAL_UARTLITE_CONSOLE=y
483CONFIG_SERIAL_CORE=y 517CONFIG_SERIAL_CORE=y
484CONFIG_SERIAL_CORE_CONSOLE=y 518CONFIG_SERIAL_CORE_CONSOLE=y
519# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
485CONFIG_UNIX98_PTYS=y 520CONFIG_UNIX98_PTYS=y
486# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 521# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
487CONFIG_LEGACY_PTYS=y 522CONFIG_LEGACY_PTYS=y
@@ -508,7 +543,6 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
508# CONFIG_POWER_SUPPLY is not set 543# CONFIG_POWER_SUPPLY is not set
509# CONFIG_HWMON is not set 544# CONFIG_HWMON is not set
510# CONFIG_THERMAL is not set 545# CONFIG_THERMAL is not set
511# CONFIG_THERMAL_HWMON is not set
512# CONFIG_WATCHDOG is not set 546# CONFIG_WATCHDOG is not set
513 547
514# 548#
@@ -616,7 +650,6 @@ CONFIG_INOTIFY_USER=y
616CONFIG_PROC_FS=y 650CONFIG_PROC_FS=y
617CONFIG_PROC_SYSCTL=y 651CONFIG_PROC_SYSCTL=y
618CONFIG_SYSFS=y 652CONFIG_SYSFS=y
619# CONFIG_TMPFS is not set
620# CONFIG_HUGETLB_PAGE is not set 653# CONFIG_HUGETLB_PAGE is not set
621# CONFIG_CONFIGFS_FS is not set 654# CONFIG_CONFIGFS_FS is not set
622CONFIG_MISC_FILESYSTEMS=y 655CONFIG_MISC_FILESYSTEMS=y
@@ -672,11 +705,13 @@ CONFIG_MSDOS_PARTITION=y
672# 705#
673# Kernel hacking 706# Kernel hacking
674# 707#
708CONFIG_TRACE_IRQFLAGS_SUPPORT=y
675# CONFIG_PRINTK_TIME is not set 709# CONFIG_PRINTK_TIME is not set
676CONFIG_ENABLE_WARN_DEPRECATED=y 710CONFIG_ENABLE_WARN_DEPRECATED=y
677CONFIG_ENABLE_MUST_CHECK=y 711CONFIG_ENABLE_MUST_CHECK=y
678CONFIG_FRAME_WARN=1024 712CONFIG_FRAME_WARN=1024
679# CONFIG_MAGIC_SYSRQ is not set 713# CONFIG_MAGIC_SYSRQ is not set
714# CONFIG_STRIP_ASM_SYMS is not set
680CONFIG_UNUSED_SYMBOLS=y 715CONFIG_UNUSED_SYMBOLS=y
681CONFIG_DEBUG_FS=y 716CONFIG_DEBUG_FS=y
682# CONFIG_HEADERS_CHECK is not set 717# CONFIG_HEADERS_CHECK is not set
@@ -695,12 +730,16 @@ CONFIG_DEBUG_OBJECTS=y
695CONFIG_DEBUG_OBJECTS_SELFTEST=y 730CONFIG_DEBUG_OBJECTS_SELFTEST=y
696CONFIG_DEBUG_OBJECTS_FREE=y 731CONFIG_DEBUG_OBJECTS_FREE=y
697CONFIG_DEBUG_OBJECTS_TIMERS=y 732CONFIG_DEBUG_OBJECTS_TIMERS=y
733# CONFIG_DEBUG_OBJECTS_WORK is not set
698CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 734CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
699# CONFIG_DEBUG_SLAB is not set 735# CONFIG_DEBUG_SLAB is not set
700# CONFIG_DEBUG_RT_MUTEXES is not set 736# CONFIG_DEBUG_RT_MUTEXES is not set
701# CONFIG_RT_MUTEX_TESTER is not set 737# CONFIG_RT_MUTEX_TESTER is not set
702# CONFIG_DEBUG_SPINLOCK is not set 738# CONFIG_DEBUG_SPINLOCK is not set
703# CONFIG_DEBUG_MUTEXES is not set 739# CONFIG_DEBUG_MUTEXES is not set
740# CONFIG_DEBUG_LOCK_ALLOC is not set
741# CONFIG_PROVE_LOCKING is not set
742# CONFIG_LOCK_STAT is not set
704# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 743# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
705# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 744# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
706# CONFIG_DEBUG_KOBJECT is not set 745# CONFIG_DEBUG_KOBJECT is not set
@@ -720,8 +759,28 @@ CONFIG_DEBUG_SG=y
720# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 759# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
721# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 760# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
722# CONFIG_FAULT_INJECTION is not set 761# CONFIG_FAULT_INJECTION is not set
762# CONFIG_LATENCYTOP is not set
723CONFIG_SYSCTL_SYSCALL_CHECK=y 763CONFIG_SYSCTL_SYSCALL_CHECK=y
724# CONFIG_PAGE_POISONING is not set 764# CONFIG_PAGE_POISONING is not set
765CONFIG_HAVE_FUNCTION_TRACER=y
766CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
767CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
768CONFIG_HAVE_DYNAMIC_FTRACE=y
769CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
770CONFIG_TRACING_SUPPORT=y
771CONFIG_FTRACE=y
772# CONFIG_FUNCTION_TRACER is not set
773# CONFIG_IRQSOFF_TRACER is not set
774# CONFIG_SCHED_TRACER is not set
775# CONFIG_ENABLE_DEFAULT_TRACERS is not set
776# CONFIG_BOOT_TRACER is not set
777CONFIG_BRANCH_PROFILE_NONE=y
778# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
779# CONFIG_PROFILE_ALL_BRANCHES is not set
780# CONFIG_STACK_TRACER is not set
781# CONFIG_KMEMTRACE is not set
782# CONFIG_WORKQUEUE_TRACER is not set
783# CONFIG_BLK_DEV_IO_TRACE is not set
725# CONFIG_DYNAMIC_DEBUG is not set 784# CONFIG_DYNAMIC_DEBUG is not set
726# CONFIG_SAMPLES is not set 785# CONFIG_SAMPLES is not set
727CONFIG_EARLY_PRINTK=y 786CONFIG_EARLY_PRINTK=y
@@ -734,7 +793,11 @@ CONFIG_EARLY_PRINTK=y
734# CONFIG_KEYS is not set 793# CONFIG_KEYS is not set
735# CONFIG_SECURITY is not set 794# CONFIG_SECURITY is not set
736# CONFIG_SECURITYFS is not set 795# CONFIG_SECURITYFS is not set
737# CONFIG_SECURITY_FILE_CAPABILITIES is not set 796# CONFIG_DEFAULT_SECURITY_SELINUX is not set
797# CONFIG_DEFAULT_SECURITY_SMACK is not set
798# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
799CONFIG_DEFAULT_SECURITY_DAC=y
800CONFIG_DEFAULT_SECURITY=""
738CONFIG_CRYPTO=y 801CONFIG_CRYPTO=y
739 802
740# 803#
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index fc9997b73c09..267c7c779e53 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -217,7 +217,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
217 * Little endian 217 * Little endian
218 */ 218 */
219 219
220#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a)); 220#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
221#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a)) 221#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
222 222
223#define in_le32(a) __le32_to_cpu(__raw_readl(a)) 223#define in_le32(a) __le32_to_cpu(__raw_readl(a))
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index d9d63831cc2f..2a56bccce4e0 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -172,16 +172,15 @@ do { \
172/* It is used only first parameter for OP - for wic, wdc */ 172/* It is used only first parameter for OP - for wic, wdc */
173#define CACHE_RANGE_LOOP_1(start, end, line_length, op) \ 173#define CACHE_RANGE_LOOP_1(start, end, line_length, op) \
174do { \ 174do { \
175 int step = -line_length; \ 175 int volatile temp; \
176 int count = end - start; \ 176 BUG_ON(end - start <= 0); \
177 BUG_ON(count <= 0); \
178 \ 177 \
179 __asm__ __volatile__ (" 1: addk %0, %0, %1; \ 178 __asm__ __volatile__ (" 1: " #op " %1, r0; \
180 " #op " %0, r0; \ 179 cmpu %0, %1, %2; \
181 bgtid %1, 1b; \ 180 bgtid %0, 1b; \
182 addk %1, %1, %2; \ 181 addk %1, %1, %3; \
183 " : : "r" (start), "r" (count), \ 182 " : : "r" (temp), "r" (start), "r" (end),\
184 "r" (step) : "memory"); \ 183 "r" (line_length) : "memory"); \
185} while (0); 184} while (0);
186 185
187static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end) 186static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end)
@@ -313,16 +312,6 @@ static void __invalidate_dcache_all_wb(void)
313 pr_debug("%s\n", __func__); 312 pr_debug("%s\n", __func__);
314 CACHE_ALL_LOOP2(cpuinfo.dcache_size, cpuinfo.dcache_line_length, 313 CACHE_ALL_LOOP2(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
315 wdc.clear) 314 wdc.clear)
316
317#if 0
318 unsigned int i;
319
320 pr_debug("%s\n", __func__);
321
322 /* Just loop through cache size and invalidate it */
323 for (i = 0; i < cpuinfo.dcache_size; i += cpuinfo.dcache_line_length)
324 __invalidate_dcache(0, i);
325#endif
326} 315}
327 316
328static void __invalidate_dcache_range_wb(unsigned long start, 317static void __invalidate_dcache_range_wb(unsigned long start,
diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S
index 95b0855802df..391d6197fc3b 100644
--- a/arch/microblaze/kernel/entry-nommu.S
+++ b/arch/microblaze/kernel/entry-nommu.S
@@ -122,7 +122,7 @@ ENTRY(_interrupt)
122 122
123ret_from_intr: 123ret_from_intr:
124 lwi r11, r1, PT_MODE 124 lwi r11, r1, PT_MODE
125 bneid r11, 3f 125 bneid r11, no_intr_resched
126 126
127 lwi r6, r31, TS_THREAD_INFO /* get thread info */ 127 lwi r6, r31, TS_THREAD_INFO /* get thread info */
128 lwi r19, r6, TI_FLAGS /* get flags in thread info */ 128 lwi r19, r6, TI_FLAGS /* get flags in thread info */
@@ -133,16 +133,18 @@ ret_from_intr:
133 bralid r15, schedule 133 bralid r15, schedule
134 nop 134 nop
1351: andi r11, r19, _TIF_SIGPENDING 1351: andi r11, r19, _TIF_SIGPENDING
136 beqid r11, no_intr_reshed 136 beqid r11, no_intr_resched
137 addk r5, r1, r0 137 addk r5, r1, r0
138 addk r7, r0, r0 138 addk r7, r0, r0
139 bralid r15, do_signal 139 bralid r15, do_signal
140 addk r6, r0, r0 140 addk r6, r0, r0
141 141
142no_intr_reshed: 142no_intr_resched:
143 /* Disable interrupts, we are now committed to the state restore */
144 disable_irq
145
143 /* save mode indicator */ 146 /* save mode indicator */
144 lwi r11, r1, PT_MODE 147 lwi r11, r1, PT_MODE
1453:
146 swi r11, r0, PER_CPU(KM) 148 swi r11, r0, PER_CPU(KM)
147 149
148 /* save r31 */ 150 /* save r31 */
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 5372b24ad049..bb8c4b9ccb80 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -54,6 +54,7 @@ void __init setup_arch(char **cmdline_p)
54 54
55 microblaze_cache_init(); 55 microblaze_cache_init();
56 56
57 invalidate_dcache();
57 enable_dcache(); 58 enable_dcache();
58 59
59 invalidate_icache(); 60 invalidate_icache();
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index c51405e57921..29d3cbf9555f 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -141,6 +141,14 @@ static __init void prom_init_mem(void)
141 break; 141 break;
142 } 142 }
143 143
144 /* Ignoring the last page when ddr size is 128M. Cached
145 * accesses to last page is causing the processor to prefetch
146 * using address above 128M stepping out of the ddr address
147 * space.
148 */
149 if (mem == 0x8000000)
150 mem -= 0x1000;
151
144 add_memory_region(0, mem, BOOT_MEM_RAM); 152 add_memory_region(0, mem, BOOT_MEM_RAM);
145} 153}
146 154
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index ed84b4cb3c8d..84b6503f10b9 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc2 3# Linux kernel version: 2.6.33-rc6
4# Tue Aug 7 13:04:24 2007 4# Wed Feb 3 18:12:31 2010
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -9,20 +9,28 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
12# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
13# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
14# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
15# CONFIG_LEMOTE_FULONG is not set 18# CONFIG_LASAT is not set
19# CONFIG_MACH_LOONGSON is not set
16# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
17# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
18# CONFIG_MARKEINS is not set 22# CONFIG_NEC_MARKEINS is not set
19# CONFIG_MACH_VR41XX is not set 23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
20# CONFIG_PNX8550_JBS is not set 26# CONFIG_PNX8550_JBS is not set
21# CONFIG_PNX8550_STB810 is not set 27# CONFIG_PNX8550_STB810 is not set
22# CONFIG_PMC_MSP is not set 28# CONFIG_PMC_MSP is not set
23# CONFIG_PMC_YOSEMITE is not set 29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_POWERTV is not set
24# CONFIG_SGI_IP22 is not set 31# CONFIG_SGI_IP22 is not set
25CONFIG_SGI_IP27=y 32CONFIG_SGI_IP27=y
33# CONFIG_SGI_IP28 is not set
26# CONFIG_SGI_IP32 is not set 34# CONFIG_SGI_IP32 is not set
27# CONFIG_SIBYTE_CRHINE is not set 35# CONFIG_SIBYTE_CRHINE is not set
28# CONFIG_SIBYTE_CARMEL is not set 36# CONFIG_SIBYTE_CARMEL is not set
@@ -33,32 +41,39 @@ CONFIG_SGI_IP27=y
33# CONFIG_SIBYTE_SENTOSA is not set 41# CONFIG_SIBYTE_SENTOSA is not set
34# CONFIG_SIBYTE_BIGSUR is not set 42# CONFIG_SIBYTE_BIGSUR is not set
35# CONFIG_SNI_RM is not set 43# CONFIG_SNI_RM is not set
36# CONFIG_TOSHIBA_JMR3927 is not set 44# CONFIG_MACH_TX39XX is not set
37# CONFIG_TOSHIBA_RBTX4927 is not set 45# CONFIG_MACH_TX49XX is not set
38# CONFIG_TOSHIBA_RBTX4938 is not set 46# CONFIG_MIKROTIK_RB532 is not set
39# CONFIG_WR_PPMC is not set 47# CONFIG_WR_PPMC is not set
48# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
49# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
50# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
40CONFIG_SGI_SN_M_MODE=y 51CONFIG_SGI_SN_M_MODE=y
41# CONFIG_SGI_SN_N_MODE is not set 52# CONFIG_SGI_SN_N_MODE is not set
42# CONFIG_MAPPED_KERNEL is not set 53# CONFIG_MAPPED_KERNEL is not set
43# CONFIG_REPLICATE_KTEXT is not set 54# CONFIG_REPLICATE_KTEXT is not set
44# CONFIG_REPLICATE_EXHANDLERS is not set 55# CONFIG_REPLICATE_EXHANDLERS is not set
56CONFIG_LOONGSON_UART_BASE=y
45CONFIG_RWSEM_GENERIC_SPINLOCK=y 57CONFIG_RWSEM_GENERIC_SPINLOCK=y
46# CONFIG_ARCH_HAS_ILOG2_U32 is not set 58# CONFIG_ARCH_HAS_ILOG2_U32 is not set
47# CONFIG_ARCH_HAS_ILOG2_U64 is not set 59# CONFIG_ARCH_HAS_ILOG2_U64 is not set
60CONFIG_ARCH_SUPPORTS_OPROFILE=y
48CONFIG_GENERIC_FIND_NEXT_BIT=y 61CONFIG_GENERIC_FIND_NEXT_BIT=y
49CONFIG_GENERIC_HWEIGHT=y 62CONFIG_GENERIC_HWEIGHT=y
50CONFIG_GENERIC_CALIBRATE_DELAY=y 63CONFIG_GENERIC_CALIBRATE_DELAY=y
64CONFIG_GENERIC_CLOCKEVENTS=y
51CONFIG_GENERIC_TIME=y 65CONFIG_GENERIC_TIME=y
52CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 66CONFIG_GENERIC_CMOS_UPDATE=y
67CONFIG_SCHED_OMIT_FRAME_POINTER=y
53CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 68CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
54CONFIG_ARC=y 69CONFIG_ARC=y
55CONFIG_DMA_COHERENT=y 70CONFIG_DMA_COHERENT=y
56CONFIG_EARLY_PRINTK=y
57CONFIG_SYS_HAS_EARLY_PRINTK=y 71CONFIG_SYS_HAS_EARLY_PRINTK=y
58# CONFIG_NO_IOPORT is not set 72# CONFIG_NO_IOPORT is not set
59CONFIG_CPU_BIG_ENDIAN=y 73CONFIG_CPU_BIG_ENDIAN=y
60# CONFIG_CPU_LITTLE_ENDIAN is not set 74# CONFIG_CPU_LITTLE_ENDIAN is not set
61CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 75CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76CONFIG_DEFAULT_SGI_PARTITION=y
62CONFIG_MIPS_L1_CACHE_SHIFT=7 77CONFIG_MIPS_L1_CACHE_SHIFT=7
63CONFIG_ARC64=y 78CONFIG_ARC64=y
64CONFIG_BOOT_ELF64=y 79CONFIG_BOOT_ELF64=y
@@ -66,7 +81,8 @@ CONFIG_BOOT_ELF64=y
66# 81#
67# CPU selection 82# CPU selection
68# 83#
69# CONFIG_CPU_LOONGSON2 is not set 84# CONFIG_CPU_LOONGSON2E is not set
85# CONFIG_CPU_LOONGSON2F is not set
70# CONFIG_CPU_MIPS32_R1 is not set 86# CONFIG_CPU_MIPS32_R1 is not set
71# CONFIG_CPU_MIPS32_R2 is not set 87# CONFIG_CPU_MIPS32_R2 is not set
72# CONFIG_CPU_MIPS64_R1 is not set 88# CONFIG_CPU_MIPS64_R1 is not set
@@ -79,6 +95,7 @@ CONFIG_BOOT_ELF64=y
79# CONFIG_CPU_TX49XX is not set 95# CONFIG_CPU_TX49XX is not set
80# CONFIG_CPU_R5000 is not set 96# CONFIG_CPU_R5000 is not set
81# CONFIG_CPU_R5432 is not set 97# CONFIG_CPU_R5432 is not set
98# CONFIG_CPU_R5500 is not set
82# CONFIG_CPU_R6000 is not set 99# CONFIG_CPU_R6000 is not set
83# CONFIG_CPU_NEVADA is not set 100# CONFIG_CPU_NEVADA is not set
84# CONFIG_CPU_R8000 is not set 101# CONFIG_CPU_R8000 is not set
@@ -86,6 +103,7 @@ CONFIG_CPU_R10000=y
86# CONFIG_CPU_RM7000 is not set 103# CONFIG_CPU_RM7000 is not set
87# CONFIG_CPU_RM9000 is not set 104# CONFIG_CPU_RM9000 is not set
88# CONFIG_CPU_SB1 is not set 105# CONFIG_CPU_SB1 is not set
106# CONFIG_CPU_CAVIUM_OCTEON is not set
89CONFIG_SYS_HAS_CPU_R10000=y 107CONFIG_SYS_HAS_CPU_R10000=y
90CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y 108CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
91CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 109CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
@@ -99,6 +117,7 @@ CONFIG_64BIT=y
99CONFIG_PAGE_SIZE_4KB=y 117CONFIG_PAGE_SIZE_4KB=y
100# CONFIG_PAGE_SIZE_8KB is not set 118# CONFIG_PAGE_SIZE_8KB is not set
101# CONFIG_PAGE_SIZE_16KB is not set 119# CONFIG_PAGE_SIZE_16KB is not set
120# CONFIG_PAGE_SIZE_32KB is not set
102# CONFIG_PAGE_SIZE_64KB is not set 121# CONFIG_PAGE_SIZE_64KB is not set
103CONFIG_CPU_HAS_PREFETCH=y 122CONFIG_CPU_HAS_PREFETCH=y
104CONFIG_MIPS_MT_DISABLED=y 123CONFIG_MIPS_MT_DISABLED=y
@@ -110,6 +129,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
110CONFIG_IRQ_PER_CPU=y 129CONFIG_IRQ_PER_CPU=y
111CONFIG_CPU_SUPPORTS_HIGHMEM=y 130CONFIG_CPU_SUPPORTS_HIGHMEM=y
112CONFIG_ARCH_DISCONTIGMEM_ENABLE=y 131CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
132CONFIG_ARCH_POPULATES_NODE_MAP=y
113CONFIG_NUMA=y 133CONFIG_NUMA=y
114CONFIG_SYS_SUPPORTS_NUMA=y 134CONFIG_SYS_SUPPORTS_NUMA=y
115CONFIG_NODES_SHIFT=6 135CONFIG_NODES_SHIFT=6
@@ -120,16 +140,22 @@ CONFIG_DISCONTIGMEM_MANUAL=y
120CONFIG_DISCONTIGMEM=y 140CONFIG_DISCONTIGMEM=y
121CONFIG_FLAT_NODE_MEM_MAP=y 141CONFIG_FLAT_NODE_MEM_MAP=y
122CONFIG_NEED_MULTIPLE_NODES=y 142CONFIG_NEED_MULTIPLE_NODES=y
123# CONFIG_SPARSEMEM_STATIC is not set 143CONFIG_PAGEFLAGS_EXTENDED=y
124CONFIG_SPLIT_PTLOCK_CPUS=4 144CONFIG_SPLIT_PTLOCK_CPUS=4
125CONFIG_MIGRATION=y 145CONFIG_MIGRATION=y
126CONFIG_RESOURCES_64BIT=y 146CONFIG_PHYS_ADDR_T_64BIT=y
127CONFIG_ZONE_DMA_FLAG=0 147CONFIG_ZONE_DMA_FLAG=0
128CONFIG_VIRT_TO_BUS=y 148CONFIG_VIRT_TO_BUS=y
149# CONFIG_KSM is not set
150CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
129CONFIG_SMP=y 151CONFIG_SMP=y
130CONFIG_SYS_SUPPORTS_SMP=y 152CONFIG_SYS_SUPPORTS_SMP=y
131CONFIG_NR_CPUS_DEFAULT_64=y 153CONFIG_NR_CPUS_DEFAULT_64=y
132CONFIG_NR_CPUS=64 154CONFIG_NR_CPUS=64
155CONFIG_TICK_ONESHOT=y
156CONFIG_NO_HZ=y
157CONFIG_HIGH_RES_TIMERS=y
158CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
133# CONFIG_HZ_48 is not set 159# CONFIG_HZ_48 is not set
134# CONFIG_HZ_100 is not set 160# CONFIG_HZ_100 is not set
135# CONFIG_HZ_128 is not set 161# CONFIG_HZ_128 is not set
@@ -142,13 +168,13 @@ CONFIG_HZ=1000
142CONFIG_PREEMPT_NONE=y 168CONFIG_PREEMPT_NONE=y
143# CONFIG_PREEMPT_VOLUNTARY is not set 169# CONFIG_PREEMPT_VOLUNTARY is not set
144# CONFIG_PREEMPT is not set 170# CONFIG_PREEMPT is not set
145CONFIG_PREEMPT_BKL=y
146# CONFIG_MIPS_INSANE_LARGE is not set 171# CONFIG_MIPS_INSANE_LARGE is not set
147# CONFIG_KEXEC is not set 172# CONFIG_KEXEC is not set
148CONFIG_SECCOMP=y 173CONFIG_SECCOMP=y
149CONFIG_LOCKDEP_SUPPORT=y 174CONFIG_LOCKDEP_SUPPORT=y
150CONFIG_STACKTRACE_SUPPORT=y 175CONFIG_STACKTRACE_SUPPORT=y
151CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 176CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
177CONFIG_CONSTRUCTORS=y
152 178
153# 179#
154# General setup 180# General setup
@@ -162,20 +188,41 @@ CONFIG_SWAP=y
162CONFIG_SYSVIPC=y 188CONFIG_SYSVIPC=y
163CONFIG_SYSVIPC_SYSCTL=y 189CONFIG_SYSVIPC_SYSCTL=y
164CONFIG_POSIX_MQUEUE=y 190CONFIG_POSIX_MQUEUE=y
191CONFIG_POSIX_MQUEUE_SYSCTL=y
165# CONFIG_BSD_PROCESS_ACCT is not set 192# CONFIG_BSD_PROCESS_ACCT is not set
166# CONFIG_TASKSTATS is not set 193# CONFIG_TASKSTATS is not set
167# CONFIG_USER_NS is not set
168# CONFIG_AUDIT is not set 194# CONFIG_AUDIT is not set
195
196#
197# RCU Subsystem
198#
199CONFIG_TREE_RCU=y
200# CONFIG_TREE_PREEMPT_RCU is not set
201# CONFIG_TINY_RCU is not set
202# CONFIG_RCU_TRACE is not set
203CONFIG_RCU_FANOUT=64
204# CONFIG_RCU_FANOUT_EXACT is not set
205# CONFIG_TREE_RCU_TRACE is not set
169CONFIG_IKCONFIG=y 206CONFIG_IKCONFIG=y
170CONFIG_IKCONFIG_PROC=y 207CONFIG_IKCONFIG_PROC=y
171CONFIG_LOG_BUF_SHIFT=15 208CONFIG_LOG_BUF_SHIFT=15
209# CONFIG_GROUP_SCHED is not set
172CONFIG_CGROUPS=y 210CONFIG_CGROUPS=y
211# CONFIG_CGROUP_DEBUG is not set
212# CONFIG_CGROUP_NS is not set
213# CONFIG_CGROUP_FREEZER is not set
214# CONFIG_CGROUP_DEVICE is not set
173CONFIG_CPUSETS=y 215CONFIG_CPUSETS=y
174CONFIG_SYSFS_DEPRECATED=y 216CONFIG_PROC_PID_CPUSET=y
217# CONFIG_CGROUP_CPUACCT is not set
218# CONFIG_RESOURCE_COUNTERS is not set
219# CONFIG_SYSFS_DEPRECATED_V2 is not set
175CONFIG_RELAY=y 220CONFIG_RELAY=y
221# CONFIG_NAMESPACES is not set
176# CONFIG_BLK_DEV_INITRD is not set 222# CONFIG_BLK_DEV_INITRD is not set
177# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 223# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
178CONFIG_SYSCTL=y 224CONFIG_SYSCTL=y
225CONFIG_ANON_INODES=y
179CONFIG_EMBEDDED=y 226CONFIG_EMBEDDED=y
180CONFIG_SYSCTL_SYSCALL=y 227CONFIG_SYSCTL_SYSCALL=y
181CONFIG_KALLSYMS=y 228CONFIG_KALLSYMS=y
@@ -184,44 +231,92 @@ CONFIG_HOTPLUG=y
184CONFIG_PRINTK=y 231CONFIG_PRINTK=y
185CONFIG_BUG=y 232CONFIG_BUG=y
186CONFIG_ELF_CORE=y 233CONFIG_ELF_CORE=y
234# CONFIG_PCSPKR_PLATFORM is not set
187CONFIG_BASE_FULL=y 235CONFIG_BASE_FULL=y
188CONFIG_FUTEX=y 236CONFIG_FUTEX=y
189CONFIG_ANON_INODES=y
190CONFIG_EPOLL=y 237CONFIG_EPOLL=y
191CONFIG_SIGNALFD=y 238CONFIG_SIGNALFD=y
192CONFIG_TIMERFD=y 239CONFIG_TIMERFD=y
193CONFIG_EVENTFD=y 240CONFIG_EVENTFD=y
194CONFIG_SHMEM=y 241CONFIG_SHMEM=y
242CONFIG_AIO=y
243
244#
245# Kernel Performance Events And Counters
246#
195CONFIG_VM_EVENT_COUNTERS=y 247CONFIG_VM_EVENT_COUNTERS=y
248CONFIG_PCI_QUIRKS=y
249CONFIG_COMPAT_BRK=y
196CONFIG_SLAB=y 250CONFIG_SLAB=y
197# CONFIG_SLUB is not set 251# CONFIG_SLUB is not set
198# CONFIG_SLOB is not set 252# CONFIG_SLOB is not set
253# CONFIG_PROFILING is not set
254CONFIG_HAVE_OPROFILE=y
255CONFIG_HAVE_SYSCALL_WRAPPERS=y
256CONFIG_USE_GENERIC_SMP_HELPERS=y
257
258#
259# GCOV-based kernel profiling
260#
261CONFIG_SLOW_WORK=y
262CONFIG_HAVE_GENERIC_DMA_COHERENT=y
263CONFIG_SLABINFO=y
199CONFIG_RT_MUTEXES=y 264CONFIG_RT_MUTEXES=y
200# CONFIG_TINY_SHMEM is not set
201CONFIG_BASE_SMALL=0 265CONFIG_BASE_SMALL=0
202CONFIG_MODULES=y 266CONFIG_MODULES=y
267# CONFIG_MODULE_FORCE_LOAD is not set
203CONFIG_MODULE_UNLOAD=y 268CONFIG_MODULE_UNLOAD=y
204# CONFIG_MODULE_FORCE_UNLOAD is not set 269# CONFIG_MODULE_FORCE_UNLOAD is not set
205# CONFIG_MODVERSIONS is not set 270# CONFIG_MODVERSIONS is not set
206CONFIG_MODULE_SRCVERSION_ALL=y 271CONFIG_MODULE_SRCVERSION_ALL=y
207CONFIG_KMOD=y
208CONFIG_STOP_MACHINE=y 272CONFIG_STOP_MACHINE=y
209CONFIG_BLOCK=y 273CONFIG_BLOCK=y
210# CONFIG_BLK_DEV_IO_TRACE is not set
211# CONFIG_BLK_DEV_BSG is not set 274# CONFIG_BLK_DEV_BSG is not set
275# CONFIG_BLK_DEV_INTEGRITY is not set
276# CONFIG_BLK_CGROUP is not set
277CONFIG_BLOCK_COMPAT=y
212 278
213# 279#
214# IO Schedulers 280# IO Schedulers
215# 281#
216CONFIG_IOSCHED_NOOP=y 282CONFIG_IOSCHED_NOOP=y
217CONFIG_IOSCHED_AS=y
218CONFIG_IOSCHED_DEADLINE=y 283CONFIG_IOSCHED_DEADLINE=y
219CONFIG_IOSCHED_CFQ=y 284CONFIG_IOSCHED_CFQ=y
220CONFIG_DEFAULT_AS=y 285# CONFIG_CFQ_GROUP_IOSCHED is not set
221# CONFIG_DEFAULT_DEADLINE is not set 286# CONFIG_DEFAULT_DEADLINE is not set
222# CONFIG_DEFAULT_CFQ is not set 287CONFIG_DEFAULT_CFQ=y
223# CONFIG_DEFAULT_NOOP is not set 288# CONFIG_DEFAULT_NOOP is not set
224CONFIG_DEFAULT_IOSCHED="anticipatory" 289CONFIG_DEFAULT_IOSCHED="cfq"
290# CONFIG_INLINE_SPIN_TRYLOCK is not set
291# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
292# CONFIG_INLINE_SPIN_LOCK is not set
293# CONFIG_INLINE_SPIN_LOCK_BH is not set
294# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
295# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
296CONFIG_INLINE_SPIN_UNLOCK=y
297# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
298CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
299# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
300# CONFIG_INLINE_READ_TRYLOCK is not set
301# CONFIG_INLINE_READ_LOCK is not set
302# CONFIG_INLINE_READ_LOCK_BH is not set
303# CONFIG_INLINE_READ_LOCK_IRQ is not set
304# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
305CONFIG_INLINE_READ_UNLOCK=y
306# CONFIG_INLINE_READ_UNLOCK_BH is not set
307CONFIG_INLINE_READ_UNLOCK_IRQ=y
308# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
309# CONFIG_INLINE_WRITE_TRYLOCK is not set
310# CONFIG_INLINE_WRITE_LOCK is not set
311# CONFIG_INLINE_WRITE_LOCK_BH is not set
312# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
313# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
314CONFIG_INLINE_WRITE_UNLOCK=y
315# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
316CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
317# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
318CONFIG_MUTEX_SPIN_ON_OWNER=y
319# CONFIG_FREEZER is not set
225 320
226# 321#
227# Bus options (PCI, PCMCIA, EISA, ISA, TC) 322# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -230,11 +325,10 @@ CONFIG_HW_HAS_PCI=y
230CONFIG_PCI=y 325CONFIG_PCI=y
231CONFIG_PCI_DOMAINS=y 326CONFIG_PCI_DOMAINS=y
232# CONFIG_ARCH_SUPPORTS_MSI is not set 327# CONFIG_ARCH_SUPPORTS_MSI is not set
328# CONFIG_PCI_LEGACY is not set
329# CONFIG_PCI_STUB is not set
330# CONFIG_PCI_IOV is not set
233CONFIG_MMU=y 331CONFIG_MMU=y
234
235#
236# PCCARD (PCMCIA/CardBus) support
237#
238# CONFIG_PCCARD is not set 332# CONFIG_PCCARD is not set
239# CONFIG_HOTPLUG_PCI is not set 333# CONFIG_HOTPLUG_PCI is not set
240 334
@@ -242,8 +336,9 @@ CONFIG_MMU=y
242# Executable file formats 336# Executable file formats
243# 337#
244CONFIG_BINFMT_ELF=y 338CONFIG_BINFMT_ELF=y
339CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
340# CONFIG_HAVE_AOUT is not set
245# CONFIG_BINFMT_MISC is not set 341# CONFIG_BINFMT_MISC is not set
246# CONFIG_BUILD_ELF64 is not set
247CONFIG_MIPS32_COMPAT=y 342CONFIG_MIPS32_COMPAT=y
248CONFIG_COMPAT=y 343CONFIG_COMPAT=y
249CONFIG_SYSVIPC_COMPAT=y 344CONFIG_SYSVIPC_COMPAT=y
@@ -255,13 +350,10 @@ CONFIG_BINFMT_ELF32=y
255# Power management options 350# Power management options
256# 351#
257CONFIG_PM=y 352CONFIG_PM=y
258# CONFIG_PM_LEGACY is not set
259# CONFIG_PM_DEBUG is not set 353# CONFIG_PM_DEBUG is not set
260 354# CONFIG_PM_RUNTIME is not set
261#
262# Networking
263#
264CONFIG_NET=y 355CONFIG_NET=y
356CONFIG_COMPAT_NETLINK_MESSAGES=y
265 357
266# 358#
267# Networking options 359# Networking options
@@ -273,6 +365,8 @@ CONFIG_XFRM=y
273CONFIG_XFRM_USER=m 365CONFIG_XFRM_USER=m
274# CONFIG_XFRM_SUB_POLICY is not set 366# CONFIG_XFRM_SUB_POLICY is not set
275CONFIG_XFRM_MIGRATE=y 367CONFIG_XFRM_MIGRATE=y
368CONFIG_XFRM_STATISTICS=y
369CONFIG_XFRM_IPCOMP=m
276CONFIG_NET_KEY=y 370CONFIG_NET_KEY=y
277CONFIG_NET_KEY_MIGRATE=y 371CONFIG_NET_KEY_MIGRATE=y
278CONFIG_INET=y 372CONFIG_INET=y
@@ -292,19 +386,40 @@ CONFIG_IP_PNP=y
292# CONFIG_INET_ESP is not set 386# CONFIG_INET_ESP is not set
293# CONFIG_INET_IPCOMP is not set 387# CONFIG_INET_IPCOMP is not set
294# CONFIG_INET_XFRM_TUNNEL is not set 388# CONFIG_INET_XFRM_TUNNEL is not set
295# CONFIG_INET_TUNNEL is not set 389CONFIG_INET_TUNNEL=m
296CONFIG_INET_XFRM_MODE_TRANSPORT=m 390CONFIG_INET_XFRM_MODE_TRANSPORT=m
297CONFIG_INET_XFRM_MODE_TUNNEL=m 391CONFIG_INET_XFRM_MODE_TUNNEL=m
298CONFIG_INET_XFRM_MODE_BEET=m 392CONFIG_INET_XFRM_MODE_BEET=m
393CONFIG_INET_LRO=y
299CONFIG_INET_DIAG=y 394CONFIG_INET_DIAG=y
300CONFIG_INET_TCP_DIAG=y 395CONFIG_INET_TCP_DIAG=y
301# CONFIG_TCP_CONG_ADVANCED is not set 396# CONFIG_TCP_CONG_ADVANCED is not set
302CONFIG_TCP_CONG_CUBIC=y 397CONFIG_TCP_CONG_CUBIC=y
303CONFIG_DEFAULT_TCP_CONG="cubic" 398CONFIG_DEFAULT_TCP_CONG="cubic"
304CONFIG_TCP_MD5SIG=y 399CONFIG_TCP_MD5SIG=y
305# CONFIG_IPV6 is not set 400CONFIG_IPV6=y
306# CONFIG_INET6_XFRM_TUNNEL is not set 401CONFIG_IPV6_PRIVACY=y
307# CONFIG_INET6_TUNNEL is not set 402CONFIG_IPV6_ROUTER_PREF=y
403CONFIG_IPV6_ROUTE_INFO=y
404CONFIG_IPV6_OPTIMISTIC_DAD=y
405CONFIG_INET6_AH=m
406CONFIG_INET6_ESP=m
407CONFIG_INET6_IPCOMP=m
408CONFIG_IPV6_MIP6=m
409CONFIG_INET6_XFRM_TUNNEL=m
410CONFIG_INET6_TUNNEL=m
411CONFIG_INET6_XFRM_MODE_TRANSPORT=m
412CONFIG_INET6_XFRM_MODE_TUNNEL=m
413CONFIG_INET6_XFRM_MODE_BEET=m
414CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
415CONFIG_IPV6_SIT=m
416CONFIG_IPV6_SIT_6RD=y
417CONFIG_IPV6_NDISC_NODETYPE=y
418CONFIG_IPV6_TUNNEL=m
419CONFIG_IPV6_MULTIPLE_TABLES=y
420CONFIG_IPV6_SUBTREES=y
421CONFIG_IPV6_MROUTE=y
422CONFIG_IPV6_PIMSM_V2=y
308CONFIG_NETWORK_SECMARK=y 423CONFIG_NETWORK_SECMARK=y
309# CONFIG_NETFILTER is not set 424# CONFIG_NETFILTER is not set
310# CONFIG_IP_DCCP is not set 425# CONFIG_IP_DCCP is not set
@@ -314,9 +429,11 @@ CONFIG_IP_SCTP=m
314# CONFIG_SCTP_HMAC_NONE is not set 429# CONFIG_SCTP_HMAC_NONE is not set
315# CONFIG_SCTP_HMAC_SHA1 is not set 430# CONFIG_SCTP_HMAC_SHA1 is not set
316CONFIG_SCTP_HMAC_MD5=y 431CONFIG_SCTP_HMAC_MD5=y
432# CONFIG_RDS is not set
317# CONFIG_TIPC is not set 433# CONFIG_TIPC is not set
318# CONFIG_ATM is not set 434# CONFIG_ATM is not set
319# CONFIG_BRIDGE is not set 435# CONFIG_BRIDGE is not set
436# CONFIG_NET_DSA is not set
320# CONFIG_VLAN_8021Q is not set 437# CONFIG_VLAN_8021Q is not set
321# CONFIG_DECNET is not set 438# CONFIG_DECNET is not set
322# CONFIG_LLC2 is not set 439# CONFIG_LLC2 is not set
@@ -326,12 +443,9 @@ CONFIG_SCTP_HMAC_MD5=y
326# CONFIG_LAPB is not set 443# CONFIG_LAPB is not set
327# CONFIG_ECONET is not set 444# CONFIG_ECONET is not set
328# CONFIG_WAN_ROUTER is not set 445# CONFIG_WAN_ROUTER is not set
329 446# CONFIG_PHONET is not set
330# 447# CONFIG_IEEE802154 is not set
331# QoS and/or fair queueing
332#
333CONFIG_NET_SCHED=y 448CONFIG_NET_SCHED=y
334CONFIG_NET_SCH_FIFO=y
335 449
336# 450#
337# Queueing/Scheduling 451# Queueing/Scheduling
@@ -340,7 +454,7 @@ CONFIG_NET_SCH_CBQ=m
340CONFIG_NET_SCH_HTB=m 454CONFIG_NET_SCH_HTB=m
341CONFIG_NET_SCH_HFSC=m 455CONFIG_NET_SCH_HFSC=m
342CONFIG_NET_SCH_PRIO=m 456CONFIG_NET_SCH_PRIO=m
343CONFIG_NET_SCH_RR=m 457CONFIG_NET_SCH_MULTIQ=y
344CONFIG_NET_SCH_RED=m 458CONFIG_NET_SCH_RED=m
345CONFIG_NET_SCH_SFQ=m 459CONFIG_NET_SCH_SFQ=m
346CONFIG_NET_SCH_TEQL=m 460CONFIG_NET_SCH_TEQL=m
@@ -348,6 +462,7 @@ CONFIG_NET_SCH_TBF=m
348CONFIG_NET_SCH_GRED=m 462CONFIG_NET_SCH_GRED=m
349CONFIG_NET_SCH_DSMARK=m 463CONFIG_NET_SCH_DSMARK=m
350CONFIG_NET_SCH_NETEM=m 464CONFIG_NET_SCH_NETEM=m
465# CONFIG_NET_SCH_DRR is not set
351CONFIG_NET_SCH_INGRESS=m 466CONFIG_NET_SCH_INGRESS=m
352 467
353# 468#
@@ -364,41 +479,63 @@ CONFIG_NET_CLS_U32=m
364CONFIG_CLS_U32_MARK=y 479CONFIG_CLS_U32_MARK=y
365CONFIG_NET_CLS_RSVP=m 480CONFIG_NET_CLS_RSVP=m
366CONFIG_NET_CLS_RSVP6=m 481CONFIG_NET_CLS_RSVP6=m
482CONFIG_NET_CLS_FLOW=m
483CONFIG_NET_CLS_CGROUP=y
367# CONFIG_NET_EMATCH is not set 484# CONFIG_NET_EMATCH is not set
368CONFIG_NET_CLS_ACT=y 485CONFIG_NET_CLS_ACT=y
369CONFIG_NET_ACT_POLICE=y 486CONFIG_NET_ACT_POLICE=y
370CONFIG_NET_ACT_GACT=m 487CONFIG_NET_ACT_GACT=m
371CONFIG_GACT_PROB=y 488CONFIG_GACT_PROB=y
372CONFIG_NET_ACT_MIRRED=m 489CONFIG_NET_ACT_MIRRED=m
490CONFIG_NET_ACT_NAT=m
373CONFIG_NET_ACT_PEDIT=m 491CONFIG_NET_ACT_PEDIT=m
374# CONFIG_NET_ACT_SIMP is not set 492# CONFIG_NET_ACT_SIMP is not set
375CONFIG_NET_CLS_POLICE=y 493CONFIG_NET_ACT_SKBEDIT=m
376# CONFIG_NET_CLS_IND is not set 494# CONFIG_NET_CLS_IND is not set
495CONFIG_NET_SCH_FIFO=y
496# CONFIG_DCB is not set
377 497
378# 498#
379# Network testing 499# Network testing
380# 500#
381# CONFIG_NET_PKTGEN is not set 501# CONFIG_NET_PKTGEN is not set
382# CONFIG_HAMRADIO is not set 502# CONFIG_HAMRADIO is not set
503# CONFIG_CAN is not set
383# CONFIG_IRDA is not set 504# CONFIG_IRDA is not set
384# CONFIG_BT is not set 505# CONFIG_BT is not set
385# CONFIG_AF_RXRPC is not set 506# CONFIG_AF_RXRPC is not set
386 507CONFIG_FIB_RULES=y
387# 508CONFIG_WIRELESS=y
388# Wireless
389#
390CONFIG_CFG80211=m
391CONFIG_WIRELESS_EXT=y 509CONFIG_WIRELESS_EXT=y
510CONFIG_WEXT_CORE=y
511CONFIG_WEXT_PROC=y
512CONFIG_WEXT_SPY=y
513CONFIG_WEXT_PRIV=y
514CONFIG_CFG80211=m
515# CONFIG_NL80211_TESTMODE is not set
516# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
517# CONFIG_CFG80211_REG_DEBUG is not set
518CONFIG_CFG80211_DEFAULT_PS=y
519# CONFIG_WIRELESS_OLD_REGULATORY is not set
520CONFIG_CFG80211_WEXT=y
521CONFIG_WIRELESS_EXT_SYSFS=y
522CONFIG_LIB80211=m
523CONFIG_LIB80211_CRYPT_WEP=m
524CONFIG_LIB80211_CRYPT_CCMP=m
525CONFIG_LIB80211_CRYPT_TKIP=m
526# CONFIG_LIB80211_DEBUG is not set
392CONFIG_MAC80211=m 527CONFIG_MAC80211=m
393# CONFIG_MAC80211_DEBUG is not set 528CONFIG_MAC80211_RC_PID=y
394CONFIG_IEEE80211=m 529CONFIG_MAC80211_RC_MINSTREL=y
395# CONFIG_IEEE80211_DEBUG is not set 530# CONFIG_MAC80211_RC_DEFAULT_PID is not set
396CONFIG_IEEE80211_CRYPT_WEP=m 531CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
397CONFIG_IEEE80211_CRYPT_CCMP=m 532CONFIG_MAC80211_RC_DEFAULT="minstrel"
398CONFIG_IEEE80211_CRYPT_TKIP=m 533# CONFIG_MAC80211_MESH is not set
399CONFIG_IEEE80211_SOFTMAC=m 534CONFIG_MAC80211_LEDS=y
400# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set 535# CONFIG_MAC80211_DEBUG_MENU is not set
536# CONFIG_WIMAX is not set
401CONFIG_RFKILL=m 537CONFIG_RFKILL=m
538CONFIG_RFKILL_LEDS=y
402# CONFIG_NET_9P is not set 539# CONFIG_NET_9P is not set
403 540
404# 541#
@@ -408,9 +545,13 @@ CONFIG_RFKILL=m
408# 545#
409# Generic Driver Options 546# Generic Driver Options
410# 547#
548CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
549# CONFIG_DEVTMPFS is not set
411CONFIG_STANDALONE=y 550CONFIG_STANDALONE=y
412CONFIG_PREVENT_FIRMWARE_BUILD=y 551CONFIG_PREVENT_FIRMWARE_BUILD=y
413CONFIG_FW_LOADER=y 552CONFIG_FW_LOADER=y
553CONFIG_FIRMWARE_IN_KERNEL=y
554CONFIG_EXTRA_FIRMWARE=""
414# CONFIG_SYS_HYPERVISOR is not set 555# CONFIG_SYS_HYPERVISOR is not set
415CONFIG_CONNECTOR=m 556CONFIG_CONNECTOR=m
416# CONFIG_MTD is not set 557# CONFIG_MTD is not set
@@ -423,14 +564,19 @@ CONFIG_BLK_DEV=y
423# CONFIG_BLK_DEV_COW_COMMON is not set 564# CONFIG_BLK_DEV_COW_COMMON is not set
424CONFIG_BLK_DEV_LOOP=y 565CONFIG_BLK_DEV_LOOP=y
425CONFIG_BLK_DEV_CRYPTOLOOP=m 566CONFIG_BLK_DEV_CRYPTOLOOP=m
567# CONFIG_BLK_DEV_DRBD is not set
426# CONFIG_BLK_DEV_NBD is not set 568# CONFIG_BLK_DEV_NBD is not set
569CONFIG_BLK_DEV_OSD=m
427# CONFIG_BLK_DEV_SX8 is not set 570# CONFIG_BLK_DEV_SX8 is not set
428# CONFIG_BLK_DEV_RAM is not set 571# CONFIG_BLK_DEV_RAM is not set
429CONFIG_CDROM_PKTCDVD=m 572CONFIG_CDROM_PKTCDVD=m
430CONFIG_CDROM_PKTCDVD_BUFFERS=8 573CONFIG_CDROM_PKTCDVD_BUFFERS=8
431# CONFIG_CDROM_PKTCDVD_WCACHE is not set 574# CONFIG_CDROM_PKTCDVD_WCACHE is not set
432CONFIG_ATA_OVER_ETH=m 575CONFIG_ATA_OVER_ETH=m
576# CONFIG_BLK_DEV_HD is not set
433# CONFIG_MISC_DEVICES is not set 577# CONFIG_MISC_DEVICES is not set
578CONFIG_EEPROM_93CX6=m
579CONFIG_HAVE_IDE=y
434# CONFIG_IDE is not set 580# CONFIG_IDE is not set
435 581
436# 582#
@@ -453,10 +599,6 @@ CONFIG_BLK_DEV_SR=m
453CONFIG_BLK_DEV_SR_VENDOR=y 599CONFIG_BLK_DEV_SR_VENDOR=y
454CONFIG_CHR_DEV_SG=m 600CONFIG_CHR_DEV_SG=m
455CONFIG_CHR_DEV_SCH=m 601CONFIG_CHR_DEV_SCH=m
456
457#
458# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
459#
460# CONFIG_SCSI_MULTI_LUN is not set 602# CONFIG_SCSI_MULTI_LUN is not set
461CONFIG_SCSI_CONSTANTS=y 603CONFIG_SCSI_CONSTANTS=y
462CONFIG_SCSI_LOGGING=y 604CONFIG_SCSI_LOGGING=y
@@ -471,11 +613,18 @@ CONFIG_SCSI_FC_ATTRS=y
471CONFIG_SCSI_ISCSI_ATTRS=m 613CONFIG_SCSI_ISCSI_ATTRS=m
472CONFIG_SCSI_SAS_ATTRS=m 614CONFIG_SCSI_SAS_ATTRS=m
473CONFIG_SCSI_SAS_LIBSAS=m 615CONFIG_SCSI_SAS_LIBSAS=m
616CONFIG_SCSI_SAS_HOST_SMP=y
474# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set 617# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
618# CONFIG_SCSI_SRP_ATTRS is not set
475CONFIG_SCSI_LOWLEVEL=y 619CONFIG_SCSI_LOWLEVEL=y
476# CONFIG_ISCSI_TCP is not set 620# CONFIG_ISCSI_TCP is not set
621CONFIG_SCSI_CXGB3_ISCSI=m
622CONFIG_SCSI_BNX2_ISCSI=m
623CONFIG_BE2ISCSI=m
477# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 624# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
625CONFIG_SCSI_HPSA=m
478# CONFIG_SCSI_3W_9XXX is not set 626# CONFIG_SCSI_3W_9XXX is not set
627CONFIG_SCSI_3W_SAS=m
479# CONFIG_SCSI_ACARD is not set 628# CONFIG_SCSI_ACARD is not set
480# CONFIG_SCSI_AACRAID is not set 629# CONFIG_SCSI_AACRAID is not set
481# CONFIG_SCSI_AIC7XXX is not set 630# CONFIG_SCSI_AIC7XXX is not set
@@ -483,11 +632,21 @@ CONFIG_SCSI_LOWLEVEL=y
483# CONFIG_SCSI_AIC79XX is not set 632# CONFIG_SCSI_AIC79XX is not set
484CONFIG_SCSI_AIC94XX=m 633CONFIG_SCSI_AIC94XX=m
485# CONFIG_AIC94XX_DEBUG is not set 634# CONFIG_AIC94XX_DEBUG is not set
635CONFIG_SCSI_MVSAS=m
636# CONFIG_SCSI_MVSAS_DEBUG is not set
637CONFIG_SCSI_DPT_I2O=m
638# CONFIG_SCSI_ADVANSYS is not set
486# CONFIG_SCSI_ARCMSR is not set 639# CONFIG_SCSI_ARCMSR is not set
487# CONFIG_MEGARAID_NEWGEN is not set 640# CONFIG_MEGARAID_NEWGEN is not set
488# CONFIG_MEGARAID_LEGACY is not set 641# CONFIG_MEGARAID_LEGACY is not set
489# CONFIG_MEGARAID_SAS is not set 642# CONFIG_MEGARAID_SAS is not set
643CONFIG_SCSI_MPT2SAS=m
644CONFIG_SCSI_MPT2SAS_MAX_SGE=128
645# CONFIG_SCSI_MPT2SAS_LOGGING is not set
490# CONFIG_SCSI_HPTIOP is not set 646# CONFIG_SCSI_HPTIOP is not set
647CONFIG_LIBFC=m
648# CONFIG_LIBFCOE is not set
649# CONFIG_FCOE is not set
491# CONFIG_SCSI_DMX3191D is not set 650# CONFIG_SCSI_DMX3191D is not set
492# CONFIG_SCSI_FUTURE_DOMAIN is not set 651# CONFIG_SCSI_FUTURE_DOMAIN is not set
493# CONFIG_SCSI_IPS is not set 652# CONFIG_SCSI_IPS is not set
@@ -502,16 +661,31 @@ CONFIG_SCSI_QLOGIC_1280=y
502# CONFIG_SCSI_DC395x is not set 661# CONFIG_SCSI_DC395x is not set
503# CONFIG_SCSI_DC390T is not set 662# CONFIG_SCSI_DC390T is not set
504# CONFIG_SCSI_DEBUG is not set 663# CONFIG_SCSI_DEBUG is not set
664CONFIG_SCSI_PMCRAID=m
665# CONFIG_SCSI_PM8001 is not set
505# CONFIG_SCSI_SRP is not set 666# CONFIG_SCSI_SRP is not set
667CONFIG_SCSI_BFA_FC=m
668CONFIG_SCSI_DH=m
669CONFIG_SCSI_DH_RDAC=m
670CONFIG_SCSI_DH_HP_SW=m
671CONFIG_SCSI_DH_EMC=m
672CONFIG_SCSI_DH_ALUA=m
673CONFIG_SCSI_OSD_INITIATOR=m
674CONFIG_SCSI_OSD_ULD=m
675CONFIG_SCSI_OSD_DPRINT_SENSE=1
676# CONFIG_SCSI_OSD_DEBUG is not set
506# CONFIG_ATA is not set 677# CONFIG_ATA is not set
507CONFIG_MD=y 678CONFIG_MD=y
508CONFIG_BLK_DEV_MD=y 679CONFIG_BLK_DEV_MD=y
680CONFIG_MD_AUTODETECT=y
509CONFIG_MD_LINEAR=m 681CONFIG_MD_LINEAR=m
510CONFIG_MD_RAID0=y 682CONFIG_MD_RAID0=y
511CONFIG_MD_RAID1=y 683CONFIG_MD_RAID1=y
512CONFIG_MD_RAID10=m 684CONFIG_MD_RAID10=m
513CONFIG_MD_RAID456=y 685CONFIG_MD_RAID456=y
514CONFIG_MD_RAID5_RESHAPE=y 686# CONFIG_MULTICORE_RAID456 is not set
687CONFIG_MD_RAID6_PQ=y
688# CONFIG_ASYNC_RAID6_TEST is not set
515CONFIG_MD_MULTIPATH=m 689CONFIG_MD_MULTIPATH=m
516CONFIG_MD_FAULTY=m 690CONFIG_MD_FAULTY=m
517CONFIG_BLK_DEV_DM=m 691CONFIG_BLK_DEV_DM=m
@@ -519,36 +693,39 @@ CONFIG_BLK_DEV_DM=m
519CONFIG_DM_CRYPT=m 693CONFIG_DM_CRYPT=m
520CONFIG_DM_SNAPSHOT=m 694CONFIG_DM_SNAPSHOT=m
521CONFIG_DM_MIRROR=m 695CONFIG_DM_MIRROR=m
696CONFIG_DM_LOG_USERSPACE=m
522CONFIG_DM_ZERO=m 697CONFIG_DM_ZERO=m
523CONFIG_DM_MULTIPATH=m 698CONFIG_DM_MULTIPATH=m
524CONFIG_DM_MULTIPATH_EMC=m 699CONFIG_DM_MULTIPATH_QL=m
525CONFIG_DM_MULTIPATH_RDAC=m 700CONFIG_DM_MULTIPATH_ST=m
526# CONFIG_DM_DELAY is not set 701# CONFIG_DM_DELAY is not set
702CONFIG_DM_UEVENT=y
703# CONFIG_FUSION is not set
527 704
528# 705#
529# Fusion MPT device support 706# IEEE 1394 (FireWire) support
530# 707#
531# CONFIG_FUSION is not set
532# CONFIG_FUSION_SPI is not set
533# CONFIG_FUSION_FC is not set
534# CONFIG_FUSION_SAS is not set
535 708
536# 709#
537# IEEE 1394 (FireWire) support 710# You can enable one or both FireWire driver stacks.
711#
712
713#
714# The newer stack is recommended.
538# 715#
539# CONFIG_FIREWIRE is not set 716# CONFIG_FIREWIRE is not set
540# CONFIG_IEEE1394 is not set 717# CONFIG_IEEE1394 is not set
541# CONFIG_I2O is not set 718# CONFIG_I2O is not set
542CONFIG_NETDEVICES=y 719CONFIG_NETDEVICES=y
543CONFIG_NETDEVICES_MULTIQUEUE=y
544CONFIG_IFB=m 720CONFIG_IFB=m
545# CONFIG_DUMMY is not set 721# CONFIG_DUMMY is not set
546# CONFIG_BONDING is not set 722# CONFIG_BONDING is not set
547CONFIG_MACVLAN=m 723CONFIG_MACVLAN=m
548# CONFIG_EQUALIZER is not set 724# CONFIG_EQUALIZER is not set
549# CONFIG_TUN is not set 725# CONFIG_TUN is not set
726CONFIG_VETH=m
550# CONFIG_ARCNET is not set 727# CONFIG_ARCNET is not set
551CONFIG_PHYLIB=m 728CONFIG_PHYLIB=y
552 729
553# 730#
554# MII PHY device drivers 731# MII PHY device drivers
@@ -562,23 +739,51 @@ CONFIG_VITESSE_PHY=m
562CONFIG_SMSC_PHY=m 739CONFIG_SMSC_PHY=m
563# CONFIG_BROADCOM_PHY is not set 740# CONFIG_BROADCOM_PHY is not set
564CONFIG_ICPLUS_PHY=m 741CONFIG_ICPLUS_PHY=m
742CONFIG_REALTEK_PHY=m
743CONFIG_NATIONAL_PHY=m
744CONFIG_STE10XP=m
745CONFIG_LSI_ET1011C_PHY=m
565# CONFIG_FIXED_PHY is not set 746# CONFIG_FIXED_PHY is not set
747CONFIG_MDIO_BITBANG=m
566CONFIG_NET_ETHERNET=y 748CONFIG_NET_ETHERNET=y
567CONFIG_MII=y 749CONFIG_MII=y
568CONFIG_AX88796=m 750CONFIG_AX88796=m
751CONFIG_AX88796_93CX6=y
569CONFIG_SGI_IOC3_ETH=y 752CONFIG_SGI_IOC3_ETH=y
570# CONFIG_HAPPYMEAL is not set 753# CONFIG_HAPPYMEAL is not set
571# CONFIG_SUNGEM is not set 754# CONFIG_SUNGEM is not set
572# CONFIG_CASSINI is not set 755# CONFIG_CASSINI is not set
573# CONFIG_NET_VENDOR_3COM is not set 756# CONFIG_NET_VENDOR_3COM is not set
757CONFIG_SMC91X=m
574# CONFIG_DM9000 is not set 758# CONFIG_DM9000 is not set
759CONFIG_ETHOC=m
760CONFIG_SMSC911X=m
761CONFIG_DNET=m
575# CONFIG_NET_TULIP is not set 762# CONFIG_NET_TULIP is not set
576# CONFIG_HP100 is not set 763# CONFIG_HP100 is not set
764# CONFIG_IBM_NEW_EMAC_ZMII is not set
765# CONFIG_IBM_NEW_EMAC_RGMII is not set
766# CONFIG_IBM_NEW_EMAC_TAH is not set
767# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
768# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
769# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
770# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
577# CONFIG_NET_PCI is not set 771# CONFIG_NET_PCI is not set
772CONFIG_B44=m
773CONFIG_B44_PCI_AUTOSELECT=y
774CONFIG_B44_PCICORE_AUTOSELECT=y
775CONFIG_B44_PCI=y
776CONFIG_KS8842=m
777CONFIG_KS8851_MLL=m
778CONFIG_ATL2=m
578CONFIG_NETDEV_1000=y 779CONFIG_NETDEV_1000=y
579# CONFIG_ACENIC is not set 780# CONFIG_ACENIC is not set
580# CONFIG_DL2K is not set 781# CONFIG_DL2K is not set
581# CONFIG_E1000 is not set 782# CONFIG_E1000 is not set
783CONFIG_E1000E=m
784CONFIG_IP1000=m
785CONFIG_IGB=m
786CONFIG_IGBVF=m
582# CONFIG_NS83820 is not set 787# CONFIG_NS83820 is not set
583# CONFIG_HAMACHI is not set 788# CONFIG_HAMACHI is not set
584# CONFIG_YELLOWFIN is not set 789# CONFIG_YELLOWFIN is not set
@@ -588,24 +793,75 @@ CONFIG_NETDEV_1000=y
588# CONFIG_SKY2 is not set 793# CONFIG_SKY2 is not set
589CONFIG_VIA_VELOCITY=m 794CONFIG_VIA_VELOCITY=m
590# CONFIG_TIGON3 is not set 795# CONFIG_TIGON3 is not set
591# CONFIG_BNX2 is not set 796CONFIG_BNX2=m
797CONFIG_CNIC=m
592CONFIG_QLA3XXX=m 798CONFIG_QLA3XXX=m
593# CONFIG_ATL1 is not set 799# CONFIG_ATL1 is not set
800CONFIG_ATL1E=m
801CONFIG_ATL1C=m
802CONFIG_JME=m
594CONFIG_NETDEV_10000=y 803CONFIG_NETDEV_10000=y
804CONFIG_MDIO=m
595# CONFIG_CHELSIO_T1 is not set 805# CONFIG_CHELSIO_T1 is not set
806CONFIG_CHELSIO_T3_DEPENDS=y
596CONFIG_CHELSIO_T3=m 807CONFIG_CHELSIO_T3=m
808CONFIG_ENIC=m
809CONFIG_IXGBE=m
597# CONFIG_IXGB is not set 810# CONFIG_IXGB is not set
598# CONFIG_S2IO is not set 811# CONFIG_S2IO is not set
812CONFIG_VXGE=m
813# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
599# CONFIG_MYRI10GE is not set 814# CONFIG_MYRI10GE is not set
600CONFIG_NETXEN_NIC=m 815CONFIG_NETXEN_NIC=m
601# CONFIG_MLX4_CORE is not set 816CONFIG_NIU=m
817CONFIG_MLX4_EN=m
818CONFIG_MLX4_CORE=m
819# CONFIG_MLX4_DEBUG is not set
820CONFIG_TEHUTI=m
821CONFIG_BNX2X=m
822CONFIG_QLGE=m
823CONFIG_SFC=m
824CONFIG_BE2NET=m
602# CONFIG_TR is not set 825# CONFIG_TR is not set
603 826CONFIG_WLAN=y
604# 827CONFIG_LIBERTAS_THINFIRM=m
605# Wireless LAN 828CONFIG_ATMEL=m
606# 829CONFIG_PCI_ATMEL=m
607# CONFIG_WLAN_PRE80211 is not set 830CONFIG_PRISM54=m
608CONFIG_WLAN_80211=y 831CONFIG_RTL8180=m
832CONFIG_ADM8211=m
833# CONFIG_MAC80211_HWSIM is not set
834CONFIG_MWL8K=m
835CONFIG_ATH_COMMON=m
836# CONFIG_ATH_DEBUG is not set
837CONFIG_ATH5K=m
838# CONFIG_ATH5K_DEBUG is not set
839CONFIG_ATH9K_HW=m
840CONFIG_ATH9K_COMMON=m
841CONFIG_ATH9K=m
842CONFIG_B43=m
843CONFIG_B43_PCI_AUTOSELECT=y
844CONFIG_B43_PCICORE_AUTOSELECT=y
845CONFIG_B43_PHY_LP=y
846CONFIG_B43_LEDS=y
847CONFIG_B43_HWRNG=y
848# CONFIG_B43_DEBUG is not set
849CONFIG_B43LEGACY=m
850CONFIG_B43LEGACY_PCI_AUTOSELECT=y
851CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
852CONFIG_B43LEGACY_LEDS=y
853CONFIG_B43LEGACY_HWRNG=y
854# CONFIG_B43LEGACY_DEBUG is not set
855CONFIG_B43LEGACY_DMA=y
856CONFIG_B43LEGACY_PIO=y
857CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
858# CONFIG_B43LEGACY_DMA_MODE is not set
859# CONFIG_B43LEGACY_PIO_MODE is not set
860CONFIG_HOSTAP=m
861CONFIG_HOSTAP_FIRMWARE=y
862CONFIG_HOSTAP_FIRMWARE_NVRAM=y
863CONFIG_HOSTAP_PLX=m
864CONFIG_HOSTAP_PCI=m
609CONFIG_IPW2100=m 865CONFIG_IPW2100=m
610CONFIG_IPW2100_MONITOR=y 866CONFIG_IPW2100_MONITOR=y
611CONFIG_IPW2100_DEBUG=y 867CONFIG_IPW2100_DEBUG=y
@@ -615,38 +871,57 @@ CONFIG_IPW2200_RADIOTAP=y
615CONFIG_IPW2200_PROMISCUOUS=y 871CONFIG_IPW2200_PROMISCUOUS=y
616CONFIG_IPW2200_QOS=y 872CONFIG_IPW2200_QOS=y
617CONFIG_IPW2200_DEBUG=y 873CONFIG_IPW2200_DEBUG=y
874CONFIG_LIBIPW=m
875# CONFIG_LIBIPW_DEBUG is not set
876CONFIG_IWLWIFI=m
877CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT=y
878# CONFIG_IWLWIFI_DEBUG is not set
879CONFIG_IWLAGN=m
880CONFIG_IWL4965=y
881CONFIG_IWL5000=y
882CONFIG_IWL3945=m
883CONFIG_IWL3945_SPECTRUM_MEASUREMENT=y
618CONFIG_LIBERTAS=m 884CONFIG_LIBERTAS=m
619# CONFIG_LIBERTAS_DEBUG is not set 885# CONFIG_LIBERTAS_DEBUG is not set
620CONFIG_HERMES=m 886CONFIG_HERMES=m
887# CONFIG_HERMES_CACHE_FW_ON_INIT is not set
621CONFIG_PLX_HERMES=m 888CONFIG_PLX_HERMES=m
622CONFIG_TMD_HERMES=m 889CONFIG_TMD_HERMES=m
623CONFIG_NORTEL_HERMES=m 890CONFIG_NORTEL_HERMES=m
624CONFIG_PCI_HERMES=m 891CONFIG_PCI_HERMES=m
625CONFIG_ATMEL=m 892CONFIG_P54_COMMON=m
626CONFIG_PCI_ATMEL=m 893CONFIG_P54_PCI=m
627CONFIG_PRISM54=m 894CONFIG_P54_LEDS=y
628CONFIG_HOSTAP=m 895CONFIG_RT2X00=m
629CONFIG_HOSTAP_FIRMWARE=y 896CONFIG_RT2400PCI=m
630CONFIG_HOSTAP_FIRMWARE_NVRAM=y 897CONFIG_RT2500PCI=m
631CONFIG_HOSTAP_PLX=m 898CONFIG_RT61PCI=m
632CONFIG_HOSTAP_PCI=m 899CONFIG_RT2800PCI_PCI=m
633CONFIG_BCM43XX=m 900CONFIG_RT2800PCI=m
634CONFIG_BCM43XX_DEBUG=y 901CONFIG_RT2800_LIB=m
635CONFIG_BCM43XX_DMA=y 902CONFIG_RT2X00_LIB_PCI=m
636CONFIG_BCM43XX_PIO=y 903CONFIG_RT2X00_LIB=m
637CONFIG_BCM43XX_DMA_AND_PIO_MODE=y 904CONFIG_RT2X00_LIB_HT=y
638# CONFIG_BCM43XX_DMA_MODE is not set 905CONFIG_RT2X00_LIB_FIRMWARE=y
639# CONFIG_BCM43XX_PIO_MODE is not set 906CONFIG_RT2X00_LIB_CRYPTO=y
907CONFIG_RT2X00_LIB_LEDS=y
908# CONFIG_RT2X00_DEBUG is not set
909CONFIG_WL12XX=m
910CONFIG_WL1251=m
911
912#
913# Enable WiMAX (Networking options) to see the WiMAX drivers
914#
640# CONFIG_WAN is not set 915# CONFIG_WAN is not set
641# CONFIG_FDDI is not set 916# CONFIG_FDDI is not set
642# CONFIG_HIPPI is not set 917# CONFIG_HIPPI is not set
643# CONFIG_PPP is not set 918# CONFIG_PPP is not set
644# CONFIG_SLIP is not set 919# CONFIG_SLIP is not set
645# CONFIG_NET_FC is not set 920# CONFIG_NET_FC is not set
646# CONFIG_SHAPER is not set
647# CONFIG_NETCONSOLE is not set 921# CONFIG_NETCONSOLE is not set
648# CONFIG_NETPOLL is not set 922# CONFIG_NETPOLL is not set
649# CONFIG_NET_POLL_CONTROLLER is not set 923# CONFIG_NET_POLL_CONTROLLER is not set
924# CONFIG_VMXNET3 is not set
650# CONFIG_ISDN is not set 925# CONFIG_ISDN is not set
651# CONFIG_PHONE is not set 926# CONFIG_PHONE is not set
652 927
@@ -664,13 +939,16 @@ CONFIG_SERIO_SERPORT=y
664# CONFIG_SERIO_PCIPS2 is not set 939# CONFIG_SERIO_PCIPS2 is not set
665CONFIG_SERIO_LIBPS2=m 940CONFIG_SERIO_LIBPS2=m
666CONFIG_SERIO_RAW=m 941CONFIG_SERIO_RAW=m
942CONFIG_SERIO_ALTERA_PS2=m
667# CONFIG_GAMEPORT is not set 943# CONFIG_GAMEPORT is not set
668 944
669# 945#
670# Character devices 946# Character devices
671# 947#
672# CONFIG_VT is not set 948# CONFIG_VT is not set
949CONFIG_DEVKMEM=y
673# CONFIG_SERIAL_NONSTANDARD is not set 950# CONFIG_SERIAL_NONSTANDARD is not set
951CONFIG_NOZOMI=m
674 952
675# 953#
676# Serial drivers 954# Serial drivers
@@ -693,95 +971,258 @@ CONFIG_SERIAL_CORE=y
693CONFIG_SERIAL_CORE_CONSOLE=y 971CONFIG_SERIAL_CORE_CONSOLE=y
694# CONFIG_SERIAL_JSM is not set 972# CONFIG_SERIAL_JSM is not set
695CONFIG_UNIX98_PTYS=y 973CONFIG_UNIX98_PTYS=y
974CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
696CONFIG_LEGACY_PTYS=y 975CONFIG_LEGACY_PTYS=y
697CONFIG_LEGACY_PTY_COUNT=256 976CONFIG_LEGACY_PTY_COUNT=256
698# CONFIG_IPMI_HANDLER is not set 977# CONFIG_IPMI_HANDLER is not set
699# CONFIG_WATCHDOG is not set
700CONFIG_HW_RANDOM=m 978CONFIG_HW_RANDOM=m
701# CONFIG_RTC is not set 979CONFIG_HW_RANDOM_TIMERIOMEM=m
702# CONFIG_R3964 is not set 980# CONFIG_R3964 is not set
703# CONFIG_APPLICOM is not set 981# CONFIG_APPLICOM is not set
704# CONFIG_DRM is not set
705# CONFIG_RAW_DRIVER is not set 982# CONFIG_RAW_DRIVER is not set
706# CONFIG_TCG_TPM is not set 983# CONFIG_TCG_TPM is not set
707CONFIG_DEVPORT=y 984CONFIG_DEVPORT=y
708# CONFIG_I2C is not set 985CONFIG_I2C=m
986CONFIG_I2C_BOARDINFO=y
987CONFIG_I2C_COMPAT=y
988CONFIG_I2C_CHARDEV=m
989CONFIG_I2C_HELPER_AUTO=y
990CONFIG_I2C_ALGOBIT=m
991CONFIG_I2C_ALGOPCA=m
992
993#
994# I2C Hardware Bus support
995#
996
997#
998# PC SMBus host controller drivers
999#
1000CONFIG_I2C_ALI1535=m
1001CONFIG_I2C_ALI1563=m
1002CONFIG_I2C_ALI15X3=m
1003CONFIG_I2C_AMD756=m
1004CONFIG_I2C_AMD8111=m
1005CONFIG_I2C_I801=m
1006CONFIG_I2C_ISCH=m
1007CONFIG_I2C_PIIX4=m
1008CONFIG_I2C_NFORCE2=m
1009CONFIG_I2C_SIS5595=m
1010CONFIG_I2C_SIS630=m
1011CONFIG_I2C_SIS96X=m
1012CONFIG_I2C_VIA=m
1013CONFIG_I2C_VIAPRO=m
709 1014
710# 1015#
711# SPI support 1016# I2C system bus drivers (mostly embedded / system-on-chip)
712# 1017#
1018CONFIG_I2C_OCORES=m
1019CONFIG_I2C_SIMTEC=m
1020
1021#
1022# External I2C/SMBus adapter drivers
1023#
1024CONFIG_I2C_PARPORT_LIGHT=m
1025CONFIG_I2C_TAOS_EVM=m
1026
1027#
1028# Other I2C/SMBus bus drivers
1029#
1030CONFIG_I2C_PCA_PLATFORM=m
1031CONFIG_I2C_STUB=m
1032
1033#
1034# Miscellaneous I2C Chip support
1035#
1036CONFIG_SENSORS_TSL2550=m
1037# CONFIG_I2C_DEBUG_CORE is not set
1038# CONFIG_I2C_DEBUG_ALGO is not set
1039# CONFIG_I2C_DEBUG_BUS is not set
1040# CONFIG_I2C_DEBUG_CHIP is not set
713# CONFIG_SPI is not set 1041# CONFIG_SPI is not set
714# CONFIG_SPI_MASTER is not set 1042
1043#
1044# PPS support
1045#
1046CONFIG_PPS=m
1047# CONFIG_PPS_DEBUG is not set
715# CONFIG_W1 is not set 1048# CONFIG_W1 is not set
716# CONFIG_POWER_SUPPLY is not set 1049# CONFIG_POWER_SUPPLY is not set
717# CONFIG_HWMON is not set 1050# CONFIG_HWMON is not set
1051CONFIG_THERMAL=m
1052# CONFIG_WATCHDOG is not set
1053CONFIG_SSB_POSSIBLE=y
718 1054
719# 1055#
720# Multifunction device drivers 1056# Sonics Silicon Backplane
721# 1057#
722# CONFIG_MFD_SM501 is not set 1058CONFIG_SSB=m
1059CONFIG_SSB_SPROM=y
1060CONFIG_SSB_PCIHOST_POSSIBLE=y
1061CONFIG_SSB_PCIHOST=y
1062CONFIG_SSB_B43_PCI_BRIDGE=y
1063# CONFIG_SSB_SILENT is not set
1064# CONFIG_SSB_DEBUG is not set
1065CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
1066CONFIG_SSB_DRIVER_PCICORE=y
1067# CONFIG_SSB_DRIVER_MIPS is not set
723 1068
724# 1069#
725# Multimedia devices 1070# Multifunction device drivers
726# 1071#
727# CONFIG_VIDEO_DEV is not set 1072# CONFIG_MFD_CORE is not set
728# CONFIG_DVB_CORE is not set 1073# CONFIG_MFD_SM501 is not set
729# CONFIG_DAB is not set 1074# CONFIG_HTC_PASIC3 is not set
1075# CONFIG_MFD_TMIO is not set
1076# CONFIG_MFD_WM8400 is not set
1077CONFIG_MFD_WM8350=m
1078CONFIG_MFD_WM8350_I2C=m
1079CONFIG_MFD_PCF50633=m
1080CONFIG_PCF50633_ADC=m
1081CONFIG_PCF50633_GPIO=m
1082CONFIG_AB3100_CORE=m
1083CONFIG_AB3100_OTP=m
1084# CONFIG_REGULATOR is not set
1085# CONFIG_MEDIA_SUPPORT is not set
730 1086
731# 1087#
732# Graphics support 1088# Graphics support
733# 1089#
734# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1090# CONFIG_VGA_ARB is not set
735 1091# CONFIG_DRM is not set
736#
737# Display device support
738#
739# CONFIG_DISPLAY_SUPPORT is not set
740# CONFIG_VGASTATE is not set 1092# CONFIG_VGASTATE is not set
741# CONFIG_VIDEO_OUTPUT_CONTROL is not set 1093# CONFIG_VIDEO_OUTPUT_CONTROL is not set
742# CONFIG_FB is not set 1094# CONFIG_FB is not set
1095# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
743 1096
744# 1097#
745# Sound 1098# Display device support
746# 1099#
1100# CONFIG_DISPLAY_SUPPORT is not set
747# CONFIG_SOUND is not set 1101# CONFIG_SOUND is not set
748CONFIG_USB_SUPPORT=y 1102CONFIG_USB_SUPPORT=y
749CONFIG_USB_ARCH_HAS_HCD=y 1103CONFIG_USB_ARCH_HAS_HCD=y
750CONFIG_USB_ARCH_HAS_OHCI=y 1104CONFIG_USB_ARCH_HAS_OHCI=y
751CONFIG_USB_ARCH_HAS_EHCI=y 1105CONFIG_USB_ARCH_HAS_EHCI=y
752# CONFIG_USB is not set 1106# CONFIG_USB is not set
1107# CONFIG_USB_OTG_WHITELIST is not set
1108# CONFIG_USB_OTG_BLACKLIST_HUB is not set
753 1109
754# 1110#
755# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1111# Enable Host or Gadget support to see Inventra options
756# 1112#
757 1113
758# 1114#
759# USB Gadget Support 1115# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
760# 1116#
761# CONFIG_USB_GADGET is not set 1117# CONFIG_USB_GADGET is not set
1118
1119#
1120# OTG and related infrastructure
1121#
1122# CONFIG_UWB is not set
762# CONFIG_MMC is not set 1123# CONFIG_MMC is not set
763# CONFIG_NEW_LEDS is not set 1124# CONFIG_MEMSTICK is not set
764# CONFIG_INFINIBAND is not set 1125CONFIG_NEW_LEDS=y
765# CONFIG_RTC_CLASS is not set 1126CONFIG_LEDS_CLASS=m
1127
1128#
1129# LED drivers
1130#
1131CONFIG_LEDS_LP3944=m
1132CONFIG_LEDS_PCA955X=m
1133CONFIG_LEDS_WM8350=m
1134CONFIG_LEDS_BD2802=m
1135
1136#
1137# LED Triggers
1138#
1139CONFIG_LEDS_TRIGGERS=y
1140CONFIG_LEDS_TRIGGER_TIMER=m
1141CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1142CONFIG_LEDS_TRIGGER_BACKLIGHT=m
1143CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
766 1144
767# 1145#
768# DMA Engine support 1146# iptables trigger is under Netfilter config (LED target)
769# 1147#
770# CONFIG_DMA_ENGINE is not set 1148# CONFIG_ACCESSIBILITY is not set
1149# CONFIG_INFINIBAND is not set
1150CONFIG_RTC_LIB=y
1151CONFIG_RTC_CLASS=y
1152CONFIG_RTC_HCTOSYS=y
1153CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1154# CONFIG_RTC_DEBUG is not set
771 1155
772# 1156#
773# DMA Clients 1157# RTC interfaces
774# 1158#
1159CONFIG_RTC_INTF_SYSFS=y
1160CONFIG_RTC_INTF_PROC=y
1161CONFIG_RTC_INTF_DEV=y
1162# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1163# CONFIG_RTC_DRV_TEST is not set
775 1164
776# 1165#
777# DMA Devices 1166# I2C RTC drivers
1167#
1168# CONFIG_RTC_DRV_DS1307 is not set
1169# CONFIG_RTC_DRV_DS1374 is not set
1170# CONFIG_RTC_DRV_DS1672 is not set
1171# CONFIG_RTC_DRV_MAX6900 is not set
1172# CONFIG_RTC_DRV_RS5C372 is not set
1173# CONFIG_RTC_DRV_ISL1208 is not set
1174# CONFIG_RTC_DRV_X1205 is not set
1175# CONFIG_RTC_DRV_PCF8563 is not set
1176# CONFIG_RTC_DRV_PCF8583 is not set
1177# CONFIG_RTC_DRV_M41T80 is not set
1178# CONFIG_RTC_DRV_BQ32K is not set
1179# CONFIG_RTC_DRV_S35390A is not set
1180# CONFIG_RTC_DRV_FM3130 is not set
1181# CONFIG_RTC_DRV_RX8581 is not set
1182# CONFIG_RTC_DRV_RX8025 is not set
1183
1184#
1185# SPI RTC drivers
1186#
1187
778# 1188#
1189# Platform RTC drivers
1190#
1191# CONFIG_RTC_DRV_CMOS is not set
1192# CONFIG_RTC_DRV_DS1286 is not set
1193# CONFIG_RTC_DRV_DS1511 is not set
1194# CONFIG_RTC_DRV_DS1553 is not set
1195# CONFIG_RTC_DRV_DS1742 is not set
1196# CONFIG_RTC_DRV_STK17TA8 is not set
1197# CONFIG_RTC_DRV_M48T86 is not set
1198CONFIG_RTC_DRV_M48T35=y
1199# CONFIG_RTC_DRV_M48T59 is not set
1200# CONFIG_RTC_DRV_MSM6242 is not set
1201# CONFIG_RTC_DRV_BQ4802 is not set
1202# CONFIG_RTC_DRV_RP5C01 is not set
1203# CONFIG_RTC_DRV_V3020 is not set
1204# CONFIG_RTC_DRV_WM8350 is not set
1205# CONFIG_RTC_DRV_PCF50633 is not set
1206CONFIG_RTC_DRV_AB3100=m
779 1207
780# 1208#
781# Userspace I/O 1209# on-CPU RTC drivers
782# 1210#
1211# CONFIG_DMADEVICES is not set
1212# CONFIG_AUXDISPLAY is not set
783CONFIG_UIO=y 1213CONFIG_UIO=y
784# CONFIG_UIO_CIF is not set 1214# CONFIG_UIO_CIF is not set
1215# CONFIG_UIO_PDRV is not set
1216# CONFIG_UIO_PDRV_GENIRQ is not set
1217CONFIG_UIO_SMX=m
1218CONFIG_UIO_AEC=m
1219CONFIG_UIO_SERCOS3=m
1220CONFIG_UIO_PCI_GENERIC=m
1221
1222#
1223# TI VLYNQ
1224#
1225# CONFIG_STAGING is not set
785 1226
786# 1227#
787# File systems 1228# File systems
@@ -792,36 +1233,58 @@ CONFIG_EXT2_FS_POSIX_ACL=y
792CONFIG_EXT2_FS_SECURITY=y 1233CONFIG_EXT2_FS_SECURITY=y
793# CONFIG_EXT2_FS_XIP is not set 1234# CONFIG_EXT2_FS_XIP is not set
794CONFIG_EXT3_FS=y 1235CONFIG_EXT3_FS=y
1236# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
795CONFIG_EXT3_FS_XATTR=y 1237CONFIG_EXT3_FS_XATTR=y
796CONFIG_EXT3_FS_POSIX_ACL=y 1238CONFIG_EXT3_FS_POSIX_ACL=y
797CONFIG_EXT3_FS_SECURITY=y 1239CONFIG_EXT3_FS_SECURITY=y
798# CONFIG_EXT4DEV_FS is not set 1240CONFIG_EXT4_FS=y
1241CONFIG_EXT4_FS_XATTR=y
1242CONFIG_EXT4_FS_POSIX_ACL=y
1243CONFIG_EXT4_FS_SECURITY=y
1244# CONFIG_EXT4_DEBUG is not set
799CONFIG_JBD=y 1245CONFIG_JBD=y
800CONFIG_JBD_DEBUG=y 1246CONFIG_JBD2=y
801CONFIG_FS_MBCACHE=y 1247CONFIG_FS_MBCACHE=y
802# CONFIG_REISERFS_FS is not set 1248# CONFIG_REISERFS_FS is not set
803# CONFIG_JFS_FS is not set 1249# CONFIG_JFS_FS is not set
804CONFIG_FS_POSIX_ACL=y 1250CONFIG_FS_POSIX_ACL=y
805CONFIG_XFS_FS=m 1251CONFIG_XFS_FS=m
806CONFIG_XFS_QUOTA=y 1252CONFIG_XFS_QUOTA=y
807CONFIG_XFS_SECURITY=y
808CONFIG_XFS_POSIX_ACL=y 1253CONFIG_XFS_POSIX_ACL=y
809# CONFIG_XFS_RT is not set 1254# CONFIG_XFS_RT is not set
1255# CONFIG_XFS_DEBUG is not set
810# CONFIG_GFS2_FS is not set 1256# CONFIG_GFS2_FS is not set
811# CONFIG_OCFS2_FS is not set 1257# CONFIG_OCFS2_FS is not set
812# CONFIG_MINIX_FS is not set 1258CONFIG_BTRFS_FS=m
813# CONFIG_ROMFS_FS is not set 1259CONFIG_BTRFS_FS_POSIX_ACL=y
1260# CONFIG_NILFS2_FS is not set
1261CONFIG_FILE_LOCKING=y
1262CONFIG_FSNOTIFY=y
1263CONFIG_DNOTIFY=y
814CONFIG_INOTIFY=y 1264CONFIG_INOTIFY=y
815CONFIG_INOTIFY_USER=y 1265CONFIG_INOTIFY_USER=y
816# CONFIG_QUOTA is not set 1266# CONFIG_QUOTA is not set
1267CONFIG_QUOTA_NETLINK_INTERFACE=y
817CONFIG_QUOTACTL=y 1268CONFIG_QUOTACTL=y
818CONFIG_DNOTIFY=y
819CONFIG_AUTOFS_FS=m 1269CONFIG_AUTOFS_FS=m
820# CONFIG_AUTOFS4_FS is not set 1270# CONFIG_AUTOFS4_FS is not set
821CONFIG_FUSE_FS=m 1271CONFIG_FUSE_FS=m
1272CONFIG_CUSE=m
822CONFIG_GENERIC_ACL=y 1273CONFIG_GENERIC_ACL=y
823 1274
824# 1275#
1276# Caches
1277#
1278CONFIG_FSCACHE=m
1279CONFIG_FSCACHE_STATS=y
1280# CONFIG_FSCACHE_HISTOGRAM is not set
1281# CONFIG_FSCACHE_DEBUG is not set
1282# CONFIG_FSCACHE_OBJECT_LIST is not set
1283CONFIG_CACHEFILES=m
1284# CONFIG_CACHEFILES_DEBUG is not set
1285# CONFIG_CACHEFILES_HISTOGRAM is not set
1286
1287#
825# CD-ROM/DVD Filesystems 1288# CD-ROM/DVD Filesystems
826# 1289#
827# CONFIG_ISO9660_FS is not set 1290# CONFIG_ISO9660_FS is not set
@@ -840,16 +1303,13 @@ CONFIG_GENERIC_ACL=y
840CONFIG_PROC_FS=y 1303CONFIG_PROC_FS=y
841CONFIG_PROC_KCORE=y 1304CONFIG_PROC_KCORE=y
842CONFIG_PROC_SYSCTL=y 1305CONFIG_PROC_SYSCTL=y
1306CONFIG_PROC_PAGE_MONITOR=y
843CONFIG_SYSFS=y 1307CONFIG_SYSFS=y
844CONFIG_TMPFS=y 1308CONFIG_TMPFS=y
845CONFIG_TMPFS_POSIX_ACL=y 1309CONFIG_TMPFS_POSIX_ACL=y
846# CONFIG_HUGETLB_PAGE is not set 1310# CONFIG_HUGETLB_PAGE is not set
847CONFIG_RAMFS=y
848CONFIG_CONFIGFS_FS=m 1311CONFIG_CONFIGFS_FS=m
849 1312CONFIG_MISC_FILESYSTEMS=y
850#
851# Miscellaneous filesystems
852#
853# CONFIG_ADFS_FS is not set 1313# CONFIG_ADFS_FS is not set
854# CONFIG_AFFS_FS is not set 1314# CONFIG_AFFS_FS is not set
855# CONFIG_ECRYPT_FS is not set 1315# CONFIG_ECRYPT_FS is not set
@@ -859,28 +1319,32 @@ CONFIG_CONFIGFS_FS=m
859# CONFIG_BFS_FS is not set 1319# CONFIG_BFS_FS is not set
860# CONFIG_EFS_FS is not set 1320# CONFIG_EFS_FS is not set
861# CONFIG_CRAMFS is not set 1321# CONFIG_CRAMFS is not set
1322CONFIG_SQUASHFS=m
1323# CONFIG_SQUASHFS_EMBEDDED is not set
1324CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
862# CONFIG_VXFS_FS is not set 1325# CONFIG_VXFS_FS is not set
1326# CONFIG_MINIX_FS is not set
1327CONFIG_OMFS_FS=m
863# CONFIG_HPFS_FS is not set 1328# CONFIG_HPFS_FS is not set
864# CONFIG_QNX4FS_FS is not set 1329# CONFIG_QNX4FS_FS is not set
1330# CONFIG_ROMFS_FS is not set
865# CONFIG_SYSV_FS is not set 1331# CONFIG_SYSV_FS is not set
866# CONFIG_UFS_FS is not set 1332# CONFIG_UFS_FS is not set
867 1333CONFIG_EXOFS_FS=m
868# 1334# CONFIG_EXOFS_DEBUG is not set
869# Network File Systems 1335CONFIG_NETWORK_FILESYSTEMS=y
870#
871CONFIG_NFS_FS=y 1336CONFIG_NFS_FS=y
872CONFIG_NFS_V3=y 1337CONFIG_NFS_V3=y
873# CONFIG_NFS_V3_ACL is not set 1338# CONFIG_NFS_V3_ACL is not set
874# CONFIG_NFS_V4 is not set 1339# CONFIG_NFS_V4 is not set
875# CONFIG_NFS_DIRECTIO is not set
876# CONFIG_NFSD is not set
877# CONFIG_ROOT_NFS is not set 1340# CONFIG_ROOT_NFS is not set
1341# CONFIG_NFSD is not set
878CONFIG_LOCKD=y 1342CONFIG_LOCKD=y
879CONFIG_LOCKD_V4=y 1343CONFIG_LOCKD_V4=y
1344CONFIG_EXPORTFS=m
880CONFIG_NFS_COMMON=y 1345CONFIG_NFS_COMMON=y
881CONFIG_SUNRPC=y 1346CONFIG_SUNRPC=y
882CONFIG_SUNRPC_GSS=y 1347CONFIG_SUNRPC_GSS=y
883# CONFIG_SUNRPC_BIND34 is not set
884CONFIG_RPCSEC_GSS_KRB5=y 1348CONFIG_RPCSEC_GSS_KRB5=y
885# CONFIG_RPCSEC_GSS_SPKM3 is not set 1349# CONFIG_RPCSEC_GSS_SPKM3 is not set
886# CONFIG_SMB_FS is not set 1350# CONFIG_SMB_FS is not set
@@ -910,35 +1374,37 @@ CONFIG_SGI_PARTITION=y
910# CONFIG_KARMA_PARTITION is not set 1374# CONFIG_KARMA_PARTITION is not set
911# CONFIG_EFI_PARTITION is not set 1375# CONFIG_EFI_PARTITION is not set
912# CONFIG_SYSV68_PARTITION is not set 1376# CONFIG_SYSV68_PARTITION is not set
913
914#
915# Native Language Support
916#
917# CONFIG_NLS is not set 1377# CONFIG_NLS is not set
918
919#
920# Distributed Lock Manager
921#
922CONFIG_DLM=m 1378CONFIG_DLM=m
923# CONFIG_DLM_DEBUG is not set 1379# CONFIG_DLM_DEBUG is not set
924 1380
925# 1381#
926# Profiling support
927#
928# CONFIG_PROFILING is not set
929
930#
931# Kernel hacking 1382# Kernel hacking
932# 1383#
933CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1384CONFIG_TRACE_IRQFLAGS_SUPPORT=y
934# CONFIG_PRINTK_TIME is not set 1385# CONFIG_PRINTK_TIME is not set
1386CONFIG_ENABLE_WARN_DEPRECATED=y
935CONFIG_ENABLE_MUST_CHECK=y 1387CONFIG_ENABLE_MUST_CHECK=y
1388CONFIG_FRAME_WARN=2048
936# CONFIG_MAGIC_SYSRQ is not set 1389# CONFIG_MAGIC_SYSRQ is not set
1390# CONFIG_STRIP_ASM_SYMS is not set
937# CONFIG_UNUSED_SYMBOLS is not set 1391# CONFIG_UNUSED_SYMBOLS is not set
938# CONFIG_DEBUG_FS is not set 1392# CONFIG_DEBUG_FS is not set
939# CONFIG_HEADERS_CHECK is not set 1393# CONFIG_HEADERS_CHECK is not set
940# CONFIG_DEBUG_KERNEL is not set 1394# CONFIG_DEBUG_KERNEL is not set
941CONFIG_CROSSCOMPILE=y 1395# CONFIG_DEBUG_MEMORY_INIT is not set
1396# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1397# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1398CONFIG_HAVE_FUNCTION_TRACER=y
1399CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1400CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1401CONFIG_HAVE_DYNAMIC_FTRACE=y
1402CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1403CONFIG_TRACING_SUPPORT=y
1404# CONFIG_FTRACE is not set
1405# CONFIG_SAMPLES is not set
1406CONFIG_HAVE_ARCH_KGDB=y
1407CONFIG_EARLY_PRINTK=y
942# CONFIG_CMDLINE_BOOL is not set 1408# CONFIG_CMDLINE_BOOL is not set
943 1409
944# 1410#
@@ -947,65 +1413,140 @@ CONFIG_CROSSCOMPILE=y
947CONFIG_KEYS=y 1413CONFIG_KEYS=y
948CONFIG_KEYS_DEBUG_PROC_KEYS=y 1414CONFIG_KEYS_DEBUG_PROC_KEYS=y
949# CONFIG_SECURITY is not set 1415# CONFIG_SECURITY is not set
950CONFIG_XOR_BLOCKS=m 1416CONFIG_SECURITYFS=y
951CONFIG_ASYNC_CORE=m 1417# CONFIG_DEFAULT_SECURITY_SELINUX is not set
952CONFIG_ASYNC_MEMCPY=m 1418# CONFIG_DEFAULT_SECURITY_SMACK is not set
953CONFIG_ASYNC_XOR=m 1419# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1420CONFIG_DEFAULT_SECURITY_DAC=y
1421CONFIG_DEFAULT_SECURITY=""
1422CONFIG_XOR_BLOCKS=y
1423CONFIG_ASYNC_CORE=y
1424CONFIG_ASYNC_MEMCPY=y
1425CONFIG_ASYNC_XOR=y
1426CONFIG_ASYNC_PQ=y
1427CONFIG_ASYNC_RAID6_RECOV=y
954CONFIG_CRYPTO=y 1428CONFIG_CRYPTO=y
1429
1430#
1431# Crypto core or helper
1432#
1433CONFIG_CRYPTO_FIPS=y
955CONFIG_CRYPTO_ALGAPI=y 1434CONFIG_CRYPTO_ALGAPI=y
956CONFIG_CRYPTO_ABLKCIPHER=m 1435CONFIG_CRYPTO_ALGAPI2=y
1436CONFIG_CRYPTO_AEAD=m
1437CONFIG_CRYPTO_AEAD2=y
957CONFIG_CRYPTO_BLKCIPHER=y 1438CONFIG_CRYPTO_BLKCIPHER=y
1439CONFIG_CRYPTO_BLKCIPHER2=y
958CONFIG_CRYPTO_HASH=y 1440CONFIG_CRYPTO_HASH=y
1441CONFIG_CRYPTO_HASH2=y
1442CONFIG_CRYPTO_RNG=m
1443CONFIG_CRYPTO_RNG2=y
1444CONFIG_CRYPTO_PCOMP=y
959CONFIG_CRYPTO_MANAGER=y 1445CONFIG_CRYPTO_MANAGER=y
1446CONFIG_CRYPTO_MANAGER2=y
1447CONFIG_CRYPTO_GF128MUL=m
1448CONFIG_CRYPTO_NULL=m
1449CONFIG_CRYPTO_WORKQUEUE=y
1450CONFIG_CRYPTO_CRYPTD=m
1451CONFIG_CRYPTO_AUTHENC=m
1452# CONFIG_CRYPTO_TEST is not set
1453
1454#
1455# Authenticated Encryption with Associated Data
1456#
1457CONFIG_CRYPTO_CCM=m
1458CONFIG_CRYPTO_GCM=m
1459CONFIG_CRYPTO_SEQIV=m
1460
1461#
1462# Block modes
1463#
1464CONFIG_CRYPTO_CBC=y
1465CONFIG_CRYPTO_CTR=m
1466CONFIG_CRYPTO_CTS=m
1467CONFIG_CRYPTO_ECB=m
1468CONFIG_CRYPTO_LRW=m
1469CONFIG_CRYPTO_PCBC=m
1470CONFIG_CRYPTO_XTS=m
1471
1472#
1473# Hash modes
1474#
960CONFIG_CRYPTO_HMAC=y 1475CONFIG_CRYPTO_HMAC=y
961CONFIG_CRYPTO_XCBC=m 1476CONFIG_CRYPTO_XCBC=m
962CONFIG_CRYPTO_NULL=m 1477CONFIG_CRYPTO_VMAC=m
1478
1479#
1480# Digest
1481#
1482CONFIG_CRYPTO_CRC32C=m
1483CONFIG_CRYPTO_GHASH=m
963CONFIG_CRYPTO_MD4=m 1484CONFIG_CRYPTO_MD4=m
964CONFIG_CRYPTO_MD5=y 1485CONFIG_CRYPTO_MD5=y
1486CONFIG_CRYPTO_MICHAEL_MIC=m
1487CONFIG_CRYPTO_RMD128=m
1488CONFIG_CRYPTO_RMD160=m
1489CONFIG_CRYPTO_RMD256=m
1490CONFIG_CRYPTO_RMD320=m
965CONFIG_CRYPTO_SHA1=m 1491CONFIG_CRYPTO_SHA1=m
966CONFIG_CRYPTO_SHA256=m 1492CONFIG_CRYPTO_SHA256=m
967CONFIG_CRYPTO_SHA512=m 1493CONFIG_CRYPTO_SHA512=m
968CONFIG_CRYPTO_WP512=m
969CONFIG_CRYPTO_TGR192=m 1494CONFIG_CRYPTO_TGR192=m
970CONFIG_CRYPTO_GF128MUL=m 1495CONFIG_CRYPTO_WP512=m
971CONFIG_CRYPTO_ECB=m 1496
972CONFIG_CRYPTO_CBC=y 1497#
973CONFIG_CRYPTO_PCBC=m 1498# Ciphers
974CONFIG_CRYPTO_LRW=m 1499#
975CONFIG_CRYPTO_CRYPTD=m
976CONFIG_CRYPTO_DES=y
977CONFIG_CRYPTO_FCRYPT=m
978CONFIG_CRYPTO_BLOWFISH=m
979CONFIG_CRYPTO_TWOFISH=m
980CONFIG_CRYPTO_TWOFISH_COMMON=m
981CONFIG_CRYPTO_SERPENT=m
982CONFIG_CRYPTO_AES=m 1500CONFIG_CRYPTO_AES=m
1501CONFIG_CRYPTO_ANUBIS=m
1502CONFIG_CRYPTO_ARC4=m
1503CONFIG_CRYPTO_BLOWFISH=m
1504CONFIG_CRYPTO_CAMELLIA=m
983CONFIG_CRYPTO_CAST5=m 1505CONFIG_CRYPTO_CAST5=m
984CONFIG_CRYPTO_CAST6=m 1506CONFIG_CRYPTO_CAST6=m
985CONFIG_CRYPTO_TEA=m 1507CONFIG_CRYPTO_DES=y
986CONFIG_CRYPTO_ARC4=m 1508CONFIG_CRYPTO_FCRYPT=m
987CONFIG_CRYPTO_KHAZAD=m 1509CONFIG_CRYPTO_KHAZAD=m
988CONFIG_CRYPTO_ANUBIS=m 1510CONFIG_CRYPTO_SALSA20=m
1511CONFIG_CRYPTO_SEED=m
1512CONFIG_CRYPTO_SERPENT=m
1513CONFIG_CRYPTO_TEA=m
1514CONFIG_CRYPTO_TWOFISH=m
1515CONFIG_CRYPTO_TWOFISH_COMMON=m
1516
1517#
1518# Compression
1519#
989CONFIG_CRYPTO_DEFLATE=m 1520CONFIG_CRYPTO_DEFLATE=m
990CONFIG_CRYPTO_MICHAEL_MIC=m 1521CONFIG_CRYPTO_ZLIB=m
991CONFIG_CRYPTO_CRC32C=m 1522CONFIG_CRYPTO_LZO=m
992CONFIG_CRYPTO_CAMELLIA=m 1523
993# CONFIG_CRYPTO_TEST is not set 1524#
1525# Random Number Generation
1526#
1527CONFIG_CRYPTO_ANSI_CPRNG=m
994CONFIG_CRYPTO_HW=y 1528CONFIG_CRYPTO_HW=y
1529CONFIG_CRYPTO_DEV_HIFN_795X=m
1530# CONFIG_CRYPTO_DEV_HIFN_795X_RNG is not set
1531# CONFIG_BINARY_PRINTF is not set
995 1532
996# 1533#
997# Library routines 1534# Library routines
998# 1535#
999CONFIG_BITREVERSE=y 1536CONFIG_BITREVERSE=y
1537CONFIG_GENERIC_FIND_LAST_BIT=y
1000CONFIG_CRC_CCITT=m 1538CONFIG_CRC_CCITT=m
1001# CONFIG_CRC16 is not set 1539CONFIG_CRC16=y
1002# CONFIG_CRC_ITU_T is not set 1540CONFIG_CRC_T10DIF=m
1541CONFIG_CRC_ITU_T=m
1003CONFIG_CRC32=y 1542CONFIG_CRC32=y
1004# CONFIG_CRC7 is not set 1543CONFIG_CRC7=m
1005CONFIG_LIBCRC32C=m 1544CONFIG_LIBCRC32C=m
1006CONFIG_ZLIB_INFLATE=m 1545CONFIG_ZLIB_INFLATE=m
1007CONFIG_ZLIB_DEFLATE=m 1546CONFIG_ZLIB_DEFLATE=m
1008CONFIG_PLIST=y 1547CONFIG_LZO_COMPRESS=m
1548CONFIG_LZO_DECOMPRESS=m
1009CONFIG_HAS_IOMEM=y 1549CONFIG_HAS_IOMEM=y
1010CONFIG_HAS_IOPORT=y 1550CONFIG_HAS_IOPORT=y
1011CONFIG_HAS_DMA=y 1551CONFIG_HAS_DMA=y
1552CONFIG_NLATTR=y
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 9c187a64649b..758ad426c57f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -287,9 +287,9 @@ static inline int __cpu_has_fpu(void)
287static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 287static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
288{ 288{
289#ifdef __NEED_VMBITS_PROBE 289#ifdef __NEED_VMBITS_PROBE
290 write_c0_entryhi(0x3ffffffffffff000ULL); 290 write_c0_entryhi(0x3fffffffffffe000ULL);
291 back_to_back_c0_hazard(); 291 back_to_back_c0_hazard();
292 c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); 292 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
293#endif 293#endif
294} 294}
295 295
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 338dfe8ed002..31b204b26ba0 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1501,6 +1501,7 @@ void __cpuinit per_cpu_trap_init(void)
1501 cp0_perfcount_irq = -1; 1501 cp0_perfcount_irq = -1;
1502 } else { 1502 } else {
1503 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1503 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1504 cp0_compare_irq_shift = cp0_compare_irq;
1504 cp0_perfcount_irq = -1; 1505 cp0_perfcount_irq = -1;
1505 } 1506 }
1506 1507
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 94e05e5733c1..e06f1af760a7 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
174 * Probe Octeon's caches 174 * Probe Octeon's caches
175 * 175 *
176 */ 176 */
177static void __devinit probe_octeon(void) 177static void __cpuinit probe_octeon(void)
178{ 178{
179 unsigned long icache_size; 179 unsigned long icache_size;
180 unsigned long dcache_size; 180 unsigned long dcache_size;
@@ -235,7 +235,7 @@ static void __devinit probe_octeon(void)
235 * Setup the Octeon cache flush routines 235 * Setup the Octeon cache flush routines
236 * 236 *
237 */ 237 */
238void __devinit octeon_cache_init(void) 238void __cpuinit octeon_cache_init(void)
239{ 239{
240 extern unsigned long ebase; 240 extern unsigned long ebase;
241 extern char except_vec2_octeon; 241 extern char except_vec2_octeon;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 102b2dfa542a..e716cafc346d 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -155,7 +155,7 @@ static inline void setup_protection_map(void)
155 protection_map[15] = PAGE_SHARED; 155 protection_map[15] = PAGE_SHARED;
156} 156}
157 157
158void __devinit cpu_cache_init(void) 158void __cpuinit cpu_cache_init(void)
159{ 159{
160 if (cpu_has_3k_cache) { 160 if (cpu_has_3k_cache) {
161 extern void __weak r3k_cache_init(void); 161 extern void __weak r3k_cache_init(void);
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index e274fda329f4..127d732474bf 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -1,5 +1,6 @@
1#include <linux/module.h> 1#include <linux/module.h>
2#include <linux/highmem.h> 2#include <linux/highmem.h>
3#include <linux/sched.h>
3#include <linux/smp.h> 4#include <linux/smp.h>
4#include <asm/fixmap.h> 5#include <asm/fixmap.h>
5#include <asm/tlbflush.h> 6#include <asm/tlbflush.h>
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 46f00691f448..31e2583ec622 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -404,7 +404,7 @@ void __init sni_rm200_i8259_irqs(void)
404 if (!rm200_pic_master) 404 if (!rm200_pic_master)
405 return; 405 return;
406 rm200_pic_slave = ioremap_nocache(0x160000a0, 4); 406 rm200_pic_slave = ioremap_nocache(0x160000a0, 4);
407 if (!rm200_pic_master) { 407 if (!rm200_pic_slave) {
408 iounmap(rm200_pic_master); 408 iounmap(rm200_pic_master);
409 return; 409 return;
410 } 410 }
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 524d9352f17e..f388dc68f605 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -18,7 +18,6 @@ config PARISC
18 select BUG 18 select BUG
19 select HAVE_PERF_EVENTS 19 select HAVE_PERF_EVENTS
20 select GENERIC_ATOMIC64 if !64BIT 20 select GENERIC_ATOMIC64 if !64BIT
21 select HAVE_ARCH_TRACEHOOK
22 help 21 help
23 The PA-RISC microprocessor is designed by Hewlett-Packard and used 22 The PA-RISC microprocessor is designed by Hewlett-Packard and used
24 in many of their workstations & servers (HP9000 700 and 800 series, 23 in many of their workstations & servers (HP9000 700 and 800 series,
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index f7064abc3bb6..9e74bfe071dc 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -18,7 +18,6 @@
18 18
19#include <asm/io.h> 19#include <asm/io.h>
20#include <asm/system.h> 20#include <asm/system.h>
21#include <asm/cache.h> /* for L1_CACHE_BYTES */
22#include <asm/superio.h> 21#include <asm/superio.h>
23 22
24#define DEBUG_RESOURCES 0 23#define DEBUG_RESOURCES 0
@@ -123,6 +122,10 @@ static int __init pcibios_init(void)
123 } else { 122 } else {
124 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 123 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
125 } 124 }
125
126 /* Set the CLS for PCI as early as possible. */
127 pci_cache_line_size = pci_dfl_cache_line_size;
128
126 return 0; 129 return 0;
127} 130}
128 131
@@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev)
171 ** upper byte is PCI_LATENCY_TIMER. 174 ** upper byte is PCI_LATENCY_TIMER.
172 */ 175 */
173 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 176 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
174 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); 177 (0x80 << 8) | pci_cache_line_size);
175} 178}
176 179
177 180
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index fb37ac52e46c..35c827e94e31 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -468,7 +468,9 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
468 recalc_sigpending(); 468 recalc_sigpending();
469 spin_unlock_irq(&current->sighand->siglock); 469 spin_unlock_irq(&current->sighand->siglock);
470 470
471 tracehook_signal_handler(sig, info, ka, regs, 0); 471 tracehook_signal_handler(sig, info, ka, regs,
472 test_thread_flag(TIF_SINGLESTEP) ||
473 test_thread_flag(TIF_BLOCKSTEP));
472 474
473 return 1; 475 return 1;
474} 476}
diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c
index a3c11cac3d71..95ad9dad298e 100644
--- a/arch/powerpc/kernel/perf_callchain.c
+++ b/arch/powerpc/kernel/perf_callchain.c
@@ -495,9 +495,6 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
495 495
496 entry->nr = 0; 496 entry->nr = 0;
497 497
498 if (current->pid == 0) /* idle task? */
499 return entry;
500
501 if (!user_mode(regs)) { 498 if (!user_mode(regs)) {
502 perf_callchain_kernel(regs, entry); 499 perf_callchain_kernel(regs, entry);
503 if (current->mm) 500 if (current->mm)
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 1eb85fbf53a5..b6cf8f1f4d35 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -718,10 +718,10 @@ static int collect_events(struct perf_event *group, int max_count,
718 return n; 718 return n;
719} 719}
720 720
721static void event_sched_in(struct perf_event *event, int cpu) 721static void event_sched_in(struct perf_event *event)
722{ 722{
723 event->state = PERF_EVENT_STATE_ACTIVE; 723 event->state = PERF_EVENT_STATE_ACTIVE;
724 event->oncpu = cpu; 724 event->oncpu = smp_processor_id();
725 event->tstamp_running += event->ctx->time - event->tstamp_stopped; 725 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
726 if (is_software_event(event)) 726 if (is_software_event(event))
727 event->pmu->enable(event); 727 event->pmu->enable(event);
@@ -735,7 +735,7 @@ static void event_sched_in(struct perf_event *event, int cpu)
735 */ 735 */
736int hw_perf_group_sched_in(struct perf_event *group_leader, 736int hw_perf_group_sched_in(struct perf_event *group_leader,
737 struct perf_cpu_context *cpuctx, 737 struct perf_cpu_context *cpuctx,
738 struct perf_event_context *ctx, int cpu) 738 struct perf_event_context *ctx)
739{ 739{
740 struct cpu_hw_events *cpuhw; 740 struct cpu_hw_events *cpuhw;
741 long i, n, n0; 741 long i, n, n0;
@@ -766,10 +766,10 @@ int hw_perf_group_sched_in(struct perf_event *group_leader,
766 cpuhw->event[i]->hw.config = cpuhw->events[i]; 766 cpuhw->event[i]->hw.config = cpuhw->events[i];
767 cpuctx->active_oncpu += n; 767 cpuctx->active_oncpu += n;
768 n = 1; 768 n = 1;
769 event_sched_in(group_leader, cpu); 769 event_sched_in(group_leader);
770 list_for_each_entry(sub, &group_leader->sibling_list, group_entry) { 770 list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
771 if (sub->state != PERF_EVENT_STATE_OFF) { 771 if (sub->state != PERF_EVENT_STATE_OFF) {
772 event_sched_in(sub, cpu); 772 event_sched_in(sub);
773 ++n; 773 ++n;
774 } 774 }
775 } 775 }
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 282d9306361f..1ec06576f619 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -63,15 +63,21 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
63 if (huge) { 63 if (huge) {
64#ifdef CONFIG_HUGETLB_PAGE 64#ifdef CONFIG_HUGETLB_PAGE
65 psize = get_slice_psize(mm, addr); 65 psize = get_slice_psize(mm, addr);
66 /* Mask the address for the correct page size */
67 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
66#else 68#else
67 BUG(); 69 BUG();
68 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */ 70 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
69#endif 71#endif
70 } else 72 } else {
71 psize = pte_pagesize_index(mm, addr, pte); 73 psize = pte_pagesize_index(mm, addr, pte);
74 /* Mask the address for the standard page size. If we
75 * have a 64k page kernel, but the hardware does not
76 * support 64k pages, this might be different from the
77 * hardware page size encoded in the slice table. */
78 addr &= PAGE_MASK;
79 }
72 80
73 /* Mask the address for the correct page size */
74 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
75 81
76 /* Build full vaddr */ 82 /* Build full vaddr */
77 if (!is_kernel_addr(addr)) { 83 if (!is_kernel_addr(addr)) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 21f61b8c445b..cc29c0f5300d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -338,7 +338,8 @@ static void __init mpc85xx_mds_pic_init(void)
338 } 338 }
339 339
340 mpic = mpic_alloc(np, r.start, 340 mpic = mpic_alloc(np, r.start,
341 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 341 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
342 MPIC_BROKEN_FRR_NIRQS,
342 0, 256, " OpenPIC "); 343 0, 256, " OpenPIC ");
343 BUG_ON(mpic == NULL); 344 BUG_ON(mpic == NULL);
344 of_node_put(np); 345 of_node_put(np);
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 04160a4cc699..a15f582300d8 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -46,6 +46,7 @@ smp_85xx_kick_cpu(int nr)
46 __iomem u32 *bptr_vaddr; 46 __iomem u32 *bptr_vaddr;
47 struct device_node *np; 47 struct device_node *np;
48 int n = 0; 48 int n = 0;
49 int ioremappable;
49 50
50 WARN_ON (nr < 0 || nr >= NR_CPUS); 51 WARN_ON (nr < 0 || nr >= NR_CPUS);
51 52
@@ -59,21 +60,37 @@ smp_85xx_kick_cpu(int nr)
59 return; 60 return;
60 } 61 }
61 62
63 /*
64 * A secondary core could be in a spinloop in the bootpage
65 * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
66 * The bootpage and highmem can be accessed via ioremap(), but
67 * we need to directly access the spinloop if its in lowmem.
68 */
69 ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
70
62 /* Map the spin table */ 71 /* Map the spin table */
63 bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); 72 if (ioremappable)
73 bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
74 else
75 bptr_vaddr = phys_to_virt(*cpu_rel_addr);
64 76
65 local_irq_save(flags); 77 local_irq_save(flags);
66 78
67 out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); 79 out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr);
68 out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); 80 out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
69 81
82 if (!ioremappable)
83 flush_dcache_range((ulong)bptr_vaddr,
84 (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
85
70 /* Wait a bit for the CPU to ack. */ 86 /* Wait a bit for the CPU to ack. */
71 while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) 87 while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
72 mdelay(1); 88 mdelay(1);
73 89
74 local_irq_restore(flags); 90 local_irq_restore(flags);
75 91
76 iounmap(bptr_vaddr); 92 if (ioremappable)
93 iounmap(bptr_vaddr);
77 94
78 pr_debug("waited %d msecs for CPU #%d.\n", n, nr); 95 pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
79} 96}
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index 1ee66db003be..f5f79196721c 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -784,9 +784,13 @@ static void xics_set_cpu_priority(unsigned char cppr)
784{ 784{
785 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); 785 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
786 786
787 BUG_ON(os_cppr->index != 0); 787 /*
788 * we only really want to set the priority when there's
789 * just one cppr value on the stack
790 */
791 WARN_ON(os_cppr->index != 0);
788 792
789 os_cppr->stack[os_cppr->index] = cppr; 793 os_cppr->stack[0] = cppr;
790 794
791 if (firmware_has_feature(FW_FEATURE_LPAR)) 795 if (firmware_has_feature(FW_FEATURE_LPAR))
792 lpar_cppr_info(cppr); 796 lpar_cppr_info(cppr);
@@ -821,8 +825,14 @@ void xics_setup_cpu(void)
821 825
822void xics_teardown_cpu(void) 826void xics_teardown_cpu(void)
823{ 827{
828 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
824 int cpu = smp_processor_id(); 829 int cpu = smp_processor_id();
825 830
831 /*
832 * we have to reset the cppr index to 0 because we're
833 * not going to return from the IPI
834 */
835 os_cppr->index = 0;
826 xics_set_cpu_priority(0); 836 xics_set_cpu_priority(0);
827 837
828 /* Clear any pending IPI request */ 838 /* Clear any pending IPI request */
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index f2ef4b619ce1..c25dfac7dd76 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -293,12 +293,12 @@ struct _lowcore
293 __u64 clock_comparator; /* 0x02d0 */ 293 __u64 clock_comparator; /* 0x02d0 */
294 __u32 machine_flags; /* 0x02d8 */ 294 __u32 machine_flags; /* 0x02d8 */
295 __u32 ftrace_func; /* 0x02dc */ 295 __u32 ftrace_func; /* 0x02dc */
296 __u8 pad_0x02f0[0x0300-0x02f0]; /* 0x02f0 */ 296 __u8 pad_0x02e0[0x0300-0x02e0]; /* 0x02e0 */
297 297
298 /* Interrupt response block */ 298 /* Interrupt response block */
299 __u8 irb[64]; /* 0x0300 */ 299 __u8 irb[64]; /* 0x0300 */
300 300
301 __u8 pad_0x0400[0x0e00-0x0400]; /* 0x0400 */ 301 __u8 pad_0x0340[0x0e00-0x0340]; /* 0x0340 */
302 302
303 /* 303 /*
304 * 0xe00 contains the address of the IPL Parameter Information 304 * 0xe00 contains the address of the IPL Parameter Information
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 3f7e2a22c7c2..f6a389c996cb 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -132,7 +132,6 @@ ENTRY(tlb_protection_violation_store)
132 mov #1, r5 132 mov #1, r5
133 133
134call_handle_tlbmiss: 134call_handle_tlbmiss:
135 setup_frame_reg
136 mov.l 1f, r0 135 mov.l 1f, r0
137 mov r5, r8 136 mov r5, r8
138 mov.l @r0, r6 137 mov.l @r0, r6
@@ -365,6 +364,8 @@ handle_exception:
365 mov.l @k2, k2 ! read out vector and keep in k2 364 mov.l @k2, k2 ! read out vector and keep in k2
366 365
367handle_exception_special: 366handle_exception_special:
367 setup_frame_reg
368
368 ! Setup return address and jump to exception handler 369 ! Setup return address and jump to exception handler
369 mov.l 7f, r9 ! fetch return address 370 mov.l 7f, r9 ! fetch return address
370 stc r2_bank, r0 ! k2 (vector) 371 stc r2_bank, r0 ! k2 (vector)
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index 88d28ec3780a..e51168064e56 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -540,6 +540,8 @@ void dwarf_free_frame(struct dwarf_frame *frame)
540 mempool_free(frame, dwarf_frame_pool); 540 mempool_free(frame, dwarf_frame_pool);
541} 541}
542 542
543extern void ret_from_irq(void);
544
543/** 545/**
544 * dwarf_unwind_stack - unwind the stack 546 * dwarf_unwind_stack - unwind the stack
545 * 547 *
@@ -678,6 +680,24 @@ struct dwarf_frame * dwarf_unwind_stack(unsigned long pc,
678 addr = frame->cfa + reg->addr; 680 addr = frame->cfa + reg->addr;
679 frame->return_addr = __raw_readl(addr); 681 frame->return_addr = __raw_readl(addr);
680 682
683 /*
684 * Ah, the joys of unwinding through interrupts.
685 *
686 * Interrupts are tricky - the DWARF info needs to be _really_
687 * accurate and unfortunately I'm seeing a lot of bogus DWARF
688 * info. For example, I've seen interrupts occur in epilogues
689 * just after the frame pointer (r14) had been restored. The
690 * problem was that the DWARF info claimed that the CFA could be
691 * reached by using the value of the frame pointer before it was
692 * restored.
693 *
694 * So until the compiler can be trusted to produce reliable
695 * DWARF info when it really matters, let's stop unwinding once
696 * we've calculated the function that was interrupted.
697 */
698 if (prev && prev->pc == (unsigned long)ret_from_irq)
699 frame->return_addr = 0;
700
681 return frame; 701 return frame;
682 702
683bail: 703bail:
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index f0abd58c3a69..2b15ae60c3a0 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -70,8 +70,14 @@ ret_from_exception:
70 CFI_STARTPROC simple 70 CFI_STARTPROC simple
71 CFI_DEF_CFA r14, 0 71 CFI_DEF_CFA r14, 0
72 CFI_REL_OFFSET 17, 64 72 CFI_REL_OFFSET 17, 64
73 CFI_REL_OFFSET 15, 0 73 CFI_REL_OFFSET 15, 60
74 CFI_REL_OFFSET 14, 56 74 CFI_REL_OFFSET 14, 56
75 CFI_REL_OFFSET 13, 52
76 CFI_REL_OFFSET 12, 48
77 CFI_REL_OFFSET 11, 44
78 CFI_REL_OFFSET 10, 40
79 CFI_REL_OFFSET 9, 36
80 CFI_REL_OFFSET 8, 32
75 preempt_stop() 81 preempt_stop()
76ENTRY(ret_from_irq) 82ENTRY(ret_from_irq)
77 ! 83 !
diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c
index 24ea837eac5b..a9dd3abde28e 100644
--- a/arch/sh/kernel/perf_callchain.c
+++ b/arch/sh/kernel/perf_callchain.c
@@ -68,9 +68,6 @@ perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
68 68
69 is_user = user_mode(regs); 69 is_user = user_mode(regs);
70 70
71 if (!current || current->pid == 0)
72 return;
73
74 if (is_user && current->state != TASK_RUNNING) 71 if (is_user && current->state != TASK_RUNNING)
75 return; 72 return;
76 73
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 873ebdc4f98e..b063eb8b18e3 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -133,6 +133,8 @@ void user_enable_single_step(struct task_struct *child)
133 struct pt_regs *regs = child->thread.uregs; 133 struct pt_regs *regs = child->thread.uregs;
134 134
135 regs->sr |= SR_SSTEP; /* auto-resetting upon exception */ 135 regs->sr |= SR_SSTEP; /* auto-resetting upon exception */
136
137 set_tsk_thread_flag(child, TIF_SINGLESTEP);
136} 138}
137 139
138void user_disable_single_step(struct task_struct *child) 140void user_disable_single_step(struct task_struct *child)
@@ -140,6 +142,8 @@ void user_disable_single_step(struct task_struct *child)
140 struct pt_regs *regs = child->thread.uregs; 142 struct pt_regs *regs = child->thread.uregs;
141 143
142 regs->sr &= ~SR_SSTEP; 144 regs->sr &= ~SR_SSTEP;
145
146 clear_tsk_thread_flag(child, TIF_SINGLESTEP);
143} 147}
144 148
145static int genregs_get(struct task_struct *target, 149static int genregs_get(struct task_struct *target,
@@ -454,6 +458,8 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs)
454 458
455asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) 459asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
456{ 460{
461 int step;
462
457 if (unlikely(current->audit_context)) 463 if (unlikely(current->audit_context))
458 audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]), 464 audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]),
459 regs->regs[9]); 465 regs->regs[9]);
@@ -461,8 +467,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
461 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) 467 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
462 trace_sys_exit(regs, regs->regs[9]); 468 trace_sys_exit(regs, regs->regs[9]);
463 469
464 if (test_thread_flag(TIF_SYSCALL_TRACE)) 470 step = test_thread_flag(TIF_SINGLESTEP);
465 tracehook_report_syscall_exit(regs, 0); 471 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
472 tracehook_report_syscall_exit(regs, step);
466} 473}
467 474
468/* Called with interrupts disabled */ 475/* Called with interrupts disabled */
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index ce76dbdef294..580e97d46ca5 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -118,7 +118,9 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
118 * clear the TS_RESTORE_SIGMASK flag. 118 * clear the TS_RESTORE_SIGMASK flag.
119 */ 119 */
120 current_thread_info()->status &= ~TS_RESTORE_SIGMASK; 120 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
121 tracehook_signal_handler(signr, &info, &ka, regs, 0); 121
122 tracehook_signal_handler(signr, &info, &ka, regs,
123 test_thread_flag(TIF_SINGLESTEP));
122 return 1; 124 return 1;
123 } 125 }
124 } 126 }
diff --git a/arch/sparc/include/asm/stat.h b/arch/sparc/include/asm/stat.h
index 55db5eca08e2..39327d6a57eb 100644
--- a/arch/sparc/include/asm/stat.h
+++ b/arch/sparc/include/asm/stat.h
@@ -53,8 +53,8 @@ struct stat {
53 ino_t st_ino; 53 ino_t st_ino;
54 mode_t st_mode; 54 mode_t st_mode;
55 short st_nlink; 55 short st_nlink;
56 uid_t st_uid; 56 uid16_t st_uid;
57 gid_t st_gid; 57 gid16_t st_gid;
58 unsigned short st_rdev; 58 unsigned short st_rdev;
59 off_t st_size; 59 off_t st_size;
60 time_t st_atime; 60 time_t st_atime;
diff --git a/arch/sparc/kernel/kstack.h b/arch/sparc/kernel/kstack.h
index 4248d969272f..5247283d1c03 100644
--- a/arch/sparc/kernel/kstack.h
+++ b/arch/sparc/kernel/kstack.h
@@ -11,6 +11,10 @@ static inline bool kstack_valid(struct thread_info *tp, unsigned long sp)
11{ 11{
12 unsigned long base = (unsigned long) tp; 12 unsigned long base = (unsigned long) tp;
13 13
14 /* Stack pointer must be 16-byte aligned. */
15 if (sp & (16UL - 1))
16 return false;
17
14 if (sp >= (base + sizeof(struct thread_info)) && 18 if (sp >= (base + sizeof(struct thread_info)) &&
15 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) 19 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
16 return true; 20 return true;
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index 4c26eb59e742..53a58b349849 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -105,7 +105,7 @@ static unsigned long of_bus_sbus_get_flags(const u32 *addr, unsigned long flags)
105 105
106static int of_bus_ambapp_match(struct device_node *np) 106static int of_bus_ambapp_match(struct device_node *np)
107{ 107{
108 return !strcmp(np->name, "ambapp"); 108 return !strcmp(np->type, "ambapp");
109} 109}
110 110
111static void of_bus_ambapp_count_cells(struct device_node *child, 111static void of_bus_ambapp_count_cells(struct device_node *child,
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 539e83f8e087..592b03d85167 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -247,6 +247,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 struct pci_bus *bus, int devfn) 247 struct pci_bus *bus, int devfn)
248{ 248{
249 struct dev_archdata *sd; 249 struct dev_archdata *sd;
250 struct pci_slot *slot;
250 struct of_device *op; 251 struct of_device *op;
251 struct pci_dev *dev; 252 struct pci_dev *dev;
252 const char *type; 253 const char *type;
@@ -286,6 +287,11 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
286 dev->dev.bus = &pci_bus_type; 287 dev->dev.bus = &pci_bus_type;
287 dev->devfn = devfn; 288 dev->devfn = devfn;
288 dev->multifunction = 0; /* maybe a lie? */ 289 dev->multifunction = 0; /* maybe a lie? */
290 set_pcie_port_type(dev);
291
292 list_for_each_entry(slot, &dev->bus->slots, list)
293 if (PCI_SLOT(dev->devfn) == slot->number)
294 dev->slot = slot;
289 295
290 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 296 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
291 dev->device = of_getintprop_default(node, "device-id", 0xffff); 297 dev->device = of_getintprop_default(node, "device-id", 0xffff);
@@ -322,6 +328,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
322 328
323 dev->current_state = 4; /* unknown power state */ 329 dev->current_state = 4; /* unknown power state */
324 dev->error_state = pci_channel_io_normal; 330 dev->error_state = pci_channel_io_normal;
331 dev->dma_mask = 0xffffffff;
325 332
326 if (!strcmp(node->name, "pci")) { 333 if (!strcmp(node->name, "pci")) {
327 /* a PCI-PCI bridge */ 334 /* a PCI-PCI bridge */
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index e856456ec02f..9f2b2bac8b2b 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -980,10 +980,10 @@ static int collect_events(struct perf_event *group, int max_count,
980 return n; 980 return n;
981} 981}
982 982
983static void event_sched_in(struct perf_event *event, int cpu) 983static void event_sched_in(struct perf_event *event)
984{ 984{
985 event->state = PERF_EVENT_STATE_ACTIVE; 985 event->state = PERF_EVENT_STATE_ACTIVE;
986 event->oncpu = cpu; 986 event->oncpu = smp_processor_id();
987 event->tstamp_running += event->ctx->time - event->tstamp_stopped; 987 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
988 if (is_software_event(event)) 988 if (is_software_event(event))
989 event->pmu->enable(event); 989 event->pmu->enable(event);
@@ -991,7 +991,7 @@ static void event_sched_in(struct perf_event *event, int cpu)
991 991
992int hw_perf_group_sched_in(struct perf_event *group_leader, 992int hw_perf_group_sched_in(struct perf_event *group_leader,
993 struct perf_cpu_context *cpuctx, 993 struct perf_cpu_context *cpuctx,
994 struct perf_event_context *ctx, int cpu) 994 struct perf_event_context *ctx)
995{ 995{
996 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 996 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
997 struct perf_event *sub; 997 struct perf_event *sub;
@@ -1015,10 +1015,10 @@ int hw_perf_group_sched_in(struct perf_event *group_leader,
1015 1015
1016 cpuctx->active_oncpu += n; 1016 cpuctx->active_oncpu += n;
1017 n = 1; 1017 n = 1;
1018 event_sched_in(group_leader, cpu); 1018 event_sched_in(group_leader);
1019 list_for_each_entry(sub, &group_leader->sibling_list, group_entry) { 1019 list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
1020 if (sub->state != PERF_EVENT_STATE_OFF) { 1020 if (sub->state != PERF_EVENT_STATE_OFF) {
1021 event_sched_in(sub, cpu); 1021 event_sched_in(sub);
1022 n++; 1022 n++;
1023 } 1023 }
1024 } 1024 }
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index 2830b415e214..c49865b30719 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -526,7 +526,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
526 * Set some valid stack frames to give to the child. 526 * Set some valid stack frames to give to the child.
527 */ 527 */
528 childstack = (struct sparc_stackf __user *) 528 childstack = (struct sparc_stackf __user *)
529 (sp & ~0x7UL); 529 (sp & ~0xfUL);
530 parentstack = (struct sparc_stackf __user *) 530 parentstack = (struct sparc_stackf __user *)
531 regs->u_regs[UREG_FP]; 531 regs->u_regs[UREG_FP];
532 532
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index c3f1cce0e95e..cb70476bd8f5 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -398,11 +398,11 @@ static unsigned long clone_stackframe(unsigned long csp, unsigned long psp)
398 } else 398 } else
399 __get_user(fp, &(((struct reg_window32 __user *)psp)->ins[6])); 399 __get_user(fp, &(((struct reg_window32 __user *)psp)->ins[6]));
400 400
401 /* Now 8-byte align the stack as this is mandatory in the 401 /* Now align the stack as this is mandatory in the Sparc ABI
402 * Sparc ABI due to how register windows work. This hides 402 * due to how register windows work. This hides the
403 * the restriction from thread libraries etc. -DaveM 403 * restriction from thread libraries etc.
404 */ 404 */
405 csp &= ~7UL; 405 csp &= ~15UL;
406 406
407 distance = fp - psp; 407 distance = fp - psp;
408 rval = (csp - distance); 408 rval = (csp - distance);
diff --git a/arch/sparc/kernel/signal32.c b/arch/sparc/kernel/signal32.c
index ba5b09ad6666..ea22cd373c64 100644
--- a/arch/sparc/kernel/signal32.c
+++ b/arch/sparc/kernel/signal32.c
@@ -120,8 +120,8 @@ struct rt_signal_frame32 {
120}; 120};
121 121
122/* Align macros */ 122/* Align macros */
123#define SF_ALIGNEDSZ (((sizeof(struct signal_frame32) + 7) & (~7))) 123#define SF_ALIGNEDSZ (((sizeof(struct signal_frame32) + 15) & (~15)))
124#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 7) & (~7))) 124#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 15) & (~15)))
125 125
126int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) 126int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
127{ 127{
@@ -420,15 +420,17 @@ static void __user *get_sigframe(struct sigaction *sa, struct pt_regs *regs, uns
420 sp = current->sas_ss_sp + current->sas_ss_size; 420 sp = current->sas_ss_sp + current->sas_ss_size;
421 } 421 }
422 422
423 sp -= framesize;
424
423 /* Always align the stack frame. This handles two cases. First, 425 /* Always align the stack frame. This handles two cases. First,
424 * sigaltstack need not be mindful of platform specific stack 426 * sigaltstack need not be mindful of platform specific stack
425 * alignment. Second, if we took this signal because the stack 427 * alignment. Second, if we took this signal because the stack
426 * is not aligned properly, we'd like to take the signal cleanly 428 * is not aligned properly, we'd like to take the signal cleanly
427 * and report that. 429 * and report that.
428 */ 430 */
429 sp &= ~7UL; 431 sp &= ~15UL;
430 432
431 return (void __user *)(sp - framesize); 433 return (void __user *) sp;
432} 434}
433 435
434static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu) 436static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index 7ce1a1005b1d..9882df92ba0a 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -267,15 +267,17 @@ static inline void __user *get_sigframe(struct sigaction *sa, struct pt_regs *re
267 sp = current->sas_ss_sp + current->sas_ss_size; 267 sp = current->sas_ss_sp + current->sas_ss_size;
268 } 268 }
269 269
270 sp -= framesize;
271
270 /* Always align the stack frame. This handles two cases. First, 272 /* Always align the stack frame. This handles two cases. First,
271 * sigaltstack need not be mindful of platform specific stack 273 * sigaltstack need not be mindful of platform specific stack
272 * alignment. Second, if we took this signal because the stack 274 * alignment. Second, if we took this signal because the stack
273 * is not aligned properly, we'd like to take the signal cleanly 275 * is not aligned properly, we'd like to take the signal cleanly
274 * and report that. 276 * and report that.
275 */ 277 */
276 sp &= ~7UL; 278 sp &= ~15UL;
277 279
278 return (void __user *)(sp - framesize); 280 return (void __user *) sp;
279} 281}
280 282
281static inline int 283static inline int
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index 647afbda7ae1..9fa48c30037e 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -353,7 +353,7 @@ segv:
353/* Checks if the fp is valid */ 353/* Checks if the fp is valid */
354static int invalid_frame_pointer(void __user *fp, int fplen) 354static int invalid_frame_pointer(void __user *fp, int fplen)
355{ 355{
356 if (((unsigned long) fp) & 7) 356 if (((unsigned long) fp) & 15)
357 return 1; 357 return 1;
358 return 0; 358 return 0;
359} 359}
@@ -396,15 +396,17 @@ static inline void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *
396 sp = current->sas_ss_sp + current->sas_ss_size; 396 sp = current->sas_ss_sp + current->sas_ss_size;
397 } 397 }
398 398
399 sp -= framesize;
400
399 /* Always align the stack frame. This handles two cases. First, 401 /* Always align the stack frame. This handles two cases. First,
400 * sigaltstack need not be mindful of platform specific stack 402 * sigaltstack need not be mindful of platform specific stack
401 * alignment. Second, if we took this signal because the stack 403 * alignment. Second, if we took this signal because the stack
402 * is not aligned properly, we'd like to take the signal cleanly 404 * is not aligned properly, we'd like to take the signal cleanly
403 * and report that. 405 * and report that.
404 */ 406 */
405 sp &= ~7UL; 407 sp &= ~15UL;
406 408
407 return (void __user *)(sp - framesize); 409 return (void __user *) sp;
408} 410}
409 411
410static inline void 412static inline void
diff --git a/arch/sparc/kernel/tsb.S b/arch/sparc/kernel/tsb.S
index 8c91d9b29a2f..db15d123f054 100644
--- a/arch/sparc/kernel/tsb.S
+++ b/arch/sparc/kernel/tsb.S
@@ -191,10 +191,12 @@ tsb_dtlb_load:
191 191
192tsb_itlb_load: 192tsb_itlb_load:
193 /* Executable bit must be set. */ 193 /* Executable bit must be set. */
194661: andcc %g5, _PAGE_EXEC_4U, %g0 194661: sethi %hi(_PAGE_EXEC_4U), %g4
195 .section .sun4v_1insn_patch, "ax" 195 andcc %g5, %g4, %g0
196 .section .sun4v_2insn_patch, "ax"
196 .word 661b 197 .word 661b
197 andcc %g5, _PAGE_EXEC_4V, %g0 198 andcc %g5, _PAGE_EXEC_4V, %g0
199 nop
198 .previous 200 .previous
199 201
200 be,pn %xcc, tsb_do_fault 202 be,pn %xcc, tsb_do_fault
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 69b74a7b877f..ac80b7d70014 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -65,12 +65,17 @@ extern void alternatives_smp_module_add(struct module *mod, char *name,
65 void *text, void *text_end); 65 void *text, void *text_end);
66extern void alternatives_smp_module_del(struct module *mod); 66extern void alternatives_smp_module_del(struct module *mod);
67extern void alternatives_smp_switch(int smp); 67extern void alternatives_smp_switch(int smp);
68extern int alternatives_text_reserved(void *start, void *end);
68#else 69#else
69static inline void alternatives_smp_module_add(struct module *mod, char *name, 70static inline void alternatives_smp_module_add(struct module *mod, char *name,
70 void *locks, void *locks_end, 71 void *locks, void *locks_end,
71 void *text, void *text_end) {} 72 void *text, void *text_end) {}
72static inline void alternatives_smp_module_del(struct module *mod) {} 73static inline void alternatives_smp_module_del(struct module *mod) {}
73static inline void alternatives_smp_switch(int smp) {} 74static inline void alternatives_smp_switch(int smp) {}
75static inline int alternatives_text_reserved(void *start, void *end)
76{
77 return 0;
78}
74#endif /* CONFIG_SMP */ 79#endif /* CONFIG_SMP */
75 80
76/* alternative assembly primitive: */ 81/* alternative assembly primitive: */
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 8240f76b531e..b81002f23614 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -14,6 +14,9 @@
14 which debugging register was responsible for the trap. The other bits 14 which debugging register was responsible for the trap. The other bits
15 are either reserved or not of interest to us. */ 15 are either reserved or not of interest to us. */
16 16
17/* Define reserved bits in DR6 which are always set to 1 */
18#define DR6_RESERVED (0xFFFF0FF0)
19
17#define DR_TRAP0 (0x1) /* db0 */ 20#define DR_TRAP0 (0x1) /* db0 */
18#define DR_TRAP1 (0x2) /* db1 */ 21#define DR_TRAP1 (0x2) /* db1 */
19#define DR_TRAP2 (0x4) /* db2 */ 22#define DR_TRAP2 (0x4) /* db2 */
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 1994d3f58443..f2ad2163109d 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -170,10 +170,7 @@ static inline void elf_common_init(struct thread_struct *t,
170} 170}
171 171
172#define ELF_PLAT_INIT(_r, load_addr) \ 172#define ELF_PLAT_INIT(_r, load_addr) \
173do { \ 173 elf_common_init(&current->thread, _r, 0)
174 elf_common_init(&current->thread, _r, 0); \
175 clear_thread_flag(TIF_IA32); \
176} while (0)
177 174
178#define COMPAT_ELF_PLAT_INIT(regs, load_addr) \ 175#define COMPAT_ELF_PLAT_INIT(regs, load_addr) \
179 elf_common_init(&current->thread, regs, __USER_DS) 176 elf_common_init(&current->thread, regs, __USER_DS)
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index 0675a7c4c20e..2a1bd8f4f23a 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -10,7 +10,6 @@
10 * (display/resolving) 10 * (display/resolving)
11 */ 11 */
12struct arch_hw_breakpoint { 12struct arch_hw_breakpoint {
13 char *name; /* Contains name of the symbol to set bkpt */
14 unsigned long address; 13 unsigned long address;
15 u8 len; 14 u8 len;
16 u8 type; 15 u8 type;
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index 139d4c1a33a7..93da9c3f3341 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -19,7 +19,6 @@ extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
19extern int check_nmi_watchdog(void); 19extern int check_nmi_watchdog(void);
20extern int nmi_watchdog_enabled; 20extern int nmi_watchdog_enabled;
21extern int avail_to_resrv_perfctr_nmi_bit(unsigned int); 21extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);
22extern int avail_to_resrv_perfctr_nmi(unsigned int);
23extern int reserve_perfctr_nmi(unsigned int); 22extern int reserve_perfctr_nmi(unsigned int);
24extern void release_perfctr_nmi(unsigned int); 23extern void release_perfctr_nmi(unsigned int);
25extern int reserve_evntsel_nmi(unsigned int); 24extern int reserve_evntsel_nmi(unsigned int);
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 1380367dabd9..db6109a885a7 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -18,7 +18,7 @@
18#define MSR_ARCH_PERFMON_EVENTSEL0 0x186 18#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
19#define MSR_ARCH_PERFMON_EVENTSEL1 0x187 19#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
20 20
21#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22) 21#define ARCH_PERFMON_EVENTSEL_ENABLE (1 << 22)
22#define ARCH_PERFMON_EVENTSEL_ANY (1 << 21) 22#define ARCH_PERFMON_EVENTSEL_ANY (1 << 21)
23#define ARCH_PERFMON_EVENTSEL_INT (1 << 20) 23#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
24#define ARCH_PERFMON_EVENTSEL_OS (1 << 17) 24#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
@@ -27,7 +27,14 @@
27/* 27/*
28 * Includes eventsel and unit mask as well: 28 * Includes eventsel and unit mask as well:
29 */ 29 */
30#define ARCH_PERFMON_EVENT_MASK 0xffff 30
31
32#define INTEL_ARCH_EVTSEL_MASK 0x000000FFULL
33#define INTEL_ARCH_UNIT_MASK 0x0000FF00ULL
34#define INTEL_ARCH_EDGE_MASK 0x00040000ULL
35#define INTEL_ARCH_INV_MASK 0x00800000ULL
36#define INTEL_ARCH_CNT_MASK 0xFF000000ULL
37#define INTEL_ARCH_EVENT_MASK (INTEL_ARCH_UNIT_MASK|INTEL_ARCH_EVTSEL_MASK)
31 38
32/* 39/*
33 * filter mask to validate fixed counter events. 40 * filter mask to validate fixed counter events.
@@ -38,7 +45,12 @@
38 * The other filters are supported by fixed counters. 45 * The other filters are supported by fixed counters.
39 * The any-thread option is supported starting with v3. 46 * The any-thread option is supported starting with v3.
40 */ 47 */
41#define ARCH_PERFMON_EVENT_FILTER_MASK 0xff840000 48#define INTEL_ARCH_FIXED_MASK \
49 (INTEL_ARCH_CNT_MASK| \
50 INTEL_ARCH_INV_MASK| \
51 INTEL_ARCH_EDGE_MASK|\
52 INTEL_ARCH_UNIT_MASK|\
53 INTEL_ARCH_EVENT_MASK)
42 54
43#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c 55#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
44#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) 56#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
@@ -105,6 +117,18 @@ union cpuid10_edx {
105 */ 117 */
106#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) 118#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
107 119
120/* IbsFetchCtl bits/masks */
121#define IBS_FETCH_RAND_EN (1ULL<<57)
122#define IBS_FETCH_VAL (1ULL<<49)
123#define IBS_FETCH_ENABLE (1ULL<<48)
124#define IBS_FETCH_CNT 0xFFFF0000ULL
125#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
126
127/* IbsOpCtl bits */
128#define IBS_OP_CNT_CTL (1ULL<<19)
129#define IBS_OP_VAL (1ULL<<18)
130#define IBS_OP_ENABLE (1ULL<<17)
131#define IBS_OP_MAX_CNT 0x0000FFFFULL
108 132
109#ifdef CONFIG_PERF_EVENTS 133#ifdef CONFIG_PERF_EVENTS
110extern void init_hw_perf_events(void); 134extern void init_hw_perf_events(void);
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 9d369f680321..20102808b191 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -274,10 +274,6 @@ static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
274 return 0; 274 return 0;
275} 275}
276 276
277/* Get Nth argument at function call */
278extern unsigned long regs_get_argument_nth(struct pt_regs *regs,
279 unsigned int n);
280
281/* 277/*
282 * These are defined as per linux/ptrace.h, which see. 278 * These are defined as per linux/ptrace.h, which see.
283 */ 279 */
diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index 35e89122a42f..4dab78edbad9 100644
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -3,8 +3,6 @@
3 3
4extern int kstack_depth_to_print; 4extern int kstack_depth_to_print;
5 5
6int x86_is_stack_id(int id, char *name);
7
8struct thread_info; 6struct thread_info;
9struct stacktrace_ops; 7struct stacktrace_ops;
10 8
diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h
index ecb544e65382..e04740f7a0bb 100644
--- a/arch/x86/include/asm/system.h
+++ b/arch/x86/include/asm/system.h
@@ -11,9 +11,9 @@
11#include <linux/irqflags.h> 11#include <linux/irqflags.h>
12 12
13/* entries in ARCH_DLINFO: */ 13/* entries in ARCH_DLINFO: */
14#ifdef CONFIG_IA32_EMULATION 14#if defined(CONFIG_IA32_EMULATION) || !defined(CONFIG_X86_64)
15# define AT_VECTOR_SIZE_ARCH 2 15# define AT_VECTOR_SIZE_ARCH 2
16#else 16#else /* else it's non-compat x86-64 */
17# define AT_VECTOR_SIZE_ARCH 1 17# define AT_VECTOR_SIZE_ARCH 1
18#endif 18#endif
19 19
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 036d28adf59d..af1c5833ff23 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -1185,9 +1185,6 @@ static void __init acpi_process_madt(void)
1185 if (!error) { 1185 if (!error) {
1186 acpi_lapic = 1; 1186 acpi_lapic = 1;
1187 1187
1188#ifdef CONFIG_X86_BIGSMP
1189 generic_bigsmp_probe();
1190#endif
1191 /* 1188 /*
1192 * Parse MADT IO-APIC entries 1189 * Parse MADT IO-APIC entries
1193 */ 1190 */
@@ -1197,8 +1194,6 @@ static void __init acpi_process_madt(void)
1197 acpi_ioapic = 1; 1194 acpi_ioapic = 1;
1198 1195
1199 smp_found_config = 1; 1196 smp_found_config = 1;
1200 if (apic->setup_apic_routing)
1201 apic->setup_apic_routing();
1202 } 1197 }
1203 } 1198 }
1204 if (error == -EINVAL) { 1199 if (error == -EINVAL) {
@@ -1349,14 +1344,6 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = {
1349 }, 1344 },
1350 { 1345 {
1351 .callback = force_acpi_ht, 1346 .callback = force_acpi_ht,
1352 .ident = "ASUS P2B-DS",
1353 .matches = {
1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1355 DMI_MATCH(DMI_BOARD_NAME, "P2B-DS"),
1356 },
1357 },
1358 {
1359 .callback = force_acpi_ht,
1360 .ident = "ASUS CUR-DLS", 1347 .ident = "ASUS CUR-DLS",
1361 .matches = { 1348 .matches = {
1362 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1349 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index de7353c0ce9c..e63b80e5861c 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -390,6 +390,24 @@ void alternatives_smp_switch(int smp)
390 mutex_unlock(&smp_alt); 390 mutex_unlock(&smp_alt);
391} 391}
392 392
393/* Return 1 if the address range is reserved for smp-alternatives */
394int alternatives_text_reserved(void *start, void *end)
395{
396 struct smp_alt_module *mod;
397 u8 **ptr;
398 u8 *text_start = start;
399 u8 *text_end = end;
400
401 list_for_each_entry(mod, &smp_alt_modules, next) {
402 if (mod->text > text_end || mod->text_end < text_start)
403 continue;
404 for (ptr = mod->locks; ptr < mod->locks_end; ptr++)
405 if (text_start <= *ptr && text_end >= *ptr)
406 return 1;
407 }
408
409 return 0;
410}
393#endif 411#endif
394 412
395#ifdef CONFIG_PARAVIRT 413#ifdef CONFIG_PARAVIRT
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 3987e4408f75..dfca210f6a10 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1641,9 +1641,7 @@ int __init APIC_init_uniprocessor(void)
1641#endif 1641#endif
1642 1642
1643 enable_IR_x2apic(); 1643 enable_IR_x2apic();
1644#ifdef CONFIG_X86_64
1645 default_setup_apic_routing(); 1644 default_setup_apic_routing();
1646#endif
1647 1645
1648 verify_local_APIC(); 1646 verify_local_APIC();
1649 connect_bsp_APIC(); 1647 connect_bsp_APIC();
@@ -1891,21 +1889,6 @@ void __cpuinit generic_processor_info(int apicid, int version)
1891 if (apicid > max_physical_apicid) 1889 if (apicid > max_physical_apicid)
1892 max_physical_apicid = apicid; 1890 max_physical_apicid = apicid;
1893 1891
1894#ifdef CONFIG_X86_32
1895 if (num_processors > 8) {
1896 switch (boot_cpu_data.x86_vendor) {
1897 case X86_VENDOR_INTEL:
1898 if (!APIC_XAPIC(version)) {
1899 def_to_bigsmp = 0;
1900 break;
1901 }
1902 /* If P4 and above fall through */
1903 case X86_VENDOR_AMD:
1904 def_to_bigsmp = 1;
1905 }
1906 }
1907#endif
1908
1909#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1892#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1910 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1893 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1911 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1894 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 1a6559f6768c..99d2fe016084 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -52,7 +52,32 @@ static int __init print_ipi_mode(void)
52} 52}
53late_initcall(print_ipi_mode); 53late_initcall(print_ipi_mode);
54 54
55void default_setup_apic_routing(void) 55void __init default_setup_apic_routing(void)
56{
57 int version = apic_version[boot_cpu_physical_apicid];
58
59 if (num_possible_cpus() > 8) {
60 switch (boot_cpu_data.x86_vendor) {
61 case X86_VENDOR_INTEL:
62 if (!APIC_XAPIC(version)) {
63 def_to_bigsmp = 0;
64 break;
65 }
66 /* If P4 and above fall through */
67 case X86_VENDOR_AMD:
68 def_to_bigsmp = 1;
69 }
70 }
71
72#ifdef CONFIG_X86_BIGSMP
73 generic_bigsmp_probe();
74#endif
75
76 if (apic->setup_apic_routing)
77 apic->setup_apic_routing();
78}
79
80static void setup_apic_flat_routing(void)
56{ 81{
57#ifdef CONFIG_X86_IO_APIC 82#ifdef CONFIG_X86_IO_APIC
58 printk(KERN_INFO 83 printk(KERN_INFO
@@ -103,7 +128,7 @@ struct apic apic_default = {
103 .init_apic_ldr = default_init_apic_ldr, 128 .init_apic_ldr = default_init_apic_ldr,
104 129
105 .ioapic_phys_id_map = default_ioapic_phys_id_map, 130 .ioapic_phys_id_map = default_ioapic_phys_id_map,
106 .setup_apic_routing = default_setup_apic_routing, 131 .setup_apic_routing = setup_apic_flat_routing,
107 .multi_timer_check = NULL, 132 .multi_timer_check = NULL,
108 .apicid_to_node = default_apicid_to_node, 133 .apicid_to_node = default_apicid_to_node,
109 .cpu_to_logical_apicid = default_cpu_to_logical_apicid, 134 .cpu_to_logical_apicid = default_cpu_to_logical_apicid,
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index 450fe2064a14..83e9be4778e2 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -67,7 +67,7 @@ void __init default_setup_apic_routing(void)
67 } 67 }
68#endif 68#endif
69 69
70 if (apic == &apic_flat && num_processors > 8) 70 if (apic == &apic_flat && num_possible_cpus() > 8)
71 apic = &apic_physflat; 71 apic = &apic_physflat;
72 72
73 printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); 73 printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index f125e5c551c0..6e44519960c8 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1356,6 +1356,7 @@ static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol)
1356 1356
1357 kfree(data->powernow_table); 1357 kfree(data->powernow_table);
1358 kfree(data); 1358 kfree(data);
1359 per_cpu(powernow_data, pol->cpu) = NULL;
1359 1360
1360 return 0; 1361 return 0;
1361} 1362}
@@ -1375,7 +1376,7 @@ static unsigned int powernowk8_get(unsigned int cpu)
1375 int err; 1376 int err;
1376 1377
1377 if (!data) 1378 if (!data)
1378 return -EINVAL; 1379 return 0;
1379 1380
1380 smp_call_function_single(cpu, query_values_on_cpu, &err, true); 1381 smp_call_function_single(cpu, query_values_on_cpu, &err, true);
1381 if (err) 1382 if (err)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 8c1c07073ccc..bfc43fa208bc 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
10 * 11 *
11 * For licencing details see kernel-base/COPYING 12 * For licencing details see kernel-base/COPYING
12 */ 13 */
@@ -22,6 +23,7 @@
22#include <linux/uaccess.h> 23#include <linux/uaccess.h>
23#include <linux/highmem.h> 24#include <linux/highmem.h>
24#include <linux/cpu.h> 25#include <linux/cpu.h>
26#include <linux/bitops.h>
25 27
26#include <asm/apic.h> 28#include <asm/apic.h>
27#include <asm/stacktrace.h> 29#include <asm/stacktrace.h>
@@ -68,26 +70,59 @@ struct debug_store {
68 u64 pebs_event_reset[MAX_PEBS_EVENTS]; 70 u64 pebs_event_reset[MAX_PEBS_EVENTS];
69}; 71};
70 72
73struct event_constraint {
74 union {
75 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
76 u64 idxmsk64;
77 };
78 u64 code;
79 u64 cmask;
80 int weight;
81};
82
83struct amd_nb {
84 int nb_id; /* NorthBridge id */
85 int refcnt; /* reference count */
86 struct perf_event *owners[X86_PMC_IDX_MAX];
87 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
88};
89
71struct cpu_hw_events { 90struct cpu_hw_events {
72 struct perf_event *events[X86_PMC_IDX_MAX]; 91 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
73 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
74 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 92 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
75 unsigned long interrupts; 93 unsigned long interrupts;
76 int enabled; 94 int enabled;
77 struct debug_store *ds; 95 struct debug_store *ds;
78};
79 96
80struct event_constraint { 97 int n_events;
81 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 98 int n_added;
82 int code; 99 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
100 u64 tags[X86_PMC_IDX_MAX];
101 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
102 struct amd_nb *amd_nb;
83}; 103};
84 104
85#define EVENT_CONSTRAINT(c, m) { .code = (c), .idxmsk[0] = (m) } 105#define __EVENT_CONSTRAINT(c, n, m, w) {\
86#define EVENT_CONSTRAINT_END { .code = 0, .idxmsk[0] = 0 } 106 { .idxmsk64 = (n) }, \
107 .code = (c), \
108 .cmask = (m), \
109 .weight = (w), \
110}
111
112#define EVENT_CONSTRAINT(c, n, m) \
113 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
87 114
88#define for_each_event_constraint(e, c) \ 115#define INTEL_EVENT_CONSTRAINT(c, n) \
89 for ((e) = (c); (e)->idxmsk[0]; (e)++) 116 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
90 117
118#define FIXED_EVENT_CONSTRAINT(c, n) \
119 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
120
121#define EVENT_CONSTRAINT_END \
122 EVENT_CONSTRAINT(0, 0, 0)
123
124#define for_each_event_constraint(e, c) \
125 for ((e) = (c); (e)->cmask; (e)++)
91 126
92/* 127/*
93 * struct x86_pmu - generic x86 pmu 128 * struct x86_pmu - generic x86 pmu
@@ -114,8 +149,14 @@ struct x86_pmu {
114 u64 intel_ctrl; 149 u64 intel_ctrl;
115 void (*enable_bts)(u64 config); 150 void (*enable_bts)(u64 config);
116 void (*disable_bts)(void); 151 void (*disable_bts)(void);
117 int (*get_event_idx)(struct cpu_hw_events *cpuc, 152
118 struct hw_perf_event *hwc); 153 struct event_constraint *
154 (*get_event_constraints)(struct cpu_hw_events *cpuc,
155 struct perf_event *event);
156
157 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
158 struct perf_event *event);
159 struct event_constraint *event_constraints;
119}; 160};
120 161
121static struct x86_pmu x86_pmu __read_mostly; 162static struct x86_pmu x86_pmu __read_mostly;
@@ -124,111 +165,8 @@ static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
124 .enabled = 1, 165 .enabled = 1,
125}; 166};
126 167
127static const struct event_constraint *event_constraints; 168static int x86_perf_event_set_period(struct perf_event *event,
128 169 struct hw_perf_event *hwc, int idx);
129/*
130 * Not sure about some of these
131 */
132static const u64 p6_perfmon_event_map[] =
133{
134 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
135 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
136 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
137 [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
138 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
139 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
140 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
141};
142
143static u64 p6_pmu_event_map(int hw_event)
144{
145 return p6_perfmon_event_map[hw_event];
146}
147
148/*
149 * Event setting that is specified not to count anything.
150 * We use this to effectively disable a counter.
151 *
152 * L2_RQSTS with 0 MESI unit mask.
153 */
154#define P6_NOP_EVENT 0x0000002EULL
155
156static u64 p6_pmu_raw_event(u64 hw_event)
157{
158#define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
159#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
160#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
161#define P6_EVNTSEL_INV_MASK 0x00800000ULL
162#define P6_EVNTSEL_REG_MASK 0xFF000000ULL
163
164#define P6_EVNTSEL_MASK \
165 (P6_EVNTSEL_EVENT_MASK | \
166 P6_EVNTSEL_UNIT_MASK | \
167 P6_EVNTSEL_EDGE_MASK | \
168 P6_EVNTSEL_INV_MASK | \
169 P6_EVNTSEL_REG_MASK)
170
171 return hw_event & P6_EVNTSEL_MASK;
172}
173
174static const struct event_constraint intel_p6_event_constraints[] =
175{
176 EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
177 EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
178 EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
179 EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
180 EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
181 EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
182 EVENT_CONSTRAINT_END
183};
184
185/*
186 * Intel PerfMon v3. Used on Core2 and later.
187 */
188static const u64 intel_perfmon_event_map[] =
189{
190 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
191 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
192 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
193 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
194 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
195 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
196 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
197};
198
199static const struct event_constraint intel_core_event_constraints[] =
200{
201 EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
202 EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
203 EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
204 EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
205 EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
206 EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
207 EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
208 EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
209 EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
210 EVENT_CONSTRAINT_END
211};
212
213static const struct event_constraint intel_nehalem_event_constraints[] =
214{
215 EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
216 EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
217 EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
218 EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
219 EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
220 EVENT_CONSTRAINT(0x4c, 0x3), /* LOAD_HIT_PRE */
221 EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
222 EVENT_CONSTRAINT(0x52, 0x3), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
223 EVENT_CONSTRAINT(0x53, 0x3), /* L1D_CACHE_LOCK_FB_HIT */
224 EVENT_CONSTRAINT(0xc5, 0x3), /* CACHE_LOCK_CYCLES */
225 EVENT_CONSTRAINT_END
226};
227
228static u64 intel_pmu_event_map(int hw_event)
229{
230 return intel_perfmon_event_map[hw_event];
231}
232 170
233/* 171/*
234 * Generalized hw caching related hw_event table, filled 172 * Generalized hw caching related hw_event table, filled
@@ -245,424 +183,6 @@ static u64 __read_mostly hw_cache_event_ids
245 [PERF_COUNT_HW_CACHE_OP_MAX] 183 [PERF_COUNT_HW_CACHE_OP_MAX]
246 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 184 [PERF_COUNT_HW_CACHE_RESULT_MAX];
247 185
248static __initconst u64 nehalem_hw_cache_event_ids
249 [PERF_COUNT_HW_CACHE_MAX]
250 [PERF_COUNT_HW_CACHE_OP_MAX]
251 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
252{
253 [ C(L1D) ] = {
254 [ C(OP_READ) ] = {
255 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
256 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
257 },
258 [ C(OP_WRITE) ] = {
259 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
260 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
261 },
262 [ C(OP_PREFETCH) ] = {
263 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
264 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
265 },
266 },
267 [ C(L1I ) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
270 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
271 },
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = -1,
274 [ C(RESULT_MISS) ] = -1,
275 },
276 [ C(OP_PREFETCH) ] = {
277 [ C(RESULT_ACCESS) ] = 0x0,
278 [ C(RESULT_MISS) ] = 0x0,
279 },
280 },
281 [ C(LL ) ] = {
282 [ C(OP_READ) ] = {
283 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
284 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
285 },
286 [ C(OP_WRITE) ] = {
287 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
288 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
289 },
290 [ C(OP_PREFETCH) ] = {
291 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
292 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
293 },
294 },
295 [ C(DTLB) ] = {
296 [ C(OP_READ) ] = {
297 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
298 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
299 },
300 [ C(OP_WRITE) ] = {
301 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
302 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
303 },
304 [ C(OP_PREFETCH) ] = {
305 [ C(RESULT_ACCESS) ] = 0x0,
306 [ C(RESULT_MISS) ] = 0x0,
307 },
308 },
309 [ C(ITLB) ] = {
310 [ C(OP_READ) ] = {
311 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
312 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
313 },
314 [ C(OP_WRITE) ] = {
315 [ C(RESULT_ACCESS) ] = -1,
316 [ C(RESULT_MISS) ] = -1,
317 },
318 [ C(OP_PREFETCH) ] = {
319 [ C(RESULT_ACCESS) ] = -1,
320 [ C(RESULT_MISS) ] = -1,
321 },
322 },
323 [ C(BPU ) ] = {
324 [ C(OP_READ) ] = {
325 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
326 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
327 },
328 [ C(OP_WRITE) ] = {
329 [ C(RESULT_ACCESS) ] = -1,
330 [ C(RESULT_MISS) ] = -1,
331 },
332 [ C(OP_PREFETCH) ] = {
333 [ C(RESULT_ACCESS) ] = -1,
334 [ C(RESULT_MISS) ] = -1,
335 },
336 },
337};
338
339static __initconst u64 core2_hw_cache_event_ids
340 [PERF_COUNT_HW_CACHE_MAX]
341 [PERF_COUNT_HW_CACHE_OP_MAX]
342 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
343{
344 [ C(L1D) ] = {
345 [ C(OP_READ) ] = {
346 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
347 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
348 },
349 [ C(OP_WRITE) ] = {
350 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
351 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
352 },
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
355 [ C(RESULT_MISS) ] = 0,
356 },
357 },
358 [ C(L1I ) ] = {
359 [ C(OP_READ) ] = {
360 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
361 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
362 },
363 [ C(OP_WRITE) ] = {
364 [ C(RESULT_ACCESS) ] = -1,
365 [ C(RESULT_MISS) ] = -1,
366 },
367 [ C(OP_PREFETCH) ] = {
368 [ C(RESULT_ACCESS) ] = 0,
369 [ C(RESULT_MISS) ] = 0,
370 },
371 },
372 [ C(LL ) ] = {
373 [ C(OP_READ) ] = {
374 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
375 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
376 },
377 [ C(OP_WRITE) ] = {
378 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
379 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
380 },
381 [ C(OP_PREFETCH) ] = {
382 [ C(RESULT_ACCESS) ] = 0,
383 [ C(RESULT_MISS) ] = 0,
384 },
385 },
386 [ C(DTLB) ] = {
387 [ C(OP_READ) ] = {
388 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
389 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
390 },
391 [ C(OP_WRITE) ] = {
392 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
393 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
394 },
395 [ C(OP_PREFETCH) ] = {
396 [ C(RESULT_ACCESS) ] = 0,
397 [ C(RESULT_MISS) ] = 0,
398 },
399 },
400 [ C(ITLB) ] = {
401 [ C(OP_READ) ] = {
402 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
403 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
404 },
405 [ C(OP_WRITE) ] = {
406 [ C(RESULT_ACCESS) ] = -1,
407 [ C(RESULT_MISS) ] = -1,
408 },
409 [ C(OP_PREFETCH) ] = {
410 [ C(RESULT_ACCESS) ] = -1,
411 [ C(RESULT_MISS) ] = -1,
412 },
413 },
414 [ C(BPU ) ] = {
415 [ C(OP_READ) ] = {
416 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
417 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
418 },
419 [ C(OP_WRITE) ] = {
420 [ C(RESULT_ACCESS) ] = -1,
421 [ C(RESULT_MISS) ] = -1,
422 },
423 [ C(OP_PREFETCH) ] = {
424 [ C(RESULT_ACCESS) ] = -1,
425 [ C(RESULT_MISS) ] = -1,
426 },
427 },
428};
429
430static __initconst u64 atom_hw_cache_event_ids
431 [PERF_COUNT_HW_CACHE_MAX]
432 [PERF_COUNT_HW_CACHE_OP_MAX]
433 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
434{
435 [ C(L1D) ] = {
436 [ C(OP_READ) ] = {
437 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
438 [ C(RESULT_MISS) ] = 0,
439 },
440 [ C(OP_WRITE) ] = {
441 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
442 [ C(RESULT_MISS) ] = 0,
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0,
447 },
448 },
449 [ C(L1I ) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
452 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
453 },
454 [ C(OP_WRITE) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 [ C(OP_PREFETCH) ] = {
459 [ C(RESULT_ACCESS) ] = 0,
460 [ C(RESULT_MISS) ] = 0,
461 },
462 },
463 [ C(LL ) ] = {
464 [ C(OP_READ) ] = {
465 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
466 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
467 },
468 [ C(OP_WRITE) ] = {
469 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
470 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
471 },
472 [ C(OP_PREFETCH) ] = {
473 [ C(RESULT_ACCESS) ] = 0,
474 [ C(RESULT_MISS) ] = 0,
475 },
476 },
477 [ C(DTLB) ] = {
478 [ C(OP_READ) ] = {
479 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
480 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
481 },
482 [ C(OP_WRITE) ] = {
483 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
484 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
485 },
486 [ C(OP_PREFETCH) ] = {
487 [ C(RESULT_ACCESS) ] = 0,
488 [ C(RESULT_MISS) ] = 0,
489 },
490 },
491 [ C(ITLB) ] = {
492 [ C(OP_READ) ] = {
493 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
494 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
495 },
496 [ C(OP_WRITE) ] = {
497 [ C(RESULT_ACCESS) ] = -1,
498 [ C(RESULT_MISS) ] = -1,
499 },
500 [ C(OP_PREFETCH) ] = {
501 [ C(RESULT_ACCESS) ] = -1,
502 [ C(RESULT_MISS) ] = -1,
503 },
504 },
505 [ C(BPU ) ] = {
506 [ C(OP_READ) ] = {
507 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
508 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
509 },
510 [ C(OP_WRITE) ] = {
511 [ C(RESULT_ACCESS) ] = -1,
512 [ C(RESULT_MISS) ] = -1,
513 },
514 [ C(OP_PREFETCH) ] = {
515 [ C(RESULT_ACCESS) ] = -1,
516 [ C(RESULT_MISS) ] = -1,
517 },
518 },
519};
520
521static u64 intel_pmu_raw_event(u64 hw_event)
522{
523#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
524#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
525#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
526#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
527#define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
528
529#define CORE_EVNTSEL_MASK \
530 (CORE_EVNTSEL_EVENT_MASK | \
531 CORE_EVNTSEL_UNIT_MASK | \
532 CORE_EVNTSEL_EDGE_MASK | \
533 CORE_EVNTSEL_INV_MASK | \
534 CORE_EVNTSEL_REG_MASK)
535
536 return hw_event & CORE_EVNTSEL_MASK;
537}
538
539static __initconst u64 amd_hw_cache_event_ids
540 [PERF_COUNT_HW_CACHE_MAX]
541 [PERF_COUNT_HW_CACHE_OP_MAX]
542 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
543{
544 [ C(L1D) ] = {
545 [ C(OP_READ) ] = {
546 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
547 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
548 },
549 [ C(OP_WRITE) ] = {
550 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
551 [ C(RESULT_MISS) ] = 0,
552 },
553 [ C(OP_PREFETCH) ] = {
554 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
555 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
556 },
557 },
558 [ C(L1I ) ] = {
559 [ C(OP_READ) ] = {
560 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
561 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
562 },
563 [ C(OP_WRITE) ] = {
564 [ C(RESULT_ACCESS) ] = -1,
565 [ C(RESULT_MISS) ] = -1,
566 },
567 [ C(OP_PREFETCH) ] = {
568 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
569 [ C(RESULT_MISS) ] = 0,
570 },
571 },
572 [ C(LL ) ] = {
573 [ C(OP_READ) ] = {
574 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
575 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
576 },
577 [ C(OP_WRITE) ] = {
578 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
579 [ C(RESULT_MISS) ] = 0,
580 },
581 [ C(OP_PREFETCH) ] = {
582 [ C(RESULT_ACCESS) ] = 0,
583 [ C(RESULT_MISS) ] = 0,
584 },
585 },
586 [ C(DTLB) ] = {
587 [ C(OP_READ) ] = {
588 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
589 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
590 },
591 [ C(OP_WRITE) ] = {
592 [ C(RESULT_ACCESS) ] = 0,
593 [ C(RESULT_MISS) ] = 0,
594 },
595 [ C(OP_PREFETCH) ] = {
596 [ C(RESULT_ACCESS) ] = 0,
597 [ C(RESULT_MISS) ] = 0,
598 },
599 },
600 [ C(ITLB) ] = {
601 [ C(OP_READ) ] = {
602 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
603 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
604 },
605 [ C(OP_WRITE) ] = {
606 [ C(RESULT_ACCESS) ] = -1,
607 [ C(RESULT_MISS) ] = -1,
608 },
609 [ C(OP_PREFETCH) ] = {
610 [ C(RESULT_ACCESS) ] = -1,
611 [ C(RESULT_MISS) ] = -1,
612 },
613 },
614 [ C(BPU ) ] = {
615 [ C(OP_READ) ] = {
616 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
617 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
618 },
619 [ C(OP_WRITE) ] = {
620 [ C(RESULT_ACCESS) ] = -1,
621 [ C(RESULT_MISS) ] = -1,
622 },
623 [ C(OP_PREFETCH) ] = {
624 [ C(RESULT_ACCESS) ] = -1,
625 [ C(RESULT_MISS) ] = -1,
626 },
627 },
628};
629
630/*
631 * AMD Performance Monitor K7 and later.
632 */
633static const u64 amd_perfmon_event_map[] =
634{
635 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
636 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
637 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
638 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
639 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
640 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
641};
642
643static u64 amd_pmu_event_map(int hw_event)
644{
645 return amd_perfmon_event_map[hw_event];
646}
647
648static u64 amd_pmu_raw_event(u64 hw_event)
649{
650#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
651#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
652#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
653#define K7_EVNTSEL_INV_MASK 0x000800000ULL
654#define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
655
656#define K7_EVNTSEL_MASK \
657 (K7_EVNTSEL_EVENT_MASK | \
658 K7_EVNTSEL_UNIT_MASK | \
659 K7_EVNTSEL_EDGE_MASK | \
660 K7_EVNTSEL_INV_MASK | \
661 K7_EVNTSEL_REG_MASK)
662
663 return hw_event & K7_EVNTSEL_MASK;
664}
665
666/* 186/*
667 * Propagate event elapsed time into the generic event. 187 * Propagate event elapsed time into the generic event.
668 * Can only be executed on the CPU where the event is active. 188 * Can only be executed on the CPU where the event is active.
@@ -914,42 +434,6 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
914 return 0; 434 return 0;
915} 435}
916 436
917static void intel_pmu_enable_bts(u64 config)
918{
919 unsigned long debugctlmsr;
920
921 debugctlmsr = get_debugctlmsr();
922
923 debugctlmsr |= X86_DEBUGCTL_TR;
924 debugctlmsr |= X86_DEBUGCTL_BTS;
925 debugctlmsr |= X86_DEBUGCTL_BTINT;
926
927 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
928 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
929
930 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
931 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
932
933 update_debugctlmsr(debugctlmsr);
934}
935
936static void intel_pmu_disable_bts(void)
937{
938 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
939 unsigned long debugctlmsr;
940
941 if (!cpuc->ds)
942 return;
943
944 debugctlmsr = get_debugctlmsr();
945
946 debugctlmsr &=
947 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
948 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
949
950 update_debugctlmsr(debugctlmsr);
951}
952
953/* 437/*
954 * Setup the hardware configuration for a given attr_type 438 * Setup the hardware configuration for a given attr_type
955 */ 439 */
@@ -988,6 +472,8 @@ static int __hw_perf_event_init(struct perf_event *event)
988 hwc->config = ARCH_PERFMON_EVENTSEL_INT; 472 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
989 473
990 hwc->idx = -1; 474 hwc->idx = -1;
475 hwc->last_cpu = -1;
476 hwc->last_tag = ~0ULL;
991 477
992 /* 478 /*
993 * Count user and OS events unless requested not to. 479 * Count user and OS events unless requested not to.
@@ -1017,6 +503,9 @@ static int __hw_perf_event_init(struct perf_event *event)
1017 */ 503 */
1018 if (attr->type == PERF_TYPE_RAW) { 504 if (attr->type == PERF_TYPE_RAW) {
1019 hwc->config |= x86_pmu.raw_event(attr->config); 505 hwc->config |= x86_pmu.raw_event(attr->config);
506 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
507 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
508 return -EACCES;
1020 return 0; 509 return 0;
1021 } 510 }
1022 511
@@ -1056,216 +545,323 @@ static int __hw_perf_event_init(struct perf_event *event)
1056 return 0; 545 return 0;
1057} 546}
1058 547
1059static void p6_pmu_disable_all(void) 548static void x86_pmu_disable_all(void)
1060{ 549{
1061 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 550 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1062 u64 val; 551 int idx;
1063
1064 if (!cpuc->enabled)
1065 return;
1066 552
1067 cpuc->enabled = 0; 553 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1068 barrier(); 554 u64 val;
1069 555
1070 /* p6 only has one enable register */ 556 if (!test_bit(idx, cpuc->active_mask))
1071 rdmsrl(MSR_P6_EVNTSEL0, val); 557 continue;
1072 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; 558 rdmsrl(x86_pmu.eventsel + idx, val);
1073 wrmsrl(MSR_P6_EVNTSEL0, val); 559 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
560 continue;
561 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
562 wrmsrl(x86_pmu.eventsel + idx, val);
563 }
1074} 564}
1075 565
1076static void intel_pmu_disable_all(void) 566void hw_perf_disable(void)
1077{ 567{
1078 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 568 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1079 569
570 if (!x86_pmu_initialized())
571 return;
572
1080 if (!cpuc->enabled) 573 if (!cpuc->enabled)
1081 return; 574 return;
1082 575
576 cpuc->n_added = 0;
1083 cpuc->enabled = 0; 577 cpuc->enabled = 0;
1084 barrier(); 578 barrier();
1085 579
1086 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 580 x86_pmu.disable_all();
1087
1088 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1089 intel_pmu_disable_bts();
1090} 581}
1091 582
1092static void amd_pmu_disable_all(void) 583static void x86_pmu_enable_all(void)
1093{ 584{
1094 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 585 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1095 int idx; 586 int idx;
1096 587
1097 if (!cpuc->enabled)
1098 return;
1099
1100 cpuc->enabled = 0;
1101 /*
1102 * ensure we write the disable before we start disabling the
1103 * events proper, so that amd_pmu_enable_event() does the
1104 * right thing.
1105 */
1106 barrier();
1107
1108 for (idx = 0; idx < x86_pmu.num_events; idx++) { 588 for (idx = 0; idx < x86_pmu.num_events; idx++) {
589 struct perf_event *event = cpuc->events[idx];
1109 u64 val; 590 u64 val;
1110 591
1111 if (!test_bit(idx, cpuc->active_mask)) 592 if (!test_bit(idx, cpuc->active_mask))
1112 continue; 593 continue;
1113 rdmsrl(MSR_K7_EVNTSEL0 + idx, val); 594
1114 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) 595 val = event->hw.config;
1115 continue; 596 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
1116 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; 597 wrmsrl(x86_pmu.eventsel + idx, val);
1117 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1118 } 598 }
1119} 599}
1120 600
1121void hw_perf_disable(void) 601static const struct pmu pmu;
602
603static inline int is_x86_event(struct perf_event *event)
1122{ 604{
1123 if (!x86_pmu_initialized()) 605 return event->pmu == &pmu;
1124 return;
1125 return x86_pmu.disable_all();
1126} 606}
1127 607
1128static void p6_pmu_enable_all(void) 608static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1129{ 609{
1130 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 610 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
1131 unsigned long val; 611 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
612 int i, j, w, wmax, num = 0;
613 struct hw_perf_event *hwc;
1132 614
1133 if (cpuc->enabled) 615 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1134 return;
1135 616
1136 cpuc->enabled = 1; 617 for (i = 0; i < n; i++) {
1137 barrier(); 618 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
619 constraints[i] = c;
620 }
1138 621
1139 /* p6 only has one enable register */ 622 /*
1140 rdmsrl(MSR_P6_EVNTSEL0, val); 623 * fastpath, try to reuse previous register
1141 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 624 */
1142 wrmsrl(MSR_P6_EVNTSEL0, val); 625 for (i = 0; i < n; i++) {
1143} 626 hwc = &cpuc->event_list[i]->hw;
627 c = constraints[i];
1144 628
1145static void intel_pmu_enable_all(void) 629 /* never assigned */
1146{ 630 if (hwc->idx == -1)
1147 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 631 break;
1148 632
1149 if (cpuc->enabled) 633 /* constraint still honored */
1150 return; 634 if (!test_bit(hwc->idx, c->idxmsk))
635 break;
1151 636
1152 cpuc->enabled = 1; 637 /* not already used */
1153 barrier(); 638 if (test_bit(hwc->idx, used_mask))
639 break;
640
641 set_bit(hwc->idx, used_mask);
642 if (assign)
643 assign[i] = hwc->idx;
644 }
645 if (i == n)
646 goto done;
647
648 /*
649 * begin slow path
650 */
651
652 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1154 653
1155 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); 654 /*
655 * weight = number of possible counters
656 *
657 * 1 = most constrained, only works on one counter
658 * wmax = least constrained, works on any counter
659 *
660 * assign events to counters starting with most
661 * constrained events.
662 */
663 wmax = x86_pmu.num_events;
664
665 /*
666 * when fixed event counters are present,
667 * wmax is incremented by 1 to account
668 * for one more choice
669 */
670 if (x86_pmu.num_events_fixed)
671 wmax++;
672
673 for (w = 1, num = n; num && w <= wmax; w++) {
674 /* for each event */
675 for (i = 0; num && i < n; i++) {
676 c = constraints[i];
677 hwc = &cpuc->event_list[i]->hw;
678
679 if (c->weight != w)
680 continue;
681
682 for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
683 if (!test_bit(j, used_mask))
684 break;
685 }
1156 686
1157 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 687 if (j == X86_PMC_IDX_MAX)
1158 struct perf_event *event = 688 break;
1159 cpuc->events[X86_PMC_IDX_FIXED_BTS];
1160 689
1161 if (WARN_ON_ONCE(!event)) 690 set_bit(j, used_mask);
1162 return;
1163 691
1164 intel_pmu_enable_bts(event->hw.config); 692 if (assign)
693 assign[i] = j;
694 num--;
695 }
696 }
697done:
698 /*
699 * scheduling failed or is just a simulation,
700 * free resources if necessary
701 */
702 if (!assign || num) {
703 for (i = 0; i < n; i++) {
704 if (x86_pmu.put_event_constraints)
705 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
706 }
1165 } 707 }
708 return num ? -ENOSPC : 0;
1166} 709}
1167 710
1168static void amd_pmu_enable_all(void) 711/*
712 * dogrp: true if must collect siblings events (group)
713 * returns total number of events and error code
714 */
715static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1169{ 716{
1170 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 717 struct perf_event *event;
1171 int idx; 718 int n, max_count;
1172 719
1173 if (cpuc->enabled) 720 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
1174 return;
1175 721
1176 cpuc->enabled = 1; 722 /* current number of events already accepted */
1177 barrier(); 723 n = cpuc->n_events;
1178 724
1179 for (idx = 0; idx < x86_pmu.num_events; idx++) { 725 if (is_x86_event(leader)) {
1180 struct perf_event *event = cpuc->events[idx]; 726 if (n >= max_count)
1181 u64 val; 727 return -ENOSPC;
728 cpuc->event_list[n] = leader;
729 n++;
730 }
731 if (!dogrp)
732 return n;
1182 733
1183 if (!test_bit(idx, cpuc->active_mask)) 734 list_for_each_entry(event, &leader->sibling_list, group_entry) {
735 if (!is_x86_event(event) ||
736 event->state <= PERF_EVENT_STATE_OFF)
1184 continue; 737 continue;
1185 738
1186 val = event->hw.config; 739 if (n >= max_count)
1187 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 740 return -ENOSPC;
1188 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1189 }
1190}
1191 741
1192void hw_perf_enable(void) 742 cpuc->event_list[n] = event;
1193{ 743 n++;
1194 if (!x86_pmu_initialized()) 744 }
1195 return; 745 return n;
1196 x86_pmu.enable_all();
1197} 746}
1198 747
1199static inline u64 intel_pmu_get_status(void) 748static inline void x86_assign_hw_event(struct perf_event *event,
749 struct cpu_hw_events *cpuc, int i)
1200{ 750{
1201 u64 status; 751 struct hw_perf_event *hwc = &event->hw;
1202 752
1203 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 753 hwc->idx = cpuc->assign[i];
754 hwc->last_cpu = smp_processor_id();
755 hwc->last_tag = ++cpuc->tags[i];
1204 756
1205 return status; 757 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
758 hwc->config_base = 0;
759 hwc->event_base = 0;
760 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
761 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
762 /*
763 * We set it so that event_base + idx in wrmsr/rdmsr maps to
764 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
765 */
766 hwc->event_base =
767 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
768 } else {
769 hwc->config_base = x86_pmu.eventsel;
770 hwc->event_base = x86_pmu.perfctr;
771 }
1206} 772}
1207 773
1208static inline void intel_pmu_ack_status(u64 ack) 774static inline int match_prev_assignment(struct hw_perf_event *hwc,
775 struct cpu_hw_events *cpuc,
776 int i)
1209{ 777{
1210 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 778 return hwc->idx == cpuc->assign[i] &&
779 hwc->last_cpu == smp_processor_id() &&
780 hwc->last_tag == cpuc->tags[i];
1211} 781}
1212 782
1213static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx) 783static void x86_pmu_stop(struct perf_event *event);
1214{
1215 (void)checking_wrmsrl(hwc->config_base + idx,
1216 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1217}
1218 784
1219static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx) 785void hw_perf_enable(void)
1220{ 786{
1221 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config); 787 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1222} 788 struct perf_event *event;
789 struct hw_perf_event *hwc;
790 int i;
1223 791
1224static inline void 792 if (!x86_pmu_initialized())
1225intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx) 793 return;
1226{
1227 int idx = __idx - X86_PMC_IDX_FIXED;
1228 u64 ctrl_val, mask;
1229 794
1230 mask = 0xfULL << (idx * 4); 795 if (cpuc->enabled)
796 return;
1231 797
1232 rdmsrl(hwc->config_base, ctrl_val); 798 if (cpuc->n_added) {
1233 ctrl_val &= ~mask; 799 /*
1234 (void)checking_wrmsrl(hwc->config_base, ctrl_val); 800 * apply assignment obtained either from
1235} 801 * hw_perf_group_sched_in() or x86_pmu_enable()
802 *
803 * step1: save events moving to new counters
804 * step2: reprogram moved events into new counters
805 */
806 for (i = 0; i < cpuc->n_events; i++) {
1236 807
1237static inline void 808 event = cpuc->event_list[i];
1238p6_pmu_disable_event(struct hw_perf_event *hwc, int idx) 809 hwc = &event->hw;
1239{
1240 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1241 u64 val = P6_NOP_EVENT;
1242 810
1243 if (cpuc->enabled) 811 /*
1244 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 812 * we can avoid reprogramming counter if:
813 * - assigned same counter as last time
814 * - running on same CPU as last time
815 * - no other event has used the counter since
816 */
817 if (hwc->idx == -1 ||
818 match_prev_assignment(hwc, cpuc, i))
819 continue;
1245 820
1246 (void)checking_wrmsrl(hwc->config_base + idx, val); 821 x86_pmu_stop(event);
1247}
1248 822
1249static inline void 823 hwc->idx = -1;
1250intel_pmu_disable_event(struct hw_perf_event *hwc, int idx) 824 }
1251{
1252 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1253 intel_pmu_disable_bts();
1254 return;
1255 }
1256 825
1257 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 826 for (i = 0; i < cpuc->n_events; i++) {
1258 intel_pmu_disable_fixed(hwc, idx); 827
1259 return; 828 event = cpuc->event_list[i];
829 hwc = &event->hw;
830
831 if (hwc->idx == -1) {
832 x86_assign_hw_event(event, cpuc, i);
833 x86_perf_event_set_period(event, hwc, hwc->idx);
834 }
835 /*
836 * need to mark as active because x86_pmu_disable()
837 * clear active_mask and events[] yet it preserves
838 * idx
839 */
840 set_bit(hwc->idx, cpuc->active_mask);
841 cpuc->events[hwc->idx] = event;
842
843 x86_pmu.enable(hwc, hwc->idx);
844 perf_event_update_userpage(event);
845 }
846 cpuc->n_added = 0;
847 perf_events_lapic_init();
1260 } 848 }
1261 849
1262 x86_pmu_disable_event(hwc, idx); 850 cpuc->enabled = 1;
851 barrier();
852
853 x86_pmu.enable_all();
1263} 854}
1264 855
1265static inline void 856static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1266amd_pmu_disable_event(struct hw_perf_event *hwc, int idx) 857{
858 (void)checking_wrmsrl(hwc->config_base + idx,
859 hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
860}
861
862static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1267{ 863{
1268 x86_pmu_disable_event(hwc, idx); 864 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1269} 865}
1270 866
1271static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 867static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
@@ -1326,220 +922,60 @@ x86_perf_event_set_period(struct perf_event *event,
1326 return ret; 922 return ret;
1327} 923}
1328 924
1329static inline void 925static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1330intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
1331{
1332 int idx = __idx - X86_PMC_IDX_FIXED;
1333 u64 ctrl_val, bits, mask;
1334 int err;
1335
1336 /*
1337 * Enable IRQ generation (0x8),
1338 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1339 * if requested:
1340 */
1341 bits = 0x8ULL;
1342 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1343 bits |= 0x2;
1344 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1345 bits |= 0x1;
1346
1347 /*
1348 * ANY bit is supported in v3 and up
1349 */
1350 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1351 bits |= 0x4;
1352
1353 bits <<= (idx * 4);
1354 mask = 0xfULL << (idx * 4);
1355
1356 rdmsrl(hwc->config_base, ctrl_val);
1357 ctrl_val &= ~mask;
1358 ctrl_val |= bits;
1359 err = checking_wrmsrl(hwc->config_base, ctrl_val);
1360}
1361
1362static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1363{ 926{
1364 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 927 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1365 u64 val;
1366
1367 val = hwc->config;
1368 if (cpuc->enabled) 928 if (cpuc->enabled)
1369 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 929 __x86_pmu_enable_event(hwc, idx);
1370
1371 (void)checking_wrmsrl(hwc->config_base + idx, val);
1372} 930}
1373 931
1374 932/*
1375static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx) 933 * activate a single event
1376{ 934 *
1377 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { 935 * The event is added to the group of enabled events
1378 if (!__get_cpu_var(cpu_hw_events).enabled) 936 * but only if it can be scehduled with existing events.
1379 return; 937 *
1380 938 * Called with PMU disabled. If successful and return value 1,
1381 intel_pmu_enable_bts(hwc->config); 939 * then guaranteed to call perf_enable() and hw_perf_enable()
1382 return; 940 */
1383 } 941static int x86_pmu_enable(struct perf_event *event)
1384
1385 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1386 intel_pmu_enable_fixed(hwc, idx);
1387 return;
1388 }
1389
1390 x86_pmu_enable_event(hwc, idx);
1391}
1392
1393static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1394{ 942{
1395 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 943 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
944 struct hw_perf_event *hwc;
945 int assign[X86_PMC_IDX_MAX];
946 int n, n0, ret;
1396 947
1397 if (cpuc->enabled) 948 hwc = &event->hw;
1398 x86_pmu_enable_event(hwc, idx);
1399}
1400
1401static int fixed_mode_idx(struct hw_perf_event *hwc)
1402{
1403 unsigned int hw_event;
1404
1405 hw_event = hwc->config & ARCH_PERFMON_EVENT_MASK;
1406
1407 if (unlikely((hw_event ==
1408 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
1409 (hwc->sample_period == 1)))
1410 return X86_PMC_IDX_FIXED_BTS;
1411 949
1412 if (!x86_pmu.num_events_fixed) 950 n0 = cpuc->n_events;
1413 return -1; 951 n = collect_events(cpuc, event, false);
952 if (n < 0)
953 return n;
1414 954
955 ret = x86_schedule_events(cpuc, n, assign);
956 if (ret)
957 return ret;
1415 /* 958 /*
1416 * fixed counters do not take all possible filters 959 * copy new assignment, now we know it is possible
960 * will be used by hw_perf_enable()
1417 */ 961 */
1418 if (hwc->config & ARCH_PERFMON_EVENT_FILTER_MASK) 962 memcpy(cpuc->assign, assign, n*sizeof(int));
1419 return -1;
1420
1421 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
1422 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
1423 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
1424 return X86_PMC_IDX_FIXED_CPU_CYCLES;
1425 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
1426 return X86_PMC_IDX_FIXED_BUS_CYCLES;
1427
1428 return -1;
1429}
1430
1431/*
1432 * generic counter allocator: get next free counter
1433 */
1434static int
1435gen_get_event_idx(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
1436{
1437 int idx;
1438
1439 idx = find_first_zero_bit(cpuc->used_mask, x86_pmu.num_events);
1440 return idx == x86_pmu.num_events ? -1 : idx;
1441}
1442
1443/*
1444 * intel-specific counter allocator: check event constraints
1445 */
1446static int
1447intel_get_event_idx(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
1448{
1449 const struct event_constraint *event_constraint;
1450 int i, code;
1451
1452 if (!event_constraints)
1453 goto skip;
1454 963
1455 code = hwc->config & CORE_EVNTSEL_EVENT_MASK; 964 cpuc->n_events = n;
1456 965 cpuc->n_added = n - n0;
1457 for_each_event_constraint(event_constraint, event_constraints) {
1458 if (code == event_constraint->code) {
1459 for_each_bit(i, event_constraint->idxmsk, X86_PMC_IDX_MAX) {
1460 if (!test_and_set_bit(i, cpuc->used_mask))
1461 return i;
1462 }
1463 return -1;
1464 }
1465 }
1466skip:
1467 return gen_get_event_idx(cpuc, hwc);
1468}
1469
1470static int
1471x86_schedule_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
1472{
1473 int idx;
1474 966
1475 idx = fixed_mode_idx(hwc); 967 return 0;
1476 if (idx == X86_PMC_IDX_FIXED_BTS) {
1477 /* BTS is already occupied. */
1478 if (test_and_set_bit(idx, cpuc->used_mask))
1479 return -EAGAIN;
1480
1481 hwc->config_base = 0;
1482 hwc->event_base = 0;
1483 hwc->idx = idx;
1484 } else if (idx >= 0) {
1485 /*
1486 * Try to get the fixed event, if that is already taken
1487 * then try to get a generic event:
1488 */
1489 if (test_and_set_bit(idx, cpuc->used_mask))
1490 goto try_generic;
1491
1492 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1493 /*
1494 * We set it so that event_base + idx in wrmsr/rdmsr maps to
1495 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1496 */
1497 hwc->event_base =
1498 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1499 hwc->idx = idx;
1500 } else {
1501 idx = hwc->idx;
1502 /* Try to get the previous generic event again */
1503 if (idx == -1 || test_and_set_bit(idx, cpuc->used_mask)) {
1504try_generic:
1505 idx = x86_pmu.get_event_idx(cpuc, hwc);
1506 if (idx == -1)
1507 return -EAGAIN;
1508
1509 set_bit(idx, cpuc->used_mask);
1510 hwc->idx = idx;
1511 }
1512 hwc->config_base = x86_pmu.eventsel;
1513 hwc->event_base = x86_pmu.perfctr;
1514 }
1515
1516 return idx;
1517} 968}
1518 969
1519/* 970static int x86_pmu_start(struct perf_event *event)
1520 * Find a PMC slot for the freshly enabled / scheduled in event:
1521 */
1522static int x86_pmu_enable(struct perf_event *event)
1523{ 971{
1524 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1525 struct hw_perf_event *hwc = &event->hw; 972 struct hw_perf_event *hwc = &event->hw;
1526 int idx;
1527
1528 idx = x86_schedule_event(cpuc, hwc);
1529 if (idx < 0)
1530 return idx;
1531
1532 perf_events_lapic_init();
1533
1534 x86_pmu.disable(hwc, idx);
1535 973
1536 cpuc->events[idx] = event; 974 if (hwc->idx == -1)
1537 set_bit(idx, cpuc->active_mask); 975 return -EAGAIN;
1538 976
1539 x86_perf_event_set_period(event, hwc, idx); 977 x86_perf_event_set_period(event, hwc, hwc->idx);
1540 x86_pmu.enable(hwc, idx); 978 x86_pmu.enable(hwc, hwc->idx);
1541
1542 perf_event_update_userpage(event);
1543 979
1544 return 0; 980 return 0;
1545} 981}
@@ -1583,7 +1019,7 @@ void perf_event_print_debug(void)
1583 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); 1019 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1584 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); 1020 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1585 } 1021 }
1586 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); 1022 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1587 1023
1588 for (idx = 0; idx < x86_pmu.num_events; idx++) { 1024 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1589 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); 1025 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
@@ -1607,67 +1043,7 @@ void perf_event_print_debug(void)
1607 local_irq_restore(flags); 1043 local_irq_restore(flags);
1608} 1044}
1609 1045
1610static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc) 1046static void x86_pmu_stop(struct perf_event *event)
1611{
1612 struct debug_store *ds = cpuc->ds;
1613 struct bts_record {
1614 u64 from;
1615 u64 to;
1616 u64 flags;
1617 };
1618 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
1619 struct bts_record *at, *top;
1620 struct perf_output_handle handle;
1621 struct perf_event_header header;
1622 struct perf_sample_data data;
1623 struct pt_regs regs;
1624
1625 if (!event)
1626 return;
1627
1628 if (!ds)
1629 return;
1630
1631 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
1632 top = (struct bts_record *)(unsigned long)ds->bts_index;
1633
1634 if (top <= at)
1635 return;
1636
1637 ds->bts_index = ds->bts_buffer_base;
1638
1639
1640 data.period = event->hw.last_period;
1641 data.addr = 0;
1642 data.raw = NULL;
1643 regs.ip = 0;
1644
1645 /*
1646 * Prepare a generic sample, i.e. fill in the invariant fields.
1647 * We will overwrite the from and to address before we output
1648 * the sample.
1649 */
1650 perf_prepare_sample(&header, &data, event, &regs);
1651
1652 if (perf_output_begin(&handle, event,
1653 header.size * (top - at), 1, 1))
1654 return;
1655
1656 for (; at < top; at++) {
1657 data.ip = at->from;
1658 data.addr = at->to;
1659
1660 perf_output_sample(&handle, &header, &data, event);
1661 }
1662
1663 perf_output_end(&handle);
1664
1665 /* There's new data available. */
1666 event->hw.interrupts++;
1667 event->pending_kill = POLL_IN;
1668}
1669
1670static void x86_pmu_disable(struct perf_event *event)
1671{ 1047{
1672 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 1048 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1673 struct hw_perf_event *hwc = &event->hw; 1049 struct hw_perf_event *hwc = &event->hw;
@@ -1681,183 +1057,38 @@ static void x86_pmu_disable(struct perf_event *event)
1681 x86_pmu.disable(hwc, idx); 1057 x86_pmu.disable(hwc, idx);
1682 1058
1683 /* 1059 /*
1684 * Make sure the cleared pointer becomes visible before we
1685 * (potentially) free the event:
1686 */
1687 barrier();
1688
1689 /*
1690 * Drain the remaining delta count out of a event 1060 * Drain the remaining delta count out of a event
1691 * that we are disabling: 1061 * that we are disabling:
1692 */ 1062 */
1693 x86_perf_event_update(event, hwc, idx); 1063 x86_perf_event_update(event, hwc, idx);
1694 1064
1695 /* Drain the remaining BTS records. */
1696 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1697 intel_pmu_drain_bts_buffer(cpuc);
1698
1699 cpuc->events[idx] = NULL; 1065 cpuc->events[idx] = NULL;
1700 clear_bit(idx, cpuc->used_mask);
1701
1702 perf_event_update_userpage(event);
1703}
1704
1705/*
1706 * Save and restart an expired event. Called by NMI contexts,
1707 * so it has to be careful about preempting normal event ops:
1708 */
1709static int intel_pmu_save_and_restart(struct perf_event *event)
1710{
1711 struct hw_perf_event *hwc = &event->hw;
1712 int idx = hwc->idx;
1713 int ret;
1714
1715 x86_perf_event_update(event, hwc, idx);
1716 ret = x86_perf_event_set_period(event, hwc, idx);
1717
1718 if (event->state == PERF_EVENT_STATE_ACTIVE)
1719 intel_pmu_enable_event(hwc, idx);
1720
1721 return ret;
1722}
1723
1724static void intel_pmu_reset(void)
1725{
1726 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
1727 unsigned long flags;
1728 int idx;
1729
1730 if (!x86_pmu.num_events)
1731 return;
1732
1733 local_irq_save(flags);
1734
1735 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1736
1737 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1738 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1739 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1740 }
1741 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1742 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1743 }
1744 if (ds)
1745 ds->bts_index = ds->bts_buffer_base;
1746
1747 local_irq_restore(flags);
1748}
1749
1750static int p6_pmu_handle_irq(struct pt_regs *regs)
1751{
1752 struct perf_sample_data data;
1753 struct cpu_hw_events *cpuc;
1754 struct perf_event *event;
1755 struct hw_perf_event *hwc;
1756 int idx, handled = 0;
1757 u64 val;
1758
1759 data.addr = 0;
1760 data.raw = NULL;
1761
1762 cpuc = &__get_cpu_var(cpu_hw_events);
1763
1764 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1765 if (!test_bit(idx, cpuc->active_mask))
1766 continue;
1767
1768 event = cpuc->events[idx];
1769 hwc = &event->hw;
1770
1771 val = x86_perf_event_update(event, hwc, idx);
1772 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1773 continue;
1774
1775 /*
1776 * event overflow
1777 */
1778 handled = 1;
1779 data.period = event->hw.last_period;
1780
1781 if (!x86_perf_event_set_period(event, hwc, idx))
1782 continue;
1783
1784 if (perf_event_overflow(event, 1, &data, regs))
1785 p6_pmu_disable_event(hwc, idx);
1786 }
1787
1788 if (handled)
1789 inc_irq_stat(apic_perf_irqs);
1790
1791 return handled;
1792} 1066}
1793 1067
1794/* 1068static void x86_pmu_disable(struct perf_event *event)
1795 * This handler is triggered by the local APIC, so the APIC IRQ handling
1796 * rules apply:
1797 */
1798static int intel_pmu_handle_irq(struct pt_regs *regs)
1799{ 1069{
1800 struct perf_sample_data data; 1070 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1801 struct cpu_hw_events *cpuc; 1071 int i;
1802 int bit, loops;
1803 u64 ack, status;
1804
1805 data.addr = 0;
1806 data.raw = NULL;
1807
1808 cpuc = &__get_cpu_var(cpu_hw_events);
1809
1810 perf_disable();
1811 intel_pmu_drain_bts_buffer(cpuc);
1812 status = intel_pmu_get_status();
1813 if (!status) {
1814 perf_enable();
1815 return 0;
1816 }
1817
1818 loops = 0;
1819again:
1820 if (++loops > 100) {
1821 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1822 perf_event_print_debug();
1823 intel_pmu_reset();
1824 perf_enable();
1825 return 1;
1826 }
1827 1072
1828 inc_irq_stat(apic_perf_irqs); 1073 x86_pmu_stop(event);
1829 ack = status;
1830 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1831 struct perf_event *event = cpuc->events[bit];
1832 1074
1833 clear_bit(bit, (unsigned long *) &status); 1075 for (i = 0; i < cpuc->n_events; i++) {
1834 if (!test_bit(bit, cpuc->active_mask)) 1076 if (event == cpuc->event_list[i]) {
1835 continue;
1836 1077
1837 if (!intel_pmu_save_and_restart(event)) 1078 if (x86_pmu.put_event_constraints)
1838 continue; 1079 x86_pmu.put_event_constraints(cpuc, event);
1839 1080
1840 data.period = event->hw.last_period; 1081 while (++i < cpuc->n_events)
1082 cpuc->event_list[i-1] = cpuc->event_list[i];
1841 1083
1842 if (perf_event_overflow(event, 1, &data, regs)) 1084 --cpuc->n_events;
1843 intel_pmu_disable_event(&event->hw, bit); 1085 break;
1086 }
1844 } 1087 }
1845 1088 perf_event_update_userpage(event);
1846 intel_pmu_ack_status(ack);
1847
1848 /*
1849 * Repeat if there is more work to be done:
1850 */
1851 status = intel_pmu_get_status();
1852 if (status)
1853 goto again;
1854
1855 perf_enable();
1856
1857 return 1;
1858} 1089}
1859 1090
1860static int amd_pmu_handle_irq(struct pt_regs *regs) 1091static int x86_pmu_handle_irq(struct pt_regs *regs)
1861{ 1092{
1862 struct perf_sample_data data; 1093 struct perf_sample_data data;
1863 struct cpu_hw_events *cpuc; 1094 struct cpu_hw_events *cpuc;
@@ -1892,7 +1123,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs)
1892 continue; 1123 continue;
1893 1124
1894 if (perf_event_overflow(event, 1, &data, regs)) 1125 if (perf_event_overflow(event, 1, &data, regs))
1895 amd_pmu_disable_event(hwc, idx); 1126 x86_pmu.disable(hwc, idx);
1896 } 1127 }
1897 1128
1898 if (handled) 1129 if (handled)
@@ -1975,194 +1206,137 @@ static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1975 .priority = 1 1206 .priority = 1
1976}; 1207};
1977 1208
1978static __initconst struct x86_pmu p6_pmu = { 1209static struct event_constraint unconstrained;
1979 .name = "p6", 1210static struct event_constraint emptyconstraint;
1980 .handle_irq = p6_pmu_handle_irq,
1981 .disable_all = p6_pmu_disable_all,
1982 .enable_all = p6_pmu_enable_all,
1983 .enable = p6_pmu_enable_event,
1984 .disable = p6_pmu_disable_event,
1985 .eventsel = MSR_P6_EVNTSEL0,
1986 .perfctr = MSR_P6_PERFCTR0,
1987 .event_map = p6_pmu_event_map,
1988 .raw_event = p6_pmu_raw_event,
1989 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
1990 .apic = 1,
1991 .max_period = (1ULL << 31) - 1,
1992 .version = 0,
1993 .num_events = 2,
1994 /*
1995 * Events have 40 bits implemented. However they are designed such
1996 * that bits [32-39] are sign extensions of bit 31. As such the
1997 * effective width of a event for P6-like PMU is 32 bits only.
1998 *
1999 * See IA-32 Intel Architecture Software developer manual Vol 3B
2000 */
2001 .event_bits = 32,
2002 .event_mask = (1ULL << 32) - 1,
2003 .get_event_idx = intel_get_event_idx,
2004};
2005 1211
2006static __initconst struct x86_pmu intel_pmu = { 1212static struct event_constraint *
2007 .name = "Intel", 1213x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2008 .handle_irq = intel_pmu_handle_irq, 1214{
2009 .disable_all = intel_pmu_disable_all, 1215 struct event_constraint *c;
2010 .enable_all = intel_pmu_enable_all,
2011 .enable = intel_pmu_enable_event,
2012 .disable = intel_pmu_disable_event,
2013 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2014 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2015 .event_map = intel_pmu_event_map,
2016 .raw_event = intel_pmu_raw_event,
2017 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2018 .apic = 1,
2019 /*
2020 * Intel PMCs cannot be accessed sanely above 32 bit width,
2021 * so we install an artificial 1<<31 period regardless of
2022 * the generic event period:
2023 */
2024 .max_period = (1ULL << 31) - 1,
2025 .enable_bts = intel_pmu_enable_bts,
2026 .disable_bts = intel_pmu_disable_bts,
2027 .get_event_idx = intel_get_event_idx,
2028};
2029 1216
2030static __initconst struct x86_pmu amd_pmu = { 1217 if (x86_pmu.event_constraints) {
2031 .name = "AMD", 1218 for_each_event_constraint(c, x86_pmu.event_constraints) {
2032 .handle_irq = amd_pmu_handle_irq, 1219 if ((event->hw.config & c->cmask) == c->code)
2033 .disable_all = amd_pmu_disable_all, 1220 return c;
2034 .enable_all = amd_pmu_enable_all, 1221 }
2035 .enable = amd_pmu_enable_event, 1222 }
2036 .disable = amd_pmu_disable_event, 1223
2037 .eventsel = MSR_K7_EVNTSEL0, 1224 return &unconstrained;
2038 .perfctr = MSR_K7_PERFCTR0, 1225}
2039 .event_map = amd_pmu_event_map,
2040 .raw_event = amd_pmu_raw_event,
2041 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
2042 .num_events = 4,
2043 .event_bits = 48,
2044 .event_mask = (1ULL << 48) - 1,
2045 .apic = 1,
2046 /* use highest bit to detect overflow */
2047 .max_period = (1ULL << 47) - 1,
2048 .get_event_idx = gen_get_event_idx,
2049};
2050 1226
2051static __init int p6_pmu_init(void) 1227static int x86_event_sched_in(struct perf_event *event,
1228 struct perf_cpu_context *cpuctx)
2052{ 1229{
2053 switch (boot_cpu_data.x86_model) { 1230 int ret = 0;
2054 case 1:
2055 case 3: /* Pentium Pro */
2056 case 5:
2057 case 6: /* Pentium II */
2058 case 7:
2059 case 8:
2060 case 11: /* Pentium III */
2061 event_constraints = intel_p6_event_constraints;
2062 break;
2063 case 9:
2064 case 13:
2065 /* Pentium M */
2066 event_constraints = intel_p6_event_constraints;
2067 break;
2068 default:
2069 pr_cont("unsupported p6 CPU model %d ",
2070 boot_cpu_data.x86_model);
2071 return -ENODEV;
2072 }
2073 1231
2074 x86_pmu = p6_pmu; 1232 event->state = PERF_EVENT_STATE_ACTIVE;
1233 event->oncpu = smp_processor_id();
1234 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
2075 1235
2076 return 0; 1236 if (!is_x86_event(event))
1237 ret = event->pmu->enable(event);
1238
1239 if (!ret && !is_software_event(event))
1240 cpuctx->active_oncpu++;
1241
1242 if (!ret && event->attr.exclusive)
1243 cpuctx->exclusive = 1;
1244
1245 return ret;
2077} 1246}
2078 1247
2079static __init int intel_pmu_init(void) 1248static void x86_event_sched_out(struct perf_event *event,
1249 struct perf_cpu_context *cpuctx)
2080{ 1250{
2081 union cpuid10_edx edx; 1251 event->state = PERF_EVENT_STATE_INACTIVE;
2082 union cpuid10_eax eax; 1252 event->oncpu = -1;
2083 unsigned int unused;
2084 unsigned int ebx;
2085 int version;
2086
2087 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2088 /* check for P6 processor family */
2089 if (boot_cpu_data.x86 == 6) {
2090 return p6_pmu_init();
2091 } else {
2092 return -ENODEV;
2093 }
2094 }
2095 1253
2096 /* 1254 if (!is_x86_event(event))
2097 * Check whether the Architectural PerfMon supports 1255 event->pmu->disable(event);
2098 * Branch Misses Retired hw_event or not.
2099 */
2100 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
2101 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
2102 return -ENODEV;
2103 1256
2104 version = eax.split.version_id; 1257 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
2105 if (version < 2)
2106 return -ENODEV;
2107 1258
2108 x86_pmu = intel_pmu; 1259 if (!is_software_event(event))
2109 x86_pmu.version = version; 1260 cpuctx->active_oncpu--;
2110 x86_pmu.num_events = eax.split.num_events;
2111 x86_pmu.event_bits = eax.split.bit_width;
2112 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
2113 1261
2114 /* 1262 if (event->attr.exclusive || !cpuctx->active_oncpu)
2115 * Quirk: v2 perfmon does not report fixed-purpose events, so 1263 cpuctx->exclusive = 0;
2116 * assume at least 3 events: 1264}
2117 */
2118 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
2119 1265
1266/*
1267 * Called to enable a whole group of events.
1268 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1269 * Assumes the caller has disabled interrupts and has
1270 * frozen the PMU with hw_perf_save_disable.
1271 *
1272 * called with PMU disabled. If successful and return value 1,
1273 * then guaranteed to call perf_enable() and hw_perf_enable()
1274 */
1275int hw_perf_group_sched_in(struct perf_event *leader,
1276 struct perf_cpu_context *cpuctx,
1277 struct perf_event_context *ctx)
1278{
1279 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1280 struct perf_event *sub;
1281 int assign[X86_PMC_IDX_MAX];
1282 int n0, n1, ret;
1283
1284 /* n0 = total number of events */
1285 n0 = collect_events(cpuc, leader, true);
1286 if (n0 < 0)
1287 return n0;
1288
1289 ret = x86_schedule_events(cpuc, n0, assign);
1290 if (ret)
1291 return ret;
1292
1293 ret = x86_event_sched_in(leader, cpuctx);
1294 if (ret)
1295 return ret;
1296
1297 n1 = 1;
1298 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1299 if (sub->state > PERF_EVENT_STATE_OFF) {
1300 ret = x86_event_sched_in(sub, cpuctx);
1301 if (ret)
1302 goto undo;
1303 ++n1;
1304 }
1305 }
2120 /* 1306 /*
2121 * Install the hw-cache-events table: 1307 * copy new assignment, now we know it is possible
1308 * will be used by hw_perf_enable()
2122 */ 1309 */
2123 switch (boot_cpu_data.x86_model) { 1310 memcpy(cpuc->assign, assign, n0*sizeof(int));
2124 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2125 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2126 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2127 case 29: /* six-core 45 nm xeon "Dunnington" */
2128 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2129 sizeof(hw_cache_event_ids));
2130
2131 pr_cont("Core2 events, ");
2132 event_constraints = intel_core_event_constraints;
2133 break;
2134 default:
2135 case 26:
2136 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2137 sizeof(hw_cache_event_ids));
2138 1311
2139 event_constraints = intel_nehalem_event_constraints; 1312 cpuc->n_events = n0;
2140 pr_cont("Nehalem/Corei7 events, "); 1313 cpuc->n_added = n1;
2141 break; 1314 ctx->nr_active += n1;
2142 case 28:
2143 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2144 sizeof(hw_cache_event_ids));
2145 1315
2146 pr_cont("Atom events, "); 1316 /*
2147 break; 1317 * 1 means successful and events are active
1318 * This is not quite true because we defer
1319 * actual activation until hw_perf_enable() but
1320 * this way we* ensure caller won't try to enable
1321 * individual events
1322 */
1323 return 1;
1324undo:
1325 x86_event_sched_out(leader, cpuctx);
1326 n0 = 1;
1327 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1328 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1329 x86_event_sched_out(sub, cpuctx);
1330 if (++n0 == n1)
1331 break;
1332 }
2148 } 1333 }
2149 return 0; 1334 return ret;
2150} 1335}
2151 1336
2152static __init int amd_pmu_init(void) 1337#include "perf_event_amd.c"
2153{ 1338#include "perf_event_p6.c"
2154 /* Performance-monitoring supported from K7 and later: */ 1339#include "perf_event_intel.c"
2155 if (boot_cpu_data.x86 < 6)
2156 return -ENODEV;
2157
2158 x86_pmu = amd_pmu;
2159
2160 /* Events are common for all AMDs */
2161 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
2162 sizeof(hw_cache_event_ids));
2163
2164 return 0;
2165}
2166 1340
2167static void __init pmu_check_apic(void) 1341static void __init pmu_check_apic(void)
2168{ 1342{
@@ -2176,6 +1350,7 @@ static void __init pmu_check_apic(void)
2176 1350
2177void __init init_hw_perf_events(void) 1351void __init init_hw_perf_events(void)
2178{ 1352{
1353 struct event_constraint *c;
2179 int err; 1354 int err;
2180 1355
2181 pr_info("Performance Events: "); 1356 pr_info("Performance Events: ");
@@ -2220,6 +1395,20 @@ void __init init_hw_perf_events(void)
2220 perf_events_lapic_init(); 1395 perf_events_lapic_init();
2221 register_die_notifier(&perf_event_nmi_notifier); 1396 register_die_notifier(&perf_event_nmi_notifier);
2222 1397
1398 unconstrained = (struct event_constraint)
1399 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1400 0, x86_pmu.num_events);
1401
1402 if (x86_pmu.event_constraints) {
1403 for_each_event_constraint(c, x86_pmu.event_constraints) {
1404 if (c->cmask != INTEL_ARCH_FIXED_MASK)
1405 continue;
1406
1407 c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1408 c->weight += x86_pmu.num_events;
1409 }
1410 }
1411
2223 pr_info("... version: %d\n", x86_pmu.version); 1412 pr_info("... version: %d\n", x86_pmu.version);
2224 pr_info("... bit width: %d\n", x86_pmu.event_bits); 1413 pr_info("... bit width: %d\n", x86_pmu.event_bits);
2225 pr_info("... generic registers: %d\n", x86_pmu.num_events); 1414 pr_info("... generic registers: %d\n", x86_pmu.num_events);
@@ -2237,50 +1426,79 @@ static inline void x86_pmu_read(struct perf_event *event)
2237static const struct pmu pmu = { 1426static const struct pmu pmu = {
2238 .enable = x86_pmu_enable, 1427 .enable = x86_pmu_enable,
2239 .disable = x86_pmu_disable, 1428 .disable = x86_pmu_disable,
1429 .start = x86_pmu_start,
1430 .stop = x86_pmu_stop,
2240 .read = x86_pmu_read, 1431 .read = x86_pmu_read,
2241 .unthrottle = x86_pmu_unthrottle, 1432 .unthrottle = x86_pmu_unthrottle,
2242}; 1433};
2243 1434
2244static int 1435/*
2245validate_event(struct cpu_hw_events *cpuc, struct perf_event *event) 1436 * validate a single event group
2246{ 1437 *
2247 struct hw_perf_event fake_event = event->hw; 1438 * validation include:
2248 1439 * - check events are compatible which each other
2249 if (event->pmu && event->pmu != &pmu) 1440 * - events do not compete for the same counter
2250 return 0; 1441 * - number of events <= number of counters
2251 1442 *
2252 return x86_schedule_event(cpuc, &fake_event) >= 0; 1443 * validation ensures the group can be loaded onto the
2253} 1444 * PMU if it was the only group available.
2254 1445 */
2255static int validate_group(struct perf_event *event) 1446static int validate_group(struct perf_event *event)
2256{ 1447{
2257 struct perf_event *sibling, *leader = event->group_leader; 1448 struct perf_event *leader = event->group_leader;
2258 struct cpu_hw_events fake_pmu; 1449 struct cpu_hw_events *fake_cpuc;
1450 int ret, n;
2259 1451
2260 memset(&fake_pmu, 0, sizeof(fake_pmu)); 1452 ret = -ENOMEM;
1453 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1454 if (!fake_cpuc)
1455 goto out;
1456
1457 /*
1458 * the event is not yet connected with its
1459 * siblings therefore we must first collect
1460 * existing siblings, then add the new event
1461 * before we can simulate the scheduling
1462 */
1463 ret = -ENOSPC;
1464 n = collect_events(fake_cpuc, leader, true);
1465 if (n < 0)
1466 goto out_free;
2261 1467
2262 if (!validate_event(&fake_pmu, leader)) 1468 fake_cpuc->n_events = n;
2263 return -ENOSPC; 1469 n = collect_events(fake_cpuc, event, false);
1470 if (n < 0)
1471 goto out_free;
2264 1472
2265 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 1473 fake_cpuc->n_events = n;
2266 if (!validate_event(&fake_pmu, sibling))
2267 return -ENOSPC;
2268 }
2269 1474
2270 if (!validate_event(&fake_pmu, event)) 1475 ret = x86_schedule_events(fake_cpuc, n, NULL);
2271 return -ENOSPC;
2272 1476
2273 return 0; 1477out_free:
1478 kfree(fake_cpuc);
1479out:
1480 return ret;
2274} 1481}
2275 1482
2276const struct pmu *hw_perf_event_init(struct perf_event *event) 1483const struct pmu *hw_perf_event_init(struct perf_event *event)
2277{ 1484{
1485 const struct pmu *tmp;
2278 int err; 1486 int err;
2279 1487
2280 err = __hw_perf_event_init(event); 1488 err = __hw_perf_event_init(event);
2281 if (!err) { 1489 if (!err) {
1490 /*
1491 * we temporarily connect event to its pmu
1492 * such that validate_group() can classify
1493 * it as an x86 event using is_x86_event()
1494 */
1495 tmp = event->pmu;
1496 event->pmu = &pmu;
1497
2282 if (event->group_leader != event) 1498 if (event->group_leader != event)
2283 err = validate_group(event); 1499 err = validate_group(event);
1500
1501 event->pmu = tmp;
2284 } 1502 }
2285 if (err) { 1503 if (err) {
2286 if (event->destroy) 1504 if (event->destroy)
@@ -2304,7 +1522,6 @@ void callchain_store(struct perf_callchain_entry *entry, u64 ip)
2304 1522
2305static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); 1523static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
2306static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); 1524static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
2307static DEFINE_PER_CPU(int, in_ignored_frame);
2308 1525
2309 1526
2310static void 1527static void
@@ -2320,10 +1537,6 @@ static void backtrace_warning(void *data, char *msg)
2320 1537
2321static int backtrace_stack(void *data, char *name) 1538static int backtrace_stack(void *data, char *name)
2322{ 1539{
2323 per_cpu(in_ignored_frame, smp_processor_id()) =
2324 x86_is_stack_id(NMI_STACK, name) ||
2325 x86_is_stack_id(DEBUG_STACK, name);
2326
2327 return 0; 1540 return 0;
2328} 1541}
2329 1542
@@ -2331,9 +1544,6 @@ static void backtrace_address(void *data, unsigned long addr, int reliable)
2331{ 1544{
2332 struct perf_callchain_entry *entry = data; 1545 struct perf_callchain_entry *entry = data;
2333 1546
2334 if (per_cpu(in_ignored_frame, smp_processor_id()))
2335 return;
2336
2337 if (reliable) 1547 if (reliable)
2338 callchain_store(entry, addr); 1548 callchain_store(entry, addr);
2339} 1549}
@@ -2440,9 +1650,6 @@ perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2440 1650
2441 is_user = user_mode(regs); 1651 is_user = user_mode(regs);
2442 1652
2443 if (!current || current->pid == 0)
2444 return;
2445
2446 if (is_user && current->state != TASK_RUNNING) 1653 if (is_user && current->state != TASK_RUNNING)
2447 return; 1654 return;
2448 1655
@@ -2472,4 +1679,25 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2472void hw_perf_event_setup_online(int cpu) 1679void hw_perf_event_setup_online(int cpu)
2473{ 1680{
2474 init_debug_store_on_cpu(cpu); 1681 init_debug_store_on_cpu(cpu);
1682
1683 switch (boot_cpu_data.x86_vendor) {
1684 case X86_VENDOR_AMD:
1685 amd_pmu_cpu_online(cpu);
1686 break;
1687 default:
1688 return;
1689 }
1690}
1691
1692void hw_perf_event_setup_offline(int cpu)
1693{
1694 init_debug_store_on_cpu(cpu);
1695
1696 switch (boot_cpu_data.x86_vendor) {
1697 case X86_VENDOR_AMD:
1698 amd_pmu_cpu_offline(cpu);
1699 break;
1700 default:
1701 return;
1702 }
2475} 1703}
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
new file mode 100644
index 000000000000..8f3dbfda3c4f
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -0,0 +1,416 @@
1#ifdef CONFIG_CPU_SUP_AMD
2
3static DEFINE_RAW_SPINLOCK(amd_nb_lock);
4
5static __initconst u64 amd_hw_cache_event_ids
6 [PERF_COUNT_HW_CACHE_MAX]
7 [PERF_COUNT_HW_CACHE_OP_MAX]
8 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
9{
10 [ C(L1D) ] = {
11 [ C(OP_READ) ] = {
12 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
13 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
14 },
15 [ C(OP_WRITE) ] = {
16 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
17 [ C(RESULT_MISS) ] = 0,
18 },
19 [ C(OP_PREFETCH) ] = {
20 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
21 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
22 },
23 },
24 [ C(L1I ) ] = {
25 [ C(OP_READ) ] = {
26 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
27 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
28 },
29 [ C(OP_WRITE) ] = {
30 [ C(RESULT_ACCESS) ] = -1,
31 [ C(RESULT_MISS) ] = -1,
32 },
33 [ C(OP_PREFETCH) ] = {
34 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
35 [ C(RESULT_MISS) ] = 0,
36 },
37 },
38 [ C(LL ) ] = {
39 [ C(OP_READ) ] = {
40 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
41 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
42 },
43 [ C(OP_WRITE) ] = {
44 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
45 [ C(RESULT_MISS) ] = 0,
46 },
47 [ C(OP_PREFETCH) ] = {
48 [ C(RESULT_ACCESS) ] = 0,
49 [ C(RESULT_MISS) ] = 0,
50 },
51 },
52 [ C(DTLB) ] = {
53 [ C(OP_READ) ] = {
54 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
55 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
56 },
57 [ C(OP_WRITE) ] = {
58 [ C(RESULT_ACCESS) ] = 0,
59 [ C(RESULT_MISS) ] = 0,
60 },
61 [ C(OP_PREFETCH) ] = {
62 [ C(RESULT_ACCESS) ] = 0,
63 [ C(RESULT_MISS) ] = 0,
64 },
65 },
66 [ C(ITLB) ] = {
67 [ C(OP_READ) ] = {
68 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
69 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
70 },
71 [ C(OP_WRITE) ] = {
72 [ C(RESULT_ACCESS) ] = -1,
73 [ C(RESULT_MISS) ] = -1,
74 },
75 [ C(OP_PREFETCH) ] = {
76 [ C(RESULT_ACCESS) ] = -1,
77 [ C(RESULT_MISS) ] = -1,
78 },
79 },
80 [ C(BPU ) ] = {
81 [ C(OP_READ) ] = {
82 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
83 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
84 },
85 [ C(OP_WRITE) ] = {
86 [ C(RESULT_ACCESS) ] = -1,
87 [ C(RESULT_MISS) ] = -1,
88 },
89 [ C(OP_PREFETCH) ] = {
90 [ C(RESULT_ACCESS) ] = -1,
91 [ C(RESULT_MISS) ] = -1,
92 },
93 },
94};
95
96/*
97 * AMD Performance Monitor K7 and later.
98 */
99static const u64 amd_perfmon_event_map[] =
100{
101 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
102 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
103 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
104 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
105 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
106 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
107};
108
109static u64 amd_pmu_event_map(int hw_event)
110{
111 return amd_perfmon_event_map[hw_event];
112}
113
114static u64 amd_pmu_raw_event(u64 hw_event)
115{
116#define K7_EVNTSEL_EVENT_MASK 0xF000000FFULL
117#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
118#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
119#define K7_EVNTSEL_INV_MASK 0x000800000ULL
120#define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
121
122#define K7_EVNTSEL_MASK \
123 (K7_EVNTSEL_EVENT_MASK | \
124 K7_EVNTSEL_UNIT_MASK | \
125 K7_EVNTSEL_EDGE_MASK | \
126 K7_EVNTSEL_INV_MASK | \
127 K7_EVNTSEL_REG_MASK)
128
129 return hw_event & K7_EVNTSEL_MASK;
130}
131
132/*
133 * AMD64 events are detected based on their event codes.
134 */
135static inline int amd_is_nb_event(struct hw_perf_event *hwc)
136{
137 return (hwc->config & 0xe0) == 0xe0;
138}
139
140static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
141 struct perf_event *event)
142{
143 struct hw_perf_event *hwc = &event->hw;
144 struct amd_nb *nb = cpuc->amd_nb;
145 int i;
146
147 /*
148 * only care about NB events
149 */
150 if (!(nb && amd_is_nb_event(hwc)))
151 return;
152
153 /*
154 * need to scan whole list because event may not have
155 * been assigned during scheduling
156 *
157 * no race condition possible because event can only
158 * be removed on one CPU at a time AND PMU is disabled
159 * when we come here
160 */
161 for (i = 0; i < x86_pmu.num_events; i++) {
162 if (nb->owners[i] == event) {
163 cmpxchg(nb->owners+i, event, NULL);
164 break;
165 }
166 }
167}
168
169 /*
170 * AMD64 NorthBridge events need special treatment because
171 * counter access needs to be synchronized across all cores
172 * of a package. Refer to BKDG section 3.12
173 *
174 * NB events are events measuring L3 cache, Hypertransport
175 * traffic. They are identified by an event code >= 0xe00.
176 * They measure events on the NorthBride which is shared
177 * by all cores on a package. NB events are counted on a
178 * shared set of counters. When a NB event is programmed
179 * in a counter, the data actually comes from a shared
180 * counter. Thus, access to those counters needs to be
181 * synchronized.
182 *
183 * We implement the synchronization such that no two cores
184 * can be measuring NB events using the same counters. Thus,
185 * we maintain a per-NB allocation table. The available slot
186 * is propagated using the event_constraint structure.
187 *
188 * We provide only one choice for each NB event based on
189 * the fact that only NB events have restrictions. Consequently,
190 * if a counter is available, there is a guarantee the NB event
191 * will be assigned to it. If no slot is available, an empty
192 * constraint is returned and scheduling will eventually fail
193 * for this event.
194 *
195 * Note that all cores attached the same NB compete for the same
196 * counters to host NB events, this is why we use atomic ops. Some
197 * multi-chip CPUs may have more than one NB.
198 *
199 * Given that resources are allocated (cmpxchg), they must be
200 * eventually freed for others to use. This is accomplished by
201 * calling amd_put_event_constraints().
202 *
203 * Non NB events are not impacted by this restriction.
204 */
205static struct event_constraint *
206amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
207{
208 struct hw_perf_event *hwc = &event->hw;
209 struct amd_nb *nb = cpuc->amd_nb;
210 struct perf_event *old = NULL;
211 int max = x86_pmu.num_events;
212 int i, j, k = -1;
213
214 /*
215 * if not NB event or no NB, then no constraints
216 */
217 if (!(nb && amd_is_nb_event(hwc)))
218 return &unconstrained;
219
220 /*
221 * detect if already present, if so reuse
222 *
223 * cannot merge with actual allocation
224 * because of possible holes
225 *
226 * event can already be present yet not assigned (in hwc->idx)
227 * because of successive calls to x86_schedule_events() from
228 * hw_perf_group_sched_in() without hw_perf_enable()
229 */
230 for (i = 0; i < max; i++) {
231 /*
232 * keep track of first free slot
233 */
234 if (k == -1 && !nb->owners[i])
235 k = i;
236
237 /* already present, reuse */
238 if (nb->owners[i] == event)
239 goto done;
240 }
241 /*
242 * not present, so grab a new slot
243 * starting either at:
244 */
245 if (hwc->idx != -1) {
246 /* previous assignment */
247 i = hwc->idx;
248 } else if (k != -1) {
249 /* start from free slot found */
250 i = k;
251 } else {
252 /*
253 * event not found, no slot found in
254 * first pass, try again from the
255 * beginning
256 */
257 i = 0;
258 }
259 j = i;
260 do {
261 old = cmpxchg(nb->owners+i, NULL, event);
262 if (!old)
263 break;
264 if (++i == max)
265 i = 0;
266 } while (i != j);
267done:
268 if (!old)
269 return &nb->event_constraints[i];
270
271 return &emptyconstraint;
272}
273
274static __initconst struct x86_pmu amd_pmu = {
275 .name = "AMD",
276 .handle_irq = x86_pmu_handle_irq,
277 .disable_all = x86_pmu_disable_all,
278 .enable_all = x86_pmu_enable_all,
279 .enable = x86_pmu_enable_event,
280 .disable = x86_pmu_disable_event,
281 .eventsel = MSR_K7_EVNTSEL0,
282 .perfctr = MSR_K7_PERFCTR0,
283 .event_map = amd_pmu_event_map,
284 .raw_event = amd_pmu_raw_event,
285 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
286 .num_events = 4,
287 .event_bits = 48,
288 .event_mask = (1ULL << 48) - 1,
289 .apic = 1,
290 /* use highest bit to detect overflow */
291 .max_period = (1ULL << 47) - 1,
292 .get_event_constraints = amd_get_event_constraints,
293 .put_event_constraints = amd_put_event_constraints
294};
295
296static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
297{
298 struct amd_nb *nb;
299 int i;
300
301 nb = kmalloc(sizeof(struct amd_nb), GFP_KERNEL);
302 if (!nb)
303 return NULL;
304
305 memset(nb, 0, sizeof(*nb));
306 nb->nb_id = nb_id;
307
308 /*
309 * initialize all possible NB constraints
310 */
311 for (i = 0; i < x86_pmu.num_events; i++) {
312 set_bit(i, nb->event_constraints[i].idxmsk);
313 nb->event_constraints[i].weight = 1;
314 }
315 return nb;
316}
317
318static void amd_pmu_cpu_online(int cpu)
319{
320 struct cpu_hw_events *cpu1, *cpu2;
321 struct amd_nb *nb = NULL;
322 int i, nb_id;
323
324 if (boot_cpu_data.x86_max_cores < 2)
325 return;
326
327 /*
328 * function may be called too early in the
329 * boot process, in which case nb_id is bogus
330 */
331 nb_id = amd_get_nb_id(cpu);
332 if (nb_id == BAD_APICID)
333 return;
334
335 cpu1 = &per_cpu(cpu_hw_events, cpu);
336 cpu1->amd_nb = NULL;
337
338 raw_spin_lock(&amd_nb_lock);
339
340 for_each_online_cpu(i) {
341 cpu2 = &per_cpu(cpu_hw_events, i);
342 nb = cpu2->amd_nb;
343 if (!nb)
344 continue;
345 if (nb->nb_id == nb_id)
346 goto found;
347 }
348
349 nb = amd_alloc_nb(cpu, nb_id);
350 if (!nb) {
351 pr_err("perf_events: failed NB allocation for CPU%d\n", cpu);
352 raw_spin_unlock(&amd_nb_lock);
353 return;
354 }
355found:
356 nb->refcnt++;
357 cpu1->amd_nb = nb;
358
359 raw_spin_unlock(&amd_nb_lock);
360}
361
362static void amd_pmu_cpu_offline(int cpu)
363{
364 struct cpu_hw_events *cpuhw;
365
366 if (boot_cpu_data.x86_max_cores < 2)
367 return;
368
369 cpuhw = &per_cpu(cpu_hw_events, cpu);
370
371 raw_spin_lock(&amd_nb_lock);
372
373 if (--cpuhw->amd_nb->refcnt == 0)
374 kfree(cpuhw->amd_nb);
375
376 cpuhw->amd_nb = NULL;
377
378 raw_spin_unlock(&amd_nb_lock);
379}
380
381static __init int amd_pmu_init(void)
382{
383 /* Performance-monitoring supported from K7 and later: */
384 if (boot_cpu_data.x86 < 6)
385 return -ENODEV;
386
387 x86_pmu = amd_pmu;
388
389 /* Events are common for all AMDs */
390 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
391 sizeof(hw_cache_event_ids));
392
393 /*
394 * explicitly initialize the boot cpu, other cpus will get
395 * the cpu hotplug callbacks from smp_init()
396 */
397 amd_pmu_cpu_online(smp_processor_id());
398 return 0;
399}
400
401#else /* CONFIG_CPU_SUP_AMD */
402
403static int amd_pmu_init(void)
404{
405 return 0;
406}
407
408static void amd_pmu_cpu_online(int cpu)
409{
410}
411
412static void amd_pmu_cpu_offline(int cpu)
413{
414}
415
416#endif
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
new file mode 100644
index 000000000000..4fbdfe5708d9
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -0,0 +1,982 @@
1#ifdef CONFIG_CPU_SUP_INTEL
2
3/*
4 * Intel PerfMon, used on Core and later.
5 */
6static const u64 intel_perfmon_event_map[] =
7{
8 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
9 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
10 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
11 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
12 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
13 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
14 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
15};
16
17static struct event_constraint intel_core_event_constraints[] =
18{
19 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
20 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
21 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
22 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
23 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
24 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
25 EVENT_CONSTRAINT_END
26};
27
28static struct event_constraint intel_core2_event_constraints[] =
29{
30 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
31 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
32 /*
33 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
34 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
35 * ratio between these counters.
36 */
37 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
38 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
46 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
47 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
48 EVENT_CONSTRAINT_END
49};
50
51static struct event_constraint intel_nehalem_event_constraints[] =
52{
53 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
54 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
55 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
56 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
57 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
58 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
59 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
60 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
61 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
62 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
63 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
64 EVENT_CONSTRAINT_END
65};
66
67static struct event_constraint intel_westmere_event_constraints[] =
68{
69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
71 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
72 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
73 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
74 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
75 EVENT_CONSTRAINT_END
76};
77
78static struct event_constraint intel_gen_event_constraints[] =
79{
80 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
81 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
82 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
83 EVENT_CONSTRAINT_END
84};
85
86static u64 intel_pmu_event_map(int hw_event)
87{
88 return intel_perfmon_event_map[hw_event];
89}
90
91static __initconst u64 westmere_hw_cache_event_ids
92 [PERF_COUNT_HW_CACHE_MAX]
93 [PERF_COUNT_HW_CACHE_OP_MAX]
94 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
95{
96 [ C(L1D) ] = {
97 [ C(OP_READ) ] = {
98 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
99 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
100 },
101 [ C(OP_WRITE) ] = {
102 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
103 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
104 },
105 [ C(OP_PREFETCH) ] = {
106 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
107 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
108 },
109 },
110 [ C(L1I ) ] = {
111 [ C(OP_READ) ] = {
112 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
113 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
114 },
115 [ C(OP_WRITE) ] = {
116 [ C(RESULT_ACCESS) ] = -1,
117 [ C(RESULT_MISS) ] = -1,
118 },
119 [ C(OP_PREFETCH) ] = {
120 [ C(RESULT_ACCESS) ] = 0x0,
121 [ C(RESULT_MISS) ] = 0x0,
122 },
123 },
124 [ C(LL ) ] = {
125 [ C(OP_READ) ] = {
126 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
127 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
128 },
129 [ C(OP_WRITE) ] = {
130 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
131 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
132 },
133 [ C(OP_PREFETCH) ] = {
134 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
135 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
136 },
137 },
138 [ C(DTLB) ] = {
139 [ C(OP_READ) ] = {
140 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
141 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
142 },
143 [ C(OP_WRITE) ] = {
144 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
145 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
146 },
147 [ C(OP_PREFETCH) ] = {
148 [ C(RESULT_ACCESS) ] = 0x0,
149 [ C(RESULT_MISS) ] = 0x0,
150 },
151 },
152 [ C(ITLB) ] = {
153 [ C(OP_READ) ] = {
154 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
155 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
156 },
157 [ C(OP_WRITE) ] = {
158 [ C(RESULT_ACCESS) ] = -1,
159 [ C(RESULT_MISS) ] = -1,
160 },
161 [ C(OP_PREFETCH) ] = {
162 [ C(RESULT_ACCESS) ] = -1,
163 [ C(RESULT_MISS) ] = -1,
164 },
165 },
166 [ C(BPU ) ] = {
167 [ C(OP_READ) ] = {
168 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
169 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
170 },
171 [ C(OP_WRITE) ] = {
172 [ C(RESULT_ACCESS) ] = -1,
173 [ C(RESULT_MISS) ] = -1,
174 },
175 [ C(OP_PREFETCH) ] = {
176 [ C(RESULT_ACCESS) ] = -1,
177 [ C(RESULT_MISS) ] = -1,
178 },
179 },
180};
181
182static __initconst u64 nehalem_hw_cache_event_ids
183 [PERF_COUNT_HW_CACHE_MAX]
184 [PERF_COUNT_HW_CACHE_OP_MAX]
185 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
186{
187 [ C(L1D) ] = {
188 [ C(OP_READ) ] = {
189 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
190 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
191 },
192 [ C(OP_WRITE) ] = {
193 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
194 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
195 },
196 [ C(OP_PREFETCH) ] = {
197 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
198 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
199 },
200 },
201 [ C(L1I ) ] = {
202 [ C(OP_READ) ] = {
203 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
204 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
205 },
206 [ C(OP_WRITE) ] = {
207 [ C(RESULT_ACCESS) ] = -1,
208 [ C(RESULT_MISS) ] = -1,
209 },
210 [ C(OP_PREFETCH) ] = {
211 [ C(RESULT_ACCESS) ] = 0x0,
212 [ C(RESULT_MISS) ] = 0x0,
213 },
214 },
215 [ C(LL ) ] = {
216 [ C(OP_READ) ] = {
217 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
218 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
219 },
220 [ C(OP_WRITE) ] = {
221 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
222 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
223 },
224 [ C(OP_PREFETCH) ] = {
225 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
226 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
227 },
228 },
229 [ C(DTLB) ] = {
230 [ C(OP_READ) ] = {
231 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
232 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
233 },
234 [ C(OP_WRITE) ] = {
235 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
236 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
237 },
238 [ C(OP_PREFETCH) ] = {
239 [ C(RESULT_ACCESS) ] = 0x0,
240 [ C(RESULT_MISS) ] = 0x0,
241 },
242 },
243 [ C(ITLB) ] = {
244 [ C(OP_READ) ] = {
245 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
246 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
247 },
248 [ C(OP_WRITE) ] = {
249 [ C(RESULT_ACCESS) ] = -1,
250 [ C(RESULT_MISS) ] = -1,
251 },
252 [ C(OP_PREFETCH) ] = {
253 [ C(RESULT_ACCESS) ] = -1,
254 [ C(RESULT_MISS) ] = -1,
255 },
256 },
257 [ C(BPU ) ] = {
258 [ C(OP_READ) ] = {
259 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
260 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
261 },
262 [ C(OP_WRITE) ] = {
263 [ C(RESULT_ACCESS) ] = -1,
264 [ C(RESULT_MISS) ] = -1,
265 },
266 [ C(OP_PREFETCH) ] = {
267 [ C(RESULT_ACCESS) ] = -1,
268 [ C(RESULT_MISS) ] = -1,
269 },
270 },
271};
272
273static __initconst u64 core2_hw_cache_event_ids
274 [PERF_COUNT_HW_CACHE_MAX]
275 [PERF_COUNT_HW_CACHE_OP_MAX]
276 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
277{
278 [ C(L1D) ] = {
279 [ C(OP_READ) ] = {
280 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
281 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
282 },
283 [ C(OP_WRITE) ] = {
284 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
285 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
286 },
287 [ C(OP_PREFETCH) ] = {
288 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
289 [ C(RESULT_MISS) ] = 0,
290 },
291 },
292 [ C(L1I ) ] = {
293 [ C(OP_READ) ] = {
294 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
295 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
296 },
297 [ C(OP_WRITE) ] = {
298 [ C(RESULT_ACCESS) ] = -1,
299 [ C(RESULT_MISS) ] = -1,
300 },
301 [ C(OP_PREFETCH) ] = {
302 [ C(RESULT_ACCESS) ] = 0,
303 [ C(RESULT_MISS) ] = 0,
304 },
305 },
306 [ C(LL ) ] = {
307 [ C(OP_READ) ] = {
308 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
309 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
310 },
311 [ C(OP_WRITE) ] = {
312 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
313 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
314 },
315 [ C(OP_PREFETCH) ] = {
316 [ C(RESULT_ACCESS) ] = 0,
317 [ C(RESULT_MISS) ] = 0,
318 },
319 },
320 [ C(DTLB) ] = {
321 [ C(OP_READ) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
323 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
324 },
325 [ C(OP_WRITE) ] = {
326 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
327 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
328 },
329 [ C(OP_PREFETCH) ] = {
330 [ C(RESULT_ACCESS) ] = 0,
331 [ C(RESULT_MISS) ] = 0,
332 },
333 },
334 [ C(ITLB) ] = {
335 [ C(OP_READ) ] = {
336 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
337 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
338 },
339 [ C(OP_WRITE) ] = {
340 [ C(RESULT_ACCESS) ] = -1,
341 [ C(RESULT_MISS) ] = -1,
342 },
343 [ C(OP_PREFETCH) ] = {
344 [ C(RESULT_ACCESS) ] = -1,
345 [ C(RESULT_MISS) ] = -1,
346 },
347 },
348 [ C(BPU ) ] = {
349 [ C(OP_READ) ] = {
350 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
351 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
352 },
353 [ C(OP_WRITE) ] = {
354 [ C(RESULT_ACCESS) ] = -1,
355 [ C(RESULT_MISS) ] = -1,
356 },
357 [ C(OP_PREFETCH) ] = {
358 [ C(RESULT_ACCESS) ] = -1,
359 [ C(RESULT_MISS) ] = -1,
360 },
361 },
362};
363
364static __initconst u64 atom_hw_cache_event_ids
365 [PERF_COUNT_HW_CACHE_MAX]
366 [PERF_COUNT_HW_CACHE_OP_MAX]
367 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
368{
369 [ C(L1D) ] = {
370 [ C(OP_READ) ] = {
371 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
372 [ C(RESULT_MISS) ] = 0,
373 },
374 [ C(OP_WRITE) ] = {
375 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
376 [ C(RESULT_MISS) ] = 0,
377 },
378 [ C(OP_PREFETCH) ] = {
379 [ C(RESULT_ACCESS) ] = 0x0,
380 [ C(RESULT_MISS) ] = 0,
381 },
382 },
383 [ C(L1I ) ] = {
384 [ C(OP_READ) ] = {
385 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
386 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
387 },
388 [ C(OP_WRITE) ] = {
389 [ C(RESULT_ACCESS) ] = -1,
390 [ C(RESULT_MISS) ] = -1,
391 },
392 [ C(OP_PREFETCH) ] = {
393 [ C(RESULT_ACCESS) ] = 0,
394 [ C(RESULT_MISS) ] = 0,
395 },
396 },
397 [ C(LL ) ] = {
398 [ C(OP_READ) ] = {
399 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
400 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
401 },
402 [ C(OP_WRITE) ] = {
403 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
404 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
405 },
406 [ C(OP_PREFETCH) ] = {
407 [ C(RESULT_ACCESS) ] = 0,
408 [ C(RESULT_MISS) ] = 0,
409 },
410 },
411 [ C(DTLB) ] = {
412 [ C(OP_READ) ] = {
413 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
414 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
415 },
416 [ C(OP_WRITE) ] = {
417 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
418 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
419 },
420 [ C(OP_PREFETCH) ] = {
421 [ C(RESULT_ACCESS) ] = 0,
422 [ C(RESULT_MISS) ] = 0,
423 },
424 },
425 [ C(ITLB) ] = {
426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
428 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
429 },
430 [ C(OP_WRITE) ] = {
431 [ C(RESULT_ACCESS) ] = -1,
432 [ C(RESULT_MISS) ] = -1,
433 },
434 [ C(OP_PREFETCH) ] = {
435 [ C(RESULT_ACCESS) ] = -1,
436 [ C(RESULT_MISS) ] = -1,
437 },
438 },
439 [ C(BPU ) ] = {
440 [ C(OP_READ) ] = {
441 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
442 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
443 },
444 [ C(OP_WRITE) ] = {
445 [ C(RESULT_ACCESS) ] = -1,
446 [ C(RESULT_MISS) ] = -1,
447 },
448 [ C(OP_PREFETCH) ] = {
449 [ C(RESULT_ACCESS) ] = -1,
450 [ C(RESULT_MISS) ] = -1,
451 },
452 },
453};
454
455static u64 intel_pmu_raw_event(u64 hw_event)
456{
457#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
458#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
459#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
460#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
461#define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
462
463#define CORE_EVNTSEL_MASK \
464 (INTEL_ARCH_EVTSEL_MASK | \
465 INTEL_ARCH_UNIT_MASK | \
466 INTEL_ARCH_EDGE_MASK | \
467 INTEL_ARCH_INV_MASK | \
468 INTEL_ARCH_CNT_MASK)
469
470 return hw_event & CORE_EVNTSEL_MASK;
471}
472
473static void intel_pmu_enable_bts(u64 config)
474{
475 unsigned long debugctlmsr;
476
477 debugctlmsr = get_debugctlmsr();
478
479 debugctlmsr |= X86_DEBUGCTL_TR;
480 debugctlmsr |= X86_DEBUGCTL_BTS;
481 debugctlmsr |= X86_DEBUGCTL_BTINT;
482
483 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
484 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
485
486 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
487 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
488
489 update_debugctlmsr(debugctlmsr);
490}
491
492static void intel_pmu_disable_bts(void)
493{
494 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
495 unsigned long debugctlmsr;
496
497 if (!cpuc->ds)
498 return;
499
500 debugctlmsr = get_debugctlmsr();
501
502 debugctlmsr &=
503 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
504 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
505
506 update_debugctlmsr(debugctlmsr);
507}
508
509static void intel_pmu_disable_all(void)
510{
511 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
512
513 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
514
515 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
516 intel_pmu_disable_bts();
517}
518
519static void intel_pmu_enable_all(void)
520{
521 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
522
523 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
524
525 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
526 struct perf_event *event =
527 cpuc->events[X86_PMC_IDX_FIXED_BTS];
528
529 if (WARN_ON_ONCE(!event))
530 return;
531
532 intel_pmu_enable_bts(event->hw.config);
533 }
534}
535
536static inline u64 intel_pmu_get_status(void)
537{
538 u64 status;
539
540 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
541
542 return status;
543}
544
545static inline void intel_pmu_ack_status(u64 ack)
546{
547 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
548}
549
550static inline void
551intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
552{
553 int idx = __idx - X86_PMC_IDX_FIXED;
554 u64 ctrl_val, mask;
555
556 mask = 0xfULL << (idx * 4);
557
558 rdmsrl(hwc->config_base, ctrl_val);
559 ctrl_val &= ~mask;
560 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
561}
562
563static void intel_pmu_drain_bts_buffer(void)
564{
565 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
566 struct debug_store *ds = cpuc->ds;
567 struct bts_record {
568 u64 from;
569 u64 to;
570 u64 flags;
571 };
572 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
573 struct bts_record *at, *top;
574 struct perf_output_handle handle;
575 struct perf_event_header header;
576 struct perf_sample_data data;
577 struct pt_regs regs;
578
579 if (!event)
580 return;
581
582 if (!ds)
583 return;
584
585 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
586 top = (struct bts_record *)(unsigned long)ds->bts_index;
587
588 if (top <= at)
589 return;
590
591 ds->bts_index = ds->bts_buffer_base;
592
593
594 data.period = event->hw.last_period;
595 data.addr = 0;
596 data.raw = NULL;
597 regs.ip = 0;
598
599 /*
600 * Prepare a generic sample, i.e. fill in the invariant fields.
601 * We will overwrite the from and to address before we output
602 * the sample.
603 */
604 perf_prepare_sample(&header, &data, event, &regs);
605
606 if (perf_output_begin(&handle, event,
607 header.size * (top - at), 1, 1))
608 return;
609
610 for (; at < top; at++) {
611 data.ip = at->from;
612 data.addr = at->to;
613
614 perf_output_sample(&handle, &header, &data, event);
615 }
616
617 perf_output_end(&handle);
618
619 /* There's new data available. */
620 event->hw.interrupts++;
621 event->pending_kill = POLL_IN;
622}
623
624static inline void
625intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
626{
627 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
628 intel_pmu_disable_bts();
629 intel_pmu_drain_bts_buffer();
630 return;
631 }
632
633 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
634 intel_pmu_disable_fixed(hwc, idx);
635 return;
636 }
637
638 x86_pmu_disable_event(hwc, idx);
639}
640
641static inline void
642intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
643{
644 int idx = __idx - X86_PMC_IDX_FIXED;
645 u64 ctrl_val, bits, mask;
646 int err;
647
648 /*
649 * Enable IRQ generation (0x8),
650 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
651 * if requested:
652 */
653 bits = 0x8ULL;
654 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
655 bits |= 0x2;
656 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
657 bits |= 0x1;
658
659 /*
660 * ANY bit is supported in v3 and up
661 */
662 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
663 bits |= 0x4;
664
665 bits <<= (idx * 4);
666 mask = 0xfULL << (idx * 4);
667
668 rdmsrl(hwc->config_base, ctrl_val);
669 ctrl_val &= ~mask;
670 ctrl_val |= bits;
671 err = checking_wrmsrl(hwc->config_base, ctrl_val);
672}
673
674static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
675{
676 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
677 if (!__get_cpu_var(cpu_hw_events).enabled)
678 return;
679
680 intel_pmu_enable_bts(hwc->config);
681 return;
682 }
683
684 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
685 intel_pmu_enable_fixed(hwc, idx);
686 return;
687 }
688
689 __x86_pmu_enable_event(hwc, idx);
690}
691
692/*
693 * Save and restart an expired event. Called by NMI contexts,
694 * so it has to be careful about preempting normal event ops:
695 */
696static int intel_pmu_save_and_restart(struct perf_event *event)
697{
698 struct hw_perf_event *hwc = &event->hw;
699 int idx = hwc->idx;
700 int ret;
701
702 x86_perf_event_update(event, hwc, idx);
703 ret = x86_perf_event_set_period(event, hwc, idx);
704
705 return ret;
706}
707
708static void intel_pmu_reset(void)
709{
710 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
711 unsigned long flags;
712 int idx;
713
714 if (!x86_pmu.num_events)
715 return;
716
717 local_irq_save(flags);
718
719 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
720
721 for (idx = 0; idx < x86_pmu.num_events; idx++) {
722 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
723 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
724 }
725 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
726 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
727 }
728 if (ds)
729 ds->bts_index = ds->bts_buffer_base;
730
731 local_irq_restore(flags);
732}
733
734/*
735 * This handler is triggered by the local APIC, so the APIC IRQ handling
736 * rules apply:
737 */
738static int intel_pmu_handle_irq(struct pt_regs *regs)
739{
740 struct perf_sample_data data;
741 struct cpu_hw_events *cpuc;
742 int bit, loops;
743 u64 ack, status;
744
745 data.addr = 0;
746 data.raw = NULL;
747
748 cpuc = &__get_cpu_var(cpu_hw_events);
749
750 perf_disable();
751 intel_pmu_drain_bts_buffer();
752 status = intel_pmu_get_status();
753 if (!status) {
754 perf_enable();
755 return 0;
756 }
757
758 loops = 0;
759again:
760 if (++loops > 100) {
761 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
762 perf_event_print_debug();
763 intel_pmu_reset();
764 perf_enable();
765 return 1;
766 }
767
768 inc_irq_stat(apic_perf_irqs);
769 ack = status;
770 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
771 struct perf_event *event = cpuc->events[bit];
772
773 clear_bit(bit, (unsigned long *) &status);
774 if (!test_bit(bit, cpuc->active_mask))
775 continue;
776
777 if (!intel_pmu_save_and_restart(event))
778 continue;
779
780 data.period = event->hw.last_period;
781
782 if (perf_event_overflow(event, 1, &data, regs))
783 intel_pmu_disable_event(&event->hw, bit);
784 }
785
786 intel_pmu_ack_status(ack);
787
788 /*
789 * Repeat if there is more work to be done:
790 */
791 status = intel_pmu_get_status();
792 if (status)
793 goto again;
794
795 perf_enable();
796
797 return 1;
798}
799
800static struct event_constraint bts_constraint =
801 EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
802
803static struct event_constraint *
804intel_special_constraints(struct perf_event *event)
805{
806 unsigned int hw_event;
807
808 hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK;
809
810 if (unlikely((hw_event ==
811 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
812 (event->hw.sample_period == 1))) {
813
814 return &bts_constraint;
815 }
816 return NULL;
817}
818
819static struct event_constraint *
820intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
821{
822 struct event_constraint *c;
823
824 c = intel_special_constraints(event);
825 if (c)
826 return c;
827
828 return x86_get_event_constraints(cpuc, event);
829}
830
831static __initconst struct x86_pmu core_pmu = {
832 .name = "core",
833 .handle_irq = x86_pmu_handle_irq,
834 .disable_all = x86_pmu_disable_all,
835 .enable_all = x86_pmu_enable_all,
836 .enable = x86_pmu_enable_event,
837 .disable = x86_pmu_disable_event,
838 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
839 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
840 .event_map = intel_pmu_event_map,
841 .raw_event = intel_pmu_raw_event,
842 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
843 .apic = 1,
844 /*
845 * Intel PMCs cannot be accessed sanely above 32 bit width,
846 * so we install an artificial 1<<31 period regardless of
847 * the generic event period:
848 */
849 .max_period = (1ULL << 31) - 1,
850 .get_event_constraints = intel_get_event_constraints,
851 .event_constraints = intel_core_event_constraints,
852};
853
854static __initconst struct x86_pmu intel_pmu = {
855 .name = "Intel",
856 .handle_irq = intel_pmu_handle_irq,
857 .disable_all = intel_pmu_disable_all,
858 .enable_all = intel_pmu_enable_all,
859 .enable = intel_pmu_enable_event,
860 .disable = intel_pmu_disable_event,
861 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
862 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
863 .event_map = intel_pmu_event_map,
864 .raw_event = intel_pmu_raw_event,
865 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
866 .apic = 1,
867 /*
868 * Intel PMCs cannot be accessed sanely above 32 bit width,
869 * so we install an artificial 1<<31 period regardless of
870 * the generic event period:
871 */
872 .max_period = (1ULL << 31) - 1,
873 .enable_bts = intel_pmu_enable_bts,
874 .disable_bts = intel_pmu_disable_bts,
875 .get_event_constraints = intel_get_event_constraints
876};
877
878static __init int intel_pmu_init(void)
879{
880 union cpuid10_edx edx;
881 union cpuid10_eax eax;
882 unsigned int unused;
883 unsigned int ebx;
884 int version;
885
886 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
887 /* check for P6 processor family */
888 if (boot_cpu_data.x86 == 6) {
889 return p6_pmu_init();
890 } else {
891 return -ENODEV;
892 }
893 }
894
895 /*
896 * Check whether the Architectural PerfMon supports
897 * Branch Misses Retired hw_event or not.
898 */
899 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
900 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
901 return -ENODEV;
902
903 version = eax.split.version_id;
904 if (version < 2)
905 x86_pmu = core_pmu;
906 else
907 x86_pmu = intel_pmu;
908
909 x86_pmu.version = version;
910 x86_pmu.num_events = eax.split.num_events;
911 x86_pmu.event_bits = eax.split.bit_width;
912 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
913
914 /*
915 * Quirk: v2 perfmon does not report fixed-purpose events, so
916 * assume at least 3 events:
917 */
918 if (version > 1)
919 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
920
921 /*
922 * Install the hw-cache-events table:
923 */
924 switch (boot_cpu_data.x86_model) {
925 case 14: /* 65 nm core solo/duo, "Yonah" */
926 pr_cont("Core events, ");
927 break;
928
929 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
930 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
931 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
932 case 29: /* six-core 45 nm xeon "Dunnington" */
933 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
934 sizeof(hw_cache_event_ids));
935
936 x86_pmu.event_constraints = intel_core2_event_constraints;
937 pr_cont("Core2 events, ");
938 break;
939
940 case 26: /* 45 nm nehalem, "Bloomfield" */
941 case 30: /* 45 nm nehalem, "Lynnfield" */
942 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
943 sizeof(hw_cache_event_ids));
944
945 x86_pmu.event_constraints = intel_nehalem_event_constraints;
946 pr_cont("Nehalem/Corei7 events, ");
947 break;
948 case 28: /* Atom */
949 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
950 sizeof(hw_cache_event_ids));
951
952 x86_pmu.event_constraints = intel_gen_event_constraints;
953 pr_cont("Atom events, ");
954 break;
955
956 case 37: /* 32 nm nehalem, "Clarkdale" */
957 case 44: /* 32 nm nehalem, "Gulftown" */
958 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
959 sizeof(hw_cache_event_ids));
960
961 x86_pmu.event_constraints = intel_westmere_event_constraints;
962 pr_cont("Westmere events, ");
963 break;
964
965 default:
966 /*
967 * default constraints for v2 and up
968 */
969 x86_pmu.event_constraints = intel_gen_event_constraints;
970 pr_cont("generic architected perfmon, ");
971 }
972 return 0;
973}
974
975#else /* CONFIG_CPU_SUP_INTEL */
976
977static int intel_pmu_init(void)
978{
979 return 0;
980}
981
982#endif /* CONFIG_CPU_SUP_INTEL */
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
new file mode 100644
index 000000000000..a4e67b99d91c
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -0,0 +1,157 @@
1#ifdef CONFIG_CPU_SUP_INTEL
2
3/*
4 * Not sure about some of these
5 */
6static const u64 p6_perfmon_event_map[] =
7{
8 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
9 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
10 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
11 [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
12 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
13 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
14 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
15};
16
17static u64 p6_pmu_event_map(int hw_event)
18{
19 return p6_perfmon_event_map[hw_event];
20}
21
22/*
23 * Event setting that is specified not to count anything.
24 * We use this to effectively disable a counter.
25 *
26 * L2_RQSTS with 0 MESI unit mask.
27 */
28#define P6_NOP_EVENT 0x0000002EULL
29
30static u64 p6_pmu_raw_event(u64 hw_event)
31{
32#define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
33#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
34#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
35#define P6_EVNTSEL_INV_MASK 0x00800000ULL
36#define P6_EVNTSEL_REG_MASK 0xFF000000ULL
37
38#define P6_EVNTSEL_MASK \
39 (P6_EVNTSEL_EVENT_MASK | \
40 P6_EVNTSEL_UNIT_MASK | \
41 P6_EVNTSEL_EDGE_MASK | \
42 P6_EVNTSEL_INV_MASK | \
43 P6_EVNTSEL_REG_MASK)
44
45 return hw_event & P6_EVNTSEL_MASK;
46}
47
48static struct event_constraint p6_event_constraints[] =
49{
50 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
51 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
52 INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
53 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
54 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
55 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
56 EVENT_CONSTRAINT_END
57};
58
59static void p6_pmu_disable_all(void)
60{
61 u64 val;
62
63 /* p6 only has one enable register */
64 rdmsrl(MSR_P6_EVNTSEL0, val);
65 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
66 wrmsrl(MSR_P6_EVNTSEL0, val);
67}
68
69static void p6_pmu_enable_all(void)
70{
71 unsigned long val;
72
73 /* p6 only has one enable register */
74 rdmsrl(MSR_P6_EVNTSEL0, val);
75 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
76 wrmsrl(MSR_P6_EVNTSEL0, val);
77}
78
79static inline void
80p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
81{
82 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
83 u64 val = P6_NOP_EVENT;
84
85 if (cpuc->enabled)
86 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
87
88 (void)checking_wrmsrl(hwc->config_base + idx, val);
89}
90
91static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
92{
93 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
94 u64 val;
95
96 val = hwc->config;
97 if (cpuc->enabled)
98 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
99
100 (void)checking_wrmsrl(hwc->config_base + idx, val);
101}
102
103static __initconst struct x86_pmu p6_pmu = {
104 .name = "p6",
105 .handle_irq = x86_pmu_handle_irq,
106 .disable_all = p6_pmu_disable_all,
107 .enable_all = p6_pmu_enable_all,
108 .enable = p6_pmu_enable_event,
109 .disable = p6_pmu_disable_event,
110 .eventsel = MSR_P6_EVNTSEL0,
111 .perfctr = MSR_P6_PERFCTR0,
112 .event_map = p6_pmu_event_map,
113 .raw_event = p6_pmu_raw_event,
114 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
115 .apic = 1,
116 .max_period = (1ULL << 31) - 1,
117 .version = 0,
118 .num_events = 2,
119 /*
120 * Events have 40 bits implemented. However they are designed such
121 * that bits [32-39] are sign extensions of bit 31. As such the
122 * effective width of a event for P6-like PMU is 32 bits only.
123 *
124 * See IA-32 Intel Architecture Software developer manual Vol 3B
125 */
126 .event_bits = 32,
127 .event_mask = (1ULL << 32) - 1,
128 .get_event_constraints = x86_get_event_constraints,
129 .event_constraints = p6_event_constraints,
130};
131
132static __init int p6_pmu_init(void)
133{
134 switch (boot_cpu_data.x86_model) {
135 case 1:
136 case 3: /* Pentium Pro */
137 case 5:
138 case 6: /* Pentium II */
139 case 7:
140 case 8:
141 case 11: /* Pentium III */
142 case 9:
143 case 13:
144 /* Pentium M */
145 break;
146 default:
147 pr_cont("unsupported p6 CPU model %d ",
148 boot_cpu_data.x86_model);
149 return -ENODEV;
150 }
151
152 x86_pmu = p6_pmu;
153
154 return 0;
155}
156
157#endif /* CONFIG_CPU_SUP_INTEL */
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 898df9719afb..fb329e9f8494 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -115,17 +115,6 @@ int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
115 115
116 return !test_bit(counter, perfctr_nmi_owner); 116 return !test_bit(counter, perfctr_nmi_owner);
117} 117}
118
119/* checks the an msr for availability */
120int avail_to_resrv_perfctr_nmi(unsigned int msr)
121{
122 unsigned int counter;
123
124 counter = nmi_perfctr_msr_to_bit(msr);
125 BUG_ON(counter > NMI_MAX_COUNTER_BITS);
126
127 return !test_bit(counter, perfctr_nmi_owner);
128}
129EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit); 118EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
130 119
131int reserve_perfctr_nmi(unsigned int msr) 120int reserve_perfctr_nmi(unsigned int msr)
@@ -691,7 +680,7 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
691 cpu_nmi_set_wd_enabled(); 680 cpu_nmi_set_wd_enabled();
692 681
693 apic_write(APIC_LVTPC, APIC_DM_NMI); 682 apic_write(APIC_LVTPC, APIC_DM_NMI);
694 evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE; 683 evntsel |= ARCH_PERFMON_EVENTSEL_ENABLE;
695 wrmsr(evntsel_msr, evntsel, 0); 684 wrmsr(evntsel_msr, evntsel, 0);
696 intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1); 685 intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
697 return 1; 686 return 1;
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index ae775ca47b25..11540a189d93 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -18,11 +18,6 @@
18 18
19#include "dumpstack.h" 19#include "dumpstack.h"
20 20
21/* Just a stub for now */
22int x86_is_stack_id(int id, char *name)
23{
24 return 0;
25}
26 21
27void dump_trace(struct task_struct *task, struct pt_regs *regs, 22void dump_trace(struct task_struct *task, struct pt_regs *regs,
28 unsigned long *stack, unsigned long bp, 23 unsigned long *stack, unsigned long bp,
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 0ad9597073f5..676bc051252e 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -33,11 +33,6 @@ static char x86_stack_ids[][8] = {
33#endif 33#endif
34}; 34};
35 35
36int x86_is_stack_id(int id, char *name)
37{
38 return x86_stack_ids[id - 1] == name;
39}
40
41static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack, 36static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
42 unsigned *usedp, char **idp) 37 unsigned *usedp, char **idp)
43{ 38{
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 1e8ceadc0d6a..d6cc065f519f 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -344,13 +344,6 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp,
344 } 344 }
345 345
346 /* 346 /*
347 * For kernel-addresses, either the address or symbol name can be
348 * specified.
349 */
350 if (info->name)
351 info->address = (unsigned long)
352 kallsyms_lookup_name(info->name);
353 /*
354 * Check that the low-order bits of the address are appropriate 347 * Check that the low-order bits of the address are appropriate
355 * for the alignment implied by len. 348 * for the alignment implied by len.
356 */ 349 */
@@ -486,8 +479,6 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
486 rcu_read_lock(); 479 rcu_read_lock();
487 480
488 bp = per_cpu(bp_per_reg[i], cpu); 481 bp = per_cpu(bp_per_reg[i], cpu);
489 if (bp)
490 rc = NOTIFY_DONE;
491 /* 482 /*
492 * Reset the 'i'th TRAP bit in dr6 to denote completion of 483 * Reset the 'i'th TRAP bit in dr6 to denote completion of
493 * exception handling 484 * exception handling
@@ -506,7 +497,13 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
506 497
507 rcu_read_unlock(); 498 rcu_read_unlock();
508 } 499 }
509 if (dr6 & (~DR_TRAP_BITS)) 500 /*
501 * Further processing in do_debug() is needed for a) user-space
502 * breakpoints (to generate signals) and b) when the system has
503 * taken exception due to multiple causes
504 */
505 if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
506 (dr6 & (~DR_TRAP_BITS)))
510 rc = NOTIFY_DONE; 507 rc = NOTIFY_DONE;
511 508
512 set_debugreg(dr7, 7); 509 set_debugreg(dr7, 7);
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index 5b8c7505b3bc..5de9f4a9c3fd 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -337,6 +337,9 @@ static void __kprobes arch_copy_kprobe(struct kprobe *p)
337 337
338int __kprobes arch_prepare_kprobe(struct kprobe *p) 338int __kprobes arch_prepare_kprobe(struct kprobe *p)
339{ 339{
340 if (alternatives_text_reserved(p->addr, p->addr))
341 return -EINVAL;
342
340 if (!can_probe((unsigned long)p->addr)) 343 if (!can_probe((unsigned long)p->addr))
341 return -EILSEQ; 344 return -EILSEQ;
342 /* insn: must be on special executable page on x86. */ 345 /* insn: must be on special executable page on x86. */
@@ -429,7 +432,7 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
429static void __kprobes setup_singlestep(struct kprobe *p, struct pt_regs *regs, 432static void __kprobes setup_singlestep(struct kprobe *p, struct pt_regs *regs,
430 struct kprobe_ctlblk *kcb) 433 struct kprobe_ctlblk *kcb)
431{ 434{
432#if !defined(CONFIG_PREEMPT) || defined(CONFIG_FREEZER) 435#if !defined(CONFIG_PREEMPT)
433 if (p->ainsn.boostable == 1 && !p->post_handler) { 436 if (p->ainsn.boostable == 1 && !p->post_handler) {
434 /* Boost up -- we can execute copied instructions directly */ 437 /* Boost up -- we can execute copied instructions directly */
435 reset_current_kprobe(); 438 reset_current_kprobe();
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 40b54ceb68b5..a2c1edd2d3ac 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -359,13 +359,6 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
359 x86_init.mpparse.mpc_record(1); 359 x86_init.mpparse.mpc_record(1);
360 } 360 }
361 361
362#ifdef CONFIG_X86_BIGSMP
363 generic_bigsmp_probe();
364#endif
365
366 if (apic->setup_apic_routing)
367 apic->setup_apic_routing();
368
369 if (!num_processors) 362 if (!num_processors)
370 printk(KERN_ERR "MPTABLE: no processors registered!\n"); 363 printk(KERN_ERR "MPTABLE: no processors registered!\n");
371 return num_processors; 364 return num_processors;
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 41a26a82470a..126f0b493d04 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -527,6 +527,7 @@ void set_personality_ia32(void)
527 527
528 /* Make sure to be in 32bit mode */ 528 /* Make sure to be in 32bit mode */
529 set_thread_flag(TIF_IA32); 529 set_thread_flag(TIF_IA32);
530 current->personality |= force_personality32;
530 531
531 /* Prepare the first "return" to user space */ 532 /* Prepare the first "return" to user space */
532 current_thread_info()->status |= TS_COMPAT; 533 current_thread_info()->status |= TS_COMPAT;
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 0c1033d61e59..d03146f71b2f 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -140,30 +140,6 @@ static const int arg_offs_table[] = {
140#endif 140#endif
141}; 141};
142 142
143/**
144 * regs_get_argument_nth() - get Nth argument at function call
145 * @regs: pt_regs which contains registers at function entry.
146 * @n: argument number.
147 *
148 * regs_get_argument_nth() returns @n th argument of a function call.
149 * Since usually the kernel stack will be changed right after function entry,
150 * you must use this at function entry. If the @n th entry is NOT in the
151 * kernel stack or pt_regs, this returns 0.
152 */
153unsigned long regs_get_argument_nth(struct pt_regs *regs, unsigned int n)
154{
155 if (n < ARRAY_SIZE(arg_offs_table))
156 return *(unsigned long *)((char *)regs + arg_offs_table[n]);
157 else {
158 /*
159 * The typical case: arg n is on the stack.
160 * (Note: stack[0] = return address, so skip it)
161 */
162 n -= ARRAY_SIZE(arg_offs_table);
163 return regs_get_kernel_stack_nth(regs, 1 + n);
164 }
165}
166
167/* 143/*
168 * does not yet catch signals sent when the child dies. 144 * does not yet catch signals sent when the child dies.
169 * in exit.c or in signal.c. 145 * in exit.c or in signal.c.
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 678d0b8c26f3..b4e870cbdc60 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1083,9 +1083,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
1083 set_cpu_sibling_map(0); 1083 set_cpu_sibling_map(0);
1084 1084
1085 enable_IR_x2apic(); 1085 enable_IR_x2apic();
1086#ifdef CONFIG_X86_64
1087 default_setup_apic_routing(); 1086 default_setup_apic_routing();
1088#endif
1089 1087
1090 if (smp_sanity_check(max_cpus) < 0) { 1088 if (smp_sanity_check(max_cpus) < 0) {
1091 printk(KERN_INFO "SMP disabled\n"); 1089 printk(KERN_INFO "SMP disabled\n");
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 33399176512a..1168e4454188 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -534,6 +534,9 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
534 534
535 get_debugreg(dr6, 6); 535 get_debugreg(dr6, 6);
536 536
537 /* Filter out all the reserved bits which are preset to 1 */
538 dr6 &= ~DR6_RESERVED;
539
537 /* Catch kmemcheck conditions first of all! */ 540 /* Catch kmemcheck conditions first of all! */
538 if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) 541 if ((dr6 & DR_STEP) && kmemcheck_trap(regs))
539 return; 542 return;
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 296aba49472a..15578f180e59 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -467,6 +467,9 @@ static int pit_ioport_read(struct kvm_io_device *this,
467 return -EOPNOTSUPP; 467 return -EOPNOTSUPP;
468 468
469 addr &= KVM_PIT_CHANNEL_MASK; 469 addr &= KVM_PIT_CHANNEL_MASK;
470 if (addr == 3)
471 return 0;
472
470 s = &pit_state->channels[addr]; 473 s = &pit_state->channels[addr];
471 474
472 mutex_lock(&pit_state->lock); 475 mutex_lock(&pit_state->lock);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 1ddcad452add..a1e1bc9d412d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -670,7 +670,7 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
670{ 670{
671 static int version; 671 static int version;
672 struct pvclock_wall_clock wc; 672 struct pvclock_wall_clock wc;
673 struct timespec now, sys, boot; 673 struct timespec boot;
674 674
675 if (!wall_clock) 675 if (!wall_clock)
676 return; 676 return;
@@ -685,9 +685,7 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
685 * wall clock specified here. guest system time equals host 685 * wall clock specified here. guest system time equals host
686 * system time for us, thus we must fill in host boot time here. 686 * system time for us, thus we must fill in host boot time here.
687 */ 687 */
688 now = current_kernel_time(); 688 getboottime(&boot);
689 ktime_get_ts(&sys);
690 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
691 689
692 wc.sec = boot.tv_sec; 690 wc.sec = boot.tv_sec;
693 wc.nsec = boot.tv_nsec; 691 wc.nsec = boot.tv_nsec;
@@ -762,6 +760,7 @@ static void kvm_write_guest_time(struct kvm_vcpu *v)
762 local_irq_save(flags); 760 local_irq_save(flags);
763 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); 761 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
764 ktime_get_ts(&ts); 762 ktime_get_ts(&ts);
763 monotonic_to_bootbased(&ts);
765 local_irq_restore(flags); 764 local_irq_restore(flags);
766 765
767 /* With all the info we got, fill in the values */ 766 /* With all the info we got, fill in the values */
diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c
index 71da1bca13cb..738e6593799d 100644
--- a/arch/x86/mm/gup.c
+++ b/arch/x86/mm/gup.c
@@ -18,7 +18,7 @@ static inline pte_t gup_get_pte(pte_t *ptep)
18#else 18#else
19 /* 19 /*
20 * With get_user_pages_fast, we walk down the pagetables without taking 20 * With get_user_pages_fast, we walk down the pagetables without taking
21 * any locks. For this we would like to load the pointers atoimcally, 21 * any locks. For this we would like to load the pointers atomically,
22 * but that is not possible (without expensive cmpxchg8b) on PAE. What 22 * but that is not possible (without expensive cmpxchg8b) on PAE. What
23 * we do have is the guarantee that a pte will only either go from not 23 * we do have is the guarantee that a pte will only either go from not
24 * present to present, or present to not present or both -- it will not 24 * present to present, or present to not present or both -- it will not
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 3347f696edc7..2c505ee71014 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -159,7 +159,7 @@ static int nmi_setup_mux(void)
159 159
160 for_each_possible_cpu(i) { 160 for_each_possible_cpu(i) {
161 per_cpu(cpu_msrs, i).multiplex = 161 per_cpu(cpu_msrs, i).multiplex =
162 kmalloc(multiplex_size, GFP_KERNEL); 162 kzalloc(multiplex_size, GFP_KERNEL);
163 if (!per_cpu(cpu_msrs, i).multiplex) 163 if (!per_cpu(cpu_msrs, i).multiplex)
164 return 0; 164 return 0;
165 } 165 }
@@ -179,7 +179,6 @@ static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
179 if (counter_config[i].enabled) { 179 if (counter_config[i].enabled) {
180 multiplex[i].saved = -(u64)counter_config[i].count; 180 multiplex[i].saved = -(u64)counter_config[i].count;
181 } else { 181 } else {
182 multiplex[i].addr = 0;
183 multiplex[i].saved = 0; 182 multiplex[i].saved = 0;
184 } 183 }
185 } 184 }
@@ -189,25 +188,27 @@ static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
189 188
190static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) 189static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
191{ 190{
191 struct op_msr *counters = msrs->counters;
192 struct op_msr *multiplex = msrs->multiplex; 192 struct op_msr *multiplex = msrs->multiplex;
193 int i; 193 int i;
194 194
195 for (i = 0; i < model->num_counters; ++i) { 195 for (i = 0; i < model->num_counters; ++i) {
196 int virt = op_x86_phys_to_virt(i); 196 int virt = op_x86_phys_to_virt(i);
197 if (multiplex[virt].addr) 197 if (counters[i].addr)
198 rdmsrl(multiplex[virt].addr, multiplex[virt].saved); 198 rdmsrl(counters[i].addr, multiplex[virt].saved);
199 } 199 }
200} 200}
201 201
202static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) 202static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
203{ 203{
204 struct op_msr *counters = msrs->counters;
204 struct op_msr *multiplex = msrs->multiplex; 205 struct op_msr *multiplex = msrs->multiplex;
205 int i; 206 int i;
206 207
207 for (i = 0; i < model->num_counters; ++i) { 208 for (i = 0; i < model->num_counters; ++i) {
208 int virt = op_x86_phys_to_virt(i); 209 int virt = op_x86_phys_to_virt(i);
209 if (multiplex[virt].addr) 210 if (counters[i].addr)
210 wrmsrl(multiplex[virt].addr, multiplex[virt].saved); 211 wrmsrl(counters[i].addr, multiplex[virt].saved);
211 } 212 }
212} 213}
213 214
@@ -303,11 +304,11 @@ static int allocate_msrs(void)
303 304
304 int i; 305 int i;
305 for_each_possible_cpu(i) { 306 for_each_possible_cpu(i) {
306 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, 307 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
307 GFP_KERNEL); 308 GFP_KERNEL);
308 if (!per_cpu(cpu_msrs, i).counters) 309 if (!per_cpu(cpu_msrs, i).counters)
309 return 0; 310 return 0;
310 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size, 311 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
311 GFP_KERNEL); 312 GFP_KERNEL);
312 if (!per_cpu(cpu_msrs, i).controls) 313 if (!per_cpu(cpu_msrs, i).controls)
313 return 0; 314 return 0;
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 39686c29f03a..090cbbec7dbd 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -22,6 +22,9 @@
22#include <asm/ptrace.h> 22#include <asm/ptrace.h>
23#include <asm/msr.h> 23#include <asm/msr.h>
24#include <asm/nmi.h> 24#include <asm/nmi.h>
25#include <asm/apic.h>
26#include <asm/processor.h>
27#include <asm/cpufeature.h>
25 28
26#include "op_x86_model.h" 29#include "op_x86_model.h"
27#include "op_counter.h" 30#include "op_counter.h"
@@ -43,23 +46,10 @@
43 46
44static unsigned long reset_value[NUM_VIRT_COUNTERS]; 47static unsigned long reset_value[NUM_VIRT_COUNTERS];
45 48
46#ifdef CONFIG_OPROFILE_IBS
47
48/* IbsFetchCtl bits/masks */
49#define IBS_FETCH_RAND_EN (1ULL<<57)
50#define IBS_FETCH_VAL (1ULL<<49)
51#define IBS_FETCH_ENABLE (1ULL<<48)
52#define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
53
54/*IbsOpCtl bits */
55#define IBS_OP_CNT_CTL (1ULL<<19)
56#define IBS_OP_VAL (1ULL<<18)
57#define IBS_OP_ENABLE (1ULL<<17)
58
59#define IBS_FETCH_SIZE 6 49#define IBS_FETCH_SIZE 6
60#define IBS_OP_SIZE 12 50#define IBS_OP_SIZE 12
61 51
62static int has_ibs; /* AMD Family10h and later */ 52static u32 ibs_caps;
63 53
64struct op_ibs_config { 54struct op_ibs_config {
65 unsigned long op_enabled; 55 unsigned long op_enabled;
@@ -71,24 +61,52 @@ struct op_ibs_config {
71}; 61};
72 62
73static struct op_ibs_config ibs_config; 63static struct op_ibs_config ibs_config;
64static u64 ibs_op_ctl;
74 65
75#endif 66/*
67 * IBS cpuid feature detection
68 */
76 69
77#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX 70#define IBS_CPUID_FEATURES 0x8000001b
71
72/*
73 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
74 * bit 0 is used to indicate the existence of IBS.
75 */
76#define IBS_CAPS_AVAIL (1LL<<0)
77#define IBS_CAPS_RDWROPCNT (1LL<<3)
78#define IBS_CAPS_OPCNT (1LL<<4)
78 79
79static void op_mux_fill_in_addresses(struct op_msrs * const msrs) 80/*
81 * IBS randomization macros
82 */
83#define IBS_RANDOM_BITS 12
84#define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
85#define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
86
87static u32 get_ibs_caps(void)
80{ 88{
81 int i; 89 u32 ibs_caps;
90 unsigned int max_level;
82 91
83 for (i = 0; i < NUM_VIRT_COUNTERS; i++) { 92 if (!boot_cpu_has(X86_FEATURE_IBS))
84 int hw_counter = op_x86_virt_to_phys(i); 93 return 0;
85 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) 94
86 msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter; 95 /* check IBS cpuid feature flags */
87 else 96 max_level = cpuid_eax(0x80000000);
88 msrs->multiplex[i].addr = 0; 97 if (max_level < IBS_CPUID_FEATURES)
89 } 98 return IBS_CAPS_AVAIL;
99
100 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
101 if (!(ibs_caps & IBS_CAPS_AVAIL))
102 /* cpuid flags not valid */
103 return IBS_CAPS_AVAIL;
104
105 return ibs_caps;
90} 106}
91 107
108#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
109
92static void op_mux_switch_ctrl(struct op_x86_model_spec const *model, 110static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
93 struct op_msrs const * const msrs) 111 struct op_msrs const * const msrs)
94{ 112{
@@ -98,7 +116,7 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
98 /* enable active counters */ 116 /* enable active counters */
99 for (i = 0; i < NUM_COUNTERS; ++i) { 117 for (i = 0; i < NUM_COUNTERS; ++i) {
100 int virt = op_x86_phys_to_virt(i); 118 int virt = op_x86_phys_to_virt(i);
101 if (!counter_config[virt].enabled) 119 if (!reset_value[virt])
102 continue; 120 continue;
103 rdmsrl(msrs->controls[i].addr, val); 121 rdmsrl(msrs->controls[i].addr, val);
104 val &= model->reserved; 122 val &= model->reserved;
@@ -107,10 +125,6 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
107 } 125 }
108} 126}
109 127
110#else
111
112static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
113
114#endif 128#endif
115 129
116/* functions for op_amd_spec */ 130/* functions for op_amd_spec */
@@ -122,18 +136,12 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
122 for (i = 0; i < NUM_COUNTERS; i++) { 136 for (i = 0; i < NUM_COUNTERS; i++) {
123 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) 137 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
124 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; 138 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
125 else
126 msrs->counters[i].addr = 0;
127 } 139 }
128 140
129 for (i = 0; i < NUM_CONTROLS; i++) { 141 for (i = 0; i < NUM_CONTROLS; i++) {
130 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) 142 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
131 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; 143 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
132 else
133 msrs->controls[i].addr = 0;
134 } 144 }
135
136 op_mux_fill_in_addresses(msrs);
137} 145}
138 146
139static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, 147static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
@@ -144,7 +152,8 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
144 152
145 /* setup reset_value */ 153 /* setup reset_value */
146 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) { 154 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
147 if (counter_config[i].enabled) 155 if (counter_config[i].enabled
156 && msrs->counters[op_x86_virt_to_phys(i)].addr)
148 reset_value[i] = counter_config[i].count; 157 reset_value[i] = counter_config[i].count;
149 else 158 else
150 reset_value[i] = 0; 159 reset_value[i] = 0;
@@ -152,9 +161,18 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
152 161
153 /* clear all counters */ 162 /* clear all counters */
154 for (i = 0; i < NUM_CONTROLS; ++i) { 163 for (i = 0; i < NUM_CONTROLS; ++i) {
155 if (unlikely(!msrs->controls[i].addr)) 164 if (unlikely(!msrs->controls[i].addr)) {
165 if (counter_config[i].enabled && !smp_processor_id())
166 /*
167 * counter is reserved, this is on all
168 * cpus, so report only for cpu #0
169 */
170 op_x86_warn_reserved(i);
156 continue; 171 continue;
172 }
157 rdmsrl(msrs->controls[i].addr, val); 173 rdmsrl(msrs->controls[i].addr, val);
174 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
175 op_x86_warn_in_use(i);
158 val &= model->reserved; 176 val &= model->reserved;
159 wrmsrl(msrs->controls[i].addr, val); 177 wrmsrl(msrs->controls[i].addr, val);
160 } 178 }
@@ -169,9 +187,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
169 /* enable active counters */ 187 /* enable active counters */
170 for (i = 0; i < NUM_COUNTERS; ++i) { 188 for (i = 0; i < NUM_COUNTERS; ++i) {
171 int virt = op_x86_phys_to_virt(i); 189 int virt = op_x86_phys_to_virt(i);
172 if (!counter_config[virt].enabled) 190 if (!reset_value[virt])
173 continue;
174 if (!msrs->counters[i].addr)
175 continue; 191 continue;
176 192
177 /* setup counter registers */ 193 /* setup counter registers */
@@ -185,7 +201,60 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
185 } 201 }
186} 202}
187 203
188#ifdef CONFIG_OPROFILE_IBS 204/*
205 * 16-bit Linear Feedback Shift Register (LFSR)
206 *
207 * 16 14 13 11
208 * Feedback polynomial = X + X + X + X + 1
209 */
210static unsigned int lfsr_random(void)
211{
212 static unsigned int lfsr_value = 0xF00D;
213 unsigned int bit;
214
215 /* Compute next bit to shift in */
216 bit = ((lfsr_value >> 0) ^
217 (lfsr_value >> 2) ^
218 (lfsr_value >> 3) ^
219 (lfsr_value >> 5)) & 0x0001;
220
221 /* Advance to next register value */
222 lfsr_value = (lfsr_value >> 1) | (bit << 15);
223
224 return lfsr_value;
225}
226
227/*
228 * IBS software randomization
229 *
230 * The IBS periodic op counter is randomized in software. The lower 12
231 * bits of the 20 bit counter are randomized. IbsOpCurCnt is
232 * initialized with a 12 bit random value.
233 */
234static inline u64 op_amd_randomize_ibs_op(u64 val)
235{
236 unsigned int random = lfsr_random();
237
238 if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
239 /*
240 * Work around if the hw can not write to IbsOpCurCnt
241 *
242 * Randomize the lower 8 bits of the 16 bit
243 * IbsOpMaxCnt [15:0] value in the range of -128 to
244 * +127 by adding/subtracting an offset to the
245 * maximum count (IbsOpMaxCnt).
246 *
247 * To avoid over or underflows and protect upper bits
248 * starting at bit 16, the initial value for
249 * IbsOpMaxCnt must fit in the range from 0x0081 to
250 * 0xff80.
251 */
252 val += (s8)(random >> 4);
253 else
254 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
255
256 return val;
257}
189 258
190static inline void 259static inline void
191op_amd_handle_ibs(struct pt_regs * const regs, 260op_amd_handle_ibs(struct pt_regs * const regs,
@@ -194,7 +263,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
194 u64 val, ctl; 263 u64 val, ctl;
195 struct op_entry entry; 264 struct op_entry entry;
196 265
197 if (!has_ibs) 266 if (!ibs_caps)
198 return; 267 return;
199 268
200 if (ibs_config.fetch_enabled) { 269 if (ibs_config.fetch_enabled) {
@@ -210,7 +279,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
210 oprofile_write_commit(&entry); 279 oprofile_write_commit(&entry);
211 280
212 /* reenable the IRQ */ 281 /* reenable the IRQ */
213 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK); 282 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
214 ctl |= IBS_FETCH_ENABLE; 283 ctl |= IBS_FETCH_ENABLE;
215 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); 284 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
216 } 285 }
@@ -236,8 +305,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
236 oprofile_write_commit(&entry); 305 oprofile_write_commit(&entry);
237 306
238 /* reenable the IRQ */ 307 /* reenable the IRQ */
239 ctl &= ~IBS_OP_VAL & 0xFFFFFFFF; 308 ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
240 ctl |= IBS_OP_ENABLE;
241 wrmsrl(MSR_AMD64_IBSOPCTL, ctl); 309 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
242 } 310 }
243 } 311 }
@@ -246,41 +314,57 @@ op_amd_handle_ibs(struct pt_regs * const regs,
246static inline void op_amd_start_ibs(void) 314static inline void op_amd_start_ibs(void)
247{ 315{
248 u64 val; 316 u64 val;
249 if (has_ibs && ibs_config.fetch_enabled) { 317
250 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; 318 if (!ibs_caps)
319 return;
320
321 if (ibs_config.fetch_enabled) {
322 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
251 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; 323 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
252 val |= IBS_FETCH_ENABLE; 324 val |= IBS_FETCH_ENABLE;
253 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); 325 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
254 } 326 }
255 327
256 if (has_ibs && ibs_config.op_enabled) { 328 if (ibs_config.op_enabled) {
257 val = (ibs_config.max_cnt_op >> 4) & 0xFFFF; 329 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
258 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; 330 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
259 val |= IBS_OP_ENABLE; 331 /*
332 * IbsOpCurCnt not supported. See
333 * op_amd_randomize_ibs_op() for details.
334 */
335 ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
336 } else {
337 /*
338 * The start value is randomized with a
339 * positive offset, we need to compensate it
340 * with the half of the randomized range. Also
341 * avoid underflows.
342 */
343 ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
344 IBS_OP_MAX_CNT);
345 }
346 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
347 ibs_op_ctl |= IBS_OP_CNT_CTL;
348 ibs_op_ctl |= IBS_OP_ENABLE;
349 val = op_amd_randomize_ibs_op(ibs_op_ctl);
260 wrmsrl(MSR_AMD64_IBSOPCTL, val); 350 wrmsrl(MSR_AMD64_IBSOPCTL, val);
261 } 351 }
262} 352}
263 353
264static void op_amd_stop_ibs(void) 354static void op_amd_stop_ibs(void)
265{ 355{
266 if (has_ibs && ibs_config.fetch_enabled) 356 if (!ibs_caps)
357 return;
358
359 if (ibs_config.fetch_enabled)
267 /* clear max count and enable */ 360 /* clear max count and enable */
268 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); 361 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
269 362
270 if (has_ibs && ibs_config.op_enabled) 363 if (ibs_config.op_enabled)
271 /* clear max count and enable */ 364 /* clear max count and enable */
272 wrmsrl(MSR_AMD64_IBSOPCTL, 0); 365 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
273} 366}
274 367
275#else
276
277static inline void op_amd_handle_ibs(struct pt_regs * const regs,
278 struct op_msrs const * const msrs) { }
279static inline void op_amd_start_ibs(void) { }
280static inline void op_amd_stop_ibs(void) { }
281
282#endif
283
284static int op_amd_check_ctrs(struct pt_regs * const regs, 368static int op_amd_check_ctrs(struct pt_regs * const regs,
285 struct op_msrs const * const msrs) 369 struct op_msrs const * const msrs)
286{ 370{
@@ -314,7 +398,7 @@ static void op_amd_start(struct op_msrs const * const msrs)
314 if (!reset_value[op_x86_phys_to_virt(i)]) 398 if (!reset_value[op_x86_phys_to_virt(i)])
315 continue; 399 continue;
316 rdmsrl(msrs->controls[i].addr, val); 400 rdmsrl(msrs->controls[i].addr, val);
317 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 401 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
318 wrmsrl(msrs->controls[i].addr, val); 402 wrmsrl(msrs->controls[i].addr, val);
319 } 403 }
320 404
@@ -334,7 +418,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
334 if (!reset_value[op_x86_phys_to_virt(i)]) 418 if (!reset_value[op_x86_phys_to_virt(i)])
335 continue; 419 continue;
336 rdmsrl(msrs->controls[i].addr, val); 420 rdmsrl(msrs->controls[i].addr, val);
337 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; 421 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
338 wrmsrl(msrs->controls[i].addr, val); 422 wrmsrl(msrs->controls[i].addr, val);
339 } 423 }
340 424
@@ -355,8 +439,6 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
355 } 439 }
356} 440}
357 441
358#ifdef CONFIG_OPROFILE_IBS
359
360static u8 ibs_eilvt_off; 442static u8 ibs_eilvt_off;
361 443
362static inline void apic_init_ibs_nmi_per_cpu(void *arg) 444static inline void apic_init_ibs_nmi_per_cpu(void *arg)
@@ -405,45 +487,36 @@ static int init_ibs_nmi(void)
405 return 1; 487 return 1;
406 } 488 }
407 489
408#ifdef CONFIG_NUMA
409 /* Sanity check */
410 /* Works only for 64bit with proper numa implementation. */
411 if (nodes != num_possible_nodes()) {
412 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
413 "found: %d, expected %d",
414 nodes, num_possible_nodes());
415 return 1;
416 }
417#endif
418 return 0; 490 return 0;
419} 491}
420 492
421/* uninitialize the APIC for the IBS interrupts if needed */ 493/* uninitialize the APIC for the IBS interrupts if needed */
422static void clear_ibs_nmi(void) 494static void clear_ibs_nmi(void)
423{ 495{
424 if (has_ibs) 496 if (ibs_caps)
425 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); 497 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
426} 498}
427 499
428/* initialize the APIC for the IBS interrupts if available */ 500/* initialize the APIC for the IBS interrupts if available */
429static void ibs_init(void) 501static void ibs_init(void)
430{ 502{
431 has_ibs = boot_cpu_has(X86_FEATURE_IBS); 503 ibs_caps = get_ibs_caps();
432 504
433 if (!has_ibs) 505 if (!ibs_caps)
434 return; 506 return;
435 507
436 if (init_ibs_nmi()) { 508 if (init_ibs_nmi()) {
437 has_ibs = 0; 509 ibs_caps = 0;
438 return; 510 return;
439 } 511 }
440 512
441 printk(KERN_INFO "oprofile: AMD IBS detected\n"); 513 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
514 (unsigned)ibs_caps);
442} 515}
443 516
444static void ibs_exit(void) 517static void ibs_exit(void)
445{ 518{
446 if (!has_ibs) 519 if (!ibs_caps)
447 return; 520 return;
448 521
449 clear_ibs_nmi(); 522 clear_ibs_nmi();
@@ -463,7 +536,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
463 if (ret) 536 if (ret)
464 return ret; 537 return ret;
465 538
466 if (!has_ibs) 539 if (!ibs_caps)
467 return ret; 540 return ret;
468 541
469 /* model specific files */ 542 /* model specific files */
@@ -473,7 +546,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
473 ibs_config.fetch_enabled = 0; 546 ibs_config.fetch_enabled = 0;
474 ibs_config.max_cnt_op = 250000; 547 ibs_config.max_cnt_op = 250000;
475 ibs_config.op_enabled = 0; 548 ibs_config.op_enabled = 0;
476 ibs_config.dispatched_ops = 1; 549 ibs_config.dispatched_ops = 0;
477 550
478 dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); 551 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
479 oprofilefs_create_ulong(sb, dir, "enable", 552 oprofilefs_create_ulong(sb, dir, "enable",
@@ -488,8 +561,9 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
488 &ibs_config.op_enabled); 561 &ibs_config.op_enabled);
489 oprofilefs_create_ulong(sb, dir, "max_count", 562 oprofilefs_create_ulong(sb, dir, "max_count",
490 &ibs_config.max_cnt_op); 563 &ibs_config.max_cnt_op);
491 oprofilefs_create_ulong(sb, dir, "dispatched_ops", 564 if (ibs_caps & IBS_CAPS_OPCNT)
492 &ibs_config.dispatched_ops); 565 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
566 &ibs_config.dispatched_ops);
493 567
494 return 0; 568 return 0;
495} 569}
@@ -507,19 +581,6 @@ static void op_amd_exit(void)
507 ibs_exit(); 581 ibs_exit();
508} 582}
509 583
510#else
511
512/* no IBS support */
513
514static int op_amd_init(struct oprofile_operations *ops)
515{
516 return 0;
517}
518
519static void op_amd_exit(void) {}
520
521#endif /* CONFIG_OPROFILE_IBS */
522
523struct op_x86_model_spec op_amd_spec = { 584struct op_x86_model_spec op_amd_spec = {
524 .num_counters = NUM_COUNTERS, 585 .num_counters = NUM_COUNTERS,
525 .num_controls = NUM_CONTROLS, 586 .num_controls = NUM_CONTROLS,
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index ac6b354becdf..e6a160a4684a 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -394,12 +394,6 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
394 setup_num_counters(); 394 setup_num_counters();
395 stag = get_stagger(); 395 stag = get_stagger();
396 396
397 /* initialize some registers */
398 for (i = 0; i < num_counters; ++i)
399 msrs->counters[i].addr = 0;
400 for (i = 0; i < num_controls; ++i)
401 msrs->controls[i].addr = 0;
402
403 /* the counter & cccr registers we pay attention to */ 397 /* the counter & cccr registers we pay attention to */
404 for (i = 0; i < num_counters; ++i) { 398 for (i = 0; i < num_counters; ++i) {
405 addr = p4_counters[VIRT_CTR(stag, i)].counter_address; 399 addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 8eb05878554c..2bf90fafa7b5 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -37,15 +37,11 @@ static void ppro_fill_in_addresses(struct op_msrs * const msrs)
37 for (i = 0; i < num_counters; i++) { 37 for (i = 0; i < num_counters; i++) {
38 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i)) 38 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
39 msrs->counters[i].addr = MSR_P6_PERFCTR0 + i; 39 msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
40 else
41 msrs->counters[i].addr = 0;
42 } 40 }
43 41
44 for (i = 0; i < num_counters; i++) { 42 for (i = 0; i < num_counters; i++) {
45 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) 43 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
46 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; 44 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
47 else
48 msrs->controls[i].addr = 0;
49 } 45 }
50} 46}
51 47
@@ -57,7 +53,7 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
57 int i; 53 int i;
58 54
59 if (!reset_value) { 55 if (!reset_value) {
60 reset_value = kmalloc(sizeof(reset_value[0]) * num_counters, 56 reset_value = kzalloc(sizeof(reset_value[0]) * num_counters,
61 GFP_ATOMIC); 57 GFP_ATOMIC);
62 if (!reset_value) 58 if (!reset_value)
63 return; 59 return;
@@ -82,9 +78,18 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
82 78
83 /* clear all counters */ 79 /* clear all counters */
84 for (i = 0; i < num_counters; ++i) { 80 for (i = 0; i < num_counters; ++i) {
85 if (unlikely(!msrs->controls[i].addr)) 81 if (unlikely(!msrs->controls[i].addr)) {
82 if (counter_config[i].enabled && !smp_processor_id())
83 /*
84 * counter is reserved, this is on all
85 * cpus, so report only for cpu #0
86 */
87 op_x86_warn_reserved(i);
86 continue; 88 continue;
89 }
87 rdmsrl(msrs->controls[i].addr, val); 90 rdmsrl(msrs->controls[i].addr, val);
91 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
92 op_x86_warn_in_use(i);
88 val &= model->reserved; 93 val &= model->reserved;
89 wrmsrl(msrs->controls[i].addr, val); 94 wrmsrl(msrs->controls[i].addr, val);
90 } 95 }
@@ -161,7 +166,7 @@ static void ppro_start(struct op_msrs const * const msrs)
161 for (i = 0; i < num_counters; ++i) { 166 for (i = 0; i < num_counters; ++i) {
162 if (reset_value[i]) { 167 if (reset_value[i]) {
163 rdmsrl(msrs->controls[i].addr, val); 168 rdmsrl(msrs->controls[i].addr, val);
164 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 169 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
165 wrmsrl(msrs->controls[i].addr, val); 170 wrmsrl(msrs->controls[i].addr, val);
166 } 171 }
167 } 172 }
@@ -179,7 +184,7 @@ static void ppro_stop(struct op_msrs const * const msrs)
179 if (!reset_value[i]) 184 if (!reset_value[i])
180 continue; 185 continue;
181 rdmsrl(msrs->controls[i].addr, val); 186 rdmsrl(msrs->controls[i].addr, val);
182 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; 187 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
183 wrmsrl(msrs->controls[i].addr, val); 188 wrmsrl(msrs->controls[i].addr, val);
184 } 189 }
185} 190}
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index 7b8e75d16081..ff82a755edd4 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -57,6 +57,26 @@ struct op_x86_model_spec {
57 57
58struct op_counter_config; 58struct op_counter_config;
59 59
60static inline void op_x86_warn_in_use(int counter)
61{
62 /*
63 * The warning indicates an already running counter. If
64 * oprofile doesn't collect data, then try using a different
65 * performance counter on your platform to monitor the desired
66 * event. Delete counter #%d from the desired event by editing
67 * the /usr/share/oprofile/%s/<cpu>/events file. If the event
68 * cannot be monitored by any other counter, contact your
69 * hardware or BIOS vendor.
70 */
71 pr_warning("oprofile: counter #%d on cpu #%d may already be used\n",
72 counter, smp_processor_id());
73}
74
75static inline void op_x86_warn_reserved(int counter)
76{
77 pr_warning("oprofile: counter #%d is already reserved\n", counter);
78}
79
60extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, 80extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
61 struct op_counter_config *counter_config); 81 struct op_counter_config *counter_config);
62extern int op_x86_phys_to_virt(int phys); 82extern int op_x86_phys_to_virt(int phys);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 02:31:07 -0500