Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (112 commits)
  sh: Move SH-4 CPU headers down one more level.
  sh: Only build in gpio.o when CONFIG_GENERIC_GPIO is selected.
  sh: Migrate common board headers to mach-common/.
  sh: Move the CPU definition headers from asm/ to cpu/.
  serial: sh-sci: Add support SCIF of SH7723
  video: add sh_mobile_lcdc platform flags
  video: remove unused sh_mobile_lcdc platform data
  sh: remove consistent alloc cruft
  sh: add dynamic crash base address support
  sh: reduce Migo-R smc91x overruns
  sh: Fix up some merge damage.
  Fix debugfs_create_file's error checking method for arch/sh/mm/
  Fix debugfs_create_dir's error checking method for arch/sh/kernel/
  sh: ap325rxa: Add support RTC RX-8564LC in AP325RXA board
  sh: Use sh7720 GPIO on magicpanelr2 board
  sh: Add sh7720 pinmux code
  sh: Use sh7203 GPIO on rsk7203 board
  sh: Add sh7203 pinmux code
  sh: Use sh7723 GPIO on AP325RXA board
  sh: Add sh7723 pinmux code
  ...

163 files changed, 12970 insertions, 1915 deletions

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 2ed5713b7540..cb2c87df70ce 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -12,6 +12,7 @@ config SUPERH
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_GENERIC_DMA_COHERENT
+        select HAVE_IOREMAP_PROT if MMU
         help
           The SuperH is a RISC processor targeted for use in embedded systems
           and consumer electronics; it was also used in the Sega Dreamcast
@@ -20,6 +21,10 @@ config SUPERH
 
 config SUPERH32
         def_bool !SUPERH64
+        select HAVE_KPROBES
+        select HAVE_KRETPROBES
+        select HAVE_ARCH_TRACEHOOK
+        select HAVE_FTRACE
 
 config SUPERH64
         def_bool y if CPU_SH5
@@ -54,8 +59,11 @@ config GENERIC_HARDIRQS_NO__DO_IRQ
 config GENERIC_IRQ_PROBE
         def_bool y
 
+config GENERIC_GPIO
+        def_bool n
+
 config GENERIC_CALIBRATE_DELAY
-        def_bool y
+        bool
 
 config GENERIC_IOMAP
         bool
@@ -66,6 +74,9 @@ config GENERIC_TIME
 config GENERIC_CLOCKEVENTS
         def_bool n
 
+config GENERIC_CLOCKEVENTS_BROADCAST
+        bool
+
 config GENERIC_LOCKBREAK
         def_bool y
         depends on SMP && PREEMPT
@@ -92,6 +103,10 @@ config STACKTRACE_SUPPORT
 config LOCKDEP_SUPPORT
         def_bool y
 
+config HAVE_LATENCYTOP_SUPPORT
+        def_bool y
+        depends on !SMP
+
 config ARCH_HAS_ILOG2_U32
         def_bool n
 
@@ -325,6 +340,7 @@ config CPU_SUBTYPE_SHX3
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_NUMA
         select SYS_SUPPORTS_SMP
+        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 
 # SH4AL-DSP Processor Support
 
@@ -492,7 +508,6 @@ config CRASH_DUMP
 config SECCOMP
         bool "Enable seccomp to safely compute untrusted bytecode"
         depends on PROC_FS
-        default y
         help
           This kernel feature is useful for number crunching applications
           that may need to compute untrusted bytecode during their
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 4d2d102e00d5..e6d2c8b11abd 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -82,7 +82,7 @@ config DEBUG_STACK_USAGE
 
 config 4KSTACKS
         bool "Use 4Kb for kernel stacks instead of 8Kb"
-        depends on DEBUG_KERNEL && (MMU || BROKEN)
+        depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
         help
           If you say Y here the kernel will use a 4Kb stacksize for the
           kernel stack attached to each process/thread. This facilitates
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 01d85c74481d..1f409bf81809 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -76,8 +76,10 @@ KBUILD_IMAGE		:= $(defaultimage-y)
 # error messages during linking.
 #
 ifdef CONFIG_SUPERH32
+UTS_MACHINE     := sh
 LDFLAGS_vmlinux += -e _stext
 else
+UTS_MACHINE     := sh64
 LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
                    --defsym phys_stext_shmedia=phys_stext+1 \
                    -e phys_stext_shmedia
@@ -123,6 +125,9 @@ core-y	+= $(addprefix arch/sh/boards/, \
              $(filter-out ., $(patsubst %,%/,$(machdir-y))))
 endif
 
+# Common machine type headers. Not part of the arch/sh/boards/ hierarchy.
+machdir-y       += mach-common
+
 # Companion chips
 core-$(CONFIG_HD6446X_SERIES)   += arch/sh/cchips/hd6446x/
 
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index ae194869fd60..50467f9d0d0b 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -128,6 +128,7 @@ config SH_RTS7751R2D
 
 config SH_RSK7203
         bool "RSK7203"
+        select GENERIC_GPIO
         depends on CPU_SUBTYPE_SH7203
 
 config SH_SDK7780
@@ -162,6 +163,7 @@ config SH_SH7785LCR_29BIT_PHYSMAPS
 config SH_MIGOR
         bool "Migo-R"
         depends on CPU_SUBTYPE_SH7722
+        select GENERIC_GPIO
         help
           Select Migo-R if configuring for the SH7722 Migo-R platform
           by Renesas System Solutions Asia Pte. Ltd.
@@ -169,6 +171,7 @@ config SH_MIGOR
 config SH_AP325RXA
         bool "AP-325RXA"
         depends on CPU_SUBTYPE_SH7723
+        select GENERIC_GPIO
         help
           Renesas "AP-325RXA" support.
           Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
@@ -184,6 +187,13 @@ config SH_EDOSK7705
         bool "EDOSK7705"
         depends on CPU_SUBTYPE_SH7705
 
+config SH_EDOSK7760
+        bool "EDOSK7760"
+        depends on CPU_SUBTYPE_SH7760
+        help
+          Select if configuring for a Renesas EDOSK7760
+          evaluation board.
+
 config SH_SH4202_MICRODEV
         bool "SH4-202 MicroDev"
         depends on CPU_SUBTYPE_SH4_202
@@ -228,6 +238,7 @@ config SH_X3PROTO
 config SH_MAGIC_PANEL_R2
         bool "Magic Panel R2"
         depends on CPU_SUBTYPE_SH7720
+        select GENERIC_GPIO
         help
           Select Magic Panel R2 if configuring for Magic Panel R2.
 
diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile
index 463022c7df3c..d9efa3923721 100644
--- a/arch/sh/boards/Makefile
+++ b/arch/sh/boards/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_SH_MAGIC_PANEL_R2)	+= board-magicpanelr2.o
 obj-$(CONFIG_SH_RSK7203)        += board-rsk7203.o
 obj-$(CONFIG_SH_SH7785LCR)      += board-sh7785lcr.o
 obj-$(CONFIG_SH_SHMIN)          += board-shmin.o
+obj-$(CONFIG_SH_EDOSK7760)      += board-edosk7760.o
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index fd1612590bf4..7c7874e6ac36 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -18,11 +18,13 @@
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/smc911x.h>
+#include <linux/gpio.h>
 #include <media/soc_camera_platform.h>
 #include <media/sh_mobile_ceu.h>
-#include <asm/sh_mobile_lcdc.h>
+#include <video/sh_mobile_lcdc.h>
 #include <asm/io.h>
 #include <asm/clock.h>
+#include <cpu/sh7723.h>
 
 static struct smc911x_platdata smc911x_info = {
         .flags = SMC911X_USE_32BIT,
@@ -52,20 +54,33 @@ static struct platform_device smc9118_device = {
         },
 };
 
+/*
+ * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
+ * If this area erased, this board can not boot.
+ */
 static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
         {
-                 .name = "uboot",
-                 .offset = 0,
-                 .size = (1 * 1024 * 1024),
-                 .mask_flags = MTD_WRITEABLE,   /* Read-only */
+                .name = "uboot",
+                .offset = 0,
+                .size = (1 * 1024 * 1024),
+                .mask_flags = MTD_WRITEABLE,    /* Read-only */
+        }, {
+                .name = "kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = (2 * 1024 * 1024),
+        }, {
+                .name = "free-area0",
+                .offset = MTDPART_OFS_APPEND,
+                .size = ((7 * 1024 * 1024) + (512 * 1024)),
         }, {
-                 .name = "kernel",
-                 .offset = MTDPART_OFS_APPEND,
-                 .size = (2 * 1024 * 1024),
+                .name = "CPLD-Data",
+                .offset = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,    /* Read-only */
+                .size = (1024 * 128 * 2),
         }, {
-                 .name = "other",
-                 .offset = MTDPART_OFS_APPEND,
-                 .size = MTDPART_SIZ_FULL,
+                .name = "free-area1",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
         },
 };
 
@@ -96,17 +111,7 @@ static struct platform_device ap325rxa_nor_flash_device = {
 #define FPGA_LCDREG     0xB4100180
 #define FPGA_BKLREG     0xB4100212
 #define FPGA_LCDREG_VAL 0x0018
-#define PORT_PHCR       0xA405010E
-#define PORT_PLCR       0xA4050114
-#define PORT_PMCR       0xA4050116
-#define PORT_PRCR       0xA405011C
-#define PORT_PSCR       0xA405011E
-#define PORT_PZCR       0xA405014C
-#define PORT_HIZCRA     0xA4050158
 #define PORT_MSELCRB    0xA4050182
-#define PORT_PSDR       0xA405013E
-#define PORT_PZDR       0xA405016C
-#define PORT_PSELD      0xA4050154
 
 static void ap320_wvga_power_on(void *board_data)
 {
@@ -116,8 +121,7 @@ static void ap320_wvga_power_on(void *board_data)
         ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
 
         /* backlight */
-        ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR);
-        ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR);
+        gpio_set_value(GPIO_PTS3, 0);
         ctrl_outw(0x100, FPGA_BKLREG);
 }
 
@@ -281,12 +285,84 @@ static struct platform_device *ap325rxa_devices[] __initdata = {
 };
 
 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
 };
 
 static int __init ap325rxa_devices_setup(void)
 {
-        clk_always_enable("mstp200"); /* LCDC */
-        clk_always_enable("mstp203"); /* CEU */
+        /* LD3 and LD4 LEDs */
+        gpio_request(GPIO_PTX5, NULL); /* RUN */
+        gpio_direction_output(GPIO_PTX5, 1);
+        gpio_export(GPIO_PTX5, 0);
+
+        gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
+        gpio_direction_output(GPIO_PTX4, 0);
+        gpio_export(GPIO_PTX4, 0);
+
+        /* SW1 input */
+        gpio_request(GPIO_PTF7, NULL); /* MODE */
+        gpio_direction_input(GPIO_PTF7);
+        gpio_export(GPIO_PTF7, 0);
+
+        /* LCDC */
+        clk_always_enable("mstp200");
+        gpio_request(GPIO_FN_LCDD15, NULL);
+        gpio_request(GPIO_FN_LCDD14, NULL);
+        gpio_request(GPIO_FN_LCDD13, NULL);
+        gpio_request(GPIO_FN_LCDD12, NULL);
+        gpio_request(GPIO_FN_LCDD11, NULL);
+        gpio_request(GPIO_FN_LCDD10, NULL);
+        gpio_request(GPIO_FN_LCDD9, NULL);
+        gpio_request(GPIO_FN_LCDD8, NULL);
+        gpio_request(GPIO_FN_LCDD7, NULL);
+        gpio_request(GPIO_FN_LCDD6, NULL);
+        gpio_request(GPIO_FN_LCDD5, NULL);
+        gpio_request(GPIO_FN_LCDD4, NULL);
+        gpio_request(GPIO_FN_LCDD3, NULL);
+        gpio_request(GPIO_FN_LCDD2, NULL);
+        gpio_request(GPIO_FN_LCDD1, NULL);
+        gpio_request(GPIO_FN_LCDD0, NULL);
+        gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
+        gpio_request(GPIO_FN_LCDDCK, NULL);
+        gpio_request(GPIO_FN_LCDVEPWC, NULL);
+        gpio_request(GPIO_FN_LCDVCPWC, NULL);
+        gpio_request(GPIO_FN_LCDVSYN, NULL);
+        gpio_request(GPIO_FN_LCDHSYN, NULL);
+        gpio_request(GPIO_FN_LCDDISP, NULL);
+        gpio_request(GPIO_FN_LCDDON, NULL);
+
+        /* LCD backlight */
+        gpio_request(GPIO_PTS3, NULL);
+        gpio_direction_output(GPIO_PTS3, 1);
+
+        /* CEU */
+        clk_always_enable("mstp203");
+        gpio_request(GPIO_FN_VIO_CLK2, NULL);
+        gpio_request(GPIO_FN_VIO_VD2, NULL);
+        gpio_request(GPIO_FN_VIO_HD2, NULL);
+        gpio_request(GPIO_FN_VIO_FLD, NULL);
+        gpio_request(GPIO_FN_VIO_CKO, NULL);
+        gpio_request(GPIO_FN_VIO_D15, NULL);
+        gpio_request(GPIO_FN_VIO_D14, NULL);
+        gpio_request(GPIO_FN_VIO_D13, NULL);
+        gpio_request(GPIO_FN_VIO_D12, NULL);
+        gpio_request(GPIO_FN_VIO_D11, NULL);
+        gpio_request(GPIO_FN_VIO_D10, NULL);
+        gpio_request(GPIO_FN_VIO_D9, NULL);
+        gpio_request(GPIO_FN_VIO_D8, NULL);
+
+        gpio_request(GPIO_PTZ7, NULL);
+        gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
+        gpio_request(GPIO_PTZ6, NULL);
+        gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
+        gpio_request(GPIO_PTZ5, NULL);
+        gpio_direction_output(GPIO_PTZ5, 1); /* RST_CAM */
+        gpio_request(GPIO_PTZ4, NULL);
+        gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
+
+        ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
 
         platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
 
@@ -300,18 +376,6 @@ device_initcall(ap325rxa_devices_setup);
 
 static void __init ap325rxa_setup(char **cmdline_p)
 {
-        /* LCDC configuration */
-        ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR);
-        ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR);
-        ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR);
-        ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA);
-
-        /* CEU */
-        ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
-        ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD);
-        ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR);
-        ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR);
 }
 
 static struct sh_machine_vector mv_ap325rxa __initmv = {
diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c
new file mode 100644
index 000000000000..35dc0994875d
--- /dev/null
+++ b/arch/sh/boards/board-edosk7760.c
@@ -0,0 +1,193 @@
+/*
+ * Renesas Europe EDOSK7760 Board Support
+ *
+ * Copyright (C) 2008 SPES Societa' Progettazione Elettronica e Software Ltd.
+ * Author: Luca Santini <luca.santini@spesonline.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/smc91x.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/mtd/physmap.h>
+#include <asm/machvec.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/delay.h>
+#include <asm/i2c-sh7760.h>
+#include <asm/sizes.h>
+
+/* Bus state controller registers for CS4 area */
+#define BSC_CS4BCR      0xA4FD0010
+#define BSC_CS4WCR      0xA4FD0030
+
+#define SMC_IOBASE      0xA2000000
+#define SMC_IO_OFFSET   0x300
+#define SMC_IOADDR      (SMC_IOBASE + SMC_IO_OFFSET)
+
+#define ETHERNET_IRQ    5
+
+/* NOR flash */
+static struct mtd_partition edosk7760_nor_flash_partitions[] = {
+        {
+                .name = "bootloader",
+                .offset = 0,
+                .size = SZ_256K,
+                .mask_flags = MTD_WRITEABLE,    /* Read-only */
+        }, {
+                .name = "kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_2M,
+        }, {
+                .name = "fs",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_26M,
+        }, {
+                .name = "other",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data edosk7760_nor_flash_data = {
+        .width          = 4,
+        .parts          = edosk7760_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(edosk7760_nor_flash_partitions),
+};
+
+static struct resource edosk7760_nor_flash_resources[] = {
+        [0] = {
+                .name   = "NOR Flash",
+                .start  = 0x00000000,
+                .end    = 0x00000000 + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device edosk7760_nor_flash_device = {
+        .name           = "physmap-flash",
+        .resource       = edosk7760_nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(edosk7760_nor_flash_resources),
+        .dev            = {
+                .platform_data = &edosk7760_nor_flash_data,
+        },
+};
+
+/* i2c initialization functions */
+static struct sh7760_i2c_platdata i2c_pd = {
+        .speed_khz      = 400,
+};
+
+static struct resource sh7760_i2c1_res[] = {
+        {
+                .start  = SH7760_I2C1_MMIO,
+                .end    = SH7760_I2C1_MMIOEND,
+                .flags  = IORESOURCE_MEM,
+        },{
+                .start  = SH7760_I2C1_IRQ,
+                .end    = SH7760_I2C1_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh7760_i2c1_dev = {
+        .dev    = {
+                .platform_data  = &i2c_pd,
+        },
+
+        .name           = SH7760_I2C_DEVNAME,
+        .id             = 1,
+        .resource       = sh7760_i2c1_res,
+        .num_resources  = ARRAY_SIZE(sh7760_i2c1_res),
+};
+
+static struct resource sh7760_i2c0_res[] = {
+        {
+                .start  = SH7760_I2C0_MMIO,
+                .end    = SH7760_I2C0_MMIOEND,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = SH7760_I2C0_IRQ,
+                .end    = SH7760_I2C0_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh7760_i2c0_dev = {
+        .dev    = {
+                .platform_data  = &i2c_pd,
+        },
+        .name           = SH7760_I2C_DEVNAME,
+        .id             = 0,
+        .resource       = sh7760_i2c0_res,
+        .num_resources  = ARRAY_SIZE(sh7760_i2c0_res),
+};
+
+/* eth initialization functions */
+static struct smc91x_platdata smc91x_info = {
+        .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL,
+};
+
+static struct resource smc91x_res[] = {
+        [0] = {
+                .start  = SMC_IOADDR,
+                .end    = SMC_IOADDR + SZ_32 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ETHERNET_IRQ,
+                .end    = ETHERNET_IRQ,
+                .flags  = IORESOURCE_IRQ ,
+        }
+};
+
+static struct platform_device smc91x_dev = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91x_res),
+        .resource       = smc91x_res,
+
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
+};
+
+/* platform init code */
+static struct platform_device *edosk7760_devices[] __initdata = {
+        &smc91x_dev,
+        &edosk7760_nor_flash_device,
+        &sh7760_i2c0_dev,
+        &sh7760_i2c1_dev,
+};
+
+static int __init init_edosk7760_devices(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRQ);
+
+        return platform_add_devices(edosk7760_devices,
+                                    ARRAY_SIZE(edosk7760_devices));
+}
+__initcall(init_edosk7760_devices);
+
+/*
+ * The Machine Vector
+ */
+struct sh_machine_vector mv_edosk7760 __initmv = {
+        .mv_name        = "EDOSK7760",
+        .mv_nr_irqs     = 128,
+};
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index f3b8b07ea5d6..3de22ccdeb7e 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -13,12 +13,14 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/map.h>
-#include <asm/magicpanelr2.h>
+#include <mach/magicpanelr2.h>
 #include <asm/heartbeat.h>
+#include <cpu/sh7720.h>
 
 #define LAN9115_READY   (ctrl_inl(0xA8000084UL) & 0x00000001UL)
 
@@ -170,7 +172,14 @@ static void __init setup_port_multiplexing(void)
         /* R7 A25;           R6 A24;         R5 A23;              R4 A22;
          * R3 A21;           R2 A20;         R1 A19;              R0 A0;
          */
-        ctrl_outw(0x0000, PORT_PRCR);   /* 00 00 00 00 00 00 00 00 */
+        gpio_request(GPIO_FN_A25, NULL);
+        gpio_request(GPIO_FN_A24, NULL);
+        gpio_request(GPIO_FN_A23, NULL);
+        gpio_request(GPIO_FN_A22, NULL);
+        gpio_request(GPIO_FN_A21, NULL);
+        gpio_request(GPIO_FN_A20, NULL);
+        gpio_request(GPIO_FN_A19, NULL);
+        gpio_request(GPIO_FN_A0, NULL);
 
         /* S7 (x);              S6 (x);        S5 (x);       S4 GPO(EEPROM_CS2);
          * S3 GPO(EEPROM_CS1);  S2 SIOF0_TXD;  S1 SIOF0_RXD; S0 SIOF0_SCK;
diff --git a/arch/sh/boards/board-rsk7203.c b/arch/sh/boards/board-rsk7203.c
index ffbedc59a973..ded799cf3eae 100644
--- a/arch/sh/boards/board-rsk7203.c
+++ b/arch/sh/boards/board-rsk7203.c
@@ -16,8 +16,10 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/map.h>
 #include <linux/smc911x.h>
+#include <linux/gpio.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
+#include <asm/sh7203.h>
 
 static struct smc911x_platdata smc911x_info = {
         .flags          = SMC911X_USE_16BIT,
@@ -122,6 +124,15 @@ static struct platform_device *rsk7203_devices[] __initdata = {
 
 static int __init rsk7203_devices_setup(void)
 {
+        /* Select pins for SCIF0 */
+        gpio_request(GPIO_FN_TXD0, NULL);
+        gpio_request(GPIO_FN_RXD0, NULL);
+
+        /* Lit LED0 */
+        gpio_request(GPIO_PE10, NULL);
+        gpio_direction_output(GPIO_PE10, 0);
+        gpio_export(GPIO_PE10, 0);
+
         set_mtd_partitions();
         return platform_add_devices(rsk7203_devices,
                                     ARRAY_SIZE(rsk7203_devices));
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index b95d674ee704..408bbddaf325 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -19,7 +19,7 @@
 #include <linux/i2c-pca-platform.h>
 #include <linux/i2c-algo-pca.h>
 #include <asm/heartbeat.h>
-#include <asm/sh7785lcr.h>
+#include <mach/sh7785lcr.h>
 
 /*
  * NOTE: This board has 2 physical memory maps.
diff --git a/arch/sh/boards/board-shmin.c b/arch/sh/boards/board-shmin.c
index 16e5dae8ecfb..5cc0867de5ab 100644
--- a/arch/sh/boards/board-shmin.c
+++ b/arch/sh/boards/board-shmin.c
@@ -8,7 +8,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/machvec.h>
-#include <asm/shmin.h>
+#include <mach/shmin.h>
 #include <asm/clock.h>
 #include <asm/io.h>
 
diff --git a/arch/sh/boards/mach-edosk7705/io.c b/arch/sh/boards/mach-edosk7705/io.c
index 541cea2a652f..7d153e50a01b 100644
--- a/arch/sh/boards/mach-edosk7705/io.c
+++ b/arch/sh/boards/mach-edosk7705/io.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <asm/io.h>
-#include <asm/edosk7705/io.h>
+#include <mach/edosk7705.h>
 #include <asm/addrspace.h>
 
 #define SMC_IOADDR      0xA2000000
diff --git a/arch/sh/boards/mach-edosk7705/setup.c b/arch/sh/boards/mach-edosk7705/setup.c
index f076c45308dd..ab3f47bffdf3 100644
--- a/arch/sh/boards/mach-edosk7705/setup.c
+++ b/arch/sh/boards/mach-edosk7705/setup.c
@@ -10,7 +10,7 @@
  */
 #include <linux/init.h>
 #include <asm/machvec.h>
-#include <asm/edosk7705/io.h>
+#include <mach/edosk7705.h>
 
 static void __init sh_edosk7705_init_irq(void)
 {
diff --git a/arch/sh/boards/mach-highlander/irq-r7780mp.c b/arch/sh/boards/mach-highlander/irq-r7780mp.c
index ae1cfcb29700..83c28bcd4d2a 100644
--- a/arch/sh/boards/mach-highlander/irq-r7780mp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780mp.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/r7780rp.h>
+#include <mach/highlander.h>
 
 enum {
         UNUSED = 0,
diff --git a/arch/sh/boards/mach-highlander/irq-r7780rp.c b/arch/sh/boards/mach-highlander/irq-r7780rp.c
index 9d3921fe27c0..b721e86b5af4 100644
--- a/arch/sh/boards/mach-highlander/irq-r7780rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780rp.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/r7780rp.h>
+#include <mach/highlander.h>
 
 enum {
         UNUSED = 0,
diff --git a/arch/sh/boards/mach-highlander/irq-r7785rp.c b/arch/sh/boards/mach-highlander/irq-r7785rp.c
index 896c045aa39d..3811b060a39b 100644
--- a/arch/sh/boards/mach-highlander/irq-r7785rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7785rp.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/r7780rp.h>
+#include <mach/highlander.h>
 
 enum {
         UNUSED = 0,
diff --git a/arch/sh/boards/mach-highlander/psw.c b/arch/sh/boards/mach-highlander/psw.c
index be8d5477fc65..37b1a2ee71a5 100644
--- a/arch/sh/boards/mach-highlander/psw.c
+++ b/arch/sh/boards/mach-highlander/psw.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <asm/r7780rp.h>
+#include <mach/highlander.h>
 #include <asm/push-switch.h>
 
 static irqreturn_t psw_irq_handler(int irq, void *arg)
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index bc79afb6fc4c..c5a40f7906d7 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -20,7 +20,7 @@
 #include <linux/i2c.h>
 #include <net/ax88796.h>
 #include <asm/machvec.h>
-#include <asm/r7780rp.h>
+#include <mach/highlander.h>
 #include <asm/clock.h>
 #include <asm/heartbeat.h>
 #include <asm/io.h>
diff --git a/arch/sh/boards/mach-hp6xx/hp6xx_apm.c b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
index 177f4f028e0d..e85212faf40a 100644
--- a/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
+++ b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
@@ -14,7 +14,7 @@
 #include <linux/apm-emulation.h>
 #include <linux/io.h>
 #include <asm/adc.h>
-#include <asm/hp6xx.h>
+#include <mach/hp6xx.h>
 
 /* percentage values */
 #define APM_CRITICAL                    10
diff --git a/arch/sh/boards/mach-hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c
index e96684def788..64af1f2eef05 100644
--- a/arch/sh/boards/mach-hp6xx/pm.c
+++ b/arch/sh/boards/mach-hp6xx/pm.c
@@ -12,7 +12,7 @@
 #include <linux/time.h>
 #include <asm/io.h>
 #include <asm/hd64461.h>
-#include <asm/hp6xx.h>
+#include <mach/hp6xx.h>
 #include <cpu/dac.h>
 #include <asm/pm.h>
 
diff --git a/arch/sh/boards/mach-hp6xx/setup.c b/arch/sh/boards/mach-hp6xx/setup.c
index 475b46caec1f..48fece78ff54 100644
--- a/arch/sh/boards/mach-hp6xx/setup.c
+++ b/arch/sh/boards/mach-hp6xx/setup.c
@@ -15,7 +15,7 @@
 #include <asm/hd64461.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/hp6xx.h>
+#include <mach/hp6xx.h>
 #include <cpu/dac.h>
 
 #define SCPCR   0xa4000116
diff --git a/arch/sh/boards/mach-lboxre2/irq.c b/arch/sh/boards/mach-lboxre2/irq.c
index 5a1c3bbe7b50..8aa171ab833e 100644
--- a/arch/sh/boards/mach-lboxre2/irq.c
+++ b/arch/sh/boards/mach-lboxre2/irq.c
@@ -15,7 +15,7 @@
 #include <linux/irq.h>
 #include <asm/irq.h>
 #include <asm/io.h>
-#include <asm/lboxre2.h>
+#include <mach/lboxre2.h>
 
 /*
  * Initialize IRQ setting
diff --git a/arch/sh/boards/mach-lboxre2/setup.c b/arch/sh/boards/mach-lboxre2/setup.c
index c74440d38ee9..2b0b5818e1e4 100644
--- a/arch/sh/boards/mach-lboxre2/setup.c
+++ b/arch/sh/boards/mach-lboxre2/setup.c
@@ -16,7 +16,7 @@
 #include <linux/ata_platform.h>
 #include <asm/machvec.h>
 #include <asm/addrspace.h>
-#include <asm/lboxre2.h>
+#include <mach/lboxre2.h>
 #include <asm/io.h>
 
 static struct resource cf_ide_resources[] = {
diff --git a/arch/sh/boards/mach-microdev/io.c b/arch/sh/boards/mach-microdev/io.c
index 9f8a540f7e14..52dd748211c7 100644
--- a/arch/sh/boards/mach-microdev/io.c
+++ b/arch/sh/boards/mach-microdev/io.c
@@ -15,7 +15,7 @@
 #include <linux/pci.h>
 #include <linux/wait.h>
 #include <asm/io.h>
-#include <asm/microdev.h>
+#include <mach/microdev.h>
 
         /*
          *      we need to have a 'safe' address to re-direct all I/O requests
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index 4d335077a3ff..702753cbd28f 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/microdev.h>
+#include <mach/microdev.h>
 
 #define NUM_EXTERNAL_IRQS 16    /* IRL0 .. IRL15 */
 
diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c
index fc8cd06d66cf..a9202fe3cb59 100644
--- a/arch/sh/boards/mach-microdev/setup.c
+++ b/arch/sh/boards/mach-microdev/setup.c
@@ -14,7 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/ioport.h>
 #include <video/s1d13xxxfb.h>
-#include <asm/microdev.h>
+#include <mach/microdev.h>
 #include <asm/io.h>
 #include <asm/machvec.h>
 
diff --git a/arch/sh/boards/mach-migor/lcd_qvga.c b/arch/sh/boards/mach-migor/lcd_qvga.c
index 6e9609596448..de9014a8a93e 100644
--- a/arch/sh/boards/mach-migor/lcd_qvga.c
+++ b/arch/sh/boards/mach-migor/lcd_qvga.c
@@ -17,8 +17,10 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <asm/sh_mobile_lcdc.h>
-#include <asm/migor.h>
+#include <linux/gpio.h>
+#include <video/sh_mobile_lcdc.h>
+#include <cpu/sh7722.h>
+#include <mach/migor.h>
 
 /* LCD Module is a PH240320T according to board schematics. This module
  * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
@@ -30,9 +32,9 @@
 
 static void reset_lcd_module(void)
 {
-        ctrl_outb(ctrl_inb(PORT_PHDR) & ~0x04, PORT_PHDR);
+        gpio_set_value(GPIO_PTH2, 0);
         mdelay(2);
-        ctrl_outb(ctrl_inb(PORT_PHDR) | 0x04, PORT_PHDR);
+        gpio_set_value(GPIO_PTH2, 1);
         mdelay(1);
 }
 
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 714dce91cc9b..769d63043424 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -17,14 +17,16 @@
 #include <linux/smc91x.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 #include <media/soc_camera_platform.h>
 #include <media/sh_mobile_ceu.h>
+#include <video/sh_mobile_lcdc.h>
 #include <asm/clock.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
 #include <asm/sh_keysc.h>
-#include <asm/sh_mobile_lcdc.h>
-#include <asm/migor.h>
+#include <mach/migor.h>
+#include <cpu/sh7722.h>
 
 /* Address     IRQ  Size  Bus  Description
  * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
@@ -35,7 +37,7 @@
  */
 
 static struct smc91x_platdata smc91x_info = {
-        .flags = SMC91X_USE_16BIT,
+        .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
 
 static struct resource smc91x_eth_resources[] = {
@@ -169,7 +171,7 @@ static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
 
 static int migor_nand_flash_ready(struct mtd_info *mtd)
 {
-        return ctrl_inb(PORT_PADR) & 0x02; /* PTA1 */
+        return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
 }
 
 struct platform_nand_data migor_nand_flash_data = {
@@ -286,22 +288,15 @@ static struct clk *camera_clk;
 
 static void camera_power_on(void)
 {
-        unsigned char value;
-
         camera_clk = clk_get(NULL, "video_clk");
         clk_set_rate(camera_clk, 24000000);
         clk_enable(camera_clk); /* start VIO_CKO */
 
+        /* use VIO_RST to take camera out of reset */
         mdelay(10);
-        value = ctrl_inb(PORT_PTDR);
-        value &= ~0x09;
-#ifndef CONFIG_SH_MIGOR_RTA_WVGA
-        value |= 0x01;
-#endif
-        ctrl_outb(value, PORT_PTDR);
+        gpio_set_value(GPIO_PTT3, 0);
         mdelay(10);
-
-        ctrl_outb(value | 8, PORT_PTDR);
+        gpio_set_value(GPIO_PTT3, 1);
 }
 
 static void camera_power_off(void)
@@ -309,7 +304,7 @@ static void camera_power_off(void)
         clk_disable(camera_clk); /* stop VIO_CKO */
         clk_put(camera_clk);
 
-        ctrl_outb(ctrl_inb(PORT_PTDR) & ~0x08, PORT_PTDR);
+        gpio_set_value(GPIO_PTT3, 0);
 }
 
 #ifdef CONFIG_I2C
@@ -458,75 +453,135 @@ static struct i2c_board_info migor_i2c_devices[] = {
 
 static int __init migor_devices_setup(void)
 {
+        /* Lit D11 LED */
+        gpio_request(GPIO_PTJ7, NULL);
+        gpio_direction_output(GPIO_PTJ7, 1);
+        gpio_export(GPIO_PTJ7, 0);
+
+        /* Lit D12 LED */
+        gpio_request(GPIO_PTJ5, NULL);
+        gpio_direction_output(GPIO_PTJ5, 1);
+        gpio_export(GPIO_PTJ5, 0);
+
+        /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
+        gpio_request(GPIO_FN_IRQ0, NULL);
+        ctrl_outl(0x00003400, BSC_CS4BCR);
+        ctrl_outl(0x00110080, BSC_CS4WCR);
+
+        /* KEYSC */
         clk_always_enable("mstp214"); /* KEYSC */
+        gpio_request(GPIO_FN_KEYOUT0, NULL);
+        gpio_request(GPIO_FN_KEYOUT1, NULL);
+        gpio_request(GPIO_FN_KEYOUT2, NULL);
+        gpio_request(GPIO_FN_KEYOUT3, NULL);
+        gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
+        gpio_request(GPIO_FN_KEYIN1, NULL);
+        gpio_request(GPIO_FN_KEYIN2, NULL);
+        gpio_request(GPIO_FN_KEYIN3, NULL);
+        gpio_request(GPIO_FN_KEYIN4, NULL);
+        gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
+
+        /* NAND Flash */
+        gpio_request(GPIO_FN_CS6A_CE2B, NULL);
+        ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
+        gpio_request(GPIO_PTA1, NULL);
+        gpio_direction_input(GPIO_PTA1);
+
+        /* Touch Panel */
+        gpio_request(GPIO_FN_IRQ6, NULL);
+
+        /* LCD Panel */
         clk_always_enable("mstp200"); /* LCDC */
+#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
+        gpio_request(GPIO_FN_LCDD17, NULL);
+        gpio_request(GPIO_FN_LCDD16, NULL);
+        gpio_request(GPIO_FN_LCDD15, NULL);
+        gpio_request(GPIO_FN_LCDD14, NULL);
+        gpio_request(GPIO_FN_LCDD13, NULL);
+        gpio_request(GPIO_FN_LCDD12, NULL);
+        gpio_request(GPIO_FN_LCDD11, NULL);
+        gpio_request(GPIO_FN_LCDD10, NULL);
+        gpio_request(GPIO_FN_LCDD8, NULL);
+        gpio_request(GPIO_FN_LCDD7, NULL);
+        gpio_request(GPIO_FN_LCDD6, NULL);
+        gpio_request(GPIO_FN_LCDD5, NULL);
+        gpio_request(GPIO_FN_LCDD4, NULL);
+        gpio_request(GPIO_FN_LCDD3, NULL);
+        gpio_request(GPIO_FN_LCDD2, NULL);
+        gpio_request(GPIO_FN_LCDD1, NULL);
+        gpio_request(GPIO_FN_LCDRS, NULL);
+        gpio_request(GPIO_FN_LCDCS, NULL);
+        gpio_request(GPIO_FN_LCDRD, NULL);
+        gpio_request(GPIO_FN_LCDWR, NULL);
+        gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
+        gpio_direction_output(GPIO_PTH2, 1);
+#endif
+#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
+        gpio_request(GPIO_FN_LCDD15, NULL);
+        gpio_request(GPIO_FN_LCDD14, NULL);
+        gpio_request(GPIO_FN_LCDD13, NULL);
+        gpio_request(GPIO_FN_LCDD12, NULL);
+        gpio_request(GPIO_FN_LCDD11, NULL);
+        gpio_request(GPIO_FN_LCDD10, NULL);
+        gpio_request(GPIO_FN_LCDD9, NULL);
+        gpio_request(GPIO_FN_LCDD8, NULL);
+        gpio_request(GPIO_FN_LCDD7, NULL);
+        gpio_request(GPIO_FN_LCDD6, NULL);
+        gpio_request(GPIO_FN_LCDD5, NULL);
+        gpio_request(GPIO_FN_LCDD4, NULL);
+        gpio_request(GPIO_FN_LCDD3, NULL);
+        gpio_request(GPIO_FN_LCDD2, NULL);
+        gpio_request(GPIO_FN_LCDD1, NULL);
+        gpio_request(GPIO_FN_LCDD0, NULL);
+        gpio_request(GPIO_FN_LCDLCLK, NULL);
+        gpio_request(GPIO_FN_LCDDCK, NULL);
+        gpio_request(GPIO_FN_LCDVEPWC, NULL);
+        gpio_request(GPIO_FN_LCDVCPWC, NULL);
+        gpio_request(GPIO_FN_LCDVSYN, NULL);
+        gpio_request(GPIO_FN_LCDHSYN, NULL);
+        gpio_request(GPIO_FN_LCDDISP, NULL);
+        gpio_request(GPIO_FN_LCDDON, NULL);
+#endif
+
+        /* CEU */
         clk_always_enable("mstp203"); /* CEU */
+        gpio_request(GPIO_FN_VIO_CLK2, NULL);
+        gpio_request(GPIO_FN_VIO_VD2, NULL);
+        gpio_request(GPIO_FN_VIO_HD2, NULL);
+        gpio_request(GPIO_FN_VIO_FLD, NULL);
+        gpio_request(GPIO_FN_VIO_CKO, NULL);
+        gpio_request(GPIO_FN_VIO_D15, NULL);
+        gpio_request(GPIO_FN_VIO_D14, NULL);
+        gpio_request(GPIO_FN_VIO_D13, NULL);
+        gpio_request(GPIO_FN_VIO_D12, NULL);
+        gpio_request(GPIO_FN_VIO_D11, NULL);
+        gpio_request(GPIO_FN_VIO_D10, NULL);
+        gpio_request(GPIO_FN_VIO_D9, NULL);
+        gpio_request(GPIO_FN_VIO_D8, NULL);
+
+        gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
+        gpio_direction_output(GPIO_PTT3, 0);
+        gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
+        gpio_direction_output(GPIO_PTT2, 1);
+        gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
+#ifdef CONFIG_SH_MIGOR_RTA_WVGA
+        gpio_direction_output(GPIO_PTT0, 0);
+#else
+        gpio_direction_output(GPIO_PTT0, 1);
+#endif
+        ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
 
         platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
 
         i2c_register_board_info(0, migor_i2c_devices,
                                 ARRAY_SIZE(migor_i2c_devices));
- 
+
         return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
 }
 __initcall(migor_devices_setup);
 
 static void __init migor_setup(char **cmdline_p)
 {
-        /* SMC91C111 - Enable IRQ0 */
-        ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR);
-
-        /* KEYSC */
-        ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR);
-        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR);
-        ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
-        ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
-
-        /* NAND Flash */
-        ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
-        ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
-                  BSC_CS6ABCR);
-
-        /* Touch Panel - Enable IRQ6 */
-        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
-        ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
-        ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
-
-#ifdef CONFIG_SH_MIGOR_RTA_WVGA
-        /* LCDC - WVGA - Enable RGB Interface signals */
-        ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR);
-        ctrl_outw(0x0000, PORT_PHCR);
-        ctrl_outw(0x0000, PORT_PLCR);
-        ctrl_outw(0x0000, PORT_PMCR);
-        ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x000f, PORT_PRCR);
-        ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x000d) | 0x0400, PORT_PSELD);
-        ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0100, PORT_MSELCRB);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA);
-#endif
-#ifdef CONFIG_SH_MIGOR_QVGA
-        /* LCDC - QVGA - Enable SYS Interface signals */
-        ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR);
-        ctrl_outw((ctrl_inw(PORT_PHCR) & ~0xcfff) | 0x0010, PORT_PHCR);
-        ctrl_outw(0x0000, PORT_PLCR);
-        ctrl_outw(0x0000, PORT_PMCR);
-        ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x030f, PORT_PRCR);
-        ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x0001) | 0x0420, PORT_PSELD);
-        ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x0100, PORT_MSELCRB);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA);
-#endif
-
-        /* CEU */
-        ctrl_outw((ctrl_inw(PORT_PTCR) & ~0x03c3) | 0x0051, PORT_PTCR);
-        ctrl_outw(ctrl_inw(PORT_PUCR) & ~0x03ff, PORT_PUCR);
-        ctrl_outw(ctrl_inw(PORT_PVCR) & ~0x03ff, PORT_PVCR);
-        ctrl_outw(ctrl_inw(PORT_PWCR) & ~0x3c00, PORT_PWCR);
-        ctrl_outw(ctrl_inw(PORT_PSELC) | 0x0001, PORT_PSELC);
-        ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x2000, PORT_PSELD);
-        ctrl_outw(ctrl_inw(PORT_PSELE) | 0x000f, PORT_PSELE);
-        ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2200, PORT_MSELCRB);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x0a00, PORT_HIZCRA);
-        ctrl_outw(ctrl_inw(PORT_HIZCRB) & ~0x0003, PORT_HIZCRB);
 }
 
 static struct sh_machine_vector mv_migor __initmv = {
diff --git a/arch/sh/boards/mach-r2d/irq.c b/arch/sh/boards/mach-r2d/irq.c
index 8e49f6e51247..c70fecedcac4 100644
--- a/arch/sh/boards/mach-r2d/irq.c
+++ b/arch/sh/boards/mach-r2d/irq.c
@@ -13,7 +13,7 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <asm/rts7751r2d.h>
+#include <mach/r2d.h>
 
 #define R2D_NR_IRL 13
 
diff --git a/arch/sh/boards/mach-r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index 2308e8753bcd..c585be00956e 100644
--- a/arch/sh/boards/mach-r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
@@ -18,7 +18,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 #include <asm/machvec.h>
-#include <asm/rts7751r2d.h>
+#include <mach/r2d.h>
 #include <asm/io.h>
 #include <asm/io_trapped.h>
 #include <asm/spi.h>
diff --git a/arch/sh/boards/mach-sdk7780/irq.c b/arch/sh/boards/mach-sdk7780/irq.c
index 87cdc578f6ff..855558163c58 100644
--- a/arch/sh/boards/mach-sdk7780/irq.c
+++ b/arch/sh/boards/mach-sdk7780/irq.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/sdk7780.h>
+#include <mach/sdk7780.h>
 
 enum {
         UNUSED = 0,
diff --git a/arch/sh/boards/mach-sdk7780/setup.c b/arch/sh/boards/mach-sdk7780/setup.c
index acc5932587f1..aad94a78dc70 100644
--- a/arch/sh/boards/mach-sdk7780/setup.c
+++ b/arch/sh/boards/mach-sdk7780/setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <asm/machvec.h>
-#include <asm/sdk7780.h>
+#include <mach/sdk7780.h>
 #include <asm/heartbeat.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
diff --git a/arch/sh/boards/mach-sh7763rdp/irq.c b/arch/sh/boards/mach-sh7763rdp/irq.c
index fd850bad2dec..d8ebfa7d8c76 100644
--- a/arch/sh/boards/mach-sh7763rdp/irq.c
+++ b/arch/sh/boards/mach-sh7763rdp/irq.c
@@ -15,7 +15,7 @@
 #include <linux/irq.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/sh7763rdp.h>
+#include <mach/sh7763rdp.h>
 
 #define INTC_BASE               (0xFFD00000)
 #define INTC_INT2PRI7   (INTC_BASE+0x4001C)
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
index 23850da05e3c..6f926fd2162b 100644
--- a/arch/sh/boards/mach-sh7763rdp/setup.c
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -17,7 +17,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/fb.h>
 #include <linux/io.h>
-#include <asm/sh7763rdp.h>
+#include <mach/sh7763rdp.h>
 #include <asm/sh_eth.h>
 #include <asm/sh7760fb.h>
 
diff --git a/arch/sh/boards/mach-snapgear/setup.c b/arch/sh/boards/mach-snapgear/setup.c
index a5e349d3dda2..a3277a23cf14 100644
--- a/arch/sh/boards/mach-snapgear/setup.c
+++ b/arch/sh/boards/mach-snapgear/setup.c
@@ -19,7 +19,7 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <asm/machvec.h>
-#include <asm/snapgear.h>
+#include <mach/snapgear.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <cpu/timer.h>
diff --git a/arch/sh/boards/mach-systemh/io.c b/arch/sh/boards/mach-systemh/io.c
index 1b767e1a1428..dec3db0ee933 100644
--- a/arch/sh/boards/mach-systemh/io.c
+++ b/arch/sh/boards/mach-systemh/io.c
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/pci.h>
-#include <asm/systemh7751.h>
+#include <mach/systemh7751.h>
 #include <asm/addrspace.h>
 #include <asm/io.h>
 
diff --git a/arch/sh/boards/mach-systemh/irq.c b/arch/sh/boards/mach-systemh/irq.c
index 601c9c8cdbec..538406872a89 100644
--- a/arch/sh/boards/mach-systemh/irq.c
+++ b/arch/sh/boards/mach-systemh/irq.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 
 #include <asm/io.h>
-#include <asm/systemh7751.h>
+#include <mach/systemh7751.h>
 #include <asm/smc37c93x.h>
 
 /* address of external interrupt mask register
diff --git a/arch/sh/boards/mach-systemh/setup.c b/arch/sh/boards/mach-systemh/setup.c
index ee78af842778..219fd800a43f 100644
--- a/arch/sh/boards/mach-systemh/setup.c
+++ b/arch/sh/boards/mach-systemh/setup.c
@@ -16,7 +16,7 @@
  */
 #include <linux/init.h>
 #include <asm/machvec.h>
-#include <asm/systemh7751.h>
+#include <mach/systemh7751.h>
 
 extern void make_systemh_irq(unsigned int irq);
 
diff --git a/arch/sh/boards/mach-titan/io.c b/arch/sh/boards/mach-titan/io.c
index 4730c1dd697d..4badad4c6f30 100644
--- a/arch/sh/boards/mach-titan/io.c
+++ b/arch/sh/boards/mach-titan/io.c
@@ -4,7 +4,7 @@
 #include <linux/pci.h>
 #include <asm/machvec.h>
 #include <asm/addrspace.h>
-#include <asm/titan.h>
+#include <mach/titan.h>
 #include <asm/io.h>
 
 static inline unsigned int port2adr(unsigned int port)
diff --git a/arch/sh/boards/mach-titan/setup.c b/arch/sh/boards/mach-titan/setup.c
index 5de3b2ad71af..81e7e0f03863 100644
--- a/arch/sh/boards/mach-titan/setup.c
+++ b/arch/sh/boards/mach-titan/setup.c
@@ -9,7 +9,7 @@
  */
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <asm/titan.h>
+#include <mach/titan.h>
 #include <asm/io.h>
 
 static void __init init_titan_irq(void)
diff --git a/arch/sh/boot/.gitignore b/arch/sh/boot/.gitignore
index b6718de23693..aad5edddf93b 100644
--- a/arch/sh/boot/.gitignore
+++ b/arch/sh/boot/.gitignore
@@ -1 +1,4 @@
 zImage
+vmlinux.srec
+uImage
+uImage.srec
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 5b54965eef98..c16ccd4bfa16 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -33,10 +33,16 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
 $(obj)/compressed/vmlinux: FORCE
         $(Q)$(MAKE) $(build)=$(obj)/compressed $@
 
+ifeq ($(CONFIG_32BIT),y)
+KERNEL_LOAD     := $(shell /bin/bash -c 'printf "0x%08x" \
+                     $$[$(CONFIG_PAGE_OFFSET)  + \
+                        $(CONFIG_ZERO_PAGE_OFFSET)]')
+else
 KERNEL_LOAD     := $(shell /bin/bash -c 'printf "0x%08x" \
                      $$[$(CONFIG_PAGE_OFFSET)  + \
                         $(CONFIG_MEMORY_START) + \
                         $(CONFIG_ZERO_PAGE_OFFSET)]')
+endif
 
 KERNEL_ENTRY    := $(shell /bin/bash -c 'printf "0x%08x" \
                      $$[$(CONFIG_PAGE_OFFSET)  + \
diff --git a/arch/sh/boot/compressed/Makefile_32 b/arch/sh/boot/compressed/Makefile_32
index 47685f618ae7..301e6d503256 100644
--- a/arch/sh/boot/compressed/Makefile_32
+++ b/arch/sh/boot/compressed/Makefile_32
@@ -23,6 +23,11 @@ IMAGE_OFFSET	:= $(shell /bin/bash -c 'printf "0x%08x" \
 
 LIBGCC  := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
 
+ifeq ($(CONFIG_FTRACE),y)
+ORIG_CFLAGS := $(KBUILD_CFLAGS)
+KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
+endif
+
 LDFLAGS_vmlinux := -Ttext $(IMAGE_OFFSET) -e startup -T $(obj)/../../kernel/vmlinux.lds
 
 $(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE
diff --git a/arch/sh/boot/compressed/misc_32.c b/arch/sh/boot/compressed/misc_32.c
index f386997e4d9c..efdba6b29572 100644
--- a/arch/sh/boot/compressed/misc_32.c
+++ b/arch/sh/boot/compressed/misc_32.c
@@ -191,7 +191,7 @@ long* stack_start = &user_stack[STACK_SIZE];
 
 void decompress_kernel(void)
 {
-        output_data = 0;
+        output_data = NULL;
         output_ptr = PHYSADDR((unsigned long)&_text+PAGE_SIZE);
 #ifdef CONFIG_29BIT
         output_ptr |= P2SEG;
diff --git a/arch/sh/configs/edosk7760_defconfig b/arch/sh/configs/edosk7760_defconfig
new file mode 100644
index 000000000000..bef07fa8d858
--- /dev/null
+++ b/arch/sh/configs/edosk7760_defconfig
@@ -0,0 +1,1050 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26
+# Tue Aug 26 11:36:09 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="_edosk7760"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+CONFIG_CPU_SUBTYPE_SH7760=y
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+CONFIG_SH_STORE_QUEUES=y
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+CONFIG_SH_EDOSK7760=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=33333333
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+CONFIG_SH_DMA_API=y
+CONFIG_SH_DMA=y
+CONFIG_NR_ONCHIP_DMA_CHANNELS=4
+# CONFIG_NR_DMA_CHANNELS_BOOL is not set
+# CONFIG_SH_DMABRG is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+# CONFIG_HEARTBEAT is not set
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x02000000
+# CONFIG_UBC_WAKEUP is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="mem=64M console=ttySC2,115200 root=/dev/nfs rw nfsroot=192.168.0.3:/scripts/filesys ip=192.168.0.4"
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+CONFIG_DEBUG_DRIVER=y
+CONFIG_DEBUG_DEVRES=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_MAP_BANK_WIDTH_8=y
+CONFIG_MTD_MAP_BANK_WIDTH_16=y
+CONFIG_MTD_MAP_BANK_WIDTH_32=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_I4=y
+CONFIG_MTD_CFI_I8=y
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xffffffff
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=26000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_STNIC is not set
+# CONFIG_SMC9194 is not set
+CONFIG_SMC91X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=3
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_SH7760=y
+# CONFIG_I2C_SH_MOBILE is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+CONFIG_I2C_DEBUG_CORE=y
+CONFIG_I2C_DEBUG_ALGO=y
+CONFIG_I2C_DEBUG_BUS=y
+CONFIG_I2C_DEBUG_CHIP=y
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=m
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_MB86290_640X480_16BPP is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_VERBOSE_PRINTK=y
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# SUPERH devices
+#
+
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=y
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# SoC Audio for the Texas Instruments OMAP
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+CONFIG_EARLY_SCIF_CONSOLE=y
+CONFIG_EARLY_SCIF_CONSOLE_PORT=0xffe80000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_DEBUG_BOOTMEM is not set
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/rts7751r2dplus_qemu_defconfig b/arch/sh/configs/rts7751r2dplus_qemu_defconfig
new file mode 100644
index 000000000000..a72796c0293c
--- /dev/null
+++ b/arch/sh/configs/rts7751r2dplus_qemu_defconfig
@@ -0,0 +1,909 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-rc2
+# Mon Aug 18 22:17:44 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_SYS_SUPPORTS_PCI=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_IO_TRAPPED=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+CONFIG_CPU_SUBTYPE_SH7751R=y
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+# CONFIG_SH_STORE_QUEUES is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+# CONFIG_SH_7751_SYSTEMH is not set
+# CONFIG_SH_SECUREEDGE5410 is not set
+CONFIG_SH_RTS7751R2D=y
+# CONFIG_SH_LANDISK is not set
+# CONFIG_SH_TITAN is not set
+# CONFIG_SH_LBOX_RE2 is not set
+
+#
+# RTS7751R2D Board Revision
+#
+CONFIG_RTS7751R2D_PLUS=y
+# CONFIG_RTS7751R2D_1 is not set
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=60000000
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_SECCOMP=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00010000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+# CONFIG_UBC_WAKEUP is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=serial"
+
+#
+# Bus options
+#
+# CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=1
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_SH_SCI is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_SH_MOBILE_LCDC=m
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+CONFIG_LOGO_SUPERH_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=m
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPERH=y
+# CONFIG_SND_SOC is not set
+CONFIG_SOUND_PRIME=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+CONFIG_RTC_DRV_R9701=y
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SH is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=y
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+CONFIG_EARLY_SCIF_CONSOLE=y
+CONFIG_EARLY_SCIF_CONSOLE_PORT=0xffe80000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_DEBUG_BOOTMEM is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c
index a13cb764b0b9..86c0b6fb7375 100644
--- a/arch/sh/drivers/pci/ops-lboxre2.c
+++ b/arch/sh/drivers/pci/ops-lboxre2.c
@@ -10,7 +10,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/io.h>
-#include <asm/lboxre2.h>
+#include <mach/lboxre2.h>
 #include "pci-sh4.h"
 
 static char lboxre2_irq_tab[] __initdata = {
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
index 5fdadaeed6fc..8555238e63eb 100644
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ b/arch/sh/drivers/pci/ops-r7780rp.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
-#include <asm/r7780rp.h>
+#include <mach/highlander.h>
 #include <asm/io.h>
 #include "pci-sh4.h"
 
diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c
index b3fa3e2ef184..d6ca74b25d5f 100644
--- a/arch/sh/drivers/pci/ops-rts7751r2d.c
+++ b/arch/sh/drivers/pci/ops-rts7751r2d.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/io.h>
-#include <asm/rts7751r2d.h>
+#include <mach/r2d.h>
 #include "pci-sh4.h"
 
 static u8 rts7751r2d_irq_tab[] __initdata = {
diff --git a/arch/sh/drivers/pci/ops-sdk7780.c b/arch/sh/drivers/pci/ops-sdk7780.c
index 66a9b4047f26..4dcc64184b23 100644
--- a/arch/sh/drivers/pci/ops-sdk7780.c
+++ b/arch/sh/drivers/pci/ops-sdk7780.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
-#include <asm/sdk7780.h>
+#include <mach/sdk7780.h>
 #include <asm/io.h>
 #include "pci-sh4.h"
 
diff --git a/arch/sh/drivers/pci/ops-titan.c b/arch/sh/drivers/pci/ops-titan.c
index ac8ee2312cd8..a8f7801a34af 100644
--- a/arch/sh/drivers/pci/ops-titan.c
+++ b/arch/sh/drivers/pci/ops-titan.c
@@ -16,7 +16,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/io.h>
-#include <asm/titan.h>
+#include <mach/titan.h>
 #include "pci-sh4.h"
 
 static char titan_irq_tab[] __initdata = {
diff --git a/arch/sh/include/asm/bitops-llsc.h b/arch/sh/include/asm/bitops-llsc.h
new file mode 100644
index 000000000000..43b8e1a8239e
--- /dev/null
+++ b/arch/sh/include/asm/bitops-llsc.h
@@ -0,0 +1,144 @@
+#ifndef __ASM_SH_BITOPS_LLSC_H
+#define __ASM_SH_BITOPS_LLSC_H
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! set_bit               \n\t"
+                "or             %3, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp), "=r" (a)
+                : "1" (a), "r" (mask)
+                : "t", "memory"
+        );
+}
+
+static inline void clear_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! clear_bit             \n\t"
+                "and            %3, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp), "=r" (a)
+                : "1" (a), "r" (~mask)
+                : "t", "memory"
+        );
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! change_bit            \n\t"
+                "xor            %3, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp), "=r" (a)
+                : "1" (a), "r" (mask)
+                : "t", "memory"
+        );
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! test_and_set_bit      \n\t"
+                "mov            %0, %2                          \n\t"
+                "or             %4, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                "and            %4, %2                          \n\t"
+                : "=&z" (tmp), "=r" (a), "=&r" (retval)
+                : "1" (a), "r" (mask)
+                : "t", "memory"
+        );
+
+        return retval != 0;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! test_and_clear_bit    \n\t"
+                "mov            %0, %2                          \n\t"
+                "and            %5, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                "and            %4, %2                          \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=r" (a), "=&r" (retval)
+                : "1" (a), "r" (mask), "r" (~mask)
+                : "t", "memory"
+        );
+
+        return retval != 0;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! test_and_change_bit   \n\t"
+                "mov            %0, %2                          \n\t"
+                "xor            %4, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                "and            %4, %2                          \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=r" (a), "=&r" (retval)
+                : "1" (a), "r" (mask)
+                : "t", "memory"
+        );
+
+        return retval != 0;
+}
+
+#endif /* __ASM_SH_BITOPS_LLSC_H */
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
index d7d382f63ee5..367930d8e5ae 100644
--- a/arch/sh/include/asm/bitops.h
+++ b/arch/sh/include/asm/bitops.h
@@ -13,6 +13,8 @@
 
 #ifdef CONFIG_GUSA_RB
 #include <asm/bitops-grb.h>
+#elif defined(CONFIG_CPU_SH4A)
+#include <asm/bitops-llsc.h>
 #else
 #include <asm/bitops-irq.h>
 #endif
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 720dfab7b15e..f9c88583d90a 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -39,6 +39,7 @@ struct clk {
 
 /* Should be defined by processor-specific code */
 void arch_init_clk_ops(struct clk_ops **, int type);
+int __init arch_clk_init(void);
 
 /* arch/sh/kernel/cpu/clock.c */
 int clk_init(void);
diff --git a/arch/sh/include/asm/cmpxchg-llsc.h b/arch/sh/include/asm/cmpxchg-llsc.h
new file mode 100644
index 000000000000..aee3bf286581
--- /dev/null
+++ b/arch/sh/include/asm/cmpxchg-llsc.h
@@ -0,0 +1,71 @@
+#ifndef __ASM_SH_CMPXCHG_LLSC_H
+#define __ASM_SH_CMPXCHG_LLSC_H
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+        unsigned long retval;
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                     \n\t"
+                "movli.l        @%1, %0 ! xchg_u32      \n\t"
+                "mov            %0, %2                  \n\t"
+                "mov            %4, %0                  \n\t"
+                "movco.l        %0, @%1                 \n\t"
+                "bf             1b                      \n\t"
+                "synco                                  \n\t"
+                : "=&z"(tmp), "=r" (m), "=&r" (retval)
+                : "1" (m), "r" (val)
+                : "t", "memory"
+        );
+
+        return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+        unsigned long retval;
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                     \n\t"
+                "movli.l        @%1, %0 ! xchg_u8       \n\t"
+                "mov            %0, %2                  \n\t"
+                "mov            %4, %0                  \n\t"
+                "movco.l        %0, @%1                 \n\t"
+                "bf             1b                      \n\t"
+                "synco                                  \n\t"
+                : "=&z"(tmp), "=r" (m), "=&r" (retval)
+                : "1" (m), "r" (val & 0xff)
+                : "t", "memory"
+        );
+
+        return retval;
+}
+
+static inline unsigned long
+__cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
+{
+        unsigned long retval;
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __cmpxchg_u32         \n\t"
+                "mov            %0, %2                          \n\t"
+                "cmp/eq         %2, %4                          \n\t"
+                "bf             2f                              \n\t"
+                "mov            %5, %0                          \n\t"
+                "2:                                             \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=r" (m), "=&r" (retval)
+                : "1" (m), "r" (old), "r" (new)
+                : "t", "memory"
+        );
+
+        return retval;
+}
+
+#endif /* __ASM_SH_CMPXCHG_LLSC_H */
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
index ee02db110f0d..9eb9036a1bdc 100644
--- a/arch/sh/include/asm/elf.h
+++ b/arch/sh/include/asm/elf.h
@@ -108,6 +108,14 @@ typedef struct user_fpu_struct elf_fpregset_t;
 #define elf_check_fdpic(x)              ((x)->e_flags & EF_SH_FDPIC)
 #define elf_check_const_displacement(x) ((x)->e_flags & EF_SH_PIC)
 
+#ifdef CONFIG_SUPERH32
+/*
+ * Enable dump using regset.
+ * This covers all of general/DSP/FPU regs.
+ */
+#define CORE_DUMP_USE_REGSET
+#endif
+
 #define USE_ELF_CORE_DUMP
 #define ELF_FDPIC_CORE_EFLAGS   EF_SH_FDPIC
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
@@ -190,12 +198,6 @@ do {									\
 #endif
 
 #define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
-struct task_struct;
-extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
-extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
-
-#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
-#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
 
 #ifdef CONFIG_VSYSCALL
 /* vDSO has arch_setup_additional_pages */
diff --git a/arch/sh/include/asm/fpu.h b/arch/sh/include/asm/fpu.h
index 91462fea1507..1d3aee04b5cc 100644
--- a/arch/sh/include/asm/fpu.h
+++ b/arch/sh/include/asm/fpu.h
@@ -30,8 +30,15 @@ static inline void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
 }
 #endif
 
+struct user_regset;
+
 extern int do_fpu_inst(unsigned short, struct pt_regs *);
 
+extern int fpregs_get(struct task_struct *target,
+                      const struct user_regset *regset,
+                      unsigned int pos, unsigned int count,
+                      void *kbuf, void __user *ubuf);
+
 static inline void unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs)
 {
         preempt_disable();
@@ -50,6 +57,18 @@ static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs)
         preempt_enable();
 }
 
+static inline int init_fpu(struct task_struct *tsk)
+{
+        if (tsk_used_math(tsk)) {
+                if ((boot_cpu_data.flags & CPU_HAS_FPU) && tsk == current)
+                        unlazy_fpu(tsk, task_pt_regs(tsk));
+                return 0;
+        }
+
+        set_stopped_child_used_math(tsk);
+        return 0;
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_SH_FPU_H */
diff --git a/arch/sh/include/asm/ftrace.h b/arch/sh/include/asm/ftrace.h
new file mode 100644
index 000000000000..3aed362c9463
--- /dev/null
+++ b/arch/sh/include/asm/ftrace.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_FTRACE_H
+#define __ASM_SH_FTRACE_H
+
+#ifndef __ASSEMBLY__
+extern void mcount(void);
+#endif
+
+#endif /* __ASM_SH_FTRACE_H */
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
index cf32bd2df881..9650e7c9c39e 100644
--- a/arch/sh/include/asm/gpio.h
+++ b/arch/sh/include/asm/gpio.h
@@ -1,9 +1,9 @@
 /*
  *  include/asm-sh/gpio.h
  *
- *  Copyright (C) 2007 Markus Brunner, Mark Jonas
+ * Generic GPIO API and pinmux table support for SuperH.
  *
- *  Addresses for the Pin Function Controller
+ * Copyright (c) 2008 Magnus Damm
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -16,4 +16,92 @@
 #include <cpu/gpio.h>
 #endif
 
+typedef unsigned short pinmux_enum_t;
+typedef unsigned char pinmux_flag_t;
+
+#define PINMUX_TYPE_NONE            0
+#define PINMUX_TYPE_FUNCTION        1
+#define PINMUX_TYPE_GPIO            2
+#define PINMUX_TYPE_OUTPUT          3
+#define PINMUX_TYPE_INPUT           4
+#define PINMUX_TYPE_INPUT_PULLUP    5
+#define PINMUX_TYPE_INPUT_PULLDOWN  6
+
+#define PINMUX_FLAG_TYPE            (0x7)
+#define PINMUX_FLAG_WANT_PULLUP     (1 << 3)
+#define PINMUX_FLAG_WANT_PULLDOWN   (1 << 4)
+
+struct pinmux_gpio {
+        pinmux_enum_t enum_id;
+        pinmux_flag_t flags;
+};
+
+#define PINMUX_GPIO(gpio, data_or_mark) [gpio] = { data_or_mark }
+#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
+
+struct pinmux_cfg_reg {
+        unsigned long reg, reg_width, field_width;
+        unsigned long *cnt;
+        pinmux_enum_t *enum_ids;
+};
+
+#define PINMUX_CFG_REG(name, r, r_width, f_width) \
+        .reg = r, .reg_width = r_width, .field_width = f_width,         \
+        .cnt = (unsigned long [r_width / f_width]) {}, \
+        .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \
+
+struct pinmux_data_reg {
+        unsigned long reg, reg_width;
+        pinmux_enum_t *enum_ids;
+};
+
+#define PINMUX_DATA_REG(name, r, r_width) \
+        .reg = r, .reg_width = r_width, \
+        .enum_ids = (pinmux_enum_t [r_width]) \
+
+struct pinmux_range {
+        pinmux_enum_t begin;
+        pinmux_enum_t end;
+};
+
+struct pinmux_info {
+        char *name;
+        pinmux_enum_t reserved_id;
+        struct pinmux_range data;
+        struct pinmux_range input;
+        struct pinmux_range input_pd;
+        struct pinmux_range input_pu;
+        struct pinmux_range output;
+        struct pinmux_range mark;
+        struct pinmux_range function;
+
+        unsigned first_gpio, last_gpio;
+
+        struct pinmux_gpio *gpios;
+        struct pinmux_cfg_reg *cfg_regs;
+        struct pinmux_data_reg *data_regs;
+
+        pinmux_enum_t *gpio_data;
+        unsigned int gpio_data_size;
+
+        unsigned long *gpio_in_use;
+};
+
+int register_pinmux(struct pinmux_info *pip);
+
+int __gpio_request(unsigned gpio);
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return __gpio_request(gpio);
+}
+void gpio_free(unsigned gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+static inline int gpio_export(unsigned gpio, bool direction_may_change)
+{
+        return 0;
+}
+
 #endif /* __ASM_SH_GPIO_H */
diff --git a/arch/sh/include/asm/hw_irq.h b/arch/sh/include/asm/hw_irq.h
index d557b00111bf..603cdde813d1 100644
--- a/arch/sh/include/asm/hw_irq.h
+++ b/arch/sh/include/asm/hw_irq.h
@@ -2,6 +2,7 @@
 #define __ASM_SH_HW_IRQ_H
 
 #include <linux/init.h>
+#include <linux/sh_intc.h>
 #include <asm/atomic.h>
 
 extern atomic_t irq_err_count;
@@ -23,101 +24,12 @@ struct ipr_desc {
 
 void register_ipr_controller(struct ipr_desc *);
 
-typedef unsigned char intc_enum;
-
-struct intc_vect {
-        intc_enum enum_id;
-        unsigned short vect;
-};
-
-#define INTC_VECT(enum_id, vect) { enum_id, vect }
-#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
-
-struct intc_group {
-        intc_enum enum_id;
-        intc_enum enum_ids[32];
-};
-
-#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
-
-struct intc_mask_reg {
-        unsigned long set_reg, clr_reg, reg_width;
-        intc_enum enum_ids[32];
-#ifdef CONFIG_SMP
-        unsigned long smp;
-#endif
-};
-
-struct intc_prio_reg {
-        unsigned long set_reg, clr_reg, reg_width, field_width;
-        intc_enum enum_ids[16];
-#ifdef CONFIG_SMP
-        unsigned long smp;
-#endif
-};
-
-struct intc_sense_reg {
-        unsigned long reg, reg_width, field_width;
-        intc_enum enum_ids[16];
-};
-
-#ifdef CONFIG_SMP
-#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
-#else
-#define INTC_SMP(stride, nr)
-#endif
-
-struct intc_desc {
-        struct intc_vect *vectors;
-        unsigned int nr_vectors;
-        struct intc_group *groups;
-        unsigned int nr_groups;
-        struct intc_mask_reg *mask_regs;
-        unsigned int nr_mask_regs;
-        struct intc_prio_reg *prio_regs;
-        unsigned int nr_prio_regs;
-        struct intc_sense_reg *sense_regs;
-        unsigned int nr_sense_regs;
-        char *name;
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        struct intc_mask_reg *ack_regs;
-        unsigned int nr_ack_regs;
-#endif
-};
-
-#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
-#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,            \
-        mask_regs, prio_regs, sense_regs)                               \
-struct intc_desc symbol __initdata = {                                  \
-        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
-        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
-        _INTC_ARRAY(sense_regs),                                        \
-        chipname,                                                       \
-}
-
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,        \
-        mask_regs, prio_regs, sense_regs, ack_regs)                     \
-struct intc_desc symbol __initdata = {                                  \
-        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
-        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
-        _INTC_ARRAY(sense_regs),                                        \
-        chipname,                                                       \
-        _INTC_ARRAY(ack_regs),                                          \
-}
-#endif
-
-void __init register_intc_controller(struct intc_desc *desc);
-int intc_set_priority(unsigned int irq, unsigned int prio);
-
 void __init plat_irq_setup(void);
-#ifdef CONFIG_CPU_SH3
 void __init plat_irq_setup_sh3(void);
-#endif
+void __init plat_irq_setup_pins(int mode);
 
 enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
        IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
        IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
-void __init plat_irq_setup_pins(int mode);
 
 #endif /* __ASM_SH_HW_IRQ_H */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index a4fbf0c84fb1..436c28539577 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -1,27 +1,26 @@
 #ifndef __ASM_SH_IO_H
 #define __ASM_SH_IO_H
-
 /*
  * Convention:
- *    read{b,w,l}/write{b,w,l} are for PCI,
+ *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
  *    while in{b,w,l}/out{b,w,l} are for ISA
- * These may (will) be platform specific function.
+ *
  * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
  * and 'string' versions: ins{b,w,l}/outs{b,w,l}
- * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
- * do not have a memory barrier after them.
  *
- * In addition, we have
- *   ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
- *   which are processor specific.
- */
-
-/*
- * We follow the Alpha convention here:
- *  __inb expands to an inline function call (which calls via the mv)
- *  _inb  is a real function call (note ___raw fns are _ version of __raw)
- *  inb   by default expands to _inb, but the machine specific code may
- *        define it to __inb if it chooses.
+ * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
+ * automatically, there are also __raw versions, which do not.
+ *
+ * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
+ * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
+ * these have the same semantics as the __raw variants, and as such, all
+ * new code should be using the __raw versions.
+ *
+ * All ISA I/O routines are wrapped through the machine vector. If a
+ * board does not provide overrides, a generic set that are copied in
+ * from the default machine vector are used instead. These are largely
+ * for old compat code for I/O offseting to SuperIOs, all of which are
+ * better handled through the machvec ioport mapping routines these days.
  */
 #include <asm/cache.h>
 #include <asm/system.h>
@@ -31,7 +30,6 @@
 #include <asm-generic/iomap.h>
 
 #ifdef __KERNEL__
-
 /*
  * Depending on which platform we are running on, we need different
  * I/O functions.
@@ -40,105 +38,68 @@
 #include <asm/io_generic.h>
 #include <asm/io_trapped.h>
 
-#define maybebadio(port) \
-  printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
-         __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
-
-/*
- * Since boards are able to define their own set of I/O routines through
- * their respective machine vector, we always wrap through the mv.
- *
- * Also, in the event that a board hasn't provided its own definition for
- * a given routine, it will be wrapped to generic code at run-time.
- */
+#define inb(p)                  sh_mv.mv_inb((p))
+#define inw(p)                  sh_mv.mv_inw((p))
+#define inl(p)                  sh_mv.mv_inl((p))
+#define outb(x,p)               sh_mv.mv_outb((x),(p))
+#define outw(x,p)               sh_mv.mv_outw((x),(p))
+#define outl(x,p)               sh_mv.mv_outl((x),(p))
+
+#define inb_p(p)                sh_mv.mv_inb_p((p))
+#define inw_p(p)                sh_mv.mv_inw_p((p))
+#define inl_p(p)                sh_mv.mv_inl_p((p))
+#define outb_p(x,p)             sh_mv.mv_outb_p((x),(p))
+#define outw_p(x,p)             sh_mv.mv_outw_p((x),(p))
+#define outl_p(x,p)             sh_mv.mv_outl_p((x),(p))
+
+#define insb(p,b,c)             sh_mv.mv_insb((p), (b), (c))
+#define insw(p,b,c)             sh_mv.mv_insw((p), (b), (c))
+#define insl(p,b,c)             sh_mv.mv_insl((p), (b), (c))
+#define outsb(p,b,c)            sh_mv.mv_outsb((p), (b), (c))
+#define outsw(p,b,c)            sh_mv.mv_outsw((p), (b), (c))
+#define outsl(p,b,c)            sh_mv.mv_outsl((p), (b), (c))
+
+#define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
+#define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
+#define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
+#define __raw_writeq(v,a)       (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
+
+#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile u8  __force *)(a))
+#define __raw_readw(a)          (__chk_io_ptr(a), *(volatile u16 __force *)(a))
+#define __raw_readl(a)          (__chk_io_ptr(a), *(volatile u32 __force *)(a))
+#define __raw_readq(a)          (__chk_io_ptr(a), *(volatile u64 __force *)(a))
+
+#define readb(a)                ({ u8  r_ = __raw_readb(a); mb(); r_; })
+#define readw(a)                ({ u16 r_ = __raw_readw(a); mb(); r_; })
+#define readl(a)                ({ u32 r_ = __raw_readl(a); mb(); r_; })
+#define readq(a)                ({ u64 r_ = __raw_readq(a); mb(); r_; })
+
+#define writeb(v,a)             ({ __raw_writeb((v),(a)); mb(); })
+#define writew(v,a)             ({ __raw_writew((v),(a)); mb(); })
+#define writel(v,a)             ({ __raw_writel((v),(a)); mb(); })
+#define writeq(v,a)             ({ __raw_writeq((v),(a)); mb(); })
 
-#define __inb(p)        sh_mv.mv_inb((p))
-#define __inw(p)        sh_mv.mv_inw((p))
-#define __inl(p)        sh_mv.mv_inl((p))
-#define __outb(x,p)     sh_mv.mv_outb((x),(p))
-#define __outw(x,p)     sh_mv.mv_outw((x),(p))
-#define __outl(x,p)     sh_mv.mv_outl((x),(p))
-
-#define __inb_p(p)      sh_mv.mv_inb_p((p))
-#define __inw_p(p)      sh_mv.mv_inw_p((p))
-#define __inl_p(p)      sh_mv.mv_inl_p((p))
-#define __outb_p(x,p)   sh_mv.mv_outb_p((x),(p))
-#define __outw_p(x,p)   sh_mv.mv_outw_p((x),(p))
-#define __outl_p(x,p)   sh_mv.mv_outl_p((x),(p))
-
-#define __insb(p,b,c)   sh_mv.mv_insb((p), (b), (c))
-#define __insw(p,b,c)   sh_mv.mv_insw((p), (b), (c))
-#define __insl(p,b,c)   sh_mv.mv_insl((p), (b), (c))
-#define __outsb(p,b,c)  sh_mv.mv_outsb((p), (b), (c))
-#define __outsw(p,b,c)  sh_mv.mv_outsw((p), (b), (c))
-#define __outsl(p,b,c)  sh_mv.mv_outsl((p), (b), (c))
-
-#define __readb(a)      sh_mv.mv_readb((a))
-#define __readw(a)      sh_mv.mv_readw((a))
-#define __readl(a)      sh_mv.mv_readl((a))
-#define __writeb(v,a)   sh_mv.mv_writeb((v),(a))
-#define __writew(v,a)   sh_mv.mv_writew((v),(a))
-#define __writel(v,a)   sh_mv.mv_writel((v),(a))
-
-#define inb             __inb
-#define inw             __inw
-#define inl             __inl
-#define outb            __outb
-#define outw            __outw
-#define outl            __outl
-
-#define inb_p           __inb_p
-#define inw_p           __inw_p
-#define inl_p           __inl_p
-#define outb_p          __outb_p
-#define outw_p          __outw_p
-#define outl_p          __outl_p
-
-#define insb            __insb
-#define insw            __insw
-#define insl            __insl
-#define outsb           __outsb
-#define outsw           __outsw
-#define outsl           __outsl
-
-#define __raw_readb(a)          __readb((void __iomem *)(a))
-#define __raw_readw(a)          __readw((void __iomem *)(a))
-#define __raw_readl(a)          __readl((void __iomem *)(a))
-#define __raw_writeb(v, a)      __writeb(v, (void __iomem *)(a))
-#define __raw_writew(v, a)      __writew(v, (void __iomem *)(a))
-#define __raw_writel(v, a)      __writel(v, (void __iomem *)(a))
-
-void __raw_writesl(unsigned long addr, const void *data, int longlen);
-void __raw_readsl(unsigned long addr, void *data, int longlen);
+/* SuperH on-chip I/O functions */
+#define ctrl_inb                __raw_readb
+#define ctrl_inw                __raw_readw
+#define ctrl_inl                __raw_readl
+#define ctrl_inq                __raw_readq
 
-/*
- * The platform header files may define some of these macros to use
- * the inlined versions where appropriate.  These macros may also be
- * redefined by userlevel programs.
- */
-#ifdef __readb
-# define readb(a)       ({ unsigned int r_ = __raw_readb(a); mb(); r_; })
-#endif
-#ifdef __raw_readw
-# define readw(a)       ({ unsigned int r_ = __raw_readw(a); mb(); r_; })
-#endif
-#ifdef __raw_readl
-# define readl(a)       ({ unsigned int r_ = __raw_readl(a); mb(); r_; })
-#endif
+#define ctrl_outb               __raw_writeb
+#define ctrl_outw               __raw_writew
+#define ctrl_outl               __raw_writel
+#define ctrl_outq               __raw_writeq
 
-#ifdef __raw_writeb
-# define writeb(v,a)    ({ __raw_writeb((v),(a)); mb(); })
-#endif
-#ifdef __raw_writew
-# define writew(v,a)    ({ __raw_writew((v),(a)); mb(); })
-#endif
-#ifdef __raw_writel
-# define writel(v,a)    ({ __raw_writel((v),(a)); mb(); })
+static inline void ctrl_delay(void)
+{
+#ifdef P2SEG
+        __raw_readw(P2SEG);
 #endif
+}
 
 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
                                                                         \
-static inline void writes##bwlq(volatile void __iomem *mem,             \
+static inline void __raw_writes##bwlq(volatile void __iomem *mem,       \
                                 const void *addr, unsigned int count)   \
 {                                                                       \
         const volatile type *__addr = addr;                             \
@@ -149,8 +110,8 @@ static inline void writes##bwlq(volatile void __iomem *mem,		\
         }                                                               \
 }                                                                       \
                                                                         \
-static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
-                               unsigned int count)                      \
+static inline void __raw_reads##bwlq(volatile void __iomem *mem,        \
+                               void *addr, unsigned int count)          \
 {                                                                       \
         volatile type *__addr = addr;                                   \
                                                                         \
@@ -162,106 +123,71 @@ static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
 
 __BUILD_MEMORY_STRING(b, u8)
 __BUILD_MEMORY_STRING(w, u16)
-#define writesl __raw_writesl
-#define readsl  __raw_readsl
+__BUILD_MEMORY_STRING(q, u64)
+
+void __raw_writesl(void __iomem *addr, const void *data, int longlen);
+void __raw_readsl(const void __iomem *addr, void *data, int longlen);
+
+#define writesb                 __raw_writesb
+#define writesw                 __raw_writesw
+#define writesl                 __raw_writesl
+
+#define readsb                  __raw_readsb
+#define readsw                  __raw_readsw
+#define readsl                  __raw_readsl
 
-#define readb_relaxed(a) readb(a)
-#define readw_relaxed(a) readw(a)
-#define readl_relaxed(a) readl(a)
+#define readb_relaxed(a)        readb(a)
+#define readw_relaxed(a)        readw(a)
+#define readl_relaxed(a)        readl(a)
+#define readq_relaxed(a)        readq(a)
 
 /* Simple MMIO */
-#define ioread8(a)              readb(a)
-#define ioread16(a)             readw(a)
+#define ioread8(a)              __raw_readb(a)
+#define ioread16(a)             __raw_readw(a)
 #define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
-#define ioread32(a)             readl(a)
+#define ioread32(a)             __raw_readl(a)
 #define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
 
-#define iowrite8(v,a)           writeb((v),(a))
-#define iowrite16(v,a)          writew((v),(a))
+#define iowrite8(v,a)           __raw_writeb((v),(a))
+#define iowrite16(v,a)          __raw_writew((v),(a))
 #define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
-#define iowrite32(v,a)          writel((v),(a))
+#define iowrite32(v,a)          __raw_writel((v),(a))
 #define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
 
-#define ioread8_rep(a, d, c)    readsb((a), (d), (c))
-#define ioread16_rep(a, d, c)   readsw((a), (d), (c))
-#define ioread32_rep(a, d, c)   readsl((a), (d), (c))
+#define ioread8_rep(a, d, c)    __raw_readsb((a), (d), (c))
+#define ioread16_rep(a, d, c)   __raw_readsw((a), (d), (c))
+#define ioread32_rep(a, d, c)   __raw_readsl((a), (d), (c))
 
-#define iowrite8_rep(a, s, c)   writesb((a), (s), (c))
-#define iowrite16_rep(a, s, c)  writesw((a), (s), (c))
-#define iowrite32_rep(a, s, c)  writesl((a), (s), (c))
+#define iowrite8_rep(a, s, c)   __raw_writesb((a), (s), (c))
+#define iowrite16_rep(a, s, c)  __raw_writesw((a), (s), (c))
+#define iowrite32_rep(a, s, c)  __raw_writesl((a), (s), (c))
 
-#define mmiowb()        wmb()   /* synco on SH-4A, otherwise a nop */
+/* synco on SH-4A, otherwise a nop */
+#define mmiowb()                wmb()
 
 #define IO_SPACE_LIMIT 0xffffffff
 
+extern unsigned long generic_io_base;
+
 /*
- * This function provides a method for the generic case where a board-specific
- * ioport_map simply needs to return the port + some arbitrary port base.
+ * This function provides a method for the generic case where a
+ * board-specific ioport_map simply needs to return the port + some
+ * arbitrary port base.
  *
  * We use this at board setup time to implicitly set the port base, and
  * as a result, we can use the generic ioport_map.
  */
 static inline void __set_io_port_base(unsigned long pbase)
 {
-        extern unsigned long generic_io_base;
-
         generic_io_base = pbase;
 }
 
 #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
 
 /* We really want to try and get these to memcpy etc */
-extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
-extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
-extern void memset_io(volatile void __iomem *, int, unsigned long);
-
-/* SuperH on-chip I/O functions */
-static inline unsigned char ctrl_inb(unsigned long addr)
-{
-        return *(volatile unsigned char*)addr;
-}
-
-static inline unsigned short ctrl_inw(unsigned long addr)
-{
-        return *(volatile unsigned short*)addr;
-}
-
-static inline unsigned int ctrl_inl(unsigned long addr)
-{
-        return *(volatile unsigned long*)addr;
-}
-
-static inline unsigned long long ctrl_inq(unsigned long addr)
-{
-        return *(volatile unsigned long long*)addr;
-}
-
-static inline void ctrl_outb(unsigned char b, unsigned long addr)
-{
-        *(volatile unsigned char*)addr = b;
-}
-
-static inline void ctrl_outw(unsigned short b, unsigned long addr)
-{
-        *(volatile unsigned short*)addr = b;
-}
-
-static inline void ctrl_outl(unsigned int b, unsigned long addr)
-{
-        *(volatile unsigned long*)addr = b;
-}
-
-static inline void ctrl_outq(unsigned long long b, unsigned long addr)
-{
-        *(volatile unsigned long long*)addr = b;
-}
-
-static inline void ctrl_delay(void)
-{
-#ifdef P2SEG
-        ctrl_inw(P2SEG);
-#endif
-}
+void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
+void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
+void memset_io(volatile void __iomem *, int, unsigned long);
 
 /* Quad-word real-mode I/O, don't ask.. */
 unsigned long long peek_real_address_q(unsigned long long addr);
@@ -347,9 +273,15 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
         __ioremap_mode((offset), (size), _PAGE_CACHABLE)
 #define p3_ioremap(offset, size, flags)                 \
         __ioremap((offset), (size), (flags))
+#define ioremap_prot(offset, size, flags)               \
+        __ioremap_mode((offset), (size), (flags))
 #define iounmap(addr)                                   \
         __iounmap((addr))
 
+#define maybebadio(port) \
+        printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
+               __func__, __LINE__, (port), (u32)__builtin_return_address(0))
+
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access
diff --git a/arch/sh/include/asm/io_generic.h b/arch/sh/include/asm/io_generic.h
index 92fc6070d7b3..1e5d375f55dc 100644
--- a/arch/sh/include/asm/io_generic.h
+++ b/arch/sh/include/asm/io_generic.h
@@ -33,13 +33,6 @@ void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long
 void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
 void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
 
-u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
-u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
-u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
-void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
-void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
-void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
-
 void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
 void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
 
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 6195a531c1b0..d319baaf4fbd 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -41,6 +41,9 @@ static inline int generic_irq_demux(int irq)
 #define irq_canonicalize(irq)   (irq)
 #define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
 
+void init_IRQ(void);
+asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs);
+
 #ifdef CONFIG_IRQSTACKS
 extern void irq_ctx_init(int cpu);
 extern void irq_ctx_exit(int cpu);
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
new file mode 100644
index 000000000000..6078d8e551d4
--- /dev/null
+++ b/arch/sh/include/asm/kprobes.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_KPROBES_H
+#define __ASM_SH_KPROBES_H
+
+#ifdef CONFIG_KPROBES
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+typedef u16 kprobe_opcode_t;
+#define BREAKPOINT_INSTRUCTION  0xc33a
+
+#define MAX_INSN_SIZE 16
+#define MAX_STACK_SIZE 64
+#define MIN_STACK_SIZE(ADDR) (((MAX_STACK_SIZE) < \
+        (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) \
+        ? (MAX_STACK_SIZE) \
+        : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
+
+#define regs_return_value(regs)         ((regs)->regs[0])
+#define flush_insn_slot(p)              do { } while (0)
+#define kretprobe_blacklist_size        0
+
+struct kprobe;
+
+void arch_remove_kprobe(struct kprobe *);
+void kretprobe_trampoline(void);
+void jprobe_return_end(void);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the original instruction */
+        kprobe_opcode_t insn[MAX_INSN_SIZE];
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long jprobe_saved_r15;
+        struct pt_regs jprobe_saved_regs;
+        kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE];
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+extern int kprobe_handle_illslot(unsigned long pc);
+#else
+
+#define kprobe_handle_illslot(pc)       (-1)
+
+#endif /* CONFIG_KPROBES */
+#endif /* __ASM_SH_KPROBES_H */
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index b2e4124070ae..f1bae02ef7b6 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -42,13 +42,6 @@ struct sh_machine_vector {
         void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
         void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
 
-        u8 (*mv_readb)(void __iomem *);
-        u16 (*mv_readw)(void __iomem *);
-        u32 (*mv_readl)(void __iomem *);
-        void (*mv_writeb)(u8, void __iomem *);
-        void (*mv_writew)(u16, void __iomem *);
-        void (*mv_writel)(u32, void __iomem *);
-
         int (*mv_irq_demux)(int irq);
 
         void (*mv_init_irq)(void);
diff --git a/arch/sh/include/asm/mmzone.h b/arch/sh/include/asm/mmzone.h
index 2969253c4042..7f5363b29ba0 100644
--- a/arch/sh/include/asm/mmzone.h
+++ b/arch/sh/include/asm/mmzone.h
@@ -4,6 +4,8 @@
 #ifdef __KERNEL__
 
 #ifdef CONFIG_NEED_MULTIPLE_NODES
+#include <linux/numa.h>
+
 extern struct pglist_data *node_data[];
 #define NODE_DATA(nid)          (node_data[nid])
 
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index 77fb8bf02e4e..5871d78e47e5 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -104,6 +104,8 @@ typedef struct { unsigned long pgd; } pgd_t;
 
 typedef struct page *pgtable_t;
 
+#define pte_pgprot(x) __pgprot(pte_val(x) & PTE_FLAGS_MASK)
+
 #endif /* !__ASSEMBLY__ */
 
 /*
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index a4a8f8b93463..52220d70a096 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -76,6 +76,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 #endif
 
 #define PTE_PHYS_MASK           (PHYS_ADDR_MASK & PAGE_MASK)
+#define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
 
 #ifdef CONFIG_SUPERH32
 #define VMALLOC_START   (P3SEG)
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 15d9f92ca383..693364a20ad7 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -3,6 +3,7 @@
 
 #include <asm/cpu-features.h>
 #include <asm/segment.h>
+#include <asm/cache.h>
 
 #ifndef __ASSEMBLY__
 /*
@@ -43,11 +44,52 @@ enum cpu_type {
         CPU_SH_NONE
 };
 
+/*
+ * TLB information structure
+ *
+ * Defined for both I and D tlb, per-processor.
+ */
+struct tlb_info {
+        unsigned long long next;
+        unsigned long long first;
+        unsigned long long last;
+
+        unsigned int entries;
+        unsigned int step;
+
+        unsigned long flags;
+};
+
+struct sh_cpuinfo {
+        unsigned int type;
+        int cut_major, cut_minor;
+        unsigned long loops_per_jiffy;
+        unsigned long asid_cache;
+
+        struct cache_info icache;       /* Primary I-cache */
+        struct cache_info dcache;       /* Primary D-cache */
+        struct cache_info scache;       /* Secondary cache */
+
+        /* TLB info */
+        struct tlb_info itlb;
+        struct tlb_info dtlb;
+
+        unsigned long flags;
+} __attribute__ ((aligned(L1_CACHE_BYTES)));
+
+extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+
 /* Forward decl */
-struct sh_cpuinfo;
+struct seq_operations;
+
+extern struct pt_regs fake_swapper_regs;
 
 /* arch/sh/kernel/setup.c */
 const char *get_cpu_subtype(struct sh_cpuinfo *c);
+extern const struct seq_operations cpuinfo_op;
 
 #ifdef CONFIG_VSYSCALL
 int vsyscall_init(void);
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index 0dadd75bd93c..a46a0207e977 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -10,9 +10,9 @@
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
+#include <linux/linkage.h>
 #include <asm/page.h>
 #include <asm/types.h>
-#include <asm/cache.h>
 #include <asm/ptrace.h>
 
 /*
@@ -26,23 +26,7 @@
 #define CCN_CVR         0xff000040
 #define CCN_PRR         0xff000044
 
-struct sh_cpuinfo {
-        unsigned int type;
-        int cut_major, cut_minor;
-        unsigned long loops_per_jiffy;
-        unsigned long asid_cache;
-
-        struct cache_info icache;       /* Primary I-cache */
-        struct cache_info dcache;       /* Primary D-cache */
-        struct cache_info scache;       /* Secondary cache */
-
-        unsigned long flags;
-} __attribute__ ((aligned(L1_CACHE_BYTES)));
-
-extern struct sh_cpuinfo cpu_data[];
-#define boot_cpu_data cpu_data[0]
-#define current_cpu_data cpu_data[smp_processor_id()]
-#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+asmlinkage void __init sh_cpu_init(void);
 
 /*
  * User space process size: 2GB.
@@ -196,6 +180,8 @@ extern unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)  (task_pt_regs(tsk)->pc)
 #define KSTK_ESP(tsk)  (task_pt_regs(tsk)->regs[15])
 
+#define user_stack_pointer(regs)        ((regs)->regs[15])
+
 #define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
 #define cpu_relax()     barrier()
 
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index 770d5169983b..b0b4824dfc4c 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -17,7 +17,6 @@
 #include <linux/compiler.h>
 #include <asm/page.h>
 #include <asm/types.h>
-#include <asm/cache.h>
 #include <asm/ptrace.h>
 #include <cpu/registers.h>
 
@@ -36,46 +35,6 @@ __asm__("gettr	tr0, %1\n\t" \
         : "1" (__dummy)); \
 pc; })
 
-/*
- * TLB information structure
- *
- * Defined for both I and D tlb, per-processor.
- */
-struct tlb_info {
-        unsigned long long next;
-        unsigned long long first;
-        unsigned long long last;
-
-        unsigned int entries;
-        unsigned int step;
-
-        unsigned long flags;
-};
-
-struct sh_cpuinfo {
-        enum cpu_type type;
-        unsigned long loops_per_jiffy;
-        unsigned long asid_cache;
-
-        unsigned int cpu_clock, master_clock, bus_clock, module_clock;
-
-        /* Cache info */
-        struct cache_info icache;
-        struct cache_info dcache;
-        struct cache_info scache;
-
-        /* TLB info */
-        struct tlb_info itlb;
-        struct tlb_info dtlb;
-
-        unsigned long flags;
-};
-
-extern struct sh_cpuinfo cpu_data[];
-#define boot_cpu_data cpu_data[0]
-#define current_cpu_data cpu_data[smp_processor_id()]
-#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
-
 #endif
 
 /*
@@ -169,8 +128,6 @@ struct thread_struct {
 #define INIT_MMAP \
 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
 
-extern  struct pt_regs fake_swapper_regs;
-
 #define INIT_THREAD  {                          \
         .sp             = sizeof(init_stack) +  \
                           (long) &init_stack,   \
@@ -269,6 +226,8 @@ extern unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)  ((tsk)->thread.pc)
 #define KSTK_ESP(tsk)  ((tsk)->thread.sp)
 
+#define user_stack_pointer(regs)        ((regs)->sp)
+
 #define cpu_relax()     barrier()
 
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index b86aeabba61a..3ad18e91bca6 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -87,12 +87,18 @@ struct pt_dspregs {
         unsigned long   mod;
 };
 
+#define PTRACE_GETREGS          12      /* General registers */
+#define PTRACE_SETREGS          13
+
+#define PTRACE_GETFPREGS        14      /* FPU registers */
+#define PTRACE_SETFPREGS        15
+
 #define PTRACE_GETFDPIC         31      /* get the ELF fdpic loadmap address */
 
 #define PTRACE_GETFDPIC_EXEC    0       /* [addr] request the executable loadmap */
 #define PTRACE_GETFDPIC_INTERP  1       /* [addr] request the interpreter loadmap */
 
-#define PTRACE_GETDSPREGS       55
+#define PTRACE_GETDSPREGS       55      /* DSP registers */
 #define PTRACE_SETDSPREGS       56
 #endif
 
@@ -117,6 +123,9 @@ extern void user_disable_single_step(struct task_struct *);
 #define task_pt_regs(task) \
         ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
                  - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#define task_pt_dspregs(task) \
+        ((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE \
+                 - sizeof(unsigned long)) - 1)
 #else
 #define task_pt_regs(task) \
         ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
index 1813f4202a24..f7b010d48af7 100644
--- a/arch/sh/include/asm/rtc.h
+++ b/arch/sh/include/asm/rtc.h
@@ -1,6 +1,7 @@
 #ifndef _ASM_RTC_H
 #define _ASM_RTC_H
 
+void time_init(void);
 extern void (*board_time_init)(void);
 extern void (*rtc_sh_get_time)(struct timespec *);
 extern int (*rtc_sh_set_time)(const time_t);
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
index 55a2bd328d99..d450bcf59ee2 100644
--- a/arch/sh/include/asm/setup.h
+++ b/arch/sh/include/asm/setup.h
@@ -4,7 +4,6 @@
 #define COMMAND_LINE_SIZE 256
 
 #ifdef __KERNEL__
-
 /*
  * This is set up by the setup-routine at boot-time
  */
diff --git a/arch/sh/include/asm/sh_mobile_lcdc.h b/arch/sh/include/asm/sh_mobile_lcdc.h
deleted file mode 100644
index 130102f663f5..000000000000
--- a/arch/sh/include/asm/sh_mobile_lcdc.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef __ASM_SH_MOBILE_LCDC_H__
-#define __ASM_SH_MOBILE_LCDC_H__
-
-#include <linux/fb.h>
-
-enum { RGB8,   /* 24bpp, 8:8:8 */
-       RGB9,   /* 18bpp, 9:9 */
-       RGB12A, /* 24bpp, 12:12 */
-       RGB12B, /* 12bpp */
-       RGB16,  /* 16bpp */
-       RGB18,  /* 18bpp */
-       RGB24,  /* 24bpp */
-       SYS8A,  /* 24bpp, 8:8:8 */
-       SYS8B,  /* 18bpp, 8:8:2 */
-       SYS8C,  /* 18bpp, 2:8:8 */
-       SYS8D,  /* 16bpp, 8:8 */
-       SYS9,   /* 18bpp, 9:9 */
-       SYS12,  /* 24bpp, 12:12 */
-       SYS16A, /* 16bpp */
-       SYS16B, /* 18bpp, 16:2 */
-       SYS16C, /* 18bpp, 2:16 */
-       SYS18,  /* 18bpp */
-       SYS24 };/* 24bpp */
-
-enum { LCDC_CHAN_DISABLED = 0,
-       LCDC_CHAN_MAINLCD,
-       LCDC_CHAN_SUBLCD };
-
-enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
-
-struct sh_mobile_lcdc_sys_bus_cfg {
-        unsigned long ldmt2r;
-        unsigned long ldmt3r;
-};
-
-struct sh_mobile_lcdc_sys_bus_ops {
-        void (*write_index)(void *handle, unsigned long data);
-        void (*write_data)(void *handle, unsigned long data);
-        unsigned long (*read_data)(void *handle);
-};
-
-struct sh_mobile_lcdc_board_cfg {
-        void *board_data;
-        int (*setup_sys)(void *board_data, void *sys_ops_handle,
-                         struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
-        void (*display_on)(void *board_data);
-        void (*display_off)(void *board_data);
-};
-
-struct sh_mobile_lcdc_lcd_size_cfg { /* width and height of panel in mm */
-        unsigned long width;
-        unsigned long height;
-};
-
-struct sh_mobile_lcdc_chan_cfg {
-        int chan;
-        int bpp;
-        int interface_type; /* selects RGBn or SYSn I/F, see above */
-        int clock_divider;
-        struct fb_videomode lcd_cfg;
-        struct sh_mobile_lcdc_lcd_size_cfg lcd_size_cfg;
-        struct sh_mobile_lcdc_board_cfg board_cfg;
-        struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
-};
-
-struct sh_mobile_lcdc_info {
-        unsigned long lddckr;
-        int clock_source;
-        struct sh_mobile_lcdc_chan_cfg ch[2];
-};
-
-#endif /* __ASM_SH_MOBILE_LCDC_H__ */
diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h
new file mode 100644
index 000000000000..3a1fb97770f1
--- /dev/null
+++ b/arch/sh/include/asm/sizes.h
@@ -0,0 +1,61 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *                 from .s file by awk -f s2h.awk
+ */
+/*  Size definitions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h                       1
+
+/* handy sizes */
+#define SZ_16                           0x00000010
+#define SZ_32                           0x00000020
+#define SZ_64                           0x00000040
+#define SZ_128                          0x00000080
+#define SZ_256                          0x00000100
+#define SZ_512                          0x00000200
+
+#define SZ_1K                           0x00000400
+#define SZ_4K                           0x00001000
+#define SZ_8K                           0x00002000
+#define SZ_16K                          0x00004000
+#define SZ_32K                          0x00008000
+#define SZ_64K                          0x00010000
+#define SZ_128K                         0x00020000
+#define SZ_256K                         0x00040000
+#define SZ_512K                         0x00080000
+
+#define SZ_1M                           0x00100000
+#define SZ_2M                           0x00200000
+#define SZ_4M                           0x00400000
+#define SZ_8M                           0x00800000
+#define SZ_16M                          0x01000000
+#define SZ_26M                          0x01a00000
+#define SZ_32M                          0x02000000
+#define SZ_64M                          0x04000000
+#define SZ_128M                         0x08000000
+#define SZ_256M                         0x10000000
+#define SZ_512M                         0x20000000
+
+#define SZ_1G                           0x40000000
+#define SZ_2G                           0x80000000
+
+#endif
+
+/*         END */
diff --git a/arch/sh/include/asm/smp.h b/arch/sh/include/asm/smp.h
index 593343cd26ee..85b660c17eb0 100644
--- a/arch/sh/include/asm/smp.h
+++ b/arch/sh/include/asm/smp.h
@@ -21,25 +21,29 @@ extern int __cpu_number_map[NR_CPUS];
 extern int __cpu_logical_map[NR_CPUS];
 #define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
 
-/* I've no idea what the real meaning of this is */
-#define PROC_CHANGE_PENALTY     20
+enum {
+        SMP_MSG_FUNCTION,
+        SMP_MSG_RESCHEDULE,
+        SMP_MSG_FUNCTION_SINGLE,
+        SMP_MSG_TIMER,
 
-#define NO_PROC_ID      (-1)
+        SMP_MSG_NR,     /* must be last */
+};
 
-#define SMP_MSG_FUNCTION        0
-#define SMP_MSG_RESCHEDULE      1
-#define SMP_MSG_FUNCTION_SINGLE 2
-#define SMP_MSG_NR              3
+void smp_message_recv(unsigned int msg);
+void smp_timer_broadcast(cpumask_t mask);
+
+void local_timer_interrupt(void);
+void local_timer_setup(unsigned int cpu);
 
 void plat_smp_setup(void);
 void plat_prepare_cpus(unsigned int max_cpus);
 int plat_smp_processor_id(void);
 void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
 void plat_send_ipi(unsigned int cpu, unsigned int message);
-int plat_register_ipi_handler(unsigned int message,
-                              void (*handler)(void *), void *arg);
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi(cpumask_t mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+void arch_send_call_function_ipi(cpumask_t mask);
 
 #else
 
diff --git a/arch/sh/include/asm/syscall.h b/arch/sh/include/asm/syscall.h
new file mode 100644
index 000000000000..6a381429ee9d
--- /dev/null
+++ b/arch/sh/include/asm/syscall.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_SH_SYSCALL_H
+#define __ASM_SH_SYSCALL_H
+
+#ifdef CONFIG_SUPERH32
+# include "syscall_32.h"
+#else
+# include "syscall_64.h"
+#endif
+
+#endif /* __ASM_SH_SYSCALL_H */
diff --git a/arch/sh/include/asm/syscall_32.h b/arch/sh/include/asm/syscall_32.h
new file mode 100644
index 000000000000..54773f26cd44
--- /dev/null
+++ b/arch/sh/include/asm/syscall_32.h
@@ -0,0 +1,110 @@
+#ifndef __ASM_SH_SYSCALL_32_H
+#define __ASM_SH_SYSCALL_32_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+
+/* The system call number is given by the user in %g1 */
+static inline long syscall_get_nr(struct task_struct *task,
+                                  struct pt_regs *regs)
+{
+        return (regs->tra >= 0) ? regs->regs[3] : -1L;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        /*
+         * XXX: This needs some thought. On SH we don't
+         * save away the original r0 value anywhere.
+         */
+}
+
+static inline bool syscall_has_error(struct pt_regs *regs)
+{
+        return (regs->sr & 0x1) ? true : false;
+}
+static inline void syscall_set_error(struct pt_regs *regs)
+{
+        regs->sr |= 0x1;
+}
+static inline void syscall_clear_error(struct pt_regs *regs)
+{
+        regs->sr &= ~0x1;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        return syscall_has_error(regs) ? regs->regs[0] : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->regs[0];
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        if (error) {
+                syscall_set_error(regs);
+                regs->regs[0] = -error;
+        } else {
+                syscall_clear_error(regs);
+                regs->regs[0] = val;
+        }
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        /*
+         * Do this simply for now. If we need to start supporting
+         * fetching arguments from arbitrary indices, this will need some
+         * extra logic. Presently there are no in-tree users that depend
+         * on this behaviour.
+         */
+        BUG_ON(i);
+
+        /* Argument pattern is: R4, R5, R6, R7, R0, R1 */
+        switch (n) {
+        case 6: args[5] = regs->regs[1];
+        case 5: args[4] = regs->regs[0];
+        case 4: args[3] = regs->regs[7];
+        case 3: args[2] = regs->regs[6];
+        case 2: args[1] = regs->regs[5];
+        case 1: args[0] = regs->regs[4];
+                break;
+        default:
+                BUG();
+        }
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        /* Same note as above applies */
+        BUG_ON(i);
+
+        switch (n) {
+        case 6: regs->regs[1] = args[5];
+        case 5: regs->regs[0] = args[4];
+        case 4: regs->regs[7] = args[3];
+        case 3: regs->regs[6] = args[2];
+        case 2: regs->regs[5] = args[1];
+        case 1: regs->regs[4] = args[0];
+                break;
+        default:
+                BUG();
+        }
+}
+
+#endif /* __ASM_SH_SYSCALL_32_H */
diff --git a/arch/sh/include/asm/syscall_64.h b/arch/sh/include/asm/syscall_64.h
new file mode 100644
index 000000000000..bcaaa8ca4d70
--- /dev/null
+++ b/arch/sh/include/asm/syscall_64.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_SYSCALL_64_H
+#define __ASM_SH_SYSCALL_64_H
+
+#include <asm-generic/syscall.h>
+
+#endif /* __ASM_SH_SYSCALL_64_H */
diff --git a/arch/sh/include/asm/syscalls.h b/arch/sh/include/asm/syscalls.h
new file mode 100644
index 000000000000..c1e2b8deb837
--- /dev/null
+++ b/arch/sh/include/asm/syscalls.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_SH_SYSCALLS_H
+#define __ASM_SH_SYSCALLS_H
+
+#ifdef __KERNEL__
+
+struct old_utsname;
+
+asmlinkage int old_mmap(unsigned long addr, unsigned long len,
+                        unsigned long prot, unsigned long flags,
+                        int fd, unsigned long off);
+asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
+                          unsigned long prot, unsigned long flags,
+                          unsigned long fd, unsigned long pgoff);
+asmlinkage int sys_ipc(uint call, int first, int second,
+                       int third, void __user *ptr, long fifth);
+asmlinkage int sys_uname(struct old_utsname __user *name);
+
+#ifdef CONFIG_SUPERH32
+# include "syscalls_32.h"
+#else
+# include "syscalls_64.h"
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_SYSCALLS_H */
diff --git a/arch/sh/include/asm/syscalls_32.h b/arch/sh/include/asm/syscalls_32.h
new file mode 100644
index 000000000000..104c5e686106
--- /dev/null
+++ b/arch/sh/include/asm/syscalls_32.h
@@ -0,0 +1,56 @@
+#ifndef __ASM_SH_SYSCALLS_32_H
+#define __ASM_SH_SYSCALLS_32_H
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+
+struct pt_regs;
+
+asmlinkage int sys_fork(unsigned long r4, unsigned long r5,
+                        unsigned long r6, unsigned long r7,
+                        struct pt_regs __regs);
+asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
+                         unsigned long parent_tidptr,
+                         unsigned long child_tidptr,
+                         struct pt_regs __regs);
+asmlinkage int sys_vfork(unsigned long r4, unsigned long r5,
+                         unsigned long r6, unsigned long r7,
+                         struct pt_regs __regs);
+asmlinkage int sys_execve(char __user *ufilename, char __user * __user *uargv,
+                          char __user * __user *uenvp, unsigned long r7,
+                          struct pt_regs __regs);
+asmlinkage int sys_sigsuspend(old_sigset_t mask, unsigned long r5,
+                              unsigned long r6, unsigned long r7,
+                              struct pt_regs __regs);
+asmlinkage int sys_sigaction(int sig, const struct old_sigaction __user *act,
+                             struct old_sigaction __user *oact);
+asmlinkage int sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
+                               unsigned long r6, unsigned long r7,
+                               struct pt_regs __regs);
+asmlinkage int sys_sigreturn(unsigned long r4, unsigned long r5,
+                             unsigned long r6, unsigned long r7,
+                             struct pt_regs __regs);
+asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
+                                unsigned long r6, unsigned long r7,
+                                struct pt_regs __regs);
+asmlinkage int sys_pipe(unsigned long r4, unsigned long r5,
+                        unsigned long r6, unsigned long r7,
+                        struct pt_regs __regs);
+asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf,
+                                     size_t count, long dummy, loff_t pos);
+asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf,
+                                      size_t count, long dummy, loff_t pos);
+asmlinkage int sys_fadvise64_64_wrapper(int fd, u32 offset0, u32 offset1,
+                                        u32 len0, u32 len1, int advice);
+
+/* Misc syscall related bits */
+asmlinkage long do_syscall_trace_enter(struct pt_regs *regs);
+asmlinkage void do_syscall_trace_leave(struct pt_regs *regs);
+asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned int save_r0,
+                                 unsigned long thread_info_flags);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_SYSCALLS_32_H */
diff --git a/arch/sh/include/asm/syscalls_64.h b/arch/sh/include/asm/syscalls_64.h
new file mode 100644
index 000000000000..751fd8811364
--- /dev/null
+++ b/arch/sh/include/asm/syscalls_64.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_SH_SYSCALLS_64_H
+#define __ASM_SH_SYSCALLS_64_H
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+
+struct pt_regs;
+
+asmlinkage int sys_fork(unsigned long r2, unsigned long r3,
+                        unsigned long r4, unsigned long r5,
+                        unsigned long r6, unsigned long r7,
+                        struct pt_regs *pregs);
+asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
+                         unsigned long r4, unsigned long r5,
+                         unsigned long r6, unsigned long r7,
+                         struct pt_regs *pregs);
+asmlinkage int sys_vfork(unsigned long r2, unsigned long r3,
+                         unsigned long r4, unsigned long r5,
+                         unsigned long r6, unsigned long r7,
+                         struct pt_regs *pregs);
+asmlinkage int sys_execve(char *ufilename, char **uargv,
+                          char **uenvp, unsigned long r5,
+                          unsigned long r6, unsigned long r7,
+                          struct pt_regs *pregs);
+
+/* Misc syscall related bits */
+asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs);
+asmlinkage void do_syscall_trace_leave(struct pt_regs *regs);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_SYSCALLS_64_H */
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index 056d68cd2108..6160fe445161 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -70,6 +70,8 @@
 
 #ifdef CONFIG_GUSA_RB
 #include <asm/cmpxchg-grb.h>
+#elif defined(CONFIG_CPU_SH4A)
+#include <asm/cmpxchg-llsc.h>
 #else
 #include <asm/cmpxchg-irq.h>
 #endif
@@ -125,6 +127,8 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
   })
 
 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+void free_initmem(void);
+void free_initrd_mem(unsigned long start, unsigned long end);
 
 extern void *set_exception_table_vec(unsigned int vec, void *handler);
 
@@ -177,8 +181,8 @@ BUILD_TRAP_HANDLER(fpu_state_restore);
 #define arch_align_stack(x) (x)
 
 struct mem_access {
-        unsigned long (*from)(void *dst, const void *src, unsigned long cnt);
-        unsigned long (*to)(void *dst, const void *src, unsigned long cnt);
+        unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt);
+        unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt);
 };
 
 #ifdef CONFIG_SUPERH32
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index f11bcf0855ed..a726d5d07277 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -58,7 +58,8 @@ do {									\
         last = __last;                                                  \
 } while (0)
 
-#define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text")))
+#define __uses_jump_to_uncached \
+        noinline __attribute__ ((__section__ (".uncached.text")))
 
 /*
  * Jump to uncached area.
@@ -96,7 +97,48 @@ do {							\
                 : "=&r" (__dummy));                     \
 } while (0)
 
+#ifdef CONFIG_CPU_HAS_SR_RB
+#define lookup_exception_vector()       \
+({                                      \
+        unsigned long _vec;             \
+                                        \
+        __asm__ __volatile__ (          \
+                "stc r2_bank, %0\n\t"   \
+                : "=r" (_vec)           \
+        );                              \
+                                        \
+        _vec;                           \
+})
+#else
+#define lookup_exception_vector()       \
+({                                      \
+        unsigned long _vec;             \
+        __asm__ __volatile__ (          \
+                "mov r4, %0\n\t"        \
+                : "=r" (_vec)           \
+        );                              \
+                                        \
+        _vec;                           \
+})
+#endif
+
 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
                             struct mem_access *ma);
 
+asmlinkage void do_address_error(struct pt_regs *regs,
+                                 unsigned long writeaccess,
+                                 unsigned long address);
+asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
+                                unsigned long r6, unsigned long r7,
+                                struct pt_regs __regs);
+asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
+                                unsigned long r6, unsigned long r7,
+                                struct pt_regs __regs);
+asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
+                                unsigned long r6, unsigned long r7,
+                                struct pt_regs __regs);
+asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
+                                   unsigned long r6, unsigned long r7,
+                                   struct pt_regs __regs);
+
 #endif /* __ASM_SH_SYSTEM_32_H */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index 0a894cafb1dd..f09ac4806294 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -33,20 +33,12 @@ struct thread_info {
 #define PREEMPT_ACTIVE          0x10000000
 
 #if defined(CONFIG_4KSTACKS)
-#define THREAD_SIZE_ORDER       (0)
-#elif defined(CONFIG_PAGE_SIZE_4KB)
-#define THREAD_SIZE_ORDER       (1)
-#elif defined(CONFIG_PAGE_SIZE_8KB)
-#define THREAD_SIZE_ORDER       (1)
-#elif defined(CONFIG_PAGE_SIZE_16KB)
-#define THREAD_SIZE_ORDER       (0)
-#elif defined(CONFIG_PAGE_SIZE_64KB)
-#define THREAD_SIZE_ORDER       (0)
+#define THREAD_SHIFT    12
 #else
-#error "Unknown thread size"
+#define THREAD_SHIFT    13
 #endif
 
-#define THREAD_SIZE     (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_SIZE     (1 << THREAD_SHIFT)
 #define STACK_WARN      (THREAD_SIZE >> 3)
 
 /*
@@ -94,15 +86,19 @@ static inline struct thread_info *current_thread_info(void)
         return ti;
 }
 
+/* thread information allocation */
+#if THREAD_SHIFT >= PAGE_SHIFT
+
+#define THREAD_SIZE_ORDER       (THREAD_SHIFT - PAGE_SHIFT)
+
+#else /* THREAD_SHIFT < PAGE_SHIFT */
+
 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(ti)   kzalloc(THREAD_SIZE, GFP_KERNEL)
-#else
-#define alloc_thread_info(ti)   kmalloc(THREAD_SIZE, GFP_KERNEL)
-#endif
-#define free_thread_info(ti)    kfree(ti)
+extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
+extern void free_thread_info(struct thread_info *ti);
+ 
+#endif /* THREAD_SHIFT < PAGE_SHIFT */
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/sh/include/asm/uaccess_64.h b/arch/sh/include/asm/uaccess_64.h
index 5580fd471003..56fd20b8cdcc 100644
--- a/arch/sh/include/asm/uaccess_64.h
+++ b/arch/sh/include/asm/uaccess_64.h
@@ -26,16 +26,20 @@ do {								\
         retval = 0;                                             \
         switch (size) {                                         \
         case 1:                                                 \
-                retval = __get_user_asm_b(x, ptr);              \
+                retval = __get_user_asm_b((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         case 2:                                                 \
-                retval = __get_user_asm_w(x, ptr);              \
+                retval = __get_user_asm_w((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         case 4:                                                 \
-                retval = __get_user_asm_l(x, ptr);              \
+                retval = __get_user_asm_l((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         case 8:                                                 \
-                retval = __get_user_asm_q(x, ptr);              \
+                retval = __get_user_asm_q((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         default:                                                \
                 __get_user_unknown();                           \
@@ -54,16 +58,20 @@ do {								\
         retval = 0;                                             \
         switch (size) {                                         \
         case 1:                                                 \
-                retval = __put_user_asm_b(x, ptr);              \
+                retval = __put_user_asm_b((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         case 2:                                                 \
-                retval = __put_user_asm_w(x, ptr);              \
+                retval = __put_user_asm_w((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         case 4:                                                 \
-                retval = __put_user_asm_l(x, ptr);              \
+                retval = __put_user_asm_l((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         case 8:                                                 \
-                retval = __put_user_asm_q(x, ptr);              \
+                retval = __put_user_asm_q((void *)&x,           \
+                                          (long)ptr);           \
                 break;                                          \
         default:                                                \
                 __put_user_unknown();                           \
@@ -77,5 +85,7 @@ extern long __put_user_asm_q(void *, long);
 extern void __put_user_unknown(void);
 
 extern long __strnlen_user(const char *__s, long __n);
+extern int __strncpy_from_user(unsigned long __dest,
+               unsigned long __user __src, int __count);
 
 #endif /* __ASM_SH_UACCESS_64_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7203.h b/arch/sh/include/cpu-sh2a/cpu/sh7203.h
new file mode 100644
index 000000000000..79f93159018d
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/sh7203.h
@@ -0,0 +1,143 @@
+#ifndef __ASM_SH7203_H__
+#define __ASM_SH7203_H__
+
+enum {
+        /* PA */
+        GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
+        GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
+
+        /* PB */
+        GPIO_PB12,
+        GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
+        GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
+        GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
+
+        /* PC */
+        GPIO_PC14, GPIO_PC13, GPIO_PC12,
+        GPIO_PC11, GPIO_PC10, GPIO_PC9, GPIO_PC8,
+        GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
+        GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
+
+        /* PD */
+        GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
+        GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
+        GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
+        GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
+
+        /* PE */
+        GPIO_PE15, GPIO_PE14, GPIO_PE13, GPIO_PE12,
+        GPIO_PE11, GPIO_PE10, GPIO_PE9, GPIO_PE8,
+        GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
+        GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
+
+        /* PF */
+        GPIO_PF30, GPIO_PF29, GPIO_PF28,
+        GPIO_PF27, GPIO_PF26, GPIO_PF25, GPIO_PF24,
+        GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20,
+        GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16,
+        GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12,
+        GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
+        GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
+        GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
+
+        /* INTC: IRQ and PINT on PB/PD/PE */
+        GPIO_FN_PINT7_PB, GPIO_FN_PINT6_PB, GPIO_FN_PINT5_PB, GPIO_FN_PINT4_PB,
+        GPIO_FN_PINT3_PB, GPIO_FN_PINT2_PB, GPIO_FN_PINT1_PB, GPIO_FN_PINT0_PB,
+        GPIO_FN_PINT7_PD, GPIO_FN_PINT6_PD, GPIO_FN_PINT5_PD, GPIO_FN_PINT4_PD,
+        GPIO_FN_PINT3_PD, GPIO_FN_PINT2_PD, GPIO_FN_PINT1_PD, GPIO_FN_PINT0_PD,
+        GPIO_FN_IRQ7_PB, GPIO_FN_IRQ6_PB, GPIO_FN_IRQ5_PB, GPIO_FN_IRQ4_PB,
+        GPIO_FN_IRQ3_PB, GPIO_FN_IRQ2_PB, GPIO_FN_IRQ1_PB, GPIO_FN_IRQ0_PB,
+        GPIO_FN_IRQ7_PD, GPIO_FN_IRQ6_PD, GPIO_FN_IRQ5_PD, GPIO_FN_IRQ4_PD,
+        GPIO_FN_IRQ3_PD, GPIO_FN_IRQ2_PD, GPIO_FN_IRQ1_PD, GPIO_FN_IRQ0_PD,
+        GPIO_FN_IRQ7_PE, GPIO_FN_IRQ6_PE, GPIO_FN_IRQ5_PE, GPIO_FN_IRQ4_PE,
+        GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE,
+
+        GPIO_FN_WDTOVF, GPIO_FN_IRQOUT, GPIO_FN_REFOUT, GPIO_FN_IRQOUT_REFOUT,
+        GPIO_FN_UBCTRG,
+
+        /* CAN */
+        GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
+        GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1,
+
+        /* IIC3 */
+        GPIO_FN_SDA3, GPIO_FN_SCL3,
+        GPIO_FN_SDA2, GPIO_FN_SCL2,
+        GPIO_FN_SDA1, GPIO_FN_SCL1,
+        GPIO_FN_SDA0, GPIO_FN_SCL0,
+
+        /* DMAC */
+        GPIO_FN_TEND0_PD, GPIO_FN_TEND0_PE, GPIO_FN_DACK0_PD,
+        GPIO_FN_DACK0_PE, GPIO_FN_DREQ0_PD, GPIO_FN_DREQ0_PE,
+        GPIO_FN_TEND1_PD, GPIO_FN_TEND1_PE, GPIO_FN_DACK1_PD,
+        GPIO_FN_DACK1_PE, GPIO_FN_DREQ1_PD, GPIO_FN_DREQ1_PE,
+        GPIO_FN_DACK2, GPIO_FN_DREQ2,
+        GPIO_FN_DACK3, GPIO_FN_DREQ3,
+
+        /* ADC */
+        GPIO_FN_ADTRG_PD, GPIO_FN_ADTRG_PE,
+
+        /* BSC */
+        GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+        GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+        GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+        GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+        GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+        GPIO_FN_A21, GPIO_FN_CS4, GPIO_FN_MRES, GPIO_FN_BS,
+        GPIO_FN_IOIS16, GPIO_FN_CS1, GPIO_FN_CS6_CE1B,
+        GPIO_FN_CE2B, GPIO_FN_CS5_CE1A, GPIO_FN_CE2A,
+        GPIO_FN_FRAME, GPIO_FN_WAIT, GPIO_FN_RDWR,
+        GPIO_FN_CKE, GPIO_FN_CASU, GPIO_FN_BREQ, GPIO_FN_RASU,
+        GPIO_FN_BACK, GPIO_FN_CASL, GPIO_FN_RASL,
+        GPIO_FN_WE3_DQMUU_AH_ICIO_WR, GPIO_FN_WE2_DQMUL_ICIORD,
+        GPIO_FN_WE1_DQMLU_WE, GPIO_FN_WE0_DQMLL,
+        GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_A1, GPIO_FN_A0, GPIO_FN_CS7,
+
+        /* TMU */
+        GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
+        GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
+        GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
+        GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
+        GPIO_FN_TCLKD_PD, GPIO_FN_TCLKC_PD, GPIO_FN_TCLKB_PD, GPIO_FN_TCLKA_PD,
+        GPIO_FN_TCLKD_PF, GPIO_FN_TCLKC_PF, GPIO_FN_TCLKB_PF, GPIO_FN_TCLKA_PF,
+
+        /* SSU */
+        GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
+        GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
+        GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
+        GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
+
+        /* SCIF */
+        GPIO_FN_TXD0, GPIO_FN_RXD0, GPIO_FN_SCK0,
+        GPIO_FN_TXD1, GPIO_FN_RXD1, GPIO_FN_SCK1,
+        GPIO_FN_TXD2, GPIO_FN_RXD2, GPIO_FN_SCK2,
+        GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3, GPIO_FN_SCK3,
+
+        /* SSI */
+        GPIO_FN_AUDIO_CLK,
+        GPIO_FN_SSIDATA3, GPIO_FN_SSIWS3, GPIO_FN_SSISCK3,
+        GPIO_FN_SSIDATA2, GPIO_FN_SSIWS2, GPIO_FN_SSISCK2,
+        GPIO_FN_SSIDATA1, GPIO_FN_SSIWS1, GPIO_FN_SSISCK1,
+        GPIO_FN_SSIDATA0, GPIO_FN_SSIWS0, GPIO_FN_SSISCK0,
+
+        /* FLCTL */
+        GPIO_FN_FCE, GPIO_FN_FRB,
+        GPIO_FN_NAF7, GPIO_FN_NAF6, GPIO_FN_NAF5, GPIO_FN_NAF4,
+        GPIO_FN_NAF3, GPIO_FN_NAF2, GPIO_FN_NAF1, GPIO_FN_NAF0,
+        GPIO_FN_FSC, GPIO_FN_FOE, GPIO_FN_FCDE, GPIO_FN_FWE,
+
+        /* LCDC */
+        GPIO_FN_LCD_VEPWC, GPIO_FN_LCD_VCPWC,
+        GPIO_FN_LCD_CLK, GPIO_FN_LCD_FLM,
+        GPIO_FN_LCD_M_DISP, GPIO_FN_LCD_CL2,
+        GPIO_FN_LCD_CL1, GPIO_FN_LCD_DON,
+        GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
+        GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
+        GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
+        GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
+        GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
+        GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
+        GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
+        GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
+};
+
+#endif /* __ASM_SH7203_H__ */
diff --git a/arch/sh/include/cpu-sh3/cpu/sh7720.h b/arch/sh/include/cpu-sh3/cpu/sh7720.h
new file mode 100644
index 000000000000..41c1406d6da2
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/sh7720.h
@@ -0,0 +1,174 @@
+#ifndef __ASM_SH7720_H__
+#define __ASM_SH7720_H__
+
+enum {
+        /* PTA */
+        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+        /* PTB */
+        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+        /* PTC */
+        GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
+        GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+
+        /* PTD */
+        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+        /* PTE */
+        GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, GPIO_PTE3,
+        GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
+
+        /* PTF */
+        GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3,
+        GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, GPIO_PTG6,
+
+        /* PTG */
+        GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2,
+        GPIO_PTG1, GPIO_PTG0,
+
+        /* PTH */
+        GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3,
+        GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+        /* PTJ */
+        GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, GPIO_PTJ3,
+        GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
+
+        /* PTK */
+        GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+        /* PTL */
+        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3,
+
+        /* PTM */
+        GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+        /* PTP */
+        GPIO_PTP4, GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
+
+        /* PTR */
+        GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
+        GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+        /* PTS */
+        GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+        /* PTT */
+        GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+
+        /* PTU */
+        GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+
+        /* PTV */
+        GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+        /* BSC */
+        GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+        GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+        GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+        GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+        GPIO_FN_IOIS16, GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
+        GPIO_FN_CS5B_CE1A, GPIO_FN_CS6B_CE1B,
+        GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+        GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A0,
+        GPIO_FN_REFOUT, GPIO_FN_IRQOUT,
+
+        /* LCDC */
+        GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
+        GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
+        GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
+        GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
+        GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
+        GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
+        GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
+        GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
+        GPIO_FN_LCD_M_DISP,
+        GPIO_FN_LCD_CL1, GPIO_FN_LCD_CL2,
+        GPIO_FN_LCD_DON, GPIO_FN_LCD_FLM,
+        GPIO_FN_LCD_VEPWC, GPIO_FN_LCD_VCPWC,
+
+        /* AFEIF */
+        GPIO_FN_AFE_RXIN, GPIO_FN_AFE_RDET,
+        GPIO_FN_AFE_FS, GPIO_FN_AFE_TXOUT,
+        GPIO_FN_AFE_SCLK, GPIO_FN_AFE_RLYCNT,
+        GPIO_FN_AFE_HC1,
+
+        /* IIC */
+        GPIO_FN_IIC_SCL, GPIO_FN_IIC_SDA,
+
+        /* DAC */
+        GPIO_FN_DA1, GPIO_FN_DA0,
+
+        /* ADC */
+        GPIO_FN_AN3, GPIO_FN_AN2, GPIO_FN_AN1, GPIO_FN_AN0, GPIO_FN_ADTRG,
+
+        /* USB */
+        GPIO_FN_USB1D_RCV, GPIO_FN_USB1D_TXSE0,
+        GPIO_FN_USB1D_TXDPLS, GPIO_FN_USB1D_DMNS,
+        GPIO_FN_USB1D_DPLS, GPIO_FN_USB1D_SPEED,
+        GPIO_FN_USB1D_TXENL, GPIO_FN_USB2_PWR_EN,
+        GPIO_FN_USB1_PWR_EN_USBF_UPLUP, GPIO_FN_USB1D_SUSPEND,
+
+        /* INTC */
+        GPIO_FN_IRQ5, GPIO_FN_IRQ4,
+        GPIO_FN_IRQ3_IRL3, GPIO_FN_IRQ2_IRL2,
+        GPIO_FN_IRQ1_IRL1, GPIO_FN_IRQ0_IRL0,
+
+        /* PCC */
+        GPIO_FN_PCC_REG, GPIO_FN_PCC_DRV,
+        GPIO_FN_PCC_BVD2, GPIO_FN_PCC_BVD1,
+        GPIO_FN_PCC_CD2, GPIO_FN_PCC_CD1,
+        GPIO_FN_PCC_RESET, GPIO_FN_PCC_RDY,
+        GPIO_FN_PCC_VS2, GPIO_FN_PCC_VS1,
+
+        /* HUDI */
+        GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
+        GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_ASEBRKAK, GPIO_FN_TRST,
+        GPIO_FN_TMS, GPIO_FN_TDO, GPIO_FN_TDI, GPIO_FN_TCK,
+
+        /* DMAC */
+        GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DACK0, GPIO_FN_DREQ0,
+        GPIO_FN_TEND1, GPIO_FN_TEND0,
+
+        /* SIOF0 */
+        GPIO_FN_SIOF0_SYNC, GPIO_FN_SIOF0_MCLK,
+        GPIO_FN_SIOF0_TXD, GPIO_FN_SIOF0_RXD,
+        GPIO_FN_SIOF0_SCK,
+
+        /* SIOF1 */
+        GPIO_FN_SIOF1_SYNC, GPIO_FN_SIOF1_MCLK,
+        GPIO_FN_SIOF1_TXD, GPIO_FN_SIOF1_RXD,
+        GPIO_FN_SIOF1_SCK,
+
+        /* SCIF0 */
+        GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD,
+        GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_SCK,
+
+        /* SCIF1 */
+        GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF1_RXD,
+        GPIO_FN_SCIF1_RTS, GPIO_FN_SCIF1_CTS, GPIO_FN_SCIF1_SCK,
+
+        /* TPU */
+        GPIO_FN_TPU_TO1, GPIO_FN_TPU_TO0,
+        GPIO_FN_TPU_TI3B, GPIO_FN_TPU_TI3A,
+        GPIO_FN_TPU_TI2B, GPIO_FN_TPU_TI2A,
+        GPIO_FN_TPU_TO3, GPIO_FN_TPU_TO2,
+
+        /* SIM */
+        GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
+
+        /* MMC */
+        GPIO_FN_MMC_DAT, GPIO_FN_MMC_CMD,
+        GPIO_FN_MMC_CLK, GPIO_FN_MMC_VDDON,
+        GPIO_FN_MMC_ODMOD,
+
+        /* SYSC */
+        GPIO_FN_STATUS0, GPIO_FN_STATUS1,
+};
+
+#endif /* __ASM_SH7720_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
new file mode 100644
index 000000000000..4b3096f5307b
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -0,0 +1,210 @@
+#ifndef __ASM_SH7722_H__
+#define __ASM_SH7722_H__
+
+enum {
+        /* PTA */
+        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+        /* PTB */
+        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+        /* PTC */
+        GPIO_PTC7, GPIO_PTC5, GPIO_PTC4, GPIO_PTC3,
+        GPIO_PTC2, GPIO_PTC0,
+
+        /* PTD */
+        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+        /* PTE */
+        GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
+        GPIO_PTE1, GPIO_PTE0,
+
+        /* PTF */
+        GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3,
+        GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
+
+        /* PTG */
+        GPIO_PTG4, GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
+
+        /* PTH */
+        GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
+        GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+        /* PTJ */
+        GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ1, GPIO_PTJ0,
+
+        /* PTK */
+        GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, GPIO_PTK3,
+        GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+        /* PTL */
+        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
+        GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
+
+        /* PTM */
+        GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+        /* PTN */
+        GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
+        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
+
+        /* PTQ */
+        GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
+        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
+
+        /* PTR */
+        GPIO_PTR4, GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+        /* PTS */
+        GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+        /* PTT */
+        GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+
+        /* PTU */
+        GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+
+        /* PTV */
+        GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+        /* PTW */
+        GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, GPIO_PTW3,
+        GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
+
+        /* PTX */
+        GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, GPIO_PTX3,
+        GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
+
+        /* PTY */
+        GPIO_PTY5, GPIO_PTY4, GPIO_PTY3, GPIO_PTY2,
+        GPIO_PTY1, GPIO_PTY0,
+
+        /* PTZ */
+        GPIO_PTZ5, GPIO_PTZ4, GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1,
+
+        /* SCIF0 */
+        GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD,
+        GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_SCK,
+
+        /* SCIF1 */
+        GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF1_RXD,
+        GPIO_FN_SCIF1_RTS, GPIO_FN_SCIF1_CTS, GPIO_FN_SCIF1_SCK,
+
+        /* SCIF2 */
+        GPIO_FN_SCIF2_TXD, GPIO_FN_SCIF2_RXD,
+        GPIO_FN_SCIF2_RTS, GPIO_FN_SCIF2_CTS, GPIO_FN_SCIF2_SCK,
+
+        /* SIO */
+        GPIO_FN_SIOTXD, GPIO_FN_SIORXD,
+        GPIO_FN_SIOD, GPIO_FN_SIOSTRB0, GPIO_FN_SIOSTRB1,
+        GPIO_FN_SIOSCK, GPIO_FN_SIOMCK,
+
+        /* CEU */
+        GPIO_FN_VIO_D15, GPIO_FN_VIO_D14, GPIO_FN_VIO_D13, GPIO_FN_VIO_D12,
+        GPIO_FN_VIO_D11, GPIO_FN_VIO_D10, GPIO_FN_VIO_D9, GPIO_FN_VIO_D8,
+        GPIO_FN_VIO_D7, GPIO_FN_VIO_D6, GPIO_FN_VIO_D5, GPIO_FN_VIO_D4,
+        GPIO_FN_VIO_D3, GPIO_FN_VIO_D2, GPIO_FN_VIO_D1, GPIO_FN_VIO_D0,
+        GPIO_FN_VIO_FLD, GPIO_FN_VIO_CKO, GPIO_FN_VIO_STEX, GPIO_FN_VIO_STEM,
+        GPIO_FN_VIO_VD, GPIO_FN_VIO_HD, GPIO_FN_VIO_CLK,
+        GPIO_FN_VIO_VD2, GPIO_FN_VIO_HD2, GPIO_FN_VIO_CLK2,
+
+        /* LCDC */
+        GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
+        GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
+        GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
+        GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8,
+        GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4,
+        GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0,
+        GPIO_FN_LCDLCLK,
+        /* Main LCD */
+        GPIO_FN_LCDDON, GPIO_FN_LCDVCPWC, GPIO_FN_LCDVEPWC, GPIO_FN_LCDVSYN,
+        /* Main LCD - RGB Mode */
+        GPIO_FN_LCDDCK, GPIO_FN_LCDHSYN, GPIO_FN_LCDDISP,
+        /* Main LCD - SYS Mode */
+        GPIO_FN_LCDRS, GPIO_FN_LCDCS, GPIO_FN_LCDWR, GPIO_FN_LCDRD,
+        /* Sub LCD - SYS Mode */
+        GPIO_FN_LCDDON2, GPIO_FN_LCDVCPWC2, GPIO_FN_LCDVEPWC2,
+        GPIO_FN_LCDVSYN2, GPIO_FN_LCDCS2,
+
+        /* BSC */
+        GPIO_FN_IOIS16, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+        GPIO_FN_BS, GPIO_FN_CS6B_CE1B, GPIO_FN_WAIT, GPIO_FN_CS6A_CE2B,
+
+        /* SBSC */
+        GPIO_FN_HPD63, GPIO_FN_HPD62, GPIO_FN_HPD61, GPIO_FN_HPD60,
+        GPIO_FN_HPD59, GPIO_FN_HPD58, GPIO_FN_HPD57, GPIO_FN_HPD56,
+        GPIO_FN_HPD55, GPIO_FN_HPD54, GPIO_FN_HPD53, GPIO_FN_HPD52,
+        GPIO_FN_HPD51, GPIO_FN_HPD50, GPIO_FN_HPD49, GPIO_FN_HPD48,
+        GPIO_FN_HPDQM7, GPIO_FN_HPDQM6, GPIO_FN_HPDQM5, GPIO_FN_HPDQM4,
+
+        /* IRQ */
+        GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3,
+        GPIO_FN_IRQ4, GPIO_FN_IRQ5, GPIO_FN_IRQ6, GPIO_FN_IRQ7,
+
+        /* SDHI */
+        GPIO_FN_SDHICD, GPIO_FN_SDHIWP, GPIO_FN_SDHID3, GPIO_FN_SDHID2,
+        GPIO_FN_SDHID1, GPIO_FN_SDHID0, GPIO_FN_SDHICMD, GPIO_FN_SDHICLK,
+
+        /* SIU - Port A */
+        GPIO_FN_SIUAOLR, GPIO_FN_SIUAOBT, GPIO_FN_SIUAISLD, GPIO_FN_SIUAILR,
+        GPIO_FN_SIUAIBT, GPIO_FN_SIUAOSLD, GPIO_FN_SIUMCKA, GPIO_FN_SIUFCKA,
+
+        /* SIU - Port B */
+        GPIO_FN_SIUBOLR, GPIO_FN_SIUBOBT, GPIO_FN_SIUBISLD, GPIO_FN_SIUBILR,
+        GPIO_FN_SIUBIBT, GPIO_FN_SIUBOSLD, GPIO_FN_SIUMCKB, GPIO_FN_SIUFCKB,
+
+        /* AUD */
+        GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1,
+        GPIO_FN_AUDATA0,
+
+        /* DMAC */
+        GPIO_FN_DACK, GPIO_FN_DREQ0,
+
+        /* VOU */
+        GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_HSYNC, GPIO_FN_DV_VSYNC,
+        GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12,
+        GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8,
+        GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4,
+        GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0,
+
+        /* CPG */
+        GPIO_FN_STATUS0, GPIO_FN_PDSTATUS,
+
+        /* SIOF0 */
+        GPIO_FN_SIOF0_MCK, GPIO_FN_SIOF0_SCK,
+        GPIO_FN_SIOF0_SYNC, GPIO_FN_SIOF0_SS1, GPIO_FN_SIOF0_SS2,
+        GPIO_FN_SIOF0_TXD, GPIO_FN_SIOF0_RXD,
+
+        /* SIOF1 */
+        GPIO_FN_SIOF1_MCK, GPIO_FN_SIOF1_SCK,
+        GPIO_FN_SIOF1_SYNC, GPIO_FN_SIOF1_SS1, GPIO_FN_SIOF1_SS2,
+        GPIO_FN_SIOF1_TXD, GPIO_FN_SIOF1_RXD,
+
+        /* SIM */
+        GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
+
+        /* TSIF */
+        GPIO_FN_TS_SDAT, GPIO_FN_TS_SCK, GPIO_FN_TS_SDEN, GPIO_FN_TS_SPSYNC,
+
+        /* IRDA */
+        GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
+
+        /* TPU */
+        GPIO_FN_TPUTO,
+
+        /* FLCTL */
+        GPIO_FN_FCE, GPIO_FN_NAF7, GPIO_FN_NAF6, GPIO_FN_NAF5, GPIO_FN_NAF4,
+        GPIO_FN_NAF3, GPIO_FN_NAF2, GPIO_FN_NAF1, GPIO_FN_NAF0, GPIO_FN_FCDE,
+        GPIO_FN_FOE, GPIO_FN_FSC, GPIO_FN_FWE, GPIO_FN_FRB,
+
+        /* KEYSC */
+        GPIO_FN_KEYIN0, GPIO_FN_KEYIN1, GPIO_FN_KEYIN2, GPIO_FN_KEYIN3,
+        GPIO_FN_KEYIN4, GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
+        GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5,
+};
+
+#endif /* __ASM_SH7722_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
new file mode 100644
index 000000000000..9d2f6d7aa938
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -0,0 +1,254 @@
+#ifndef __ASM_SH7723_H__
+#define __ASM_SH7723_H__
+
+enum {
+        /* PTA */
+        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+        /* PTB */
+        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+        /* PTC */
+        GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
+        GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+
+        /* PTD */
+        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+        /* PTE */
+        GPIO_PTE5, GPIO_PTE4, GPIO_PTE3, GPIO_PTE2,
+        GPIO_PTE1, GPIO_PTE0,
+
+        /* PTF */
+        GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
+        GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
+
+        /* PTG */
+        GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2,
+        GPIO_PTG1, GPIO_PTG0,
+
+        /* PTH */
+        GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
+        GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+        /* PTJ */
+        GPIO_PTJ7, GPIO_PTJ5, GPIO_PTJ3, GPIO_PTJ2,
+        GPIO_PTJ1, GPIO_PTJ0,
+
+        /* PTK */
+        GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
+        GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+        /* PTL */
+        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
+        GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
+
+        /* PTM */
+        GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+        /* PTN */
+        GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
+        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
+
+        /* PTQ */
+        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
+
+        /* PTR */
+        GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
+        GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+        /* PTS */
+        GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
+        GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+        /* PTT */
+        GPIO_PTT5, GPIO_PTT4, GPIO_PTT3, GPIO_PTT2,
+        GPIO_PTT1, GPIO_PTT0,
+
+        /* PTU */
+        GPIO_PTU5, GPIO_PTU4, GPIO_PTU3, GPIO_PTU2,
+        GPIO_PTU1, GPIO_PTU0,
+
+        /* PTV */
+        GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
+        GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+        /* PTW */
+        GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
+        GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
+
+        /* PTX */
+        GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
+        GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
+
+        /* PTY */
+        GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
+        GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
+
+        /* PTZ */
+        GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
+        GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
+
+        /* SCIF0 (SCIF: 3 pin PTT/PTU) */
+        GPIO_FN_SCIF0_PTT_TXD, GPIO_FN_SCIF0_PTT_RXD, GPIO_FN_SCIF0_PTT_SCK,
+        GPIO_FN_SCIF0_PTU_TXD, GPIO_FN_SCIF0_PTU_RXD, GPIO_FN_SCIF0_PTU_SCK,
+
+        /* SCIF1 (SCIF: 3 pin PTS/PTV) */
+        GPIO_FN_SCIF1_PTS_TXD, GPIO_FN_SCIF1_PTS_RXD, GPIO_FN_SCIF1_PTS_SCK,
+        GPIO_FN_SCIF1_PTV_TXD, GPIO_FN_SCIF1_PTV_RXD, GPIO_FN_SCIF1_PTV_SCK,
+
+        /* SCIF2 (SCIF: 3 pin PTT/PTU) */
+        GPIO_FN_SCIF2_PTT_TXD, GPIO_FN_SCIF2_PTT_RXD, GPIO_FN_SCIF2_PTT_SCK,
+        GPIO_FN_SCIF2_PTU_TXD, GPIO_FN_SCIF2_PTU_RXD, GPIO_FN_SCIF2_PTU_SCK,
+
+        /* SCIF3 (SCIFA: 5 pin PTS/PTV) */
+        GPIO_FN_SCIF3_PTS_TXD, GPIO_FN_SCIF3_PTS_RXD, GPIO_FN_SCIF3_PTS_SCK,
+        GPIO_FN_SCIF3_PTS_RTS, GPIO_FN_SCIF3_PTS_CTS,
+        GPIO_FN_SCIF3_PTV_TXD, GPIO_FN_SCIF3_PTV_RXD, GPIO_FN_SCIF3_PTV_SCK,
+        GPIO_FN_SCIF3_PTV_RTS, GPIO_FN_SCIF3_PTV_CTS,
+
+        /* SCIF4 (SCIFA: 3 pin PTE/PTN) */
+        GPIO_FN_SCIF4_PTE_TXD, GPIO_FN_SCIF4_PTE_RXD, GPIO_FN_SCIF4_PTE_SCK,
+        GPIO_FN_SCIF4_PTN_TXD, GPIO_FN_SCIF4_PTN_RXD, GPIO_FN_SCIF4_PTN_SCK,
+
+        /* SCIF5 (SCIFA: 3 pin PTE/PTN) */
+        GPIO_FN_SCIF5_PTE_TXD, GPIO_FN_SCIF5_PTE_RXD, GPIO_FN_SCIF5_PTE_SCK,
+        GPIO_FN_SCIF5_PTN_TXD, GPIO_FN_SCIF5_PTN_RXD, GPIO_FN_SCIF5_PTN_SCK,
+
+        /* CEU */
+        GPIO_FN_VIO_D15, GPIO_FN_VIO_D14, GPIO_FN_VIO_D13, GPIO_FN_VIO_D12,
+        GPIO_FN_VIO_D11, GPIO_FN_VIO_D10, GPIO_FN_VIO_D9, GPIO_FN_VIO_D8,
+        GPIO_FN_VIO_D7, GPIO_FN_VIO_D6, GPIO_FN_VIO_D5, GPIO_FN_VIO_D4,
+        GPIO_FN_VIO_D3, GPIO_FN_VIO_D2, GPIO_FN_VIO_D1, GPIO_FN_VIO_D0,
+        GPIO_FN_VIO_FLD, GPIO_FN_VIO_CKO,
+        GPIO_FN_VIO_VD1, GPIO_FN_VIO_HD1, GPIO_FN_VIO_CLK1,
+        GPIO_FN_VIO_VD2, GPIO_FN_VIO_HD2, GPIO_FN_VIO_CLK2,
+
+        /* LCDC */
+        GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
+        GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
+        GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
+        GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8,
+        GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4,
+        GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0,
+        GPIO_FN_LCDLCLK_PTR, GPIO_FN_LCDLCLK_PTW,
+        /* Main LCD */
+        GPIO_FN_LCDDON, GPIO_FN_LCDVCPWC, GPIO_FN_LCDVEPWC, GPIO_FN_LCDVSYN,
+        /* Main LCD - RGB Mode */
+        GPIO_FN_LCDDCK, GPIO_FN_LCDHSYN, GPIO_FN_LCDDISP,
+        /* Main LCD - SYS Mode */
+        GPIO_FN_LCDRS, GPIO_FN_LCDCS, GPIO_FN_LCDWR, GPIO_FN_LCDRD,
+
+        /* IRQ */
+        GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3,
+        GPIO_FN_IRQ4, GPIO_FN_IRQ5, GPIO_FN_IRQ6, GPIO_FN_IRQ7,
+
+        /* AUD */
+        GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
+        GPIO_FN_AUDCK, GPIO_FN_AUDSYNC,
+
+        /* SDHI0 (PTD) */
+        GPIO_FN_SDHI0CD_PTD, GPIO_FN_SDHI0WP_PTD,
+        GPIO_FN_SDHI0D3_PTD, GPIO_FN_SDHI0D2_PTD,
+        GPIO_FN_SDHI0D1_PTD, GPIO_FN_SDHI0D0_PTD,
+        GPIO_FN_SDHI0CMD_PTD, GPIO_FN_SDHI0CLK_PTD,
+
+        /* SDHI0 (PTS) */
+        GPIO_FN_SDHI0CD_PTS, GPIO_FN_SDHI0WP_PTS,
+        GPIO_FN_SDHI0D3_PTS, GPIO_FN_SDHI0D2_PTS,
+        GPIO_FN_SDHI0D1_PTS, GPIO_FN_SDHI0D0_PTS,
+        GPIO_FN_SDHI0CMD_PTS, GPIO_FN_SDHI0CLK_PTS,
+
+        /* SDHI1 */
+        GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2,
+        GPIO_FN_SDHI1D1, GPIO_FN_SDHI1D0, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK,
+
+        /* SIUA */
+        GPIO_FN_SIUAFCK, GPIO_FN_SIUAILR, GPIO_FN_SIUAIBT, GPIO_FN_SIUAISLD,
+        GPIO_FN_SIUAOLR, GPIO_FN_SIUAOBT, GPIO_FN_SIUAOSLD, GPIO_FN_SIUAMCK,
+        GPIO_FN_SIUAISPD, GPIO_FN_SIUOSPD,
+
+        /* SIUB */
+        GPIO_FN_SIUBFCK, GPIO_FN_SIUBILR, GPIO_FN_SIUBIBT, GPIO_FN_SIUBISLD,
+        GPIO_FN_SIUBOLR, GPIO_FN_SIUBOBT, GPIO_FN_SIUBOSLD, GPIO_FN_SIUBMCK,
+
+        /* IRDA */
+        GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
+
+        /* VOU */
+        GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_HSYNC, GPIO_FN_DV_VSYNC,
+        GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12,
+        GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8,
+        GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4,
+        GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0,
+
+        /* KEYSC */
+        GPIO_FN_KEYIN0, GPIO_FN_KEYIN1, GPIO_FN_KEYIN2, GPIO_FN_KEYIN3,
+        GPIO_FN_KEYIN4, GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
+        GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5,
+
+        /* MSIOF0 (PTF) */
+        GPIO_FN_MSIOF0_PTF_TXD, GPIO_FN_MSIOF0_PTF_RXD, GPIO_FN_MSIOF0_PTF_MCK,
+        GPIO_FN_MSIOF0_PTF_TSYNC, GPIO_FN_MSIOF0_PTF_TSCK,
+        GPIO_FN_MSIOF0_PTF_RSYNC, GPIO_FN_MSIOF0_PTF_RSCK,
+        GPIO_FN_MSIOF0_PTF_SS1, GPIO_FN_MSIOF0_PTF_SS2,
+
+        /* MSIOF0 (PTT+PTX) */
+        GPIO_FN_MSIOF0_PTT_TXD, GPIO_FN_MSIOF0_PTT_RXD, GPIO_FN_MSIOF0_PTX_MCK,
+        GPIO_FN_MSIOF0_PTT_TSYNC, GPIO_FN_MSIOF0_PTT_TSCK,
+        GPIO_FN_MSIOF0_PTT_RSYNC, GPIO_FN_MSIOF0_PTT_RSCK,
+        GPIO_FN_MSIOF0_PTT_SS1, GPIO_FN_MSIOF0_PTT_SS2,
+
+        /* MSIOF1 */
+        GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_MCK,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_TSCK,
+        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MSIOF1_RSCK,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_MSIOF1_SS2,
+
+        /* TSIF */
+        GPIO_FN_TS0_SDAT, GPIO_FN_TS0_SCK, GPIO_FN_TS0_SDEN, GPIO_FN_TS0_SPSYNC,
+
+        /* FLCTL */
+        GPIO_FN_FCE, GPIO_FN_NAF7, GPIO_FN_NAF6, GPIO_FN_NAF5, GPIO_FN_NAF4,
+        GPIO_FN_NAF3, GPIO_FN_NAF2, GPIO_FN_NAF1, GPIO_FN_NAF0, GPIO_FN_FCDE,
+        GPIO_FN_FOE, GPIO_FN_FSC, GPIO_FN_FWE, GPIO_FN_FRB,
+
+        /* DMAC */
+        GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DACK0, GPIO_FN_DREQ0,
+
+        /* ADC */
+        GPIO_FN_AN3, GPIO_FN_AN2, GPIO_FN_AN1, GPIO_FN_AN0, GPIO_FN_ADTRG,
+
+        /* CPG */
+        GPIO_FN_STATUS0, GPIO_FN_PDSTATUS,
+
+        /* TPU */
+        GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0,
+
+        /* BSC */
+        GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+        GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+        GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+        GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+        GPIO_FN_IOIS16, GPIO_FN_WAIT, GPIO_FN_BS,
+        GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+        GPIO_FN_CS6B_CE1B, GPIO_FN_CS6A_CE2B,
+        GPIO_FN_CS5B_CE1A, GPIO_FN_CS5A_CE2A,
+        GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD,
+
+        /* ATAPI */
+        GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12,
+        GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9, GPIO_FN_IDED8,
+        GPIO_FN_IDED7, GPIO_FN_IDED6, GPIO_FN_IDED5, GPIO_FN_IDED4,
+        GPIO_FN_IDED3, GPIO_FN_IDED2, GPIO_FN_IDED1, GPIO_FN_IDED0,
+        GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK,
+        GPIO_FN_IODREQ, GPIO_FN_IDEIORDY, GPIO_FN_IDEINT, GPIO_FN_IDEIOWR,
+        GPIO_FN_IDEIORD, GPIO_FN_IDECS1, GPIO_FN_IDECS0, GPIO_FN_IDEA2,
+        GPIO_FN_IDEA1, GPIO_FN_IDEA0,
+};
+
+#endif /* __ASM_SH7723_H__ */
diff --git a/arch/sh/include/asm/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h
index 5bdc9d9be3de..5bdc9d9be3de 100644
--- a/arch/sh/include/asm/edosk7705.h
+++ b/arch/sh/include/mach-common/mach/edosk7705.h
diff --git a/arch/sh/include/asm/r7780rp.h b/arch/sh/include/mach-common/mach/highlander.h
index 306f7359f7d4..306f7359f7d4 100644
--- a/arch/sh/include/asm/r7780rp.h
+++ b/arch/sh/include/mach-common/mach/highlander.h
diff --git a/arch/sh/include/asm/hp6xx.h b/arch/sh/include/mach-common/mach/hp6xx.h
index 0d4165a32dcd..0d4165a32dcd 100644
--- a/arch/sh/include/asm/hp6xx.h
+++ b/arch/sh/include/mach-common/mach/hp6xx.h
diff --git a/arch/sh/include/asm/lboxre2.h b/arch/sh/include/mach-common/mach/lboxre2.h
index e6d160504923..e6d160504923 100644
--- a/arch/sh/include/asm/lboxre2.h
+++ b/arch/sh/include/mach-common/mach/lboxre2.h
diff --git a/arch/sh/include/asm/magicpanelr2.h b/arch/sh/include/mach-common/mach/magicpanelr2.h
index c644a77ee357..c644a77ee357 100644
--- a/arch/sh/include/asm/magicpanelr2.h
+++ b/arch/sh/include/mach-common/mach/magicpanelr2.h
diff --git a/arch/sh/include/asm/microdev.h b/arch/sh/include/mach-common/mach/microdev.h
index 1aed15856e11..1aed15856e11 100644
--- a/arch/sh/include/asm/microdev.h
+++ b/arch/sh/include/mach-common/mach/microdev.h
diff --git a/arch/sh/include/asm/migor.h b/arch/sh/include/mach-common/mach/migor.h
index c12b632c540b..e451f0229e00 100644
--- a/arch/sh/include/asm/migor.h
+++ b/arch/sh/include/mach-common/mach/migor.h
@@ -52,9 +52,11 @@
 #define PORT_HIZCRB 0xa405015a
 #define PORT_HIZCRC 0xa405015c
 
+#define BSC_CS4BCR 0xfec10010
 #define BSC_CS6ABCR 0xfec1001c
+#define BSC_CS4WCR 0xfec10030
 
-#include <asm/sh_mobile_lcdc.h>
+#include <video/sh_mobile_lcdc.h>
 
 int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
                          struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
diff --git a/arch/sh/include/asm/rts7751r2d.h b/arch/sh/include/mach-common/mach/r2d.h
index 0a800157b826..0a800157b826 100644
--- a/arch/sh/include/asm/rts7751r2d.h
+++ b/arch/sh/include/mach-common/mach/r2d.h
diff --git a/arch/sh/include/asm/sdk7780.h b/arch/sh/include/mach-common/mach/sdk7780.h
index 697dc865f21b..697dc865f21b 100644
--- a/arch/sh/include/asm/sdk7780.h
+++ b/arch/sh/include/mach-common/mach/sdk7780.h
diff --git a/arch/sh/include/asm/sh7763rdp.h b/arch/sh/include/mach-common/mach/sh7763rdp.h
index 8750cc852977..8750cc852977 100644
--- a/arch/sh/include/asm/sh7763rdp.h
+++ b/arch/sh/include/mach-common/mach/sh7763rdp.h
diff --git a/arch/sh/include/asm/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 1ce27d5c7491..1ce27d5c7491 100644
--- a/arch/sh/include/asm/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
diff --git a/arch/sh/include/asm/shmin.h b/arch/sh/include/mach-common/mach/shmin.h
index 36ba138a81fb..36ba138a81fb 100644
--- a/arch/sh/include/asm/shmin.h
+++ b/arch/sh/include/mach-common/mach/shmin.h
diff --git a/arch/sh/include/asm/snapgear.h b/arch/sh/include/mach-common/mach/snapgear.h
index 042d95f51c4d..042d95f51c4d 100644
--- a/arch/sh/include/asm/snapgear.h
+++ b/arch/sh/include/mach-common/mach/snapgear.h
diff --git a/arch/sh/include/asm/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h
index 4161122c84ef..4161122c84ef 100644
--- a/arch/sh/include/asm/systemh7751.h
+++ b/arch/sh/include/mach-common/mach/systemh7751.h
diff --git a/arch/sh/include/asm/titan.h b/arch/sh/include/mach-common/mach/titan.h
index 03f3583c8918..03f3583c8918 100644
--- a/arch/sh/include/asm/titan.h
+++ b/arch/sh/include/mach-common/mach/titan.h
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
index 0e6905fe9fec..48edfb145fb4 100644
--- a/arch/sh/kernel/Makefile_32
+++ b/arch/sh/kernel/Makefile_32
@@ -21,7 +21,8 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
-obj-$(CONFIG_ELF_CORE)          += dump_task.o
 obj-$(CONFIG_IO_TRAPPED)        += io_trapped.o
+obj-$(CONFIG_KPROBES)           += kprobes.o
+obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64
index 6edf53b93d94..c97660b2b48d 100644
--- a/arch/sh/kernel/Makefile_64
+++ b/arch/sh/kernel/Makefile_64
@@ -17,7 +17,7 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
-obj-$(CONFIG_BINFMT_ELF)        += dump_task.o
 obj-$(CONFIG_IO_TRAPPED)        += io_trapped.o
+obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index f5eb56e6bc59..b7e46d5bba43 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -294,9 +294,10 @@ arch_init_clk_ops(struct clk_ops **ops, int type)
 {
 }
 
-void __init __attribute__ ((weak))
+int __init __attribute__ ((weak))
 arch_clk_init(void)
 {
+        return 0;
 }
 
 static int show_clocks(char *buf, char **start, off_t off,
@@ -331,7 +332,7 @@ int __init clk_init(void)
                 ret |= clk_register(clk);
         }
 
-        arch_clk_init();
+        ret |= arch_clk_init();
 
         /* Kick the child clocks.. */
         propagate_rate(&master_clk);
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile
index 462a8f6dfee2..f0c7025a67d1 100644
--- a/arch/sh/kernel/cpu/irq/Makefile
+++ b/arch/sh/kernel/cpu/irq/Makefile
@@ -1,8 +1,6 @@
 #
 # Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
 #
-obj-y   += intc.o
-
 obj-$(CONFIG_SUPERH32)                  += imask.o
 obj-$(CONFIG_CPU_SH5)                   += intc-sh5.o
 obj-$(CONFIG_CPU_HAS_IPR_IRQ)           += ipr.o
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
deleted file mode 100644
index 8c70e201bde0..000000000000
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ /dev/null
@@ -1,710 +0,0 @@
-/*
- * Shared interrupt handling code for IPR and INTC2 types of IRQs.
- *
- * Copyright (C) 2007, 2008 Magnus Damm
- *
- * Based on intc2.c and ipr.c
- *
- * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
- * Copyright (C) 2000  Kazumoto Kojima
- * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
- * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
- * Copyright (C) 2005, 2006  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/bootmem.h>
-
-#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
-        ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
-         ((addr_e) << 16) | ((addr_d << 24)))
-
-#define _INTC_SHIFT(h) (h & 0x1f)
-#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
-#define _INTC_FN(h) ((h >> 9) & 0xf)
-#define _INTC_MODE(h) ((h >> 13) & 0x7)
-#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
-#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
-
-struct intc_handle_int {
-        unsigned int irq;
-        unsigned long handle;
-};
-
-struct intc_desc_int {
-        unsigned long *reg;
-#ifdef CONFIG_SMP
-        unsigned long *smp;
-#endif
-        unsigned int nr_reg;
-        struct intc_handle_int *prio;
-        unsigned int nr_prio;
-        struct intc_handle_int *sense;
-        unsigned int nr_sense;
-        struct irq_chip chip;
-};
-
-#ifdef CONFIG_SMP
-#define IS_SMP(x) x.smp
-#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
-#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
-#else
-#define IS_SMP(x) 0
-#define INTC_REG(d, x, c) (d->reg[(x)])
-#define SMP_NR(d, x) 1
-#endif
-
-static unsigned int intc_prio_level[NR_IRQS]; /* for now */
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-static unsigned long ack_handle[NR_IRQS];
-#endif
-
-static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
-{
-        struct irq_chip *chip = get_irq_chip(irq);
-        return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
-}
-
-static inline unsigned int set_field(unsigned int value,
-                                     unsigned int field_value,
-                                     unsigned int handle)
-{
-        unsigned int width = _INTC_WIDTH(handle);
-        unsigned int shift = _INTC_SHIFT(handle);
-
-        value &= ~(((1 << width) - 1) << shift);
-        value |= field_value << shift;
-        return value;
-}
-
-static void write_8(unsigned long addr, unsigned long h, unsigned long data)
-{
-        ctrl_outb(set_field(0, data, h), addr);
-}
-
-static void write_16(unsigned long addr, unsigned long h, unsigned long data)
-{
-        ctrl_outw(set_field(0, data, h), addr);
-}
-
-static void write_32(unsigned long addr, unsigned long h, unsigned long data)
-{
-        ctrl_outl(set_field(0, data, h), addr);
-}
-
-static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
-        local_irq_restore(flags);
-}
-
-static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
-        local_irq_restore(flags);
-}
-
-static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
-        local_irq_restore(flags);
-}
-
-enum {  REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
-
-static void (*intc_reg_fns[])(unsigned long addr,
-                              unsigned long h,
-                              unsigned long data) = {
-        [REG_FN_WRITE_BASE + 0] = write_8,
-        [REG_FN_WRITE_BASE + 1] = write_16,
-        [REG_FN_WRITE_BASE + 3] = write_32,
-        [REG_FN_MODIFY_BASE + 0] = modify_8,
-        [REG_FN_MODIFY_BASE + 1] = modify_16,
-        [REG_FN_MODIFY_BASE + 3] = modify_32,
-};
-
-enum {  MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
-        MODE_MASK_REG,       /* Bit(s) set -> interrupt disabled */
-        MODE_DUAL_REG,       /* Two registers, set bit to enable / disable */
-        MODE_PRIO_REG,       /* Priority value written to enable interrupt */
-        MODE_PCLR_REG,       /* Above plus all bits set to disable interrupt */
-};
-
-static void intc_mode_field(unsigned long addr,
-                            unsigned long handle,
-                            void (*fn)(unsigned long,
-                                       unsigned long,
-                                       unsigned long),
-                            unsigned int irq)
-{
-        fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
-}
-
-static void intc_mode_zero(unsigned long addr,
-                           unsigned long handle,
-                           void (*fn)(unsigned long,
-                                       unsigned long,
-                                       unsigned long),
-                           unsigned int irq)
-{
-        fn(addr, handle, 0);
-}
-
-static void intc_mode_prio(unsigned long addr,
-                           unsigned long handle,
-                           void (*fn)(unsigned long,
-                                       unsigned long,
-                                       unsigned long),
-                           unsigned int irq)
-{
-        fn(addr, handle, intc_prio_level[irq]);
-}
-
-static void (*intc_enable_fns[])(unsigned long addr,
-                                 unsigned long handle,
-                                 void (*fn)(unsigned long,
-                                            unsigned long,
-                                            unsigned long),
-                                 unsigned int irq) = {
-        [MODE_ENABLE_REG] = intc_mode_field,
-        [MODE_MASK_REG] = intc_mode_zero,
-        [MODE_DUAL_REG] = intc_mode_field,
-        [MODE_PRIO_REG] = intc_mode_prio,
-        [MODE_PCLR_REG] = intc_mode_prio,
-};
-
-static void (*intc_disable_fns[])(unsigned long addr,
-                                  unsigned long handle,
-                                  void (*fn)(unsigned long,
-                                             unsigned long,
-                                             unsigned long),
-                                  unsigned int irq) = {
-        [MODE_ENABLE_REG] = intc_mode_zero,
-        [MODE_MASK_REG] = intc_mode_field,
-        [MODE_DUAL_REG] = intc_mode_field,
-        [MODE_PRIO_REG] = intc_mode_zero,
-        [MODE_PCLR_REG] = intc_mode_field,
-};
-
-static inline void _intc_enable(unsigned int irq, unsigned long handle)
-{
-        struct intc_desc_int *d = get_intc_desc(irq);
-        unsigned long addr;
-        unsigned int cpu;
-
-        for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
-                addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
-                intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
-                                                    [_INTC_FN(handle)], irq);
-        }
-}
-
-static void intc_enable(unsigned int irq)
-{
-        _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
-}
-
-static void intc_disable(unsigned int irq)
-{
-        struct intc_desc_int *d = get_intc_desc(irq);
-        unsigned long handle = (unsigned long) get_irq_chip_data(irq);
-        unsigned long addr;
-        unsigned int cpu;
-
-        for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
-                addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
-                intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
-                                                     [_INTC_FN(handle)], irq);
-        }
-}
-
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-static void intc_mask_ack(unsigned int irq)
-{
-        struct intc_desc_int *d = get_intc_desc(irq);
-        unsigned long handle = ack_handle[irq];
-        unsigned long addr;
-
-        intc_disable(irq);
-
-        /* read register and write zero only to the assocaited bit */
-
-        if (handle) {
-                addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
-                switch (_INTC_FN(handle)) {
-                case REG_FN_MODIFY_BASE + 0:    /* 8bit */
-                        ctrl_inb(addr);
-                        ctrl_outb(0xff ^ set_field(0, 1, handle), addr);
-                        break;
-                case REG_FN_MODIFY_BASE + 1:    /* 16bit */
-                        ctrl_inw(addr);
-                        ctrl_outw(0xffff ^ set_field(0, 1, handle), addr);
-                        break;
-                case REG_FN_MODIFY_BASE + 3:    /* 32bit */
-                        ctrl_inl(addr);
-                        ctrl_outl(0xffffffff ^ set_field(0, 1, handle), addr);
-                        break;
-                default:
-                        BUG();
-                        break;
-                }
-        }
-}
-#endif
-
-static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
-                                             unsigned int nr_hp,
-                                             unsigned int irq)
-{
-        int i;
-
-        /* this doesn't scale well, but...
-         *
-         * this function should only be used for cerain uncommon
-         * operations such as intc_set_priority() and intc_set_sense()
-         * and in those rare cases performance doesn't matter that much.
-         * keeping the memory footprint low is more important.
-         *
-         * one rather simple way to speed this up and still keep the
-         * memory footprint down is to make sure the array is sorted
-         * and then perform a bisect to lookup the irq.
-         */
-
-        for (i = 0; i < nr_hp; i++) {
-                if ((hp + i)->irq != irq)
-                        continue;
-
-                return hp + i;
-        }
-
-        return NULL;
-}
-
-int intc_set_priority(unsigned int irq, unsigned int prio)
-{
-        struct intc_desc_int *d = get_intc_desc(irq);
-        struct intc_handle_int *ihp;
-
-        if (!intc_prio_level[irq] || prio <= 1)
-                return -EINVAL;
-
-        ihp = intc_find_irq(d->prio, d->nr_prio, irq);
-        if (ihp) {
-                if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
-                        return -EINVAL;
-
-                intc_prio_level[irq] = prio;
-
-                /*
-                 * only set secondary masking method directly
-                 * primary masking method is using intc_prio_level[irq]
-                 * priority level will be set during next enable()
-                 */
-
-                if (_INTC_FN(ihp->handle) != REG_FN_ERR)
-                        _intc_enable(irq, ihp->handle);
-        }
-        return 0;
-}
-
-#define VALID(x) (x | 0x80)
-
-static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
-        [IRQ_TYPE_EDGE_FALLING] = VALID(0),
-        [IRQ_TYPE_EDGE_RISING] = VALID(1),
-        [IRQ_TYPE_LEVEL_LOW] = VALID(2),
-        /* SH7706, SH7707 and SH7709 do not support high level triggered */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
-    !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
-    !defined(CONFIG_CPU_SUBTYPE_SH7709)
-        [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
-#endif
-};
-
-static int intc_set_sense(unsigned int irq, unsigned int type)
-{
-        struct intc_desc_int *d = get_intc_desc(irq);
-        unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
-        struct intc_handle_int *ihp;
-        unsigned long addr;
-
-        if (!value)
-                return -EINVAL;
-
-        ihp = intc_find_irq(d->sense, d->nr_sense, irq);
-        if (ihp) {
-                addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
-                intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
-        }
-        return 0;
-}
-
-static unsigned int __init intc_get_reg(struct intc_desc_int *d,
-                                 unsigned long address)
-{
-        unsigned int k;
-
-        for (k = 0; k < d->nr_reg; k++) {
-                if (d->reg[k] == address)
-                        return k;
-        }
-
-        BUG();
-        return 0;
-}
-
-static intc_enum __init intc_grp_id(struct intc_desc *desc,
-                                    intc_enum enum_id)
-{
-        struct intc_group *g = desc->groups;
-        unsigned int i, j;
-
-        for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
-                g = desc->groups + i;
-
-                for (j = 0; g->enum_ids[j]; j++) {
-                        if (g->enum_ids[j] != enum_id)
-                                continue;
-
-                        return g->enum_id;
-                }
-        }
-
-        return 0;
-}
-
-static unsigned int __init intc_mask_data(struct intc_desc *desc,
-                                          struct intc_desc_int *d,
-                                          intc_enum enum_id, int do_grps)
-{
-        struct intc_mask_reg *mr = desc->mask_regs;
-        unsigned int i, j, fn, mode;
-        unsigned long reg_e, reg_d;
-
-        for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
-                mr = desc->mask_regs + i;
-
-                for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
-                        if (mr->enum_ids[j] != enum_id)
-                                continue;
-
-                        if (mr->set_reg && mr->clr_reg) {
-                                fn = REG_FN_WRITE_BASE;
-                                mode = MODE_DUAL_REG;
-                                reg_e = mr->clr_reg;
-                                reg_d = mr->set_reg;
-                        } else {
-                                fn = REG_FN_MODIFY_BASE;
-                                if (mr->set_reg) {
-                                        mode = MODE_ENABLE_REG;
-                                        reg_e = mr->set_reg;
-                                        reg_d = mr->set_reg;
-                                } else {
-                                        mode = MODE_MASK_REG;
-                                        reg_e = mr->clr_reg;
-                                        reg_d = mr->clr_reg;
-                                }
-                        }
-
-                        fn += (mr->reg_width >> 3) - 1;
-                        return _INTC_MK(fn, mode,
-                                        intc_get_reg(d, reg_e),
-                                        intc_get_reg(d, reg_d),
-                                        1,
-                                        (mr->reg_width - 1) - j);
-                }
-        }
-
-        if (do_grps)
-                return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
-
-        return 0;
-}
-
-static unsigned int __init intc_prio_data(struct intc_desc *desc,
-                                          struct intc_desc_int *d,
-                                          intc_enum enum_id, int do_grps)
-{
-        struct intc_prio_reg *pr = desc->prio_regs;
-        unsigned int i, j, fn, mode, bit;
-        unsigned long reg_e, reg_d;
-
-        for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
-                pr = desc->prio_regs + i;
-
-                for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
-                        if (pr->enum_ids[j] != enum_id)
-                                continue;
-
-                        if (pr->set_reg && pr->clr_reg) {
-                                fn = REG_FN_WRITE_BASE;
-                                mode = MODE_PCLR_REG;
-                                reg_e = pr->set_reg;
-                                reg_d = pr->clr_reg;
-                        } else {
-                                fn = REG_FN_MODIFY_BASE;
-                                mode = MODE_PRIO_REG;
-                                if (!pr->set_reg)
-                                        BUG();
-                                reg_e = pr->set_reg;
-                                reg_d = pr->set_reg;
-                        }
-
-                        fn += (pr->reg_width >> 3) - 1;
-                        bit = pr->reg_width - ((j + 1) * pr->field_width);
-
-                        BUG_ON(bit < 0);
-
-                        return _INTC_MK(fn, mode,
-                                        intc_get_reg(d, reg_e),
-                                        intc_get_reg(d, reg_d),
-                                        pr->field_width, bit);
-                }
-        }
-
-        if (do_grps)
-                return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
-
-        return 0;
-}
-
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-static unsigned int __init intc_ack_data(struct intc_desc *desc,
-                                          struct intc_desc_int *d,
-                                          intc_enum enum_id)
-{
-        struct intc_mask_reg *mr = desc->ack_regs;
-        unsigned int i, j, fn, mode;
-        unsigned long reg_e, reg_d;
-
-        for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
-                mr = desc->ack_regs + i;
-
-                for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
-                        if (mr->enum_ids[j] != enum_id)
-                                continue;
-
-                        fn = REG_FN_MODIFY_BASE;
-                        mode = MODE_ENABLE_REG;
-                        reg_e = mr->set_reg;
-                        reg_d = mr->set_reg;
-
-                        fn += (mr->reg_width >> 3) - 1;
-                        return _INTC_MK(fn, mode,
-                                        intc_get_reg(d, reg_e),
-                                        intc_get_reg(d, reg_d),
-                                        1,
-                                        (mr->reg_width - 1) - j);
-                }
-        }
-
-        return 0;
-}
-#endif
-
-static unsigned int __init intc_sense_data(struct intc_desc *desc,
-                                           struct intc_desc_int *d,
-                                           intc_enum enum_id)
-{
-        struct intc_sense_reg *sr = desc->sense_regs;
-        unsigned int i, j, fn, bit;
-
-        for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
-                sr = desc->sense_regs + i;
-
-                for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
-                        if (sr->enum_ids[j] != enum_id)
-                                continue;
-
-                        fn = REG_FN_MODIFY_BASE;
-                        fn += (sr->reg_width >> 3) - 1;
-                        bit = sr->reg_width - ((j + 1) * sr->field_width);
-
-                        BUG_ON(bit < 0);
-
-                        return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
-                                        0, sr->field_width, bit);
-                }
-        }
-
-        return 0;
-}
-
-static void __init intc_register_irq(struct intc_desc *desc,
-                                     struct intc_desc_int *d,
-                                     intc_enum enum_id,
-                                     unsigned int irq)
-{
-        struct intc_handle_int *hp;
-        unsigned int data[2], primary;
-
-        /* Prefer single interrupt source bitmap over other combinations:
-         * 1. bitmap, single interrupt source
-         * 2. priority, single interrupt source
-         * 3. bitmap, multiple interrupt sources (groups)
-         * 4. priority, multiple interrupt sources (groups)
-         */
-
-        data[0] = intc_mask_data(desc, d, enum_id, 0);
-        data[1] = intc_prio_data(desc, d, enum_id, 0);
-
-        primary = 0;
-        if (!data[0] && data[1])
-                primary = 1;
-
-        data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
-        data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
-
-        if (!data[primary])
-                primary ^= 1;
-
-        BUG_ON(!data[primary]); /* must have primary masking method */
-
-        disable_irq_nosync(irq);
-        set_irq_chip_and_handler_name(irq, &d->chip,
-                                      handle_level_irq, "level");
-        set_irq_chip_data(irq, (void *)data[primary]);
-
-        /* set priority level
-         * - this needs to be at least 2 for 5-bit priorities on 7780
-         */
-        intc_prio_level[irq] = 2;
-
-        /* enable secondary masking method if present */
-        if (data[!primary])
-                _intc_enable(irq, data[!primary]);
-
-        /* add irq to d->prio list if priority is available */
-        if (data[1]) {
-                hp = d->prio + d->nr_prio;
-                hp->irq = irq;
-                hp->handle = data[1];
-
-                if (primary) {
-                        /*
-                         * only secondary priority should access registers, so
-                         * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
-                         */
-
-                        hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
-                        hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
-                }
-                d->nr_prio++;
-        }
-
-        /* add irq to d->sense list if sense is available */
-        data[0] = intc_sense_data(desc, d, enum_id);
-        if (data[0]) {
-                (d->sense + d->nr_sense)->irq = irq;
-                (d->sense + d->nr_sense)->handle = data[0];
-                d->nr_sense++;
-        }
-
-        /* irq should be disabled by default */
-        d->chip.mask(irq);
-
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        if (desc->ack_regs)
-                ack_handle[irq] = intc_ack_data(desc, d, enum_id);
-#endif
-}
-
-static unsigned int __init save_reg(struct intc_desc_int *d,
-                                    unsigned int cnt,
-                                    unsigned long value,
-                                    unsigned int smp)
-{
-        if (value) {
-                d->reg[cnt] = value;
-#ifdef CONFIG_SMP
-                d->smp[cnt] = smp;
-#endif
-                return 1;
-        }
-
-        return 0;
-}
-
-
-void __init register_intc_controller(struct intc_desc *desc)
-{
-        unsigned int i, k, smp;
-        struct intc_desc_int *d;
-
-        d = alloc_bootmem(sizeof(*d));
-
-        d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
-        d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
-        d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
-
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
-#endif
-        d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
-#ifdef CONFIG_SMP
-        d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
-#endif
-        k = 0;
-
-        if (desc->mask_regs) {
-                for (i = 0; i < desc->nr_mask_regs; i++) {
-                        smp = IS_SMP(desc->mask_regs[i]);
-                        k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
-                        k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
-                }
-        }
-
-        if (desc->prio_regs) {
-                d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
-
-                for (i = 0; i < desc->nr_prio_regs; i++) {
-                        smp = IS_SMP(desc->prio_regs[i]);
-                        k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
-                        k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
-                }
-        }
-
-        if (desc->sense_regs) {
-                d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
-
-                for (i = 0; i < desc->nr_sense_regs; i++) {
-                        k += save_reg(d, k, desc->sense_regs[i].reg, 0);
-                }
-        }
-
-        d->chip.name = desc->name;
-        d->chip.mask = intc_disable;
-        d->chip.unmask = intc_enable;
-        d->chip.mask_ack = intc_disable;
-        d->chip.set_type = intc_set_sense;
-
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        if (desc->ack_regs) {
-                for (i = 0; i < desc->nr_ack_regs; i++)
-                        k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
-
-                d->chip.mask_ack = intc_mask_ack;
-        }
-#endif
-
-        BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
-
-        for (i = 0; i < desc->nr_vectors; i++) {
-                struct intc_vect *vect = desc->vectors + i;
-
-                intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
-        }
-}
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 56ea7b269b59..3eb17ee5540e 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -33,7 +33,7 @@ static void disable_ipr_irq(unsigned int irq)
         struct ipr_data *p = get_irq_chip_data(irq);
         unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
         /* Set the priority in IPR to 0 */
-        ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr);
+        __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
 }
 
 static void enable_ipr_irq(unsigned int irq)
@@ -41,7 +41,7 @@ static void enable_ipr_irq(unsigned int irq)
         struct ipr_data *p = get_irq_chip_data(irq);
         unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
         /* Set priority in IPR back to original value */
-        ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr);
+        __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
 }
 
 /*
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 1ab1ecf4c768..428450cc0809 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -12,3 +12,8 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7206)	+= setup-sh7206.o clock-sh7206.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7203)        += setup-sh7203.o clock-sh7203.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7263)        += setup-sh7203.o clock-sh7203.o
 obj-$(CONFIG_CPU_SUBTYPE_MXG)           += setup-mxg.o clock-sh7206.o
+
+# Pinmux setup
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7203)     := pinmux-sh7203.o
+
+obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
new file mode 100644
index 000000000000..39a5b880418f
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -0,0 +1,1599 @@
+/*
+ * SH7203 Pinmux
+ *
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <asm/sh7203.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
+        PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
+        PB12_DATA,
+        PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
+        PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+        PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
+        PC14_DATA, PC13_DATA, PC12_DATA,
+        PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
+        PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+        PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
+        PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
+        PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
+        PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+        PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
+        PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
+        PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
+        PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
+        PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
+        PF30_DATA, PF29_DATA, PF28_DATA,
+        PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
+        PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
+        PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA,
+        PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
+        PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
+        PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+        PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PA7_IN, PA6_IN, PA5_IN, PA4_IN,
+        PA3_IN, PA2_IN, PA1_IN, PA0_IN,
+        PB11_IN, PB10_IN, PB9_IN, PB8_IN,
+        PB7_IN, PB6_IN, PB5_IN, PB4_IN,
+        PB3_IN, PB2_IN, PB1_IN, PB0_IN,
+        PC14_IN, PC13_IN, PC12_IN,
+        PC11_IN, PC10_IN, PC9_IN, PC8_IN,
+        PC7_IN, PC6_IN, PC5_IN, PC4_IN,
+        PC3_IN, PC2_IN, PC1_IN, PC0_IN,
+        PD15_IN, PD14_IN, PD13_IN, PD12_IN,
+        PD11_IN, PD10_IN, PD9_IN, PD8_IN,
+        PD7_IN, PD6_IN, PD5_IN, PD4_IN,
+        PD3_IN, PD2_IN, PD1_IN, PD0_IN,
+        PE15_IN, PE14_IN, PE13_IN, PE12_IN,
+        PE11_IN, PE10_IN, PE9_IN, PE8_IN,
+        PE7_IN, PE6_IN, PE5_IN, PE4_IN,
+        PE3_IN, PE2_IN, PE1_IN, PE0_IN,
+        PF30_IN, PF29_IN, PF28_IN,
+        PF27_IN, PF26_IN, PF25_IN, PF24_IN,
+        PF23_IN, PF22_IN, PF21_IN, PF20_IN,
+        PF19_IN, PF18_IN, PF17_IN, PF16_IN,
+        PF15_IN, PF14_IN, PF13_IN, PF12_IN,
+        PF11_IN, PF10_IN, PF9_IN, PF8_IN,
+        PF7_IN, PF6_IN, PF5_IN, PF4_IN,
+        PF3_IN, PF2_IN, PF1_IN, PF0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PB12_OUT,
+        PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
+        PC14_OUT, PC13_OUT, PC12_OUT,
+        PC11_OUT, PC10_OUT, PC9_OUT, PC8_OUT,
+        PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
+        PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
+        PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
+        PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
+        PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
+        PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
+        PE15_OUT, PE14_OUT, PE13_OUT, PE12_OUT,
+        PE11_OUT, PE10_OUT, PE9_OUT, PE8_OUT,
+        PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
+        PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
+        PF30_OUT, PF29_OUT, PF28_OUT,
+        PF27_OUT, PF26_OUT, PF25_OUT, PF24_OUT,
+        PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT,
+        PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT,
+        PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT,
+        PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
+        PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
+        PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PB11_IOR_IN, PB11_IOR_OUT,
+        PB10_IOR_IN, PB10_IOR_OUT,
+        PB9_IOR_IN, PB9_IOR_OUT,
+        PB8_IOR_IN, PB8_IOR_OUT,
+        PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
+        PB11MD_0, PB11MD_1,
+        PB10MD_0, PB10MD_1,
+        PB9MD_00, PB9MD_01, PB9MD_10,
+        PB8MD_00, PB8MD_01, PB8MD_10,
+        PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
+        PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
+        PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
+        PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
+        PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
+        PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
+        PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
+        PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
+
+        PB12IRQ_00, PB12IRQ_01, PB12IRQ_10,
+
+        PC14MD_0, PC14MD_1,
+        PC13MD_0, PC13MD_1,
+        PC12MD_0, PC12MD_1,
+        PC11MD_00, PC11MD_01, PC11MD_10,
+        PC10MD_00, PC10MD_01, PC10MD_10,
+        PC9MD_0, PC9MD_1,
+        PC8MD_0, PC8MD_1,
+        PC7MD_0, PC7MD_1,
+        PC6MD_0, PC6MD_1,
+        PC5MD_0, PC5MD_1,
+        PC4MD_0, PC4MD_1,
+        PC3MD_0, PC3MD_1,
+        PC2MD_0, PC2MD_1,
+        PC1MD_0, PC1MD_1,
+        PC0MD_00, PC0MD_01, PC0MD_10,
+
+        PD15MD_000, PD15MD_001, PD15MD_010, PD15MD_100, PD15MD_101,
+        PD14MD_000, PD14MD_001, PD14MD_010, PD14MD_101,
+        PD13MD_000, PD13MD_001, PD13MD_010, PD13MD_100, PD13MD_101,
+        PD12MD_000, PD12MD_001, PD12MD_010, PD12MD_100, PD12MD_101,
+        PD11MD_000, PD11MD_001, PD11MD_010, PD11MD_100, PD11MD_101,
+        PD10MD_000, PD10MD_001, PD10MD_010, PD10MD_100, PD10MD_101,
+        PD9MD_000, PD9MD_001, PD9MD_010, PD9MD_100, PD9MD_101,
+        PD8MD_000, PD8MD_001, PD8MD_010, PD8MD_100, PD8MD_101,
+        PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, PD7MD_100, PD7MD_101,
+        PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, PD6MD_100, PD6MD_101,
+        PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, PD5MD_100, PD5MD_101,
+        PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, PD4MD_100, PD4MD_101,
+        PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, PD3MD_100, PD3MD_101,
+        PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, PD2MD_100, PD2MD_101,
+        PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, PD1MD_100, PD1MD_101,
+        PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, PD0MD_100, PD0MD_101,
+
+        PE15MD_00, PE15MD_01, PE15MD_11,
+        PE14MD_00, PE14MD_01, PE14MD_11,
+        PE13MD_00, PE13MD_11,
+        PE12MD_00, PE12MD_11,
+        PE11MD_000, PE11MD_001, PE11MD_010, PE11MD_100,
+        PE10MD_000, PE10MD_001, PE10MD_010, PE10MD_100,
+        PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11,
+        PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
+        PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, PE7MD_100,
+        PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, PE6MD_100,
+        PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, PE5MD_100,
+        PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, PE4MD_100,
+        PE3MD_00, PE3MD_01, PE3MD_11,
+        PE2MD_00, PE2MD_01, PE2MD_11,
+        PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11,
+        PE0MD_000, PE0MD_001, PE0MD_011, PE0MD_100,
+
+        PF30MD_0, PF30MD_1,
+        PF29MD_0, PF29MD_1,
+        PF28MD_0, PF28MD_1,
+        PF27MD_0, PF27MD_1,
+        PF26MD_0, PF26MD_1,
+        PF25MD_0, PF25MD_1,
+        PF24MD_0, PF24MD_1,
+        PF23MD_00, PF23MD_01, PF23MD_10,
+        PF22MD_00, PF22MD_01, PF22MD_10,
+        PF21MD_00, PF21MD_01, PF21MD_10,
+        PF20MD_00, PF20MD_01, PF20MD_10,
+        PF19MD_00, PF19MD_01, PF19MD_10,
+        PF18MD_00, PF18MD_01, PF18MD_10,
+        PF17MD_00, PF17MD_01, PF17MD_10,
+        PF16MD_00, PF16MD_01, PF16MD_10,
+        PF15MD_00, PF15MD_01, PF15MD_10,
+        PF14MD_00, PF14MD_01, PF14MD_10,
+        PF13MD_00, PF13MD_01, PF13MD_10,
+        PF12MD_00, PF12MD_01, PF12MD_10,
+        PF11MD_00, PF11MD_01, PF11MD_10,
+        PF10MD_00, PF10MD_01, PF10MD_10,
+        PF9MD_00, PF9MD_01, PF9MD_10,
+        PF8MD_00, PF8MD_01, PF8MD_10,
+        PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
+        PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11,
+        PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11,
+        PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
+        PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
+        PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11,
+        PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11,
+        PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        PINT7_PB_MARK, PINT6_PB_MARK, PINT5_PB_MARK, PINT4_PB_MARK,
+        PINT3_PB_MARK, PINT2_PB_MARK, PINT1_PB_MARK, PINT0_PB_MARK,
+        PINT7_PD_MARK, PINT6_PD_MARK, PINT5_PD_MARK, PINT4_PD_MARK,
+        PINT3_PD_MARK, PINT2_PD_MARK, PINT1_PD_MARK, PINT0_PD_MARK,
+        IRQ7_PB_MARK, IRQ6_PB_MARK, IRQ5_PB_MARK, IRQ4_PB_MARK,
+        IRQ3_PB_MARK, IRQ2_PB_MARK, IRQ1_PB_MARK, IRQ0_PB_MARK,
+        IRQ7_PD_MARK, IRQ6_PD_MARK, IRQ5_PD_MARK, IRQ4_PD_MARK,
+        IRQ3_PD_MARK, IRQ2_PD_MARK, IRQ1_PD_MARK, IRQ0_PD_MARK,
+        IRQ7_PE_MARK, IRQ6_PE_MARK, IRQ5_PE_MARK, IRQ4_PE_MARK,
+        IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
+        WDTOVF_MARK, IRQOUT_MARK, REFOUT_MARK, IRQOUT_REFOUT_MARK,
+        UBCTRG_MARK,
+        CTX1_MARK, CRX1_MARK, CTX0_MARK, CTX0_CTX1_MARK,
+        CRX0_MARK, CRX0_CRX1_MARK,
+        SDA3_MARK, SCL3_MARK,
+        SDA2_MARK, SCL2_MARK,
+        SDA1_MARK, SCL1_MARK,
+        SDA0_MARK, SCL0_MARK,
+        TEND0_PD_MARK, TEND0_PE_MARK, DACK0_PD_MARK, DACK0_PE_MARK,
+        DREQ0_PD_MARK, DREQ0_PE_MARK, TEND1_PD_MARK, TEND1_PE_MARK,
+        DACK1_PD_MARK, DACK1_PE_MARK, DREQ1_PD_MARK, DREQ1_PE_MARK,
+        DACK2_MARK, DREQ2_MARK, DACK3_MARK, DREQ3_MARK,
+        ADTRG_PD_MARK, ADTRG_PE_MARK,
+        D31_MARK, D30_MARK, D29_MARK, D28_MARK,
+        D27_MARK, D26_MARK, D25_MARK, D24_MARK,
+        D23_MARK, D22_MARK, D21_MARK, D20_MARK,
+        D19_MARK, D18_MARK, D17_MARK, D16_MARK,
+        A25_MARK, A24_MARK, A23_MARK, A22_MARK,
+        A21_MARK, CS4_MARK, MRES_MARK, BS_MARK,
+        IOIS16_MARK, CS1_MARK, CS6_CE1B_MARK, CE2B_MARK,
+        CS5_CE1A_MARK, CE2A_MARK, FRAME_MARK, WAIT_MARK,
+        RDWR_MARK, CKE_MARK, CASU_MARK, BREQ_MARK,
+        RASU_MARK, BACK_MARK, CASL_MARK, RASL_MARK,
+        WE3_DQMUU_AH_ICIO_WR_MARK, WE2_DQMUL_ICIORD_MARK,
+        WE1_DQMLU_WE_MARK, WE0_DQMLL_MARK,
+        CS3_MARK, CS2_MARK, A1_MARK, A0_MARK, CS7_MARK,
+        TIOC4D_MARK, TIOC4C_MARK, TIOC4B_MARK, TIOC4A_MARK,
+        TIOC3D_MARK, TIOC3C_MARK, TIOC3B_MARK, TIOC3A_MARK,
+        TIOC2B_MARK, TIOC1B_MARK, TIOC2A_MARK, TIOC1A_MARK,
+        TIOC0D_MARK, TIOC0C_MARK, TIOC0B_MARK, TIOC0A_MARK,
+        TCLKD_PD_MARK, TCLKC_PD_MARK, TCLKB_PD_MARK, TCLKA_PD_MARK,
+        TCLKD_PF_MARK, TCLKC_PF_MARK, TCLKB_PF_MARK, TCLKA_PF_MARK,
+        SCS0_PD_MARK, SSO0_PD_MARK, SSI0_PD_MARK, SSCK0_PD_MARK,
+        SCS0_PF_MARK, SSO0_PF_MARK, SSI0_PF_MARK, SSCK0_PF_MARK,
+        SCS1_PD_MARK, SSO1_PD_MARK, SSI1_PD_MARK, SSCK1_PD_MARK,
+        SCS1_PF_MARK, SSO1_PF_MARK, SSI1_PF_MARK, SSCK1_PF_MARK,
+        TXD0_MARK, RXD0_MARK, SCK0_MARK,
+        TXD1_MARK, RXD1_MARK, SCK1_MARK,
+        TXD2_MARK, RXD2_MARK, SCK2_MARK,
+        RTS3_MARK, CTS3_MARK, TXD3_MARK,
+        RXD3_MARK, SCK3_MARK,
+        AUDIO_CLK_MARK,
+        SSIDATA3_MARK, SSIWS3_MARK, SSISCK3_MARK,
+        SSIDATA2_MARK, SSIWS2_MARK, SSISCK2_MARK,
+        SSIDATA1_MARK, SSIWS1_MARK, SSISCK1_MARK,
+        SSIDATA0_MARK, SSIWS0_MARK, SSISCK0_MARK,
+        FCE_MARK, FRB_MARK,
+        NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
+        NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK,
+        FSC_MARK, FOE_MARK, FCDE_MARK, FWE_MARK,
+        LCD_VEPWC_MARK, LCD_VCPWC_MARK, LCD_CLK_MARK, LCD_FLM_MARK,
+        LCD_M_DISP_MARK, LCD_CL2_MARK, LCD_CL1_MARK, LCD_DON_MARK,
+        LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
+        LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
+        LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
+        LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+
+        /* PA */
+        PINMUX_DATA(PA7_DATA, PA7_IN),
+        PINMUX_DATA(PA6_DATA, PA6_IN),
+        PINMUX_DATA(PA5_DATA, PA5_IN),
+        PINMUX_DATA(PA4_DATA, PA4_IN),
+        PINMUX_DATA(PA3_DATA, PA3_IN),
+        PINMUX_DATA(PA2_DATA, PA2_IN),
+        PINMUX_DATA(PA1_DATA, PA1_IN),
+        PINMUX_DATA(PA0_DATA, PA0_IN),
+
+        /* PB */
+        PINMUX_DATA(PB12_DATA, PB12MD_00, PB12_OUT),
+        PINMUX_DATA(WDTOVF_MARK, PB12MD_01),
+        PINMUX_DATA(IRQOUT_MARK, PB12MD_10, PB12IRQ_00),
+        PINMUX_DATA(REFOUT_MARK, PB12MD_10, PB12IRQ_01),
+        PINMUX_DATA(IRQOUT_REFOUT_MARK, PB12MD_10, PB12IRQ_10),
+        PINMUX_DATA(UBCTRG_MARK, PB12MD_11),
+
+        PINMUX_DATA(PB11_DATA, PB11MD_0, PB11_IN, PB11_OUT),
+        PINMUX_DATA(CTX1_MARK, PB11MD_1),
+
+        PINMUX_DATA(PB10_DATA, PB10MD_0, PB10_IN, PB10_OUT),
+        PINMUX_DATA(CRX1_MARK, PB10MD_1),
+
+        PINMUX_DATA(PB9_DATA, PB9MD_00, PB9_IN, PB9_OUT),
+        PINMUX_DATA(CTX0_MARK, PB9MD_01),
+        PINMUX_DATA(CTX0_CTX1_MARK, PB9MD_10),
+
+        PINMUX_DATA(PB8_DATA, PB8MD_00, PB8_IN, PB8_OUT),
+        PINMUX_DATA(CRX0_MARK, PB8MD_01),
+        PINMUX_DATA(CRX0_CRX1_MARK, PB8MD_10),
+
+        PINMUX_DATA(PB7_DATA, PB7MD_00, PB7_IN),
+        PINMUX_DATA(SDA3_MARK, PB7MD_01),
+        PINMUX_DATA(PINT7_PB_MARK, PB7MD_10),
+        PINMUX_DATA(IRQ7_PB_MARK, PB7MD_11),
+
+        PINMUX_DATA(PB6_DATA, PB6MD_00, PB6_IN),
+        PINMUX_DATA(SCL3_MARK, PB6MD_01),
+        PINMUX_DATA(PINT6_PB_MARK, PB6MD_10),
+        PINMUX_DATA(IRQ6_PB_MARK, PB6MD_11),
+
+        PINMUX_DATA(PB5_DATA, PB5MD_00, PB5_IN),
+        PINMUX_DATA(SDA2_MARK, PB6MD_01),
+        PINMUX_DATA(PINT5_PB_MARK, PB6MD_10),
+        PINMUX_DATA(IRQ5_PB_MARK, PB6MD_11),
+
+        PINMUX_DATA(PB4_DATA, PB4MD_00, PB4_IN),
+        PINMUX_DATA(SCL2_MARK, PB4MD_01),
+        PINMUX_DATA(PINT4_PB_MARK, PB4MD_10),
+        PINMUX_DATA(IRQ4_PB_MARK, PB4MD_11),
+
+        PINMUX_DATA(PB3_DATA, PB3MD_00, PB3_IN),
+        PINMUX_DATA(SDA1_MARK, PB3MD_01),
+        PINMUX_DATA(PINT3_PB_MARK, PB3MD_10),
+        PINMUX_DATA(IRQ3_PB_MARK, PB3MD_11),
+
+        PINMUX_DATA(PB2_DATA, PB2MD_00, PB2_IN),
+        PINMUX_DATA(SCL1_MARK, PB2MD_01),
+        PINMUX_DATA(PINT2_PB_MARK, PB2MD_10),
+        PINMUX_DATA(IRQ2_PB_MARK, PB2MD_11),
+
+        PINMUX_DATA(PB1_DATA, PB1MD_00, PB1_IN),
+        PINMUX_DATA(SDA0_MARK, PB1MD_01),
+        PINMUX_DATA(PINT1_PB_MARK, PB1MD_10),
+        PINMUX_DATA(IRQ1_PB_MARK, PB1MD_11),
+
+        PINMUX_DATA(PB0_DATA, PB0MD_00, PB0_IN),
+        PINMUX_DATA(SCL0_MARK, PB0MD_01),
+        PINMUX_DATA(PINT0_PB_MARK, PB0MD_10),
+        PINMUX_DATA(IRQ0_PB_MARK, PB0MD_11),
+
+        /* PC */
+        PINMUX_DATA(PC14_DATA, PC14MD_0, PC14_IN, PC14_OUT),
+        PINMUX_DATA(WAIT_MARK, PC14MD_1),
+
+        PINMUX_DATA(PC13_DATA, PC13MD_0, PC13_IN, PC13_OUT),
+        PINMUX_DATA(RDWR_MARK, PC13MD_1),
+
+        PINMUX_DATA(PC12_DATA, PC12MD_0, PC12_IN, PC12_OUT),
+        PINMUX_DATA(CKE_MARK, PC12MD_1),
+
+        PINMUX_DATA(PC11_DATA, PC11MD_00, PC11_IN, PC11_OUT),
+        PINMUX_DATA(CASU_MARK, PC11MD_01),
+        PINMUX_DATA(BREQ_MARK, PC11MD_10),
+
+        PINMUX_DATA(PC10_DATA, PC10MD_00, PC10_IN, PC10_OUT),
+        PINMUX_DATA(RASU_MARK, PC10MD_01),
+        PINMUX_DATA(BACK_MARK, PC10MD_10),
+
+        PINMUX_DATA(PC9_DATA, PC9MD_0, PC9_IN, PC9_OUT),
+        PINMUX_DATA(CASL_MARK, PC9MD_1),
+
+        PINMUX_DATA(PC8_DATA, PC8MD_0, PC8_IN, PC8_OUT),
+        PINMUX_DATA(RASL_MARK, PC8MD_1),
+
+        PINMUX_DATA(PC7_DATA, PC7MD_0, PC7_IN, PC7_OUT),
+        PINMUX_DATA(WE3_DQMUU_AH_ICIO_WR_MARK, PC7MD_1),
+
+        PINMUX_DATA(PC6_DATA, PC6MD_0, PC6_IN, PC6_OUT),
+        PINMUX_DATA(WE2_DQMUL_ICIORD_MARK, PC6MD_1),
+
+        PINMUX_DATA(PC5_DATA, PC5MD_0, PC5_IN, PC5_OUT),
+        PINMUX_DATA(WE1_DQMLU_WE_MARK, PC5MD_1),
+
+        PINMUX_DATA(PC4_DATA, PC4MD_0, PC4_IN, PC4_OUT),
+        PINMUX_DATA(WE0_DQMLL_MARK, PC4MD_1),
+
+        PINMUX_DATA(PC3_DATA, PC3MD_0, PC3_IN, PC3_OUT),
+        PINMUX_DATA(CS3_MARK, PC3MD_1),
+
+        PINMUX_DATA(PC2_DATA, PC2MD_0, PC2_IN, PC2_OUT),
+        PINMUX_DATA(CS2_MARK, PC2MD_1),
+
+        PINMUX_DATA(PC1_DATA, PC1MD_0, PC1_IN, PC1_OUT),
+        PINMUX_DATA(A1_MARK, PC1MD_1),
+
+        PINMUX_DATA(PC0_DATA, PC0MD_00, PC0_IN, PC0_OUT),
+        PINMUX_DATA(A0_MARK, PC0MD_01),
+        PINMUX_DATA(CS7_MARK, PC0MD_10),
+
+        /* PD */
+        PINMUX_DATA(PD15_DATA, PD15MD_000, PD15_IN, PD15_OUT),
+        PINMUX_DATA(D31_MARK, PD15MD_001),
+        PINMUX_DATA(PINT7_PD_MARK, PD15MD_010),
+        PINMUX_DATA(ADTRG_PD_MARK, PD15MD_100),
+        PINMUX_DATA(TIOC4D_MARK, PD15MD_101),
+
+        PINMUX_DATA(PD14_DATA, PD14MD_000, PD14_IN, PD14_OUT),
+        PINMUX_DATA(D30_MARK, PD14MD_001),
+        PINMUX_DATA(PINT6_PD_MARK, PD14MD_010),
+        PINMUX_DATA(TIOC4C_MARK, PD14MD_101),
+
+        PINMUX_DATA(PD13_DATA, PD13MD_000, PD13_IN, PD13_OUT),
+        PINMUX_DATA(D29_MARK, PD13MD_001),
+        PINMUX_DATA(PINT5_PD_MARK, PD13MD_010),
+        PINMUX_DATA(TEND1_PD_MARK, PD13MD_100),
+        PINMUX_DATA(TIOC4B_MARK, PD13MD_101),
+
+        PINMUX_DATA(PD12_DATA, PD12MD_000, PD12_IN, PD12_OUT),
+        PINMUX_DATA(D28_MARK, PD12MD_001),
+        PINMUX_DATA(PINT4_PD_MARK, PD12MD_010),
+        PINMUX_DATA(DACK1_PD_MARK, PD12MD_100),
+        PINMUX_DATA(TIOC4A_MARK, PD12MD_101),
+
+        PINMUX_DATA(PD11_DATA, PD11MD_000, PD11_IN, PD11_OUT),
+        PINMUX_DATA(D27_MARK, PD11MD_001),
+        PINMUX_DATA(PINT3_PD_MARK, PD11MD_010),
+        PINMUX_DATA(DREQ1_PD_MARK, PD11MD_100),
+        PINMUX_DATA(TIOC3D_MARK, PD11MD_101),
+
+        PINMUX_DATA(PD10_DATA, PD10MD_000, PD10_IN, PD10_OUT),
+        PINMUX_DATA(D26_MARK, PD10MD_001),
+        PINMUX_DATA(PINT2_PD_MARK, PD10MD_010),
+        PINMUX_DATA(TEND0_PD_MARK, PD10MD_100),
+        PINMUX_DATA(TIOC3C_MARK, PD10MD_101),
+
+        PINMUX_DATA(PD9_DATA, PD9MD_000, PD9_IN, PD9_OUT),
+        PINMUX_DATA(D25_MARK, PD9MD_001),
+        PINMUX_DATA(PINT1_PD_MARK, PD9MD_010),
+        PINMUX_DATA(DACK0_PD_MARK, PD9MD_100),
+        PINMUX_DATA(TIOC3B_MARK, PD9MD_101),
+
+        PINMUX_DATA(PD8_DATA, PD8MD_000, PD8_IN, PD8_OUT),
+        PINMUX_DATA(D24_MARK, PD8MD_001),
+        PINMUX_DATA(PINT0_PD_MARK, PD8MD_010),
+        PINMUX_DATA(DREQ0_PD_MARK, PD8MD_100),
+        PINMUX_DATA(TIOC3A_MARK, PD8MD_101),
+
+        PINMUX_DATA(PD7_DATA, PD7MD_000, PD7_IN, PD7_OUT),
+        PINMUX_DATA(D23_MARK, PD7MD_001),
+        PINMUX_DATA(IRQ7_PD_MARK, PD7MD_010),
+        PINMUX_DATA(SCS1_PD_MARK, PD7MD_011),
+        PINMUX_DATA(TCLKD_PD_MARK, PD7MD_100),
+        PINMUX_DATA(TIOC2B_MARK, PD7MD_101),
+
+        PINMUX_DATA(PD6_DATA, PD6MD_000, PD6_IN, PD6_OUT),
+        PINMUX_DATA(D22_MARK, PD6MD_001),
+        PINMUX_DATA(IRQ6_PD_MARK, PD6MD_010),
+        PINMUX_DATA(SSO1_PD_MARK, PD6MD_011),
+        PINMUX_DATA(TCLKC_PD_MARK, PD6MD_100),
+        PINMUX_DATA(TIOC2A_MARK, PD6MD_101),
+
+        PINMUX_DATA(PD5_DATA, PD5MD_000, PD5_IN, PD5_OUT),
+        PINMUX_DATA(D21_MARK, PD5MD_001),
+        PINMUX_DATA(IRQ5_PD_MARK, PD5MD_010),
+        PINMUX_DATA(SSI1_PD_MARK, PD5MD_011),
+        PINMUX_DATA(TCLKB_PD_MARK, PD5MD_100),
+        PINMUX_DATA(TIOC1B_MARK, PD5MD_101),
+
+        PINMUX_DATA(PD4_DATA, PD4MD_000, PD4_IN, PD4_OUT),
+        PINMUX_DATA(D20_MARK, PD4MD_001),
+        PINMUX_DATA(IRQ4_PD_MARK, PD4MD_010),
+        PINMUX_DATA(SSCK1_PD_MARK, PD4MD_011),
+        PINMUX_DATA(TCLKA_PD_MARK, PD4MD_100),
+        PINMUX_DATA(TIOC1A_MARK, PD4MD_101),
+
+        PINMUX_DATA(PD3_DATA, PD3MD_000, PD3_IN, PD3_OUT),
+        PINMUX_DATA(D19_MARK, PD3MD_001),
+        PINMUX_DATA(IRQ3_PD_MARK, PD3MD_010),
+        PINMUX_DATA(SCS0_PD_MARK, PD3MD_011),
+        PINMUX_DATA(DACK3_MARK, PD3MD_100),
+        PINMUX_DATA(TIOC0D_MARK, PD3MD_101),
+
+        PINMUX_DATA(PD2_DATA, PD2MD_000, PD2_IN, PD2_OUT),
+        PINMUX_DATA(D18_MARK, PD2MD_001),
+        PINMUX_DATA(IRQ2_PD_MARK, PD2MD_010),
+        PINMUX_DATA(SSO0_PD_MARK, PD2MD_011),
+        PINMUX_DATA(DREQ3_MARK, PD2MD_100),
+        PINMUX_DATA(TIOC0C_MARK, PD2MD_101),
+
+        PINMUX_DATA(PD1_DATA, PD1MD_000, PD1_IN, PD1_OUT),
+        PINMUX_DATA(D17_MARK, PD1MD_001),
+        PINMUX_DATA(IRQ1_PD_MARK, PD1MD_010),
+        PINMUX_DATA(SSI0_PD_MARK, PD1MD_011),
+        PINMUX_DATA(DACK2_MARK, PD1MD_100),
+        PINMUX_DATA(TIOC0B_MARK, PD1MD_101),
+
+        PINMUX_DATA(PD0_DATA, PD0MD_000, PD0_IN, PD0_OUT),
+        PINMUX_DATA(D16_MARK, PD0MD_001),
+        PINMUX_DATA(IRQ0_PD_MARK, PD0MD_010),
+        PINMUX_DATA(SSCK0_PD_MARK, PD0MD_011),
+        PINMUX_DATA(DREQ2_MARK, PD0MD_100),
+        PINMUX_DATA(TIOC0A_MARK, PD0MD_101),
+
+        /* PE */
+        PINMUX_DATA(PE15_DATA, PE15MD_00, PE15_IN, PE15_OUT),
+        PINMUX_DATA(IOIS16_MARK, PE15MD_01),
+        PINMUX_DATA(RTS3_MARK, PE15MD_11),
+
+        PINMUX_DATA(PE14_DATA, PE14MD_00, PE14_IN, PE14_OUT),
+        PINMUX_DATA(CS1_MARK, PE14MD_01),
+        PINMUX_DATA(CTS3_MARK, PE14MD_11),
+
+        PINMUX_DATA(PE13_DATA, PE13MD_00, PE13_IN, PE13_OUT),
+        PINMUX_DATA(TXD3_MARK, PE13MD_11),
+
+        PINMUX_DATA(PE12_DATA, PE12MD_00, PE12_IN, PE12_OUT),
+        PINMUX_DATA(RXD3_MARK, PE12MD_11),
+
+        PINMUX_DATA(PE11_DATA, PE11MD_000, PE11_IN, PE11_OUT),
+        PINMUX_DATA(CS6_CE1B_MARK, PE11MD_001),
+        PINMUX_DATA(IRQ7_PE_MARK, PE11MD_010),
+        PINMUX_DATA(TEND1_PE_MARK, PE11MD_100),
+
+        PINMUX_DATA(PE10_DATA, PE10MD_000, PE10_IN, PE10_OUT),
+        PINMUX_DATA(CE2B_MARK, PE10MD_001),
+        PINMUX_DATA(IRQ6_PE_MARK, PE10MD_010),
+        PINMUX_DATA(TEND0_PE_MARK, PE10MD_100),
+
+        PINMUX_DATA(PE9_DATA, PE9MD_00, PE9_IN, PE9_OUT),
+        PINMUX_DATA(CS5_CE1A_MARK, PE9MD_01),
+        PINMUX_DATA(IRQ5_PE_MARK, PE9MD_10),
+        PINMUX_DATA(SCK3_MARK, PE9MD_11),
+
+        PINMUX_DATA(PE8_DATA, PE8MD_00, PE8_IN, PE8_OUT),
+        PINMUX_DATA(CE2A_MARK, PE8MD_01),
+        PINMUX_DATA(IRQ4_PE_MARK, PE8MD_10),
+        PINMUX_DATA(SCK2_MARK, PE8MD_11),
+
+        PINMUX_DATA(PE7_DATA, PE7MD_000, PE7_IN, PE7_OUT),
+        PINMUX_DATA(FRAME_MARK, PE7MD_001),
+        PINMUX_DATA(IRQ3_PE_MARK, PE7MD_010),
+        PINMUX_DATA(TXD2_MARK, PE7MD_011),
+        PINMUX_DATA(DACK1_PE_MARK, PE7MD_100),
+
+        PINMUX_DATA(PE6_DATA, PE6MD_000, PE6_IN, PE6_OUT),
+        PINMUX_DATA(A25_MARK, PE6MD_001),
+        PINMUX_DATA(IRQ2_PE_MARK, PE6MD_010),
+        PINMUX_DATA(RXD2_MARK, PE6MD_011),
+        PINMUX_DATA(DREQ1_PE_MARK, PE6MD_100),
+
+        PINMUX_DATA(PE5_DATA, PE5MD_000, PE5_IN, PE5_OUT),
+        PINMUX_DATA(A24_MARK, PE5MD_001),
+        PINMUX_DATA(IRQ1_PE_MARK, PE5MD_010),
+        PINMUX_DATA(TXD1_MARK, PE5MD_011),
+        PINMUX_DATA(DACK0_PE_MARK, PE5MD_100),
+
+        PINMUX_DATA(PE4_DATA, PE4MD_000, PE4_IN, PE4_OUT),
+        PINMUX_DATA(A23_MARK, PE4MD_001),
+        PINMUX_DATA(IRQ0_PE_MARK, PE4MD_010),
+        PINMUX_DATA(RXD1_MARK, PE4MD_011),
+        PINMUX_DATA(DREQ0_PE_MARK, PE4MD_100),
+
+        PINMUX_DATA(PE3_DATA, PE3MD_00, PE3_IN, PE3_OUT),
+        PINMUX_DATA(A22_MARK, PE3MD_01),
+        PINMUX_DATA(SCK1_MARK, PE3MD_11),
+
+        PINMUX_DATA(PE2_DATA, PE2MD_00, PE2_IN, PE2_OUT),
+        PINMUX_DATA(A21_MARK, PE2MD_01),
+        PINMUX_DATA(SCK0_MARK, PE2MD_11),
+
+        PINMUX_DATA(PE1_DATA, PE1MD_00, PE1_IN, PE1_OUT),
+        PINMUX_DATA(CS4_MARK, PE1MD_01),
+        PINMUX_DATA(MRES_MARK, PE1MD_10),
+        PINMUX_DATA(TXD0_MARK, PE1MD_11),
+
+        PINMUX_DATA(PE0_DATA, PE0MD_000, PE0_IN, PE0_OUT),
+        PINMUX_DATA(BS_MARK, PE0MD_001),
+        PINMUX_DATA(RXD0_MARK, PE0MD_011),
+        PINMUX_DATA(ADTRG_PE_MARK, PE0MD_100),
+
+        /* PF */
+        PINMUX_DATA(PF30_DATA, PF30MD_0, PF30_IN, PF30_OUT),
+        PINMUX_DATA(AUDIO_CLK_MARK, PF30MD_1),
+
+        PINMUX_DATA(PF29_DATA, PF29MD_0, PF29_IN, PF29_OUT),
+        PINMUX_DATA(SSIDATA3_MARK, PF29MD_1),
+
+        PINMUX_DATA(PF28_DATA, PF28MD_0, PF28_IN, PF28_OUT),
+        PINMUX_DATA(SSIWS3_MARK, PF28MD_1),
+
+        PINMUX_DATA(PF27_DATA, PF27MD_0, PF27_IN, PF27_OUT),
+        PINMUX_DATA(SSISCK3_MARK, PF27MD_1),
+
+        PINMUX_DATA(PF26_DATA, PF26MD_0, PF26_IN, PF26_OUT),
+        PINMUX_DATA(SSIDATA2_MARK, PF26MD_1),
+
+        PINMUX_DATA(PF25_DATA, PF25MD_0, PF25_IN, PF25_OUT),
+        PINMUX_DATA(SSIWS2_MARK, PF25MD_1),
+
+        PINMUX_DATA(PF24_DATA, PF24MD_0, PF24_IN, PF24_OUT),
+        PINMUX_DATA(SSISCK2_MARK, PF24MD_1),
+
+        PINMUX_DATA(PF23_DATA, PF23MD_00, PF23_IN, PF23_OUT),
+        PINMUX_DATA(SSIDATA1_MARK, PF23MD_01),
+        PINMUX_DATA(LCD_VEPWC_MARK, PF23MD_10),
+
+        PINMUX_DATA(PF22_DATA, PF22MD_00, PF22_IN, PF22_OUT),
+        PINMUX_DATA(SSIWS1_MARK, PF22MD_01),
+        PINMUX_DATA(LCD_VCPWC_MARK, PF22MD_10),
+
+        PINMUX_DATA(PF21_DATA, PF21MD_00, PF21_IN, PF21_OUT),
+        PINMUX_DATA(SSISCK1_MARK, PF21MD_01),
+        PINMUX_DATA(LCD_CLK_MARK, PF21MD_10),
+
+        PINMUX_DATA(PF20_DATA, PF20MD_00, PF20_IN, PF20_OUT),
+        PINMUX_DATA(SSIDATA0_MARK, PF20MD_01),
+        PINMUX_DATA(LCD_FLM_MARK, PF20MD_10),
+
+        PINMUX_DATA(PF19_DATA, PF19MD_00, PF19_IN, PF19_OUT),
+        PINMUX_DATA(SSIWS0_MARK, PF19MD_01),
+        PINMUX_DATA(LCD_M_DISP_MARK, PF19MD_10),
+
+        PINMUX_DATA(PF18_DATA, PF18MD_00, PF18_IN, PF18_OUT),
+        PINMUX_DATA(SSISCK0_MARK, PF18MD_01),
+        PINMUX_DATA(LCD_CL2_MARK, PF18MD_10),
+
+        PINMUX_DATA(PF17_DATA, PF17MD_00, PF17_IN, PF17_OUT),
+        PINMUX_DATA(FCE_MARK, PF17MD_01),
+        PINMUX_DATA(LCD_CL1_MARK, PF17MD_10),
+
+        PINMUX_DATA(PF16_DATA, PF16MD_00, PF16_IN, PF16_OUT),
+        PINMUX_DATA(FRB_MARK, PF16MD_01),
+        PINMUX_DATA(LCD_DON_MARK, PF16MD_10),
+
+        PINMUX_DATA(PF15_DATA, PF15MD_00, PF15_IN, PF15_OUT),
+        PINMUX_DATA(NAF7_MARK, PF15MD_01),
+        PINMUX_DATA(LCD_DATA15_MARK, PF15MD_10),
+
+        PINMUX_DATA(PF14_DATA, PF14MD_00, PF14_IN, PF14_OUT),
+        PINMUX_DATA(NAF6_MARK, PF14MD_01),
+        PINMUX_DATA(LCD_DATA14_MARK, PF14MD_10),
+
+        PINMUX_DATA(PF13_DATA, PF13MD_00, PF13_IN, PF13_OUT),
+        PINMUX_DATA(NAF5_MARK, PF13MD_01),
+        PINMUX_DATA(LCD_DATA13_MARK, PF13MD_10),
+
+        PINMUX_DATA(PF12_DATA, PF12MD_00, PF12_IN, PF12_OUT),
+        PINMUX_DATA(NAF4_MARK, PF12MD_01),
+        PINMUX_DATA(LCD_DATA12_MARK, PF12MD_10),
+
+        PINMUX_DATA(PF11_DATA, PF11MD_00, PF11_IN, PF11_OUT),
+        PINMUX_DATA(NAF3_MARK, PF11MD_01),
+        PINMUX_DATA(LCD_DATA11_MARK, PF11MD_10),
+
+        PINMUX_DATA(PF10_DATA, PF10MD_00, PF10_IN, PF10_OUT),
+        PINMUX_DATA(NAF2_MARK, PF10MD_01),
+        PINMUX_DATA(LCD_DATA10_MARK, PF10MD_10),
+
+        PINMUX_DATA(PF9_DATA, PF9MD_00, PF9_IN, PF9_OUT),
+        PINMUX_DATA(NAF1_MARK, PF9MD_01),
+        PINMUX_DATA(LCD_DATA9_MARK, PF9MD_10),
+
+        PINMUX_DATA(PF8_DATA, PF8MD_00, PF8_IN, PF8_OUT),
+        PINMUX_DATA(NAF0_MARK, PF8MD_01),
+        PINMUX_DATA(LCD_DATA8_MARK, PF8MD_10),
+
+        PINMUX_DATA(PF7_DATA, PF7MD_00, PF7_IN, PF7_OUT),
+        PINMUX_DATA(FSC_MARK, PF7MD_01),
+        PINMUX_DATA(LCD_DATA7_MARK, PF7MD_10),
+        PINMUX_DATA(SCS1_PF_MARK, PF7MD_11),
+
+        PINMUX_DATA(PF6_DATA, PF6MD_00, PF6_IN, PF6_OUT),
+        PINMUX_DATA(FOE_MARK, PF6MD_01),
+        PINMUX_DATA(LCD_DATA6_MARK, PF6MD_10),
+        PINMUX_DATA(SSO1_PF_MARK, PF6MD_11),
+
+        PINMUX_DATA(PF5_DATA, PF5MD_00, PF5_IN, PF5_OUT),
+        PINMUX_DATA(FCDE_MARK, PF5MD_01),
+        PINMUX_DATA(LCD_DATA5_MARK, PF5MD_10),
+        PINMUX_DATA(SSI1_PF_MARK, PF5MD_11),
+
+        PINMUX_DATA(PF4_DATA, PF4MD_00, PF4_IN, PF4_OUT),
+        PINMUX_DATA(FWE_MARK, PF4MD_01),
+        PINMUX_DATA(LCD_DATA4_MARK, PF4MD_10),
+        PINMUX_DATA(SSCK1_PF_MARK, PF4MD_11),
+
+        PINMUX_DATA(PF3_DATA, PF3MD_00, PF3_IN, PF3_OUT),
+        PINMUX_DATA(TCLKD_PF_MARK, PF3MD_01),
+        PINMUX_DATA(LCD_DATA3_MARK, PF3MD_10),
+        PINMUX_DATA(SCS0_PF_MARK, PF3MD_11),
+
+        PINMUX_DATA(PF2_DATA, PF2MD_00, PF2_IN, PF2_OUT),
+        PINMUX_DATA(TCLKC_PF_MARK, PF2MD_01),
+        PINMUX_DATA(LCD_DATA2_MARK, PF2MD_10),
+        PINMUX_DATA(SSO0_PF_MARK, PF2MD_11),
+
+        PINMUX_DATA(PF1_DATA, PF1MD_00, PF1_IN, PF1_OUT),
+        PINMUX_DATA(TCLKB_PF_MARK, PF1MD_01),
+        PINMUX_DATA(LCD_DATA1_MARK, PF1MD_10),
+        PINMUX_DATA(SSI0_PF_MARK, PF1MD_11),
+
+        PINMUX_DATA(PF0_DATA, PF0MD_00, PF0_IN, PF0_OUT),
+        PINMUX_DATA(TCLKA_PF_MARK, PF0MD_01),
+        PINMUX_DATA(LCD_DATA0_MARK, PF0MD_10),
+        PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+
+        /* PA */
+        PINMUX_GPIO(GPIO_PA7, PA7_DATA),
+        PINMUX_GPIO(GPIO_PA6, PA6_DATA),
+        PINMUX_GPIO(GPIO_PA5, PA5_DATA),
+        PINMUX_GPIO(GPIO_PA4, PA4_DATA),
+        PINMUX_GPIO(GPIO_PA3, PA3_DATA),
+        PINMUX_GPIO(GPIO_PA2, PA2_DATA),
+        PINMUX_GPIO(GPIO_PA1, PA1_DATA),
+        PINMUX_GPIO(GPIO_PA0, PA0_DATA),
+
+        /* PB */
+        PINMUX_GPIO(GPIO_PB12, PB12_DATA),
+        PINMUX_GPIO(GPIO_PB11, PB11_DATA),
+        PINMUX_GPIO(GPIO_PB10, PB10_DATA),
+        PINMUX_GPIO(GPIO_PB9, PB9_DATA),
+        PINMUX_GPIO(GPIO_PB8, PB8_DATA),
+        PINMUX_GPIO(GPIO_PB7, PB7_DATA),
+        PINMUX_GPIO(GPIO_PB6, PB6_DATA),
+        PINMUX_GPIO(GPIO_PB5, PB5_DATA),
+        PINMUX_GPIO(GPIO_PB4, PB4_DATA),
+        PINMUX_GPIO(GPIO_PB3, PB3_DATA),
+        PINMUX_GPIO(GPIO_PB2, PB2_DATA),
+        PINMUX_GPIO(GPIO_PB1, PB1_DATA),
+        PINMUX_GPIO(GPIO_PB0, PB0_DATA),
+
+        /* PC */
+        PINMUX_GPIO(GPIO_PC14, PC14_DATA),
+        PINMUX_GPIO(GPIO_PC13, PC13_DATA),
+        PINMUX_GPIO(GPIO_PC12, PC12_DATA),
+        PINMUX_GPIO(GPIO_PC11, PC11_DATA),
+        PINMUX_GPIO(GPIO_PC10, PC10_DATA),
+        PINMUX_GPIO(GPIO_PC9, PC9_DATA),
+        PINMUX_GPIO(GPIO_PC8, PC8_DATA),
+        PINMUX_GPIO(GPIO_PC7, PC7_DATA),
+        PINMUX_GPIO(GPIO_PC6, PC6_DATA),
+        PINMUX_GPIO(GPIO_PC5, PC5_DATA),
+        PINMUX_GPIO(GPIO_PC4, PC4_DATA),
+        PINMUX_GPIO(GPIO_PC3, PC3_DATA),
+        PINMUX_GPIO(GPIO_PC2, PC2_DATA),
+        PINMUX_GPIO(GPIO_PC1, PC1_DATA),
+        PINMUX_GPIO(GPIO_PC0, PC0_DATA),
+
+        /* PD */
+        PINMUX_GPIO(GPIO_PD15, PD15_DATA),
+        PINMUX_GPIO(GPIO_PD14, PD14_DATA),
+        PINMUX_GPIO(GPIO_PD13, PD13_DATA),
+        PINMUX_GPIO(GPIO_PD12, PD12_DATA),
+        PINMUX_GPIO(GPIO_PD11, PD11_DATA),
+        PINMUX_GPIO(GPIO_PD10, PD10_DATA),
+        PINMUX_GPIO(GPIO_PD9, PD9_DATA),
+        PINMUX_GPIO(GPIO_PD8, PD8_DATA),
+        PINMUX_GPIO(GPIO_PD7, PD7_DATA),
+        PINMUX_GPIO(GPIO_PD6, PD6_DATA),
+        PINMUX_GPIO(GPIO_PD5, PD5_DATA),
+        PINMUX_GPIO(GPIO_PD4, PD4_DATA),
+        PINMUX_GPIO(GPIO_PD3, PD3_DATA),
+        PINMUX_GPIO(GPIO_PD2, PD2_DATA),
+        PINMUX_GPIO(GPIO_PD1, PD1_DATA),
+        PINMUX_GPIO(GPIO_PD0, PD0_DATA),
+
+        /* PE */
+        PINMUX_GPIO(GPIO_PE15, PE15_DATA),
+        PINMUX_GPIO(GPIO_PE14, PE14_DATA),
+        PINMUX_GPIO(GPIO_PE13, PE13_DATA),
+        PINMUX_GPIO(GPIO_PE12, PE12_DATA),
+        PINMUX_GPIO(GPIO_PE11, PE11_DATA),
+        PINMUX_GPIO(GPIO_PE10, PE10_DATA),
+        PINMUX_GPIO(GPIO_PE9, PE9_DATA),
+        PINMUX_GPIO(GPIO_PE8, PE8_DATA),
+        PINMUX_GPIO(GPIO_PE7, PE7_DATA),
+        PINMUX_GPIO(GPIO_PE6, PE6_DATA),
+        PINMUX_GPIO(GPIO_PE5, PE5_DATA),
+        PINMUX_GPIO(GPIO_PE4, PE4_DATA),
+        PINMUX_GPIO(GPIO_PE3, PE3_DATA),
+        PINMUX_GPIO(GPIO_PE2, PE2_DATA),
+        PINMUX_GPIO(GPIO_PE1, PE1_DATA),
+        PINMUX_GPIO(GPIO_PE0, PE0_DATA),
+
+        /* PF */
+        PINMUX_GPIO(GPIO_PF30, PF30_DATA),
+        PINMUX_GPIO(GPIO_PF29, PF29_DATA),
+        PINMUX_GPIO(GPIO_PF28, PF28_DATA),
+        PINMUX_GPIO(GPIO_PF27, PF27_DATA),
+        PINMUX_GPIO(GPIO_PF26, PF26_DATA),
+        PINMUX_GPIO(GPIO_PF25, PF25_DATA),
+        PINMUX_GPIO(GPIO_PF24, PF24_DATA),
+        PINMUX_GPIO(GPIO_PF23, PF23_DATA),
+        PINMUX_GPIO(GPIO_PF22, PF22_DATA),
+        PINMUX_GPIO(GPIO_PF21, PF21_DATA),
+        PINMUX_GPIO(GPIO_PF20, PF20_DATA),
+        PINMUX_GPIO(GPIO_PF19, PF19_DATA),
+        PINMUX_GPIO(GPIO_PF18, PF18_DATA),
+        PINMUX_GPIO(GPIO_PF17, PF17_DATA),
+        PINMUX_GPIO(GPIO_PF16, PF16_DATA),
+        PINMUX_GPIO(GPIO_PF15, PF15_DATA),
+        PINMUX_GPIO(GPIO_PF14, PF14_DATA),
+        PINMUX_GPIO(GPIO_PF13, PF13_DATA),
+        PINMUX_GPIO(GPIO_PF12, PF12_DATA),
+        PINMUX_GPIO(GPIO_PF11, PF11_DATA),
+        PINMUX_GPIO(GPIO_PF10, PF10_DATA),
+        PINMUX_GPIO(GPIO_PF9, PF9_DATA),
+        PINMUX_GPIO(GPIO_PF8, PF8_DATA),
+        PINMUX_GPIO(GPIO_PF7, PF7_DATA),
+        PINMUX_GPIO(GPIO_PF6, PF6_DATA),
+        PINMUX_GPIO(GPIO_PF5, PF5_DATA),
+        PINMUX_GPIO(GPIO_PF4, PF4_DATA),
+        PINMUX_GPIO(GPIO_PF3, PF3_DATA),
+        PINMUX_GPIO(GPIO_PF2, PF2_DATA),
+        PINMUX_GPIO(GPIO_PF1, PF1_DATA),
+        PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+
+        /* INTC */
+        PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
+
+        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK),
+
+        /* CAN */
+        PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
+        PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
+        PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
+        PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK),
+        PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
+        PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
+
+        /* IIC3 */
+        PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
+
+        /* ADC */
+        PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK),
+
+        /* BSC */
+        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
+        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK),
+        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK),
+        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
+        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
+        PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK),
+        PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK),
+        PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
+        PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK),
+        PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK),
+        PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK),
+        PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK),
+        PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK),
+        PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
+        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
+        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
+        PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK),
+
+        /* TMU */
+        PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK),
+
+        /* SSU */
+        PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK),
+        PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK),
+
+        /* SCIF */
+        PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+
+        /* SSI */
+        PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
+
+        /* FLCTL */
+        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
+        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
+        PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
+        PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
+        PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
+        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
+
+        /* LCDC */
+        PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PB11_IN, PB11_OUT,
+                PB10_IN, PB10_OUT,
+                PB9_IN, PB9_OUT,
+                PB8_IN, PB8_OUT,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) {
+                PB11MD_0, PB11MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB10MD_0, PB10MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB9MD_00, PB9MD_01, PB9MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB8MD_00, PB8MD_01, PB8MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) {
+                PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) {
+                PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) {
+                0, 0,
+                PC14_IN, PC14_OUT,
+                PC13_IN, PC13_OUT,
+                PC12_IN, PC12_OUT,
+                PC11_IN, PC11_OUT,
+                PC10_IN, PC10_OUT,
+                PC9_IN, PC9_OUT,
+                PC8_IN, PC8_OUT,
+                PC7_IN, PC7_OUT,
+                PC6_IN, PC6_OUT,
+                PC5_IN, PC5_OUT,
+                PC4_IN, PC4_OUT,
+                PC3_IN, PC3_OUT,
+                PC2_IN, PC2_OUT,
+                PC1_IN, PC1_OUT,
+                PC0_IN, PC0_OUT }
+        },
+        { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC14MD_0, PC14MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC13MD_0, PC13MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC12MD_0, PC12MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) {
+                PC11MD_00, PC11MD_01, PC11MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC10MD_00, PC10MD_01, PC10MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC9MD_0, PC9MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC8MD_0, PC8MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) {
+                PC7MD_0, PC7MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC6MD_0, PC6MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC5MD_0, PC5MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC4MD_0, PC4MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4) {
+                PC3MD_0, PC3MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC2MD_0, PC2MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC1MD_0, PC1MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PC0MD_00, PC0MD_01, PC0MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1) {
+                PD15_IN, PD15_OUT,
+                PD14_IN, PD14_OUT,
+                PD13_IN, PD13_OUT,
+                PD12_IN, PD12_OUT,
+                PD11_IN, PD11_OUT,
+                PD10_IN, PD10_OUT,
+                PD9_IN, PD9_OUT,
+                PD8_IN, PD8_OUT,
+                PD7_IN, PD7_OUT,
+                PD6_IN, PD6_OUT,
+                PD5_IN, PD5_OUT,
+                PD4_IN, PD4_OUT,
+                PD3_IN, PD3_OUT,
+                PD2_IN, PD2_OUT,
+                PD1_IN, PD1_OUT,
+                PD0_IN, PD0_OUT }
+        },
+        { PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4) {
+                PD15MD_000, PD15MD_001, PD15MD_010, 0,
+                PD15MD_100, PD15MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD14MD_000, PD14MD_001, PD14MD_010, 0,
+                0, PD14MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD13MD_000, PD13MD_001, PD13MD_010, 0,
+                PD13MD_100, PD13MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD12MD_000, PD12MD_001, PD12MD_010, 0,
+                PD12MD_100, PD12MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4) {
+                PD11MD_000, PD11MD_001, PD11MD_010, 0,
+                PD11MD_100, PD11MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD10MD_000, PD10MD_001, PD10MD_010, 0,
+                PD10MD_100, PD10MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD9MD_000, PD9MD_001, PD9MD_010, 0,
+                PD9MD_100, PD9MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD8MD_000, PD8MD_001, PD8MD_010, 0,
+                PD8MD_100, PD8MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4) {
+                PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011,
+                PD7MD_100, PD7MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011,
+                PD6MD_100, PD6MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011,
+                PD5MD_100, PD5MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011,
+                PD4MD_100, PD4MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4) {
+                PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011,
+                PD3MD_100, PD3MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011,
+                PD2MD_100, PD2MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011,
+                PD1MD_100, PD1MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011,
+                PD0MD_100, PD0MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1) {
+                PE15_IN, PE15_OUT,
+                PE14_IN, PE14_OUT,
+                PE13_IN, PE13_OUT,
+                PE12_IN, PE12_OUT,
+                PE11_IN, PE11_OUT,
+                PE10_IN, PE10_OUT,
+                PE9_IN, PE9_OUT,
+                PE8_IN, PE8_OUT,
+                PE7_IN, PE7_OUT,
+                PE6_IN, PE6_OUT,
+                PE5_IN, PE5_OUT,
+                PE4_IN, PE4_OUT,
+                PE3_IN, PE3_OUT,
+                PE2_IN, PE2_OUT,
+                PE1_IN, PE1_OUT,
+                PE0_IN, PE0_OUT }
+        },
+        { PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4) {
+                PE15MD_00, PE15MD_01, 0, PE15MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE14MD_00, PE14MD_01, 0, PE14MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE13MD_00, 0, 0, PE13MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE12MD_00, 0, 0, PE12MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4) {
+                PE11MD_000, PE11MD_001, PE11MD_010, 0,
+                PE11MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE10MD_000, PE10MD_001, PE10MD_010, 0,
+                PE10MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4) {
+                PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011,
+                PE7MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011,
+                PE6MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011,
+                PE5MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011,
+                PE4MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4) {
+                PE3MD_00, PE3MD_01, 0, PE3MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE2MD_00, PE2MD_01, 0, PE2MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PE0MD_000, PE0MD_001, 0, PE0MD_011,
+                PE0MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1) {
+                0, 0,
+                PF30_IN, PF30_OUT,
+                PF29_IN, PF29_OUT,
+                PF28_IN, PF28_OUT,
+                PF27_IN, PF27_OUT,
+                PF26_IN, PF26_OUT,
+                PF25_IN, PF25_OUT,
+                PF24_IN, PF24_OUT,
+                PF23_IN, PF23_OUT,
+                PF22_IN, PF22_OUT,
+                PF21_IN, PF21_OUT,
+                PF20_IN, PF20_OUT,
+                PF19_IN, PF19_OUT,
+                PF18_IN, PF18_OUT,
+                PF17_IN, PF17_OUT,
+                PF16_IN, PF16_OUT }
+        },
+        { PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1) {
+                PF15_IN, PF15_OUT,
+                PF14_IN, PF14_OUT,
+                PF13_IN, PF13_OUT,
+                PF12_IN, PF12_OUT,
+                PF11_IN, PF11_OUT,
+                PF10_IN, PF10_OUT,
+                PF9_IN, PF9_OUT,
+                PF8_IN, PF8_OUT,
+                PF7_IN, PF7_OUT,
+                PF6_IN, PF6_OUT,
+                PF5_IN, PF5_OUT,
+                PF4_IN, PF4_OUT,
+                PF3_IN, PF3_OUT,
+                PF2_IN, PF2_OUT,
+                PF1_IN, PF1_OUT,
+                PF0_IN, PF0_OUT }
+        },
+        { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF30MD_0, PF30MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF29MD_0, PF29MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF28MD_0, PF28MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4) {
+                PF27MD_0, PF27MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF26MD_0, PF26MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF25MD_0, PF25MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF24MD_0, PF24MD_1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4) {
+                PF23MD_00, PF23MD_01, PF23MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF22MD_00, PF22MD_01, PF22MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF21MD_00, PF21MD_01, PF21MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF20MD_00, PF20MD_01, PF20MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4) {
+                PF19MD_00, PF19MD_01, PF19MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF18MD_00, PF18MD_01, PF18MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF17MD_00, PF17MD_01, PF17MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF16MD_00, PF16MD_01, PF16MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4) {
+                PF15MD_00, PF15MD_01, PF15MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF14MD_00, PF14MD_01, PF14MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF13MD_00, PF13MD_01, PF13MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF12MD_00, PF12MD_01, PF12MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4) {
+                PF11MD_00, PF11MD_01, PF11MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF10MD_00, PF10MD_01, PF10MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF9MD_00, PF9MD_01, PF9MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF8MD_00, PF8MD_01, PF8MD_10, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4) {
+                PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4) {
+                PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+                PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
+                PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) {
+                0, 0, 0, PB12_DATA,
+                PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
+                PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+                PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) {
+                0, PC14_DATA, PC13_DATA, PC12_DATA,
+                PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
+                PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+                PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) {
+                PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
+                PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
+                PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+                PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) {
+                PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
+                PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
+                PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
+                PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) {
+                0, PF30_DATA, PF29_DATA, PF28_DATA,
+                PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
+                PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
+                PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
+        },
+        { PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) {
+                PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
+                PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
+                PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+                PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7203_pinmux_info = {
+        .name = "sh7203_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PA7,
+        .last_gpio = GPIO_FN_LCD_DATA0,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7203_pinmux_info);
+}
+
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 511de55af832..e07c69e16d9b 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -24,4 +24,8 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7710)	:= clock-sh7710.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7720)      := clock-sh7710.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7712)      := clock-sh7712.o
 
+# Pinmux setup
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7720)     := pinmux-sh7720.o
+
 obj-y   += $(clock-y)
+obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
new file mode 100644
index 000000000000..9ca154627147
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -0,0 +1,1242 @@
+/*
+ * SH7720 Pinmux
+ *
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7720.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+        PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE6_DATA, PTE5_DATA, PTE4_DATA,
+        PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
+        PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+        PTG6_DATA, PTG5_DATA, PTG4_DATA,
+        PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+        PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+        PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
+        PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+        PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+        PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
+        PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
+        PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
+        PTE6_IN, PTE5_IN, PTE4_IN,
+        PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
+        PTF6_IN, PTF5_IN, PTF4_IN,
+        PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
+        PTG6_IN, PTG5_IN, PTG4_IN,
+        PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
+        PTH6_IN, PTH5_IN, PTH4_IN,
+        PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
+        PTJ6_IN, PTJ5_IN, PTJ4_IN,
+        PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
+        PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
+        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, PTL3_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+        PTP4_IN, PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
+        PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
+        PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
+        PTS4_IN, PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
+        PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
+        PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
+        PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
+        PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
+        PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
+        PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
+        PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
+        PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
+        PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
+        PTE4_IN_PU, PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
+        PTF0_IN_PU,
+        PTG6_IN_PU, PTG5_IN_PU, PTG4_IN_PU,
+        PTG3_IN_PU, PTG2_IN_PU, PTG1_IN_PU, PTG0_IN_PU,
+        PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
+        PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
+        PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
+        PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
+        PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
+        PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, PTL3_IN_PU,
+        PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
+        PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
+        PTP4_IN_PU, PTP3_IN_PU, PTP2_IN_PU, PTP1_IN_PU, PTP0_IN_PU,
+        PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
+        PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
+        PTS4_IN_PU, PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
+        PTT4_IN_PU, PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
+        PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
+        PTV4_IN_PU, PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
+        PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
+        PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
+        PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
+        PTF0_OUT,
+        PTG6_OUT, PTG5_OUT, PTG4_OUT,
+        PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
+        PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
+        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, PTL3_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+        PTP4_OUT, PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
+        PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
+        PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
+        PTS4_OUT, PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
+        PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
+        PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
+        PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
+        PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
+        PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
+        PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
+        PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
+        PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
+        PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
+        PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
+        PTE6_FN, PTE5_FN, PTE4_FN,
+        PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
+        PTF6_FN, PTF5_FN, PTF4_FN,
+        PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
+        PTG6_FN, PTG5_FN, PTG4_FN,
+        PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
+        PTH6_FN, PTH5_FN, PTH4_FN,
+        PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
+        PTJ6_FN, PTJ5_FN, PTJ4_FN,
+        PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
+        PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
+        PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, PTL3_FN,
+        PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
+        PTP4_FN, PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
+        PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
+        PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
+        PTS4_FN, PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
+        PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
+        PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
+        PTV4_FN, PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
+
+        PSELA_1_0_00, PSELA_1_0_01, PSELA_1_0_10,
+        PSELA_3_2_00, PSELA_3_2_01, PSELA_3_2_10, PSELA_3_2_11,
+        PSELA_5_4_00, PSELA_5_4_01, PSELA_5_4_10, PSELA_5_4_11,
+        PSELA_7_6_00, PSELA_7_6_01, PSELA_7_6_10,
+        PSELA_9_8_00, PSELA_9_8_01, PSELA_9_8_10,
+        PSELA_11_10_00, PSELA_11_10_01, PSELA_11_10_10,
+        PSELA_13_12_00, PSELA_13_12_10,
+        PSELA_15_14_00, PSELA_15_14_10,
+        PSELB_9_8_00, PSELB_9_8_11,
+        PSELB_11_10_00, PSELB_11_10_01, PSELB_11_10_10, PSELB_11_10_11,
+        PSELB_13_12_00, PSELB_13_12_01, PSELB_13_12_10, PSELB_13_12_11,
+        PSELB_15_14_00, PSELB_15_14_11,
+        PSELC_9_8_00, PSELC_9_8_10,
+        PSELC_11_10_00, PSELC_11_10_10,
+        PSELC_13_12_00, PSELC_13_12_01, PSELC_13_12_10,
+        PSELC_15_14_00, PSELC_15_14_01, PSELC_15_14_10,
+        PSELD_1_0_00, PSELD_1_0_10,
+        PSELD_11_10_00, PSELD_11_10_01,
+        PSELD_15_14_00, PSELD_15_14_01, PSELD_15_14_10,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        D31_MARK, D30_MARK, D29_MARK, D28_MARK,
+        D27_MARK, D26_MARK, D25_MARK, D24_MARK,
+        D23_MARK, D22_MARK, D21_MARK, D20_MARK,
+        D19_MARK, D18_MARK, D17_MARK, D16_MARK,
+        IOIS16_MARK, RAS_MARK, CAS_MARK, CKE_MARK,
+        CS5B_CE1A_MARK, CS6B_CE1B_MARK,
+        A25_MARK, A24_MARK, A23_MARK, A22_MARK,
+        A21_MARK, A20_MARK, A19_MARK, A0_MARK,
+        REFOUT_MARK, IRQOUT_MARK,
+        LCD_DATA15_MARK, LCD_DATA14_MARK,
+        LCD_DATA13_MARK, LCD_DATA12_MARK,
+        LCD_DATA11_MARK, LCD_DATA10_MARK,
+        LCD_DATA9_MARK, LCD_DATA8_MARK,
+        LCD_DATA7_MARK, LCD_DATA6_MARK,
+        LCD_DATA5_MARK, LCD_DATA4_MARK,
+        LCD_DATA3_MARK, LCD_DATA2_MARK,
+        LCD_DATA1_MARK, LCD_DATA0_MARK,
+        LCD_M_DISP_MARK,
+        LCD_CL1_MARK, LCD_CL2_MARK,
+        LCD_DON_MARK, LCD_FLM_MARK,
+        LCD_VEPWC_MARK, LCD_VCPWC_MARK,
+        AFE_RXIN_MARK, AFE_RDET_MARK,
+        AFE_FS_MARK, AFE_TXOUT_MARK,
+        AFE_SCLK_MARK, AFE_RLYCNT_MARK,
+        AFE_HC1_MARK,
+        IIC_SCL_MARK, IIC_SDA_MARK,
+        DA1_MARK, DA0_MARK,
+        AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK,
+        USB1D_RCV_MARK, USB1D_TXSE0_MARK,
+        USB1D_TXDPLS_MARK, USB1D_DMNS_MARK,
+        USB1D_DPLS_MARK, USB1D_SPEED_MARK,
+        USB1D_TXENL_MARK,
+        USB2_PWR_EN_MARK, USB1_PWR_EN_USBF_UPLUP_MARK, USB1D_SUSPEND_MARK,
+        IRQ5_MARK, IRQ4_MARK,
+        IRQ3_IRL3_MARK, IRQ2_IRL2_MARK,
+        IRQ1_IRL1_MARK, IRQ0_IRL0_MARK,
+        PCC_REG_MARK, PCC_DRV_MARK,
+        PCC_BVD2_MARK, PCC_BVD1_MARK,
+        PCC_CD2_MARK, PCC_CD1_MARK,
+        PCC_RESET_MARK, PCC_RDY_MARK,
+        PCC_VS2_MARK, PCC_VS1_MARK,
+        AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
+        AUDCK_MARK, AUDSYNC_MARK, ASEBRKAK_MARK, TRST_MARK,
+        TMS_MARK, TDO_MARK, TDI_MARK, TCK_MARK,
+        DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK,
+        TEND1_MARK, TEND0_MARK,
+        SIOF0_SYNC_MARK, SIOF0_MCLK_MARK,
+        SIOF0_TXD_MARK, SIOF0_RXD_MARK,
+        SIOF0_SCK_MARK,
+        SIOF1_SYNC_MARK, SIOF1_MCLK_MARK,
+        SIOF1_TXD_MARK, SIOF1_RXD_MARK,
+        SIOF1_SCK_MARK,
+        SCIF0_TXD_MARK, SCIF0_RXD_MARK,
+        SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK,
+        SCIF1_TXD_MARK, SCIF1_RXD_MARK,
+        SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK,
+        TPU_TO1_MARK, TPU_TO0_MARK,
+        TPU_TI3B_MARK, TPU_TI3A_MARK,
+        TPU_TI2B_MARK, TPU_TI2A_MARK,
+        TPU_TO3_MARK, TPU_TO2_MARK,
+        SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
+        MMC_DAT_MARK, MMC_CMD_MARK,
+        MMC_CLK_MARK, MMC_VDDON_MARK,
+        MMC_ODMOD_MARK,
+        STATUS0_MARK, STATUS1_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA GPIO */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
+
+        /* PTB GPIO */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
+
+        /* PTC GPIO */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
+        PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
+        PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
+
+        /* PTD GPIO */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
+        PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
+        PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
+        PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
+        PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
+        PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
+        PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
+        PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
+
+        /* PTE GPIO */
+        PINMUX_DATA(PTE6_DATA, PTE6_IN),
+        PINMUX_DATA(PTE5_DATA, PTE5_IN),
+        PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
+        PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
+        PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
+        PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
+        PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
+
+        /* PTF GPIO */
+        PINMUX_DATA(PTF6_DATA, PTF6_IN),
+        PINMUX_DATA(PTF5_DATA, PTF5_IN),
+        PINMUX_DATA(PTF4_DATA, PTF4_IN),
+        PINMUX_DATA(PTF3_DATA, PTF3_IN),
+        PINMUX_DATA(PTF2_DATA, PTF2_IN),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN),
+        PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
+
+        /* PTG GPIO */
+        PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT, PTG6_IN_PU),
+        PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT, PTG5_IN_PU),
+        PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT, PTG4_IN_PU),
+        PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT, PTG3_IN_PU),
+        PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT, PTG2_IN_PU),
+        PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT, PTG1_IN_PU),
+        PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT, PTG0_IN_PU),
+
+        /* PTH GPIO */
+        PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
+        PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
+        PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
+        PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
+        PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
+        PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
+        PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
+
+        /* PTJ GPIO */
+        PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT, PTJ6_IN_PU),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT, PTJ5_IN_PU),
+        PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT, PTJ4_IN_PU),
+        PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
+        PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
+
+        /* PTK GPIO */
+        PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
+        PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
+        PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
+
+        /* PTL GPIO */
+        PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
+        PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
+        PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
+        PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
+        PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
+
+        /* PTM GPIO */
+        PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
+        PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
+        PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
+        PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
+        PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
+        PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
+        PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
+        PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
+
+        /* PTP GPIO */
+        PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT, PTP4_IN_PU),
+        PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT, PTP3_IN_PU),
+        PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT, PTP2_IN_PU),
+        PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT, PTP1_IN_PU),
+        PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT, PTP0_IN_PU),
+
+        /* PTR GPIO */
+        PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
+        PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
+        PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
+        PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
+        PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT, PTR3_IN_PU),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT, PTR2_IN_PU),
+        PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
+        PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
+
+        /* PTS GPIO */
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
+        PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
+        PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
+        PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
+
+        /* PTT GPIO */
+        PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
+        PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
+        PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
+        PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
+
+        /* PTU GPIO */
+        PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
+        PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
+        PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
+        PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
+
+        /* PTV GPIO */
+        PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
+        PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
+        PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
+        PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
+        PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
+
+        /* PTA FN */
+        PINMUX_DATA(D23_MARK, PTA7_FN),
+        PINMUX_DATA(D22_MARK, PTA6_FN),
+        PINMUX_DATA(D21_MARK, PTA5_FN),
+        PINMUX_DATA(D20_MARK, PTA4_FN),
+        PINMUX_DATA(D19_MARK, PTA3_FN),
+        PINMUX_DATA(D18_MARK, PTA2_FN),
+        PINMUX_DATA(D17_MARK, PTA1_FN),
+        PINMUX_DATA(D16_MARK, PTA0_FN),
+
+        /* PTB FN */
+        PINMUX_DATA(D31_MARK, PTB7_FN),
+        PINMUX_DATA(D30_MARK, PTB6_FN),
+        PINMUX_DATA(D29_MARK, PTB5_FN),
+        PINMUX_DATA(D28_MARK, PTB4_FN),
+        PINMUX_DATA(D27_MARK, PTB3_FN),
+        PINMUX_DATA(D26_MARK, PTB2_FN),
+        PINMUX_DATA(D25_MARK, PTB1_FN),
+        PINMUX_DATA(D24_MARK, PTB0_FN),
+
+        /* PTC FN */
+        PINMUX_DATA(LCD_DATA7_MARK, PTC7_FN),
+        PINMUX_DATA(LCD_DATA6_MARK, PTC6_FN),
+        PINMUX_DATA(LCD_DATA5_MARK, PTC5_FN),
+        PINMUX_DATA(LCD_DATA4_MARK, PTC4_FN),
+        PINMUX_DATA(LCD_DATA3_MARK, PTC3_FN),
+        PINMUX_DATA(LCD_DATA2_MARK, PTC2_FN),
+        PINMUX_DATA(LCD_DATA1_MARK, PTC1_FN),
+        PINMUX_DATA(LCD_DATA0_MARK, PTC0_FN),
+
+        /* PTD FN */
+        PINMUX_DATA(LCD_DATA15_MARK, PTD7_FN),
+        PINMUX_DATA(LCD_DATA14_MARK, PTD6_FN),
+        PINMUX_DATA(LCD_DATA13_MARK, PTD5_FN),
+        PINMUX_DATA(LCD_DATA12_MARK, PTD4_FN),
+        PINMUX_DATA(LCD_DATA11_MARK, PTD3_FN),
+        PINMUX_DATA(LCD_DATA10_MARK, PTD2_FN),
+        PINMUX_DATA(LCD_DATA9_MARK, PTD1_FN),
+        PINMUX_DATA(LCD_DATA8_MARK, PTD0_FN),
+
+        /* PTE FN */
+        PINMUX_DATA(IIC_SCL_MARK, PSELB_9_8_00, PTE6_FN),
+        PINMUX_DATA(AFE_RXIN_MARK, PSELB_9_8_11, PTE6_FN),
+        PINMUX_DATA(IIC_SDA_MARK, PSELB_9_8_00, PTE5_FN),
+        PINMUX_DATA(AFE_RDET_MARK, PSELB_9_8_11, PTE5_FN),
+        PINMUX_DATA(LCD_M_DISP_MARK, PTE4_FN),
+        PINMUX_DATA(LCD_CL1_MARK, PTE3_FN),
+        PINMUX_DATA(LCD_CL2_MARK, PTE2_FN),
+        PINMUX_DATA(LCD_DON_MARK, PTE1_FN),
+        PINMUX_DATA(LCD_FLM_MARK, PTE0_FN),
+
+        /* PTF FN */
+        PINMUX_DATA(DA1_MARK, PTF6_FN),
+        PINMUX_DATA(DA0_MARK, PTF5_FN),
+        PINMUX_DATA(AN3_MARK, PTF4_FN),
+        PINMUX_DATA(AN2_MARK, PTF3_FN),
+        PINMUX_DATA(AN1_MARK, PTF2_FN),
+        PINMUX_DATA(AN0_MARK, PTF1_FN),
+        PINMUX_DATA(ADTRG_MARK, PTF0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(USB1D_RCV_MARK, PSELA_3_2_00, PTG6_FN),
+        PINMUX_DATA(AFE_FS_MARK, PSELA_3_2_01, PTG6_FN),
+        PINMUX_DATA(PCC_REG_MARK, PSELA_3_2_10, PTG6_FN),
+        PINMUX_DATA(IRQ5_MARK, PSELA_3_2_11, PTG6_FN),
+        PINMUX_DATA(USB1D_TXSE0_MARK, PSELA_5_4_00, PTG5_FN),
+        PINMUX_DATA(AFE_TXOUT_MARK, PSELA_5_4_01, PTG5_FN),
+        PINMUX_DATA(PCC_DRV_MARK, PSELA_5_4_10, PTG5_FN),
+        PINMUX_DATA(IRQ4_MARK, PSELA_5_4_11, PTG5_FN),
+        PINMUX_DATA(USB1D_TXDPLS_MARK, PSELA_7_6_00, PTG4_FN),
+        PINMUX_DATA(AFE_SCLK_MARK, PSELA_7_6_01, PTG4_FN),
+        PINMUX_DATA(IOIS16_MARK, PSELA_7_6_10, PTG4_FN),
+        PINMUX_DATA(USB1D_DMNS_MARK, PSELA_9_8_00, PTG3_FN),
+        PINMUX_DATA(AFE_RLYCNT_MARK, PSELA_9_8_01, PTG3_FN),
+        PINMUX_DATA(PCC_BVD2_MARK, PSELA_9_8_10, PTG3_FN),
+        PINMUX_DATA(USB1D_DPLS_MARK, PSELA_11_10_00, PTG2_FN),
+        PINMUX_DATA(AFE_HC1_MARK, PSELA_11_10_01, PTG2_FN),
+        PINMUX_DATA(PCC_BVD1_MARK, PSELA_11_10_10, PTG2_FN),
+        PINMUX_DATA(USB1D_SPEED_MARK, PSELA_13_12_00, PTG1_FN),
+        PINMUX_DATA(PCC_CD2_MARK, PSELA_13_12_10, PTG1_FN),
+        PINMUX_DATA(USB1D_TXENL_MARK, PSELA_15_14_00, PTG0_FN),
+        PINMUX_DATA(PCC_CD1_MARK, PSELA_15_14_10, PTG0_FN),
+
+        /* PTH FN */
+        PINMUX_DATA(RAS_MARK, PTH6_FN),
+        PINMUX_DATA(CAS_MARK, PTH5_FN),
+        PINMUX_DATA(CKE_MARK, PTH4_FN),
+        PINMUX_DATA(STATUS1_MARK, PTH3_FN),
+        PINMUX_DATA(STATUS0_MARK, PTH2_FN),
+        PINMUX_DATA(USB2_PWR_EN_MARK, PTH1_FN),
+        PINMUX_DATA(USB1_PWR_EN_USBF_UPLUP_MARK, PTH0_FN),
+
+        /* PTJ FN */
+        PINMUX_DATA(AUDCK_MARK, PTJ6_FN),
+        PINMUX_DATA(ASEBRKAK_MARK, PTJ5_FN),
+        PINMUX_DATA(AUDATA3_MARK, PTJ4_FN),
+        PINMUX_DATA(AUDATA2_MARK, PTJ3_FN),
+        PINMUX_DATA(AUDATA1_MARK, PTJ2_FN),
+        PINMUX_DATA(AUDATA0_MARK, PTJ1_FN),
+        PINMUX_DATA(AUDSYNC_MARK, PTJ0_FN),
+
+        /* PTK FN */
+        PINMUX_DATA(PCC_RESET_MARK, PTK3_FN),
+        PINMUX_DATA(PCC_RDY_MARK, PTK2_FN),
+        PINMUX_DATA(PCC_VS2_MARK, PTK1_FN),
+        PINMUX_DATA(PCC_VS1_MARK, PTK0_FN),
+
+        /* PTL FN */
+        PINMUX_DATA(TRST_MARK, PTL7_FN),
+        PINMUX_DATA(TMS_MARK, PTL6_FN),
+        PINMUX_DATA(TDO_MARK, PTL5_FN),
+        PINMUX_DATA(TDI_MARK, PTL4_FN),
+        PINMUX_DATA(TCK_MARK, PTL3_FN),
+
+        /* PTM FN */
+        PINMUX_DATA(DREQ1_MARK, PTM7_FN),
+        PINMUX_DATA(DREQ0_MARK, PTM6_FN),
+        PINMUX_DATA(DACK1_MARK, PTM5_FN),
+        PINMUX_DATA(DACK0_MARK, PTM4_FN),
+        PINMUX_DATA(TEND1_MARK, PTM3_FN),
+        PINMUX_DATA(TEND0_MARK, PTM2_FN),
+        PINMUX_DATA(CS5B_CE1A_MARK, PTM1_FN),
+        PINMUX_DATA(CS6B_CE1B_MARK, PTM0_FN),
+
+        /* PTP FN */
+        PINMUX_DATA(USB1D_SUSPEND_MARK, PSELA_1_0_00, PTP4_FN),
+        PINMUX_DATA(REFOUT_MARK, PSELA_1_0_01, PTP4_FN),
+        PINMUX_DATA(IRQOUT_MARK, PSELA_1_0_10, PTP4_FN),
+        PINMUX_DATA(IRQ3_IRL3_MARK, PTP3_FN),
+        PINMUX_DATA(IRQ2_IRL2_MARK, PTP2_FN),
+        PINMUX_DATA(IRQ1_IRL1_MARK, PTP1_FN),
+        PINMUX_DATA(IRQ0_IRL0_MARK, PTP0_FN),
+
+        /* PTR FN */
+        PINMUX_DATA(A25_MARK, PTR7_FN),
+        PINMUX_DATA(A24_MARK, PTR6_FN),
+        PINMUX_DATA(A23_MARK, PTR5_FN),
+        PINMUX_DATA(A22_MARK, PTR4_FN),
+        PINMUX_DATA(A21_MARK, PTR3_FN),
+        PINMUX_DATA(A20_MARK, PTR2_FN),
+        PINMUX_DATA(A19_MARK, PTR1_FN),
+        PINMUX_DATA(A0_MARK, PTR0_FN),
+
+        /* PTS FN */
+        PINMUX_DATA(SIOF0_SYNC_MARK, PTS4_FN),
+        PINMUX_DATA(SIOF0_MCLK_MARK, PTS3_FN),
+        PINMUX_DATA(SIOF0_TXD_MARK, PTS2_FN),
+        PINMUX_DATA(SIOF0_RXD_MARK, PTS1_FN),
+        PINMUX_DATA(SIOF0_SCK_MARK, PTS0_FN),
+
+        /* PTT FN */
+        PINMUX_DATA(SCIF0_CTS_MARK, PSELB_15_14_00, PTT4_FN),
+        PINMUX_DATA(TPU_TO1_MARK, PSELB_15_14_11, PTT4_FN),
+        PINMUX_DATA(SCIF0_RTS_MARK, PSELB_15_14_00, PTT3_FN),
+        PINMUX_DATA(TPU_TO0_MARK, PSELB_15_14_11, PTT3_FN),
+        PINMUX_DATA(SCIF0_TXD_MARK, PTT2_FN),
+        PINMUX_DATA(SCIF0_RXD_MARK, PTT1_FN),
+        PINMUX_DATA(SCIF0_SCK_MARK, PTT0_FN),
+
+        /* PTU FN */
+        PINMUX_DATA(SIOF1_SYNC_MARK, PTU4_FN),
+        PINMUX_DATA(SIOF1_MCLK_MARK, PSELD_11_10_00, PTU3_FN),
+        PINMUX_DATA(TPU_TI3B_MARK, PSELD_11_10_01, PTU3_FN),
+        PINMUX_DATA(SIOF1_TXD_MARK, PSELD_15_14_00, PTU2_FN),
+        PINMUX_DATA(TPU_TI3A_MARK, PSELD_15_14_01, PTU2_FN),
+        PINMUX_DATA(MMC_DAT_MARK, PSELD_15_14_10, PTU2_FN),
+        PINMUX_DATA(SIOF1_RXD_MARK, PSELC_13_12_00, PTU1_FN),
+        PINMUX_DATA(TPU_TI2B_MARK, PSELC_13_12_01, PTU1_FN),
+        PINMUX_DATA(MMC_CMD_MARK, PSELC_13_12_10, PTU1_FN),
+        PINMUX_DATA(SIOF1_SCK_MARK, PSELC_15_14_00, PTU0_FN),
+        PINMUX_DATA(TPU_TI2A_MARK, PSELC_15_14_01, PTU0_FN),
+        PINMUX_DATA(MMC_CLK_MARK, PSELC_15_14_10, PTU0_FN),
+
+        /* PTV FN */
+        PINMUX_DATA(SCIF1_CTS_MARK, PSELB_11_10_00, PTV4_FN),
+        PINMUX_DATA(TPU_TO3_MARK, PSELB_11_10_01, PTV4_FN),
+        PINMUX_DATA(MMC_VDDON_MARK, PSELB_11_10_10, PTV4_FN),
+        PINMUX_DATA(LCD_VEPWC_MARK, PSELB_11_10_11, PTV4_FN),
+        PINMUX_DATA(SCIF1_RTS_MARK, PSELB_13_12_00, PTV3_FN),
+        PINMUX_DATA(TPU_TO2_MARK, PSELB_13_12_01, PTV3_FN),
+        PINMUX_DATA(MMC_ODMOD_MARK, PSELB_13_12_10, PTV3_FN),
+        PINMUX_DATA(LCD_VCPWC_MARK, PSELB_13_12_11, PTV3_FN),
+        PINMUX_DATA(SCIF1_TXD_MARK, PSELC_9_8_00, PTV2_FN),
+        PINMUX_DATA(SIM_D_MARK, PSELC_9_8_10, PTV2_FN),
+        PINMUX_DATA(SCIF1_RXD_MARK, PSELC_11_10_00, PTV1_FN),
+        PINMUX_DATA(SIM_RST_MARK, PSELC_11_10_10, PTV1_FN),
+        PINMUX_DATA(SCIF1_SCK_MARK, PSELD_1_0_00, PTV0_FN),
+        PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
+        PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
+        PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
+        PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
+        PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTP */
+        PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
+        PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
+        PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
+        PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
+        PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
+        PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
+        PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* BSC */
+        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
+        PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
+        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
+        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
+        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
+        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
+        PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
+
+        /* LCDC */
+        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
+
+        /* AFEIF */
+        PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK),
+        PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK),
+        PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK),
+        PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK),
+        PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK),
+
+        /* IIC */
+        PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK),
+        PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK),
+
+        /* DAC */
+        PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK),
+        PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK),
+
+        /* ADC */
+        PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
+        PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
+        PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
+        PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+
+        /* USB */
+        PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK),
+
+        PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP,
+                    USB1_PWR_EN_USBF_UPLUP_MARK),
+        PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK),
+
+        /* INTC */
+        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK),
+
+        /* PCC */
+        PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK),
+        PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK),
+
+        /* HUDI */
+        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK),
+        PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK),
+        PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK),
+        PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK),
+        PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK),
+        PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
+
+        /* SIOF0 */
+        PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
+
+        /* SIOF1 */
+        PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
+
+        /* SCIF0 */
+        PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
+
+        /* SCIF1 */
+        PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
+
+        /* TPU */
+        PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK),
+        PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK),
+
+        /* SIM */
+        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
+
+        /* MMC */
+        PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK),
+
+        /* SYSC */
+        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
+                PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
+                PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
+                PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
+                PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
+                PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
+                PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
+                PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
+                PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
+                PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
+                PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
+                PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
+                PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
+                PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
+                PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
+                PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
+                PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
+                PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
+                PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
+                PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
+                PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
+                PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
+                PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
+                PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
+                PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
+                PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
+                PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
+                PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
+                PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
+                PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
+                PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
+                PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
+                PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
+        },
+        { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
+                0, 0, 0, 0,
+                PTE6_FN, 0, 0, PTE6_IN,
+                PTE5_FN, 0, 0, PTE5_IN,
+                PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
+                PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
+                PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
+                PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
+                PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
+                0, 0, 0, 0,
+                PTF6_FN, 0, 0, PTF6_IN,
+                PTF5_FN, 0, 0, PTF5_IN,
+                PTF4_FN, 0, 0, PTF4_IN,
+                PTF3_FN, 0, 0, PTF3_IN,
+                PTF2_FN, 0, 0, PTF2_IN,
+                PTF1_FN, 0, 0, PTF1_IN,
+                PTF0_FN, 0, 0, PTF0_IN }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
+                0, 0, 0, 0,
+                PTG6_FN, PTG6_OUT, PTG6_IN_PU, PTG6_IN,
+                PTG5_FN, PTG5_OUT, PTG5_IN_PU, PTG5_IN,
+                PTG4_FN, PTG4_OUT, PTG4_IN_PU, PTG4_IN,
+                PTG3_FN, PTG3_OUT, PTG3_IN_PU, PTG3_IN,
+                PTG2_FN, PTG2_OUT, PTG2_IN_PU, PTG2_IN,
+                PTG1_FN, PTG1_OUT, PTG1_IN_PU, PTG1_IN,
+                PTG0_FN, PTG0_OUT, PTG0_IN_PU, PTG0_IN }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
+                0, 0, 0, 0,
+                PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
+                PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
+                PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
+                PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
+                PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
+                PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
+                PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
+                0, 0, 0, 0,
+                PTJ6_FN, PTJ6_OUT, PTJ6_IN_PU, PTJ6_IN,
+                PTJ5_FN, PTJ5_OUT, PTJ5_IN_PU, PTJ5_IN,
+                PTJ4_FN, PTJ4_OUT, PTJ4_IN_PU, PTJ4_IN,
+                PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
+                PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
+                PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
+                PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
+                PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
+                PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
+                PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
+                PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
+                PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
+                PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
+                PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
+                PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
+                PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
+                PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
+                PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
+                PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
+                PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
+                PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
+                PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
+                PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
+        },
+        { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTP4_FN, PTP4_OUT, PTP4_IN_PU, PTP4_IN,
+                PTP3_FN, PTP3_OUT, PTP3_IN_PU, PTP3_IN,
+                PTP2_FN, PTP2_OUT, PTP2_IN_PU, PTP2_IN,
+                PTP1_FN, PTP1_OUT, PTP1_IN_PU, PTP1_IN,
+                PTP0_FN, PTP0_OUT, PTP0_IN_PU, PTP0_IN }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) {
+                PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
+                PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
+                PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
+                PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
+                PTR3_FN, PTR3_OUT, PTR3_IN_PU, PTR3_IN,
+                PTR2_FN, PTR2_OUT, PTR2_IN_PU, PTR2_IN,
+                PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
+                PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
+                PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
+                PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
+                PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
+                PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
+                PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
+                PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
+                PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
+                PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
+                PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
+                PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
+                PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
+                PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
+                PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
+                PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
+                PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
+                PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xa4050142, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xa4050144, 8) {
+                PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xa4050148, 8) {
+                0, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+                PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xa405014a, 8) {
+                0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xa405014c, 8) {
+                0, PTG6_DATA, PTG5_DATA, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xa405014e, 8) {
+                0, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xa4050150, 8) {
+                0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+                PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xa4050152, 8) {
+                0, 0, 0, 0,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xa4050154, 8) {
+                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, 0, 0, 0 }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xa4050156, 8) {
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PPDR", 0xa4050158, 8) {
+                0, 0, 0, PTP4_DATA,
+                PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xa405015a, 8) {
+                PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xa405015c, 8) {
+                0, 0, 0, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xa405015e, 8) {
+                0, 0, 0, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xa4050160, 8) {
+                0, 0, 0, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xa4050162, 8) {
+                0, 0, 0, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7720_pinmux_info = {
+        .name = "sh7720_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA7,
+        .last_gpio = GPIO_FN_STATUS1,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7720_pinmux_info);
+}
+
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index 2d452f67fb87..2780917c0088 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -36,7 +36,7 @@ extern unsigned long int float32_add(unsigned long int a, unsigned long int b);
 extern unsigned long long float64_sub(unsigned long long a,
                                       unsigned long long b);
 extern unsigned long int float32_sub(unsigned long int a, unsigned long int b);
-
+extern unsigned long int float64_to_float32(unsigned long long a);
 static unsigned int fpu_exception_flags;
 
 /*
@@ -417,6 +417,29 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 regs->pc = nextpc;
                 return 1;
+        } else if ((finsn & 0xf0bd) == 0xf0bd) {
+                /* fcnvds - double to single precision convert */
+                struct task_struct *tsk = current;
+                int m;
+                unsigned int hx;
+
+                m = (finsn >> 9) & 0x7;
+                hx = tsk->thread.fpu.hard.fp_regs[m];
+
+                if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR)
+                        && ((hx & 0x7fffffff) < 0x00100000)) {
+                        /* subnormal double to float conversion */
+                        long long llx;
+
+                        llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32)
+                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+
+                        tsk->thread.fpu.hard.fpul = float64_to_float32(llx);
+                } else
+                        return 0;
+
+                regs->pc = nextpc;
+                return 1;
         }
 
         return 0;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 254c5c55ab91..d9bdc931ac09 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/io.h>
 
 enum {
         UNUSED = 0,
@@ -178,10 +179,14 @@ static int __init sh7760_devices_setup(void)
 }
 __initcall(sh7760_devices_setup);
 
+#define INTC_ICR        0xffd00000UL
+#define INTC_ICR_IRLM   (1 << 7)
+
 void __init plat_irq_setup_pins(int mode)
 {
         switch (mode) {
         case IRQ_MODE_IRQ:
+                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irq);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/softfloat.c b/arch/sh/kernel/cpu/sh4/softfloat.c
index 828cb57cb959..2b747f3b02bd 100644
--- a/arch/sh/kernel/cpu/sh4/softfloat.c
+++ b/arch/sh/kernel/cpu/sh4/softfloat.c
@@ -85,6 +85,7 @@ float64 float64_div(float64 a, float64 b);
 float32 float32_div(float32 a, float32 b);
 float32 float32_mul(float32 a, float32 b);
 float64 float64_mul(float64 a, float64 b);
+float32 float64_to_float32(float64 a);
 inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
                    bits64 * z1Ptr);
 inline void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
@@ -890,3 +891,31 @@ float64 float64_mul(float64 a, float64 b)
         }
         return roundAndPackFloat64(zSign, zExp, zSig0);
 }
+
+/*
+ * -------------------------------------------------------------------------------
+ *  Returns the result of converting the double-precision floating-point value
+ *  `a' to the single-precision floating-point format.  The conversion is
+ *  performed according to the IEC/IEEE Standard for Binary Floating-point
+ *  Arithmetic.
+ *  -------------------------------------------------------------------------------
+ *  */
+float32 float64_to_float32(float64 a)
+{
+    flag aSign;
+    int16 aExp;
+    bits64 aSig;
+    bits32 zSig;
+
+    aSig = extractFloat64Frac( a );
+    aExp = extractFloat64Exp( a );
+    aSign = extractFloat64Sign( a );
+
+    shift64RightJamming( aSig, 22, &aSig );
+    zSig = aSig;
+    if ( aExp || zSig ) {
+        zSig |= 0x40000000;
+        aExp -= 0x381;
+    }
+    return roundAndPackFloat32(aSign, aExp, zSig);
+}
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 9381ad8da263..be9a0c185958 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -27,5 +27,10 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7723)	:= clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SHX3)        := clock-shx3.o
 
+# Pinmux setup
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7722)     := pinmux-sh7722.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7723)     := pinmux-sh7723.o
+
 obj-y                   += $(clock-y)
 obj-$(CONFIG_SMP)       += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
new file mode 100644
index 000000000000..cb9d07bd59f8
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -0,0 +1,1783 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7722.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC5_DATA, PTC4_DATA, PTC3_DATA, PTC2_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, PTE1_DATA, PTE0_DATA,
+        PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+        PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK6_DATA, PTK5_DATA, PTK4_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+        PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+        PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+        PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
+        PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+        PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
+        PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+        PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PTW6_DATA, PTW5_DATA, PTW4_DATA,
+        PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
+        PTX6_DATA, PTX5_DATA, PTX4_DATA,
+        PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
+        PTY6_DATA, PTY5_DATA, PTY4_DATA,
+        PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
+        PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC5_IN, PTC4_IN, PTC3_IN, PTC2_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, PTD3_IN, PTD2_IN, PTD1_IN,
+        PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, PTE1_IN, PTE0_IN,
+        PTF6_IN, PTF5_IN, PTF4_IN, PTF3_IN, PTF2_IN, PTF1_IN,
+        PTH6_IN, PTH5_IN, PTH1_IN, PTH0_IN,
+        PTJ1_IN, PTJ0_IN,
+        PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK0_IN,
+        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
+        PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+        PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
+        PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
+        PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ0_IN,
+        PTR2_IN,
+        PTS4_IN, PTS2_IN, PTS1_IN,
+        PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN,
+        PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PTW6_IN, PTW4_IN, PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
+        PTX6_IN, PTX5_IN, PTX4_IN, PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
+        PTY5_IN, PTY4_IN, PTY3_IN, PTY2_IN, PTY0_IN,
+        PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD,
+        PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD,
+        PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD,
+        PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD,
+        PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD,
+        PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD,
+        PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD,
+        PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD,
+        PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD,
+        PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD,
+        PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD,
+        PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD,
+        PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD,
+        PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD,
+        PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD,
+        PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD,
+        PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD,
+        PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD,
+        PINMUX_INPUT_PULLDOWN_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTC7_IN_PU, PTC5_IN_PU,
+        PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
+        PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU,
+        PTJ1_IN_PU, PTJ0_IN_PU,
+        PTQ0_IN_PU,
+        PTR2_IN_PU,
+        PTX6_IN_PU,
+        PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU,
+        PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA5_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC4_OUT, PTC3_OUT, PTC2_OUT, PTC0_OUT,
+        PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, PTE1_OUT, PTE0_OUT,
+        PTF6_OUT, PTF5_OUT, PTF4_OUT, PTF3_OUT, PTF2_OUT, PTF0_OUT,
+        PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK1_OUT, PTK0_OUT,
+        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
+        PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+        PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
+        PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
+        PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
+        PTR4_OUT, PTR3_OUT, PTR1_OUT, PTR0_OUT,
+        PTS3_OUT, PTS2_OUT, PTS0_OUT,
+        PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT0_OUT,
+        PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU0_OUT,
+        PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PTW5_OUT, PTW4_OUT, PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
+        PTX6_OUT, PTX5_OUT, PTX4_OUT, PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
+        PTY5_OUT, PTY4_OUT, PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_MARK_BEGIN,
+        SCIF0_TXD_MARK, SCIF0_RXD_MARK,
+        SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK,
+        SCIF1_TXD_MARK, SCIF1_RXD_MARK,
+        SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK,
+        SCIF2_TXD_MARK, SCIF2_RXD_MARK,
+        SCIF2_RTS_MARK, SCIF2_CTS_MARK, SCIF2_SCK_MARK,
+        SIOTXD_MARK, SIORXD_MARK,
+        SIOD_MARK, SIOSTRB0_MARK, SIOSTRB1_MARK,
+        SIOSCK_MARK, SIOMCK_MARK,
+        VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK,
+        VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK,
+        VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK,
+        VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK,
+        VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, VIO_FLD_MARK,
+        VIO_CKO_MARK, VIO_STEX_MARK, VIO_STEM_MARK, VIO_VD2_MARK,
+        VIO_HD2_MARK, VIO_CLK2_MARK,
+        LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK,
+        LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK,
+        LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK,
+        LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK,
+        LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK,
+        LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK,
+        LCDLCLK_MARK, LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK,
+        LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK,
+        LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK,
+        LCDDON2_MARK, LCDVCPWC2_MARK, LCDVEPWC2_MARK, LCDVSYN2_MARK,
+        LCDCS2_MARK,
+        IOIS16_MARK, A25_MARK, A24_MARK, A23_MARK, A22_MARK,
+        BS_MARK, CS6B_CE1B_MARK, WAIT_MARK, CS6A_CE2B_MARK,
+        HPD63_MARK, HPD62_MARK, HPD61_MARK, HPD60_MARK,
+        HPD59_MARK, HPD58_MARK, HPD57_MARK, HPD56_MARK,
+        HPD55_MARK, HPD54_MARK, HPD53_MARK, HPD52_MARK,
+        HPD51_MARK, HPD50_MARK, HPD49_MARK, HPD48_MARK,
+        HPDQM7_MARK, HPDQM6_MARK, HPDQM5_MARK, HPDQM4_MARK,
+        IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK,
+        IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK,
+        SDHICD_MARK, SDHIWP_MARK, SDHID3_MARK, SDHID2_MARK,
+        SDHID1_MARK, SDHID0_MARK, SDHICMD_MARK, SDHICLK_MARK,
+        SIUAOLR_MARK, SIUAOBT_MARK, SIUAISLD_MARK, SIUAILR_MARK,
+        SIUAIBT_MARK, SIUAOSLD_MARK, SIUMCKA_MARK, SIUFCKA_MARK,
+        SIUBOLR_MARK, SIUBOBT_MARK, SIUBISLD_MARK, SIUBILR_MARK,
+        SIUBIBT_MARK, SIUBOSLD_MARK, SIUMCKB_MARK, SIUFCKB_MARK,
+        AUDSYNC_MARK, AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
+        DACK_MARK, DREQ0_MARK,
+        DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK,
+        DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK,
+        DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK,
+        DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK,
+        DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK,
+        STATUS0_MARK, PDSTATUS_MARK,
+        SIOF0_MCK_MARK, SIOF0_SCK_MARK,
+        SIOF0_SYNC_MARK, SIOF0_SS1_MARK, SIOF0_SS2_MARK,
+        SIOF0_TXD_MARK, SIOF0_RXD_MARK,
+        SIOF1_MCK_MARK, SIOF1_SCK_MARK,
+        SIOF1_SYNC_MARK, SIOF1_SS1_MARK, SIOF1_SS2_MARK,
+        SIOF1_TXD_MARK, SIOF1_RXD_MARK,
+        SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
+        TS_SDAT_MARK, TS_SCK_MARK, TS_SDEN_MARK, TS_SPSYNC_MARK,
+        IRDA_IN_MARK, IRDA_OUT_MARK,
+        TPUTO_MARK,
+        FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
+        NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK,
+        FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK,
+        KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK,
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK,
+        PINMUX_MARK_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        VIO_D7_SCIF1_SCK, VIO_D6_SCIF1_RXD, VIO_D5_SCIF1_TXD, VIO_D4,
+        VIO_D3, VIO_D2, VIO_D1, VIO_D0_LCDLCLK,
+        HPD55, HPD54, HPD53, HPD52, HPD51, HPD50, HPD49, HPD48,
+        IOIS16, HPDQM7, HPDQM6, HPDQM5, HPDQM4,
+        SDHICD, SDHIWP, SDHID3, IRQ2_SDHID2, SDHID1, SDHID0, SDHICMD, SDHICLK,
+        A25, A24, A23, A22, IRQ5, IRQ4_BS,
+        PTF6, SIOSCK_SIUBOBT, SIOSTRB1_SIUBOLR,
+        SIOSTRB0_SIUBIBT, SIOD_SIUBILR, SIORXD_SIUBISLD, SIOTXD_SIUBOSLD,
+        AUDSYNC, AUDATA3, AUDATA2, AUDATA1, AUDATA0,
+        LCDVCPWC_LCDVCPWC2, LCDVSYN2_DACK, LCDVSYN, LCDDISP_LCDRS,
+        LCDHSYN_LCDCS, LCDDON_LCDDON2, LCDD17_DV_HSYNC, LCDD16_DV_VSYNC,
+        STATUS0, PDSTATUS, IRQ1, IRQ0,
+        SIUAILR_SIOF1_SS2, SIUAIBT_SIOF1_SS1, SIUAOLR_SIOF1_SYNC,
+        SIUAOBT_SIOF1_SCK, SIUAISLD_SIOF1_RXD, SIUAOSLD_SIOF1_TXD, PTK0,
+        LCDD15_DV_D15, LCDD14_DV_D14, LCDD13_DV_D13, LCDD12_DV_D12,
+        LCDD11_DV_D11, LCDD10_DV_D10, LCDD9_DV_D9, LCDD8_DV_D8,
+        LCDD7_DV_D7, LCDD6_DV_D6, LCDD5_DV_D5, LCDD4_DV_D4,
+        LCDD3_DV_D3, LCDD2_DV_D2, LCDD1_DV_D1, LCDD0_DV_D0,
+        HPD63, HPD62, HPD61, HPD60, HPD59, HPD58, HPD57, HPD56,
+        SIOF0_SS2_SIM_RST, SIOF0_SS1_TS_SPSYNC, SIOF0_SYNC_TS_SDEN,
+        SIOF0_SCK_TS_SCK, PTQ2, PTQ1, PTQ0,
+        LCDRD, CS6B_CE1B_LCDCS2, WAIT, LCDDCK_LCDWR, LCDVEPWC_LCDVEPWC2,
+        SCIF0_CTS_SIUAISPD, SCIF0_RTS_SIUAOSPD,
+        SCIF0_SCK_TPUTO, SCIF0_RXD, SCIF0_TXD,
+        FOE_VIO_VD2, FWE, FSC, DREQ0, FCDE,
+        NAF2_VIO_D10, NAF1_VIO_D9, NAF0_VIO_D8,
+        FRB_VIO_CLK2, FCE_VIO_HD2,
+        NAF7_VIO_D15, NAF6_VIO_D14, NAF5_VIO_D13, NAF4_VIO_D12, NAF3_VIO_D11,
+        VIO_FLD_SCIF2_CTS, VIO_CKO_SCIF2_RTS, VIO_STEX_SCIF2_SCK,
+        VIO_STEM_SCIF2_TXD, VIO_HD_SCIF2_RXD,
+        VIO_VD_SCIF1_CTS, VIO_CLK_SCIF1_RTS,
+        CS6A_CE2B, LCDD23, LCDD22, LCDD21, LCDD20,
+        LCDD19_DV_CLKI, LCDD18_DV_CLK,
+        KEYOUT5_IN5, KEYOUT4_IN6, KEYOUT3, KEYOUT2, KEYOUT1, KEYOUT0,
+        KEYIN4_IRQ7, KEYIN3, KEYIN2, KEYIN1, KEYIN0_IRQ6,
+
+        PSA15_KEYIN0, PSA15_IRQ6, PSA14_KEYIN4, PSA14_IRQ7,
+        PSA9_IRQ4, PSA9_BS, PSA4_IRQ2, PSA4_SDHID2,
+        PSB15_SIOTXD, PSB15_SIUBOSLD, PSB14_SIORXD, PSB14_SIUBISLD,
+        PSB13_SIOD, PSB13_SIUBILR, PSB12_SIOSTRB0, PSB12_SIUBIBT,
+        PSB11_SIOSTRB1, PSB11_SIUBOLR, PSB10_SIOSCK, PSB10_SIUBOBT,
+        PSB9_SIOMCK, PSB9_SIUMCKB, PSB8_SIOF0_MCK, PSB8_IRQ3,
+        PSB7_SIOF0_TXD, PSB7_IRDA_OUT, PSB6_SIOF0_RXD, PSB6_IRDA_IN,
+        PSB5_SIOF0_SCK, PSB5_TS_SCK, PSB4_SIOF0_SYNC, PSB4_TS_SDEN,
+        PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, PSB2_SIOF0_SS2, PSB2_SIM_RST,
+        PSB1_SIUMCKA, PSB1_SIOF1_MCK, PSB0_SIUAOSLD, PSB0_SIOF1_TXD,
+        PSC15_SIUAISLD, PSC15_SIOF1_RXD, PSC14_SIUAOBT, PSC14_SIOF1_SCK,
+        PSC13_SIUAOLR, PSC13_SIOF1_SYNC, PSC12_SIUAIBT, PSC12_SIOF1_SS1,
+        PSC11_SIUAILR, PSC11_SIOF1_SS2, PSC0_NAF, PSC0_VIO,
+        PSD13_VIO, PSD13_SCIF2, PSD12_VIO, PSD12_SCIF1,
+        PSD11_VIO, PSD11_SCIF1, PSD10_VIO_D0, PSD10_LCDLCLK,
+        PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, PSD8_SCIF0_SCK, PSD8_TPUTO,
+        PSD7_SCIF0_RTS, PSD7_SIUAOSPD, PSD6_SCIF0_CTS, PSD6_SIUAISPD,
+        PSD5_CS6B_CE1B, PSD5_LCDCS2,
+        PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
+        PSD2_LCDDON, PSD2_LCDDON2, PSD0_LCDD19_LCDD0, PSD0_DV,
+        PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
+        PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
+        PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, PSE12_LCDVSYN2, PSE12_DACK,
+        PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
+        PSE3_FLCTL, PSE3_VIO, PSE2_NAF2, PSE2_VIO_D10,
+        PSE1_NAF1, PSE1_VIO_D9, PSE0_NAF0, PSE0_VIO_D8,
+
+        HIZA14_KEYSC, HIZA14_HIZ,
+        HIZA10_NAF, HIZA10_HIZ,
+        HIZA9_VIO, HIZA9_HIZ,
+        HIZA8_LCDC, HIZA8_HIZ,
+        HIZA7_LCDC, HIZA7_HIZ,
+        HIZA6_LCDC, HIZA6_HIZ,
+        HIZB1_VIO, HIZB1_HIZ,
+        HIZB0_VIO, HIZB0_HIZ,
+        HIZC15_IRQ7, HIZC15_HIZ,
+        HIZC14_IRQ6, HIZC14_HIZ,
+        HIZC13_IRQ5, HIZC13_HIZ,
+        HIZC12_IRQ4, HIZC12_HIZ,
+        HIZC11_IRQ3, HIZC11_HIZ,
+        HIZC10_IRQ2, HIZC10_HIZ,
+        HIZC9_IRQ1, HIZC9_HIZ,
+        HIZC8_IRQ0, HIZC8_HIZ,
+        MSELB9_VIO, MSELB9_VIO2,
+        MSELB8_RGB, MSELB8_SYS,
+        PINMUX_FUNCTION_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD),
+
+        /* PTB */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
+
+        /* PTC */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
+
+        /* PTD */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU),
+        PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU),
+        PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU),
+        PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU),
+        PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU),
+        PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU),
+        PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU),
+        PINMUX_DATA(PTD0_DATA, PTD0_OUT),
+
+        /* PTE */
+        PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD),
+        PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD),
+        PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD),
+        PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD),
+        PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD),
+        PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD),
+
+        /* PTF */
+        PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD),
+        PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD),
+        PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD),
+        PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD),
+        PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD),
+        PINMUX_DATA(PTF0_DATA, PTF0_OUT),
+
+        /* PTG */
+        PINMUX_DATA(PTG4_DATA, PTG4_OUT),
+        PINMUX_DATA(PTG3_DATA, PTG3_OUT),
+        PINMUX_DATA(PTG2_DATA, PTG2_OUT),
+        PINMUX_DATA(PTG1_DATA, PTG1_OUT),
+        PINMUX_DATA(PTG0_DATA, PTG0_OUT),
+
+        /* PTH */
+        PINMUX_DATA(PTH7_DATA, PTH7_OUT),
+        PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD),
+        PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD),
+        PINMUX_DATA(PTH4_DATA, PTH4_OUT),
+        PINMUX_DATA(PTH3_DATA, PTH3_OUT),
+        PINMUX_DATA(PTH2_DATA, PTH2_OUT),
+        PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD),
+        PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD),
+
+        /* PTJ */
+        PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
+        PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU),
+
+        /* PTK */
+        PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD),
+        PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD),
+        PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD),
+        PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD),
+        PINMUX_DATA(PTK1_DATA, PTK1_OUT),
+        PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD),
+
+        /* PTL */
+        PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD),
+        PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD),
+        PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD),
+        PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD),
+        PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD),
+        PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD),
+        PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD),
+        PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD),
+
+        /* PTM */
+        PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD),
+        PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD),
+        PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD),
+        PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD),
+        PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD),
+        PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD),
+        PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD),
+        PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD),
+
+        /* PTN */
+        PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN),
+        PINMUX_DATA(PTN6_DATA, PTN6_OUT, PTN6_IN),
+        PINMUX_DATA(PTN5_DATA, PTN5_OUT, PTN5_IN),
+        PINMUX_DATA(PTN4_DATA, PTN4_OUT, PTN4_IN),
+        PINMUX_DATA(PTN3_DATA, PTN3_OUT, PTN3_IN),
+        PINMUX_DATA(PTN2_DATA, PTN2_OUT, PTN2_IN),
+        PINMUX_DATA(PTN1_DATA, PTN1_OUT, PTN1_IN),
+        PINMUX_DATA(PTN0_DATA, PTN0_OUT, PTN0_IN),
+
+        /* PTQ */
+        PINMUX_DATA(PTQ6_DATA, PTQ6_OUT),
+        PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD),
+        PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD),
+        PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD),
+        PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD),
+        PINMUX_DATA(PTQ1_DATA, PTQ1_OUT),
+        PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU),
+
+        /* PTR */
+        PINMUX_DATA(PTR4_DATA, PTR4_OUT),
+        PINMUX_DATA(PTR3_DATA, PTR3_OUT),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
+        PINMUX_DATA(PTR1_DATA, PTR1_OUT),
+        PINMUX_DATA(PTR0_DATA, PTR0_OUT),
+
+        /* PTS */
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD),
+        PINMUX_DATA(PTS3_DATA, PTS3_OUT),
+        PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD),
+        PINMUX_DATA(PTS0_DATA, PTS0_OUT),
+
+        /* PTT */
+        PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD),
+        PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD),
+        PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD),
+        PINMUX_DATA(PTT0_DATA, PTT0_OUT),
+
+        /* PTU */
+        PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD),
+        PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD),
+        PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD),
+        PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD),
+
+        /* PTV */
+        PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD),
+        PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD),
+        PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD),
+        PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD),
+        PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD),
+
+        /* PTW */
+        PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD),
+        PINMUX_DATA(PTW5_DATA, PTW5_OUT),
+        PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD),
+        PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD),
+        PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD),
+        PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD),
+        PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD),
+
+        /* PTX */
+        PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD),
+        PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD),
+        PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD),
+        PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD),
+        PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD),
+        PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD),
+        PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD),
+
+        /* PTY */
+        PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU),
+        PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU),
+        PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU),
+        PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU),
+        PINMUX_DATA(PTY1_DATA, PTY1_OUT),
+        PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU),
+
+        /* PTZ */
+        PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU),
+        PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU),
+        PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU),
+        PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU),
+        PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU),
+
+        /* SCIF0 */
+        PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD),
+        PINMUX_DATA(SCIF0_RXD_MARK, SCIF0_RXD),
+        PINMUX_DATA(SCIF0_RTS_MARK, PSD7_SCIF0_RTS, SCIF0_RTS_SIUAOSPD),
+        PINMUX_DATA(SCIF0_CTS_MARK, PSD6_SCIF0_CTS, SCIF0_CTS_SIUAISPD),
+        PINMUX_DATA(SCIF0_SCK_MARK, PSD8_SCIF0_SCK, SCIF0_SCK_TPUTO),
+
+        /* SCIF1 */
+        PINMUX_DATA(SCIF1_TXD_MARK, PSD11_SCIF1, VIO_D5_SCIF1_TXD),
+        PINMUX_DATA(SCIF1_RXD_MARK, PSD11_SCIF1, VIO_D6_SCIF1_RXD),
+        PINMUX_DATA(SCIF1_RTS_MARK, PSD12_SCIF1, VIO_CLK_SCIF1_RTS),
+        PINMUX_DATA(SCIF1_CTS_MARK, PSD12_SCIF1, VIO_VD_SCIF1_CTS),
+        PINMUX_DATA(SCIF1_SCK_MARK, PSD11_SCIF1, VIO_D7_SCIF1_SCK),
+
+        /* SCIF2 */
+        PINMUX_DATA(SCIF2_TXD_MARK, PSD13_SCIF2, VIO_STEM_SCIF2_TXD),
+        PINMUX_DATA(SCIF2_RXD_MARK, PSD13_SCIF2, VIO_HD_SCIF2_RXD),
+        PINMUX_DATA(SCIF2_RTS_MARK, PSD13_SCIF2, VIO_CKO_SCIF2_RTS),
+        PINMUX_DATA(SCIF2_CTS_MARK, PSD13_SCIF2, VIO_FLD_SCIF2_CTS),
+        PINMUX_DATA(SCIF2_SCK_MARK, PSD13_SCIF2, VIO_STEX_SCIF2_SCK),
+
+        /* SIO */
+        PINMUX_DATA(SIOTXD_MARK, PSB15_SIOTXD, SIOTXD_SIUBOSLD),
+        PINMUX_DATA(SIORXD_MARK, PSB14_SIORXD, SIORXD_SIUBISLD),
+        PINMUX_DATA(SIOD_MARK, PSB13_SIOD, SIOD_SIUBILR),
+        PINMUX_DATA(SIOSTRB0_MARK, PSB12_SIOSTRB0, SIOSTRB0_SIUBIBT),
+        PINMUX_DATA(SIOSTRB1_MARK, PSB11_SIOSTRB1, SIOSTRB1_SIUBOLR),
+        PINMUX_DATA(SIOSCK_MARK, PSB10_SIOSCK, SIOSCK_SIUBOBT),
+        PINMUX_DATA(SIOMCK_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIOMCK, PTF6),
+
+        /* CEU */
+        PINMUX_DATA(VIO_D15_MARK, PSC0_VIO, HIZA10_NAF, NAF7_VIO_D15),
+        PINMUX_DATA(VIO_D14_MARK, PSC0_VIO, HIZA10_NAF, NAF6_VIO_D14),
+        PINMUX_DATA(VIO_D13_MARK, PSC0_VIO, HIZA10_NAF, NAF5_VIO_D13),
+        PINMUX_DATA(VIO_D12_MARK, PSC0_VIO, HIZA10_NAF, NAF4_VIO_D12),
+        PINMUX_DATA(VIO_D11_MARK, PSC0_VIO, HIZA10_NAF, NAF3_VIO_D11),
+        PINMUX_DATA(VIO_D10_MARK, PSE2_VIO_D10, HIZB0_VIO, NAF2_VIO_D10),
+        PINMUX_DATA(VIO_D9_MARK, PSE1_VIO_D9, HIZB0_VIO, NAF1_VIO_D9),
+        PINMUX_DATA(VIO_D8_MARK, PSE0_VIO_D8, HIZB0_VIO, NAF0_VIO_D8),
+        PINMUX_DATA(VIO_D7_MARK, PSD11_VIO, VIO_D7_SCIF1_SCK),
+        PINMUX_DATA(VIO_D6_MARK, PSD11_VIO, VIO_D6_SCIF1_RXD),
+        PINMUX_DATA(VIO_D5_MARK, PSD11_VIO, VIO_D5_SCIF1_TXD),
+        PINMUX_DATA(VIO_D4_MARK, VIO_D4),
+        PINMUX_DATA(VIO_D3_MARK, VIO_D3),
+        PINMUX_DATA(VIO_D2_MARK, VIO_D2),
+        PINMUX_DATA(VIO_D1_MARK, VIO_D1),
+        PINMUX_DATA(VIO_D0_MARK, PSD10_VIO_D0, VIO_D0_LCDLCLK),
+        PINMUX_DATA(VIO_CLK_MARK, PSD12_VIO, MSELB9_VIO, VIO_CLK_SCIF1_RTS),
+        PINMUX_DATA(VIO_VD_MARK, PSD12_VIO, MSELB9_VIO, VIO_VD_SCIF1_CTS),
+        PINMUX_DATA(VIO_HD_MARK, PSD13_VIO, MSELB9_VIO, VIO_HD_SCIF2_RXD),
+        PINMUX_DATA(VIO_FLD_MARK, PSD13_VIO, HIZA9_VIO, VIO_FLD_SCIF2_CTS),
+        PINMUX_DATA(VIO_CKO_MARK, PSD13_VIO, HIZA9_VIO, VIO_CKO_SCIF2_RTS),
+        PINMUX_DATA(VIO_STEX_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEX_SCIF2_SCK),
+        PINMUX_DATA(VIO_STEM_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEM_SCIF2_TXD),
+        PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
+                    HIZB0_VIO, FOE_VIO_VD2),
+        PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
+                    HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2),
+        PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
+                    HIZB1_VIO, FRB_VIO_CLK2),
+
+        /* LCDC */
+        PINMUX_DATA(LCDD23_MARK, HIZA8_LCDC, LCDD23),
+        PINMUX_DATA(LCDD22_MARK, HIZA8_LCDC, LCDD22),
+        PINMUX_DATA(LCDD21_MARK, HIZA8_LCDC, LCDD21),
+        PINMUX_DATA(LCDD20_MARK, HIZA8_LCDC, LCDD20),
+        PINMUX_DATA(LCDD19_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD19_DV_CLKI),
+        PINMUX_DATA(LCDD18_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD18_DV_CLK),
+        PINMUX_DATA(LCDD17_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC,
+                    LCDD17_DV_HSYNC),
+        PINMUX_DATA(LCDD16_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC,
+                    LCDD16_DV_VSYNC),
+        PINMUX_DATA(LCDD15_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD15_DV_D15),
+        PINMUX_DATA(LCDD14_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD14_DV_D14),
+        PINMUX_DATA(LCDD13_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD13_DV_D13),
+        PINMUX_DATA(LCDD12_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD12_DV_D12),
+        PINMUX_DATA(LCDD11_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD11_DV_D11),
+        PINMUX_DATA(LCDD10_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD10_DV_D10),
+        PINMUX_DATA(LCDD9_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD9_DV_D9),
+        PINMUX_DATA(LCDD8_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD8_DV_D8),
+        PINMUX_DATA(LCDD7_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD7_DV_D7),
+        PINMUX_DATA(LCDD6_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD6_DV_D6),
+        PINMUX_DATA(LCDD5_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD5_DV_D5),
+        PINMUX_DATA(LCDD4_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD4_DV_D4),
+        PINMUX_DATA(LCDD3_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD3_DV_D3),
+        PINMUX_DATA(LCDD2_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD2_DV_D2),
+        PINMUX_DATA(LCDD1_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD1_DV_D1),
+        PINMUX_DATA(LCDD0_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD0_DV_D0),
+        PINMUX_DATA(LCDLCLK_MARK, PSD10_LCDLCLK, VIO_D0_LCDLCLK),
+        /* Main LCD */
+        PINMUX_DATA(LCDDON_MARK, PSD2_LCDDON, HIZA7_LCDC, LCDDON_LCDDON2),
+        PINMUX_DATA(LCDVCPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC,
+                    HIZA6_LCDC, LCDVCPWC_LCDVCPWC2),
+        PINMUX_DATA(LCDVEPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC,
+                    HIZA6_LCDC, LCDVEPWC_LCDVEPWC2),
+        PINMUX_DATA(LCDVSYN_MARK, HIZA7_LCDC, LCDVSYN),
+        /* Main LCD - RGB Mode */
+        PINMUX_DATA(LCDDCK_MARK, MSELB8_RGB, HIZA8_LCDC, LCDDCK_LCDWR),
+        PINMUX_DATA(LCDHSYN_MARK, MSELB8_RGB, HIZA7_LCDC, LCDHSYN_LCDCS),
+        PINMUX_DATA(LCDDISP_MARK, MSELB8_RGB, HIZA7_LCDC, LCDDISP_LCDRS),
+        /* Main LCD - SYS Mode */
+        PINMUX_DATA(LCDRS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDDISP_LCDRS),
+        PINMUX_DATA(LCDCS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDHSYN_LCDCS),
+        PINMUX_DATA(LCDWR_MARK, MSELB8_SYS, HIZA8_LCDC, LCDDCK_LCDWR),
+        PINMUX_DATA(LCDRD_MARK, HIZA7_LCDC, LCDRD),
+        /* Sub LCD - SYS Mode */
+        PINMUX_DATA(LCDDON2_MARK, PSD2_LCDDON2, HIZA7_LCDC, LCDDON_LCDDON2),
+        PINMUX_DATA(LCDVCPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2,
+                    HIZA6_LCDC, LCDVCPWC_LCDVCPWC2),
+        PINMUX_DATA(LCDVEPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2,
+                    HIZA6_LCDC, LCDVEPWC_LCDVEPWC2),
+        PINMUX_DATA(LCDVSYN2_MARK, PSE12_LCDVSYN2, HIZA8_LCDC, LCDVSYN2_DACK),
+        PINMUX_DATA(LCDCS2_MARK, PSD5_LCDCS2, CS6B_CE1B_LCDCS2),
+
+        /* BSC */
+        PINMUX_DATA(IOIS16_MARK, IOIS16),
+        PINMUX_DATA(A25_MARK, A25),
+        PINMUX_DATA(A24_MARK, A24),
+        PINMUX_DATA(A23_MARK, A23),
+        PINMUX_DATA(A22_MARK, A22),
+        PINMUX_DATA(BS_MARK, PSA9_BS, IRQ4_BS),
+        PINMUX_DATA(CS6B_CE1B_MARK, PSD5_CS6B_CE1B, CS6B_CE1B_LCDCS2),
+        PINMUX_DATA(WAIT_MARK, WAIT),
+        PINMUX_DATA(CS6A_CE2B_MARK, CS6A_CE2B),
+
+        /* SBSC */
+        PINMUX_DATA(HPD63_MARK, HPD63),
+        PINMUX_DATA(HPD62_MARK, HPD62),
+        PINMUX_DATA(HPD61_MARK, HPD61),
+        PINMUX_DATA(HPD60_MARK, HPD60),
+        PINMUX_DATA(HPD59_MARK, HPD59),
+        PINMUX_DATA(HPD58_MARK, HPD58),
+        PINMUX_DATA(HPD57_MARK, HPD57),
+        PINMUX_DATA(HPD56_MARK, HPD56),
+        PINMUX_DATA(HPD55_MARK, HPD55),
+        PINMUX_DATA(HPD54_MARK, HPD54),
+        PINMUX_DATA(HPD53_MARK, HPD53),
+        PINMUX_DATA(HPD52_MARK, HPD52),
+        PINMUX_DATA(HPD51_MARK, HPD51),
+        PINMUX_DATA(HPD50_MARK, HPD50),
+        PINMUX_DATA(HPD49_MARK, HPD49),
+        PINMUX_DATA(HPD48_MARK, HPD48),
+        PINMUX_DATA(HPDQM7_MARK, HPDQM7),
+        PINMUX_DATA(HPDQM6_MARK, HPDQM6),
+        PINMUX_DATA(HPDQM5_MARK, HPDQM5),
+        PINMUX_DATA(HPDQM4_MARK, HPDQM4),
+
+        /* IRQ */
+        PINMUX_DATA(IRQ0_MARK, HIZC8_IRQ0, IRQ0),
+        PINMUX_DATA(IRQ1_MARK, HIZC9_IRQ1, IRQ1),
+        PINMUX_DATA(IRQ2_MARK, PSA4_IRQ2, HIZC10_IRQ2, IRQ2_SDHID2),
+        PINMUX_DATA(IRQ3_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_IRQ3,
+                    HIZC11_IRQ3, PTQ0),
+        PINMUX_DATA(IRQ4_MARK, PSA9_IRQ4, HIZC12_IRQ4, IRQ4_BS),
+        PINMUX_DATA(IRQ5_MARK, HIZC13_IRQ5, IRQ5),
+        PINMUX_DATA(IRQ6_MARK, PSA15_IRQ6, HIZC14_IRQ6, KEYIN0_IRQ6),
+        PINMUX_DATA(IRQ7_MARK, PSA14_IRQ7, HIZC15_IRQ7, KEYIN4_IRQ7),
+
+        /* SDHI */
+        PINMUX_DATA(SDHICD_MARK, SDHICD),
+        PINMUX_DATA(SDHIWP_MARK, SDHIWP),
+        PINMUX_DATA(SDHID3_MARK, SDHID3),
+        PINMUX_DATA(SDHID2_MARK, PSA4_SDHID2, IRQ2_SDHID2),
+        PINMUX_DATA(SDHID1_MARK, SDHID1),
+        PINMUX_DATA(SDHID0_MARK, SDHID0),
+        PINMUX_DATA(SDHICMD_MARK, SDHICMD),
+        PINMUX_DATA(SDHICLK_MARK, SDHICLK),
+
+        /* SIU - Port A */
+        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC),
+        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK),
+        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD),
+        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2),
+        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1),
+        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD),
+        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0),
+        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0),
+
+        /* SIU - Port B */
+        PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
+        PINMUX_DATA(SIUBOBT_MARK, PSB10_SIUBOBT, SIOSCK_SIUBOBT),
+        PINMUX_DATA(SIUBISLD_MARK, PSB14_SIUBISLD, SIORXD_SIUBISLD),
+        PINMUX_DATA(SIUBILR_MARK, PSB13_SIUBILR, SIOD_SIUBILR),
+        PINMUX_DATA(SIUBIBT_MARK, PSB12_SIUBIBT, SIOSTRB0_SIUBIBT),
+        PINMUX_DATA(SIUBOSLD_MARK, PSB15_SIUBOSLD, SIOTXD_SIUBOSLD),
+        PINMUX_DATA(SIUMCKB_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIUMCKB, PTF6),
+        PINMUX_DATA(SIUFCKB_MARK, PSD9_SIUFCKB, PTF6),
+
+        /* AUD */
+        PINMUX_DATA(AUDSYNC_MARK, AUDSYNC),
+        PINMUX_DATA(AUDATA3_MARK, AUDATA3),
+        PINMUX_DATA(AUDATA2_MARK, AUDATA2),
+        PINMUX_DATA(AUDATA1_MARK, AUDATA1),
+        PINMUX_DATA(AUDATA0_MARK, AUDATA0),
+
+        /* DMAC */
+        PINMUX_DATA(DACK_MARK, PSE12_DACK, LCDVSYN2_DACK),
+        PINMUX_DATA(DREQ0_MARK, DREQ0),
+
+        /* VOU */
+        PINMUX_DATA(DV_CLKI_MARK, PSD0_DV, LCDD19_DV_CLKI),
+        PINMUX_DATA(DV_CLK_MARK, PSD0_DV, LCDD18_DV_CLK),
+        PINMUX_DATA(DV_HSYNC_MARK, PSD0_DV, LCDD17_DV_HSYNC),
+        PINMUX_DATA(DV_VSYNC_MARK, PSD0_DV, LCDD16_DV_VSYNC),
+        PINMUX_DATA(DV_D15_MARK, PSD0_DV, LCDD15_DV_D15),
+        PINMUX_DATA(DV_D14_MARK, PSD0_DV, LCDD14_DV_D14),
+        PINMUX_DATA(DV_D13_MARK, PSD0_DV, LCDD13_DV_D13),
+        PINMUX_DATA(DV_D12_MARK, PSD0_DV, LCDD12_DV_D12),
+        PINMUX_DATA(DV_D11_MARK, PSD0_DV, LCDD11_DV_D11),
+        PINMUX_DATA(DV_D10_MARK, PSD0_DV, LCDD10_DV_D10),
+        PINMUX_DATA(DV_D9_MARK, PSD0_DV, LCDD9_DV_D9),
+        PINMUX_DATA(DV_D8_MARK, PSD0_DV, LCDD8_DV_D8),
+        PINMUX_DATA(DV_D7_MARK, PSD0_DV, LCDD7_DV_D7),
+        PINMUX_DATA(DV_D6_MARK, PSD0_DV, LCDD6_DV_D6),
+        PINMUX_DATA(DV_D5_MARK, PSD0_DV, LCDD5_DV_D5),
+        PINMUX_DATA(DV_D4_MARK, PSD0_DV, LCDD4_DV_D4),
+        PINMUX_DATA(DV_D3_MARK, PSD0_DV, LCDD3_DV_D3),
+        PINMUX_DATA(DV_D2_MARK, PSD0_DV, LCDD2_DV_D2),
+        PINMUX_DATA(DV_D1_MARK, PSD0_DV, LCDD1_DV_D1),
+        PINMUX_DATA(DV_D0_MARK, PSD0_DV, LCDD0_DV_D0),
+
+        /* CPG */
+        PINMUX_DATA(STATUS0_MARK, STATUS0),
+        PINMUX_DATA(PDSTATUS_MARK, PDSTATUS),
+
+        /* SIOF0 */
+        PINMUX_DATA(SIOF0_MCK_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_SIOF0_MCK, PTQ0),
+        PINMUX_DATA(SIOF0_SCK_MARK, PSB5_SIOF0_SCK, SIOF0_SCK_TS_SCK),
+        PINMUX_DATA(SIOF0_SYNC_MARK, PSB4_SIOF0_SYNC, SIOF0_SYNC_TS_SDEN),
+        PINMUX_DATA(SIOF0_SS1_MARK, PSB3_SIOF0_SS1, SIOF0_SS1_TS_SPSYNC),
+        PINMUX_DATA(SIOF0_SS2_MARK, PSB2_SIOF0_SS2, SIOF0_SS2_SIM_RST),
+        PINMUX_DATA(SIOF0_TXD_MARK, PSE14_SIOF0_TXD_IRDA_OUT,
+                    PSB7_SIOF0_TXD, PTQ1),
+        PINMUX_DATA(SIOF0_RXD_MARK, PSE13_SIOF0_RXD_IRDA_IN,
+                    PSB6_SIOF0_RXD, PTQ2),
+
+        /* SIOF1 */
+        PINMUX_DATA(SIOF1_MCK_MARK, PSE11_SIUMCKA_SIOF1_MCK,
+                    PSB1_SIOF1_MCK, PTK0),
+        PINMUX_DATA(SIOF1_SCK_MARK, PSC14_SIOF1_SCK, SIUAOBT_SIOF1_SCK),
+        PINMUX_DATA(SIOF1_SYNC_MARK, PSC13_SIOF1_SYNC, SIUAOLR_SIOF1_SYNC),
+        PINMUX_DATA(SIOF1_SS1_MARK, PSC12_SIOF1_SS1, SIUAIBT_SIOF1_SS1),
+        PINMUX_DATA(SIOF1_SS2_MARK, PSC11_SIOF1_SS2, SIUAILR_SIOF1_SS2),
+        PINMUX_DATA(SIOF1_TXD_MARK, PSB0_SIOF1_TXD, SIUAOSLD_SIOF1_TXD),
+        PINMUX_DATA(SIOF1_RXD_MARK, PSC15_SIOF1_RXD, SIUAISLD_SIOF1_RXD),
+
+        /* SIM */
+        PINMUX_DATA(SIM_D_MARK, PSE15_SIM_D, PTQ0),
+        PINMUX_DATA(SIM_CLK_MARK, PSE14_SIM_CLK, PTQ1),
+        PINMUX_DATA(SIM_RST_MARK, PSB2_SIM_RST, SIOF0_SS2_SIM_RST),
+
+        /* TSIF */
+        PINMUX_DATA(TS_SDAT_MARK, PSE13_TS_SDAT, PTQ2),
+        PINMUX_DATA(TS_SCK_MARK, PSB5_TS_SCK, SIOF0_SCK_TS_SCK),
+        PINMUX_DATA(TS_SDEN_MARK, PSB4_TS_SDEN, SIOF0_SYNC_TS_SDEN),
+        PINMUX_DATA(TS_SPSYNC_MARK, PSB3_TS_SPSYNC, SIOF0_SS1_TS_SPSYNC),
+
+        /* IRDA */
+        PINMUX_DATA(IRDA_IN_MARK, PSE13_SIOF0_RXD_IRDA_IN, PSB6_IRDA_IN, PTQ2),
+        PINMUX_DATA(IRDA_OUT_MARK, PSE14_SIOF0_TXD_IRDA_OUT,
+                    PSB7_IRDA_OUT, PTQ1),
+
+        /* TPU */
+        PINMUX_DATA(TPUTO_MARK, PSD8_TPUTO, SCIF0_SCK_TPUTO),
+
+        /* FLCTL */
+        PINMUX_DATA(FCE_MARK, PSE3_FLCTL, FCE_VIO_HD2),
+        PINMUX_DATA(NAF7_MARK, PSC0_NAF, HIZA10_NAF, NAF7_VIO_D15),
+        PINMUX_DATA(NAF6_MARK, PSC0_NAF, HIZA10_NAF, NAF6_VIO_D14),
+        PINMUX_DATA(NAF5_MARK, PSC0_NAF, HIZA10_NAF, NAF5_VIO_D13),
+        PINMUX_DATA(NAF4_MARK, PSC0_NAF, HIZA10_NAF, NAF4_VIO_D12),
+        PINMUX_DATA(NAF3_MARK, PSC0_NAF, HIZA10_NAF, NAF3_VIO_D11),
+        PINMUX_DATA(NAF2_MARK, PSE2_NAF2, HIZB0_VIO, NAF2_VIO_D10),
+        PINMUX_DATA(NAF1_MARK, PSE1_NAF1, HIZB0_VIO, NAF1_VIO_D9),
+        PINMUX_DATA(NAF0_MARK, PSE0_NAF0, HIZB0_VIO, NAF0_VIO_D8),
+        PINMUX_DATA(FCDE_MARK, FCDE),
+        PINMUX_DATA(FOE_MARK, PSE3_FLCTL, HIZB0_VIO, FOE_VIO_VD2),
+        PINMUX_DATA(FSC_MARK, FSC),
+        PINMUX_DATA(FWE_MARK, FWE),
+        PINMUX_DATA(FRB_MARK, PSE3_FLCTL, FRB_VIO_CLK2),
+
+        /* KEYSC */
+        PINMUX_DATA(KEYIN0_MARK, PSA15_KEYIN0, HIZC14_IRQ6, KEYIN0_IRQ6),
+        PINMUX_DATA(KEYIN1_MARK, HIZA14_KEYSC, KEYIN1),
+        PINMUX_DATA(KEYIN2_MARK, HIZA14_KEYSC, KEYIN2),
+        PINMUX_DATA(KEYIN3_MARK, HIZA14_KEYSC, KEYIN3),
+        PINMUX_DATA(KEYIN4_MARK, PSA14_KEYIN4, HIZC15_IRQ7, KEYIN4_IRQ7),
+        PINMUX_DATA(KEYOUT0_MARK, HIZA14_KEYSC, KEYOUT0),
+        PINMUX_DATA(KEYOUT1_MARK, HIZA14_KEYSC, KEYOUT1),
+        PINMUX_DATA(KEYOUT2_MARK, HIZA14_KEYSC, KEYOUT2),
+        PINMUX_DATA(KEYOUT3_MARK, HIZA14_KEYSC, KEYOUT3),
+        PINMUX_DATA(KEYOUT4_IN6_MARK, HIZA14_KEYSC, KEYOUT4_IN6),
+        PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
+        PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
+        PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
+        PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
+        PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+        PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
+        PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
+        PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTN */
+        PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
+        PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
+        PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
+        PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
+        PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
+        PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
+        PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
+        PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
+
+        /* PTQ */
+        PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
+        PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
+        PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
+        PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
+        PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
+        PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
+        PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* PTW */
+        PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
+        PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
+        PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
+        PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
+        PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
+        PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
+        PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
+
+        /* PTX */
+        PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
+        PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
+        PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
+        PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
+        PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
+        PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
+        PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
+
+        /* PTY */
+        PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
+        PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
+        PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
+        PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
+        PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
+        PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
+
+        /* PTZ */
+        PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
+        PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
+        PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
+        PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
+        PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+
+        /* SCIF0 */
+        PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
+
+        /* SCIF1 */
+        PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
+
+        /* SCIF2 */
+        PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK),
+
+        /* SIO */
+        PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK),
+
+        /* CEU */
+        PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
+
+        /* LCDC */
+        PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
+        /* Main LCD */
+        PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
+        /* Main LCD - RGB Mode */
+        PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
+        /* Main LCD - SYS Mode */
+        PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
+        /* Sub LCD - SYS Mode */
+        PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK),
+
+        /* BSC */
+        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
+
+        /* SBSC */
+        PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK),
+        PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK),
+        PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK),
+        PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK),
+        PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK),
+        PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK),
+
+        /* IRQ */
+        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
+
+        /* SDHI */
+        PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK),
+
+        /* SIU - Port A */
+        PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK),
+
+        /* SIU - Port B */
+        PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK),
+
+        /* AUD */
+        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+
+        /* VOU */
+        PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
+
+        /* CPG */
+        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
+        PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
+
+        /* SIOF0 */
+        PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
+
+        /* SIOF1 */
+        PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
+
+        /* SIM */
+        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
+
+        /* TSIF */
+        PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK),
+        PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK),
+        PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK),
+
+        /* IRDA */
+        PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
+        PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
+
+        /* TPU */
+        PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK),
+
+        /* FLCTL */
+        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
+        PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
+        PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
+        PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
+        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
+        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+
+        /* KEYSC */
+        PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
+                VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
+                VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
+                VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN,
+                VIO_D4, 0, PTA4_IN_PD, PTA4_IN,
+                VIO_D3, 0, PTA3_IN_PD, PTA3_IN,
+                VIO_D2, 0, PTA2_IN_PD, PTA2_IN,
+                VIO_D1, 0, PTA1_IN_PD, PTA1_IN,
+                VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
+                HPD55, PTB7_OUT, 0, PTB7_IN,
+                HPD54, PTB6_OUT, 0, PTB6_IN,
+                HPD53, PTB5_OUT, 0, PTB5_IN,
+                HPD52, PTB4_OUT, 0, PTB4_IN,
+                HPD51, PTB3_OUT, 0, PTB3_IN,
+                HPD50, PTB2_OUT, 0, PTB2_IN,
+                HPD49, PTB1_OUT, 0, PTB1_IN,
+                HPD48, PTB0_OUT, 0, PTB0_IN }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
+                0, 0, PTC7_IN_PU, PTC7_IN,
+                0, 0, 0, 0,
+                IOIS16, 0, PTC5_IN_PU, PTC5_IN,
+                HPDQM7, PTC4_OUT, 0, PTC4_IN,
+                HPDQM6, PTC3_OUT, 0, PTC3_IN,
+                HPDQM5, PTC2_OUT, 0, PTC2_IN,
+                0, 0, 0, 0,
+                HPDQM4, PTC0_OUT, 0, PTC0_IN }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
+                SDHICD, 0, PTD7_IN_PU, PTD7_IN,
+                SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
+                SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
+                IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
+                SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
+                SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
+                SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
+                SDHICLK, PTD0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
+                A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN,
+                A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN,
+                A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN,
+                A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN,
+                IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
+                0, 0, 0, 0,
+                PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN,
+                SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN,
+                SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN,
+                SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN,
+                SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN,
+                SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN,
+                SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                AUDSYNC, PTG4_OUT, 0, 0,
+                AUDATA3, PTG3_OUT, 0, 0,
+                AUDATA2, PTG2_OUT, 0, 0,
+                AUDATA1, PTG1_OUT, 0, 0,
+                AUDATA0, PTG0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
+                LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
+                LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN,
+                LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN,
+                LCDDISP_LCDRS, PTH4_OUT, 0, 0,
+                LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
+                LCDDON_LCDDON2, PTH2_OUT, 0, 0,
+                LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN,
+                LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
+                STATUS0, PTJ7_OUT, 0, 0,
+                0, PTJ6_OUT, 0, 0,
+                PDSTATUS, PTJ5_OUT, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
+                IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
+                0, 0, 0, 0,
+                SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN,
+                SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN,
+                SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN,
+                SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN,
+                SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN,
+                SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
+                PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
+                LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN,
+                LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN,
+                LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN,
+                LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN,
+                LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN,
+                LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN,
+                LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN,
+                LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
+                LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN,
+                LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN,
+                LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN,
+                LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN,
+                LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN,
+                LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN,
+                LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN,
+                LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN }
+        },
+        { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
+                HPD63, PTN7_OUT, 0, PTN7_IN,
+                HPD62, PTN6_OUT, 0, PTN6_IN,
+                HPD61, PTN5_OUT, 0, PTN5_IN,
+                HPD60, PTN4_OUT, 0, PTN4_IN,
+                HPD59, PTN3_OUT, 0, PTN3_IN,
+                HPD58, PTN2_OUT, 0, PTN2_IN,
+                HPD57, PTN1_OUT, 0, PTN1_IN,
+                HPD56, PTN0_OUT, 0, PTN0_IN }
+        },
+        { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
+                0, 0, 0, 0,
+                SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
+                SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN,
+                SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN,
+                SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN,
+                PTQ2, 0, PTQ2_IN_PD, PTQ2_IN,
+                PTQ1, PTQ1_OUT, 0, 0,
+                PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                LCDRD, PTR4_OUT, 0, 0,
+                CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
+                WAIT, 0, PTR2_IN_PU, PTR2_IN,
+                LCDDCK_LCDWR, PTR1_OUT, 0, 0,
+                LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN,
+                SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
+                SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN,
+                SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN,
+                SCIF0_TXD, PTS0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN,
+                FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN,
+                FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN,
+                DREQ0, 0, PTT1_IN_PD, PTT1_IN,
+                FCDE, PTT0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN,
+                NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN,
+                NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN,
+                FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN,
+                FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN,
+                NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN,
+                NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN,
+                NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN,
+                NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN }
+        },
+        { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
+                0, 0, 0, 0,
+                VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN,
+                VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
+                VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN,
+                VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN,
+                VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN,
+                VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN,
+                VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN }
+        },
+        { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
+                0, 0, 0, 0,
+                CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
+                LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN,
+                LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN,
+                LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN,
+                LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN,
+                LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN,
+                LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN }
+        },
+        { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
+                KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
+                KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
+                KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
+                KEYOUT1, PTY1_OUT, 0, 0,
+                KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
+        },
+        { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN,
+                KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN,
+                KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN,
+                KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN,
+                KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
+                PSA15_KEYIN0, PSA15_IRQ6,
+                PSA14_KEYIN4, PSA14_IRQ7,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PSA9_IRQ4, PSA9_BS,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PSA4_IRQ2, PSA4_SDHID2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0 }
+        },
+        { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
+                PSB15_SIOTXD, PSB15_SIUBOSLD,
+                PSB14_SIORXD, PSB14_SIUBISLD,
+                PSB13_SIOD, PSB13_SIUBILR,
+                PSB12_SIOSTRB0, PSB12_SIUBIBT,
+                PSB11_SIOSTRB1, PSB11_SIUBOLR,
+                PSB10_SIOSCK, PSB10_SIUBOBT,
+                PSB9_SIOMCK, PSB9_SIUMCKB,
+                PSB8_SIOF0_MCK, PSB8_IRQ3,
+                PSB7_SIOF0_TXD, PSB7_IRDA_OUT,
+                PSB6_SIOF0_RXD, PSB6_IRDA_IN,
+                PSB5_SIOF0_SCK, PSB5_TS_SCK,
+                PSB4_SIOF0_SYNC, PSB4_TS_SDEN,
+                PSB3_SIOF0_SS1, PSB3_TS_SPSYNC,
+                PSB2_SIOF0_SS2, PSB2_SIM_RST,
+                PSB1_SIUMCKA, PSB1_SIOF1_MCK,
+                PSB0_SIUAOSLD, PSB0_SIOF1_TXD }
+        },
+        { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
+                PSC15_SIUAISLD, PSC15_SIOF1_RXD,
+                PSC14_SIUAOBT, PSC14_SIOF1_SCK,
+                PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
+                PSC12_SIUAIBT, PSC12_SIOF1_SS1,
+                PSC11_SIUAILR, PSC11_SIOF1_SS2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PSC0_NAF, PSC0_VIO }
+        },
+        { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
+                0, 0,
+                0, 0,
+                PSD13_VIO, PSD13_SCIF2,
+                PSD12_VIO, PSD12_SCIF1,
+                PSD11_VIO, PSD11_SCIF1,
+                PSD10_VIO_D0, PSD10_LCDLCLK,
+                PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB,
+                PSD8_SCIF0_SCK, PSD8_TPUTO,
+                PSD7_SCIF0_RTS, PSD7_SIUAOSPD,
+                PSD6_SCIF0_CTS, PSD6_SIUAISPD,
+                PSD5_CS6B_CE1B, PSD5_LCDCS2,
+                0, 0,
+                PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
+                PSD2_LCDDON, PSD2_LCDDON2,
+                0, 0,
+                PSD0_LCDD19_LCDD0, PSD0_DV }
+        },
+        { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
+                PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
+                PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
+                PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
+                PSE12_LCDVSYN2, PSE12_DACK,
+                PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PSE3_FLCTL, PSE3_VIO,
+                PSE2_NAF2, PSE2_VIO_D10,
+                PSE1_NAF1, PSE1_VIO_D9,
+                PSE0_NAF0, PSE0_VIO_D8 }
+        },
+        { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) {
+                0, 0,
+                HIZA14_KEYSC, HIZA14_HIZ,
+                0, 0,
+                0, 0,
+                0, 0,
+                HIZA10_NAF, HIZA10_HIZ,
+                HIZA9_VIO, HIZA9_HIZ,
+                HIZA8_LCDC, HIZA8_HIZ,
+                HIZA7_LCDC, HIZA7_HIZ,
+                HIZA6_LCDC, HIZA6_HIZ,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0 }
+        },
+        { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                HIZB1_VIO, HIZB1_HIZ,
+                HIZB0_VIO, HIZB0_HIZ }
+        },
+        { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) {
+                HIZC15_IRQ7, HIZC15_HIZ,
+                HIZC14_IRQ6, HIZC14_HIZ,
+                HIZC13_IRQ5, HIZC13_HIZ,
+                HIZC12_IRQ4, HIZC12_HIZ,
+                HIZC11_IRQ3, HIZC11_HIZ,
+                HIZC10_IRQ2, HIZC10_HIZ,
+                HIZC9_IRQ1, HIZC9_HIZ,
+                HIZC8_IRQ0, HIZC8_HIZ,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0 }
+        },
+        { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                MSELB9_VIO, MSELB9_VIO2,
+                MSELB8_RGB, MSELB8_SYS,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0 }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
+                PTC7_DATA, 0, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, 0, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
+                PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+                0, 0, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
+                0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
+                0, 0, 0, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
+                PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
+                PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
+                0, 0, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
+                0, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
+                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
+                PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
+        },
+        { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
+                0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+                PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
+                0, 0, 0, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
+                0, 0, 0, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
+                0, 0, 0, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
+                0, 0, 0, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
+                0, 0, 0, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
+                0, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+                PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
+        },
+        { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
+                0, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+                PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
+        },
+        { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
+                0, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+                PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
+        },
+        { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
+                0, 0, PTZ5_DATA, PTZ4_DATA,
+                PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7722_pinmux_info = {
+        .name = "sh7722_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA7,
+        .last_gpio = GPIO_FN_KEYOUT5_IN5,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7722_pinmux_info);
+}
+
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
new file mode 100644
index 000000000000..88bf5ecda849
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -0,0 +1,1909 @@
+/*
+ * SH7723 Pinmux
+ *
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7723.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+        PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE5_DATA, PTE4_DATA, PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
+        PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+        PTG5_DATA, PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTJ7_DATA, PTJ5_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+        PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+        PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+        PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
+        PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
+        PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+        PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+        PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
+        PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+        PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+        PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
+        PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+        PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
+        PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+        PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
+        PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+        PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
+        PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
+        PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
+        PTE5_IN, PTE4_IN, PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
+        PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
+        PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
+        PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
+        PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
+        PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
+        PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
+        PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
+        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
+        PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+        PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
+        PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
+        PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
+        PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
+        PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
+        PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
+        PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
+        PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
+        PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
+        PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
+        PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
+        PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
+        PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
+        PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
+        PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
+        PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
+        PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
+        PTB2_IN_PU, PTB1_IN_PU,
+        PTR2_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
+        PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
+        PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
+        PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE5_OUT, PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
+        PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
+        PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
+        PTG5_OUT, PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTJ7_OUT, PTJ5_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
+        PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
+        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
+        PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+        PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
+        PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
+        PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
+        PTR1_OUT, PTR0_OUT,
+        PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
+        PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
+        PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
+        PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
+        PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
+        PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
+        PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
+        PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
+        PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
+        PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
+        PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
+        PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
+        PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
+        PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
+        PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
+        PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
+        PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
+        PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
+        PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
+        PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
+        PTE5_FN, PTE4_FN, PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
+        PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
+        PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
+        PTG5_FN, PTG4_FN, PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
+        PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
+        PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
+        PTJ7_FN, PTJ5_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
+        PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
+        PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
+        PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
+        PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
+        PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
+        PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
+        PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
+        PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
+        PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
+        PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
+        PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
+        PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
+        PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
+        PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
+        PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
+        PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
+        PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
+        PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
+        PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
+        PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
+        PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
+        PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
+        PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
+        PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
+
+
+        PSA15_PSA14_FN1, PSA15_PSA14_FN2,
+        PSA13_PSA12_FN1, PSA13_PSA12_FN2,
+        PSA11_PSA10_FN1, PSA11_PSA10_FN2,
+        PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3,
+        PSA3_PSA2_FN1, PSA3_PSA2_FN2,
+        PSB15_PSB14_FN1, PSB15_PSB14_FN2,
+        PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS,
+        PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3,
+        PSB7_PSB6_FN1, PSB7_PSB6_FN2,
+        PSB5_PSB4_FN1, PSB5_PSB4_FN2,
+        PSB3_PSB2_FN1, PSB3_PSB2_FN2,
+        PSC15_PSC14_FN1, PSC15_PSC14_FN2,
+        PSC13_PSC12_FN1, PSC13_PSC12_FN2,
+        PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3,
+        PSC9_PSC8_FN1, PSC9_PSC8_FN2,
+        PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3,
+        PSD15_PSD14_FN1, PSD15_PSD14_FN2,
+        PSD13_PSD12_FN1, PSD13_PSD12_FN2,
+        PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3,
+        PSD9_PSD8_FN1, PSD9_PSD8_FN2,
+        PSD7_PSD6_FN1, PSD7_PSD6_FN2,
+        PSD5_PSD4_FN1, PSD5_PSD4_FN2,
+        PSD3_PSD2_FN1, PSD3_PSD2_FN2,
+        PSD1_PSD0_FN1, PSD1_PSD0_FN2,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        SCIF0_PTT_TXD_MARK, SCIF0_PTT_RXD_MARK,
+        SCIF0_PTT_SCK_MARK, SCIF0_PTU_TXD_MARK,
+        SCIF0_PTU_RXD_MARK, SCIF0_PTU_SCK_MARK,
+
+        SCIF1_PTS_TXD_MARK, SCIF1_PTS_RXD_MARK,
+        SCIF1_PTS_SCK_MARK, SCIF1_PTV_TXD_MARK,
+        SCIF1_PTV_RXD_MARK, SCIF1_PTV_SCK_MARK,
+
+        SCIF2_PTT_TXD_MARK, SCIF2_PTT_RXD_MARK,
+        SCIF2_PTT_SCK_MARK, SCIF2_PTU_TXD_MARK,
+        SCIF2_PTU_RXD_MARK, SCIF2_PTU_SCK_MARK,
+
+        SCIF3_PTS_TXD_MARK, SCIF3_PTS_RXD_MARK,
+        SCIF3_PTS_SCK_MARK, SCIF3_PTS_RTS_MARK,
+        SCIF3_PTS_CTS_MARK, SCIF3_PTV_TXD_MARK,
+        SCIF3_PTV_RXD_MARK, SCIF3_PTV_SCK_MARK,
+        SCIF3_PTV_RTS_MARK, SCIF3_PTV_CTS_MARK,
+
+        SCIF4_PTE_TXD_MARK, SCIF4_PTE_RXD_MARK,
+        SCIF4_PTE_SCK_MARK, SCIF4_PTN_TXD_MARK,
+        SCIF4_PTN_RXD_MARK, SCIF4_PTN_SCK_MARK,
+
+        SCIF5_PTE_TXD_MARK, SCIF5_PTE_RXD_MARK,
+        SCIF5_PTE_SCK_MARK, SCIF5_PTN_TXD_MARK,
+        SCIF5_PTN_RXD_MARK, SCIF5_PTN_SCK_MARK,
+
+        VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK,
+        VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK,
+        VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK,
+        VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK,
+        VIO_FLD_MARK, VIO_CKO_MARK,
+        VIO_VD1_MARK, VIO_HD1_MARK, VIO_CLK1_MARK,
+        VIO_HD2_MARK, VIO_VD2_MARK, VIO_CLK2_MARK,
+
+        LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK,
+        LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK,
+        LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK,
+        LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK,
+        LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK,
+        LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK,
+        LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK,
+        LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK,
+        LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK,
+        LCDLCLK_PTR_MARK, LCDLCLK_PTW_MARK,
+
+        IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK,
+        IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK,
+
+        AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
+        AUDCK_MARK, AUDSYNC_MARK,
+
+        SDHI0CD_PTD_MARK, SDHI0WP_PTD_MARK,
+        SDHI0D3_PTD_MARK, SDHI0D2_PTD_MARK,
+        SDHI0D1_PTD_MARK, SDHI0D0_PTD_MARK,
+        SDHI0CMD_PTD_MARK, SDHI0CLK_PTD_MARK,
+
+        SDHI0CD_PTS_MARK, SDHI0WP_PTS_MARK,
+        SDHI0D3_PTS_MARK, SDHI0D2_PTS_MARK,
+        SDHI0D1_PTS_MARK, SDHI0D0_PTS_MARK,
+        SDHI0CMD_PTS_MARK, SDHI0CLK_PTS_MARK,
+
+        SDHI1CD_MARK, SDHI1WP_MARK, SDHI1D3_MARK, SDHI1D2_MARK,
+        SDHI1D1_MARK, SDHI1D0_MARK, SDHI1CMD_MARK, SDHI1CLK_MARK,
+
+        SIUAFCK_MARK, SIUAILR_MARK, SIUAIBT_MARK, SIUAISLD_MARK,
+        SIUAOLR_MARK, SIUAOBT_MARK, SIUAOSLD_MARK, SIUAMCK_MARK,
+        SIUAISPD_MARK, SIUAOSPD_MARK,
+
+        SIUBFCK_MARK, SIUBILR_MARK, SIUBIBT_MARK, SIUBISLD_MARK,
+        SIUBOLR_MARK, SIUBOBT_MARK, SIUBOSLD_MARK, SIUBMCK_MARK,
+
+        IRDA_IN_MARK, IRDA_OUT_MARK,
+
+        DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK,
+        DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK,
+        DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK,
+        DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK,
+        DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK,
+
+        KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK,
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK,
+
+        MSIOF0_PTF_TXD_MARK, MSIOF0_PTF_RXD_MARK, MSIOF0_PTF_MCK_MARK,
+        MSIOF0_PTF_TSYNC_MARK, MSIOF0_PTF_TSCK_MARK, MSIOF0_PTF_RSYNC_MARK,
+        MSIOF0_PTF_RSCK_MARK, MSIOF0_PTF_SS1_MARK, MSIOF0_PTF_SS2_MARK,
+
+        MSIOF0_PTT_TXD_MARK, MSIOF0_PTT_RXD_MARK, MSIOF0_PTX_MCK_MARK,
+        MSIOF0_PTT_TSYNC_MARK, MSIOF0_PTT_TSCK_MARK, MSIOF0_PTT_RSYNC_MARK,
+        MSIOF0_PTT_RSCK_MARK, MSIOF0_PTT_SS1_MARK, MSIOF0_PTT_SS2_MARK,
+
+        MSIOF1_TXD_MARK, MSIOF1_RXD_MARK, MSIOF1_MCK_MARK,
+        MSIOF1_TSYNC_MARK, MSIOF1_TSCK_MARK, MSIOF1_RSYNC_MARK,
+        MSIOF1_RSCK_MARK, MSIOF1_SS1_MARK, MSIOF1_SS2_MARK,
+
+        TS0_SDAT_MARK, TS0_SCK_MARK, TS0_SDEN_MARK, TS0_SPSYNC_MARK,
+
+        FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
+        NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK,
+        FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK,
+
+        DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK,
+
+        AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK,
+
+        STATUS0_MARK, PDSTATUS_MARK,
+
+        TPUTO3_MARK, TPUTO2_MARK, TPUTO1_MARK, TPUTO0_MARK,
+
+        D31_MARK, D30_MARK, D29_MARK, D28_MARK,
+        D27_MARK, D26_MARK, D25_MARK, D24_MARK,
+        D23_MARK, D22_MARK, D21_MARK, D20_MARK,
+        D19_MARK, D18_MARK, D17_MARK, D16_MARK,
+        IOIS16_MARK, WAIT_MARK, BS_MARK,
+        A25_MARK, A24_MARK, A23_MARK, A22_MARK,
+        CS6B_CE1B_MARK, CS6A_CE2B_MARK,
+        CS5B_CE1A_MARK, CS5A_CE2A_MARK,
+        WE3_ICIOWR_MARK, WE2_ICIORD_MARK,
+
+        IDED15_MARK, IDED14_MARK, IDED13_MARK, IDED12_MARK,
+        IDED11_MARK, IDED10_MARK, IDED9_MARK, IDED8_MARK,
+        IDED7_MARK, IDED6_MARK, IDED5_MARK, IDED4_MARK,
+        IDED3_MARK, IDED2_MARK, IDED1_MARK, IDED0_MARK,
+        DIRECTION_MARK, EXBUF_ENB_MARK, IDERST_MARK, IODACK_MARK,
+        IODREQ_MARK, IDEIORDY_MARK, IDEINT_MARK, IDEIOWR_MARK,
+        IDEIORD_MARK, IDECS1_MARK, IDECS0_MARK, IDEA2_MARK,
+        IDEA1_MARK, IDEA0_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA GPIO */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
+
+        /* PTB GPIO */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
+
+        /* PTC GPIO */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
+        PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
+        PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
+
+        /* PTD GPIO */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
+        PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
+        PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
+        PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
+        PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
+        PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
+        PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
+        PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
+
+        /* PTE GPIO */
+        PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
+        PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
+        PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
+        PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
+        PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
+        PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
+
+        /* PTF GPIO */
+        PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
+        PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
+        PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
+        PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
+        PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
+        PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
+        PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
+
+        /* PTG GPIO */
+        PINMUX_DATA(PTG5_DATA, PTG5_OUT),
+        PINMUX_DATA(PTG4_DATA, PTG4_OUT),
+        PINMUX_DATA(PTG3_DATA, PTG3_OUT),
+        PINMUX_DATA(PTG2_DATA, PTG2_OUT),
+        PINMUX_DATA(PTG1_DATA, PTG1_OUT),
+        PINMUX_DATA(PTG0_DATA, PTG0_OUT),
+
+        /* PTH GPIO */
+        PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
+        PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
+        PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
+        PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
+        PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
+        PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
+        PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
+        PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
+
+        /* PTJ GPIO */
+        PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
+        PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
+        PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
+
+        /* PTK GPIO */
+        PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
+        PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
+        PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
+        PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
+        PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
+        PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
+        PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
+
+        /* PTL GPIO */
+        PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
+        PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
+        PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
+        PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
+        PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
+        PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
+        PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
+        PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
+
+        /* PTM GPIO */
+        PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT),
+        PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
+        PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
+        PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
+        PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
+        PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
+        PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
+        PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
+
+        /* PTN GPIO */
+        PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
+        PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
+        PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
+        PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
+        PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
+        PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
+        PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
+        PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
+
+        /* PTQ GPIO */
+        PINMUX_DATA(PTQ3_DATA, PTQ3_IN),
+        PINMUX_DATA(PTQ2_DATA, PTQ2_IN),
+        PINMUX_DATA(PTQ1_DATA, PTQ1_IN),
+        PINMUX_DATA(PTQ0_DATA, PTQ0_IN),
+
+        /* PTR GPIO */
+        PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
+        PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
+        PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
+        PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
+        PINMUX_DATA(PTR3_DATA, PTR3_IN),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
+        PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
+        PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
+
+        /* PTS GPIO */
+        PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
+        PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
+        PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
+        PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
+        PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
+        PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
+
+        /* PTT GPIO */
+        PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
+        PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
+        PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
+        PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
+        PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
+
+        /* PTU GPIO */
+        PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
+        PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
+        PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
+        PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
+        PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
+
+        /* PTV GPIO */
+        PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
+        PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
+        PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
+        PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
+        PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
+        PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
+        PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
+        PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
+
+        /* PTW GPIO */
+        PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
+        PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
+        PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
+        PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
+        PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
+        PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
+        PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
+        PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
+
+        /* PTX GPIO */
+        PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
+        PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
+        PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
+        PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
+        PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
+        PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
+        PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
+        PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
+
+        /* PTY GPIO */
+        PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
+        PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
+        PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
+        PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
+        PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
+        PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
+        PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
+        PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
+
+        /* PTZ GPIO */
+        PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
+        PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
+        PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
+        PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
+        PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
+        PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
+        PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
+        PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
+
+        /* PTA FN */
+        PINMUX_DATA(D23_MARK, PSA15_PSA14_FN1, PTA7_FN),
+        PINMUX_DATA(KEYOUT2_MARK, PSA15_PSA14_FN2, PTA7_FN),
+        PINMUX_DATA(D22_MARK, PSA15_PSA14_FN1, PTA6_FN),
+        PINMUX_DATA(KEYOUT1_MARK, PSA15_PSA14_FN2, PTA6_FN),
+        PINMUX_DATA(D21_MARK, PSA15_PSA14_FN1, PTA5_FN),
+        PINMUX_DATA(KEYOUT0_MARK, PSA15_PSA14_FN2, PTA5_FN),
+        PINMUX_DATA(D20_MARK, PSA15_PSA14_FN1, PTA4_FN),
+        PINMUX_DATA(KEYIN4_MARK, PSA15_PSA14_FN2, PTA4_FN),
+        PINMUX_DATA(D19_MARK, PSA15_PSA14_FN1, PTA3_FN),
+        PINMUX_DATA(KEYIN3_MARK, PSA15_PSA14_FN2, PTA3_FN),
+        PINMUX_DATA(D18_MARK, PSA15_PSA14_FN1, PTA2_FN),
+        PINMUX_DATA(KEYIN2_MARK, PSA15_PSA14_FN2, PTA2_FN),
+        PINMUX_DATA(D17_MARK, PSA15_PSA14_FN1, PTA1_FN),
+        PINMUX_DATA(KEYIN1_MARK, PSA15_PSA14_FN2, PTA1_FN),
+        PINMUX_DATA(D16_MARK, PSA15_PSA14_FN1, PTA0_FN),
+        PINMUX_DATA(KEYIN0_MARK, PSA15_PSA14_FN2, PTA0_FN),
+
+        /* PTB FN */
+        PINMUX_DATA(D31_MARK, PTB7_FN),
+        PINMUX_DATA(D30_MARK, PTB6_FN),
+        PINMUX_DATA(D29_MARK, PTB5_FN),
+        PINMUX_DATA(D28_MARK, PTB4_FN),
+        PINMUX_DATA(D27_MARK, PTB3_FN),
+        PINMUX_DATA(D26_MARK, PSA15_PSA14_FN1, PTB2_FN),
+        PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_PSA14_FN2, PTB2_FN),
+        PINMUX_DATA(D25_MARK, PSA15_PSA14_FN1, PTB1_FN),
+        PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_PSA14_FN2, PTB1_FN),
+        PINMUX_DATA(D24_MARK, PSA15_PSA14_FN1, PTB0_FN),
+        PINMUX_DATA(KEYOUT3_MARK, PSA15_PSA14_FN2, PTB0_FN),
+
+        /* PTC FN */
+        PINMUX_DATA(IDED15_MARK, PSA11_PSA10_FN1, PTC7_FN),
+        PINMUX_DATA(SDHI1CD_MARK, PSA11_PSA10_FN2, PTC7_FN),
+        PINMUX_DATA(IDED14_MARK, PSA11_PSA10_FN1, PTC6_FN),
+        PINMUX_DATA(SDHI1WP_MARK, PSA11_PSA10_FN2, PTC6_FN),
+        PINMUX_DATA(IDED13_MARK, PSA11_PSA10_FN1, PTC5_FN),
+        PINMUX_DATA(SDHI1D3_MARK, PSA11_PSA10_FN2, PTC5_FN),
+        PINMUX_DATA(IDED12_MARK, PSA11_PSA10_FN1, PTC4_FN),
+        PINMUX_DATA(SDHI1D2_MARK, PSA11_PSA10_FN2, PTC4_FN),
+        PINMUX_DATA(IDED11_MARK, PSA11_PSA10_FN1, PTC3_FN),
+        PINMUX_DATA(SDHI1D1_MARK, PSA11_PSA10_FN2, PTC3_FN),
+        PINMUX_DATA(IDED10_MARK, PSA11_PSA10_FN1, PTC2_FN),
+        PINMUX_DATA(SDHI1D0_MARK, PSA11_PSA10_FN2, PTC2_FN),
+        PINMUX_DATA(IDED9_MARK, PSA11_PSA10_FN1, PTC1_FN),
+        PINMUX_DATA(SDHI1CMD_MARK, PSA11_PSA10_FN2, PTC1_FN),
+        PINMUX_DATA(IDED8_MARK, PSA11_PSA10_FN1, PTC0_FN),
+        PINMUX_DATA(SDHI1CLK_MARK, PSA11_PSA10_FN2, PTC0_FN),
+
+        /* PTD FN */
+        PINMUX_DATA(IDED7_MARK, PSA11_PSA10_FN1, PTD7_FN),
+        PINMUX_DATA(SDHI0CD_PTD_MARK, PSA11_PSA10_FN2, PTD7_FN),
+        PINMUX_DATA(IDED6_MARK, PSA11_PSA10_FN1, PTD6_FN),
+        PINMUX_DATA(SDHI0WP_PTD_MARK, PSA11_PSA10_FN2, PTD6_FN),
+        PINMUX_DATA(IDED5_MARK, PSA11_PSA10_FN1, PTD5_FN),
+        PINMUX_DATA(SDHI0D3_PTD_MARK, PSA11_PSA10_FN2, PTD5_FN),
+        PINMUX_DATA(IDED4_MARK, PSA11_PSA10_FN1, PTD4_FN),
+        PINMUX_DATA(SDHI0D2_PTD_MARK, PSA11_PSA10_FN2, PTD4_FN),
+        PINMUX_DATA(IDED3_MARK, PSA11_PSA10_FN1, PTD3_FN),
+        PINMUX_DATA(SDHI0D1_PTD_MARK, PSA11_PSA10_FN2, PTD3_FN),
+        PINMUX_DATA(IDED2_MARK, PSA11_PSA10_FN1, PTD2_FN),
+        PINMUX_DATA(SDHI0D0_PTD_MARK, PSA11_PSA10_FN2, PTD2_FN),
+        PINMUX_DATA(IDED1_MARK, PSA11_PSA10_FN1, PTD1_FN),
+        PINMUX_DATA(SDHI0CMD_PTD_MARK, PSA11_PSA10_FN2, PTD1_FN),
+        PINMUX_DATA(IDED0_MARK, PSA11_PSA10_FN1, PTD0_FN),
+        PINMUX_DATA(SDHI0CLK_PTD_MARK, PSA11_PSA10_FN2, PTD0_FN),
+
+        /* PTE FN */
+        PINMUX_DATA(DIRECTION_MARK, PSA11_PSA10_FN1, PTE5_FN),
+        PINMUX_DATA(SCIF5_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE5_FN),
+        PINMUX_DATA(EXBUF_ENB_MARK, PSA11_PSA10_FN1, PTE4_FN),
+        PINMUX_DATA(SCIF5_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE4_FN),
+        PINMUX_DATA(IDERST_MARK, PSA11_PSA10_FN1, PTE3_FN),
+        PINMUX_DATA(SCIF5_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE3_FN),
+        PINMUX_DATA(IODACK_MARK, PSA11_PSA10_FN1, PTE2_FN),
+        PINMUX_DATA(SCIF4_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE2_FN),
+        PINMUX_DATA(IODREQ_MARK, PSA11_PSA10_FN1, PTE1_FN),
+        PINMUX_DATA(SCIF4_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE1_FN),
+        PINMUX_DATA(IDEIORDY_MARK, PSA11_PSA10_FN1, PTE0_FN),
+        PINMUX_DATA(SCIF4_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE0_FN),
+
+        /* PTF FN */
+        PINMUX_DATA(IDEINT_MARK, PTF7_FN),
+        PINMUX_DATA(IDEIOWR_MARK, PSA5_PSA4_FN1, PTF6_FN),
+        PINMUX_DATA(MSIOF0_PTF_SS2_MARK, PSA5_PSA4_FN2, PTF6_FN),
+        PINMUX_DATA(MSIOF0_PTF_RSYNC_MARK, PSA5_PSA4_FN3, PTF6_FN),
+        PINMUX_DATA(IDEIORD_MARK, PSA5_PSA4_FN1, PTF5_FN),
+        PINMUX_DATA(MSIOF0_PTF_SS1_MARK, PSA5_PSA4_FN2, PTF5_FN),
+        PINMUX_DATA(MSIOF0_PTF_RSCK_MARK, PSA5_PSA4_FN3, PTF5_FN),
+        PINMUX_DATA(IDECS1_MARK, PSA11_PSA10_FN1, PTF4_FN),
+        PINMUX_DATA(MSIOF0_PTF_TSYNC_MARK, PSA11_PSA10_FN2, PTF4_FN),
+        PINMUX_DATA(IDECS0_MARK, PSA11_PSA10_FN1, PTF3_FN),
+        PINMUX_DATA(MSIOF0_PTF_TSCK_MARK, PSA11_PSA10_FN2, PTF3_FN),
+        PINMUX_DATA(IDEA2_MARK, PSA11_PSA10_FN1, PTF2_FN),
+        PINMUX_DATA(MSIOF0_PTF_RXD_MARK, PSA11_PSA10_FN2, PTF2_FN),
+        PINMUX_DATA(IDEA1_MARK, PSA11_PSA10_FN1, PTF1_FN),
+        PINMUX_DATA(MSIOF0_PTF_TXD_MARK, PSA11_PSA10_FN2, PTF1_FN),
+        PINMUX_DATA(IDEA0_MARK, PSA11_PSA10_FN1, PTF0_FN),
+        PINMUX_DATA(MSIOF0_PTF_MCK_MARK, PSA11_PSA10_FN2, PTF0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(AUDCK_MARK, PTG5_FN),
+        PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
+        PINMUX_DATA(AUDATA3_MARK, PSA3_PSA2_FN1, PTG3_FN),
+        PINMUX_DATA(TPUTO3_MARK, PSA3_PSA2_FN2, PTG3_FN),
+        PINMUX_DATA(AUDATA2_MARK, PSA3_PSA2_FN1, PTG2_FN),
+        PINMUX_DATA(TPUTO2_MARK, PSA3_PSA2_FN2, PTG2_FN),
+        PINMUX_DATA(AUDATA1_MARK, PSA3_PSA2_FN1, PTG1_FN),
+        PINMUX_DATA(TPUTO1_MARK, PSA3_PSA2_FN2, PTG1_FN),
+        PINMUX_DATA(AUDATA0_MARK, PSA3_PSA2_FN1, PTG0_FN),
+        PINMUX_DATA(TPUTO0_MARK, PSA3_PSA2_FN2, PTG0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(LCDVCPWC_MARK, PTH7_FN),
+        PINMUX_DATA(LCDRD_MARK, PSB15_PSB14_FN1, PTH6_FN),
+        PINMUX_DATA(DV_CLKI_MARK, PSB15_PSB14_FN2, PTH6_FN),
+        PINMUX_DATA(LCDVSYN_MARK, PSB15_PSB14_FN1, PTH5_FN),
+        PINMUX_DATA(DV_CLK_MARK, PSB15_PSB14_FN2, PTH5_FN),
+        PINMUX_DATA(LCDDISP_MARK, PSB13_PSB12_LCDC_RGB, PTH4_FN),
+        PINMUX_DATA(LCDRS_MARK, PSB13_PSB12_LCDC_SYS, PTH4_FN),
+        PINMUX_DATA(LCDHSYN_MARK, PSB13_PSB12_LCDC_RGB, PTH3_FN),
+        PINMUX_DATA(LCDCS_MARK, PSB13_PSB12_LCDC_SYS, PTH3_FN),
+        PINMUX_DATA(LCDDON_MARK, PTH2_FN),
+        PINMUX_DATA(LCDDCK_MARK, PSB13_PSB12_LCDC_RGB, PTH1_FN),
+        PINMUX_DATA(LCDWR_MARK, PSB13_PSB12_LCDC_SYS, PTH1_FN),
+        PINMUX_DATA(LCDVEPWC_MARK, PTH0_FN),
+
+        /* PTJ FN */
+        PINMUX_DATA(STATUS0_MARK, PTJ7_FN),
+        PINMUX_DATA(PDSTATUS_MARK, PTJ5_FN),
+        PINMUX_DATA(A25_MARK, PTJ3_FN),
+        PINMUX_DATA(A24_MARK, PTJ2_FN),
+        PINMUX_DATA(A23_MARK, PTJ1_FN),
+        PINMUX_DATA(A22_MARK, PTJ0_FN),
+
+        /* PTK FN */
+        PINMUX_DATA(SIUAFCK_MARK, PTK7_FN),
+        PINMUX_DATA(SIUAILR_MARK, PSB9_PSB8_FN1, PTK6_FN),
+        PINMUX_DATA(MSIOF1_SS2_MARK, PSB9_PSB8_FN2, PTK6_FN),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK, PSB9_PSB8_FN3, PTK6_FN),
+        PINMUX_DATA(SIUAIBT_MARK, PSB9_PSB8_FN1, PTK5_FN),
+        PINMUX_DATA(MSIOF1_SS1_MARK, PSB9_PSB8_FN2, PTK5_FN),
+        PINMUX_DATA(MSIOF1_RSCK_MARK, PSB9_PSB8_FN3, PTK5_FN),
+        PINMUX_DATA(SIUAISLD_MARK, PSB7_PSB6_FN1, PTK4_FN),
+        PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK4_FN),
+        PINMUX_DATA(SIUAOLR_MARK, PSB7_PSB6_FN1, PTK3_FN),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK, PSB7_PSB6_FN2, PTK3_FN),
+        PINMUX_DATA(SIUAOBT_MARK, PSB7_PSB6_FN1, PTK2_FN),
+        PINMUX_DATA(MSIOF1_TSCK_MARK, PSB7_PSB6_FN2, PTK2_FN),
+        PINMUX_DATA(SIUAOSLD_MARK, PSB7_PSB6_FN1, PTK1_FN),
+        PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK1_FN),
+        PINMUX_DATA(SIUAMCK_MARK, PSB7_PSB6_FN1, PTK0_FN),
+        PINMUX_DATA(MSIOF1_MCK_MARK, PSB7_PSB6_FN2, PTK0_FN),
+
+        /* PTL FN */
+        PINMUX_DATA(LCDD15_MARK, PSB5_PSB4_FN1, PTL7_FN),
+        PINMUX_DATA(DV_D15_MARK, PSB5_PSB4_FN2, PTL7_FN),
+        PINMUX_DATA(LCDD14_MARK, PSB5_PSB4_FN1, PTL6_FN),
+        PINMUX_DATA(DV_D14_MARK, PSB5_PSB4_FN2, PTL6_FN),
+        PINMUX_DATA(LCDD13_MARK, PSB5_PSB4_FN1, PTL5_FN),
+        PINMUX_DATA(DV_D13_MARK, PSB5_PSB4_FN2, PTL5_FN),
+        PINMUX_DATA(LCDD12_MARK, PSB5_PSB4_FN1, PTL4_FN),
+        PINMUX_DATA(DV_D12_MARK, PSB5_PSB4_FN2, PTL4_FN),
+        PINMUX_DATA(LCDD11_MARK, PSB5_PSB4_FN1, PTL3_FN),
+        PINMUX_DATA(DV_D11_MARK, PSB5_PSB4_FN2, PTL3_FN),
+        PINMUX_DATA(LCDD10_MARK, PSB5_PSB4_FN1, PTL2_FN),
+        PINMUX_DATA(DV_D10_MARK, PSB5_PSB4_FN2, PTL2_FN),
+        PINMUX_DATA(LCDD9_MARK, PSB5_PSB4_FN1, PTL1_FN),
+        PINMUX_DATA(DV_D9_MARK, PSB5_PSB4_FN2, PTL1_FN),
+        PINMUX_DATA(LCDD8_MARK, PSB5_PSB4_FN1, PTL0_FN),
+        PINMUX_DATA(DV_D8_MARK, PSB5_PSB4_FN2, PTL0_FN),
+
+        /* PTM FN */
+        PINMUX_DATA(LCDD7_MARK, PSB5_PSB4_FN1, PTM7_FN),
+        PINMUX_DATA(DV_D7_MARK, PSB5_PSB4_FN2, PTM7_FN),
+        PINMUX_DATA(LCDD6_MARK, PSB5_PSB4_FN1, PTM6_FN),
+        PINMUX_DATA(DV_D6_MARK, PSB5_PSB4_FN2, PTM6_FN),
+        PINMUX_DATA(LCDD5_MARK, PSB5_PSB4_FN1, PTM5_FN),
+        PINMUX_DATA(DV_D5_MARK, PSB5_PSB4_FN2, PTM5_FN),
+        PINMUX_DATA(LCDD4_MARK, PSB5_PSB4_FN1, PTM4_FN),
+        PINMUX_DATA(DV_D4_MARK, PSB5_PSB4_FN2, PTM4_FN),
+        PINMUX_DATA(LCDD3_MARK, PSB5_PSB4_FN1, PTM3_FN),
+        PINMUX_DATA(DV_D3_MARK, PSB5_PSB4_FN2, PTM3_FN),
+        PINMUX_DATA(LCDD2_MARK, PSB5_PSB4_FN1, PTM2_FN),
+        PINMUX_DATA(DV_D2_MARK, PSB5_PSB4_FN2, PTM2_FN),
+        PINMUX_DATA(LCDD1_MARK, PSB5_PSB4_FN1, PTM1_FN),
+        PINMUX_DATA(DV_D1_MARK, PSB5_PSB4_FN2, PTM1_FN),
+        PINMUX_DATA(LCDD0_MARK, PSB5_PSB4_FN1, PTM0_FN),
+        PINMUX_DATA(DV_D0_MARK, PSB5_PSB4_FN2, PTM0_FN),
+
+        /* PTN FN */
+        PINMUX_DATA(LCDD23_MARK, PSB3_PSB2_FN1, PTN7_FN),
+        PINMUX_DATA(SCIF5_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN7_FN),
+        PINMUX_DATA(LCDD22_MARK, PSB3_PSB2_FN1, PTN6_FN),
+        PINMUX_DATA(SCIF5_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN6_FN),
+        PINMUX_DATA(LCDD21_MARK, PSB3_PSB2_FN1, PTN5_FN),
+        PINMUX_DATA(SCIF5_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN5_FN),
+        PINMUX_DATA(LCDD20_MARK, PSB3_PSB2_FN1, PTN4_FN),
+        PINMUX_DATA(SCIF4_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN4_FN),
+        PINMUX_DATA(LCDD19_MARK, PSB3_PSB2_FN1, PTN3_FN),
+        PINMUX_DATA(SCIF4_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN3_FN),
+        PINMUX_DATA(LCDD18_MARK, PSB3_PSB2_FN1, PTN2_FN),
+        PINMUX_DATA(SCIF4_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN2_FN),
+        PINMUX_DATA(LCDD17_MARK, PSB5_PSB4_FN1, PTN1_FN),
+        PINMUX_DATA(DV_VSYNC_MARK, PSB5_PSB4_FN2, PTN1_FN),
+        PINMUX_DATA(LCDD16_MARK, PSB5_PSB4_FN1, PTN0_FN),
+        PINMUX_DATA(DV_HSYNC_MARK, PSB5_PSB4_FN2, PTN0_FN),
+
+        /* PTQ FN */
+        PINMUX_DATA(AN3_MARK, PTQ3_FN),
+        PINMUX_DATA(AN2_MARK, PTQ2_FN),
+        PINMUX_DATA(AN1_MARK, PTQ1_FN),
+        PINMUX_DATA(AN0_MARK, PTQ0_FN),
+
+        /* PTR FN */
+        PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN),
+        PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN),
+        PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN),
+        PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN),
+        PINMUX_DATA(IOIS16_MARK, PSA13_PSA12_FN1, PTR3_FN),
+        PINMUX_DATA(LCDLCLK_PTR_MARK, PSA13_PSA12_FN2, PTR3_FN),
+        PINMUX_DATA(WAIT_MARK, PTR2_FN),
+        PINMUX_DATA(WE3_ICIOWR_MARK, PTR1_FN),
+        PINMUX_DATA(WE2_ICIORD_MARK, PTR0_FN),
+
+        /* PTS FN */
+        PINMUX_DATA(SCIF1_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS7_FN),
+        PINMUX_DATA(SDHI0CD_PTS_MARK, PSC15_PSC14_FN2, PTS7_FN),
+        PINMUX_DATA(SCIF1_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS6_FN),
+        PINMUX_DATA(SDHI0WP_PTS_MARK, PSC15_PSC14_FN2, PTS6_FN),
+        PINMUX_DATA(SCIF1_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS5_FN),
+        PINMUX_DATA(SDHI0D3_PTS_MARK, PSC15_PSC14_FN2, PTS5_FN),
+        PINMUX_DATA(SCIF3_PTS_CTS_MARK, PSC15_PSC14_FN1, PTS4_FN),
+        PINMUX_DATA(SDHI0D2_PTS_MARK, PSC15_PSC14_FN2, PTS4_FN),
+        PINMUX_DATA(SCIF3_PTS_RTS_MARK, PSC15_PSC14_FN1, PTS3_FN),
+        PINMUX_DATA(SDHI0D1_PTS_MARK, PSC15_PSC14_FN2, PTS3_FN),
+        PINMUX_DATA(SCIF3_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS2_FN),
+        PINMUX_DATA(SDHI0D0_PTS_MARK, PSC15_PSC14_FN2, PTS2_FN),
+        PINMUX_DATA(SCIF3_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS1_FN),
+        PINMUX_DATA(SDHI0CMD_PTS_MARK, PSC15_PSC14_FN2, PTS1_FN),
+        PINMUX_DATA(SCIF3_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS0_FN),
+        PINMUX_DATA(SDHI0CLK_PTS_MARK, PSC15_PSC14_FN2, PTS0_FN),
+
+        /* PTT FN */
+        PINMUX_DATA(SCIF0_PTT_SCK_MARK, PSC13_PSC12_FN1, PTT5_FN),
+        PINMUX_DATA(MSIOF0_PTT_TSCK_MARK, PSC13_PSC12_FN2, PTT5_FN),
+        PINMUX_DATA(SCIF0_PTT_RXD_MARK, PSC13_PSC12_FN1, PTT4_FN),
+        PINMUX_DATA(MSIOF0_PTT_RXD_MARK, PSC13_PSC12_FN2, PTT4_FN),
+        PINMUX_DATA(SCIF0_PTT_TXD_MARK, PSC13_PSC12_FN1, PTT3_FN),
+        PINMUX_DATA(MSIOF0_PTT_TXD_MARK, PSC13_PSC12_FN2, PTT3_FN),
+        PINMUX_DATA(SCIF2_PTT_SCK_MARK, PSC11_PSC10_FN1, PTT2_FN),
+        PINMUX_DATA(MSIOF0_PTT_TSYNC_MARK, PSC11_PSC10_FN2, PTT2_FN),
+        PINMUX_DATA(SCIF2_PTT_RXD_MARK, PSC11_PSC10_FN1, PTT1_FN),
+        PINMUX_DATA(MSIOF0_PTT_SS1_MARK, PSC11_PSC10_FN2, PTT1_FN),
+        PINMUX_DATA(MSIOF0_PTT_RSCK_MARK, PSC11_PSC10_FN3, PTT1_FN),
+        PINMUX_DATA(SCIF2_PTT_TXD_MARK, PSC11_PSC10_FN1, PTT0_FN),
+        PINMUX_DATA(MSIOF0_PTT_SS2_MARK, PSC11_PSC10_FN2, PTT0_FN),
+        PINMUX_DATA(MSIOF0_PTT_RSYNC_MARK, PSC11_PSC10_FN3, PTT0_FN),
+
+        /* PTU FN */
+        PINMUX_DATA(FCDE_MARK, PSC9_PSC8_FN1, PTU5_FN),
+        PINMUX_DATA(SCIF0_PTU_SCK_MARK, PSC9_PSC8_FN2, PTU5_FN),
+        PINMUX_DATA(FSC_MARK, PSC9_PSC8_FN1, PTU4_FN),
+        PINMUX_DATA(SCIF0_PTU_RXD_MARK, PSC9_PSC8_FN2, PTU4_FN),
+        PINMUX_DATA(FWE_MARK, PSC9_PSC8_FN1, PTU3_FN),
+        PINMUX_DATA(SCIF0_PTU_TXD_MARK, PSC9_PSC8_FN2, PTU3_FN),
+        PINMUX_DATA(FOE_MARK, PSC7_PSC6_FN1, PTU2_FN),
+        PINMUX_DATA(SCIF2_PTU_SCK_MARK, PSC7_PSC6_FN2, PTU2_FN),
+        PINMUX_DATA(VIO_VD2_MARK, PSC7_PSC6_FN3, PTU2_FN),
+        PINMUX_DATA(FRB_MARK, PSC7_PSC6_FN1, PTU1_FN),
+        PINMUX_DATA(SCIF2_PTU_RXD_MARK, PSC7_PSC6_FN2, PTU1_FN),
+        PINMUX_DATA(VIO_CLK2_MARK, PSC7_PSC6_FN3, PTU1_FN),
+        PINMUX_DATA(FCE_MARK, PSC7_PSC6_FN1, PTU0_FN),
+        PINMUX_DATA(SCIF2_PTU_TXD_MARK, PSC7_PSC6_FN2, PTU0_FN),
+        PINMUX_DATA(VIO_HD2_MARK, PSC7_PSC6_FN3, PTU0_FN),
+
+        /* PTV FN */
+        PINMUX_DATA(NAF7_MARK, PSC7_PSC6_FN1, PTV7_FN),
+        PINMUX_DATA(SCIF1_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV7_FN),
+        PINMUX_DATA(VIO_D15_MARK, PSC7_PSC6_FN3, PTV7_FN),
+        PINMUX_DATA(NAF6_MARK, PSC7_PSC6_FN1, PTV6_FN),
+        PINMUX_DATA(SCIF1_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV6_FN),
+        PINMUX_DATA(VIO_D14_MARK, PSC7_PSC6_FN3, PTV6_FN),
+        PINMUX_DATA(NAF5_MARK, PSC7_PSC6_FN1, PTV5_FN),
+        PINMUX_DATA(SCIF1_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV5_FN),
+        PINMUX_DATA(VIO_D13_MARK, PSC7_PSC6_FN3, PTV5_FN),
+        PINMUX_DATA(NAF4_MARK, PSC7_PSC6_FN1, PTV4_FN),
+        PINMUX_DATA(SCIF3_PTV_CTS_MARK, PSC7_PSC6_FN2, PTV4_FN),
+        PINMUX_DATA(VIO_D12_MARK, PSC7_PSC6_FN3, PTV4_FN),
+        PINMUX_DATA(NAF3_MARK, PSC7_PSC6_FN1, PTV3_FN),
+        PINMUX_DATA(SCIF3_PTV_RTS_MARK, PSC7_PSC6_FN2, PTV3_FN),
+        PINMUX_DATA(VIO_D11_MARK, PSC7_PSC6_FN3, PTV3_FN),
+        PINMUX_DATA(NAF2_MARK, PSC7_PSC6_FN1, PTV2_FN),
+        PINMUX_DATA(SCIF3_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV2_FN),
+        PINMUX_DATA(VIO_D10_MARK, PSC7_PSC6_FN3, PTV2_FN),
+        PINMUX_DATA(NAF1_MARK, PSC7_PSC6_FN1, PTV1_FN),
+        PINMUX_DATA(SCIF3_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV1_FN),
+        PINMUX_DATA(VIO_D9_MARK, PSC7_PSC6_FN3, PTV1_FN),
+        PINMUX_DATA(NAF0_MARK, PSC7_PSC6_FN1, PTV0_FN),
+        PINMUX_DATA(SCIF3_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV0_FN),
+        PINMUX_DATA(VIO_D8_MARK, PSC7_PSC6_FN3, PTV0_FN),
+
+        /* PTW FN */
+        PINMUX_DATA(IRQ7_MARK, PTW7_FN),
+        PINMUX_DATA(IRQ6_MARK, PTW6_FN),
+        PINMUX_DATA(IRQ5_MARK, PTW5_FN),
+        PINMUX_DATA(IRQ4_MARK, PSD15_PSD14_FN1, PTW4_FN),
+        PINMUX_DATA(LCDLCLK_PTW_MARK, PSD15_PSD14_FN2, PTW4_FN),
+        PINMUX_DATA(IRQ3_MARK, PSD13_PSD12_FN1, PTW3_FN),
+        PINMUX_DATA(ADTRG_MARK, PSD13_PSD12_FN2, PTW3_FN),
+        PINMUX_DATA(IRQ2_MARK, PSD11_PSD10_FN1, PTW2_FN),
+        PINMUX_DATA(BS_MARK, PSD11_PSD10_FN2, PTW2_FN),
+        PINMUX_DATA(VIO_CKO_MARK, PSD11_PSD10_FN3, PTW2_FN),
+        PINMUX_DATA(IRQ1_MARK, PSD9_PSD8_FN1, PTW1_FN),
+        PINMUX_DATA(SIUAISPD_MARK, PSD9_PSD8_FN2, PTW1_FN),
+        PINMUX_DATA(IRQ0_MARK, PSD7_PSD6_FN1, PTW0_FN),
+        PINMUX_DATA(SIUAOSPD_MARK, PSD7_PSD6_FN2, PTW0_FN),
+
+        /* PTX FN */
+        PINMUX_DATA(DACK1_MARK, PTX7_FN),
+        PINMUX_DATA(DREQ1_MARK, PSD3_PSD2_FN1, PTX6_FN),
+        PINMUX_DATA(MSIOF0_PTX_MCK_MARK, PSD3_PSD2_FN2, PTX6_FN),
+        PINMUX_DATA(DACK1_MARK, PTX5_FN),
+        PINMUX_DATA(IRDA_OUT_MARK, PSD5_PSD4_FN2, PTX5_FN),
+        PINMUX_DATA(DREQ1_MARK, PTX4_FN),
+        PINMUX_DATA(IRDA_IN_MARK, PSD5_PSD4_FN2, PTX4_FN),
+        PINMUX_DATA(TS0_SDAT_MARK, PTX3_FN),
+        PINMUX_DATA(TS0_SCK_MARK, PTX2_FN),
+        PINMUX_DATA(TS0_SDEN_MARK, PTX1_FN),
+        PINMUX_DATA(TS0_SPSYNC_MARK, PTX0_FN),
+
+        /* PTY FN */
+        PINMUX_DATA(VIO_D7_MARK, PTY7_FN),
+        PINMUX_DATA(VIO_D6_MARK, PTY6_FN),
+        PINMUX_DATA(VIO_D5_MARK, PTY5_FN),
+        PINMUX_DATA(VIO_D4_MARK, PTY4_FN),
+        PINMUX_DATA(VIO_D3_MARK, PTY3_FN),
+        PINMUX_DATA(VIO_D2_MARK, PTY2_FN),
+        PINMUX_DATA(VIO_D1_MARK, PTY1_FN),
+        PINMUX_DATA(VIO_D0_MARK, PTY0_FN),
+
+        /* PTZ FN */
+        PINMUX_DATA(SIUBOBT_MARK, PTZ7_FN),
+        PINMUX_DATA(SIUBOLR_MARK, PTZ6_FN),
+        PINMUX_DATA(SIUBOSLD_MARK, PTZ5_FN),
+        PINMUX_DATA(SIUBMCK_MARK, PTZ4_FN),
+        PINMUX_DATA(VIO_FLD_MARK, PSD1_PSD0_FN1, PTZ3_FN),
+        PINMUX_DATA(SIUBFCK_MARK, PSD1_PSD0_FN2, PTZ3_FN),
+        PINMUX_DATA(VIO_HD1_MARK, PSD1_PSD0_FN1, PTZ2_FN),
+        PINMUX_DATA(SIUBILR_MARK, PSD1_PSD0_FN2, PTZ2_FN),
+        PINMUX_DATA(VIO_VD1_MARK, PSD1_PSD0_FN1, PTZ1_FN),
+        PINMUX_DATA(SIUBIBT_MARK, PSD1_PSD0_FN2, PTZ1_FN),
+        PINMUX_DATA(VIO_CLK1_MARK, PSD1_PSD0_FN1, PTZ0_FN),
+        PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
+        PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
+        PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
+        PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
+        PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
+        PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+        PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
+        PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
+        PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTN */
+        PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
+        PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
+        PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
+        PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
+        PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
+        PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
+        PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
+        PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
+
+        /* PTQ */
+        PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
+        PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
+        PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
+        PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
+        PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
+        PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
+        PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
+        PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
+        PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
+        PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* PTW */
+        PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
+        PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
+        PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
+        PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
+        PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
+        PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
+        PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
+        PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
+
+        /* PTX */
+        PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
+        PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
+        PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
+        PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
+        PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
+        PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
+        PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
+        PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
+
+        /* PTY */
+        PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
+        PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
+        PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
+        PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
+        PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
+        PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
+        PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
+        PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
+
+        /* PTZ */
+        PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
+        PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
+        PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
+        PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
+        PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
+        PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
+        PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+        PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+
+        /* SCIF0 */
+        PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK),
+
+        /* SCIF1 */
+        PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK),
+
+        /* SCIF2 */
+        PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK),
+
+        /* SCIF3 */
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK),
+
+        /* SCIF4 */
+        PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK),
+
+        /* SCIF5 */
+        PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK),
+
+        /* CEU */
+        PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
+
+        /* LCDC */
+        PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK),
+        /* Main LCD */
+        PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
+        /* Main LCD - RGB Mode */
+        PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
+        /* Main LCD - SYS Mode */
+        PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
+
+        /* IRQ */
+        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
+
+        /* AUD */
+        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+
+        /* SDHI0 (PTD) */
+        PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK),
+
+        /* SDHI0 (PTS) */
+        PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK),
+
+        /* SDHI1 */
+        PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
+
+        /* SIUA */
+        PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUOSPD, SIUAOSPD_MARK),
+
+        /* SIUB */
+        PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK),
+
+        /* IRDA */
+        PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
+        PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
+
+        /* VOU */
+        PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
+
+        /* KEYSC */
+        PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
+
+        /* MSIOF0 (PTF) */
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK),
+
+        /* MSIOF0 (PTT+PTX) */
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK),
+
+        /* MSIOF1 */
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
+
+        /* TSIF */
+        PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK),
+        PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK),
+        PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK),
+
+        /* FLCTL */
+        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
+        PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
+        PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
+        PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
+        PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
+        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
+        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+
+        /* ADC */
+        PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
+        PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
+        PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
+        PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+
+        /* CPG */
+        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
+        PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
+
+        /* TPU */
+        PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
+
+        /* BSC */
+        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
+        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
+        PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
+
+        /* ATAPI */
+        PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
+        PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
+        PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
+        PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
+        PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
+        PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
+ };
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
+                PTA7_FN, PTA7_OUT, 0, PTA7_IN,
+                PTA6_FN, PTA6_OUT, 0, PTA6_IN,
+                PTA5_FN, PTA5_OUT, 0, PTA5_IN,
+                PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
+                PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
+                PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
+                PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
+                PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
+                PTB7_FN, PTB7_OUT, 0, PTB7_IN,
+                PTB6_FN, PTB6_OUT, 0, PTB6_IN,
+                PTB5_FN, PTB5_OUT, 0, PTB5_IN,
+                PTB4_FN, PTB4_OUT, 0, PTB4_IN,
+                PTB3_FN, PTB3_OUT, 0, PTB3_IN,
+                PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
+                PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
+                PTB0_FN, PTB0_OUT, 0, PTB0_IN }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
+                PTC7_FN, PTC7_OUT, 0, PTC7_IN,
+                PTC6_FN, PTC6_OUT, 0, PTC6_IN,
+                PTC5_FN, PTC5_OUT, 0, PTC5_IN,
+                PTC4_FN, PTC4_OUT, 0, PTC4_IN,
+                PTC3_FN, PTC3_OUT, 0, PTC3_IN,
+                PTC2_FN, PTC2_OUT, 0, PTC2_IN,
+                PTC1_FN, PTC1_OUT, 0, PTC1_IN,
+                PTC0_FN, PTC0_OUT, 0, PTC0_IN }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
+                PTD7_FN, PTD7_OUT, 0, PTD7_IN,
+                PTD6_FN, PTD6_OUT, 0, PTD6_IN,
+                PTD5_FN, PTD5_OUT, 0, PTD5_IN,
+                PTD4_FN, PTD4_OUT, 0, PTD4_IN,
+                PTD3_FN, PTD3_OUT, 0, PTD3_IN,
+                PTD2_FN, PTD2_OUT, 0, PTD2_IN,
+                PTD1_FN, PTD1_OUT, 0, PTD1_IN,
+                PTD0_FN, PTD0_OUT, 0, PTD0_IN }
+        },
+        { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTE5_FN, PTE5_OUT, 0, PTE5_IN,
+                PTE4_FN, PTE4_OUT, 0, PTE4_IN,
+                PTE3_FN, PTE3_OUT, 0, PTE3_IN,
+                PTE2_FN, PTE2_OUT, 0, PTE2_IN,
+                PTE1_FN, PTE1_OUT, 0, PTE1_IN,
+                PTE0_FN, PTE0_OUT, 0, PTE0_IN }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
+                PTF7_FN, PTF7_OUT, 0, PTF7_IN,
+                PTF6_FN, PTF6_OUT, 0, PTF6_IN,
+                PTF5_FN, PTF5_OUT, 0, PTF5_IN,
+                PTF4_FN, PTF4_OUT, 0, PTF4_IN,
+                PTF3_FN, PTF3_OUT, 0, PTF3_IN,
+                PTF2_FN, PTF2_OUT, 0, PTF2_IN,
+                PTF1_FN, PTF1_OUT, 0, PTF1_IN,
+                PTF0_FN, PTF0_OUT, 0, PTF0_IN }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTG5_FN, PTG5_OUT, 0, 0,
+                PTG4_FN, PTG4_OUT, 0, 0,
+                PTG3_FN, PTG3_OUT, 0, 0,
+                PTG2_FN, PTG2_OUT, 0, 0,
+                PTG1_FN, PTG1_OUT, 0, 0,
+                PTG0_FN, PTG0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
+                PTH7_FN, PTH7_OUT, 0, PTH7_IN,
+                PTH6_FN, PTH6_OUT, 0, PTH6_IN,
+                PTH5_FN, PTH5_OUT, 0, PTH5_IN,
+                PTH4_FN, PTH4_OUT, 0, PTH4_IN,
+                PTH3_FN, PTH3_OUT, 0, PTH3_IN,
+                PTH2_FN, PTH2_OUT, 0, PTH2_IN,
+                PTH1_FN, PTH1_OUT, 0, PTH1_IN,
+                PTH0_FN, PTH0_OUT, 0, PTH0_IN }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
+                PTJ7_FN, PTJ7_OUT, 0, 0,
+                0, 0, 0, 0,
+                PTJ5_FN, PTJ5_OUT, 0, 0,
+                0, 0, 0, 0,
+                PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
+                PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
+                PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
+                PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
+                PTK7_FN, PTK7_OUT, 0, PTK7_IN,
+                PTK6_FN, PTK6_OUT, 0, PTK6_IN,
+                PTK5_FN, PTK5_OUT, 0, PTK5_IN,
+                PTK4_FN, PTK4_OUT, 0, PTK4_IN,
+                PTK3_FN, PTK3_OUT, 0, PTK3_IN,
+                PTK2_FN, PTK2_OUT, 0, PTK2_IN,
+                PTK1_FN, PTK1_OUT, 0, PTK1_IN,
+                PTK0_FN, PTK0_OUT, 0, PTK0_IN }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
+                PTL7_FN, PTL7_OUT, 0, PTL7_IN,
+                PTL6_FN, PTL6_OUT, 0, PTL6_IN,
+                PTL5_FN, PTL5_OUT, 0, PTL5_IN,
+                PTL4_FN, PTL4_OUT, 0, PTL4_IN,
+                PTL3_FN, PTL3_OUT, 0, PTL3_IN,
+                PTL2_FN, PTL2_OUT, 0, PTL2_IN,
+                PTL1_FN, PTL1_OUT, 0, PTL1_IN,
+                PTL0_FN, PTL0_OUT, 0, PTL0_IN }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
+                PTM7_FN, PTM7_OUT, 0, PTM7_IN,
+                PTM6_FN, PTM6_OUT, 0, PTM6_IN,
+                PTM5_FN, PTM5_OUT, 0, PTM5_IN,
+                PTM4_FN, PTM4_OUT, 0, PTM4_IN,
+                PTM3_FN, PTM3_OUT, 0, PTM3_IN,
+                PTM2_FN, PTM2_OUT, 0, PTM2_IN,
+                PTM1_FN, PTM1_OUT, 0, PTM1_IN,
+                PTM0_FN, PTM0_OUT, 0, PTM0_IN }
+        },
+        { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
+                PTN7_FN, PTN7_OUT, 0, PTN7_IN,
+                PTN6_FN, PTN6_OUT, 0, PTN6_IN,
+                PTN5_FN, PTN5_OUT, 0, PTN5_IN,
+                PTN4_FN, PTN4_OUT, 0, PTN4_IN,
+                PTN3_FN, PTN3_OUT, 0, PTN3_IN,
+                PTN2_FN, PTN2_OUT, 0, PTN2_IN,
+                PTN1_FN, PTN1_OUT, 0, PTN1_IN,
+                PTN0_FN, PTN0_OUT, 0, PTN0_IN }
+        },
+        { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTQ3_FN, 0, 0, PTQ3_IN,
+                PTQ2_FN, 0, 0, PTQ2_IN,
+                PTQ1_FN, 0, 0, PTQ1_IN,
+                PTQ0_FN, 0, 0, PTQ0_IN }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
+                PTR7_FN, PTR7_OUT, 0, PTR7_IN,
+                PTR6_FN, PTR6_OUT, 0, PTR6_IN,
+                PTR5_FN, PTR5_OUT, 0, PTR5_IN,
+                PTR4_FN, PTR4_OUT, 0, PTR4_IN,
+                PTR3_FN, 0, 0, PTR3_IN,
+                PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
+                PTR1_FN, PTR1_OUT, 0, PTR1_IN,
+                PTR0_FN, PTR0_OUT, 0, PTR0_IN }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
+                PTS7_FN, PTS7_OUT, 0, PTS7_IN,
+                PTS6_FN, PTS6_OUT, 0, PTS6_IN,
+                PTS5_FN, PTS5_OUT, 0, PTS5_IN,
+                PTS4_FN, PTS4_OUT, 0, PTS4_IN,
+                PTS3_FN, PTS3_OUT, 0, PTS3_IN,
+                PTS2_FN, PTS2_OUT, 0, PTS2_IN,
+                PTS1_FN, PTS1_OUT, 0, PTS1_IN,
+                PTS0_FN, PTS0_OUT, 0, PTS0_IN }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTT5_FN, PTT5_OUT, 0, PTT5_IN,
+                PTT4_FN, PTT4_OUT, 0, PTT4_IN,
+                PTT3_FN, PTT3_OUT, 0, PTT3_IN,
+                PTT2_FN, PTT2_OUT, 0, PTT2_IN,
+                PTT1_FN, PTT1_OUT, 0, PTT1_IN,
+                PTT0_FN, PTT0_OUT, 0, PTT0_IN }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTU5_FN, PTU5_OUT, 0, PTU5_IN,
+                PTU4_FN, PTU4_OUT, 0, PTU4_IN,
+                PTU3_FN, PTU3_OUT, 0, PTU3_IN,
+                PTU2_FN, PTU2_OUT, 0, PTU2_IN,
+                PTU1_FN, PTU1_OUT, 0, PTU1_IN,
+                PTU0_FN, PTU0_OUT, 0, PTU0_IN }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
+                PTV7_FN, PTV7_OUT, 0, PTV7_IN,
+                PTV6_FN, PTV6_OUT, 0, PTV6_IN,
+                PTV5_FN, PTV5_OUT, 0, PTV5_IN,
+                PTV4_FN, PTV4_OUT, 0, PTV4_IN,
+                PTV3_FN, PTV3_OUT, 0, PTV3_IN,
+                PTV2_FN, PTV2_OUT, 0, PTV2_IN,
+                PTV1_FN, PTV1_OUT, 0, PTV1_IN,
+                PTV0_FN, PTV0_OUT, 0, PTV0_IN }
+        },
+        { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
+                PTW7_FN, PTW7_OUT, 0, PTW7_IN,
+                PTW6_FN, PTW6_OUT, 0, PTW6_IN,
+                PTW5_FN, PTW5_OUT, 0, PTW5_IN,
+                PTW4_FN, PTW4_OUT, 0, PTW4_IN,
+                PTW3_FN, PTW3_OUT, 0, PTW3_IN,
+                PTW2_FN, PTW2_OUT, 0, PTW2_IN,
+                PTW1_FN, PTW1_OUT, 0, PTW1_IN,
+                PTW0_FN, PTW0_OUT, 0, PTW0_IN }
+        },
+        { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
+                PTX7_FN, PTX7_OUT, 0, PTX7_IN,
+                PTX6_FN, PTX6_OUT, 0, PTX6_IN,
+                PTX5_FN, PTX5_OUT, 0, PTX5_IN,
+                PTX4_FN, PTX4_OUT, 0, PTX4_IN,
+                PTX3_FN, PTX3_OUT, 0, PTX3_IN,
+                PTX2_FN, PTX2_OUT, 0, PTX2_IN,
+                PTX1_FN, PTX1_OUT, 0, PTX1_IN,
+                PTX0_FN, PTX0_OUT, 0, PTX0_IN }
+        },
+        { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
+                PTY7_FN, PTY7_OUT, 0, PTY7_IN,
+                PTY6_FN, PTY6_OUT, 0, PTY6_IN,
+                PTY5_FN, PTY5_OUT, 0, PTY5_IN,
+                PTY4_FN, PTY4_OUT, 0, PTY4_IN,
+                PTY3_FN, PTY3_OUT, 0, PTY3_IN,
+                PTY2_FN, PTY2_OUT, 0, PTY2_IN,
+                PTY1_FN, PTY1_OUT, 0, PTY1_IN,
+                PTY0_FN, PTY0_OUT, 0, PTY0_IN }
+        },
+        { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
+                PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
+                PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
+                PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
+                PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN,
+                PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
+                PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
+                PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
+                PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN }
+        },
+        { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) {
+                PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0,
+                PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0,
+                PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0,
+                PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) {
+                PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0,
+                PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0,
+                0, 0, 0, 0,
+                PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, 0,
+                PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0,
+                PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0,
+                PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) {
+                PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0,
+                PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0,
+                PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0,
+                PSC9_PSC8_FN1, PSC9_PSC8_FN2, 0, 0,
+                PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) {
+                PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0,
+                PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0,
+                PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0,
+                PSD9_PSD8_FN1, PSD9_PSD8_FN2, 0, 0,
+                PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0,
+                PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0,
+                PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
+                PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
+                PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
+                0, 0, PTE5_DATA, PTE4_DATA,
+                PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
+                PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
+                0, 0, PTG5_DATA, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
+                PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
+                PTJ7_DATA, 0, PTJ5_DATA, 0,
+                PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
+                PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
+                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
+                PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
+        },
+        { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
+                0, 0, 0, 0,
+                PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
+                PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
+                PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
+                0, 0, PTT5_DATA, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
+                0, 0, PTU5_DATA, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
+                PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
+                PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+                PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
+        },
+        { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
+                PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+                PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
+        },
+        { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
+                PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+                PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
+        },
+        { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
+                PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+                PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7723_pinmux_info = {
+        .name = "sh7723_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA7,
+        .last_gpio = GPIO_FN_IDEA0,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7723_pinmux_info);
+}
+
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index e5e06845fa43..b8869aa20dec 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -1,7 +1,7 @@
 /*
  * SH-X3 SMP
  *
- *  Copyright (C) 2007  Paul Mundt
+ *  Copyright (C) 2007 - 2008  Paul Mundt
  *  Copyright (C) 2007  Magnus Damm
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -14,6 +14,22 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
+static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
+{
+        unsigned int message = (unsigned int)(long)arg;
+        unsigned int cpu = hard_smp_processor_id();
+        unsigned int offs = 4 * cpu;
+        unsigned int x;
+
+        x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
+        x &= (1 << (message << 2));
+        ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
+
+        smp_message_recv(message);
+
+        return IRQ_HANDLED;
+}
+
 void __init plat_smp_setup(void)
 {
         unsigned int cpu = 0;
@@ -40,6 +56,13 @@ void __init plat_smp_setup(void)
 
 void __init plat_prepare_cpus(unsigned int max_cpus)
 {
+        int i;
+
+        BUILD_BUG_ON(SMP_MSG_NR >= 8);
+
+        for (i = 0; i < SMP_MSG_NR; i++)
+                request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED,
+                            "IPI", (void *)(long)i);
 }
 
 #define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
@@ -59,7 +82,7 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
                 ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
 
         while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
-                ;
+                cpu_relax();
 
         /* Start up secondary processor by sending a reset */
         ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
@@ -75,46 +98,6 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
         unsigned long addr = 0xfe410070 + (cpu * 4);
 
         BUG_ON(cpu >= 4);
-        BUG_ON(message >= SMP_MSG_NR);
 
         ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
 }
-
-struct ipi_data {
-        void (*handler)(void *);
-        void *arg;
-        unsigned int message;
-};
-
-static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
-{
-        struct ipi_data *id = arg;
-        unsigned int cpu = hard_smp_processor_id();
-        unsigned int offs = 4 * cpu;
-        unsigned int x;
-
-        x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
-        x &= (1 << (id->message << 2));
-        ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
-
-        id->handler(id->arg);
-
-        return IRQ_HANDLED;
-}
-
-static struct ipi_data ipi_handlers[SMP_MSG_NR];
-
-int plat_register_ipi_handler(unsigned int message,
-                              void (*handler)(void *), void *arg)
-{
-        struct ipi_data *id = &ipi_handlers[message];
-
-        BUG_ON(SMP_MSG_NR >= 8);
-        BUG_ON(message >= SMP_MSG_NR);
-
-        id->handler = handler;
-        id->arg = arg;
-        id->message = message;
-
-        return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id);
-}
diff --git a/arch/sh/kernel/cpu/sh5/Makefile b/arch/sh/kernel/cpu/sh5/Makefile
index 8646363e9ded..ce4602ea23a8 100644
--- a/arch/sh/kernel/cpu/sh5/Makefile
+++ b/arch/sh/kernel/cpu/sh5/Makefile
@@ -5,3 +5,8 @@ obj-y := entry.o probe.o switchto.o
 
 obj-$(CONFIG_SH_FPU)            += fpu.o
 obj-$(CONFIG_KALLSYMS)          += unwind.o
+
+# Primary on-chip clocks (common)
+clock-$(CONFIG_CPU_SH5)         := clock-sh5.o
+
+obj-y                   += $(clock-y)
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
new file mode 100644
index 000000000000..52c49248833a
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -0,0 +1,79 @@
+/*
+ * arch/sh/kernel/cpu/sh5/clock-sh5.c
+ *
+ * SH-5 support for the clock framework
+ *
+ *  Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/clock.h>
+#include <asm/io.h>
+
+static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
+
+/* Clock, Power and Reset Controller */
+#define CPRC_BLOCK_OFF  0x01010000
+#define CPRC_BASE       (PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF)
+
+static unsigned long cprc_base;
+
+static void master_clk_init(struct clk *clk)
+{
+        int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007;
+        clk->rate *= ifc_table[idx];
+}
+
+static struct clk_ops sh5_master_clk_ops = {
+        .init           = master_clk_init,
+};
+
+static void module_clk_recalc(struct clk *clk)
+{
+        int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
+        clk->rate = clk->parent->rate / ifc_table[idx];
+}
+
+static struct clk_ops sh5_module_clk_ops = {
+        .recalc         = module_clk_recalc,
+};
+
+static void bus_clk_recalc(struct clk *clk)
+{
+        int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
+        clk->rate = clk->parent->rate / ifc_table[idx];
+}
+
+static struct clk_ops sh5_bus_clk_ops = {
+        .recalc         = bus_clk_recalc,
+};
+
+static void cpu_clk_recalc(struct clk *clk)
+{
+        int idx = (ctrl_inw(cprc_base) & 0x0007);
+        clk->rate = clk->parent->rate / ifc_table[idx];
+}
+
+static struct clk_ops sh5_cpu_clk_ops = {
+        .recalc         = cpu_clk_recalc,
+};
+
+static struct clk_ops *sh5_clk_ops[] = {
+        &sh5_master_clk_ops,
+        &sh5_module_clk_ops,
+        &sh5_bus_clk_ops,
+        &sh5_cpu_clk_ops,
+};
+
+void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+{
+        cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
+        BUG_ON(!cprc_base);
+
+        if (idx < ARRAY_SIZE(sh5_clk_ops))
+                *ops = sh5_clk_ops[idx];
+}
diff --git a/arch/sh/kernel/dump_task.c b/arch/sh/kernel/dump_task.c
deleted file mode 100644
index 1db7ce0f25d4..000000000000
--- a/arch/sh/kernel/dump_task.c
+++ /dev/null
@@ -1,32 +0,0 @@
-#include <linux/elfcore.h>
-#include <linux/sched.h>
-#include <asm/fpu.h>
-
-/*
- * Capture the user space registers if the task is not running (in user space)
- */
-int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
-{
-        struct pt_regs ptregs;
-
-        ptregs = *task_pt_regs(tsk);
-        elf_core_copy_regs(regs, &ptregs);
-
-        return 1;
-}
-
-int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpu)
-{
-        int fpvalid = 0;
-
-#if defined(CONFIG_SH_FPU)
-        fpvalid = !!tsk_used_math(tsk);
-        if (fpvalid) {
-                unlazy_fpu(tsk, task_pt_regs(tsk));
-                memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu));
-        }
-#endif
-
-        return fpvalid;
-}
-
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index efbb4268875e..1a5cf9dd82de 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -371,3 +371,47 @@ syscall_exit:
 #endif
 7:      .long   do_syscall_trace_enter
 8:      .long   do_syscall_trace_leave
+
+#ifdef CONFIG_FTRACE
+        .align 2
+        .globl  _mcount
+        .type   _mcount,@function
+        .globl  mcount
+        .type   mcount,@function
+_mcount:
+mcount:
+        mov.l   r4, @-r15
+        mov.l   r5, @-r15
+        mov.l   r6, @-r15
+        mov.l   r7, @-r15
+        sts.l   pr, @-r15
+
+        mov.l   @(20,r15),r4
+        sts     pr, r5
+
+        mov.l   1f, r6
+        mov.l   ftrace_stub, r7 
+        cmp/eq  r6, r7
+        bt      skip_trace
+
+        mov.l   @r6, r6
+        jsr     @r6
+         nop
+
+skip_trace:
+
+        lds.l   @r15+, pr
+        mov.l   @r15+, r7
+        mov.l   @r15+, r6
+        mov.l   @r15+, r5
+        rts
+         mov.l  @r15+, r4
+
+        .align 2
+1:      .long   ftrace_trace_function
+
+        .globl  ftrace_stub
+ftrace_stub:
+        rts
+         nop
+#endif /* CONFIG_FTRACE */
diff --git a/arch/sh/kernel/gpio.c b/arch/sh/kernel/gpio.c
new file mode 100644
index 000000000000..bb8b812c6895
--- /dev/null
+++ b/arch/sh/kernel/gpio.c
@@ -0,0 +1,498 @@
+/*
+ * Pinmuxed GPIO support for SuperH.
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+
+static struct pinmux_info *registered_gpio;
+
+static struct pinmux_info *gpio_controller(unsigned gpio)
+{
+        if (!registered_gpio)
+                return NULL;
+
+        if (gpio < registered_gpio->first_gpio)
+                return NULL;
+
+        if (gpio > registered_gpio->last_gpio)
+                return NULL;
+
+        return registered_gpio;
+}
+
+static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+{
+        if (enum_id < r->begin)
+                return 0;
+
+        if (enum_id > r->end)
+                return 0;
+
+        return 1;
+}
+
+static int read_write_reg(unsigned long reg, unsigned long reg_width,
+                          unsigned long field_width, unsigned long in_pos,
+                          unsigned long value, int do_write)
+{
+        unsigned long data, mask, pos;
+
+        data = 0;
+        mask = (1 << field_width) - 1;
+        pos = reg_width - ((in_pos + 1) * field_width);
+
+#ifdef DEBUG
+        pr_info("%s, addr = %lx, value = %ld, pos = %ld, "
+                "r_width = %ld, f_width = %ld\n",
+                do_write ? "write" : "read", reg, value, pos,
+                reg_width, field_width);
+#endif
+
+        switch (reg_width) {
+        case 8:
+                data = ctrl_inb(reg);
+                break;
+        case 16:
+                data = ctrl_inw(reg);
+                break;
+        case 32:
+                data = ctrl_inl(reg);
+                break;
+        }
+
+        if (!do_write)
+                return (data >> pos) & mask;
+
+        data &= ~(mask << pos);
+        data |= value << pos;
+
+        switch (reg_width) {
+        case 8:
+                ctrl_outb(data, reg);
+                break;
+        case 16:
+                ctrl_outw(data, reg);
+                break;
+        case 32:
+                ctrl_outl(data, reg);
+                break;
+        }
+        return 0;
+}
+
+static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
+                        struct pinmux_data_reg **drp, int *bitp)
+{
+        pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
+        struct pinmux_data_reg *data_reg;
+        int k, n;
+
+        if (!enum_in_range(enum_id, &gpioc->data))
+                return -1;
+
+        k = 0;
+        while (1) {
+                data_reg = gpioc->data_regs + k;
+
+                if (!data_reg->reg_width)
+                        break;
+
+                for (n = 0; n < data_reg->reg_width; n++) {
+                        if (data_reg->enum_ids[n] == enum_id) {
+                                *drp = data_reg;
+                                *bitp = n;
+                                return 0;
+
+                        }
+                }
+                k++;
+        }
+
+        return -1;
+}
+
+static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
+                          struct pinmux_cfg_reg **crp, int *indexp,
+                          unsigned long **cntp)
+{
+        struct pinmux_cfg_reg *config_reg;
+        unsigned long r_width, f_width;
+        int k, n;
+
+        k = 0;
+        while (1) {
+                config_reg = gpioc->cfg_regs + k;
+
+                r_width = config_reg->reg_width;
+                f_width = config_reg->field_width;
+
+                if (!r_width)
+                        break;
+                for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
+                        if (config_reg->enum_ids[n] == enum_id) {
+                                *crp = config_reg;
+                                *indexp = n;
+                                *cntp = &config_reg->cnt[n / (1 << f_width)];
+                                return 0;
+                        }
+                }
+                k++;
+        }
+
+        return -1;
+}
+
+static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
+                            int pos, pinmux_enum_t *enum_idp)
+{
+        pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
+        pinmux_enum_t *data = gpioc->gpio_data;
+        int k;
+
+        if (!enum_in_range(enum_id, &gpioc->data)) {
+                if (!enum_in_range(enum_id, &gpioc->mark)) {
+                        pr_err("non data/mark enum_id for gpio %d\n", gpio);
+                        return -1;
+                }
+        }
+
+        if (pos) {
+                *enum_idp = data[pos + 1];
+                return pos + 1;
+        }
+
+        for (k = 0; k < gpioc->gpio_data_size; k++) {
+                if (data[k] == enum_id) {
+                        *enum_idp = data[k + 1];
+                        return k + 1;
+                }
+        }
+
+        pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
+        return -1;
+}
+
+static int write_config_reg(struct pinmux_info *gpioc,
+                            struct pinmux_cfg_reg *crp,
+                            int index)
+{
+        unsigned long ncomb, pos, value;
+
+        ncomb = 1 << crp->field_width;
+        pos = index / ncomb;
+        value = index % ncomb;
+
+        return read_write_reg(crp->reg, crp->reg_width,
+                              crp->field_width, pos, value, 1);
+}
+
+static int check_config_reg(struct pinmux_info *gpioc,
+                            struct pinmux_cfg_reg *crp,
+                            int index)
+{
+        unsigned long ncomb, pos, value;
+
+        ncomb = 1 << crp->field_width;
+        pos = index / ncomb;
+        value = index % ncomb;
+
+        if (read_write_reg(crp->reg, crp->reg_width,
+                           crp->field_width, pos, 0, 0) == value)
+                return 0;
+
+        return -1;
+}
+
+enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
+
+int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
+                       int pinmux_type, int cfg_mode)
+{
+        struct pinmux_cfg_reg *cr = NULL;
+        pinmux_enum_t enum_id;
+        struct pinmux_range *range;
+        int in_range, pos, index;
+        unsigned long *cntp;
+
+        switch (pinmux_type) {
+
+        case PINMUX_TYPE_FUNCTION:
+                range = NULL;
+                break;
+
+        case PINMUX_TYPE_OUTPUT:
+                range = &gpioc->output;
+                break;
+
+        case PINMUX_TYPE_INPUT:
+                range = &gpioc->input;
+                break;
+
+        case PINMUX_TYPE_INPUT_PULLUP:
+                range = &gpioc->input_pu;
+                break;
+
+        case PINMUX_TYPE_INPUT_PULLDOWN:
+                range = &gpioc->input_pd;
+                break;
+
+        default:
+                goto out_err;
+        }
+
+        pos = 0;
+        enum_id = 0;
+        index = 0;
+        while (1) {
+                pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
+                if (pos <= 0)
+                        goto out_err;
+
+                if (!enum_id)
+                        break;
+
+                in_range = enum_in_range(enum_id, &gpioc->function);
+                if (!in_range && range)
+                        in_range = enum_in_range(enum_id, range);
+
+                if (!in_range)
+                        continue;
+
+                if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
+                        goto out_err;
+
+                switch (cfg_mode) {
+                case GPIO_CFG_DRYRUN:
+                        if (!*cntp || !check_config_reg(gpioc, cr, index))
+                                continue;
+                        break;
+
+                case GPIO_CFG_REQ:
+                        if (write_config_reg(gpioc, cr, index) != 0)
+                                goto out_err;
+                        *cntp = *cntp + 1;
+                        break;
+
+                case GPIO_CFG_FREE:
+                        *cntp = *cntp - 1;
+                        break;
+                }
+        }
+
+        return 0;
+ out_err:
+        return -1;
+}
+
+static DEFINE_SPINLOCK(gpio_lock);
+
+int __gpio_request(unsigned gpio)
+{
+        struct pinmux_info *gpioc = gpio_controller(gpio);
+        struct pinmux_data_reg *dummy;
+        unsigned long flags;
+        int i, ret, pinmux_type;
+
+        ret = -EINVAL;
+
+        if (!gpioc)
+                goto err_out;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
+                goto err_unlock;
+
+        /* setup pin function here if no data is associated with pin */
+
+        if (get_data_reg(gpioc, gpio, &dummy, &i) != 0)
+                pinmux_type = PINMUX_TYPE_FUNCTION;
+        else
+                pinmux_type = PINMUX_TYPE_GPIO;
+
+        if (pinmux_type == PINMUX_TYPE_FUNCTION) {
+                if (pinmux_config_gpio(gpioc, gpio,
+                                       pinmux_type,
+                                       GPIO_CFG_DRYRUN) != 0)
+                        goto err_unlock;
+
+                if (pinmux_config_gpio(gpioc, gpio,
+                                       pinmux_type,
+                                       GPIO_CFG_REQ) != 0)
+                        BUG();
+        }
+
+        gpioc->gpios[gpio].flags = pinmux_type;
+
+        ret = 0;
+ err_unlock:
+        spin_unlock_irqrestore(&gpio_lock, flags);
+ err_out:
+        return ret;
+}
+EXPORT_SYMBOL(__gpio_request);
+
+void gpio_free(unsigned gpio)
+{
+        struct pinmux_info *gpioc = gpio_controller(gpio);
+        unsigned long flags;
+        int pinmux_type;
+
+        if (!gpioc)
+                return;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
+        pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
+        gpioc->gpios[gpio].flags = PINMUX_TYPE_NONE;
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+}
+EXPORT_SYMBOL(gpio_free);
+
+static int pinmux_direction(struct pinmux_info *gpioc,
+                            unsigned gpio, int new_pinmux_type)
+{
+        int ret, pinmux_type;
+
+        ret = -EINVAL;
+        pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
+
+        switch (pinmux_type) {
+        case PINMUX_TYPE_GPIO:
+                break;
+        case PINMUX_TYPE_OUTPUT:
+        case PINMUX_TYPE_INPUT:
+        case PINMUX_TYPE_INPUT_PULLUP:
+        case PINMUX_TYPE_INPUT_PULLDOWN:
+                pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
+                break;
+        default:
+                goto err_out;
+        }
+
+        if (pinmux_config_gpio(gpioc, gpio,
+                               new_pinmux_type,
+                               GPIO_CFG_DRYRUN) != 0)
+                goto err_out;
+
+        if (pinmux_config_gpio(gpioc, gpio,
+                               new_pinmux_type,
+                               GPIO_CFG_REQ) != 0)
+                BUG();
+
+        gpioc->gpios[gpio].flags = new_pinmux_type;
+
+        ret = 0;
+ err_out:
+        return ret;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+        struct pinmux_info *gpioc = gpio_controller(gpio);
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (!gpioc)
+                goto err_out;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+        ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT);
+        spin_unlock_irqrestore(&gpio_lock, flags);
+ err_out:
+        return ret;
+}
+EXPORT_SYMBOL(gpio_direction_input);
+
+static int __gpio_get_set_value(struct pinmux_info *gpioc,
+                                unsigned gpio, int value,
+                                int do_write)
+{
+        struct pinmux_data_reg *dr = NULL;
+        int bit = 0;
+
+        if (get_data_reg(gpioc, gpio, &dr, &bit) != 0)
+                BUG();
+        else
+                value = read_write_reg(dr->reg, dr->reg_width,
+                                       1, bit, value, do_write);
+
+        return value;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+        struct pinmux_info *gpioc = gpio_controller(gpio);
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (!gpioc)
+                goto err_out;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+        __gpio_get_set_value(gpioc, gpio, value, 1);
+        ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
+        spin_unlock_irqrestore(&gpio_lock, flags);
+ err_out:
+        return ret;
+}
+EXPORT_SYMBOL(gpio_direction_output);
+
+int gpio_get_value(unsigned gpio)
+{
+        struct pinmux_info *gpioc = gpio_controller(gpio);
+        unsigned long flags;
+        int value = 0;
+
+        if (!gpioc)
+                BUG();
+        else {
+                spin_lock_irqsave(&gpio_lock, flags);
+                value = __gpio_get_set_value(gpioc, gpio, 0, 0);
+                spin_unlock_irqrestore(&gpio_lock, flags);
+        }
+
+        return value;
+}
+EXPORT_SYMBOL(gpio_get_value);
+
+void gpio_set_value(unsigned gpio, int value)
+{
+        struct pinmux_info *gpioc = gpio_controller(gpio);
+        unsigned long flags;
+
+        if (!gpioc)
+                BUG();
+        else {
+                spin_lock_irqsave(&gpio_lock, flags);
+                __gpio_get_set_value(gpioc, gpio, value, 1);
+                spin_unlock_irqrestore(&gpio_lock, flags);
+        }
+}
+EXPORT_SYMBOL(gpio_set_value);
+
+int register_pinmux(struct pinmux_info *pip)
+{
+        registered_gpio = pip;
+        pr_info("pinmux: %s handling gpio %d -> %d\n",
+                pip->name, pip->first_gpio, pip->last_gpio);
+
+        return 0;
+}
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 2b8991229900..29cf4588fc05 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -19,12 +19,12 @@
  * Copy data from IO memory space to "real" memory space.
  * This needs to be optimized.
  */
-void memcpy_fromio(void *to, volatile void __iomem *from, unsigned long count)
+void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count)
 {
-        char *p = to;
+        unsigned char *p = to;
         while (count) {
                 count--;
-                *p = readb((void __iomem *)from);
+                *p = readb(from);
                 p++;
                 from++;
         }
@@ -37,10 +37,10 @@ EXPORT_SYMBOL(memcpy_fromio);
  */
 void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count)
 {
-        const char *p = from;
+        const unsigned char *p = from;
         while (count) {
                 count--;
-                writeb(*p, (void __iomem *)to);
+                writeb(*p, to);
                 p++;
                 to++;
         }
@@ -55,7 +55,7 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
 {
         while (count) {
                 count--;
-                writeb(c, (void __iomem *)dst);
+                writeb(c, dst);
                 dst++;
         }
 }
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
index db769449f5a7..5a7f554d9ca1 100644
--- a/arch/sh/kernel/io_generic.c
+++ b/arch/sh/kernel/io_generic.c
@@ -19,38 +19,33 @@
 /* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
  * workaround. */
 /* I'm not sure SH7709 has this kind of bug */
-#define dummy_read()    ctrl_inb(0xba000000)
+#define dummy_read()    __raw_readb(0xba000000)
 #else
 #define dummy_read()
 #endif
 
 unsigned long generic_io_base;
 
-static inline void delay(void)
-{
-        ctrl_inw(0xa0000000);
-}
-
 u8 generic_inb(unsigned long port)
 {
-        return ctrl_inb((unsigned long __force)__ioport_map(port, 1));
+        return __raw_readb(__ioport_map(port, 1));
 }
 
 u16 generic_inw(unsigned long port)
 {
-        return ctrl_inw((unsigned long __force)__ioport_map(port, 2));
+        return __raw_readw(__ioport_map(port, 2));
 }
 
 u32 generic_inl(unsigned long port)
 {
-        return ctrl_inl((unsigned long __force)__ioport_map(port, 4));
+        return __raw_readl(__ioport_map(port, 4));
 }
 
 u8 generic_inb_p(unsigned long port)
 {
         unsigned long v = generic_inb(port);
 
-        delay();
+        ctrl_delay();
         return v;
 }
 
@@ -58,7 +53,7 @@ u16 generic_inw_p(unsigned long port)
 {
         unsigned long v = generic_inw(port);
 
-        delay();
+        ctrl_delay();
         return v;
 }
 
@@ -66,7 +61,7 @@ u32 generic_inl_p(unsigned long port)
 {
         unsigned long v = generic_inl(port);
 
-        delay();
+        ctrl_delay();
         return v;
 }
 
@@ -81,7 +76,7 @@ void generic_insb(unsigned long port, void *dst, unsigned long count)
         volatile u8 *port_addr;
         u8 *buf = dst;
 
-        port_addr = (volatile u8 *)__ioport_map(port, 1);
+        port_addr = (volatile u8 __force *)__ioport_map(port, 1);
         while (count--)
                 *buf++ = *port_addr;
 }
@@ -91,7 +86,7 @@ void generic_insw(unsigned long port, void *dst, unsigned long count)
         volatile u16 *port_addr;
         u16 *buf = dst;
 
-        port_addr = (volatile u16 *)__ioport_map(port, 2);
+        port_addr = (volatile u16 __force *)__ioport_map(port, 2);
         while (count--)
                 *buf++ = *port_addr;
 
@@ -103,7 +98,7 @@ void generic_insl(unsigned long port, void *dst, unsigned long count)
         volatile u32 *port_addr;
         u32 *buf = dst;
 
-        port_addr = (volatile u32 *)__ioport_map(port, 4);
+        port_addr = (volatile u32 __force *)__ioport_map(port, 4);
         while (count--)
                 *buf++ = *port_addr;
 
@@ -112,35 +107,35 @@ void generic_insl(unsigned long port, void *dst, unsigned long count)
 
 void generic_outb(u8 b, unsigned long port)
 {
-        ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1));
+        __raw_writeb(b, __ioport_map(port, 1));
 }
 
 void generic_outw(u16 b, unsigned long port)
 {
-        ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2));
+        __raw_writew(b, __ioport_map(port, 2));
 }
 
 void generic_outl(u32 b, unsigned long port)
 {
-        ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4));
+        __raw_writel(b, __ioport_map(port, 4));
 }
 
 void generic_outb_p(u8 b, unsigned long port)
 {
         generic_outb(b, port);
-        delay();
+        ctrl_delay();
 }
 
 void generic_outw_p(u16 b, unsigned long port)
 {
         generic_outw(b, port);
-        delay();
+        ctrl_delay();
 }
 
 void generic_outl_p(u32 b, unsigned long port)
 {
         generic_outl(b, port);
-        delay();
+        ctrl_delay();
 }
 
 /*
@@ -184,36 +179,6 @@ void generic_outsl(unsigned long port, const void *src, unsigned long count)
         dummy_read();
 }
 
-u8 generic_readb(void __iomem *addr)
-{
-        return ctrl_inb((unsigned long __force)addr);
-}
-
-u16 generic_readw(void __iomem *addr)
-{
-        return ctrl_inw((unsigned long __force)addr);
-}
-
-u32 generic_readl(void __iomem *addr)
-{
-        return ctrl_inl((unsigned long __force)addr);
-}
-
-void generic_writeb(u8 b, void __iomem *addr)
-{
-        ctrl_outb(b, (unsigned long __force)addr);
-}
-
-void generic_writew(u16 b, void __iomem *addr)
-{
-        ctrl_outw(b, (unsigned long __force)addr);
-}
-
-void generic_writel(u32 b, void __iomem *addr)
-{
-        ctrl_outl(b, (unsigned long __force)addr);
-}
-
 void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
 {
         return (void __iomem *)(addr + generic_io_base);
diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c
new file mode 100644
index 000000000000..c96850b061fb
--- /dev/null
+++ b/arch/sh/kernel/kprobes.c
@@ -0,0 +1,584 @@
+/*
+ * Kernel probes (kprobes) for SuperH
+ *
+ * Copyright (C) 2007 Chris Smith <chris.smith@st.com>
+ * Copyright (C) 2006 Lineo Solutions, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kprobes.h>
+#include <linux/module.h>
+#include <linux/ptrace.h>
+#include <linux/preempt.h>
+#include <linux/kdebug.h>
+#include <asm/cacheflush.h>
+#include <asm/uaccess.h>
+
+DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
+DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
+
+static struct kprobe saved_current_opcode;
+static struct kprobe saved_next_opcode;
+static struct kprobe saved_next_opcode2;
+
+#define OPCODE_JMP(x)   (((x) & 0xF0FF) == 0x402b)
+#define OPCODE_JSR(x)   (((x) & 0xF0FF) == 0x400b)
+#define OPCODE_BRA(x)   (((x) & 0xF000) == 0xa000)
+#define OPCODE_BRAF(x)  (((x) & 0xF0FF) == 0x0023)
+#define OPCODE_BSR(x)   (((x) & 0xF000) == 0xb000)
+#define OPCODE_BSRF(x)  (((x) & 0xF0FF) == 0x0003)
+
+#define OPCODE_BF_S(x)  (((x) & 0xFF00) == 0x8f00)
+#define OPCODE_BT_S(x)  (((x) & 0xFF00) == 0x8d00)
+
+#define OPCODE_BF(x)    (((x) & 0xFF00) == 0x8b00)
+#define OPCODE_BT(x)    (((x) & 0xFF00) == 0x8900)
+
+#define OPCODE_RTS(x)   (((x) & 0x000F) == 0x000b)
+#define OPCODE_RTE(x)   (((x) & 0xFFFF) == 0x002b)
+
+int __kprobes arch_prepare_kprobe(struct kprobe *p)
+{
+        kprobe_opcode_t opcode = *(kprobe_opcode_t *) (p->addr);
+
+        if (OPCODE_RTE(opcode))
+                return -EFAULT; /* Bad breakpoint */
+
+        p->opcode = opcode;
+
+        return 0;
+}
+
+void __kprobes arch_copy_kprobe(struct kprobe *p)
+{
+        memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
+        p->opcode = *p->addr;
+}
+
+void __kprobes arch_arm_kprobe(struct kprobe *p)
+{
+        *p->addr = BREAKPOINT_INSTRUCTION;
+        flush_icache_range((unsigned long)p->addr,
+                           (unsigned long)p->addr + sizeof(kprobe_opcode_t));
+}
+
+void __kprobes arch_disarm_kprobe(struct kprobe *p)
+{
+        *p->addr = p->opcode;
+        flush_icache_range((unsigned long)p->addr,
+                           (unsigned long)p->addr + sizeof(kprobe_opcode_t));
+}
+
+int __kprobes arch_trampoline_kprobe(struct kprobe *p)
+{
+        if (*p->addr == BREAKPOINT_INSTRUCTION)
+                return 1;
+
+        return 0;
+}
+
+/**
+ * If an illegal slot instruction exception occurs for an address
+ * containing a kprobe, remove the probe.
+ *
+ * Returns 0 if the exception was handled successfully, 1 otherwise.
+ */
+int __kprobes kprobe_handle_illslot(unsigned long pc)
+{
+        struct kprobe *p = get_kprobe((kprobe_opcode_t *) pc + 1);
+
+        if (p != NULL) {
+                printk("Warning: removing kprobe from delay slot: 0x%.8x\n",
+                       (unsigned int)pc + 2);
+                unregister_kprobe(p);
+                return 0;
+        }
+
+        return 1;
+}
+
+void __kprobes arch_remove_kprobe(struct kprobe *p)
+{
+        if (saved_next_opcode.addr != 0x0) {
+                arch_disarm_kprobe(p);
+                arch_disarm_kprobe(&saved_next_opcode);
+                saved_next_opcode.addr = 0x0;
+                saved_next_opcode.opcode = 0x0;
+
+                if (saved_next_opcode2.addr != 0x0) {
+                        arch_disarm_kprobe(&saved_next_opcode2);
+                        saved_next_opcode2.addr = 0x0;
+                        saved_next_opcode2.opcode = 0x0;
+                }
+        }
+}
+
+static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+        kcb->prev_kprobe.kp = kprobe_running();
+        kcb->prev_kprobe.status = kcb->kprobe_status;
+}
+
+static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+        __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
+        kcb->kprobe_status = kcb->prev_kprobe.status;
+}
+
+static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
+                                         struct kprobe_ctlblk *kcb)
+{
+        __get_cpu_var(current_kprobe) = p;
+}
+
+/*
+ * Singlestep is implemented by disabling the current kprobe and setting one
+ * on the next instruction, following branches. Two probes are set if the
+ * branch is conditional.
+ */
+static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+        kprobe_opcode_t *addr = NULL;
+        saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc);
+        addr = saved_current_opcode.addr;
+
+        if (p != NULL) {
+                arch_disarm_kprobe(p);
+
+                if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) {
+                        unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
+                        saved_next_opcode.addr =
+                            (kprobe_opcode_t *) regs->regs[reg_nr];
+                } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) {
+                        unsigned long disp = (p->opcode & 0x0FFF);
+                        saved_next_opcode.addr =
+                            (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
+
+                } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) {
+                        unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
+                        saved_next_opcode.addr =
+                            (kprobe_opcode_t *) (regs->pc + 4 +
+                                                 regs->regs[reg_nr]);
+
+                } else if (OPCODE_RTS(p->opcode)) {
+                        saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr;
+
+                } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) {
+                        unsigned long disp = (p->opcode & 0x00FF);
+                        /* case 1 */
+                        saved_next_opcode.addr = p->addr + 1;
+                        /* case 2 */
+                        saved_next_opcode2.addr =
+                            (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
+                        saved_next_opcode2.opcode = *(saved_next_opcode2.addr);
+                        arch_arm_kprobe(&saved_next_opcode2);
+
+                } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) {
+                        unsigned long disp = (p->opcode & 0x00FF);
+                        /* case 1 */
+                        saved_next_opcode.addr = p->addr + 2;
+                        /* case 2 */
+                        saved_next_opcode2.addr =
+                            (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
+                        saved_next_opcode2.opcode = *(saved_next_opcode2.addr);
+                        arch_arm_kprobe(&saved_next_opcode2);
+
+                } else {
+                        saved_next_opcode.addr = p->addr + 1;
+                }
+
+                saved_next_opcode.opcode = *(saved_next_opcode.addr);
+                arch_arm_kprobe(&saved_next_opcode);
+        }
+}
+
+/* Called with kretprobe_lock held */
+void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
+                                      struct pt_regs *regs)
+{
+        ri->ret_addr = (kprobe_opcode_t *) regs->pr;
+
+        /* Replace the return addr with trampoline addr */
+        regs->pr = (unsigned long)kretprobe_trampoline;
+}
+
+static int __kprobes kprobe_handler(struct pt_regs *regs)
+{
+        struct kprobe *p;
+        int ret = 0;
+        kprobe_opcode_t *addr = NULL;
+        struct kprobe_ctlblk *kcb;
+
+        /*
+         * We don't want to be preempted for the entire
+         * duration of kprobe processing
+         */
+        preempt_disable();
+        kcb = get_kprobe_ctlblk();
+
+        addr = (kprobe_opcode_t *) (regs->pc);
+
+        /* Check we're not actually recursing */
+        if (kprobe_running()) {
+                p = get_kprobe(addr);
+                if (p) {
+                        if (kcb->kprobe_status == KPROBE_HIT_SS &&
+                            *p->ainsn.insn == BREAKPOINT_INSTRUCTION) {
+                                goto no_kprobe;
+                        }
+                        /* We have reentered the kprobe_handler(), since
+                         * another probe was hit while within the handler.
+                         * We here save the original kprobes variables and
+                         * just single step on the instruction of the new probe
+                         * without calling any user handlers.
+                         */
+                        save_previous_kprobe(kcb);
+                        set_current_kprobe(p, regs, kcb);
+                        kprobes_inc_nmissed_count(p);
+                        prepare_singlestep(p, regs);
+                        kcb->kprobe_status = KPROBE_REENTER;
+                        return 1;
+                } else {
+                        p = __get_cpu_var(current_kprobe);
+                        if (p->break_handler && p->break_handler(p, regs)) {
+                                goto ss_probe;
+                        }
+                }
+                goto no_kprobe;
+        }
+
+        p = get_kprobe(addr);
+        if (!p) {
+                /* Not one of ours: let kernel handle it */
+                if (*(kprobe_opcode_t *)addr != BREAKPOINT_INSTRUCTION) {
+                        /*
+                         * The breakpoint instruction was removed right
+                         * after we hit it. Another cpu has removed
+                         * either a probepoint or a debugger breakpoint
+                         * at this address. In either case, no further
+                         * handling of this interrupt is appropriate.
+                         */
+                        ret = 1;
+                }
+
+                goto no_kprobe;
+        }
+
+        set_current_kprobe(p, regs, kcb);
+        kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+
+        if (p->pre_handler && p->pre_handler(p, regs))
+                /* handler has already set things up, so skip ss setup */
+                return 1;
+
+ss_probe:
+        prepare_singlestep(p, regs);
+        kcb->kprobe_status = KPROBE_HIT_SS;
+        return 1;
+
+no_kprobe:
+        preempt_enable_no_resched();
+        return ret;
+}
+
+/*
+ * For function-return probes, init_kprobes() establishes a probepoint
+ * here. When a retprobed function returns, this probe is hit and
+ * trampoline_probe_handler() runs, calling the kretprobe's handler.
+ */
+static void __used kretprobe_trampoline_holder(void)
+{
+        asm volatile (".globl kretprobe_trampoline\n"
+                      "kretprobe_trampoline:\n\t"
+                      "nop\n");
+}
+
+/*
+ * Called when we hit the probe point at kretprobe_trampoline
+ */
+int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct kretprobe_instance *ri = NULL;
+        struct hlist_head *head, empty_rp;
+        struct hlist_node *node, *tmp;
+        unsigned long flags, orig_ret_address = 0;
+        unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline;
+
+        INIT_HLIST_HEAD(&empty_rp);
+        kretprobe_hash_lock(current, &head, &flags);
+
+        /*
+         * It is possible to have multiple instances associated with a given
+         * task either because an multiple functions in the call path
+         * have a return probe installed on them, and/or more then one return
+         * return probe was registered for a target function.
+         *
+         * We can handle this because:
+         *     - instances are always inserted at the head of the list
+         *     - when multiple return probes are registered for the same
+         *       function, the first instance's ret_addr will point to the
+         *       real return address, and all the rest will point to
+         *       kretprobe_trampoline
+         */
+        hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
+                if (ri->task != current)
+                        /* another task is sharing our hash bucket */
+                        continue;
+
+                if (ri->rp && ri->rp->handler) {
+                        __get_cpu_var(current_kprobe) = &ri->rp->kp;
+                        ri->rp->handler(ri, regs);
+                        __get_cpu_var(current_kprobe) = NULL;
+                }
+
+                orig_ret_address = (unsigned long)ri->ret_addr;
+                recycle_rp_inst(ri, &empty_rp);
+
+                if (orig_ret_address != trampoline_address)
+                        /*
+                         * This is the real return address. Any other
+                         * instances associated with this task are for
+                         * other calls deeper on the call stack
+                         */
+                        break;
+        }
+
+        kretprobe_assert(ri, orig_ret_address, trampoline_address);
+
+        regs->pc = orig_ret_address;
+        kretprobe_hash_unlock(current, &flags);
+
+        preempt_enable_no_resched();
+
+        hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
+                hlist_del(&ri->hlist);
+                kfree(ri);
+        }
+
+        return orig_ret_address;
+}
+
+static int __kprobes post_kprobe_handler(struct pt_regs *regs)
+{
+        struct kprobe *cur = kprobe_running();
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        kprobe_opcode_t *addr = NULL;
+        struct kprobe *p = NULL;
+
+        if (!cur)
+                return 0;
+
+        if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
+                kcb->kprobe_status = KPROBE_HIT_SSDONE;
+                cur->post_handler(cur, regs, 0);
+        }
+
+        if (saved_next_opcode.addr != 0x0) {
+                arch_disarm_kprobe(&saved_next_opcode);
+                saved_next_opcode.addr = 0x0;
+                saved_next_opcode.opcode = 0x0;
+
+                addr = saved_current_opcode.addr;
+                saved_current_opcode.addr = 0x0;
+
+                p = get_kprobe(addr);
+                arch_arm_kprobe(p);
+
+                if (saved_next_opcode2.addr != 0x0) {
+                        arch_disarm_kprobe(&saved_next_opcode2);
+                        saved_next_opcode2.addr = 0x0;
+                        saved_next_opcode2.opcode = 0x0;
+                }
+        }
+
+        /* Restore back the original saved kprobes variables and continue. */
+        if (kcb->kprobe_status == KPROBE_REENTER) {
+                restore_previous_kprobe(kcb);
+                goto out;
+        }
+
+        reset_current_kprobe();
+
+out:
+        preempt_enable_no_resched();
+
+        return 1;
+}
+
+int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+        struct kprobe *cur = kprobe_running();
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        const struct exception_table_entry *entry;
+
+        switch (kcb->kprobe_status) {
+        case KPROBE_HIT_SS:
+        case KPROBE_REENTER:
+                /*
+                 * We are here because the instruction being single
+                 * stepped caused a page fault. We reset the current
+                 * kprobe, point the pc back to the probe address
+                 * and allow the page fault handler to continue as a
+                 * normal page fault.
+                 */
+                regs->pc = (unsigned long)cur->addr;
+                if (kcb->kprobe_status == KPROBE_REENTER)
+                        restore_previous_kprobe(kcb);
+                else
+                        reset_current_kprobe();
+                preempt_enable_no_resched();
+                break;
+        case KPROBE_HIT_ACTIVE:
+        case KPROBE_HIT_SSDONE:
+                /*
+                 * We increment the nmissed count for accounting,
+                 * we can also use npre/npostfault count for accounting
+                 * these specific fault cases.
+                 */
+                kprobes_inc_nmissed_count(cur);
+
+                /*
+                 * We come here because instructions in the pre/post
+                 * handler caused the page_fault, this could happen
+                 * if handler tries to access user space by
+                 * copy_from_user(), get_user() etc. Let the
+                 * user-specified handler try to fix it first.
+                 */
+                if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
+                        return 1;
+
+                /*
+                 * In case the user-specified fault handler returned
+                 * zero, try to fix up.
+                 */
+                if ((entry = search_exception_tables(regs->pc)) != NULL) {
+                        regs->pc = entry->fixup;
+                        return 1;
+                }
+
+                /*
+                 * fixup_exception() could not handle it,
+                 * Let do_page_fault() fix it.
+                 */
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+/*
+ * Wrapper routine to for handling exceptions.
+ */
+int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
+                                       unsigned long val, void *data)
+{
+        struct kprobe *p = NULL;
+        struct die_args *args = (struct die_args *)data;
+        int ret = NOTIFY_DONE;
+        kprobe_opcode_t *addr = NULL;
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        addr = (kprobe_opcode_t *) (args->regs->pc);
+        if (val == DIE_TRAP) {
+                if (!kprobe_running()) {
+                        if (kprobe_handler(args->regs)) {
+                                ret = NOTIFY_STOP;
+                        } else {
+                                /* Not a kprobe trap */
+                                ret = NOTIFY_DONE;
+                        }
+                } else {
+                        p = get_kprobe(addr);
+                        if ((kcb->kprobe_status == KPROBE_HIT_SS) ||
+                            (kcb->kprobe_status == KPROBE_REENTER)) {
+                                if (post_kprobe_handler(args->regs))
+                                        ret = NOTIFY_STOP;
+                        } else {
+                                if (kprobe_handler(args->regs)) {
+                                        ret = NOTIFY_STOP;
+                                } else {
+                                        p = __get_cpu_var(current_kprobe);
+                                        if (p->break_handler &&
+                                            p->break_handler(p, args->regs))
+                                                ret = NOTIFY_STOP;
+                                }
+                        }
+                }
+        }
+
+        return ret;
+}
+
+int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct jprobe *jp = container_of(p, struct jprobe, kp);
+        unsigned long addr;
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        kcb->jprobe_saved_regs = *regs;
+        kcb->jprobe_saved_r15 = regs->regs[15];
+        addr = kcb->jprobe_saved_r15;
+
+        /*
+         * TBD: As Linus pointed out, gcc assumes that the callee
+         * owns the argument space and could overwrite it, e.g.
+         * tailcall optimization. So, to be absolutely safe
+         * we also save and restore enough stack bytes to cover
+         * the argument area.
+         */
+        memcpy(kcb->jprobes_stack, (kprobe_opcode_t *) addr,
+               MIN_STACK_SIZE(addr));
+
+        regs->pc = (unsigned long)(jp->entry);
+
+        return 1;
+}
+
+void __kprobes jprobe_return(void)
+{
+        asm volatile ("trapa #0x3a\n\t" "jprobe_return_end:\n\t" "nop\n\t");
+}
+
+int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        unsigned long stack_addr = kcb->jprobe_saved_r15;
+        u8 *addr = (u8 *)regs->pc;
+
+        if ((addr >= (u8 *)jprobe_return) &&
+            (addr <= (u8 *)jprobe_return_end)) {
+                *regs = kcb->jprobe_saved_regs;
+
+                memcpy((kprobe_opcode_t *)stack_addr, kcb->jprobes_stack,
+                       MIN_STACK_SIZE(stack_addr));
+
+                kcb->kprobe_status = KPROBE_HIT_SS;
+                preempt_enable_no_resched();
+                return 1;
+        }
+
+        return 0;
+}
+
+static struct kprobe trampoline_p = {
+        .addr = (kprobe_opcode_t *)&kretprobe_trampoline,
+        .pre_handler = trampoline_probe_handler
+};
+
+int __init arch_init_kprobes(void)
+{
+        saved_next_opcode.addr = 0x0;
+        saved_next_opcode.opcode = 0x0;
+
+        saved_current_opcode.addr = 0x0;
+        saved_current_opcode.opcode = 0x0;
+
+        saved_next_opcode2.addr = 0x0;
+        saved_next_opcode2.opcode = 0x0;
+
+        return register_kprobe(&trampoline_p);
+}
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 129b2cfd18a8..c1ea41e5812a 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -14,6 +14,7 @@
 #include <linux/string.h>
 #include <asm/machvec.h>
 #include <asm/sections.h>
+#include <asm/setup.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
@@ -125,9 +126,6 @@ void __init sh_mv_setup(void)
         mv_set(insb);   mv_set(insw);   mv_set(insl);
         mv_set(outsb);  mv_set(outsw);  mv_set(outsl);
 
-        mv_set(readb);  mv_set(readw);  mv_set(readl);
-        mv_set(writeb); mv_set(writew); mv_set(writel);
-
         mv_set(ioport_map);
         mv_set(ioport_unmap);
         mv_set(irq_demux);
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 3326a45749d9..b965f0282c7d 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -7,7 +7,11 @@
  *
  *  SuperH version:  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
  *                   Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
- *                   Copyright (C) 2002 - 2007  Paul Mundt
+ *                   Copyright (C) 2002 - 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  */
 #include <linux/module.h>
 #include <linux/mm.h>
@@ -26,6 +30,7 @@
 #include <asm/system.h>
 #include <asm/ubc.h>
 #include <asm/fpu.h>
+#include <asm/syscalls.h>
 
 static int hlt_counter;
 int ubc_usercnt = 0;
@@ -111,15 +116,21 @@ void show_regs(struct pt_regs * regs)
 {
         printk("\n");
         printk("Pid : %d, Comm: %20s\n", task_pid_nr(current), current->comm);
+        printk("CPU : %d    %s  (%s %.*s)\n",
+               smp_processor_id(), print_tainted(), init_utsname()->release,
+               (int)strcspn(init_utsname()->version, " "),
+               init_utsname()->version);
+
         print_symbol("PC is at %s\n", instruction_pointer(regs));
+        print_symbol("PR is at %s\n", regs->pr);
+
         printk("PC  : %08lx SP  : %08lx SR  : %08lx ",
                regs->pc, regs->regs[15], regs->sr);
 #ifdef CONFIG_MMU
-        printk("TEA : %08x    ", ctrl_inl(MMU_TEA));
+        printk("TEA : %08x\n", ctrl_inl(MMU_TEA));
 #else
-        printk("                  ");
+        printk("\n");
 #endif
-        printk("%s\n", print_tainted());
 
         printk("R0  : %08lx R1  : %08lx R2  : %08lx R3  : %08lx\n",
                regs->regs[0],regs->regs[1],
@@ -162,6 +173,7 @@ __asm__(".align 5\n"
 int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
 {
         struct pt_regs regs;
+        int pid;
 
         memset(&regs, 0, sizeof(regs));
         regs.regs[4] = (unsigned long)arg;
@@ -171,8 +183,12 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
         regs.sr = (1 << 30);
 
         /* Ok, create the new process.. */
-        return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
-                       &regs, 0, NULL, NULL);
+        pid = do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
+                      &regs, 0, NULL, NULL);
+
+        trace_mark(kernel_arch_kthread_create, "pid %d fn %p", pid, fn);
+
+        return pid;
 }
 
 /*
@@ -210,10 +226,10 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
         struct task_struct *tsk = current;
 
         fpvalid = !!tsk_used_math(tsk);
-        if (fpvalid) {
-                unlazy_fpu(tsk, regs);
-                memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu));
-        }
+        if (fpvalid)
+                fpvalid = !fpregs_get(tsk, NULL, 0,
+                                      sizeof(struct user_fpu_struct),
+                                      fpu, NULL);
 #endif
 
         return fpvalid;
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index b9dbd2d3b4a5..b7aa09235b51 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/proc_fs.h>
 #include <linux/io.h>
+#include <asm/syscalls.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/mmu_context.h>
@@ -395,6 +396,7 @@ ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *))
 int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
 {
         struct pt_regs regs;
+        int pid;
 
         memset(&regs, 0, sizeof(regs));
         regs.regs[2] = (unsigned long)arg;
@@ -403,8 +405,13 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
         regs.pc = (unsigned long)kernel_thread_helper;
         regs.sr = (1 << 30);
 
-        return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
-                       &regs, 0, NULL, NULL);
+        /* Ok, create the new process.. */
+        pid = do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
+                      &regs, 0, NULL, NULL);
+
+        trace_mark(kernel_arch_kthread_create, "pid %d fn %p", pid, fn);
+
+        return pid;
 }
 
 /*
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 035cb300d3dc..29ca09d24ef8 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -1,12 +1,14 @@
 /*
- * linux/arch/sh/kernel/ptrace.c
+ * SuperH process tracing
  *
- * Original x86 implementation:
- *      By Ross Biro 1/23/92
- *      edited by Linus Torvalds
+ * Copyright (C) 1999, 2000  Kaz Kojima & Niibe Yutaka
+ * Copyright (C) 2002 - 2008  Paul Mundt
  *
- * SuperH version:   Copyright (C) 1999, 2000  Kaz Kojima & Niibe Yutaka
- * Audit support: Yuichi Nakamura <ynakam@hitachisoft.jp>
+ * Audit support by Yuichi Nakamura <ynakam@hitachisoft.jp>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  */
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -22,16 +24,15 @@
 #include <linux/audit.h>
 #include <linux/seccomp.h>
 #include <linux/tracehook.h>
+#include <linux/elf.h>
+#include <linux/regset.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/mmu_context.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
+#include <asm/syscalls.h>
+#include <asm/fpu.h>
 
 /*
  * This routine will get a word off of the process kernel stack.
@@ -61,16 +62,12 @@ static inline int put_stack_long(struct task_struct *task, int offset,
 
 void user_enable_single_step(struct task_struct *child)
 {
-        struct pt_regs *regs = task_pt_regs(child);
-        long pc;
-
-        pc = get_stack_long(child, (long)&regs->pc);
-
         /* Next scheduling will set up UBC */
         if (child->thread.ubc_pc == 0)
                 ubc_usercnt += 1;
 
-        child->thread.ubc_pc = pc;
+        child->thread.ubc_pc = get_stack_long(child,
+                                offsetof(struct pt_regs, pc));
 
         set_tsk_thread_flag(child, TIF_SINGLESTEP);
 }
@@ -102,9 +99,213 @@ void ptrace_disable(struct task_struct *child)
         user_disable_single_step(child);
 }
 
+static int genregs_get(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       void *kbuf, void __user *ubuf)
+{
+        const struct pt_regs *regs = task_pt_regs(target);
+        int ret;
+
+        ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                  regs->regs,
+                                  0, 16 * sizeof(unsigned long));
+        if (!ret)
+                /* PC, PR, SR, GBR, MACH, MACL, TRA */
+                ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                          &regs->pc,
+                                          offsetof(struct pt_regs, pc),
+                                          sizeof(struct pt_regs));
+        if (!ret)
+                ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
+                                               sizeof(struct pt_regs), -1);
+
+        return ret;
+}
+
+static int genregs_set(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       const void *kbuf, const void __user *ubuf)
+{
+        struct pt_regs *regs = task_pt_regs(target);
+        int ret;
+
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                 regs->regs,
+                                 0, 16 * sizeof(unsigned long));
+        if (!ret && count > 0)
+                ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                         &regs->pc,
+                                         offsetof(struct pt_regs, pc),
+                                         sizeof(struct pt_regs));
+        if (!ret)
+                ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+                                                sizeof(struct pt_regs), -1);
+
+        return ret;
+}
+
+#ifdef CONFIG_SH_FPU
+int fpregs_get(struct task_struct *target,
+               const struct user_regset *regset,
+               unsigned int pos, unsigned int count,
+               void *kbuf, void __user *ubuf)
+{
+        int ret;
+
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
+
+        if ((boot_cpu_data.flags & CPU_HAS_FPU))
+                return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                           &target->thread.fpu.hard, 0, -1);
+
+        return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                   &target->thread.fpu.soft, 0, -1);
+}
+
+static int fpregs_set(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       const void *kbuf, const void __user *ubuf)
+{
+        int ret;
+
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
+
+        set_stopped_child_used_math(target);
+
+        if ((boot_cpu_data.flags & CPU_HAS_FPU))
+                return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                          &target->thread.fpu.hard, 0, -1);
+
+        return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                  &target->thread.fpu.soft, 0, -1);
+}
+
+static int fpregs_active(struct task_struct *target,
+                         const struct user_regset *regset)
+{
+        return tsk_used_math(target) ? regset->n : 0;
+}
+#endif
+
+#ifdef CONFIG_SH_DSP
+static int dspregs_get(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       void *kbuf, void __user *ubuf)
+{
+        const struct pt_dspregs *regs = task_pt_dspregs(target);
+        int ret;
+
+        ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, regs,
+                                  0, sizeof(struct pt_dspregs));
+        if (!ret)
+                ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
+                                               sizeof(struct pt_dspregs), -1);
+
+        return ret;
+}
+
+static int dspregs_set(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       const void *kbuf, const void __user *ubuf)
+{
+        struct pt_dspregs *regs = task_pt_dspregs(target);
+        int ret;
+
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs,
+                                 0, sizeof(struct pt_dspregs));
+        if (!ret)
+                ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+                                                sizeof(struct pt_dspregs), -1);
+
+        return ret;
+}
+
+static int dspregs_active(struct task_struct *target,
+                          const struct user_regset *regset)
+{
+        struct pt_regs *regs = task_pt_regs(target);
+
+        return regs->sr & SR_DSP ? regset->n : 0;
+}
+#endif
+
+/*
+ * These are our native regset flavours.
+ */
+enum sh_regset {
+        REGSET_GENERAL,
+#ifdef CONFIG_SH_FPU
+        REGSET_FPU,
+#endif
+#ifdef CONFIG_SH_DSP
+        REGSET_DSP,
+#endif
+};
+
+static const struct user_regset sh_regsets[] = {
+        /*
+         * Format is:
+         *      R0 --> R15
+         *      PC, PR, SR, GBR, MACH, MACL, TRA
+         */
+        [REGSET_GENERAL] = {
+                .core_note_type = NT_PRSTATUS,
+                .n              = ELF_NGREG,
+                .size           = sizeof(long),
+                .align          = sizeof(long),
+                .get            = genregs_get,
+                .set            = genregs_set,
+        },
+
+#ifdef CONFIG_SH_FPU
+        [REGSET_FPU] = {
+                .core_note_type = NT_PRFPREG,
+                .n              = sizeof(struct user_fpu_struct) / sizeof(long),
+                .size           = sizeof(long),
+                .align          = sizeof(long),
+                .get            = fpregs_get,
+                .set            = fpregs_set,
+                .active         = fpregs_active,
+        },
+#endif
+
+#ifdef CONFIG_SH_DSP
+        [REGSET_DSP] = {
+                .n              = sizeof(struct pt_dspregs) / sizeof(long),
+                .size           = sizeof(long),
+                .align          = sizeof(long),
+                .get            = dspregs_get,
+                .set            = dspregs_set,
+                .active         = dspregs_active,
+        },
+#endif
+};
+
+static const struct user_regset_view user_sh_native_view = {
+        .name           = "sh",
+        .e_machine      = EM_SH,
+        .regsets        = sh_regsets,
+        .n              = ARRAY_SIZE(sh_regsets),
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+        return &user_sh_native_view;
+}
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         struct user * dummy = NULL;
+        unsigned long __user *datap = (unsigned long __user *)data;
         int ret;
 
         switch (request) {
@@ -133,7 +334,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         tmp = !!tsk_used_math(child);
                 else
                         tmp = 0;
-                ret = put_user(tmp, (unsigned long __user *)data);
+                ret = put_user(tmp, datap);
                 break;
         }
 
@@ -157,34 +358,39 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 }
                 break;
 
+        case PTRACE_GETREGS:
+                return copy_regset_to_user(child, &user_sh_native_view,
+                                           REGSET_GENERAL,
+                                           0, sizeof(struct pt_regs),
+                                           (void __user *)data);
+        case PTRACE_SETREGS:
+                return copy_regset_from_user(child, &user_sh_native_view,
+                                             REGSET_GENERAL,
+                                             0, sizeof(struct pt_regs),
+                                             (const void __user *)data);
+#ifdef CONFIG_SH_FPU
+        case PTRACE_GETFPREGS:
+                return copy_regset_to_user(child, &user_sh_native_view,
+                                           REGSET_FPU,
+                                           0, sizeof(struct user_fpu_struct),
+                                           (void __user *)data);
+        case PTRACE_SETFPREGS:
+                return copy_regset_from_user(child, &user_sh_native_view,
+                                             REGSET_FPU,
+                                             0, sizeof(struct user_fpu_struct),
+                                             (const void __user *)data);
+#endif
 #ifdef CONFIG_SH_DSP
-        case PTRACE_GETDSPREGS: {
-                unsigned long dp;
-
-                ret = -EIO;
-                dp = ((unsigned long) child) + THREAD_SIZE -
-                         sizeof(struct pt_dspregs);
-                if (*((int *) (dp - 4)) == SR_FD) {
-                        copy_to_user((void *)addr, (void *) dp,
-                                sizeof(struct pt_dspregs));
-                        ret = 0;
-                }
-                break;
-        }
-
-        case PTRACE_SETDSPREGS: {
-                unsigned long dp;
-
-                ret = -EIO;
-                dp = ((unsigned long) child) + THREAD_SIZE -
-                         sizeof(struct pt_dspregs);
-                if (*((int *) (dp - 4)) == SR_FD) {
-                        copy_from_user((void *) dp, (void *)addr,
-                                sizeof(struct pt_dspregs));
-                        ret = 0;
-                }
-                break;
-        }
+        case PTRACE_GETDSPREGS:
+                return copy_regset_to_user(child, &user_sh_native_view,
+                                           REGSET_DSP,
+                                           0, sizeof(struct pt_dspregs),
+                                           (void __user *)data);
+        case PTRACE_SETDSPREGS:
+                return copy_regset_from_user(child, &user_sh_native_view,
+                                             REGSET_DSP,
+                                             0, sizeof(struct pt_dspregs),
+                                             (const void __user *)data);
 #endif
 #ifdef CONFIG_BINFMT_ELF_FDPIC
         case PTRACE_GETFDPIC: {
@@ -202,7 +408,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 }
 
                 ret = 0;
-                if (put_user(tmp, (unsigned long *) data)) {
+                if (put_user(tmp, datap)) {
                         ret = -EFAULT;
                         break;
                 }
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 9c6424892bd3..e15b099c1f06 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -35,6 +35,7 @@
 #include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/mmu_context.h>
+#include <asm/syscalls.h>
 #include <asm/fpu.h>
 
 /* This mask defines the bits of the SR which the user is not allowed to
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index de832056bf1b..e7152cc6930e 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -26,6 +26,9 @@
 #include <linux/err.h>
 #include <linux/debugfs.h>
 #include <linux/crash_dump.h>
+#include <linux/mmzone.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
@@ -144,6 +147,7 @@ static void __init reserve_crashkernel(void)
 {
         unsigned long long free_mem;
         unsigned long long crash_size, crash_base;
+        void *vp;
         int ret;
 
         free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
@@ -152,12 +156,14 @@ static void __init reserve_crashkernel(void)
                         &crash_size, &crash_base);
         if (ret == 0 && crash_size) {
                 if (crash_base <= 0) {
-                        printk(KERN_INFO "crashkernel reservation failed - "
-                                        "you have to specify a base address\n");
-                        return;
-                }
-
-                if (reserve_bootmem(crash_base, crash_size,
+                        vp = alloc_bootmem_nopanic(crash_size); 
+                        if (!vp) {
+                                printk(KERN_INFO "crashkernel allocation "
+                                       "failed\n");
+                                return;
+                        }
+                        crash_base = __pa(vp);
+                } else if (reserve_bootmem(crash_base, crash_size,
                                         BOOTMEM_EXCLUSIVE) < 0) {
                         printk(KERN_INFO "crashkernel reservation failed - "
                                         "memory is in use\n");
@@ -179,6 +185,24 @@ static inline void __init reserve_crashkernel(void)
 {}
 #endif
 
+#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
+void __cpuinit calibrate_delay(void)
+{
+        struct clk *clk = clk_get(NULL, "cpu_clk");
+
+        if (IS_ERR(clk))
+                panic("Need a sane CPU clock definition!");
+
+        loops_per_jiffy = (clk_get_rate(clk) >> 1) / HZ;
+
+        printk(KERN_INFO "Calibrating delay loop (skipped)... "
+                         "%lu.%02lu BogoMIPS PRESET (lpj=%lu)\n",
+                         loops_per_jiffy/(500000/HZ),
+                         (loops_per_jiffy/(5000/HZ)) % 100,
+                         loops_per_jiffy);
+}
+#endif
+
 void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
                                                 unsigned long end_pfn)
 {
@@ -232,15 +256,17 @@ void __init setup_bootmem_allocator(unsigned long free_pfn)
          * case of us accidentally initializing the bootmem allocator with
          * an invalid RAM area.
          */
-        reserve_bootmem(__MEMORY_START+PAGE_SIZE,
-                (PFN_PHYS(free_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START,
-                BOOTMEM_DEFAULT);
+        reserve_bootmem(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET,
+                        (PFN_PHYS(free_pfn) + bootmap_size + PAGE_SIZE - 1) -
+                        (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET),
+                        BOOTMEM_DEFAULT);
 
         /*
          * reserve physical page 0 - it's a special BIOS page on many boxes,
          * enabling clean reboots, SMP operation, laptop functions.
          */
-        reserve_bootmem(__MEMORY_START, PAGE_SIZE, BOOTMEM_DEFAULT);
+        reserve_bootmem(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET,
+                        BOOTMEM_DEFAULT);
 
         sparse_memory_present_with_active_regions(0);
 
@@ -248,17 +274,18 @@ void __init setup_bootmem_allocator(unsigned long free_pfn)
         ROOT_DEV = Root_RAM0;
 
         if (LOADER_TYPE && INITRD_START) {
-                if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
-                        reserve_bootmem(INITRD_START + __MEMORY_START,
-                                        INITRD_SIZE, BOOTMEM_DEFAULT);
-                        initrd_start = INITRD_START + PAGE_OFFSET +
-                                        __MEMORY_START;
+                unsigned long initrd_start_phys = INITRD_START + __MEMORY_START;
+
+                if (initrd_start_phys + INITRD_SIZE <= PFN_PHYS(max_low_pfn)) {
+                        reserve_bootmem(initrd_start_phys, INITRD_SIZE,
+                                        BOOTMEM_DEFAULT);
+                        initrd_start = (unsigned long)__va(initrd_start_phys);
                         initrd_end = initrd_start + INITRD_SIZE;
                 } else {
                         printk("initrd extends beyond end of memory "
-                            "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
-                                    INITRD_START + INITRD_SIZE,
-                                    max_low_pfn << PAGE_SHIFT);
+                               "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
+                               initrd_start_phys + INITRD_SIZE,
+                               (unsigned long)PFN_PHYS(max_low_pfn));
                         initrd_start = 0;
                 }
         }
@@ -530,6 +557,8 @@ struct dentry *sh_debugfs_root;
 static int __init sh_debugfs_init(void)
 {
         sh_debugfs_root = debugfs_create_dir("sh", NULL);
+        if (!sh_debugfs_root)
+                return -ENOMEM;
         if (IS_ERR(sh_debugfs_root))
                 return PTR_ERR(sh_debugfs_root);
 
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index 6e1b1c271658..d917b7b4042b 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -16,6 +16,7 @@
 #include <asm/delay.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
+#include <asm/ftrace.h>
 
 extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
 extern struct hw_interrupt_type no_irq_type;
@@ -133,6 +134,9 @@ EXPORT_SYMBOL(__flush_purge_region);
 EXPORT_SYMBOL(clear_user_page);
 #endif
 
+#ifdef CONFIG_FTRACE
+EXPORT_SYMBOL(mcount);
+#endif
 EXPORT_SYMBOL(csum_partial);
 EXPORT_SYMBOL(csum_partial_copy_generic);
 #ifdef CONFIG_IPV6
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 51689d29ad45..69d09c0b3498 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -30,6 +30,7 @@
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
+#include <asm/syscalls.h>
 #include <asm/fpu.h>
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
@@ -215,6 +216,9 @@ asmlinkage int sys_sigreturn(unsigned long r4, unsigned long r5,
         sigset_t set;
         int r0;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
                 goto badframe;
 
@@ -247,9 +251,11 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
         struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs->regs[15];
         sigset_t set;
-        stack_t st;
         int r0;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
                 goto badframe;
 
@@ -265,11 +271,9 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
                 goto badframe;
 
-        if (__copy_from_user(&st, &frame->uc.uc_stack, sizeof(st)))
+        if (do_sigaltstack(&frame->uc.uc_stack, NULL,
+                           regs->regs[15]) == -EFAULT)
                 goto badframe;
-        /* It is more difficult to avoid calling this function than to
-           call it and ignore errors.  */
-        do_sigaltstack((const stack_t __user *)&st, NULL, (unsigned long)frame);
 
         return r0;
 
@@ -429,7 +433,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* Create the ucontext.  */
         err |= __put_user(0, &frame->uc.uc_flags);
-        err |= __put_user(0, &frame->uc.uc_link);
+        err |= __put_user(NULL, &frame->uc.uc_link);
         err |= __put_user((void *)current->sas_ss_sp,
                           &frame->uc.uc_stack.ss_sp);
         err |= __put_user(sas_ss_flags(regs->regs[15]),
@@ -492,37 +496,43 @@ give_sigsegv:
         return -EFAULT;
 }
 
+static inline void
+handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs,
+                       struct sigaction *sa)
+{
+        /* If we're not from a syscall, bail out */
+        if (regs->tra < 0)
+                return;
+
+        /* check for system call restart.. */
+        switch (regs->regs[0]) {
+                case -ERESTART_RESTARTBLOCK:
+                case -ERESTARTNOHAND:
+                no_system_call_restart:
+                        regs->regs[0] = -EINTR;
+                        regs->sr |= 1;
+                        break;
+
+                case -ERESTARTSYS:
+                        if (!(sa->sa_flags & SA_RESTART))
+                                goto no_system_call_restart;
+                /* fallthrough */
+                case -ERESTARTNOINTR:
+                        regs->regs[0] = save_r0;
+                        regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
+                        break;
+        }
+}
+
 /*
  * OK, we're invoking a handler
  */
-
 static int
 handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
               sigset_t *oldset, struct pt_regs *regs, unsigned int save_r0)
 {
         int ret;
 
-        /* Are we from a system call? */
-        if (regs->tra >= 0) {
-                /* If so, check system call restarting.. */
-                switch (regs->regs[0]) {
-                        case -ERESTART_RESTARTBLOCK:
-                        case -ERESTARTNOHAND:
-                        no_system_call_restart:
-                                regs->regs[0] = -EINTR;
-                                break;
-
-                        case -ERESTARTSYS:
-                                if (!(ka->sa.sa_flags & SA_RESTART))
-                                        goto no_system_call_restart;
-                        /* fallthrough */
-                        case -ERESTARTNOINTR:
-                                regs->regs[0] = save_r0;
-                                regs->pc -= instruction_size(
-                                                ctrl_inw(regs->pc - 4));
-                                break;
-                }
-        }
 
         /* Set up the stack frame */
         if (ka->sa.sa_flags & SA_SIGINFO)
@@ -580,6 +590,9 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
 
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
         if (signr > 0) {
+                if (regs->sr & 1)
+                        handle_syscall_restart(save_r0, regs, &ka.sa);
+
                 /* Whee!  Actually deliver the signal.  */
                 if (handle_signal(signr, &ka, &info, oldset,
                                   regs, save_r0) == 0) {
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 1d62dfef77f1..ce3e851dffcb 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -43,6 +43,10 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
+static void
+handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
+                sigset_t *oldset, struct pt_regs * regs);
+
 /*
  * Note that 'init' is a special process: it doesn't get signals it doesn't
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
@@ -371,6 +375,9 @@ asmlinkage int sys_sigreturn(unsigned long r2, unsigned long r3,
         sigset_t set;
         long long ret;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
                 goto badframe;
 
@@ -408,6 +415,9 @@ asmlinkage int sys_rt_sigreturn(unsigned long r2, unsigned long r3,
         stack_t __user st;
         long long ret;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
                 goto badframe;
 
@@ -535,7 +545,7 @@ static void setup_frame(int sig, struct k_sigaction *ka,
                  * On SH5 all edited pointers are subject to NEFF
                  */
                 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
-                                (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
+                        (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
         } else {
                 /*
                  * Different approach on SH5.
@@ -550,10 +560,10 @@ static void setup_frame(int sig, struct k_sigaction *ka,
                  */
                 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01;
                 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
-                                (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
+                        (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
 
                 if (__copy_to_user(frame->retcode,
-                        (unsigned long long)sa_default_restorer & (~1), 16) != 0)
+                        (void *)((unsigned long)sa_default_restorer & (~1)), 16) != 0)
                         goto give_sigsegv;
 
                 /* Cohere the trampoline with the I-cache. */
@@ -566,7 +576,7 @@ static void setup_frame(int sig, struct k_sigaction *ka,
          */
         regs->regs[REG_SP] = (unsigned long) frame;
         regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ?
-                         (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
+                 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
         regs->regs[REG_ARG1] = signal; /* Arg for signal handler */
 
         /* FIXME:
@@ -652,7 +662,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                  * On SH5 all edited pointers are subject to NEFF
                  */
                 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
-                                (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
+                        (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
         } else {
                 /*
                  * Different approach on SH5.
@@ -668,10 +678,10 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
 
                 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01;
                 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
-                                (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
+                        (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
 
                 if (__copy_to_user(frame->retcode,
-                        (unsigned long long)sa_default_rt_restorer & (~1), 16) != 0)
+                        (void *)((unsigned long)sa_default_rt_restorer & (~1)), 16) != 0)
                         goto give_sigsegv;
 
                 flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15);
@@ -683,7 +693,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
          */
         regs->regs[REG_SP] = (unsigned long) frame;
         regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ?
-                         (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
+                 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
         regs->regs[REG_ARG1] = signal; /* Arg for signal handler */
         regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info;
         regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext;
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 001778f9adaf..508dfb023628 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -3,7 +3,7 @@
  *
  * SMP support for the SuperH processors.
  *
- * Copyright (C) 2002 - 2007 Paul Mundt
+ * Copyright (C) 2002 - 2008 Paul Mundt
  * Copyright (C) 2006 - 2007 Akio Idehara
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -86,9 +86,12 @@ asmlinkage void __cpuinit start_secondary(void)
 
         local_irq_enable();
 
+        cpu = smp_processor_id();
+
+        /* Enable local timers */
+        local_timer_setup(cpu);
         calibrate_delay();
 
-        cpu = smp_processor_id();
         smp_store_cpu_info(cpu);
 
         cpu_set(cpu, cpu_online_map);
@@ -186,6 +189,42 @@ void arch_send_call_function_single_ipi(int cpu)
         plat_send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE);
 }
 
+void smp_timer_broadcast(cpumask_t mask)
+{
+        int cpu;
+
+        for_each_cpu_mask(cpu, mask)
+                plat_send_ipi(cpu, SMP_MSG_TIMER);
+}
+
+static void ipi_timer(void)
+{
+        irq_enter();
+        local_timer_interrupt();
+        irq_exit();
+}
+
+void smp_message_recv(unsigned int msg)
+{
+        switch (msg) {
+        case SMP_MSG_FUNCTION:
+                generic_smp_call_function_interrupt();
+                break;
+        case SMP_MSG_RESCHEDULE:
+                break;
+        case SMP_MSG_FUNCTION_SINGLE:
+                generic_smp_call_function_single_interrupt();
+                break;
+        case SMP_MSG_TIMER:
+                ipi_timer();
+                break;
+        default:
+                printk(KERN_WARNING "SMP %d: %s(): unknown IPI %d\n",
+                       smp_processor_id(), __func__, msg);
+                break;
+        }
+}
+
 /* Not really SMP stuff ... */
 int setup_profiling_timer(unsigned int multiplier)
 {
diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c
index 54d1f61aa007..1a2a5eb76e41 100644
--- a/arch/sh/kernel/stacktrace.c
+++ b/arch/sh/kernel/stacktrace.c
@@ -3,7 +3,7 @@
  *
  * Stack trace management functions
  *
- *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2006 - 2008  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -36,3 +36,24 @@ void save_stack_trace(struct stack_trace *trace)
         }
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+        unsigned long *sp = (unsigned long *)tsk->thread.sp;
+
+        while (!kstack_end(sp)) {
+                unsigned long addr = *sp++;
+
+                if (__kernel_text_address(addr)) {
+                        if (in_sched_functions(addr))
+                                break;
+                        if (trace->skip > 0)
+                                trace->skip--;
+                        else
+                                trace->entries[trace->nr_entries++] = addr;
+                        if (trace->nr_entries >= trace->max_entries)
+                                break;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 9061b86d73fa..38f098c9c72d 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -23,6 +23,7 @@
 #include <linux/fs.h>
 #include <linux/ipc.h>
 #include <asm/cacheflush.h>
+#include <asm/syscalls.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 
@@ -170,6 +171,8 @@ asmlinkage int sys_ipc(uint call, int first, int second,
         version = call >> 16; /* hack for backward compatibility */
         call &= 0xffff;
 
+        trace_mark(kernel_arch_ipc_call, "call %u first %d", call, first);
+
         if (call <= SEMTIMEDOP)
                 switch (call) {
                 case SEMOP:
@@ -186,7 +189,7 @@ asmlinkage int sys_ipc(uint call, int first, int second,
                         union semun fourth;
                         if (!ptr)
                                 return -EINVAL;
-                        if (get_user(fourth.__pad, (void * __user *) ptr))
+                        if (get_user(fourth.__pad, (void __user * __user *) ptr))
                                 return -EFAULT;
                         return sys_semctl (first, second, third, fourth);
                         }
@@ -261,13 +264,13 @@ asmlinkage int sys_ipc(uint call, int first, int second,
         return -EINVAL;
 }
 
-asmlinkage int sys_uname(struct old_utsname * name)
+asmlinkage int sys_uname(struct old_utsname __user *name)
 {
         int err;
         if (!name)
                 return -EFAULT;
         down_read(&uts_sem);
-        err = copy_to_user(name, utsname(), sizeof (*name));
+        err = copy_to_user(name, utsname(), sizeof(*name));
         up_read(&uts_sem);
         return err?-EFAULT:0;
 }
diff --git a/arch/sh/kernel/sys_sh32.c b/arch/sh/kernel/sys_sh32.c
index f0aa5c398656..dbba1e1833d4 100644
--- a/arch/sh/kernel/sys_sh32.c
+++ b/arch/sh/kernel/sys_sh32.c
@@ -16,6 +16,7 @@
 #include <asm/cacheflush.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
+#include <asm/syscalls.h>
 
 /*
  * sys_pipe() is the normal C calling standard for creating
@@ -37,13 +38,13 @@ asmlinkage int sys_pipe(unsigned long r4, unsigned long r5,
         return error;
 }
 
-asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char * buf,
+asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf,
                              size_t count, long dummy, loff_t pos)
 {
         return sys_pread64(fd, buf, count, pos);
 }
 
-asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char * buf,
+asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf,
                               size_t count, long dummy, loff_t pos)
 {
         return sys_pwrite64(fd, buf, count, pos);
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
index 0758b5ee8180..23ca711c27d2 100644
--- a/arch/sh/kernel/time_32.c
+++ b/arch/sh/kernel/time_32.c
@@ -1,9 +1,9 @@
 /*
- *  arch/sh/kernel/time.c
+ *  arch/sh/kernel/time_32.c
  *
  *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
  *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
- *  Copyright (C) 2002 - 2007  Paul Mundt
+ *  Copyright (C) 2002 - 2008  Paul Mundt
  *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
  *
  *  Some code taken from i386 version.
@@ -16,6 +16,8 @@
 #include <linux/timex.h>
 #include <linux/sched.h>
 #include <linux/clockchips.h>
+#include <linux/mc146818rtc.h>  /* for rtc_lock */
+#include <linux/smp.h>
 #include <asm/clock.h>
 #include <asm/rtc.h>
 #include <asm/timer.h>
@@ -253,6 +255,10 @@ void __init time_init(void)
         set_normalized_timespec(&wall_to_monotonic,
                                 -xtime.tv_sec, -xtime.tv_nsec);
 
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+        local_timer_setup(smp_processor_id());
+#endif
+
         /*
          * Find the timer to use as the system timer, it will be
          * initialized for us.
@@ -260,6 +266,7 @@ void __init time_init(void)
         sys_timer = get_sys_timer();
         printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
 
+
         if (sys_timer->ops->read)
                 clocksource_sh.read = sys_timer->ops->read;
 
diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c
index 791edabf7d83..bbb2af1004d9 100644
--- a/arch/sh/kernel/time_64.c
+++ b/arch/sh/kernel/time_64.c
@@ -39,6 +39,7 @@
 #include <asm/processor.h>
 #include <asm/uaccess.h>
 #include <asm/delay.h>
+#include <asm/clock.h>
 
 #define TMU_TOCR_INIT   0x00
 #define TMU0_TCR_INIT   0x0020
@@ -51,14 +52,6 @@
 #define RTC_RCR1_CIE    0x10    /* Carry Interrupt Enable */
 #define RTC_RCR1        (rtc_base + 0x38)
 
-/* Clock, Power and Reset Controller */
-#define CPRC_BLOCK_OFF  0x01010000
-#define CPRC_BASE       PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF
-
-#define FRQCR           (cprc_base+0x0)
-#define WTCSR           (cprc_base+0x0018)
-#define STBCR           (cprc_base+0x0030)
-
 /* Time Management Unit */
 #define TMU_BLOCK_OFF   0x01020000
 #define TMU_BASE        PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
@@ -293,103 +286,17 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-
-static __init unsigned int get_cpu_hz(void)
-{
-        unsigned int count;
-        unsigned long __dummy;
-        unsigned long ctc_val_init, ctc_val;
-
-        /*
-        ** Regardless the toolchain, force the compiler to use the
-        ** arbitrary register r3 as a clock tick counter.
-        ** NOTE: r3 must be in accordance with sh64_rtc_interrupt()
-        */
-        register unsigned long long  __rtc_irq_flag __asm__ ("r3");
-
-        local_irq_enable();
-        do {} while (ctrl_inb(rtc_base) != 0);
-        ctrl_outb(RTC_RCR1_CIE, RTC_RCR1); /* Enable carry interrupt */
-
-        /*
-         * r3 is arbitrary. CDC does not support "=z".
-         */
-        ctc_val_init = 0xffffffff;
-        ctc_val = ctc_val_init;
-
-        asm volatile("gettr     tr0, %1\n\t"
-                     "putcon    %0, " __CTC "\n\t"
-                     "and       %2, r63, %2\n\t"
-                     "pta       $+4, tr0\n\t"
-                     "beq/l     %2, r63, tr0\n\t"
-                     "ptabs     %1, tr0\n\t"
-                     "getcon    " __CTC ", %0\n\t"
-                : "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag)
-                : "0" (0));
-        local_irq_disable();
-        /*
-         * SH-3:
-         * CPU clock = 4 stages * loop
-         * tst    rm,rm      if id ex
-         * bt/s   1b            if id ex
-         * add    #1,rd            if id ex
-         *                            (if) pipe line stole
-         * tst    rm,rm                  if id ex
-         * ....
-         *
-         *
-         * SH-4:
-         * CPU clock = 6 stages * loop
-         * I don't know why.
-         * ....
-         *
-         * SH-5:
-         * Use CTC register to count.  This approach returns the right value
-         * even if the I-cache is disabled (e.g. whilst debugging.)
-         *
-         */
-
-        count = ctc_val_init - ctc_val; /* CTC counts down */
-
-        /*
-         * This really is count by the number of clock cycles
-         * by the ratio between a complete R64CNT
-         * wrap-around (128) and CUI interrupt being raised (64).
-         */
-        return count*2;
-}
-
-static irqreturn_t sh64_rtc_interrupt(int irq, void *dev_id)
-{
-        struct pt_regs *regs = get_irq_regs();
-
-        ctrl_outb(0, RTC_RCR1); /* Disable Carry Interrupts */
-        regs->regs[3] = 1;      /* Using r3 */
-
-        return IRQ_HANDLED;
-}
-
 static struct irqaction irq0  = {
         .handler = timer_interrupt,
         .flags = IRQF_DISABLED,
         .mask = CPU_MASK_NONE,
         .name = "timer",
 };
-static struct irqaction irq1  = {
-        .handler = sh64_rtc_interrupt,
-        .flags = IRQF_DISABLED,
-        .mask = CPU_MASK_NONE,
-        .name = "rtc",
-};
 
 void __init time_init(void)
 {
-        unsigned int cpu_clock, master_clock, bus_clock, module_clock;
         unsigned long interval;
-        unsigned long frqcr, ifc, pfc;
-        static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
-#define bfc_table ifc_table     /* Same */
-#define pfc_table ifc_table     /* Same */
+        struct clk *clk;
 
         tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
         if (!tmu_base) {
@@ -401,50 +308,19 @@ void __init time_init(void)
                 panic("Unable to remap RTC\n");
         }
 
-        cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
-        if (!cprc_base) {
-                panic("Unable to remap CPRC\n");
-        }
+        clk = clk_get(NULL, "cpu_clk");
+        scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) /
+                        (unsigned long long)(clk_get_rate(clk) / HZ));
 
         rtc_sh_get_time(&xtime);
 
         setup_irq(TIMER_IRQ, &irq0);
-        setup_irq(RTC_IRQ, &irq1);
-
-        /* Check how fast it is.. */
-        cpu_clock = get_cpu_hz();
-
-        /* Note careful order of operations to maintain reasonable precision and avoid overflow. */
-        scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ));
-
-        free_irq(RTC_IRQ, NULL);
-
-        printk("CPU clock: %d.%02dMHz\n",
-               (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
-        {
-                unsigned short bfc;
-                frqcr = ctrl_inl(FRQCR);
-                ifc  = ifc_table[(frqcr>> 6) & 0x0007];
-                bfc  = bfc_table[(frqcr>> 3) & 0x0007];
-                pfc  = pfc_table[(frqcr>> 12) & 0x0007];
-                master_clock = cpu_clock * ifc;
-                bus_clock = master_clock/bfc;
-        }
 
-        printk("Bus clock: %d.%02dMHz\n",
-               (bus_clock/1000000), (bus_clock % 1000000)/10000);
-        module_clock = master_clock/pfc;
-        printk("Module clock: %d.%02dMHz\n",
-               (module_clock/1000000), (module_clock % 1000000)/10000);
-        interval = (module_clock/(HZ*4));
+        clk = clk_get(NULL, "module_clk");
+        interval = (clk_get_rate(clk)/(HZ*4));
 
         printk("Interval = %ld\n", interval);
 
-        current_cpu_data.cpu_clock    = cpu_clock;
-        current_cpu_data.master_clock = master_clock;
-        current_cpu_data.bus_clock    = bus_clock;
-        current_cpu_data.module_clock = module_clock;
-
         /* Start TMU0 */
         ctrl_outb(TMU_TSTR_OFF, TMU_TSTR);
         ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
@@ -454,36 +330,6 @@ void __init time_init(void)
         ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
 }
 
-void enter_deep_standby(void)
-{
-        /* Disable watchdog timer */
-        ctrl_outl(0xa5000000, WTCSR);
-        /* Configure deep standby on sleep */
-        ctrl_outl(0x03, STBCR);
-
-#ifdef CONFIG_SH_ALPHANUMERIC
-        {
-                extern void mach_alphanum(int position, unsigned char value);
-                extern void mach_alphanum_brightness(int setting);
-                char halted[] = "Halted. ";
-                int i;
-                mach_alphanum_brightness(6); /* dimmest setting above off */
-                for (i=0; i<8; i++) {
-                        mach_alphanum(i, halted[i]);
-                }
-                asm __volatile__ ("synco");
-        }
-#endif
-
-        asm __volatile__ ("sleep");
-        asm __volatile__ ("synci");
-        asm __volatile__ ("nop");
-        asm __volatile__ ("nop");
-        asm __volatile__ ("nop");
-        asm __volatile__ ("nop");
-        panic("Unexpected wakeup!\n");
-}
-
 static struct resource rtc_resources[] = {
         [0] = {
                 /* RTC base, filled in by rtc_init */
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
index bcf244ff6a12..0b7f8577193f 100644
--- a/arch/sh/kernel/timers/Makefile
+++ b/arch/sh/kernel/timers/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SH_TMU)		+= timer-tmu.o
 obj-$(CONFIG_SH_MTU2)           += timer-mtu2.o
 obj-$(CONFIG_SH_CMT)            += timer-cmt.o
 
+obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += timer-broadcast.o
diff --git a/arch/sh/kernel/timers/timer-broadcast.c b/arch/sh/kernel/timers/timer-broadcast.c
new file mode 100644
index 000000000000..c2317635230f
--- /dev/null
+++ b/arch/sh/kernel/timers/timer-broadcast.c
@@ -0,0 +1,57 @@
+/*
+ * Dummy local timer
+ *
+ * Copyright (C) 2008  Paul Mundt
+ *
+ * cloned from:
+ *
+ *  linux/arch/arm/mach-realview/localtimer.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/jiffies.h>
+#include <linux/percpu.h>
+#include <linux/clockchips.h>
+#include <linux/irq.h>
+
+static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
+
+/*
+ * Used on SMP for either the local timer or SMP_MSG_TIMER
+ */
+void local_timer_interrupt(void)
+{
+        struct clock_event_device *clk = &__get_cpu_var(local_clockevent);
+
+        clk->event_handler(clk);
+}
+
+static void dummy_timer_set_mode(enum clock_event_mode mode,
+                                 struct clock_event_device *clk)
+{
+}
+
+void __cpuinit local_timer_setup(unsigned int cpu)
+{
+        struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
+
+        clk->name               = "dummy_timer";
+        clk->features           = CLOCK_EVT_FEAT_DUMMY;
+        clk->rating             = 200;
+        clk->mult               = 1;
+        clk->set_mode           = dummy_timer_set_mode;
+        clk->broadcast          = smp_timer_broadcast;
+        clk->cpumask            = cpumask_of_cpu(cpu);
+
+        clockevents_register_device(clk);
+}
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
index d20c8c375881..c127293271e1 100644
--- a/arch/sh/kernel/timers/timer-cmt.c
+++ b/arch/sh/kernel/timers/timer-cmt.c
@@ -174,7 +174,7 @@ static int cmt_timer_init(void)
         return 0;
 }
 
-struct sys_timer_ops cmt_timer_ops = {
+static struct sys_timer_ops cmt_timer_ops = {
         .init           = cmt_timer_init,
         .start          = cmt_timer_start,
         .stop           = cmt_timer_stop,
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 1ca9ad49b541..aaaf90d06b85 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -28,43 +28,90 @@
 #define TMU_TOCR_INIT   0x00
 #define TMU_TCR_INIT    0x0020
 
-static int tmu_timer_start(void)
+#define TMU0            (0)
+#define TMU1            (1)
+
+static inline void _tmu_start(int tmu_num)
 {
-        ctrl_outb(ctrl_inb(TMU_012_TSTR) | 0x3, TMU_012_TSTR);
-        return 0;
+        ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
 }
 
-static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload)
+static inline void _tmu_set_irq(int tmu_num, int enabled)
 {
-        ctrl_outl(interval, TMU0_TCNT);
+        register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
+        ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
+}
 
-        /*
-         * TCNT reloads from TCOR on underflow, clear it if we don't
-         * intend to auto-reload
-         */
-        if (reload)
-                ctrl_outl(interval, TMU0_TCOR);
-        else
-                ctrl_outl(0, TMU0_TCOR);
+static inline void _tmu_stop(int tmu_num)
+{
+        ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
+}
+
+static inline void _tmu_clear_status(int tmu_num)
+{
+        register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
+        /* Clear UNF bit */
+        ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
+}
 
-        tmu_timer_start();
+static inline unsigned long _tmu_read(int tmu_num)
+{
+        return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
+}
+
+static int tmu_timer_start(void)
+{
+        _tmu_start(TMU0);
+        _tmu_start(TMU1);
+        _tmu_set_irq(TMU0,1);
+        return 0;
 }
 
 static int tmu_timer_stop(void)
 {
-        ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~0x3, TMU_012_TSTR);
+        _tmu_stop(TMU0);
+        _tmu_stop(TMU1);
+        _tmu_clear_status(TMU0);
         return 0;
 }
 
+/*
+ * also when the module_clk is scaled the TMU1
+ * will show the same frequency
+ */
+static int tmus_are_scaled;
+
 static cycle_t tmu_timer_read(void)
 {
-        return ~ctrl_inl(TMU1_TCNT);
+        return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
+}
+
+
+static unsigned long tmu_latest_interval[3];
+static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
+{
+        unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
+        unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
+
+        _tmu_stop(tmu_num);
+
+        ctrl_outl(interval, tmu_tcnt);
+        tmu_latest_interval[tmu_num] = interval;
+
+        /*
+         * TCNT reloads from TCOR on underflow, clear it if we don't
+         * intend to auto-reload
+         */
+        ctrl_outl( reload ? interval : 0 , tmu_tcor);
+
+        _tmu_start(tmu_num);
 }
 
 static int tmu_set_next_event(unsigned long cycles,
                               struct clock_event_device *evt)
 {
-        tmu0_timer_set_interval(cycles, 1);
+        tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
+        _tmu_set_irq(TMU0,1);
         return 0;
 }
 
@@ -96,12 +143,8 @@ static struct clock_event_device tmu0_clockevent = {
 static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
 {
         struct clock_event_device *evt = &tmu0_clockevent;
-        unsigned long timer_status;
-
-        /* Clear UNF bit */
-        timer_status = ctrl_inw(TMU0_TCR);
-        timer_status &= ~0x100;
-        ctrl_outw(timer_status, TMU0_TCR);
+        _tmu_clear_status(TMU0);
+        _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
 
         evt->event_handler(evt);
 
@@ -109,56 +152,73 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
 }
 
 static struct irqaction tmu0_irq = {
-        .name           = "periodic timer",
+        .name           = "periodic/oneshot timer",
         .handler        = tmu_timer_interrupt,
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
         .mask           = CPU_MASK_NONE,
 };
 
-static void tmu0_clk_init(struct clk *clk)
+static void __init tmu_clk_init(struct clk *clk)
 {
-        u8 divisor = TMU_TCR_INIT & 0x7;
-        ctrl_outw(TMU_TCR_INIT, TMU0_TCR);
-        clk->rate = clk->parent->rate / (4 << (divisor << 1));
+        u8 divisor  = TMU_TCR_INIT & 0x7;
+        int tmu_num = clk->name[3]-'0';
+        ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
+        clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
 }
 
-static void tmu0_clk_recalc(struct clk *clk)
+static void tmu_clk_recalc(struct clk *clk)
 {
-        u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
-        clk->rate = clk->parent->rate / (4 << (divisor << 1));
-}
+        int tmu_num = clk->name[3]-'0';
+        unsigned long prev_rate = clk_get_rate(clk);
+        unsigned long flags;
+        u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
+        clk->rate  = clk_get_rate(clk->parent) / (4 << (divisor << 1));
 
-static struct clk_ops tmu0_clk_ops = {
-        .init           = tmu0_clk_init,
-        .recalc         = tmu0_clk_recalc,
-};
+        if(prev_rate==clk_get_rate(clk))
+                return;
 
-static struct clk tmu0_clk = {
-        .name           = "tmu0_clk",
-        .ops            = &tmu0_clk_ops,
-};
+        if(tmu_num)
+                return; /* No more work on TMU1 */
 
-static void tmu1_clk_init(struct clk *clk)
-{
-        u8 divisor = TMU_TCR_INIT & 0x7;
-        ctrl_outw(divisor, TMU1_TCR);
-        clk->rate = clk->parent->rate / (4 << (divisor << 1));
-}
+        local_irq_save(flags);
+        tmus_are_scaled = (prev_rate > clk->rate);
 
-static void tmu1_clk_recalc(struct clk *clk)
-{
-        u8 divisor = ctrl_inw(TMU1_TCR) & 0x7;
-        clk->rate = clk->parent->rate / (4 << (divisor << 1));
+        _tmu_stop(TMU0);
+
+        tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
+                                tmu0_clockevent.shift);
+        tmu0_clockevent.max_delta_ns =
+                        clockevent_delta2ns(-1, &tmu0_clockevent);
+        tmu0_clockevent.min_delta_ns =
+                        clockevent_delta2ns(1, &tmu0_clockevent);
+
+        if (tmus_are_scaled)
+                tmu_latest_interval[TMU0] >>= 1;
+        else
+                tmu_latest_interval[TMU0] <<= 1;
+
+        tmu_timer_set_interval(TMU0,
+                tmu_latest_interval[TMU0],
+                tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
+
+        _tmu_start(TMU0);
+
+        local_irq_restore(flags);
 }
 
-static struct clk_ops tmu1_clk_ops = {
-        .init           = tmu1_clk_init,
-        .recalc         = tmu1_clk_recalc,
+static struct clk_ops tmu_clk_ops = {
+        .init           = tmu_clk_init,
+        .recalc         = tmu_clk_recalc,
+};
+
+static struct clk tmu0_clk = {
+        .name           = "tmu0_clk",
+        .ops            = &tmu_clk_ops,
 };
 
 static struct clk tmu1_clk = {
         .name           = "tmu1_clk",
-        .ops            = &tmu1_clk_ops,
+        .ops            = &tmu_clk_ops,
 };
 
 static int tmu_timer_init(void)
@@ -189,11 +249,12 @@ static int tmu_timer_init(void)
         frequency = clk_get_rate(&tmu0_clk);
         interval = (frequency + HZ / 2) / HZ;
 
-        sh_hpt_frequency = clk_get_rate(&tmu1_clk);
-        ctrl_outl(~0, TMU1_TCNT);
-        ctrl_outl(~0, TMU1_TCOR);
+        tmu_timer_set_interval(TMU0,interval, 1);
+        tmu_timer_set_interval(TMU1,~0,1);
 
-        tmu0_timer_set_interval(interval, 1);
+        _tmu_start(TMU1);
+
+        sh_hpt_frequency = clk_get_rate(&tmu1_clk);
 
         tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
                                       tmu0_clockevent.shift);
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 511a9426cec5..b359b08a8e33 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -26,6 +26,7 @@
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/fpu.h>
+#include <asm/kprobes.h>
 
 #ifdef CONFIG_SH_KGDB
 #include <asm/kgdb.h>
@@ -192,6 +193,7 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
         int ret, index, count;
         unsigned long *rm, *rn;
         unsigned char *src, *dst;
+        unsigned char __user *srcu, *dstu;
 
         index = (instruction>>8)&15;    /* 0x0F00 */
         rn = &regs->regs[index];
@@ -206,28 +208,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
         case 0: /* mov.[bwl] to/from memory via r0+rn */
                 if (instruction & 8) {
                         /* from memory */
-                        src = (unsigned char*) *rm;
-                        src += regs->regs[0];
-                        dst = (unsigned char*) rn;
-                        *(unsigned long*)dst = 0;
+                        srcu = (unsigned char __user *)*rm;
+                        srcu += regs->regs[0];
+                        dst = (unsigned char *)rn;
+                        *(unsigned long *)dst = 0;
 
 #if !defined(__LITTLE_ENDIAN__)
                         dst += 4-count;
 #endif
-                        if (ma->from(dst, src, count))
+                        if (ma->from(dst, srcu, count))
                                 goto fetch_fault;
 
                         sign_extend(count, dst);
                 } else {
                         /* to memory */
-                        src = (unsigned char*) rm;
+                        src = (unsigned char *)rm;
 #if !defined(__LITTLE_ENDIAN__)
                         src += 4-count;
 #endif
-                        dst = (unsigned char*) *rn;
-                        dst += regs->regs[0];
+                        dstu = (unsigned char __user *)*rn;
+                        dstu += regs->regs[0];
 
-                        if (ma->to(dst, src, count))
+                        if (ma->to(dstu, src, count))
                                 goto fetch_fault;
                 }
                 ret = 0;
@@ -235,10 +237,10 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
 
         case 1: /* mov.l Rm,@(disp,Rn) */
                 src = (unsigned char*) rm;
-                dst = (unsigned char*) *rn;
-                dst += (instruction&0x000F)<<2;
+                dstu = (unsigned char __user *)*rn;
+                dstu += (instruction&0x000F)<<2;
 
-                if (ma->to(dst, src, 4))
+                if (ma->to(dstu, src, 4))
                         goto fetch_fault;
                 ret = 0;
                 break;
@@ -247,28 +249,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
                 if (instruction & 4)
                         *rn -= count;
                 src = (unsigned char*) rm;
-                dst = (unsigned char*) *rn;
+                dstu = (unsigned char __user *)*rn;
 #if !defined(__LITTLE_ENDIAN__)
                 src += 4-count;
 #endif
-                if (ma->to(dst, src, count))
+                if (ma->to(dstu, src, count))
                         goto fetch_fault;
                 ret = 0;
                 break;
 
         case 5: /* mov.l @(disp,Rm),Rn */
-                src = (unsigned char*) *rm;
-                src += (instruction&0x000F)<<2;
-                dst = (unsigned char*) rn;
-                *(unsigned long*)dst = 0;
+                srcu = (unsigned char __user *)*rm;
+                srcu += (instruction & 0x000F) << 2;
+                dst = (unsigned char *)rn;
+                *(unsigned long *)dst = 0;
 
-                if (ma->from(dst, src, 4))
+                if (ma->from(dst, srcu, 4))
                         goto fetch_fault;
                 ret = 0;
                 break;
 
         case 6: /* mov.[bwl] from memory, possibly with post-increment */
-                src = (unsigned char*) *rm;
+                srcu = (unsigned char __user *)*rm;
                 if (instruction & 4)
                         *rm += count;
                 dst = (unsigned char*) rn;
@@ -277,7 +279,7 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
 #if !defined(__LITTLE_ENDIAN__)
                 dst += 4-count;
 #endif
-                if (ma->from(dst, src, count))
+                if (ma->from(dst, srcu, count))
                         goto fetch_fault;
                 sign_extend(count, dst);
                 ret = 0;
@@ -286,28 +288,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
         case 8:
                 switch ((instruction&0xFF00)>>8) {
                 case 0x81: /* mov.w R0,@(disp,Rn) */
-                        src = (unsigned char*) &regs->regs[0];
+                        src = (unsigned char *) &regs->regs[0];
 #if !defined(__LITTLE_ENDIAN__)
                         src += 2;
 #endif
-                        dst = (unsigned char*) *rm; /* called Rn in the spec */
-                        dst += (instruction&0x000F)<<1;
+                        dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
+                        dstu += (instruction & 0x000F) << 1;
 
-                        if (ma->to(dst, src, 2))
+                        if (ma->to(dstu, src, 2))
                                 goto fetch_fault;
                         ret = 0;
                         break;
 
                 case 0x85: /* mov.w @(disp,Rm),R0 */
-                        src = (unsigned char*) *rm;
-                        src += (instruction&0x000F)<<1;
-                        dst = (unsigned char*) &regs->regs[0];
-                        *(unsigned long*)dst = 0;
+                        srcu = (unsigned char __user *)*rm;
+                        srcu += (instruction & 0x000F) << 1;
+                        dst = (unsigned char *) &regs->regs[0];
+                        *(unsigned long *)dst = 0;
 
 #if !defined(__LITTLE_ENDIAN__)
                         dst += 2;
 #endif
-                        if (ma->from(dst, src, 2))
+                        if (ma->from(dst, srcu, 2))
                                 goto fetch_fault;
                         sign_extend(2, dst);
                         ret = 0;
@@ -333,7 +335,8 @@ static inline int handle_delayslot(struct pt_regs *regs,
                                    struct mem_access *ma)
 {
         opcode_t instruction;
-        void *addr = (void *)(regs->pc + instruction_size(old_instruction));
+        void __user *addr = (void __user *)(regs->pc +
+                instruction_size(old_instruction));
 
         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
                 /* the instruction-fetch faulted */
@@ -511,14 +514,6 @@ int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
         return ret;
 }
 
-#ifdef CONFIG_CPU_HAS_SR_RB
-#define lookup_exception_vector(x)      \
-        __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
-#else
-#define lookup_exception_vector(x)      \
-        __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
-#endif
-
 /*
  * Handle various address error exceptions:
  *  - instruction address error:
@@ -542,7 +537,7 @@ asmlinkage void do_address_error(struct pt_regs *regs,
 
         /* Intentional ifdef */
 #ifdef CONFIG_CPU_HAS_SR_RB
-        lookup_exception_vector(error_code);
+        error_code = lookup_exception_vector();
 #endif
 
         oldfs = get_fs();
@@ -559,7 +554,7 @@ asmlinkage void do_address_error(struct pt_regs *regs,
                 }
 
                 set_fs(USER_DS);
-                if (copy_from_user(&instruction, (void *)(regs->pc),
+                if (copy_from_user(&instruction, (void __user *)(regs->pc),
                                    sizeof(instruction))) {
                         /* Argh. Fault on the instruction itself.
                            This should never happen non-SMP
@@ -589,7 +584,7 @@ uspace_segv:
                         die("unaligned program counter", regs, error_code);
 
                 set_fs(KERNEL_DS);
-                if (copy_from_user(&instruction, (void *)(regs->pc),
+                if (copy_from_user(&instruction, (void __user *)(regs->pc),
                                    sizeof(instruction))) {
                         /* Argh. Fault on the instruction itself.
                            This should never happen non-SMP
@@ -683,7 +678,7 @@ asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
         }
 #endif
 
-        lookup_exception_vector(error_code);
+        error_code = lookup_exception_vector();
 
         local_irq_enable();
         CHK_REMOTE_DEBUG(regs);
@@ -739,11 +734,13 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
                                 struct pt_regs __regs)
 {
         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
-        unsigned long error_code;
+        unsigned long inst;
         struct task_struct *tsk = current;
-#ifdef CONFIG_SH_FPU_EMU
-        unsigned short inst = 0;
 
+        if (kprobe_handle_illslot(regs->pc) == 0)
+                return;
+
+#ifdef CONFIG_SH_FPU_EMU
         get_user(inst, (unsigned short *)regs->pc + 1);
         if (!do_fpu_inst(inst, regs)) {
                 get_user(inst, (unsigned short *)regs->pc);
@@ -754,12 +751,12 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
         /* not a FPU inst. */
 #endif
 
-        lookup_exception_vector(error_code);
+        inst = lookup_exception_vector();
 
         local_irq_enable();
         CHK_REMOTE_DEBUG(regs);
         force_sig(SIGILL, tsk);
-        die_if_no_fixup("illegal slot instruction", regs, error_code);
+        die_if_no_fixup("illegal slot instruction", regs, inst);
 }
 
 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
@@ -769,7 +766,7 @@ asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
         long ex;
 
-        lookup_exception_vector(ex);
+        ex = lookup_exception_vector();
         die_if_kernel("exception", regs, ex);
 }
 
diff --git a/arch/sh/lib/div64-generic.c b/arch/sh/lib/div64-generic.c
index 4bef3b5d964a..60e76aa8b53e 100644
--- a/arch/sh/lib/div64-generic.c
+++ b/arch/sh/lib/div64-generic.c
@@ -3,6 +3,7 @@
  */
 
 #include <linux/types.h>
+#include <asm/div64.h>
 
 extern uint64_t __xdiv64_32(u64 n, u32 d);
 
diff --git a/arch/sh/lib/io.c b/arch/sh/lib/io.c
index 4f54ec43516f..88dfe6e396bc 100644
--- a/arch/sh/lib/io.c
+++ b/arch/sh/lib/io.c
@@ -14,12 +14,12 @@
 #include <linux/module.h>
 #include <linux/io.h>
 
-void __raw_readsl(unsigned long addr, void *datap, int len)
+void __raw_readsl(const void __iomem *addr, void *datap, int len)
 {
         u32 *data;
 
         for (data = datap; (len != 0) && (((u32)data & 0x1f) != 0); len--)
-                *data++ = ctrl_inl(addr);
+                *data++ = __raw_readl(addr);
 
         if (likely(len >= (0x20 >> 2))) {
                 int tmp2, tmp3, tmp4, tmp5, tmp6;
@@ -59,11 +59,11 @@ void __raw_readsl(unsigned long addr, void *datap, int len)
         }
 
         for (; len != 0; len--)
-                *data++ = ctrl_inl(addr);
+                *data++ = __raw_readl(addr);
 }
 EXPORT_SYMBOL(__raw_readsl);
 
-void __raw_writesl(unsigned long addr, const void *data, int len)
+void __raw_writesl(void __iomem *addr, const void *data, int len)
 {
         if (likely(len != 0)) {
                 int tmp1;
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 8a03926ea84f..555ec9714b9e 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -132,7 +132,11 @@ config ARCH_SELECT_MEMORY_MODEL
 
 config ARCH_ENABLE_MEMORY_HOTPLUG
         def_bool y
-        depends on SPARSEMEM
+        depends on SPARSEMEM && MMU
+
+config ARCH_ENABLE_MEMORY_HOTREMOVE
+        def_bool y
+        depends on SPARSEMEM && MMU
 
 config ARCH_MEMORY_PROBE
         def_bool y
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 0e189ccd4a77..5ba067b26591 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -130,12 +130,18 @@ static int __init cache_debugfs_init(void)
         dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root,
                                             (unsigned int *)CACHE_TYPE_DCACHE,
                                             &cache_debugfs_fops);
+        if (!dcache_dentry)
+                return -ENOMEM;
         if (IS_ERR(dcache_dentry))
                 return PTR_ERR(dcache_dentry);
 
         icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root,
                                             (unsigned int *)CACHE_TYPE_ICACHE,
                                             &cache_debugfs_fops);
+        if (!icache_dentry) {
+                debugfs_remove(dcache_dentry);
+                return -ENOMEM;
+        }
         if (IS_ERR(icache_dentry)) {
                 debugfs_remove(dcache_dentry);
                 return PTR_ERR(icache_dentry);
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 1fdc8d90254a..5cfe08dbb59e 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -261,7 +261,7 @@ void flush_dcache_page(struct page *page)
 }
 
 /* TODO: Selective icache invalidation through IC address array.. */
-static inline void __uses_jump_to_uncached flush_icache_all(void)
+static void __uses_jump_to_uncached flush_icache_all(void)
 {
         unsigned long flags, ccr;
 
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index 64b8f7f96f9a..9f8ea3ada4db 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -16,14 +16,6 @@
 #include <asm/addrspace.h>
 #include <asm/io.h>
 
-struct dma_coherent_mem {
-        void            *virt_base;
-        u32             device_base;
-        int             size;
-        int             flags;
-        unsigned long   *bitmap;
-};
-
 void *dma_alloc_coherent(struct device *dev, size_t size,
                            dma_addr_t *dma_handle, gfp_t gfp)
 {
@@ -44,7 +36,7 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
          */
         dma_cache_sync(dev, ret, size, DMA_BIDIRECTIONAL);
 
-        ret_nocache = ioremap_nocache(virt_to_phys(ret), size);
+        ret_nocache = (void __force *)ioremap_nocache(virt_to_phys(ret), size);
         if (!ret_nocache) {
                 free_pages((unsigned long)ret, order);
                 return NULL;
@@ -58,12 +50,10 @@ EXPORT_SYMBOL(dma_alloc_coherent);
 void dma_free_coherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t dma_handle)
 {
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
 
         if (!dma_release_from_coherent(dev, order, vaddr)) {
                 WARN_ON(irqs_disabled());       /* for portability */
-                BUG_ON(mem && mem->flags & DMA_MEMORY_EXCLUSIVE);
                 free_pages((unsigned long)phys_to_virt(dma_handle), order);
                 iounmap(vaddr);
         }
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 0c776fdfbdda..898d477e47c1 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -2,7 +2,7 @@
  * Page fault handler for SH with an MMU.
  *
  *  Copyright (C) 1999  Niibe Yutaka
- *  Copyright (C) 2003 - 2007  Paul Mundt
+ *  Copyright (C) 2003 - 2008  Paul Mundt
  *
  *  Based on linux/arch/i386/mm/fault.c:
  *   Copyright (C) 1995  Linus Torvalds
@@ -15,6 +15,7 @@
 #include <linux/mm.h>
 #include <linux/hardirq.h>
 #include <linux/kprobes.h>
+#include <linux/marker.h>
 #include <asm/io_trapped.h>
 #include <asm/system.h>
 #include <asm/mmu_context.h>
@@ -37,10 +38,10 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
         int fault;
         siginfo_t info;
 
-#ifdef CONFIG_SH_KGDB
-        if (kgdb_nofault && kgdb_bus_err_hook)
-                kgdb_bus_err_hook();
-#endif
+        /*
+         * We don't bother with any notifier callbacks here, as they are
+         * all handled through the __do_page_fault() fast-path.
+         */
 
         tsk = current;
         si_code = SEGV_MAPERR;
@@ -61,7 +62,6 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
                 pgd = get_TTB() + offset;
                 pgd_k = swapper_pg_dir + offset;
 
-                /* This will never happen with the folded page table. */
                 if (!pgd_present(*pgd)) {
                         if (!pgd_present(*pgd_k))
                                 goto bad_area_nosemaphore;
@@ -71,9 +71,13 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
 
                 pud = pud_offset(pgd, address);
                 pud_k = pud_offset(pgd_k, address);
-                if (pud_present(*pud) || !pud_present(*pud_k))
-                        goto bad_area_nosemaphore;
-                set_pud(pud, *pud_k);
+
+                if (!pud_present(*pud)) {
+                        if (!pud_present(*pud_k))
+                                goto bad_area_nosemaphore;
+                        set_pud(pud, *pud_k);
+                        return;
+                }
 
                 pmd = pmd_offset(pud, address);
                 pmd_k = pmd_offset(pud_k, address);
@@ -242,6 +246,25 @@ do_sigbus:
                 goto no_context;
 }
 
+static inline int notify_page_fault(struct pt_regs *regs, int trap)
+{
+        int ret = 0;
+
+        trace_mark(kernel_arch_trap_entry, "trap_id %d ip #p%ld",
+                   trap >> 5, instruction_pointer(regs));
+
+#ifdef CONFIG_KPROBES
+        if (!user_mode(regs)) {
+                preempt_disable();
+                if (kprobe_running() && kprobe_fault_handler(regs, trap))
+                        ret = 1;
+                preempt_enable();
+        }
+#endif
+
+        return ret;
+}
+
 #ifdef CONFIG_SH_STORE_QUEUES
 /*
  * This is a special case for the SH-4 store queues, as pages for this
@@ -265,12 +288,18 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
         pmd_t *pmd;
         pte_t *pte;
         pte_t entry;
+        int ret = 0;
+
+        if (notify_page_fault(regs, lookup_exception_vector()))
+                goto out;
 
 #ifdef CONFIG_SH_KGDB
         if (kgdb_nofault && kgdb_bus_err_hook)
                 kgdb_bus_err_hook();
 #endif
 
+        ret = 1;
+
         /*
          * We don't take page faults for P1, P2, and parts of P4, these
          * are always mapped, whether it be due to legacy behaviour in
@@ -280,24 +309,23 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
                 pgd = pgd_offset_k(address);
         } else {
                 if (unlikely(address >= TASK_SIZE || !current->mm))
-                        return 1;
+                        goto out;
 
                 pgd = pgd_offset(current->mm, address);
         }
 
         pud = pud_offset(pgd, address);
         if (pud_none_or_clear_bad(pud))
-                return 1;
+                goto out;
         pmd = pmd_offset(pud, address);
         if (pmd_none_or_clear_bad(pmd))
-                return 1;
-
+                goto out;
         pte = pte_offset_kernel(pmd, address);
         entry = *pte;
         if (unlikely(pte_none(entry) || pte_not_present(entry)))
-                return 1;
+                goto out;
         if (unlikely(writeaccess && !pte_write(entry)))
-                return 1;
+                goto out;
 
         if (writeaccess)
                 entry = pte_mkdirty(entry);
@@ -314,5 +342,8 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
         set_pte(pte, entry);
         update_mmu_cache(NULL, address, entry);
 
-        return 0;
+        ret = 0;
+out:
+        trace_mark(kernel_arch_trap_exit, MARK_NOARGS);
+        return ret;
 }
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index b75a7acd62fb..2a53943924b2 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -23,7 +23,19 @@
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 pgd_t swapper_pg_dir[PTRS_PER_PGD];
-unsigned long cached_to_uncached = 0;
+
+#ifdef CONFIG_SUPERH32
+/*
+ * Handle trivial transitions between cached and uncached
+ * segments, making use of the 1:1 mapping relationship in
+ * 512MB lowmem.
+ *
+ * This is the offset of the uncached section from its cached alias.
+ * Default value only valid in 29 bit mode, in 32bit mode will be
+ * overridden in pmb_init.
+ */
+unsigned long cached_to_uncached = P2SEG - P1SEG;
+#endif
 
 #ifdef CONFIG_MMU
 static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
@@ -58,9 +70,7 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
         }
 
         set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot));
-
-        if (cached_to_uncached)
-                flush_tlb_one(get_asid(), addr);
+        flush_tlb_one(get_asid(), addr);
 }
 
 /*
@@ -113,7 +123,6 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
                 if (!pmd_present(*pmd)) {
                         pte_t *pte_table;
                         pte_table = (pte_t *)alloc_bootmem_low_pages(PAGE_SIZE);
-                        memset(pte_table, 0, PAGE_SIZE);
                         pmd_populate_kernel(&init_mm, pmd, pte_table);
                 }
 
@@ -165,15 +174,6 @@ void __init paging_init(void)
 #ifdef CONFIG_SUPERH32
         /* Set up the uncached fixmap */
         set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start));
-
-#ifdef CONFIG_29BIT
-        /*
-         * Handle trivial transitions between cached and uncached
-         * segments, making use of the 1:1 mapping relationship in
-         * 512MB lowmem.
-         */
-        cached_to_uncached = P2SEG - P1SEG;
-#endif
 #endif
 }
 
@@ -265,6 +265,35 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 }
 #endif
 
+#if THREAD_SHIFT < PAGE_SHIFT
+static struct kmem_cache *thread_info_cache;
+
+struct thread_info *alloc_thread_info(struct task_struct *tsk)
+{
+        struct thread_info *ti;
+
+        ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL);
+        if (unlikely(ti == NULL))
+                return NULL;
+#ifdef CONFIG_DEBUG_STACK_USAGE
+        memset(ti, 0, THREAD_SIZE);
+#endif
+        return ti;
+}
+
+void free_thread_info(struct thread_info *ti)
+{
+        kmem_cache_free(thread_info_cache, ti);
+}
+
+void thread_info_cache_init(void)
+{
+        thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
+                                              THREAD_SIZE, 0, NULL);
+        BUG_ON(thread_info_cache == NULL);
+}
+#endif /* THREAD_SHIFT < PAGE_SHIFT */
+
 #ifdef CONFIG_MEMORY_HOTPLUG
 int arch_add_memory(int nid, u64 start, u64 size)
 {
@@ -292,4 +321,21 @@ int memory_add_physaddr_to_nid(u64 addr)
 }
 EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
 #endif
+
+#ifdef CONFIG_MEMORY_HOTREMOVE
+int remove_memory(u64 start, u64 size)
+{
+        unsigned long start_pfn = start >> PAGE_SHIFT;
+        unsigned long end_pfn = start_pfn + (size >> PAGE_SHIFT);
+        int ret;
+
+        ret = offline_pages(start_pfn, end_pfn, 120 * HZ);
+        if (unlikely(ret))
+                printk("%s: Failed, offline_pages() == %d\n", __func__, ret);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(remove_memory);
 #endif
+
+#endif /* CONFIG_MEMORY_HOTPLUG */
diff --git a/arch/sh/mm/pg-nommu.c b/arch/sh/mm/pg-nommu.c
index 677dd57f0877..91ed4e695ff7 100644
--- a/arch/sh/mm/pg-nommu.c
+++ b/arch/sh/mm/pg-nommu.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <asm/page.h>
+#include <asm/uaccess.h>
 
 void copy_page(void *to, void *from)
 {
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index cef727669c87..84241676265e 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -394,6 +394,8 @@ static int __init pmb_debugfs_init(void)
 
         dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
                                      sh_debugfs_root, NULL, &pmb_debugfs_fops);
+        if (!dentry)
+                return -ENOMEM;
         if (IS_ERR(dentry))
                 return PTR_ERR(dentry);
 
diff --git a/arch/sh/mm/tlb-nommu.c b/arch/sh/mm/tlb-nommu.c
index 15111bc7ddd6..71c742b5aee3 100644
--- a/arch/sh/mm/tlb-nommu.c
+++ b/arch/sh/mm/tlb-nommu.c
@@ -10,6 +10,7 @@
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <asm/pgtable.h>
+#include <asm/tlbflush.h>
 
 /*
  * Nothing too terribly exciting here ..
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 0a11cc08f0a5..d4fb11f7e2ee 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -30,6 +30,7 @@ HP6XX			SH_HP6XX
 DREAMCAST               SH_DREAMCAST
 SNAPGEAR                SH_SECUREEDGE5410
 EDOSK7705               SH_EDOSK7705
+EDOSK7760               SH_EDOSK7760
 SH4202_MICRODEV         SH_SH4202_MICRODEV
 SH03                    SH_SH03
 LANDISK                 SH_LANDISK