diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2010-02-04 06:09:07 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-04-26 10:47:57 -0400 |
commit | f8b1a072d4f260c203eb500beb70a1e1c2ff8689 (patch) | |
tree | ccce3839d65923b64b64e5675f11071465df8ea7 /arch | |
parent | ad98454d28b70fafe526fbab77e67560bacde482 (diff) |
x86, cacheinfo: Remove NUMA dependency, fix for AMD Fam10h rev D1
commit f619b3d8427eb57f0134dab75b0d217325c72411 upstream.
The show/store_cache_disable routines depend unnecessarily on NUMA's
cpu_to_node and the disabling of cache indices broke when !CONFIG_NUMA.
Remove that dependency by using a helper which is always correct.
While at it, enable L3 Cache Index disable on rev D1 Istanbuls which
sport the feature too.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20100218184339.GG20473@aftab>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 589b705e80ed..be5f5c28ddfb 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |||
@@ -327,7 +327,7 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf) | |||
327 | 327 | ||
328 | /* see errata #382 and #388 */ | 328 | /* see errata #382 and #388 */ |
329 | if ((boot_cpu_data.x86 == 0x10) && | 329 | if ((boot_cpu_data.x86 == 0x10) && |
330 | ((boot_cpu_data.x86_model < 0x9) || | 330 | ((boot_cpu_data.x86_model < 0x8) || |
331 | (boot_cpu_data.x86_mask < 0x1))) | 331 | (boot_cpu_data.x86_mask < 0x1))) |
332 | return; | 332 | return; |
333 | 333 | ||
@@ -744,7 +744,7 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf, | |||
744 | unsigned int index) | 744 | unsigned int index) |
745 | { | 745 | { |
746 | int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map)); | 746 | int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map)); |
747 | int node = cpu_to_node(cpu); | 747 | int node = amd_get_nb_id(cpu); |
748 | struct pci_dev *dev = node_to_k8_nb_misc(node); | 748 | struct pci_dev *dev = node_to_k8_nb_misc(node); |
749 | unsigned int reg = 0; | 749 | unsigned int reg = 0; |
750 | 750 | ||
@@ -771,7 +771,7 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, | |||
771 | const char *buf, size_t count, unsigned int index) | 771 | const char *buf, size_t count, unsigned int index) |
772 | { | 772 | { |
773 | int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map)); | 773 | int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map)); |
774 | int node = cpu_to_node(cpu); | 774 | int node = amd_get_nb_id(cpu); |
775 | struct pci_dev *dev = node_to_k8_nb_misc(node); | 775 | struct pci_dev *dev = node_to_k8_nb_misc(node); |
776 | unsigned long val = 0; | 776 | unsigned long val = 0; |
777 | 777 | ||