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authorMike Frysinger <vapier@gentoo.org>2009-10-14 23:45:47 -0400
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:14:40 -0500
commitcd32cc73625641c068393978e7bb337d29c0cd29 (patch)
tree2919e991260ccb6603b9ac713cd0dff5f83d8854 /arch
parentb1fa2e8f626e997c2c4f991f10ed00b6ee080b99 (diff)
Blackfin: punt OTP MMRs
People should not be accessing OTP MMRs directly. They should instead go through the Blackfin ROM helper functions. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h22
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h40
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h22
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h40
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h30
6 files changed, 0 insertions, 176 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index c1b71bb2770a..e548e9d1d6fa 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -1046,17 +1046,6 @@
1046#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 1046#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1047#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 1047#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1048 1048
1049/* OTP/FUSE Registers */
1050
1051#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1052#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1053#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1054#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1055#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1056#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1057#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1058#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1059
1060/* Security Registers */ 1049/* Security Registers */
1061 1050
1062#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 1051#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -1066,17 +1055,6 @@
1066#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) 1055#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1067#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) 1056#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1068 1057
1069/* OTP Read/Write Data Buffer Registers */
1070
1071#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1072#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1073#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1074#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1075#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1076#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1077#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1078#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1079
1080/* These need to be last due to the cdef/linux inter-dependencies */ 1058/* These need to be last due to the cdef/linux inter-dependencies */
1081#include <asm/irq.h> 1059#include <asm/irq.h>
1082 1060
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 83e8c34547b3..78253e838f3d 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -1770,46 +1770,6 @@
1770#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ 1770#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1771#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ 1771#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1772 1772
1773/* Bit masks for OTP_CONTROL */
1774
1775#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1776#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1777#define nFIEN 0x0
1778#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1779#define nFTESTDEC 0x0
1780#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1781#define nFWRTEST 0x0
1782#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1783#define nFRDEN 0x0
1784#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1785#define nFWREN 0x0
1786
1787/* Bit masks for OTP_BEN */
1788
1789#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1790
1791/* Bit masks for OTP_STATUS */
1792
1793#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1794#define nFCOMP 0x0
1795#define FERROR 0x2 /* OTP/Fuse Access Error */
1796#define nFERROR 0x0
1797#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1798#define nMMRGLOAD 0x0
1799#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1800#define nMMRGLOCK 0x0
1801#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1802#define nFPGMEN 0x0
1803
1804/* Bit masks for OTP_TIMING */
1805
1806#define USECDIV 0xff /* Micro Second Divider */
1807#define READACC 0x7f00 /* Read Access Time */
1808#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1809#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1810#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1811#define PGMTIME 0xff000000 /* Program Time */
1812
1813/* Bit masks for SECURE_SYSSWT */ 1773/* Bit masks for SECURE_SYSSWT */
1814 1774
1815#define EMUDABL 0x1 /* Emulation Disable. */ 1775#define EMUDABL 0x1 /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index b6b99bb04739..12f2ad45314e 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -1063,17 +1063,6 @@
1063#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 1063#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1064#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 1064#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1065 1065
1066/* OTP/FUSE Registers */
1067
1068#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1069#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1070#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1071#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1072#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1073#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1074#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1075#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1076
1077/* Security Registers */ 1066/* Security Registers */
1078 1067
1079#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 1068#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -1083,17 +1072,6 @@
1083#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) 1072#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1084#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) 1073#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1085 1074
1086/* OTP Read/Write Data Buffer Registers */
1087
1088#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1089#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1090#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1091#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1092#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1093#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1094#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1095#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1096
1097/* NFC Registers */ 1075/* NFC Registers */
1098 1076
1099#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) 1077#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 3dda2b8e8512..6e6a8df02c3b 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -1783,46 +1783,6 @@
1783#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ 1783#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1784#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ 1784#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1785 1785
1786/* Bit masks for OTP_CONTROL */
1787
1788#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1789#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1790#define nFIEN 0x0
1791#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1792#define nFTESTDEC 0x0
1793#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1794#define nFWRTEST 0x0
1795#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1796#define nFRDEN 0x0
1797#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1798#define nFWREN 0x0
1799
1800/* Bit masks for OTP_BEN */
1801
1802#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1803
1804/* Bit masks for OTP_STATUS */
1805
1806#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1807#define nFCOMP 0x0
1808#define FERROR 0x2 /* OTP/Fuse Access Error */
1809#define nFERROR 0x0
1810#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1811#define nMMRGLOAD 0x0
1812#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1813#define nMMRGLOCK 0x0
1814#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1815#define nFPGMEN 0x0
1816
1817/* Bit masks for OTP_TIMING */
1818
1819#define USECDIV 0xff /* Micro Second Divider */
1820#define READACC 0x7f00 /* Read Access Time */
1821#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1822#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1823#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1824#define PGMTIME 0xff000000 /* Program Time */
1825
1826/* Bit masks for SECURE_SYSSWT */ 1786/* Bit masks for SECURE_SYSSWT */
1827 1787
1828#define EMUDABL 0x1 /* Emulation Disable. */ 1788#define EMUDABL 0x1 /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index a2e9d9849eba..32f71e6a7c15 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2615,17 +2615,6 @@
2615#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 2615#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2616#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 2616#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2617 2617
2618/* OTP/FUSE Registers */
2619
2620#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2621#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2622#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2623#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2624#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2625#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2626#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2627#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2628
2629/* Security Registers */ 2618/* Security Registers */
2630 2619
2631#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 2620#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -2640,17 +2629,6 @@
2640#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) 2629#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2641#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) 2630#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2642 2631
2643/* OTP Read/Write Data Buffer Registers */
2644
2645#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2646#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2647#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2648#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2649#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2650#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2651#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2652#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2653
2654/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ 2632/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2655 2633
2656/* legacy definitions */ 2634/* legacy definitions */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 3ce5ce6c4971..f07c0f76e6d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2143,36 +2143,6 @@
2143 2143
2144#define DPRESCALE 0xf /* Load Counter Register */ 2144#define DPRESCALE 0xf /* Load Counter Register */
2145 2145
2146/* Bit masks for OTP_CONTROL */
2147
2148#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2149#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2150#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2151#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2152#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2153#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2154
2155/* Bit masks for OTP_BEN */
2156
2157#define FBEN 0xffff /* OTP/Fuse Byte Enable */
2158
2159/* Bit masks for OTP_STATUS */
2160
2161#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2162#define FERROR 0x2 /* OTP/Fuse Access Error */
2163#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2164#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2165#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2166
2167/* Bit masks for OTP_TIMING */
2168
2169#define USECDIV 0xff /* Micro Second Divider */
2170#define READACC 0x7f00 /* Read Access Time */
2171#define CPUMPRL 0x38000 /* Charge Pump Release Time */
2172#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
2173#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
2174#define PGMTIME 0xff000000 /* Program Time */
2175
2176/* Bit masks for SECURE_SYSSWT */ 2146/* Bit masks for SECURE_SYSSWT */
2177 2147
2178#define EMUDABL 0x1 /* Emulation Disable. */ 2148#define EMUDABL 0x1 /* Emulation Disable. */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 12:34:51 -0500