[ARM] cachetype: move definitions to separate header

Rather than pollute asm/cacheflush.h with the cache type definitions,
move them to asm/cachetype.h, and include this new header where
necessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

7 files changed, 101 insertions, 90 deletions

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9073d9c6567e..de6c59f814a1 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -444,94 +444,4 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
         dmac_inv_range(start, start + size);
 }
 
-#define __cacheid_present(val)                  (val != read_cpuid(CPUID_ID))
-#define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
-
-#define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
-#define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
-
-#define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
-#define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
-#define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
-#define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
-#define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
-
-#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
-/*
- * VIVT caches only
- */
-#define cache_is_vivt()                 1
-#define cache_is_vipt()                 0
-#define cache_is_vipt_nonaliasing()     0
-#define cache_is_vipt_aliasing()        0
-#define icache_is_vivt_asid_tagged()    0
-
-#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
-/*
- * VIPT caches only
- */
-#define cache_is_vivt()                 0
-#define cache_is_vipt()                 1
-#define cache_is_vipt_nonaliasing()                                     \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vipt_nonaliasing(__val);                      \
-        })
-
-#define cache_is_vipt_aliasing()                                        \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vipt_aliasing(__val);                         \
-        })
-
-#define icache_is_vivt_asid_tagged()                                    \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vivt_asid_tagged_instr(__val);                \
-        })
-
-#else
-/*
- * VIVT or VIPT caches.  Note that this is unreliable since ARM926
- * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
- * There's no way to tell from the CacheType register what type (!)
- * the cache is.
- */
-#define cache_is_vivt()                                                 \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
-        })
-                
-#define cache_is_vipt()                                                 \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) && __cacheid_vipt(__val);      \
-        })
-
-#define cache_is_vipt_nonaliasing()                                     \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vipt_nonaliasing(__val);                     \
-        })
-
-#define cache_is_vipt_aliasing()                                        \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vipt_aliasing(__val);                        \
-        })
-
-#define icache_is_vivt_asid_tagged()                                    \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vivt_asid_tagged_instr(__val);               \
-        })
-
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
new file mode 100644
index 000000000000..b52386bfd505
--- /dev/null
+++ b/arch/arm/include/asm/cachetype.h
@@ -0,0 +1,96 @@
+#ifndef __ASM_ARM_CACHETYPE_H
+#define __ASM_ARM_CACHETYPE_H
+
+#include <asm/cputype.h>
+
+#define __cacheid_present(val)                  (val != read_cpuid_id())
+#define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
+
+#define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
+#define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+
+#define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
+#define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
+#define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
+#define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
+#define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
+
+#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
+/*
+ * VIVT caches only
+ */
+#define cache_is_vivt()                 1
+#define cache_is_vipt()                 0
+#define cache_is_vipt_nonaliasing()     0
+#define cache_is_vipt_aliasing()        0
+#define icache_is_vivt_asid_tagged()    0
+
+#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
+/*
+ * VIPT caches only
+ */
+#define cache_is_vivt()                 0
+#define cache_is_vipt()                 1
+#define cache_is_vipt_nonaliasing()                                     \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_vipt_nonaliasing(__val);                      \
+        })
+
+#define cache_is_vipt_aliasing()                                        \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_vipt_aliasing(__val);                         \
+        })
+
+#define icache_is_vivt_asid_tagged()                                    \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_vivt_asid_tagged_instr(__val);                \
+        })
+
+#else
+/*
+ * VIVT or VIPT caches.  Note that this is unreliable since ARM926
+ * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
+ * There's no way to tell from the CacheType register what type (!)
+ * the cache is.
+ */
+#define cache_is_vivt()                                                 \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
+        })
+
+#define cache_is_vipt()                                                 \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_present(__val) && __cacheid_vipt(__val);      \
+        })
+
+#define cache_is_vipt_nonaliasing()                                     \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vipt_nonaliasing(__val);                     \
+        })
+
+#define cache_is_vipt_aliasing()                                        \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vipt_aliasing(__val);                        \
+        })
+
+#define icache_is_vivt_asid_tagged()                                    \
+        ({                                                              \
+                unsigned int __val = read_cpuid_cachetype();            \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vivt_asid_tagged_instr(__val);               \
+        })
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a301e446007f..0559f37c2a27 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -15,6 +15,7 @@
 
 #include <linux/compiler.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/proc-fns.h>
 #include <asm-generic/mm_hooks.h>
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index fb04703f2a8c..e90422d374af 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -32,6 +32,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/tlbflush.h>
 
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 3adb79257f43..0e21c0767580 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 
 #include "mm.h"
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index a8ec97b4752e..dbdb7b72f2c1 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -18,6 +18,7 @@
 #include <linux/pagemap.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 029ee65fda2b..0fa9bf388f0b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -12,6 +12,7 @@
 #include <linux/pagemap.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>