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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-10 00:01:11 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-10 00:01:11 -0400
commit0fc2f137226eff4c9dd90864dda5c237474c3ec5 (patch)
tree50ec67f1f9d144a3ceb5ccff45a37bc5005f6c3d /arch
parentdcded10f6dce10411b16134ce9cc87bfdf75c13f (diff)
parentaab2393e2ec52c74b419af7c26a12e21584e483b (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits) Blackfin: gpio: add a debounce stub Blackfin: update defconfigs Blackfin: remove CONFIG_MEM_GENERIC_BOARD Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing Blackfin: unify rotary encoder bitmasks Blackfin: unify SDH/RSI bitmasks Blackfin: BF54x: tweak DMAC MMR naming to match other ports Blackfin: TWI: clean up the MMR names Blackfin: add EVT_OVERRIDE/IPRIO core MMR helpers Blackfin: add support for dynamic ftrace Blackfin: add support for LZO compressed kernels Blackfin: portmux: fix peripheral map overflow when requesting pins Blackfin: document SPI CS limitations with CPHA=0 Blackfin: remove useless and outdated documentation Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options Blackfin: gpio/portmux: clean up whitespace corruption Blackfin: make sure mmiowb inserts a write barrier with SSYNC Blackfin: fix DMA/cache bug when resuming from suspend to RAM Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin) Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS ...
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/Kconfig20
-rw-r--r--arch/blackfin/Makefile3
-rw-r--r--arch/blackfin/boot/Makefile11
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig163
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig129
-rw-r--r--arch/blackfin/configs/BF527-EZKIT-V2_defconfig149
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig139
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig93
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig131
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig141
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig121
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig156
-rw-r--r--arch/blackfin/configs/BF561-ACVILON_defconfig1
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig85
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig1
-rw-r--r--arch/blackfin/configs/CM-BF533_defconfig1
-rw-r--r--arch/blackfin/configs/CM-BF537E_defconfig1
-rw-r--r--arch/blackfin/configs/CM-BF537U_defconfig1
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig1
-rw-r--r--arch/blackfin/configs/CM-BF561_defconfig1
-rw-r--r--arch/blackfin/configs/PNAV-10_defconfig123
-rw-r--r--arch/blackfin/configs/TCM-BF518_defconfig1
-rw-r--r--arch/blackfin/configs/TCM-BF537_defconfig1
-rw-r--r--arch/blackfin/include/asm/bfin_rotary.h74
-rw-r--r--arch/blackfin/include/asm/bfin_sdh.h119
-rw-r--r--arch/blackfin/include/asm/bitops.h2
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h8
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h18
-rw-r--r--arch/blackfin/include/asm/dma.h1
-rw-r--r--arch/blackfin/include/asm/elf.h1
-rw-r--r--arch/blackfin/include/asm/ftrace.h16
-rw-r--r--arch/blackfin/include/asm/gpio.h111
-rw-r--r--arch/blackfin/include/asm/io.h8
-rw-r--r--arch/blackfin/include/asm/mem_init.h18
-rw-r--r--arch/blackfin/include/asm/portmux.h10
-rw-r--r--arch/blackfin/kernel/Makefile1
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c19
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c111
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c4
-rw-r--r--arch/blackfin/kernel/ftrace-entry.S85
-rw-r--r--arch/blackfin/kernel/ftrace.c86
-rw-r--r--arch/blackfin/kernel/setup.c7
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S7
-rw-r--r--arch/blackfin/mach-bf518/Kconfig61
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h21
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bf518.h105
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h135
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h144
-rw-r--r--arch/blackfin/mach-bf518/include/mach/gpio.h83
-rw-r--r--arch/blackfin/mach-bf518/include/mach/portmux.h7
-rw-r--r--arch/blackfin/mach-bf527/Kconfig66
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h22
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bf527.h120
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h225
-rw-r--r--arch/blackfin/mach-bf527/include/mach/gpio.h96
-rw-r--r--arch/blackfin/mach-bf527/include/mach/portmux.h3
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h10
-rw-r--r--arch/blackfin/mach-bf533/include/mach/gpio.h32
-rw-r--r--arch/blackfin/mach-bf533/include/mach/portmux.h3
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h11
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h36
-rw-r--r--arch/blackfin/mach-bf537/include/mach/gpio.h96
-rw-r--r--arch/blackfin/mach-bf537/include/mach/portmux.h7
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h16
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h64
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h14
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h108
-rw-r--r--arch/blackfin/mach-bf538/include/mach/portmux.h1
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF542.h130
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h6
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h136
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h152
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/portmux.h3
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h13
-rw-r--r--arch/blackfin/mach-bf561/include/mach/gpio.h96
-rw-r--r--arch/blackfin/mach-bf561/include/mach/portmux.h3
-rw-r--r--arch/blackfin/mach-common/arch_checks.c16
-rw-r--r--arch/blackfin/mach-common/cache.S15
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S24
-rw-r--r--arch/blackfin/mach-common/pm.c17
83 files changed, 2459 insertions, 1859 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c88fd3584122..5a3152b75cdb 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -25,6 +25,8 @@ config BLACKFIN
25 def_bool y 25 def_bool y
26 select HAVE_ARCH_KGDB 26 select HAVE_ARCH_KGDB
27 select HAVE_ARCH_TRACEHOOK 27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_DYNAMIC_FTRACE
29 select HAVE_FTRACE_MCOUNT_RECORD
28 select HAVE_FUNCTION_GRAPH_TRACER 30 select HAVE_FUNCTION_GRAPH_TRACER
29 select HAVE_FUNCTION_TRACER 31 select HAVE_FUNCTION_TRACER
30 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 32 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
@@ -32,6 +34,7 @@ config BLACKFIN
32 select HAVE_KERNEL_GZIP if RAMKERNEL 34 select HAVE_KERNEL_GZIP if RAMKERNEL
33 select HAVE_KERNEL_BZIP2 if RAMKERNEL 35 select HAVE_KERNEL_BZIP2 if RAMKERNEL
34 select HAVE_KERNEL_LZMA if RAMKERNEL 36 select HAVE_KERNEL_LZMA if RAMKERNEL
37 select HAVE_KERNEL_LZO if RAMKERNEL
35 select HAVE_OPROFILE 38 select HAVE_OPROFILE
36 select ARCH_WANT_OPTIONAL_GPIOLIB 39 select ARCH_WANT_OPTIONAL_GPIOLIB
37 40
@@ -328,11 +331,6 @@ config BF53x
328 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 331 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
329 default y 332 default y
330 333
331config MEM_GENERIC_BOARD
332 bool
333 depends on GENERIC_BOARD
334 default y
335
336config MEM_MT48LC64M4A2FB_7E 334config MEM_MT48LC64M4A2FB_7E
337 bool 335 bool
338 depends on (BFIN533_STAMP) 336 depends on (BFIN533_STAMP)
@@ -850,6 +848,18 @@ config CPLB_SWITCH_TAB_L1
850 If enabled, the CPLB Switch Tables are linked 848 If enabled, the CPLB Switch Tables are linked
851 into L1 data memory. (less latency) 849 into L1 data memory. (less latency)
852 850
851config CACHE_FLUSH_L1
852 bool "Locate cache flush funcs in L1 Inst Memory"
853 default y
854 help
855 If enabled, the Blackfin cache flushing functions are linked
856 into L1 instruction memory.
857
858 Note that this might be required to address anomalies, but
859 these functions are pretty small, so it shouldn't be too bad.
860 If you are using a processor affected by an anomaly, the build
861 system will double check for you and prevent it.
862
853config APP_STACK_L1 863config APP_STACK_L1
854 bool "Support locating application stack in L1 Scratch Memory" 864 bool "Support locating application stack in L1 Scratch Memory"
855 default y 865 default y
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 9d5ffaf5492a..3e65b0ffe084 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -140,7 +140,7 @@ archclean:
140 140
141INSTALL_PATH ?= /tftpboot 141INSTALL_PATH ?= /tftpboot
142boot := arch/$(ARCH)/boot 142boot := arch/$(ARCH)/boot
143BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.xip 143BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
144PHONY += $(BOOT_TARGETS) install 144PHONY += $(BOOT_TARGETS) install
145KBUILD_IMAGE := $(boot)/vmImage 145KBUILD_IMAGE := $(boot)/vmImage
146 146
@@ -158,6 +158,7 @@ define archhelp
158 echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)' 158 echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
159 echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)' 159 echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
160 echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)' 160 echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
161 echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)'
161 echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)' 162 echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)'
162 echo ' install - Install kernel using' 163 echo ' install - Install kernel using'
163 echo ' (your) ~/bin/$(INSTALLKERNEL) or' 164 echo ' (your) ~/bin/$(INSTALLKERNEL) or'
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index d1b3d6051fdf..13d2dbd658e3 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -8,8 +8,8 @@
8 8
9MKIMAGE := $(srctree)/scripts/mkuboot.sh 9MKIMAGE := $(srctree)/scripts/mkuboot.sh
10 10
11targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.xip 11targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
12extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xip 12extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
13 13
14UIMAGE_OPTS-y := 14UIMAGE_OPTS-y :=
15UIMAGE_OPTS-$(CONFIG_RAMKERNEL) += -a $(CONFIG_BOOT_LOAD) 15UIMAGE_OPTS-$(CONFIG_RAMKERNEL) += -a $(CONFIG_BOOT_LOAD)
@@ -33,6 +33,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
33$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE 33$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
34 $(call if_changed,lzma) 34 $(call if_changed,lzma)
35 35
36$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
37 $(call if_changed,lzo)
38
36# The mkimage tool wants 64bytes prepended to the image 39# The mkimage tool wants 64bytes prepended to the image
37quiet_cmd_mk_bin_xip = BIN $@ 40quiet_cmd_mk_bin_xip = BIN $@
38 cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@ 41 cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@
@@ -51,6 +54,9 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
51$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma 54$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
52 $(call if_changed,uimage,lzma) 55 $(call if_changed,uimage,lzma)
53 56
57$(obj)/vmImage.lzo: $(obj)/vmlinux.bin.lzo
58 $(call if_changed,uimage,lzo)
59
54$(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip 60$(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip
55 $(call if_changed,uimage,none) 61 $(call if_changed,uimage,none)
56 62
@@ -58,6 +64,7 @@ suffix-y := bin
58suffix-$(CONFIG_KERNEL_GZIP) := gz 64suffix-$(CONFIG_KERNEL_GZIP) := gz
59suffix-$(CONFIG_KERNEL_BZIP2) := bz2 65suffix-$(CONFIG_KERNEL_BZIP2) := bz2
60suffix-$(CONFIG_KERNEL_LZMA) := lzma 66suffix-$(CONFIG_KERNEL_LZMA) := lzma
67suffix-$(CONFIG_KERNEL_LZO) := lzo
61suffix-$(CONFIG_ROMKERNEL) := xip 68suffix-$(CONFIG_ROMKERNEL) := xip
62 69
63$(obj)/vmImage: $(obj)/vmImage.$(suffix-y) 70$(obj)/vmImage: $(obj)/vmImage.$(suffix-y)
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index cf7c9bc94f13..01865033f70d 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -1,7 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34.1
4# Sun Aug 1 22:52:24 2010
4# 5#
6CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 7# CONFIG_MMU is not set
6# CONFIG_FPU is not set 8# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 9CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -34,9 +36,11 @@ CONFIG_LOCALVERSION_AUTO=y
34CONFIG_HAVE_KERNEL_GZIP=y 36CONFIG_HAVE_KERNEL_GZIP=y
35CONFIG_HAVE_KERNEL_BZIP2=y 37CONFIG_HAVE_KERNEL_BZIP2=y
36CONFIG_HAVE_KERNEL_LZMA=y 38CONFIG_HAVE_KERNEL_LZMA=y
39CONFIG_HAVE_KERNEL_LZO=y
37CONFIG_KERNEL_GZIP=y 40CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 41# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 42# CONFIG_KERNEL_LZMA is not set
43# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 44CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 45CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 46# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +53,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 53#
50CONFIG_TREE_RCU=y 54CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 55# CONFIG_TREE_PREEMPT_RCU is not set
56# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 57# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 58CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 59# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +61,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 61CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 62CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 63CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 64# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 65# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 66# CONFIG_NAMESPACES is not set
@@ -66,6 +69,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 69CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 70# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 71# CONFIG_RD_LZMA is not set
72# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 73# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 74CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 75CONFIG_ANON_INODES=y
@@ -98,6 +102,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 102CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 103# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 104CONFIG_HAVE_OPROFILE=y
105CONFIG_HAVE_ARCH_TRACEHOOK=y
101 106
102# 107#
103# GCOV-based kernel profiling 108# GCOV-based kernel profiling
@@ -106,6 +111,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 111# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 112# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 113CONFIG_SLABINFO=y
114CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 115CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 116CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 117# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +128,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 128# IO Schedulers
123# 129#
124CONFIG_IOSCHED_NOOP=y 130CONFIG_IOSCHED_NOOP=y
125# CONFIG_IOSCHED_AS is not set
126# CONFIG_IOSCHED_DEADLINE is not set 131# CONFIG_IOSCHED_DEADLINE is not set
127# CONFIG_IOSCHED_CFQ is not set 132# CONFIG_IOSCHED_CFQ is not set
128# CONFIG_DEFAULT_AS is not set
129# CONFIG_DEFAULT_DEADLINE is not set 133# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 134# CONFIG_DEFAULT_CFQ is not set
131CONFIG_DEFAULT_NOOP=y 135CONFIG_DEFAULT_NOOP=y
132CONFIG_DEFAULT_IOSCHED="noop" 136CONFIG_DEFAULT_IOSCHED="noop"
137# CONFIG_INLINE_SPIN_TRYLOCK is not set
138# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK is not set
140# CONFIG_INLINE_SPIN_LOCK_BH is not set
141# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
142# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
143CONFIG_INLINE_SPIN_UNLOCK=y
144# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
145CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
146# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
147# CONFIG_INLINE_READ_TRYLOCK is not set
148# CONFIG_INLINE_READ_LOCK is not set
149# CONFIG_INLINE_READ_LOCK_BH is not set
150# CONFIG_INLINE_READ_LOCK_IRQ is not set
151# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
152CONFIG_INLINE_READ_UNLOCK=y
153# CONFIG_INLINE_READ_UNLOCK_BH is not set
154CONFIG_INLINE_READ_UNLOCK_IRQ=y
155# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
156# CONFIG_INLINE_WRITE_TRYLOCK is not set
157# CONFIG_INLINE_WRITE_LOCK is not set
158# CONFIG_INLINE_WRITE_LOCK_BH is not set
159# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
160# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
161CONFIG_INLINE_WRITE_UNLOCK=y
162# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
163CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
164# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
165# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 166# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 167CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 168# CONFIG_PREEMPT is not set
@@ -185,6 +218,7 @@ CONFIG_BF_REV_0_0=y
185CONFIG_MEM_MT48LC32M8A2_75=y 218CONFIG_MEM_MT48LC32M8A2_75=y
186CONFIG_BF51x=y 219CONFIG_BF51x=y
187CONFIG_BFIN518F_EZBRD=y 220CONFIG_BFIN518F_EZBRD=y
221# CONFIG_BFIN518F_TCM is not set
188 222
189# 223#
190# BF518 Specific Configuration 224# BF518 Specific Configuration
@@ -201,6 +235,11 @@ CONFIG_BF518_UART1_PORTF=y
201# CONFIG_BF518_UART1_PORTG is not set 235# CONFIG_BF518_UART1_PORTG is not set
202 236
203# 237#
238# Hysteresis/schmitt Trigger Control
239#
240# CONFIG_BFIN_HYSTERESIS_CONTROL is not set
241
242#
204# Interrupt Priority Assignment 243# Interrupt Priority Assignment
205# 244#
206 245
@@ -288,8 +327,16 @@ CONFIG_HZ=250
288# CONFIG_SCHED_HRTICK is not set 327# CONFIG_SCHED_HRTICK is not set
289CONFIG_GENERIC_TIME=y 328CONFIG_GENERIC_TIME=y
290CONFIG_GENERIC_CLOCKEVENTS=y 329CONFIG_GENERIC_CLOCKEVENTS=y
330
331#
332# Clock event device
333#
291# CONFIG_TICKSOURCE_GPTMR0 is not set 334# CONFIG_TICKSOURCE_GPTMR0 is not set
292CONFIG_TICKSOURCE_CORETMR=y 335CONFIG_TICKSOURCE_CORETMR=y
336
337#
338# Clock souce
339#
293# CONFIG_CYCLES_CLOCKSOURCE is not set 340# CONFIG_CYCLES_CLOCKSOURCE is not set
294# CONFIG_GPTMR0_CLOCKSOURCE is not set 341# CONFIG_GPTMR0_CLOCKSOURCE is not set
295# CONFIG_NO_HZ is not set 342# CONFIG_NO_HZ is not set
@@ -320,12 +367,17 @@ CONFIG_ARITHMETIC_OPS_L1=y
320CONFIG_ACCESS_OK_L1=y 367CONFIG_ACCESS_OK_L1=y
321# CONFIG_MEMSET_L1 is not set 368# CONFIG_MEMSET_L1 is not set
322# CONFIG_MEMCPY_L1 is not set 369# CONFIG_MEMCPY_L1 is not set
370CONFIG_STRCMP_L1=y
371CONFIG_STRNCMP_L1=y
372CONFIG_STRCPY_L1=y
373CONFIG_STRNCPY_L1=y
323# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set 374# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
324# CONFIG_IP_CHECKSUM_L1 is not set 375# CONFIG_IP_CHECKSUM_L1 is not set
325CONFIG_CACHELINE_ALIGNED_L1=y 376CONFIG_CACHELINE_ALIGNED_L1=y
326# CONFIG_SYSCALL_TAB_L1 is not set 377# CONFIG_SYSCALL_TAB_L1 is not set
327# CONFIG_CPLB_SWITCH_TAB_L1 is not set 378# CONFIG_CPLB_SWITCH_TAB_L1 is not set
328CONFIG_APP_STACK_L1=y 379CONFIG_CACHE_FLUSH_L1=y
380# CONFIG_EXCEPTION_L1_SCRATCH is not set
329 381
330# 382#
331# Speed Optimizations 383# Speed Optimizations
@@ -425,7 +477,6 @@ CONFIG_NET=y
425# Networking options 477# Networking options
426# 478#
427CONFIG_PACKET=y 479CONFIG_PACKET=y
428# CONFIG_PACKET_MMAP is not set
429CONFIG_UNIX=y 480CONFIG_UNIX=y
430# CONFIG_NET_KEY is not set 481# CONFIG_NET_KEY is not set
431CONFIG_INET=y 482CONFIG_INET=y
@@ -486,6 +537,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
486# CONFIG_HAMRADIO is not set 537# CONFIG_HAMRADIO is not set
487# CONFIG_CAN is not set 538# CONFIG_CAN is not set
488# CONFIG_IRDA is not set 539# CONFIG_IRDA is not set
540# CONFIG_SIR_BFIN_DMA is not set
541# CONFIG_SIR_BFIN_PIO is not set
489# CONFIG_BT is not set 542# CONFIG_BT is not set
490# CONFIG_AF_RXRPC is not set 543# CONFIG_AF_RXRPC is not set
491# CONFIG_WIRELESS is not set 544# CONFIG_WIRELESS is not set
@@ -596,6 +649,10 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
596CONFIG_BLK_DEV=y 649CONFIG_BLK_DEV=y
597# CONFIG_BLK_DEV_COW_COMMON is not set 650# CONFIG_BLK_DEV_COW_COMMON is not set
598# CONFIG_BLK_DEV_LOOP is not set 651# CONFIG_BLK_DEV_LOOP is not set
652
653#
654# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
655#
599# CONFIG_BLK_DEV_NBD is not set 656# CONFIG_BLK_DEV_NBD is not set
600CONFIG_BLK_DEV_RAM=y 657CONFIG_BLK_DEV_RAM=y
601CONFIG_BLK_DEV_RAM_COUNT=16 658CONFIG_BLK_DEV_RAM_COUNT=16
@@ -609,6 +666,9 @@ CONFIG_MISC_DEVICES=y
609# CONFIG_ICS932S401 is not set 666# CONFIG_ICS932S401 is not set
610# CONFIG_ENCLOSURE_SERVICES is not set 667# CONFIG_ENCLOSURE_SERVICES is not set
611# CONFIG_ISL29003 is not set 668# CONFIG_ISL29003 is not set
669# CONFIG_SENSORS_TSL2550 is not set
670# CONFIG_DS1682 is not set
671# CONFIG_TI_DAC7512 is not set
612# CONFIG_C2PORT is not set 672# CONFIG_C2PORT is not set
613 673
614# 674#
@@ -619,12 +679,14 @@ CONFIG_MISC_DEVICES=y
619# CONFIG_EEPROM_LEGACY is not set 679# CONFIG_EEPROM_LEGACY is not set
620# CONFIG_EEPROM_MAX6875 is not set 680# CONFIG_EEPROM_MAX6875 is not set
621# CONFIG_EEPROM_93CX6 is not set 681# CONFIG_EEPROM_93CX6 is not set
682# CONFIG_IWMC3200TOP is not set
622CONFIG_HAVE_IDE=y 683CONFIG_HAVE_IDE=y
623# CONFIG_IDE is not set 684# CONFIG_IDE is not set
624 685
625# 686#
626# SCSI device support 687# SCSI device support
627# 688#
689CONFIG_SCSI_MOD=y
628# CONFIG_RAID_ATTRS is not set 690# CONFIG_RAID_ATTRS is not set
629# CONFIG_SCSI is not set 691# CONFIG_SCSI is not set
630# CONFIG_SCSI_DMA is not set 692# CONFIG_SCSI_DMA is not set
@@ -656,6 +718,7 @@ CONFIG_PHYLIB=y
656# CONFIG_NATIONAL_PHY is not set 718# CONFIG_NATIONAL_PHY is not set
657# CONFIG_STE10XP is not set 719# CONFIG_STE10XP is not set
658# CONFIG_LSI_ET1011C_PHY is not set 720# CONFIG_LSI_ET1011C_PHY is not set
721# CONFIG_MICREL_PHY is not set
659# CONFIG_FIXED_PHY is not set 722# CONFIG_FIXED_PHY is not set
660# CONFIG_MDIO_BITBANG is not set 723# CONFIG_MDIO_BITBANG is not set
661CONFIG_NET_ETHERNET=y 724CONFIG_NET_ETHERNET=y
@@ -663,7 +726,6 @@ CONFIG_MII=y
663CONFIG_BFIN_MAC=y 726CONFIG_BFIN_MAC=y
664CONFIG_BFIN_TX_DESC_NUM=10 727CONFIG_BFIN_TX_DESC_NUM=10
665CONFIG_BFIN_RX_DESC_NUM=20 728CONFIG_BFIN_RX_DESC_NUM=20
666# CONFIG_BFIN_MAC_RMII is not set
667CONFIG_BFIN_MAC_USE_HWSTAMP=y 729CONFIG_BFIN_MAC_USE_HWSTAMP=y
668# CONFIG_SMC91X is not set 730# CONFIG_SMC91X is not set
669# CONFIG_DM9000 is not set 731# CONFIG_DM9000 is not set
@@ -702,32 +764,7 @@ CONFIG_BFIN_MAC_USE_HWSTAMP=y
702# 764#
703# Input device support 765# Input device support
704# 766#
705CONFIG_INPUT=y 767# CONFIG_INPUT is not set
706# CONFIG_INPUT_FF_MEMLESS is not set
707# CONFIG_INPUT_POLLDEV is not set
708
709#
710# Userland interfaces
711#
712# CONFIG_INPUT_MOUSEDEV is not set
713# CONFIG_INPUT_JOYDEV is not set
714# CONFIG_INPUT_EVDEV is not set
715# CONFIG_INPUT_EVBUG is not set
716
717#
718# Input Device Drivers
719#
720# CONFIG_INPUT_KEYBOARD is not set
721# CONFIG_INPUT_MOUSE is not set
722# CONFIG_INPUT_JOYSTICK is not set
723# CONFIG_INPUT_TABLET is not set
724# CONFIG_INPUT_TOUCHSCREEN is not set
725CONFIG_INPUT_MISC=y
726# CONFIG_INPUT_UINPUT is not set
727# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
728# CONFIG_INPUT_AD714X is not set
729# CONFIG_INPUT_ADXL34X is not set
730# CONFIG_INPUT_PCF8574 is not set
731 768
732# 769#
733# Hardware I/O ports 770# Hardware I/O ports
@@ -745,11 +782,7 @@ CONFIG_BFIN_DMA_INTERFACE=m
745# CONFIG_BFIN_SPI_ADC is not set 782# CONFIG_BFIN_SPI_ADC is not set
746# CONFIG_BFIN_SPORT is not set 783# CONFIG_BFIN_SPORT is not set
747# CONFIG_BFIN_TWI_LCD is not set 784# CONFIG_BFIN_TWI_LCD is not set
748CONFIG_VT=y 785# CONFIG_VT is not set
749CONFIG_CONSOLE_TRANSLATIONS=y
750CONFIG_VT_CONSOLE=y
751CONFIG_HW_CONSOLE=y
752# CONFIG_VT_HW_CONSOLE_BINDING is not set
753# CONFIG_DEVKMEM is not set 786# CONFIG_DEVKMEM is not set
754CONFIG_BFIN_JTAG_COMM=m 787CONFIG_BFIN_JTAG_COMM=m
755# CONFIG_SERIAL_NONSTANDARD is not set 788# CONFIG_SERIAL_NONSTANDARD is not set
@@ -773,6 +806,7 @@ CONFIG_SERIAL_BFIN_UART0=y
773CONFIG_SERIAL_CORE=y 806CONFIG_SERIAL_CORE=y
774CONFIG_SERIAL_CORE_CONSOLE=y 807CONFIG_SERIAL_CORE_CONSOLE=y
775# CONFIG_SERIAL_BFIN_SPORT is not set 808# CONFIG_SERIAL_BFIN_SPORT is not set
809# CONFIG_SERIAL_TIMBERDALE is not set
776CONFIG_UNIX98_PTYS=y 810CONFIG_UNIX98_PTYS=y
777# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 811# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
778# CONFIG_LEGACY_PTYS is not set 812# CONFIG_LEGACY_PTYS is not set
@@ -801,6 +835,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
801# CONFIG_I2C_GPIO is not set 835# CONFIG_I2C_GPIO is not set
802# CONFIG_I2C_OCORES is not set 836# CONFIG_I2C_OCORES is not set
803# CONFIG_I2C_SIMTEC is not set 837# CONFIG_I2C_SIMTEC is not set
838# CONFIG_I2C_XILINX is not set
804 839
805# 840#
806# External I2C/SMBus adapter drivers 841# External I2C/SMBus adapter drivers
@@ -813,16 +848,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
813# 848#
814# CONFIG_I2C_PCA_PLATFORM is not set 849# CONFIG_I2C_PCA_PLATFORM is not set
815# CONFIG_I2C_STUB is not set 850# CONFIG_I2C_STUB is not set
816
817#
818# Miscellaneous I2C Chip support
819#
820# CONFIG_DS1682 is not set
821# CONFIG_SENSORS_TSL2550 is not set
822# CONFIG_I2C_DEBUG_CORE is not set 851# CONFIG_I2C_DEBUG_CORE is not set
823# CONFIG_I2C_DEBUG_ALGO is not set 852# CONFIG_I2C_DEBUG_ALGO is not set
824# CONFIG_I2C_DEBUG_BUS is not set 853# CONFIG_I2C_DEBUG_BUS is not set
825# CONFIG_I2C_DEBUG_CHIP is not set
826CONFIG_SPI=y 854CONFIG_SPI=y
827# CONFIG_SPI_DEBUG is not set 855# CONFIG_SPI_DEBUG is not set
828CONFIG_SPI_MASTER=y 856CONFIG_SPI_MASTER=y
@@ -835,6 +863,8 @@ CONFIG_SPI_BFIN=y
835# CONFIG_SPI_BFIN_SPORT is not set 863# CONFIG_SPI_BFIN_SPORT is not set
836# CONFIG_SPI_BITBANG is not set 864# CONFIG_SPI_BITBANG is not set
837# CONFIG_SPI_GPIO is not set 865# CONFIG_SPI_GPIO is not set
866# CONFIG_SPI_XILINX is not set
867# CONFIG_SPI_DESIGNWARE is not set
838 868
839# 869#
840# SPI Protocol Masters 870# SPI Protocol Masters
@@ -854,10 +884,12 @@ CONFIG_GPIO_SYSFS=y
854# 884#
855# Memory mapped GPIO expanders: 885# Memory mapped GPIO expanders:
856# 886#
887# CONFIG_GPIO_IT8761E is not set
857 888
858# 889#
859# I2C GPIO expanders: 890# I2C GPIO expanders:
860# 891#
892# CONFIG_GPIO_MAX7300 is not set
861# CONFIG_GPIO_MAX732X is not set 893# CONFIG_GPIO_MAX732X is not set
862# CONFIG_GPIO_PCA953X is not set 894# CONFIG_GPIO_PCA953X is not set
863# CONFIG_GPIO_PCF857X is not set 895# CONFIG_GPIO_PCF857X is not set
@@ -900,20 +932,25 @@ CONFIG_SSB_POSSIBLE=y
900# Multifunction device drivers 932# Multifunction device drivers
901# 933#
902# CONFIG_MFD_CORE is not set 934# CONFIG_MFD_CORE is not set
935# CONFIG_MFD_88PM860X is not set
903# CONFIG_MFD_SM501 is not set 936# CONFIG_MFD_SM501 is not set
904# CONFIG_HTC_PASIC3 is not set 937# CONFIG_HTC_PASIC3 is not set
938# CONFIG_HTC_I2CPLD is not set
905# CONFIG_TPS65010 is not set 939# CONFIG_TPS65010 is not set
906# CONFIG_TWL4030_CORE is not set 940# CONFIG_TWL4030_CORE is not set
907# CONFIG_MFD_TMIO is not set 941# CONFIG_MFD_TMIO is not set
908# CONFIG_PMIC_DA903X is not set 942# CONFIG_PMIC_DA903X is not set
909# CONFIG_PMIC_ADP5520 is not set 943# CONFIG_PMIC_ADP5520 is not set
944# CONFIG_MFD_MAX8925 is not set
910# CONFIG_MFD_WM8400 is not set 945# CONFIG_MFD_WM8400 is not set
911# CONFIG_MFD_WM831X is not set 946# CONFIG_MFD_WM831X is not set
912# CONFIG_MFD_WM8350_I2C is not set 947# CONFIG_MFD_WM8350_I2C is not set
948# CONFIG_MFD_WM8994 is not set
913# CONFIG_MFD_PCF50633 is not set 949# CONFIG_MFD_PCF50633 is not set
914# CONFIG_MFD_MC13783 is not set 950# CONFIG_MFD_MC13783 is not set
915# CONFIG_AB3100_CORE is not set 951# CONFIG_AB3100_CORE is not set
916# CONFIG_EZX_PCAP is not set 952# CONFIG_EZX_PCAP is not set
953# CONFIG_AB4500_CORE is not set
917# CONFIG_REGULATOR is not set 954# CONFIG_REGULATOR is not set
918# CONFIG_MEDIA_SUPPORT is not set 955# CONFIG_MEDIA_SUPPORT is not set
919 956
@@ -929,13 +966,7 @@ CONFIG_SSB_POSSIBLE=y
929# Display device support 966# Display device support
930# 967#
931# CONFIG_DISPLAY_SUPPORT is not set 968# CONFIG_DISPLAY_SUPPORT is not set
932
933#
934# Console display driver support
935#
936CONFIG_DUMMY_CONSOLE=y
937# CONFIG_SOUND is not set 969# CONFIG_SOUND is not set
938# CONFIG_HID_SUPPORT is not set
939# CONFIG_USB_SUPPORT is not set 970# CONFIG_USB_SUPPORT is not set
940CONFIG_MMC=y 971CONFIG_MMC=y
941# CONFIG_MMC_DEBUG is not set 972# CONFIG_MMC_DEBUG is not set
@@ -953,10 +984,8 @@ CONFIG_MMC_BLOCK_BOUNCE=y
953# MMC/SD/SDIO Host Controller Drivers 984# MMC/SD/SDIO Host Controller Drivers
954# 985#
955# CONFIG_MMC_SDHCI is not set 986# CONFIG_MMC_SDHCI is not set
956# CONFIG_MMC_AT91 is not set
957# CONFIG_MMC_ATMELMCI is not set
958# CONFIG_MMC_SPI is not set 987# CONFIG_MMC_SPI is not set
959CONFIG_SDH_BFIN=m 988CONFIG_SDH_BFIN=y
960CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y 989CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
961# CONFIG_MEMSTICK is not set 990# CONFIG_MEMSTICK is not set
962# CONFIG_NEW_LEDS is not set 991# CONFIG_NEW_LEDS is not set
@@ -989,6 +1018,7 @@ CONFIG_RTC_INTF_DEV=y
989# CONFIG_RTC_DRV_PCF8563 is not set 1018# CONFIG_RTC_DRV_PCF8563 is not set
990# CONFIG_RTC_DRV_PCF8583 is not set 1019# CONFIG_RTC_DRV_PCF8583 is not set
991# CONFIG_RTC_DRV_M41T80 is not set 1020# CONFIG_RTC_DRV_M41T80 is not set
1021# CONFIG_RTC_DRV_BQ32K is not set
992# CONFIG_RTC_DRV_S35390A is not set 1022# CONFIG_RTC_DRV_S35390A is not set
993# CONFIG_RTC_DRV_FM3130 is not set 1023# CONFIG_RTC_DRV_FM3130 is not set
994# CONFIG_RTC_DRV_RX8581 is not set 1024# CONFIG_RTC_DRV_RX8581 is not set
@@ -1017,7 +1047,9 @@ CONFIG_RTC_INTF_DEV=y
1017# CONFIG_RTC_DRV_M48T86 is not set 1047# CONFIG_RTC_DRV_M48T86 is not set
1018# CONFIG_RTC_DRV_M48T35 is not set 1048# CONFIG_RTC_DRV_M48T35 is not set
1019# CONFIG_RTC_DRV_M48T59 is not set 1049# CONFIG_RTC_DRV_M48T59 is not set
1050# CONFIG_RTC_DRV_MSM6242 is not set
1020# CONFIG_RTC_DRV_BQ4802 is not set 1051# CONFIG_RTC_DRV_BQ4802 is not set
1052# CONFIG_RTC_DRV_RP5C01 is not set
1021# CONFIG_RTC_DRV_V3020 is not set 1053# CONFIG_RTC_DRV_V3020 is not set
1022 1054
1023# 1055#
@@ -1050,7 +1082,6 @@ CONFIG_EXT2_FS=m
1050# CONFIG_JFS_FS is not set 1082# CONFIG_JFS_FS is not set
1051# CONFIG_FS_POSIX_ACL is not set 1083# CONFIG_FS_POSIX_ACL is not set
1052# CONFIG_XFS_FS is not set 1084# CONFIG_XFS_FS is not set
1053# CONFIG_GFS2_FS is not set
1054# CONFIG_OCFS2_FS is not set 1085# CONFIG_OCFS2_FS is not set
1055# CONFIG_BTRFS_FS is not set 1086# CONFIG_BTRFS_FS is not set
1056# CONFIG_NILFS2_FS is not set 1087# CONFIG_NILFS2_FS is not set
@@ -1102,6 +1133,7 @@ CONFIG_MISC_FILESYSTEMS=y
1102# CONFIG_BFS_FS is not set 1133# CONFIG_BFS_FS is not set
1103# CONFIG_EFS_FS is not set 1134# CONFIG_EFS_FS is not set
1104# CONFIG_JFFS2_FS is not set 1135# CONFIG_JFFS2_FS is not set
1136# CONFIG_LOGFS is not set
1105# CONFIG_CRAMFS is not set 1137# CONFIG_CRAMFS is not set
1106# CONFIG_SQUASHFS is not set 1138# CONFIG_SQUASHFS is not set
1107# CONFIG_VXFS_FS is not set 1139# CONFIG_VXFS_FS is not set
@@ -1126,6 +1158,7 @@ CONFIG_SUNRPC=m
1126# CONFIG_RPCSEC_GSS_SPKM3 is not set 1158# CONFIG_RPCSEC_GSS_SPKM3 is not set
1127CONFIG_SMB_FS=m 1159CONFIG_SMB_FS=m
1128# CONFIG_SMB_NLS_DEFAULT is not set 1160# CONFIG_SMB_NLS_DEFAULT is not set
1161# CONFIG_CEPH_FS is not set
1129# CONFIG_CIFS is not set 1162# CONFIG_CIFS is not set
1130# CONFIG_NCP_FS is not set 1163# CONFIG_NCP_FS is not set
1131# CONFIG_CODA_FS is not set 1164# CONFIG_CODA_FS is not set
@@ -1204,6 +1237,8 @@ CONFIG_SCHED_DEBUG=y
1204# CONFIG_TIMER_STATS is not set 1237# CONFIG_TIMER_STATS is not set
1205# CONFIG_DEBUG_OBJECTS is not set 1238# CONFIG_DEBUG_OBJECTS is not set
1206# CONFIG_DEBUG_SLAB is not set 1239# CONFIG_DEBUG_SLAB is not set
1240# CONFIG_DEBUG_RT_MUTEXES is not set
1241# CONFIG_RT_MUTEX_TESTER is not set
1207# CONFIG_DEBUG_SPINLOCK is not set 1242# CONFIG_DEBUG_SPINLOCK is not set
1208# CONFIG_DEBUG_MUTEXES is not set 1243# CONFIG_DEBUG_MUTEXES is not set
1209# CONFIG_DEBUG_LOCK_ALLOC is not set 1244# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1227,17 +1262,20 @@ CONFIG_DEBUG_INFO=y
1227# CONFIG_RCU_TORTURE_TEST is not set 1262# CONFIG_RCU_TORTURE_TEST is not set
1228# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1263# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1229# CONFIG_BACKTRACE_SELF_TEST is not set 1264# CONFIG_BACKTRACE_SELF_TEST is not set
1265# CONFIG_TRACEHOOK_SELF_TEST is not set
1230# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1266# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1231# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1267# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1268# CONFIG_LKDTM is not set
1232# CONFIG_FAULT_INJECTION is not set 1269# CONFIG_FAULT_INJECTION is not set
1270# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1233# CONFIG_PAGE_POISONING is not set 1271# CONFIG_PAGE_POISONING is not set
1234CONFIG_HAVE_FUNCTION_TRACER=y 1272CONFIG_HAVE_FUNCTION_TRACER=y
1235CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1273CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1274CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1275CONFIG_HAVE_DYNAMIC_FTRACE=y
1276CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1236CONFIG_TRACING_SUPPORT=y 1277CONFIG_TRACING_SUPPORT=y
1237# CONFIG_FTRACE is not set 1278# CONFIG_FTRACE is not set
1238# CONFIG_BRANCH_PROFILE_NONE is not set
1239# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1240# CONFIG_PROFILE_ALL_BRANCHES is not set
1241# CONFIG_DYNAMIC_DEBUG is not set 1279# CONFIG_DYNAMIC_DEBUG is not set
1242# CONFIG_SAMPLES is not set 1280# CONFIG_SAMPLES is not set
1243CONFIG_HAVE_ARCH_KGDB=y 1281CONFIG_HAVE_ARCH_KGDB=y
@@ -1264,6 +1302,7 @@ CONFIG_EARLY_PRINTK=y
1264CONFIG_CPLB_INFO=y 1302CONFIG_CPLB_INFO=y
1265CONFIG_ACCESS_CHECK=y 1303CONFIG_ACCESS_CHECK=y
1266# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1304# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1305# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1267 1306
1268# 1307#
1269# Security options 1308# Security options
@@ -1273,8 +1312,12 @@ CONFIG_SECURITY=y
1273# CONFIG_SECURITYFS is not set 1312# CONFIG_SECURITYFS is not set
1274# CONFIG_SECURITY_NETWORK is not set 1313# CONFIG_SECURITY_NETWORK is not set
1275# CONFIG_SECURITY_PATH is not set 1314# CONFIG_SECURITY_PATH is not set
1276# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1277# CONFIG_SECURITY_TOMOYO is not set 1315# CONFIG_SECURITY_TOMOYO is not set
1316# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1317# CONFIG_DEFAULT_SECURITY_SMACK is not set
1318# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1319CONFIG_DEFAULT_SECURITY_DAC=y
1320CONFIG_DEFAULT_SECURITY=""
1278CONFIG_CRYPTO=y 1321CONFIG_CRYPTO=y
1279 1322
1280# 1323#
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 31c2a6db6ec5..d543f95f55ef 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 109# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 113CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 114CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 115# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +126,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 126# IO Schedulers
123# 127#
124CONFIG_IOSCHED_NOOP=y 128CONFIG_IOSCHED_NOOP=y
125# CONFIG_IOSCHED_AS is not set
126# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
127# CONFIG_IOSCHED_CFQ is not set 130# CONFIG_IOSCHED_CFQ is not set
128# CONFIG_DEFAULT_AS is not set
129# CONFIG_DEFAULT_DEADLINE is not set 131# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 132# CONFIG_DEFAULT_CFQ is not set
131CONFIG_DEFAULT_NOOP=y 133CONFIG_DEFAULT_NOOP=y
132CONFIG_DEFAULT_IOSCHED="noop" 134CONFIG_DEFAULT_IOSCHED="noop"
135# CONFIG_INLINE_SPIN_TRYLOCK is not set
136# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
137# CONFIG_INLINE_SPIN_LOCK is not set
138# CONFIG_INLINE_SPIN_LOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
141CONFIG_INLINE_SPIN_UNLOCK=y
142# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
143CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
144# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
145# CONFIG_INLINE_READ_TRYLOCK is not set
146# CONFIG_INLINE_READ_LOCK is not set
147# CONFIG_INLINE_READ_LOCK_BH is not set
148# CONFIG_INLINE_READ_LOCK_IRQ is not set
149# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
150CONFIG_INLINE_READ_UNLOCK=y
151# CONFIG_INLINE_READ_UNLOCK_BH is not set
152CONFIG_INLINE_READ_UNLOCK_IRQ=y
153# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
154# CONFIG_INLINE_WRITE_TRYLOCK is not set
155# CONFIG_INLINE_WRITE_LOCK is not set
156# CONFIG_INLINE_WRITE_LOCK_BH is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
159CONFIG_INLINE_WRITE_UNLOCK=y
160# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
161CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
162# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
163# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 164# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 165CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
@@ -232,6 +263,7 @@ CONFIG_BF52x=y
232# CONFIG_BFIN527_EZKIT_V2 is not set 263# CONFIG_BFIN527_EZKIT_V2 is not set
233# CONFIG_BFIN527_BLUETECHNIX_CM is not set 264# CONFIG_BFIN527_BLUETECHNIX_CM is not set
234CONFIG_BFIN526_EZBRD=y 265CONFIG_BFIN526_EZBRD=y
266# CONFIG_BFIN527_AD7160EVAL is not set
235 267
236# 268#
237# BF527 Specific Configuration 269# BF527 Specific Configuration
@@ -294,8 +326,16 @@ CONFIG_HZ=250
294# CONFIG_SCHED_HRTICK is not set 326# CONFIG_SCHED_HRTICK is not set
295CONFIG_GENERIC_TIME=y 327CONFIG_GENERIC_TIME=y
296CONFIG_GENERIC_CLOCKEVENTS=y 328CONFIG_GENERIC_CLOCKEVENTS=y
329
330#
331# Clock event device
332#
297# CONFIG_TICKSOURCE_GPTMR0 is not set 333# CONFIG_TICKSOURCE_GPTMR0 is not set
298CONFIG_TICKSOURCE_CORETMR=y 334CONFIG_TICKSOURCE_CORETMR=y
335
336#
337# Clock souce
338#
299# CONFIG_CYCLES_CLOCKSOURCE is not set 339# CONFIG_CYCLES_CLOCKSOURCE is not set
300# CONFIG_GPTMR0_CLOCKSOURCE is not set 340# CONFIG_GPTMR0_CLOCKSOURCE is not set
301# CONFIG_NO_HZ is not set 341# CONFIG_NO_HZ is not set
@@ -326,12 +366,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
326CONFIG_ACCESS_OK_L1=y 366CONFIG_ACCESS_OK_L1=y
327# CONFIG_MEMSET_L1 is not set 367# CONFIG_MEMSET_L1 is not set
328# CONFIG_MEMCPY_L1 is not set 368# CONFIG_MEMCPY_L1 is not set
369CONFIG_STRCMP_L1=y
370CONFIG_STRNCMP_L1=y
371CONFIG_STRCPY_L1=y
372CONFIG_STRNCPY_L1=y
329# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set 373# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
330# CONFIG_IP_CHECKSUM_L1 is not set 374# CONFIG_IP_CHECKSUM_L1 is not set
331CONFIG_CACHELINE_ALIGNED_L1=y 375CONFIG_CACHELINE_ALIGNED_L1=y
332# CONFIG_SYSCALL_TAB_L1 is not set 376# CONFIG_SYSCALL_TAB_L1 is not set
333# CONFIG_CPLB_SWITCH_TAB_L1 is not set 377# CONFIG_CPLB_SWITCH_TAB_L1 is not set
334CONFIG_APP_STACK_L1=y 378CONFIG_CACHE_FLUSH_L1=y
335 379
336# 380#
337# Speed Optimizations 381# Speed Optimizations
@@ -431,7 +475,6 @@ CONFIG_NET=y
431# Networking options 475# Networking options
432# 476#
433CONFIG_PACKET=y 477CONFIG_PACKET=y
434# CONFIG_PACKET_MMAP is not set
435CONFIG_UNIX=y 478CONFIG_UNIX=y
436# CONFIG_NET_KEY is not set 479# CONFIG_NET_KEY is not set
437CONFIG_INET=y 480CONFIG_INET=y
@@ -614,6 +657,10 @@ CONFIG_MTD_NAND_IDS=m
614CONFIG_BLK_DEV=y 657CONFIG_BLK_DEV=y
615# CONFIG_BLK_DEV_COW_COMMON is not set 658# CONFIG_BLK_DEV_COW_COMMON is not set
616# CONFIG_BLK_DEV_LOOP is not set 659# CONFIG_BLK_DEV_LOOP is not set
660
661#
662# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
663#
617# CONFIG_BLK_DEV_NBD is not set 664# CONFIG_BLK_DEV_NBD is not set
618# CONFIG_BLK_DEV_UB is not set 665# CONFIG_BLK_DEV_UB is not set
619CONFIG_BLK_DEV_RAM=y 666CONFIG_BLK_DEV_RAM=y
@@ -628,6 +675,9 @@ CONFIG_MISC_DEVICES=y
628# CONFIG_ICS932S401 is not set 675# CONFIG_ICS932S401 is not set
629# CONFIG_ENCLOSURE_SERVICES is not set 676# CONFIG_ENCLOSURE_SERVICES is not set
630# CONFIG_ISL29003 is not set 677# CONFIG_ISL29003 is not set
678# CONFIG_SENSORS_TSL2550 is not set
679# CONFIG_DS1682 is not set
680# CONFIG_TI_DAC7512 is not set
631# CONFIG_C2PORT is not set 681# CONFIG_C2PORT is not set
632 682
633# 683#
@@ -644,6 +694,7 @@ CONFIG_HAVE_IDE=y
644# 694#
645# SCSI device support 695# SCSI device support
646# 696#
697CONFIG_SCSI_MOD=y
647# CONFIG_RAID_ATTRS is not set 698# CONFIG_RAID_ATTRS is not set
648CONFIG_SCSI=y 699CONFIG_SCSI=y
649CONFIG_SCSI_DMA=y 700CONFIG_SCSI_DMA=y
@@ -705,6 +756,7 @@ CONFIG_PHYLIB=y
705# CONFIG_NATIONAL_PHY is not set 756# CONFIG_NATIONAL_PHY is not set
706# CONFIG_STE10XP is not set 757# CONFIG_STE10XP is not set
707# CONFIG_LSI_ET1011C_PHY is not set 758# CONFIG_LSI_ET1011C_PHY is not set
759# CONFIG_MICREL_PHY is not set
708# CONFIG_FIXED_PHY is not set 760# CONFIG_FIXED_PHY is not set
709# CONFIG_MDIO_BITBANG is not set 761# CONFIG_MDIO_BITBANG is not set
710CONFIG_NET_ETHERNET=y 762CONFIG_NET_ETHERNET=y
@@ -712,7 +764,6 @@ CONFIG_MII=y
712CONFIG_BFIN_MAC=y 764CONFIG_BFIN_MAC=y
713CONFIG_BFIN_TX_DESC_NUM=10 765CONFIG_BFIN_TX_DESC_NUM=10
714CONFIG_BFIN_RX_DESC_NUM=20 766CONFIG_BFIN_RX_DESC_NUM=20
715CONFIG_BFIN_MAC_RMII=y
716# CONFIG_SMC91X is not set 767# CONFIG_SMC91X is not set
717# CONFIG_DM9000 is not set 768# CONFIG_DM9000 is not set
718# CONFIG_ENC28J60 is not set 769# CONFIG_ENC28J60 is not set
@@ -747,6 +798,7 @@ CONFIG_BFIN_MAC_RMII=y
747# CONFIG_USB_PEGASUS is not set 798# CONFIG_USB_PEGASUS is not set
748# CONFIG_USB_RTL8150 is not set 799# CONFIG_USB_RTL8150 is not set
749# CONFIG_USB_USBNET is not set 800# CONFIG_USB_USBNET is not set
801# CONFIG_USB_IPHETH is not set
750# CONFIG_WAN is not set 802# CONFIG_WAN is not set
751# CONFIG_PPP is not set 803# CONFIG_PPP is not set
752# CONFIG_SLIP is not set 804# CONFIG_SLIP is not set
@@ -762,6 +814,7 @@ CONFIG_BFIN_MAC_RMII=y
762CONFIG_INPUT=y 814CONFIG_INPUT=y
763CONFIG_INPUT_FF_MEMLESS=m 815CONFIG_INPUT_FF_MEMLESS=m
764# CONFIG_INPUT_POLLDEV is not set 816# CONFIG_INPUT_POLLDEV is not set
817# CONFIG_INPUT_SPARSEKMAP is not set
765 818
766# 819#
767# Userland interfaces 820# Userland interfaces
@@ -780,6 +833,7 @@ CONFIG_INPUT_FF_MEMLESS=m
780# CONFIG_INPUT_TABLET is not set 833# CONFIG_INPUT_TABLET is not set
781# CONFIG_INPUT_TOUCHSCREEN is not set 834# CONFIG_INPUT_TOUCHSCREEN is not set
782CONFIG_INPUT_MISC=y 835CONFIG_INPUT_MISC=y
836# CONFIG_INPUT_AD714X is not set
783# CONFIG_INPUT_ATI_REMOTE is not set 837# CONFIG_INPUT_ATI_REMOTE is not set
784# CONFIG_INPUT_ATI_REMOTE2 is not set 838# CONFIG_INPUT_ATI_REMOTE2 is not set
785# CONFIG_INPUT_KEYSPAN_REMOTE is not set 839# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@@ -787,11 +841,10 @@ CONFIG_INPUT_MISC=y
787# CONFIG_INPUT_YEALINK is not set 841# CONFIG_INPUT_YEALINK is not set
788# CONFIG_INPUT_CM109 is not set 842# CONFIG_INPUT_CM109 is not set
789# CONFIG_INPUT_UINPUT is not set 843# CONFIG_INPUT_UINPUT is not set
844# CONFIG_INPUT_PCF8574 is not set
790# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 845# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
791# CONFIG_INPUT_BFIN_ROTARY is not set 846# CONFIG_INPUT_BFIN_ROTARY is not set
792# CONFIG_INPUT_AD714X is not set
793# CONFIG_INPUT_ADXL34X is not set 847# CONFIG_INPUT_ADXL34X is not set
794# CONFIG_INPUT_PCF8574 is not set
795 848
796# 849#
797# Hardware I/O ports 850# Hardware I/O ports
@@ -837,6 +890,7 @@ CONFIG_SERIAL_BFIN_UART1=y
837CONFIG_SERIAL_CORE=y 890CONFIG_SERIAL_CORE=y
838CONFIG_SERIAL_CORE_CONSOLE=y 891CONFIG_SERIAL_CORE_CONSOLE=y
839# CONFIG_SERIAL_BFIN_SPORT is not set 892# CONFIG_SERIAL_BFIN_SPORT is not set
893# CONFIG_SERIAL_TIMBERDALE is not set
840CONFIG_UNIX98_PTYS=y 894CONFIG_UNIX98_PTYS=y
841# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 895# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
842# CONFIG_LEGACY_PTYS is not set 896# CONFIG_LEGACY_PTYS is not set
@@ -865,6 +919,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
865# CONFIG_I2C_GPIO is not set 919# CONFIG_I2C_GPIO is not set
866# CONFIG_I2C_OCORES is not set 920# CONFIG_I2C_OCORES is not set
867# CONFIG_I2C_SIMTEC is not set 921# CONFIG_I2C_SIMTEC is not set
922# CONFIG_I2C_XILINX is not set
868 923
869# 924#
870# External I2C/SMBus adapter drivers 925# External I2C/SMBus adapter drivers
@@ -878,16 +933,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
878# 933#
879# CONFIG_I2C_PCA_PLATFORM is not set 934# CONFIG_I2C_PCA_PLATFORM is not set
880# CONFIG_I2C_STUB is not set 935# CONFIG_I2C_STUB is not set
881
882#
883# Miscellaneous I2C Chip support
884#
885# CONFIG_DS1682 is not set
886# CONFIG_SENSORS_TSL2550 is not set
887# CONFIG_I2C_DEBUG_CORE is not set 936# CONFIG_I2C_DEBUG_CORE is not set
888# CONFIG_I2C_DEBUG_ALGO is not set 937# CONFIG_I2C_DEBUG_ALGO is not set
889# CONFIG_I2C_DEBUG_BUS is not set 938# CONFIG_I2C_DEBUG_BUS is not set
890# CONFIG_I2C_DEBUG_CHIP is not set
891CONFIG_SPI=y 939CONFIG_SPI=y
892# CONFIG_SPI_DEBUG is not set 940# CONFIG_SPI_DEBUG is not set
893CONFIG_SPI_MASTER=y 941CONFIG_SPI_MASTER=y
@@ -900,6 +948,8 @@ CONFIG_SPI_BFIN=y
900# CONFIG_SPI_BFIN_SPORT is not set 948# CONFIG_SPI_BFIN_SPORT is not set
901# CONFIG_SPI_BITBANG is not set 949# CONFIG_SPI_BITBANG is not set
902# CONFIG_SPI_GPIO is not set 950# CONFIG_SPI_GPIO is not set
951# CONFIG_SPI_XILINX is not set
952# CONFIG_SPI_DESIGNWARE is not set
903 953
904# 954#
905# SPI Protocol Masters 955# SPI Protocol Masters
@@ -919,10 +969,12 @@ CONFIG_GPIO_SYSFS=y
919# 969#
920# Memory mapped GPIO expanders: 970# Memory mapped GPIO expanders:
921# 971#
972# CONFIG_GPIO_IT8761E is not set
922 973
923# 974#
924# I2C GPIO expanders: 975# I2C GPIO expanders:
925# 976#
977# CONFIG_GPIO_MAX7300 is not set
926# CONFIG_GPIO_MAX732X is not set 978# CONFIG_GPIO_MAX732X is not set
927# CONFIG_GPIO_PCA953X is not set 979# CONFIG_GPIO_PCA953X is not set
928# CONFIG_GPIO_PCF857X is not set 980# CONFIG_GPIO_PCF857X is not set
@@ -960,10 +1012,11 @@ CONFIG_HWMON=y
960# CONFIG_SENSORS_ADM1029 is not set 1012# CONFIG_SENSORS_ADM1029 is not set
961# CONFIG_SENSORS_ADM1031 is not set 1013# CONFIG_SENSORS_ADM1031 is not set
962# CONFIG_SENSORS_ADM9240 is not set 1014# CONFIG_SENSORS_ADM9240 is not set
1015# CONFIG_SENSORS_ADT7411 is not set
963# CONFIG_SENSORS_ADT7462 is not set 1016# CONFIG_SENSORS_ADT7462 is not set
964# CONFIG_SENSORS_ADT7470 is not set 1017# CONFIG_SENSORS_ADT7470 is not set
965# CONFIG_SENSORS_ADT7473 is not set
966# CONFIG_SENSORS_ADT7475 is not set 1018# CONFIG_SENSORS_ADT7475 is not set
1019# CONFIG_SENSORS_ASC7621 is not set
967# CONFIG_SENSORS_ATXP1 is not set 1020# CONFIG_SENSORS_ATXP1 is not set
968# CONFIG_SENSORS_DS1621 is not set 1021# CONFIG_SENSORS_DS1621 is not set
969# CONFIG_SENSORS_F71805F is not set 1022# CONFIG_SENSORS_F71805F is not set
@@ -975,6 +1028,7 @@ CONFIG_HWMON=y
975# CONFIG_SENSORS_IT87 is not set 1028# CONFIG_SENSORS_IT87 is not set
976# CONFIG_SENSORS_LM63 is not set 1029# CONFIG_SENSORS_LM63 is not set
977# CONFIG_SENSORS_LM70 is not set 1030# CONFIG_SENSORS_LM70 is not set
1031# CONFIG_SENSORS_LM73 is not set
978# CONFIG_SENSORS_LM75 is not set 1032# CONFIG_SENSORS_LM75 is not set
979# CONFIG_SENSORS_LM77 is not set 1033# CONFIG_SENSORS_LM77 is not set
980# CONFIG_SENSORS_LM78 is not set 1034# CONFIG_SENSORS_LM78 is not set
@@ -1000,6 +1054,7 @@ CONFIG_HWMON=y
1000# CONFIG_SENSORS_SMSC47M192 is not set 1054# CONFIG_SENSORS_SMSC47M192 is not set
1001# CONFIG_SENSORS_SMSC47B397 is not set 1055# CONFIG_SENSORS_SMSC47B397 is not set
1002# CONFIG_SENSORS_ADS7828 is not set 1056# CONFIG_SENSORS_ADS7828 is not set
1057# CONFIG_SENSORS_AMC6821 is not set
1003# CONFIG_SENSORS_THMC50 is not set 1058# CONFIG_SENSORS_THMC50 is not set
1004# CONFIG_SENSORS_TMP401 is not set 1059# CONFIG_SENSORS_TMP401 is not set
1005# CONFIG_SENSORS_TMP421 is not set 1060# CONFIG_SENSORS_TMP421 is not set
@@ -1013,6 +1068,7 @@ CONFIG_HWMON=y
1013# CONFIG_SENSORS_W83627HF is not set 1068# CONFIG_SENSORS_W83627HF is not set
1014# CONFIG_SENSORS_W83627EHF is not set 1069# CONFIG_SENSORS_W83627EHF is not set
1015# CONFIG_SENSORS_LIS3_SPI is not set 1070# CONFIG_SENSORS_LIS3_SPI is not set
1071# CONFIG_SENSORS_LIS3_I2C is not set
1016# CONFIG_THERMAL is not set 1072# CONFIG_THERMAL is not set
1017CONFIG_WATCHDOG=y 1073CONFIG_WATCHDOG=y
1018# CONFIG_WATCHDOG_NOWAYOUT is not set 1074# CONFIG_WATCHDOG_NOWAYOUT is not set
@@ -1038,20 +1094,25 @@ CONFIG_SSB_POSSIBLE=y
1038# Multifunction device drivers 1094# Multifunction device drivers
1039# 1095#
1040# CONFIG_MFD_CORE is not set 1096# CONFIG_MFD_CORE is not set
1097# CONFIG_MFD_88PM860X is not set
1041# CONFIG_MFD_SM501 is not set 1098# CONFIG_MFD_SM501 is not set
1042# CONFIG_HTC_PASIC3 is not set 1099# CONFIG_HTC_PASIC3 is not set
1100# CONFIG_HTC_I2CPLD is not set
1043# CONFIG_TPS65010 is not set 1101# CONFIG_TPS65010 is not set
1044# CONFIG_TWL4030_CORE is not set 1102# CONFIG_TWL4030_CORE is not set
1045# CONFIG_MFD_TMIO is not set 1103# CONFIG_MFD_TMIO is not set
1046# CONFIG_PMIC_DA903X is not set 1104# CONFIG_PMIC_DA903X is not set
1047# CONFIG_PMIC_ADP5520 is not set 1105# CONFIG_PMIC_ADP5520 is not set
1106# CONFIG_MFD_MAX8925 is not set
1048# CONFIG_MFD_WM8400 is not set 1107# CONFIG_MFD_WM8400 is not set
1049# CONFIG_MFD_WM831X is not set 1108# CONFIG_MFD_WM831X is not set
1050# CONFIG_MFD_WM8350_I2C is not set 1109# CONFIG_MFD_WM8350_I2C is not set
1110# CONFIG_MFD_WM8994 is not set
1051# CONFIG_MFD_PCF50633 is not set 1111# CONFIG_MFD_PCF50633 is not set
1052# CONFIG_MFD_MC13783 is not set 1112# CONFIG_MFD_MC13783 is not set
1053# CONFIG_AB3100_CORE is not set 1113# CONFIG_AB3100_CORE is not set
1054# CONFIG_EZX_PCAP is not set 1114# CONFIG_EZX_PCAP is not set
1115# CONFIG_AB4500_CORE is not set
1055# CONFIG_REGULATOR is not set 1116# CONFIG_REGULATOR is not set
1056# CONFIG_MEDIA_SUPPORT is not set 1117# CONFIG_MEDIA_SUPPORT is not set
1057 1118
@@ -1087,6 +1148,7 @@ CONFIG_USB_HID=y
1087# 1148#
1088# Special HID drivers 1149# Special HID drivers
1089# 1150#
1151# CONFIG_HID_3M_PCT is not set
1090CONFIG_HID_A4TECH=y 1152CONFIG_HID_A4TECH=y
1091CONFIG_HID_APPLE=y 1153CONFIG_HID_APPLE=y
1092CONFIG_HID_BELKIN=y 1154CONFIG_HID_BELKIN=y
@@ -1102,14 +1164,19 @@ CONFIG_HID_GYRATION=y
1102CONFIG_HID_LOGITECH=y 1164CONFIG_HID_LOGITECH=y
1103# CONFIG_LOGITECH_FF is not set 1165# CONFIG_LOGITECH_FF is not set
1104# CONFIG_LOGIRUMBLEPAD2_FF is not set 1166# CONFIG_LOGIRUMBLEPAD2_FF is not set
1167# CONFIG_LOGIG940_FF is not set
1105CONFIG_HID_MICROSOFT=y 1168CONFIG_HID_MICROSOFT=y
1169# CONFIG_HID_MOSART is not set
1106CONFIG_HID_MONTEREY=y 1170CONFIG_HID_MONTEREY=y
1107# CONFIG_HID_NTRIG is not set 1171# CONFIG_HID_NTRIG is not set
1172# CONFIG_HID_ORTEK is not set
1108CONFIG_HID_PANTHERLORD=y 1173CONFIG_HID_PANTHERLORD=y
1109# CONFIG_PANTHERLORD_FF is not set 1174# CONFIG_PANTHERLORD_FF is not set
1110CONFIG_HID_PETALYNX=y 1175CONFIG_HID_PETALYNX=y
1176# CONFIG_HID_QUANTA is not set
1111CONFIG_HID_SAMSUNG=y 1177CONFIG_HID_SAMSUNG=y
1112CONFIG_HID_SONY=y 1178CONFIG_HID_SONY=y
1179# CONFIG_HID_STANTUM is not set
1113CONFIG_HID_SUNPLUS=y 1180CONFIG_HID_SUNPLUS=y
1114# CONFIG_HID_GREENASIA is not set 1181# CONFIG_HID_GREENASIA is not set
1115# CONFIG_HID_SMARTJOYPLUS is not set 1182# CONFIG_HID_SMARTJOYPLUS is not set
@@ -1130,7 +1197,6 @@ CONFIG_USB=y
1130CONFIG_USB_DEVICEFS=y 1197CONFIG_USB_DEVICEFS=y
1131# CONFIG_USB_DEVICE_CLASS is not set 1198# CONFIG_USB_DEVICE_CLASS is not set
1132# CONFIG_USB_DYNAMIC_MINORS is not set 1199# CONFIG_USB_DYNAMIC_MINORS is not set
1133# CONFIG_USB_OTG is not set
1134# CONFIG_USB_OTG_WHITELIST is not set 1200# CONFIG_USB_OTG_WHITELIST is not set
1135CONFIG_USB_OTG_BLACKLIST_HUB=y 1201CONFIG_USB_OTG_BLACKLIST_HUB=y
1136CONFIG_USB_MON=y 1202CONFIG_USB_MON=y
@@ -1214,7 +1280,6 @@ CONFIG_USB_STORAGE=y
1214# CONFIG_USB_RIO500 is not set 1280# CONFIG_USB_RIO500 is not set
1215# CONFIG_USB_LEGOTOWER is not set 1281# CONFIG_USB_LEGOTOWER is not set
1216# CONFIG_USB_LCD is not set 1282# CONFIG_USB_LCD is not set
1217# CONFIG_USB_BERRY_CHARGE is not set
1218# CONFIG_USB_LED is not set 1283# CONFIG_USB_LED is not set
1219# CONFIG_USB_CYPRESS_CY7C63 is not set 1284# CONFIG_USB_CYPRESS_CY7C63 is not set
1220# CONFIG_USB_CYTHERM is not set 1285# CONFIG_USB_CYTHERM is not set
@@ -1227,7 +1292,6 @@ CONFIG_USB_STORAGE=y
1227# CONFIG_USB_IOWARRIOR is not set 1292# CONFIG_USB_IOWARRIOR is not set
1228# CONFIG_USB_TEST is not set 1293# CONFIG_USB_TEST is not set
1229# CONFIG_USB_ISIGHTFW is not set 1294# CONFIG_USB_ISIGHTFW is not set
1230# CONFIG_USB_VST is not set
1231# CONFIG_USB_GADGET is not set 1295# CONFIG_USB_GADGET is not set
1232 1296
1233# 1297#
@@ -1268,6 +1332,7 @@ CONFIG_RTC_INTF_DEV=y
1268# CONFIG_RTC_DRV_PCF8563 is not set 1332# CONFIG_RTC_DRV_PCF8563 is not set
1269# CONFIG_RTC_DRV_PCF8583 is not set 1333# CONFIG_RTC_DRV_PCF8583 is not set
1270# CONFIG_RTC_DRV_M41T80 is not set 1334# CONFIG_RTC_DRV_M41T80 is not set
1335# CONFIG_RTC_DRV_BQ32K is not set
1271# CONFIG_RTC_DRV_S35390A is not set 1336# CONFIG_RTC_DRV_S35390A is not set
1272# CONFIG_RTC_DRV_FM3130 is not set 1337# CONFIG_RTC_DRV_FM3130 is not set
1273# CONFIG_RTC_DRV_RX8581 is not set 1338# CONFIG_RTC_DRV_RX8581 is not set
@@ -1296,7 +1361,9 @@ CONFIG_RTC_INTF_DEV=y
1296# CONFIG_RTC_DRV_M48T86 is not set 1361# CONFIG_RTC_DRV_M48T86 is not set
1297# CONFIG_RTC_DRV_M48T35 is not set 1362# CONFIG_RTC_DRV_M48T35 is not set
1298# CONFIG_RTC_DRV_M48T59 is not set 1363# CONFIG_RTC_DRV_M48T59 is not set
1364# CONFIG_RTC_DRV_MSM6242 is not set
1299# CONFIG_RTC_DRV_BQ4802 is not set 1365# CONFIG_RTC_DRV_BQ4802 is not set
1366# CONFIG_RTC_DRV_RP5C01 is not set
1300# CONFIG_RTC_DRV_V3020 is not set 1367# CONFIG_RTC_DRV_V3020 is not set
1301 1368
1302# 1369#
@@ -1329,7 +1396,6 @@ CONFIG_EXT2_FS=m
1329# CONFIG_JFS_FS is not set 1396# CONFIG_JFS_FS is not set
1330# CONFIG_FS_POSIX_ACL is not set 1397# CONFIG_FS_POSIX_ACL is not set
1331# CONFIG_XFS_FS is not set 1398# CONFIG_XFS_FS is not set
1332# CONFIG_GFS2_FS is not set
1333# CONFIG_OCFS2_FS is not set 1399# CONFIG_OCFS2_FS is not set
1334# CONFIG_BTRFS_FS is not set 1400# CONFIG_BTRFS_FS is not set
1335# CONFIG_NILFS2_FS is not set 1401# CONFIG_NILFS2_FS is not set
@@ -1393,6 +1459,7 @@ CONFIG_JFFS2_ZLIB=y
1393# CONFIG_JFFS2_LZO is not set 1459# CONFIG_JFFS2_LZO is not set
1394CONFIG_JFFS2_RTIME=y 1460CONFIG_JFFS2_RTIME=y
1395# CONFIG_JFFS2_RUBIN is not set 1461# CONFIG_JFFS2_RUBIN is not set
1462# CONFIG_LOGFS is not set
1396# CONFIG_CRAMFS is not set 1463# CONFIG_CRAMFS is not set
1397# CONFIG_SQUASHFS is not set 1464# CONFIG_SQUASHFS is not set
1398# CONFIG_VXFS_FS is not set 1465# CONFIG_VXFS_FS is not set
@@ -1417,6 +1484,7 @@ CONFIG_SUNRPC=m
1417# CONFIG_RPCSEC_GSS_SPKM3 is not set 1484# CONFIG_RPCSEC_GSS_SPKM3 is not set
1418CONFIG_SMB_FS=m 1485CONFIG_SMB_FS=m
1419# CONFIG_SMB_NLS_DEFAULT is not set 1486# CONFIG_SMB_NLS_DEFAULT is not set
1487# CONFIG_CEPH_FS is not set
1420# CONFIG_CIFS is not set 1488# CONFIG_CIFS is not set
1421# CONFIG_NCP_FS is not set 1489# CONFIG_NCP_FS is not set
1422# CONFIG_CODA_FS is not set 1490# CONFIG_CODA_FS is not set
@@ -1495,6 +1563,8 @@ CONFIG_SCHED_DEBUG=y
1495# CONFIG_TIMER_STATS is not set 1563# CONFIG_TIMER_STATS is not set
1496# CONFIG_DEBUG_OBJECTS is not set 1564# CONFIG_DEBUG_OBJECTS is not set
1497# CONFIG_DEBUG_SLAB is not set 1565# CONFIG_DEBUG_SLAB is not set
1566# CONFIG_DEBUG_RT_MUTEXES is not set
1567# CONFIG_RT_MUTEX_TESTER is not set
1498# CONFIG_DEBUG_SPINLOCK is not set 1568# CONFIG_DEBUG_SPINLOCK is not set
1499# CONFIG_DEBUG_MUTEXES is not set 1569# CONFIG_DEBUG_MUTEXES is not set
1500# CONFIG_DEBUG_LOCK_ALLOC is not set 1570# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1518,17 +1588,18 @@ CONFIG_DEBUG_INFO=y
1518# CONFIG_RCU_TORTURE_TEST is not set 1588# CONFIG_RCU_TORTURE_TEST is not set
1519# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1589# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1520# CONFIG_BACKTRACE_SELF_TEST is not set 1590# CONFIG_BACKTRACE_SELF_TEST is not set
1591# CONFIG_TRACEHOOK_SELF_TEST is not set
1521# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1592# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1522# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1593# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1594# CONFIG_LKDTM is not set
1523# CONFIG_FAULT_INJECTION is not set 1595# CONFIG_FAULT_INJECTION is not set
1596# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1524# CONFIG_PAGE_POISONING is not set 1597# CONFIG_PAGE_POISONING is not set
1525CONFIG_HAVE_FUNCTION_TRACER=y 1598CONFIG_HAVE_FUNCTION_TRACER=y
1526CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1599CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1600CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1527CONFIG_TRACING_SUPPORT=y 1601CONFIG_TRACING_SUPPORT=y
1528# CONFIG_FTRACE is not set 1602# CONFIG_FTRACE is not set
1529# CONFIG_BRANCH_PROFILE_NONE is not set
1530# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1531# CONFIG_PROFILE_ALL_BRANCHES is not set
1532# CONFIG_DYNAMIC_DEBUG is not set 1603# CONFIG_DYNAMIC_DEBUG is not set
1533# CONFIG_SAMPLES is not set 1604# CONFIG_SAMPLES is not set
1534CONFIG_HAVE_ARCH_KGDB=y 1605CONFIG_HAVE_ARCH_KGDB=y
@@ -1555,6 +1626,7 @@ CONFIG_EARLY_PRINTK=y
1555CONFIG_CPLB_INFO=y 1626CONFIG_CPLB_INFO=y
1556CONFIG_ACCESS_CHECK=y 1627CONFIG_ACCESS_CHECK=y
1557# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1628# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1629# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1558 1630
1559# 1631#
1560# Security options 1632# Security options
@@ -1564,9 +1636,12 @@ CONFIG_SECURITY=y
1564# CONFIG_SECURITYFS is not set 1636# CONFIG_SECURITYFS is not set
1565# CONFIG_SECURITY_NETWORK is not set 1637# CONFIG_SECURITY_NETWORK is not set
1566# CONFIG_SECURITY_PATH is not set 1638# CONFIG_SECURITY_PATH is not set
1567# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1568# CONFIG_SECURITY_ROOTPLUG is not set
1569# CONFIG_SECURITY_TOMOYO is not set 1639# CONFIG_SECURITY_TOMOYO is not set
1640# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1641# CONFIG_DEFAULT_SECURITY_SMACK is not set
1642# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1643CONFIG_DEFAULT_SECURITY_DAC=y
1644CONFIG_DEFAULT_SECURITY=""
1570CONFIG_CRYPTO=y 1645CONFIG_CRYPTO=y
1571 1646
1572# 1647#
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index d2dfcb0e7ce4..c59670901b82 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 109# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 113CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 114CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 115# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +126,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 126# IO Schedulers
123# 127#
124CONFIG_IOSCHED_NOOP=y 128CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y 130CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 131# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 132CONFIG_DEFAULT_CFQ=y
131# CONFIG_DEFAULT_NOOP is not set 133# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 134CONFIG_DEFAULT_IOSCHED="cfq"
135# CONFIG_INLINE_SPIN_TRYLOCK is not set
136# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
137# CONFIG_INLINE_SPIN_LOCK is not set
138# CONFIG_INLINE_SPIN_LOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
141CONFIG_INLINE_SPIN_UNLOCK=y
142# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
143CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
144# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
145# CONFIG_INLINE_READ_TRYLOCK is not set
146# CONFIG_INLINE_READ_LOCK is not set
147# CONFIG_INLINE_READ_LOCK_BH is not set
148# CONFIG_INLINE_READ_LOCK_IRQ is not set
149# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
150CONFIG_INLINE_READ_UNLOCK=y
151# CONFIG_INLINE_READ_UNLOCK_BH is not set
152CONFIG_INLINE_READ_UNLOCK_IRQ=y
153# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
154# CONFIG_INLINE_WRITE_TRYLOCK is not set
155# CONFIG_INLINE_WRITE_LOCK is not set
156# CONFIG_INLINE_WRITE_LOCK_BH is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
159CONFIG_INLINE_WRITE_UNLOCK=y
160# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
161CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
162# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
163# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 164# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 165CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
@@ -232,6 +263,7 @@ CONFIG_BF52x=y
232CONFIG_BFIN527_EZKIT_V2=y 263CONFIG_BFIN527_EZKIT_V2=y
233# CONFIG_BFIN527_BLUETECHNIX_CM is not set 264# CONFIG_BFIN527_BLUETECHNIX_CM is not set
234# CONFIG_BFIN526_EZBRD is not set 265# CONFIG_BFIN526_EZBRD is not set
266# CONFIG_BFIN527_AD7160EVAL is not set
235 267
236# 268#
237# BF527 Specific Configuration 269# BF527 Specific Configuration
@@ -294,8 +326,16 @@ CONFIG_HZ=250
294# CONFIG_SCHED_HRTICK is not set 326# CONFIG_SCHED_HRTICK is not set
295CONFIG_GENERIC_TIME=y 327CONFIG_GENERIC_TIME=y
296CONFIG_GENERIC_CLOCKEVENTS=y 328CONFIG_GENERIC_CLOCKEVENTS=y
329
330#
331# Clock event device
332#
297# CONFIG_TICKSOURCE_GPTMR0 is not set 333# CONFIG_TICKSOURCE_GPTMR0 is not set
298CONFIG_TICKSOURCE_CORETMR=y 334CONFIG_TICKSOURCE_CORETMR=y
335
336#
337# Clock souce
338#
299# CONFIG_CYCLES_CLOCKSOURCE is not set 339# CONFIG_CYCLES_CLOCKSOURCE is not set
300# CONFIG_GPTMR0_CLOCKSOURCE is not set 340# CONFIG_GPTMR0_CLOCKSOURCE is not set
301# CONFIG_NO_HZ is not set 341# CONFIG_NO_HZ is not set
@@ -326,12 +366,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
326CONFIG_ACCESS_OK_L1=y 366CONFIG_ACCESS_OK_L1=y
327# CONFIG_MEMSET_L1 is not set 367# CONFIG_MEMSET_L1 is not set
328# CONFIG_MEMCPY_L1 is not set 368# CONFIG_MEMCPY_L1 is not set
369CONFIG_STRCMP_L1=y
370CONFIG_STRNCMP_L1=y
371CONFIG_STRCPY_L1=y
372CONFIG_STRNCPY_L1=y
329# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set 373# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
330# CONFIG_IP_CHECKSUM_L1 is not set 374# CONFIG_IP_CHECKSUM_L1 is not set
331CONFIG_CACHELINE_ALIGNED_L1=y 375CONFIG_CACHELINE_ALIGNED_L1=y
332# CONFIG_SYSCALL_TAB_L1 is not set 376# CONFIG_SYSCALL_TAB_L1 is not set
333# CONFIG_CPLB_SWITCH_TAB_L1 is not set 377# CONFIG_CPLB_SWITCH_TAB_L1 is not set
334CONFIG_APP_STACK_L1=y 378CONFIG_CACHE_FLUSH_L1=y
335 379
336# 380#
337# Speed Optimizations 381# Speed Optimizations
@@ -431,7 +475,6 @@ CONFIG_NET=y
431# Networking options 475# Networking options
432# 476#
433CONFIG_PACKET=y 477CONFIG_PACKET=y
434# CONFIG_PACKET_MMAP is not set
435CONFIG_UNIX=y 478CONFIG_UNIX=y
436# CONFIG_NET_KEY is not set 479# CONFIG_NET_KEY is not set
437CONFIG_INET=y 480CONFIG_INET=y
@@ -654,6 +697,10 @@ CONFIG_MTD_NAND_IDS=m
654CONFIG_BLK_DEV=y 697CONFIG_BLK_DEV=y
655# CONFIG_BLK_DEV_COW_COMMON is not set 698# CONFIG_BLK_DEV_COW_COMMON is not set
656# CONFIG_BLK_DEV_LOOP is not set 699# CONFIG_BLK_DEV_LOOP is not set
700
701#
702# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
703#
657# CONFIG_BLK_DEV_NBD is not set 704# CONFIG_BLK_DEV_NBD is not set
658# CONFIG_BLK_DEV_UB is not set 705# CONFIG_BLK_DEV_UB is not set
659CONFIG_BLK_DEV_RAM=y 706CONFIG_BLK_DEV_RAM=y
@@ -668,6 +715,9 @@ CONFIG_MISC_DEVICES=y
668# CONFIG_ICS932S401 is not set 715# CONFIG_ICS932S401 is not set
669# CONFIG_ENCLOSURE_SERVICES is not set 716# CONFIG_ENCLOSURE_SERVICES is not set
670# CONFIG_ISL29003 is not set 717# CONFIG_ISL29003 is not set
718# CONFIG_SENSORS_TSL2550 is not set
719# CONFIG_DS1682 is not set
720# CONFIG_TI_DAC7512 is not set
671# CONFIG_C2PORT is not set 721# CONFIG_C2PORT is not set
672 722
673# 723#
@@ -684,6 +734,7 @@ CONFIG_HAVE_IDE=y
684# 734#
685# SCSI device support 735# SCSI device support
686# 736#
737CONFIG_SCSI_MOD=y
687# CONFIG_RAID_ATTRS is not set 738# CONFIG_RAID_ATTRS is not set
688CONFIG_SCSI=y 739CONFIG_SCSI=y
689CONFIG_SCSI_DMA=y 740CONFIG_SCSI_DMA=y
@@ -745,6 +796,7 @@ CONFIG_PHYLIB=y
745# CONFIG_NATIONAL_PHY is not set 796# CONFIG_NATIONAL_PHY is not set
746# CONFIG_STE10XP is not set 797# CONFIG_STE10XP is not set
747# CONFIG_LSI_ET1011C_PHY is not set 798# CONFIG_LSI_ET1011C_PHY is not set
799# CONFIG_MICREL_PHY is not set
748# CONFIG_FIXED_PHY is not set 800# CONFIG_FIXED_PHY is not set
749# CONFIG_MDIO_BITBANG is not set 801# CONFIG_MDIO_BITBANG is not set
750CONFIG_NET_ETHERNET=y 802CONFIG_NET_ETHERNET=y
@@ -753,7 +805,6 @@ CONFIG_BFIN_MAC=y
753CONFIG_BFIN_MAC_USE_L1=y 805CONFIG_BFIN_MAC_USE_L1=y
754CONFIG_BFIN_TX_DESC_NUM=10 806CONFIG_BFIN_TX_DESC_NUM=10
755CONFIG_BFIN_RX_DESC_NUM=20 807CONFIG_BFIN_RX_DESC_NUM=20
756CONFIG_BFIN_MAC_RMII=y
757# CONFIG_SMC91X is not set 808# CONFIG_SMC91X is not set
758# CONFIG_DM9000 is not set 809# CONFIG_DM9000 is not set
759# CONFIG_ENC28J60 is not set 810# CONFIG_ENC28J60 is not set
@@ -788,6 +839,7 @@ CONFIG_BFIN_MAC_RMII=y
788# CONFIG_USB_PEGASUS is not set 839# CONFIG_USB_PEGASUS is not set
789# CONFIG_USB_RTL8150 is not set 840# CONFIG_USB_RTL8150 is not set
790# CONFIG_USB_USBNET is not set 841# CONFIG_USB_USBNET is not set
842# CONFIG_USB_IPHETH is not set
791# CONFIG_WAN is not set 843# CONFIG_WAN is not set
792# CONFIG_PPP is not set 844# CONFIG_PPP is not set
793# CONFIG_SLIP is not set 845# CONFIG_SLIP is not set
@@ -803,6 +855,7 @@ CONFIG_BFIN_MAC_RMII=y
803CONFIG_INPUT=y 855CONFIG_INPUT=y
804CONFIG_INPUT_FF_MEMLESS=m 856CONFIG_INPUT_FF_MEMLESS=m
805# CONFIG_INPUT_POLLDEV is not set 857# CONFIG_INPUT_POLLDEV is not set
858# CONFIG_INPUT_SPARSEKMAP is not set
806 859
807# 860#
808# Userland interfaces 861# Userland interfaces
@@ -836,8 +889,11 @@ CONFIG_KEYBOARD_ADP5520=y
836CONFIG_INPUT_TOUCHSCREEN=y 889CONFIG_INPUT_TOUCHSCREEN=y
837# CONFIG_TOUCHSCREEN_ADS7846 is not set 890# CONFIG_TOUCHSCREEN_ADS7846 is not set
838# CONFIG_TOUCHSCREEN_AD7877 is not set 891# CONFIG_TOUCHSCREEN_AD7877 is not set
839CONFIG_TOUCHSCREEN_AD7879_I2C=y
840CONFIG_TOUCHSCREEN_AD7879=y 892CONFIG_TOUCHSCREEN_AD7879=y
893CONFIG_TOUCHSCREEN_AD7879_I2C=y
894# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
895# CONFIG_TOUCHSCREEN_AD7160 is not set
896# CONFIG_TOUCHSCREEN_DYNAPRO is not set
841# CONFIG_TOUCHSCREEN_EETI is not set 897# CONFIG_TOUCHSCREEN_EETI is not set
842# CONFIG_TOUCHSCREEN_FUJITSU is not set 898# CONFIG_TOUCHSCREEN_FUJITSU is not set
843# CONFIG_TOUCHSCREEN_GUNZE is not set 899# CONFIG_TOUCHSCREEN_GUNZE is not set
@@ -855,6 +911,7 @@ CONFIG_TOUCHSCREEN_AD7879=y
855# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set 911# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
856# CONFIG_TOUCHSCREEN_TSC2007 is not set 912# CONFIG_TOUCHSCREEN_TSC2007 is not set
857CONFIG_INPUT_MISC=y 913CONFIG_INPUT_MISC=y
914# CONFIG_INPUT_AD714X is not set
858# CONFIG_INPUT_ATI_REMOTE is not set 915# CONFIG_INPUT_ATI_REMOTE is not set
859# CONFIG_INPUT_ATI_REMOTE2 is not set 916# CONFIG_INPUT_ATI_REMOTE2 is not set
860# CONFIG_INPUT_KEYSPAN_REMOTE is not set 917# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@@ -862,11 +919,10 @@ CONFIG_INPUT_MISC=y
862# CONFIG_INPUT_YEALINK is not set 919# CONFIG_INPUT_YEALINK is not set
863# CONFIG_INPUT_CM109 is not set 920# CONFIG_INPUT_CM109 is not set
864# CONFIG_INPUT_UINPUT is not set 921# CONFIG_INPUT_UINPUT is not set
922# CONFIG_INPUT_PCF8574 is not set
865# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 923# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
866# CONFIG_INPUT_BFIN_ROTARY is not set 924# CONFIG_INPUT_BFIN_ROTARY is not set
867# CONFIG_INPUT_AD714X is not set
868# CONFIG_INPUT_ADXL34X is not set 925# CONFIG_INPUT_ADXL34X is not set
869# CONFIG_INPUT_PCF8574 is not set
870 926
871# 927#
872# Hardware I/O ports 928# Hardware I/O ports
@@ -912,6 +968,7 @@ CONFIG_SERIAL_BFIN_UART1=y
912CONFIG_SERIAL_CORE=y 968CONFIG_SERIAL_CORE=y
913CONFIG_SERIAL_CORE_CONSOLE=y 969CONFIG_SERIAL_CORE_CONSOLE=y
914# CONFIG_SERIAL_BFIN_SPORT is not set 970# CONFIG_SERIAL_BFIN_SPORT is not set
971# CONFIG_SERIAL_TIMBERDALE is not set
915CONFIG_UNIX98_PTYS=y 972CONFIG_UNIX98_PTYS=y
916# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 973# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
917# CONFIG_LEGACY_PTYS is not set 974# CONFIG_LEGACY_PTYS is not set
@@ -940,6 +997,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
940# CONFIG_I2C_GPIO is not set 997# CONFIG_I2C_GPIO is not set
941# CONFIG_I2C_OCORES is not set 998# CONFIG_I2C_OCORES is not set
942# CONFIG_I2C_SIMTEC is not set 999# CONFIG_I2C_SIMTEC is not set
1000# CONFIG_I2C_XILINX is not set
943 1001
944# 1002#
945# External I2C/SMBus adapter drivers 1003# External I2C/SMBus adapter drivers
@@ -953,16 +1011,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
953# 1011#
954# CONFIG_I2C_PCA_PLATFORM is not set 1012# CONFIG_I2C_PCA_PLATFORM is not set
955# CONFIG_I2C_STUB is not set 1013# CONFIG_I2C_STUB is not set
956
957#
958# Miscellaneous I2C Chip support
959#
960# CONFIG_DS1682 is not set
961# CONFIG_SENSORS_TSL2550 is not set
962# CONFIG_I2C_DEBUG_CORE is not set 1014# CONFIG_I2C_DEBUG_CORE is not set
963# CONFIG_I2C_DEBUG_ALGO is not set 1015# CONFIG_I2C_DEBUG_ALGO is not set
964# CONFIG_I2C_DEBUG_BUS is not set 1016# CONFIG_I2C_DEBUG_BUS is not set
965# CONFIG_I2C_DEBUG_CHIP is not set
966CONFIG_SPI=y 1017CONFIG_SPI=y
967# CONFIG_SPI_DEBUG is not set 1018# CONFIG_SPI_DEBUG is not set
968CONFIG_SPI_MASTER=y 1019CONFIG_SPI_MASTER=y
@@ -975,6 +1026,8 @@ CONFIG_SPI_BFIN=y
975# CONFIG_SPI_BFIN_SPORT is not set 1026# CONFIG_SPI_BFIN_SPORT is not set
976# CONFIG_SPI_BITBANG is not set 1027# CONFIG_SPI_BITBANG is not set
977# CONFIG_SPI_GPIO is not set 1028# CONFIG_SPI_GPIO is not set
1029# CONFIG_SPI_XILINX is not set
1030# CONFIG_SPI_DESIGNWARE is not set
978 1031
979# 1032#
980# SPI Protocol Masters 1033# SPI Protocol Masters
@@ -994,10 +1047,12 @@ CONFIG_GPIO_SYSFS=y
994# 1047#
995# Memory mapped GPIO expanders: 1048# Memory mapped GPIO expanders:
996# 1049#
1050# CONFIG_GPIO_IT8761E is not set
997 1051
998# 1052#
999# I2C GPIO expanders: 1053# I2C GPIO expanders:
1000# 1054#
1055# CONFIG_GPIO_MAX7300 is not set
1001# CONFIG_GPIO_MAX732X is not set 1056# CONFIG_GPIO_MAX732X is not set
1002# CONFIG_GPIO_PCA953X is not set 1057# CONFIG_GPIO_PCA953X is not set
1003# CONFIG_GPIO_PCF857X is not set 1058# CONFIG_GPIO_PCF857X is not set
@@ -1046,21 +1101,26 @@ CONFIG_SSB_POSSIBLE=y
1046# Multifunction device drivers 1101# Multifunction device drivers
1047# 1102#
1048# CONFIG_MFD_CORE is not set 1103# CONFIG_MFD_CORE is not set
1104# CONFIG_MFD_88PM860X is not set
1049# CONFIG_MFD_SM501 is not set 1105# CONFIG_MFD_SM501 is not set
1050# CONFIG_HTC_PASIC3 is not set 1106# CONFIG_HTC_PASIC3 is not set
1107# CONFIG_HTC_I2CPLD is not set
1051# CONFIG_UCB1400_CORE is not set 1108# CONFIG_UCB1400_CORE is not set
1052# CONFIG_TPS65010 is not set 1109# CONFIG_TPS65010 is not set
1053# CONFIG_TWL4030_CORE is not set 1110# CONFIG_TWL4030_CORE is not set
1054# CONFIG_MFD_TMIO is not set 1111# CONFIG_MFD_TMIO is not set
1055# CONFIG_PMIC_DA903X is not set 1112# CONFIG_PMIC_DA903X is not set
1056CONFIG_PMIC_ADP5520=y 1113CONFIG_PMIC_ADP5520=y
1114# CONFIG_MFD_MAX8925 is not set
1057# CONFIG_MFD_WM8400 is not set 1115# CONFIG_MFD_WM8400 is not set
1058# CONFIG_MFD_WM831X is not set 1116# CONFIG_MFD_WM831X is not set
1059# CONFIG_MFD_WM8350_I2C is not set 1117# CONFIG_MFD_WM8350_I2C is not set
1118# CONFIG_MFD_WM8994 is not set
1060# CONFIG_MFD_PCF50633 is not set 1119# CONFIG_MFD_PCF50633 is not set
1061# CONFIG_MFD_MC13783 is not set 1120# CONFIG_MFD_MC13783 is not set
1062# CONFIG_AB3100_CORE is not set 1121# CONFIG_AB3100_CORE is not set
1063# CONFIG_EZX_PCAP is not set 1122# CONFIG_EZX_PCAP is not set
1123# CONFIG_AB4500_CORE is not set
1064# CONFIG_REGULATOR is not set 1124# CONFIG_REGULATOR is not set
1065# CONFIG_MEDIA_SUPPORT is not set 1125# CONFIG_MEDIA_SUPPORT is not set
1066 1126
@@ -1101,6 +1161,7 @@ CONFIG_FB_BFIN_LQ035Q1=y
1101# CONFIG_FB_BROADSHEET is not set 1161# CONFIG_FB_BROADSHEET is not set
1102CONFIG_BACKLIGHT_LCD_SUPPORT=y 1162CONFIG_BACKLIGHT_LCD_SUPPORT=y
1103CONFIG_LCD_CLASS_DEVICE=m 1163CONFIG_LCD_CLASS_DEVICE=m
1164# CONFIG_LCD_L4F00242T03 is not set
1104# CONFIG_LCD_LMS283GF05 is not set 1165# CONFIG_LCD_LMS283GF05 is not set
1105# CONFIG_LCD_LTV350QV is not set 1166# CONFIG_LCD_LTV350QV is not set
1106# CONFIG_LCD_ILI9320 is not set 1167# CONFIG_LCD_ILI9320 is not set
@@ -1110,6 +1171,7 @@ CONFIG_LCD_CLASS_DEVICE=m
1110CONFIG_BACKLIGHT_CLASS_DEVICE=m 1171CONFIG_BACKLIGHT_CLASS_DEVICE=m
1111CONFIG_BACKLIGHT_GENERIC=m 1172CONFIG_BACKLIGHT_GENERIC=m
1112# CONFIG_BACKLIGHT_ADP5520 is not set 1173# CONFIG_BACKLIGHT_ADP5520 is not set
1174# CONFIG_BACKLIGHT_ADP8860 is not set
1113# CONFIG_BACKLIGHT_ADP8870 is not set 1175# CONFIG_BACKLIGHT_ADP8870 is not set
1114 1176
1115# 1177#
@@ -1158,13 +1220,9 @@ CONFIG_SND_DRIVERS=y
1158# CONFIG_SND_SERIAL_U16550 is not set 1220# CONFIG_SND_SERIAL_U16550 is not set
1159# CONFIG_SND_MPU401 is not set 1221# CONFIG_SND_MPU401 is not set
1160CONFIG_SND_SPI=y 1222CONFIG_SND_SPI=y
1161
1162#
1163# ALSA Blackfin devices
1164#
1165# CONFIG_SND_BFIN_AD73322 is not set
1166CONFIG_SND_USB=y 1223CONFIG_SND_USB=y
1167# CONFIG_SND_USB_AUDIO is not set 1224# CONFIG_SND_USB_AUDIO is not set
1225# CONFIG_SND_USB_UA101 is not set
1168# CONFIG_SND_USB_CAIAQ is not set 1226# CONFIG_SND_USB_CAIAQ is not set
1169CONFIG_SND_SOC=m 1227CONFIG_SND_SOC=m
1170CONFIG_SND_SOC_AC97_BUS=y 1228CONFIG_SND_SOC_AC97_BUS=y
@@ -1173,6 +1231,10 @@ CONFIG_SND_BF5XX_SOC_SSM2602=m
1173# CONFIG_SND_BF5XX_SOC_AD73311 is not set 1231# CONFIG_SND_BF5XX_SOC_AD73311 is not set
1174# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set 1232# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
1175# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set 1233# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
1234# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
1235# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
1236# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
1237# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
1176# CONFIG_SND_BF5XX_TDM is not set 1238# CONFIG_SND_BF5XX_TDM is not set
1177CONFIG_SND_BF5XX_AC97=m 1239CONFIG_SND_BF5XX_AC97=m
1178CONFIG_SND_BF5XX_MMAP_SUPPORT=y 1240CONFIG_SND_BF5XX_MMAP_SUPPORT=y
@@ -1203,6 +1265,7 @@ CONFIG_USB_HID=y
1203# 1265#
1204# Special HID drivers 1266# Special HID drivers
1205# 1267#
1268# CONFIG_HID_3M_PCT is not set
1206CONFIG_HID_A4TECH=y 1269CONFIG_HID_A4TECH=y
1207CONFIG_HID_APPLE=y 1270CONFIG_HID_APPLE=y
1208CONFIG_HID_BELKIN=y 1271CONFIG_HID_BELKIN=y
@@ -1218,14 +1281,19 @@ CONFIG_HID_GYRATION=y
1218CONFIG_HID_LOGITECH=y 1281CONFIG_HID_LOGITECH=y
1219# CONFIG_LOGITECH_FF is not set 1282# CONFIG_LOGITECH_FF is not set
1220# CONFIG_LOGIRUMBLEPAD2_FF is not set 1283# CONFIG_LOGIRUMBLEPAD2_FF is not set
1284# CONFIG_LOGIG940_FF is not set
1221CONFIG_HID_MICROSOFT=y 1285CONFIG_HID_MICROSOFT=y
1286# CONFIG_HID_MOSART is not set
1222CONFIG_HID_MONTEREY=y 1287CONFIG_HID_MONTEREY=y
1223# CONFIG_HID_NTRIG is not set 1288# CONFIG_HID_NTRIG is not set
1289# CONFIG_HID_ORTEK is not set
1224CONFIG_HID_PANTHERLORD=y 1290CONFIG_HID_PANTHERLORD=y
1225# CONFIG_PANTHERLORD_FF is not set 1291# CONFIG_PANTHERLORD_FF is not set
1226CONFIG_HID_PETALYNX=y 1292CONFIG_HID_PETALYNX=y
1293# CONFIG_HID_QUANTA is not set
1227CONFIG_HID_SAMSUNG=y 1294CONFIG_HID_SAMSUNG=y
1228CONFIG_HID_SONY=y 1295CONFIG_HID_SONY=y
1296# CONFIG_HID_STANTUM is not set
1229CONFIG_HID_SUNPLUS=y 1297CONFIG_HID_SUNPLUS=y
1230# CONFIG_HID_GREENASIA is not set 1298# CONFIG_HID_GREENASIA is not set
1231# CONFIG_HID_SMARTJOYPLUS is not set 1299# CONFIG_HID_SMARTJOYPLUS is not set
@@ -1246,7 +1314,6 @@ CONFIG_USB=y
1246CONFIG_USB_DEVICEFS=y 1314CONFIG_USB_DEVICEFS=y
1247# CONFIG_USB_DEVICE_CLASS is not set 1315# CONFIG_USB_DEVICE_CLASS is not set
1248# CONFIG_USB_DYNAMIC_MINORS is not set 1316# CONFIG_USB_DYNAMIC_MINORS is not set
1249# CONFIG_USB_OTG is not set
1250# CONFIG_USB_OTG_WHITELIST is not set 1317# CONFIG_USB_OTG_WHITELIST is not set
1251CONFIG_USB_OTG_BLACKLIST_HUB=y 1318CONFIG_USB_OTG_BLACKLIST_HUB=y
1252CONFIG_USB_MON=y 1319CONFIG_USB_MON=y
@@ -1330,7 +1397,6 @@ CONFIG_USB_STORAGE=y
1330# CONFIG_USB_RIO500 is not set 1397# CONFIG_USB_RIO500 is not set
1331# CONFIG_USB_LEGOTOWER is not set 1398# CONFIG_USB_LEGOTOWER is not set
1332# CONFIG_USB_LCD is not set 1399# CONFIG_USB_LCD is not set
1333# CONFIG_USB_BERRY_CHARGE is not set
1334# CONFIG_USB_LED is not set 1400# CONFIG_USB_LED is not set
1335# CONFIG_USB_CYPRESS_CY7C63 is not set 1401# CONFIG_USB_CYPRESS_CY7C63 is not set
1336# CONFIG_USB_CYTHERM is not set 1402# CONFIG_USB_CYTHERM is not set
@@ -1343,7 +1409,6 @@ CONFIG_USB_STORAGE=y
1343# CONFIG_USB_IOWARRIOR is not set 1409# CONFIG_USB_IOWARRIOR is not set
1344# CONFIG_USB_TEST is not set 1410# CONFIG_USB_TEST is not set
1345# CONFIG_USB_ISIGHTFW is not set 1411# CONFIG_USB_ISIGHTFW is not set
1346# CONFIG_USB_VST is not set
1347# CONFIG_USB_GADGET is not set 1412# CONFIG_USB_GADGET is not set
1348 1413
1349# 1414#
@@ -1366,11 +1431,8 @@ CONFIG_LEDS_CLASS=y
1366# CONFIG_LEDS_PCA955X is not set 1431# CONFIG_LEDS_PCA955X is not set
1367# CONFIG_LEDS_DAC124S085 is not set 1432# CONFIG_LEDS_DAC124S085 is not set
1368# CONFIG_LEDS_BD2802 is not set 1433# CONFIG_LEDS_BD2802 is not set
1434# CONFIG_LEDS_LT3593 is not set
1369CONFIG_LEDS_ADP5520=y 1435CONFIG_LEDS_ADP5520=y
1370
1371#
1372# LED Triggers
1373#
1374# CONFIG_LEDS_TRIGGERS is not set 1436# CONFIG_LEDS_TRIGGERS is not set
1375# CONFIG_ACCESSIBILITY is not set 1437# CONFIG_ACCESSIBILITY is not set
1376CONFIG_RTC_LIB=y 1438CONFIG_RTC_LIB=y
@@ -1401,6 +1463,7 @@ CONFIG_RTC_INTF_DEV=y
1401# CONFIG_RTC_DRV_PCF8563 is not set 1463# CONFIG_RTC_DRV_PCF8563 is not set
1402# CONFIG_RTC_DRV_PCF8583 is not set 1464# CONFIG_RTC_DRV_PCF8583 is not set
1403# CONFIG_RTC_DRV_M41T80 is not set 1465# CONFIG_RTC_DRV_M41T80 is not set
1466# CONFIG_RTC_DRV_BQ32K is not set
1404# CONFIG_RTC_DRV_S35390A is not set 1467# CONFIG_RTC_DRV_S35390A is not set
1405# CONFIG_RTC_DRV_FM3130 is not set 1468# CONFIG_RTC_DRV_FM3130 is not set
1406# CONFIG_RTC_DRV_RX8581 is not set 1469# CONFIG_RTC_DRV_RX8581 is not set
@@ -1429,7 +1492,9 @@ CONFIG_RTC_INTF_DEV=y
1429# CONFIG_RTC_DRV_M48T86 is not set 1492# CONFIG_RTC_DRV_M48T86 is not set
1430# CONFIG_RTC_DRV_M48T35 is not set 1493# CONFIG_RTC_DRV_M48T35 is not set
1431# CONFIG_RTC_DRV_M48T59 is not set 1494# CONFIG_RTC_DRV_M48T59 is not set
1495# CONFIG_RTC_DRV_MSM6242 is not set
1432# CONFIG_RTC_DRV_BQ4802 is not set 1496# CONFIG_RTC_DRV_BQ4802 is not set
1497# CONFIG_RTC_DRV_RP5C01 is not set
1433# CONFIG_RTC_DRV_V3020 is not set 1498# CONFIG_RTC_DRV_V3020 is not set
1434 1499
1435# 1500#
@@ -1462,7 +1527,6 @@ CONFIG_EXT2_FS=m
1462# CONFIG_JFS_FS is not set 1527# CONFIG_JFS_FS is not set
1463# CONFIG_FS_POSIX_ACL is not set 1528# CONFIG_FS_POSIX_ACL is not set
1464# CONFIG_XFS_FS is not set 1529# CONFIG_XFS_FS is not set
1465# CONFIG_GFS2_FS is not set
1466# CONFIG_OCFS2_FS is not set 1530# CONFIG_OCFS2_FS is not set
1467# CONFIG_BTRFS_FS is not set 1531# CONFIG_BTRFS_FS is not set
1468# CONFIG_NILFS2_FS is not set 1532# CONFIG_NILFS2_FS is not set
@@ -1527,6 +1591,7 @@ CONFIG_JFFS2_ZLIB=y
1527# CONFIG_JFFS2_LZO is not set 1591# CONFIG_JFFS2_LZO is not set
1528CONFIG_JFFS2_RTIME=y 1592CONFIG_JFFS2_RTIME=y
1529# CONFIG_JFFS2_RUBIN is not set 1593# CONFIG_JFFS2_RUBIN is not set
1594# CONFIG_LOGFS is not set
1530# CONFIG_CRAMFS is not set 1595# CONFIG_CRAMFS is not set
1531# CONFIG_SQUASHFS is not set 1596# CONFIG_SQUASHFS is not set
1532# CONFIG_VXFS_FS is not set 1597# CONFIG_VXFS_FS is not set
@@ -1551,6 +1616,7 @@ CONFIG_SUNRPC=m
1551# CONFIG_RPCSEC_GSS_SPKM3 is not set 1616# CONFIG_RPCSEC_GSS_SPKM3 is not set
1552CONFIG_SMB_FS=m 1617CONFIG_SMB_FS=m
1553# CONFIG_SMB_NLS_DEFAULT is not set 1618# CONFIG_SMB_NLS_DEFAULT is not set
1619# CONFIG_CEPH_FS is not set
1554# CONFIG_CIFS is not set 1620# CONFIG_CIFS is not set
1555# CONFIG_NCP_FS is not set 1621# CONFIG_NCP_FS is not set
1556# CONFIG_CODA_FS is not set 1622# CONFIG_CODA_FS is not set
@@ -1629,6 +1695,8 @@ CONFIG_SCHED_DEBUG=y
1629# CONFIG_TIMER_STATS is not set 1695# CONFIG_TIMER_STATS is not set
1630# CONFIG_DEBUG_OBJECTS is not set 1696# CONFIG_DEBUG_OBJECTS is not set
1631# CONFIG_DEBUG_SLAB is not set 1697# CONFIG_DEBUG_SLAB is not set
1698# CONFIG_DEBUG_RT_MUTEXES is not set
1699# CONFIG_RT_MUTEX_TESTER is not set
1632# CONFIG_DEBUG_SPINLOCK is not set 1700# CONFIG_DEBUG_SPINLOCK is not set
1633# CONFIG_DEBUG_MUTEXES is not set 1701# CONFIG_DEBUG_MUTEXES is not set
1634# CONFIG_DEBUG_LOCK_ALLOC is not set 1702# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1652,17 +1720,18 @@ CONFIG_DEBUG_INFO=y
1652# CONFIG_RCU_TORTURE_TEST is not set 1720# CONFIG_RCU_TORTURE_TEST is not set
1653# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1721# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1654# CONFIG_BACKTRACE_SELF_TEST is not set 1722# CONFIG_BACKTRACE_SELF_TEST is not set
1723# CONFIG_TRACEHOOK_SELF_TEST is not set
1655# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1724# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1656# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1725# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1726# CONFIG_LKDTM is not set
1657# CONFIG_FAULT_INJECTION is not set 1727# CONFIG_FAULT_INJECTION is not set
1728# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1658# CONFIG_PAGE_POISONING is not set 1729# CONFIG_PAGE_POISONING is not set
1659CONFIG_HAVE_FUNCTION_TRACER=y 1730CONFIG_HAVE_FUNCTION_TRACER=y
1660CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1731CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1732CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1661CONFIG_TRACING_SUPPORT=y 1733CONFIG_TRACING_SUPPORT=y
1662# CONFIG_FTRACE is not set 1734# CONFIG_FTRACE is not set
1663# CONFIG_BRANCH_PROFILE_NONE is not set
1664# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1665# CONFIG_PROFILE_ALL_BRANCHES is not set
1666# CONFIG_DYNAMIC_DEBUG is not set 1735# CONFIG_DYNAMIC_DEBUG is not set
1667# CONFIG_SAMPLES is not set 1736# CONFIG_SAMPLES is not set
1668CONFIG_HAVE_ARCH_KGDB=y 1737CONFIG_HAVE_ARCH_KGDB=y
@@ -1689,6 +1758,7 @@ CONFIG_EARLY_PRINTK=y
1689CONFIG_CPLB_INFO=y 1758CONFIG_CPLB_INFO=y
1690CONFIG_ACCESS_CHECK=y 1759CONFIG_ACCESS_CHECK=y
1691# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1760# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1761# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1692 1762
1693# 1763#
1694# Security options 1764# Security options
@@ -1698,9 +1768,12 @@ CONFIG_SECURITY=y
1698# CONFIG_SECURITYFS is not set 1768# CONFIG_SECURITYFS is not set
1699# CONFIG_SECURITY_NETWORK is not set 1769# CONFIG_SECURITY_NETWORK is not set
1700# CONFIG_SECURITY_PATH is not set 1770# CONFIG_SECURITY_PATH is not set
1701# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1702# CONFIG_SECURITY_ROOTPLUG is not set
1703# CONFIG_SECURITY_TOMOYO is not set 1771# CONFIG_SECURITY_TOMOYO is not set
1772# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1773# CONFIG_DEFAULT_SECURITY_SMACK is not set
1774# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1775CONFIG_DEFAULT_SECURITY_DAC=y
1776CONFIG_DEFAULT_SECURITY=""
1704CONFIG_CRYPTO=y 1777CONFIG_CRYPTO=y
1705 1778
1706# 1779#
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index edbb44d26bbf..0de212e1e9bb 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 109# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 113CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 114CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 115# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +126,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 126# IO Schedulers
123# 127#
124CONFIG_IOSCHED_NOOP=y 128CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y 130CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 131# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 132CONFIG_DEFAULT_CFQ=y
131# CONFIG_DEFAULT_NOOP is not set 133# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 134CONFIG_DEFAULT_IOSCHED="cfq"
135# CONFIG_INLINE_SPIN_TRYLOCK is not set
136# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
137# CONFIG_INLINE_SPIN_LOCK is not set
138# CONFIG_INLINE_SPIN_LOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
141CONFIG_INLINE_SPIN_UNLOCK=y
142# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
143CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
144# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
145# CONFIG_INLINE_READ_TRYLOCK is not set
146# CONFIG_INLINE_READ_LOCK is not set
147# CONFIG_INLINE_READ_LOCK_BH is not set
148# CONFIG_INLINE_READ_LOCK_IRQ is not set
149# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
150CONFIG_INLINE_READ_UNLOCK=y
151# CONFIG_INLINE_READ_UNLOCK_BH is not set
152CONFIG_INLINE_READ_UNLOCK_IRQ=y
153# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
154# CONFIG_INLINE_WRITE_TRYLOCK is not set
155# CONFIG_INLINE_WRITE_LOCK is not set
156# CONFIG_INLINE_WRITE_LOCK_BH is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
159CONFIG_INLINE_WRITE_UNLOCK=y
160# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
161CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
162# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
163# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 164# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 165CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
@@ -232,6 +263,7 @@ CONFIG_BFIN527_EZKIT=y
232# CONFIG_BFIN527_EZKIT_V2 is not set 263# CONFIG_BFIN527_EZKIT_V2 is not set
233# CONFIG_BFIN527_BLUETECHNIX_CM is not set 264# CONFIG_BFIN527_BLUETECHNIX_CM is not set
234# CONFIG_BFIN526_EZBRD is not set 265# CONFIG_BFIN526_EZBRD is not set
266# CONFIG_BFIN527_AD7160EVAL is not set
235 267
236# 268#
237# BF527 Specific Configuration 269# BF527 Specific Configuration
@@ -294,8 +326,16 @@ CONFIG_HZ=250
294# CONFIG_SCHED_HRTICK is not set 326# CONFIG_SCHED_HRTICK is not set
295CONFIG_GENERIC_TIME=y 327CONFIG_GENERIC_TIME=y
296CONFIG_GENERIC_CLOCKEVENTS=y 328CONFIG_GENERIC_CLOCKEVENTS=y
329
330#
331# Clock event device
332#
297# CONFIG_TICKSOURCE_GPTMR0 is not set 333# CONFIG_TICKSOURCE_GPTMR0 is not set
298CONFIG_TICKSOURCE_CORETMR=y 334CONFIG_TICKSOURCE_CORETMR=y
335
336#
337# Clock souce
338#
299# CONFIG_CYCLES_CLOCKSOURCE is not set 339# CONFIG_CYCLES_CLOCKSOURCE is not set
300# CONFIG_GPTMR0_CLOCKSOURCE is not set 340# CONFIG_GPTMR0_CLOCKSOURCE is not set
301# CONFIG_NO_HZ is not set 341# CONFIG_NO_HZ is not set
@@ -326,12 +366,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
326CONFIG_ACCESS_OK_L1=y 366CONFIG_ACCESS_OK_L1=y
327# CONFIG_MEMSET_L1 is not set 367# CONFIG_MEMSET_L1 is not set
328# CONFIG_MEMCPY_L1 is not set 368# CONFIG_MEMCPY_L1 is not set
369CONFIG_STRCMP_L1=y
370CONFIG_STRNCMP_L1=y
371CONFIG_STRCPY_L1=y
372CONFIG_STRNCPY_L1=y
329# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set 373# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
330# CONFIG_IP_CHECKSUM_L1 is not set 374# CONFIG_IP_CHECKSUM_L1 is not set
331CONFIG_CACHELINE_ALIGNED_L1=y 375CONFIG_CACHELINE_ALIGNED_L1=y
332# CONFIG_SYSCALL_TAB_L1 is not set 376# CONFIG_SYSCALL_TAB_L1 is not set
333# CONFIG_CPLB_SWITCH_TAB_L1 is not set 377# CONFIG_CPLB_SWITCH_TAB_L1 is not set
334CONFIG_APP_STACK_L1=y 378CONFIG_CACHE_FLUSH_L1=y
335 379
336# 380#
337# Speed Optimizations 381# Speed Optimizations
@@ -431,7 +475,6 @@ CONFIG_NET=y
431# Networking options 475# Networking options
432# 476#
433CONFIG_PACKET=y 477CONFIG_PACKET=y
434# CONFIG_PACKET_MMAP is not set
435CONFIG_UNIX=y 478CONFIG_UNIX=y
436# CONFIG_NET_KEY is not set 479# CONFIG_NET_KEY is not set
437CONFIG_INET=y 480CONFIG_INET=y
@@ -654,6 +697,10 @@ CONFIG_MTD_NAND_IDS=m
654CONFIG_BLK_DEV=y 697CONFIG_BLK_DEV=y
655# CONFIG_BLK_DEV_COW_COMMON is not set 698# CONFIG_BLK_DEV_COW_COMMON is not set
656# CONFIG_BLK_DEV_LOOP is not set 699# CONFIG_BLK_DEV_LOOP is not set
700
701#
702# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
703#
657# CONFIG_BLK_DEV_NBD is not set 704# CONFIG_BLK_DEV_NBD is not set
658# CONFIG_BLK_DEV_UB is not set 705# CONFIG_BLK_DEV_UB is not set
659CONFIG_BLK_DEV_RAM=y 706CONFIG_BLK_DEV_RAM=y
@@ -668,6 +715,9 @@ CONFIG_MISC_DEVICES=y
668# CONFIG_ICS932S401 is not set 715# CONFIG_ICS932S401 is not set
669# CONFIG_ENCLOSURE_SERVICES is not set 716# CONFIG_ENCLOSURE_SERVICES is not set
670# CONFIG_ISL29003 is not set 717# CONFIG_ISL29003 is not set
718# CONFIG_SENSORS_TSL2550 is not set
719# CONFIG_DS1682 is not set
720# CONFIG_TI_DAC7512 is not set
671# CONFIG_C2PORT is not set 721# CONFIG_C2PORT is not set
672 722
673# 723#
@@ -684,6 +734,7 @@ CONFIG_HAVE_IDE=y
684# 734#
685# SCSI device support 735# SCSI device support
686# 736#
737CONFIG_SCSI_MOD=y
687# CONFIG_RAID_ATTRS is not set 738# CONFIG_RAID_ATTRS is not set
688CONFIG_SCSI=y 739CONFIG_SCSI=y
689CONFIG_SCSI_DMA=y 740CONFIG_SCSI_DMA=y
@@ -745,6 +796,7 @@ CONFIG_PHYLIB=y
745# CONFIG_NATIONAL_PHY is not set 796# CONFIG_NATIONAL_PHY is not set
746# CONFIG_STE10XP is not set 797# CONFIG_STE10XP is not set
747# CONFIG_LSI_ET1011C_PHY is not set 798# CONFIG_LSI_ET1011C_PHY is not set
799# CONFIG_MICREL_PHY is not set
748# CONFIG_FIXED_PHY is not set 800# CONFIG_FIXED_PHY is not set
749# CONFIG_MDIO_BITBANG is not set 801# CONFIG_MDIO_BITBANG is not set
750CONFIG_NET_ETHERNET=y 802CONFIG_NET_ETHERNET=y
@@ -753,7 +805,6 @@ CONFIG_BFIN_MAC=y
753CONFIG_BFIN_MAC_USE_L1=y 805CONFIG_BFIN_MAC_USE_L1=y
754CONFIG_BFIN_TX_DESC_NUM=10 806CONFIG_BFIN_TX_DESC_NUM=10
755CONFIG_BFIN_RX_DESC_NUM=20 807CONFIG_BFIN_RX_DESC_NUM=20
756CONFIG_BFIN_MAC_RMII=y
757# CONFIG_SMC91X is not set 808# CONFIG_SMC91X is not set
758# CONFIG_DM9000 is not set 809# CONFIG_DM9000 is not set
759# CONFIG_ENC28J60 is not set 810# CONFIG_ENC28J60 is not set
@@ -788,6 +839,7 @@ CONFIG_BFIN_MAC_RMII=y
788# CONFIG_USB_PEGASUS is not set 839# CONFIG_USB_PEGASUS is not set
789# CONFIG_USB_RTL8150 is not set 840# CONFIG_USB_RTL8150 is not set
790# CONFIG_USB_USBNET is not set 841# CONFIG_USB_USBNET is not set
842# CONFIG_USB_IPHETH is not set
791# CONFIG_WAN is not set 843# CONFIG_WAN is not set
792# CONFIG_PPP is not set 844# CONFIG_PPP is not set
793# CONFIG_SLIP is not set 845# CONFIG_SLIP is not set
@@ -803,6 +855,7 @@ CONFIG_BFIN_MAC_RMII=y
803CONFIG_INPUT=y 855CONFIG_INPUT=y
804CONFIG_INPUT_FF_MEMLESS=m 856CONFIG_INPUT_FF_MEMLESS=m
805# CONFIG_INPUT_POLLDEV is not set 857# CONFIG_INPUT_POLLDEV is not set
858# CONFIG_INPUT_SPARSEKMAP is not set
806 859
807# 860#
808# Userland interfaces 861# Userland interfaces
@@ -821,6 +874,7 @@ CONFIG_INPUT_FF_MEMLESS=m
821# CONFIG_INPUT_TABLET is not set 874# CONFIG_INPUT_TABLET is not set
822# CONFIG_INPUT_TOUCHSCREEN is not set 875# CONFIG_INPUT_TOUCHSCREEN is not set
823CONFIG_INPUT_MISC=y 876CONFIG_INPUT_MISC=y
877# CONFIG_INPUT_AD714X is not set
824# CONFIG_INPUT_ATI_REMOTE is not set 878# CONFIG_INPUT_ATI_REMOTE is not set
825# CONFIG_INPUT_ATI_REMOTE2 is not set 879# CONFIG_INPUT_ATI_REMOTE2 is not set
826# CONFIG_INPUT_KEYSPAN_REMOTE is not set 880# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@@ -828,11 +882,10 @@ CONFIG_INPUT_MISC=y
828# CONFIG_INPUT_YEALINK is not set 882# CONFIG_INPUT_YEALINK is not set
829# CONFIG_INPUT_CM109 is not set 883# CONFIG_INPUT_CM109 is not set
830# CONFIG_INPUT_UINPUT is not set 884# CONFIG_INPUT_UINPUT is not set
885# CONFIG_INPUT_PCF8574 is not set
831# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 886# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
832# CONFIG_INPUT_BFIN_ROTARY is not set 887# CONFIG_INPUT_BFIN_ROTARY is not set
833# CONFIG_INPUT_AD714X is not set
834# CONFIG_INPUT_ADXL34X is not set 888# CONFIG_INPUT_ADXL34X is not set
835# CONFIG_INPUT_PCF8574 is not set
836 889
837# 890#
838# Hardware I/O ports 891# Hardware I/O ports
@@ -878,6 +931,7 @@ CONFIG_SERIAL_BFIN_UART1=y
878CONFIG_SERIAL_CORE=y 931CONFIG_SERIAL_CORE=y
879CONFIG_SERIAL_CORE_CONSOLE=y 932CONFIG_SERIAL_CORE_CONSOLE=y
880# CONFIG_SERIAL_BFIN_SPORT is not set 933# CONFIG_SERIAL_BFIN_SPORT is not set
934# CONFIG_SERIAL_TIMBERDALE is not set
881CONFIG_UNIX98_PTYS=y 935CONFIG_UNIX98_PTYS=y
882# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 936# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
883# CONFIG_LEGACY_PTYS is not set 937# CONFIG_LEGACY_PTYS is not set
@@ -906,6 +960,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
906# CONFIG_I2C_GPIO is not set 960# CONFIG_I2C_GPIO is not set
907# CONFIG_I2C_OCORES is not set 961# CONFIG_I2C_OCORES is not set
908# CONFIG_I2C_SIMTEC is not set 962# CONFIG_I2C_SIMTEC is not set
963# CONFIG_I2C_XILINX is not set
909 964
910# 965#
911# External I2C/SMBus adapter drivers 966# External I2C/SMBus adapter drivers
@@ -919,16 +974,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
919# 974#
920# CONFIG_I2C_PCA_PLATFORM is not set 975# CONFIG_I2C_PCA_PLATFORM is not set
921# CONFIG_I2C_STUB is not set 976# CONFIG_I2C_STUB is not set
922
923#
924# Miscellaneous I2C Chip support
925#
926# CONFIG_DS1682 is not set
927# CONFIG_SENSORS_TSL2550 is not set
928# CONFIG_I2C_DEBUG_CORE is not set 977# CONFIG_I2C_DEBUG_CORE is not set
929# CONFIG_I2C_DEBUG_ALGO is not set 978# CONFIG_I2C_DEBUG_ALGO is not set
930# CONFIG_I2C_DEBUG_BUS is not set 979# CONFIG_I2C_DEBUG_BUS is not set
931# CONFIG_I2C_DEBUG_CHIP is not set
932CONFIG_SPI=y 980CONFIG_SPI=y
933# CONFIG_SPI_DEBUG is not set 981# CONFIG_SPI_DEBUG is not set
934CONFIG_SPI_MASTER=y 982CONFIG_SPI_MASTER=y
@@ -941,6 +989,8 @@ CONFIG_SPI_BFIN=y
941# CONFIG_SPI_BFIN_SPORT is not set 989# CONFIG_SPI_BFIN_SPORT is not set
942# CONFIG_SPI_BITBANG is not set 990# CONFIG_SPI_BITBANG is not set
943# CONFIG_SPI_GPIO is not set 991# CONFIG_SPI_GPIO is not set
992# CONFIG_SPI_XILINX is not set
993# CONFIG_SPI_DESIGNWARE is not set
944 994
945# 995#
946# SPI Protocol Masters 996# SPI Protocol Masters
@@ -960,10 +1010,12 @@ CONFIG_GPIO_SYSFS=y
960# 1010#
961# Memory mapped GPIO expanders: 1011# Memory mapped GPIO expanders:
962# 1012#
1013# CONFIG_GPIO_IT8761E is not set
963 1014
964# 1015#
965# I2C GPIO expanders: 1016# I2C GPIO expanders:
966# 1017#
1018# CONFIG_GPIO_MAX7300 is not set
967# CONFIG_GPIO_MAX732X is not set 1019# CONFIG_GPIO_MAX732X is not set
968# CONFIG_GPIO_PCA953X is not set 1020# CONFIG_GPIO_PCA953X is not set
969# CONFIG_GPIO_PCF857X is not set 1021# CONFIG_GPIO_PCF857X is not set
@@ -1011,21 +1063,26 @@ CONFIG_SSB_POSSIBLE=y
1011# Multifunction device drivers 1063# Multifunction device drivers
1012# 1064#
1013# CONFIG_MFD_CORE is not set 1065# CONFIG_MFD_CORE is not set
1066# CONFIG_MFD_88PM860X is not set
1014# CONFIG_MFD_SM501 is not set 1067# CONFIG_MFD_SM501 is not set
1015# CONFIG_HTC_PASIC3 is not set 1068# CONFIG_HTC_PASIC3 is not set
1069# CONFIG_HTC_I2CPLD is not set
1016# CONFIG_UCB1400_CORE is not set 1070# CONFIG_UCB1400_CORE is not set
1017# CONFIG_TPS65010 is not set 1071# CONFIG_TPS65010 is not set
1018# CONFIG_TWL4030_CORE is not set 1072# CONFIG_TWL4030_CORE is not set
1019# CONFIG_MFD_TMIO is not set 1073# CONFIG_MFD_TMIO is not set
1020# CONFIG_PMIC_DA903X is not set 1074# CONFIG_PMIC_DA903X is not set
1021# CONFIG_PMIC_ADP5520 is not set 1075# CONFIG_PMIC_ADP5520 is not set
1076# CONFIG_MFD_MAX8925 is not set
1022# CONFIG_MFD_WM8400 is not set 1077# CONFIG_MFD_WM8400 is not set
1023# CONFIG_MFD_WM831X is not set 1078# CONFIG_MFD_WM831X is not set
1024# CONFIG_MFD_WM8350_I2C is not set 1079# CONFIG_MFD_WM8350_I2C is not set
1080# CONFIG_MFD_WM8994 is not set
1025# CONFIG_MFD_PCF50633 is not set 1081# CONFIG_MFD_PCF50633 is not set
1026# CONFIG_MFD_MC13783 is not set 1082# CONFIG_MFD_MC13783 is not set
1027# CONFIG_AB3100_CORE is not set 1083# CONFIG_AB3100_CORE is not set
1028# CONFIG_EZX_PCAP is not set 1084# CONFIG_EZX_PCAP is not set
1085# CONFIG_AB4500_CORE is not set
1029# CONFIG_REGULATOR is not set 1086# CONFIG_REGULATOR is not set
1030# CONFIG_MEDIA_SUPPORT is not set 1087# CONFIG_MEDIA_SUPPORT is not set
1031 1088
@@ -1066,6 +1123,7 @@ CONFIG_FB_BFIN_T350MCQB=y
1066# CONFIG_FB_BROADSHEET is not set 1123# CONFIG_FB_BROADSHEET is not set
1067CONFIG_BACKLIGHT_LCD_SUPPORT=y 1124CONFIG_BACKLIGHT_LCD_SUPPORT=y
1068CONFIG_LCD_CLASS_DEVICE=m 1125CONFIG_LCD_CLASS_DEVICE=m
1126# CONFIG_LCD_L4F00242T03 is not set
1069# CONFIG_LCD_LMS283GF05 is not set 1127# CONFIG_LCD_LMS283GF05 is not set
1070CONFIG_LCD_LTV350QV=m 1128CONFIG_LCD_LTV350QV=m
1071# CONFIG_LCD_ILI9320 is not set 1129# CONFIG_LCD_ILI9320 is not set
@@ -1074,6 +1132,7 @@ CONFIG_LCD_LTV350QV=m
1074# CONFIG_LCD_PLATFORM is not set 1132# CONFIG_LCD_PLATFORM is not set
1075CONFIG_BACKLIGHT_CLASS_DEVICE=m 1133CONFIG_BACKLIGHT_CLASS_DEVICE=m
1076CONFIG_BACKLIGHT_GENERIC=m 1134CONFIG_BACKLIGHT_GENERIC=m
1135# CONFIG_BACKLIGHT_ADP8860 is not set
1077# CONFIG_BACKLIGHT_ADP8870 is not set 1136# CONFIG_BACKLIGHT_ADP8870 is not set
1078 1137
1079# 1138#
@@ -1122,13 +1181,9 @@ CONFIG_SND_DRIVERS=y
1122# CONFIG_SND_SERIAL_U16550 is not set 1181# CONFIG_SND_SERIAL_U16550 is not set
1123# CONFIG_SND_MPU401 is not set 1182# CONFIG_SND_MPU401 is not set
1124CONFIG_SND_SPI=y 1183CONFIG_SND_SPI=y
1125
1126#
1127# ALSA Blackfin devices
1128#
1129# CONFIG_SND_BFIN_AD73322 is not set
1130CONFIG_SND_USB=y 1184CONFIG_SND_USB=y
1131# CONFIG_SND_USB_AUDIO is not set 1185# CONFIG_SND_USB_AUDIO is not set
1186# CONFIG_SND_USB_UA101 is not set
1132# CONFIG_SND_USB_CAIAQ is not set 1187# CONFIG_SND_USB_CAIAQ is not set
1133CONFIG_SND_SOC=m 1188CONFIG_SND_SOC=m
1134CONFIG_SND_SOC_AC97_BUS=y 1189CONFIG_SND_SOC_AC97_BUS=y
@@ -1137,6 +1192,10 @@ CONFIG_SND_BF5XX_SOC_SSM2602=m
1137# CONFIG_SND_BF5XX_SOC_AD73311 is not set 1192# CONFIG_SND_BF5XX_SOC_AD73311 is not set
1138# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set 1193# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
1139# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set 1194# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
1195# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
1196# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
1197# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
1198# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
1140# CONFIG_SND_BF5XX_TDM is not set 1199# CONFIG_SND_BF5XX_TDM is not set
1141CONFIG_SND_BF5XX_AC97=m 1200CONFIG_SND_BF5XX_AC97=m
1142CONFIG_SND_BF5XX_MMAP_SUPPORT=y 1201CONFIG_SND_BF5XX_MMAP_SUPPORT=y
@@ -1167,6 +1226,7 @@ CONFIG_USB_HID=y
1167# 1226#
1168# Special HID drivers 1227# Special HID drivers
1169# 1228#
1229# CONFIG_HID_3M_PCT is not set
1170CONFIG_HID_A4TECH=y 1230CONFIG_HID_A4TECH=y
1171CONFIG_HID_APPLE=y 1231CONFIG_HID_APPLE=y
1172CONFIG_HID_BELKIN=y 1232CONFIG_HID_BELKIN=y
@@ -1182,14 +1242,19 @@ CONFIG_HID_GYRATION=y
1182CONFIG_HID_LOGITECH=y 1242CONFIG_HID_LOGITECH=y
1183# CONFIG_LOGITECH_FF is not set 1243# CONFIG_LOGITECH_FF is not set
1184# CONFIG_LOGIRUMBLEPAD2_FF is not set 1244# CONFIG_LOGIRUMBLEPAD2_FF is not set
1245# CONFIG_LOGIG940_FF is not set
1185CONFIG_HID_MICROSOFT=y 1246CONFIG_HID_MICROSOFT=y
1247# CONFIG_HID_MOSART is not set
1186CONFIG_HID_MONTEREY=y 1248CONFIG_HID_MONTEREY=y
1187# CONFIG_HID_NTRIG is not set 1249# CONFIG_HID_NTRIG is not set
1250# CONFIG_HID_ORTEK is not set
1188CONFIG_HID_PANTHERLORD=y 1251CONFIG_HID_PANTHERLORD=y
1189# CONFIG_PANTHERLORD_FF is not set 1252# CONFIG_PANTHERLORD_FF is not set
1190CONFIG_HID_PETALYNX=y 1253CONFIG_HID_PETALYNX=y
1254# CONFIG_HID_QUANTA is not set
1191CONFIG_HID_SAMSUNG=y 1255CONFIG_HID_SAMSUNG=y
1192CONFIG_HID_SONY=y 1256CONFIG_HID_SONY=y
1257# CONFIG_HID_STANTUM is not set
1193CONFIG_HID_SUNPLUS=y 1258CONFIG_HID_SUNPLUS=y
1194# CONFIG_HID_GREENASIA is not set 1259# CONFIG_HID_GREENASIA is not set
1195# CONFIG_HID_SMARTJOYPLUS is not set 1260# CONFIG_HID_SMARTJOYPLUS is not set
@@ -1210,7 +1275,6 @@ CONFIG_USB=y
1210CONFIG_USB_DEVICEFS=y 1275CONFIG_USB_DEVICEFS=y
1211# CONFIG_USB_DEVICE_CLASS is not set 1276# CONFIG_USB_DEVICE_CLASS is not set
1212# CONFIG_USB_DYNAMIC_MINORS is not set 1277# CONFIG_USB_DYNAMIC_MINORS is not set
1213# CONFIG_USB_OTG is not set
1214# CONFIG_USB_OTG_WHITELIST is not set 1278# CONFIG_USB_OTG_WHITELIST is not set
1215CONFIG_USB_OTG_BLACKLIST_HUB=y 1279CONFIG_USB_OTG_BLACKLIST_HUB=y
1216CONFIG_USB_MON=y 1280CONFIG_USB_MON=y
@@ -1292,7 +1356,6 @@ CONFIG_USB_STORAGE=y
1292# CONFIG_USB_RIO500 is not set 1356# CONFIG_USB_RIO500 is not set
1293# CONFIG_USB_LEGOTOWER is not set 1357# CONFIG_USB_LEGOTOWER is not set
1294# CONFIG_USB_LCD is not set 1358# CONFIG_USB_LCD is not set
1295# CONFIG_USB_BERRY_CHARGE is not set
1296# CONFIG_USB_LED is not set 1359# CONFIG_USB_LED is not set
1297# CONFIG_USB_CYPRESS_CY7C63 is not set 1360# CONFIG_USB_CYPRESS_CY7C63 is not set
1298# CONFIG_USB_CYTHERM is not set 1361# CONFIG_USB_CYTHERM is not set
@@ -1305,7 +1368,6 @@ CONFIG_USB_STORAGE=y
1305# CONFIG_USB_IOWARRIOR is not set 1368# CONFIG_USB_IOWARRIOR is not set
1306# CONFIG_USB_TEST is not set 1369# CONFIG_USB_TEST is not set
1307# CONFIG_USB_ISIGHTFW is not set 1370# CONFIG_USB_ISIGHTFW is not set
1308# CONFIG_USB_VST is not set
1309# CONFIG_USB_GADGET is not set 1371# CONFIG_USB_GADGET is not set
1310 1372
1311# 1373#
@@ -1346,6 +1408,7 @@ CONFIG_RTC_INTF_DEV=y
1346# CONFIG_RTC_DRV_PCF8563 is not set 1408# CONFIG_RTC_DRV_PCF8563 is not set
1347# CONFIG_RTC_DRV_PCF8583 is not set 1409# CONFIG_RTC_DRV_PCF8583 is not set
1348# CONFIG_RTC_DRV_M41T80 is not set 1410# CONFIG_RTC_DRV_M41T80 is not set
1411# CONFIG_RTC_DRV_BQ32K is not set
1349# CONFIG_RTC_DRV_S35390A is not set 1412# CONFIG_RTC_DRV_S35390A is not set
1350# CONFIG_RTC_DRV_FM3130 is not set 1413# CONFIG_RTC_DRV_FM3130 is not set
1351# CONFIG_RTC_DRV_RX8581 is not set 1414# CONFIG_RTC_DRV_RX8581 is not set
@@ -1374,7 +1437,9 @@ CONFIG_RTC_INTF_DEV=y
1374# CONFIG_RTC_DRV_M48T86 is not set 1437# CONFIG_RTC_DRV_M48T86 is not set
1375# CONFIG_RTC_DRV_M48T35 is not set 1438# CONFIG_RTC_DRV_M48T35 is not set
1376# CONFIG_RTC_DRV_M48T59 is not set 1439# CONFIG_RTC_DRV_M48T59 is not set
1440# CONFIG_RTC_DRV_MSM6242 is not set
1377# CONFIG_RTC_DRV_BQ4802 is not set 1441# CONFIG_RTC_DRV_BQ4802 is not set
1442# CONFIG_RTC_DRV_RP5C01 is not set
1378# CONFIG_RTC_DRV_V3020 is not set 1443# CONFIG_RTC_DRV_V3020 is not set
1379 1444
1380# 1445#
@@ -1407,7 +1472,6 @@ CONFIG_EXT2_FS=m
1407# CONFIG_JFS_FS is not set 1472# CONFIG_JFS_FS is not set
1408# CONFIG_FS_POSIX_ACL is not set 1473# CONFIG_FS_POSIX_ACL is not set
1409# CONFIG_XFS_FS is not set 1474# CONFIG_XFS_FS is not set
1410# CONFIG_GFS2_FS is not set
1411# CONFIG_OCFS2_FS is not set 1475# CONFIG_OCFS2_FS is not set
1412# CONFIG_BTRFS_FS is not set 1476# CONFIG_BTRFS_FS is not set
1413# CONFIG_NILFS2_FS is not set 1477# CONFIG_NILFS2_FS is not set
@@ -1472,6 +1536,7 @@ CONFIG_JFFS2_ZLIB=y
1472# CONFIG_JFFS2_LZO is not set 1536# CONFIG_JFFS2_LZO is not set
1473CONFIG_JFFS2_RTIME=y 1537CONFIG_JFFS2_RTIME=y
1474# CONFIG_JFFS2_RUBIN is not set 1538# CONFIG_JFFS2_RUBIN is not set
1539# CONFIG_LOGFS is not set
1475# CONFIG_CRAMFS is not set 1540# CONFIG_CRAMFS is not set
1476# CONFIG_SQUASHFS is not set 1541# CONFIG_SQUASHFS is not set
1477# CONFIG_VXFS_FS is not set 1542# CONFIG_VXFS_FS is not set
@@ -1496,6 +1561,7 @@ CONFIG_SUNRPC=m
1496# CONFIG_RPCSEC_GSS_SPKM3 is not set 1561# CONFIG_RPCSEC_GSS_SPKM3 is not set
1497CONFIG_SMB_FS=m 1562CONFIG_SMB_FS=m
1498# CONFIG_SMB_NLS_DEFAULT is not set 1563# CONFIG_SMB_NLS_DEFAULT is not set
1564# CONFIG_CEPH_FS is not set
1499# CONFIG_CIFS is not set 1565# CONFIG_CIFS is not set
1500# CONFIG_NCP_FS is not set 1566# CONFIG_NCP_FS is not set
1501# CONFIG_CODA_FS is not set 1567# CONFIG_CODA_FS is not set
@@ -1574,6 +1640,8 @@ CONFIG_SCHED_DEBUG=y
1574# CONFIG_TIMER_STATS is not set 1640# CONFIG_TIMER_STATS is not set
1575# CONFIG_DEBUG_OBJECTS is not set 1641# CONFIG_DEBUG_OBJECTS is not set
1576# CONFIG_DEBUG_SLAB is not set 1642# CONFIG_DEBUG_SLAB is not set
1643# CONFIG_DEBUG_RT_MUTEXES is not set
1644# CONFIG_RT_MUTEX_TESTER is not set
1577# CONFIG_DEBUG_SPINLOCK is not set 1645# CONFIG_DEBUG_SPINLOCK is not set
1578# CONFIG_DEBUG_MUTEXES is not set 1646# CONFIG_DEBUG_MUTEXES is not set
1579# CONFIG_DEBUG_LOCK_ALLOC is not set 1647# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1597,17 +1665,18 @@ CONFIG_DEBUG_INFO=y
1597# CONFIG_RCU_TORTURE_TEST is not set 1665# CONFIG_RCU_TORTURE_TEST is not set
1598# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1666# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1599# CONFIG_BACKTRACE_SELF_TEST is not set 1667# CONFIG_BACKTRACE_SELF_TEST is not set
1668# CONFIG_TRACEHOOK_SELF_TEST is not set
1600# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1669# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1601# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1670# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1671# CONFIG_LKDTM is not set
1602# CONFIG_FAULT_INJECTION is not set 1672# CONFIG_FAULT_INJECTION is not set
1673# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1603# CONFIG_PAGE_POISONING is not set 1674# CONFIG_PAGE_POISONING is not set
1604CONFIG_HAVE_FUNCTION_TRACER=y 1675CONFIG_HAVE_FUNCTION_TRACER=y
1605CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1676CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1677CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1606CONFIG_TRACING_SUPPORT=y 1678CONFIG_TRACING_SUPPORT=y
1607# CONFIG_FTRACE is not set 1679# CONFIG_FTRACE is not set
1608# CONFIG_BRANCH_PROFILE_NONE is not set
1609# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1610# CONFIG_PROFILE_ALL_BRANCHES is not set
1611# CONFIG_DYNAMIC_DEBUG is not set 1680# CONFIG_DYNAMIC_DEBUG is not set
1612# CONFIG_SAMPLES is not set 1681# CONFIG_SAMPLES is not set
1613CONFIG_HAVE_ARCH_KGDB=y 1682CONFIG_HAVE_ARCH_KGDB=y
@@ -1634,6 +1703,7 @@ CONFIG_EARLY_PRINTK=y
1634CONFIG_CPLB_INFO=y 1703CONFIG_CPLB_INFO=y
1635CONFIG_ACCESS_CHECK=y 1704CONFIG_ACCESS_CHECK=y
1636# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1705# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1706# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1637 1707
1638# 1708#
1639# Security options 1709# Security options
@@ -1643,9 +1713,12 @@ CONFIG_SECURITY=y
1643# CONFIG_SECURITYFS is not set 1713# CONFIG_SECURITYFS is not set
1644# CONFIG_SECURITY_NETWORK is not set 1714# CONFIG_SECURITY_NETWORK is not set
1645# CONFIG_SECURITY_PATH is not set 1715# CONFIG_SECURITY_PATH is not set
1646# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1647# CONFIG_SECURITY_ROOTPLUG is not set
1648# CONFIG_SECURITY_TOMOYO is not set 1716# CONFIG_SECURITY_TOMOYO is not set
1717# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1718# CONFIG_DEFAULT_SECURITY_SMACK is not set
1719# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1720CONFIG_DEFAULT_SECURITY_DAC=y
1721CONFIG_DEFAULT_SECURITY=""
1649CONFIG_CRYPTO=y 1722CONFIG_CRYPTO=y
1650 1723
1651# 1724#
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 0b13d5836a48..f096012c8d9a 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -122,14 +125,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 125# IO Schedulers
123# 126#
124CONFIG_IOSCHED_NOOP=y 127CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 128# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y 129CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 130# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 131CONFIG_DEFAULT_CFQ=y
131# CONFIG_DEFAULT_NOOP is not set 132# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 133CONFIG_DEFAULT_IOSCHED="cfq"
134# CONFIG_INLINE_SPIN_TRYLOCK is not set
135# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
136# CONFIG_INLINE_SPIN_LOCK is not set
137# CONFIG_INLINE_SPIN_LOCK_BH is not set
138# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
140CONFIG_INLINE_SPIN_UNLOCK=y
141# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
142CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
143# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
144# CONFIG_INLINE_READ_TRYLOCK is not set
145# CONFIG_INLINE_READ_LOCK is not set
146# CONFIG_INLINE_READ_LOCK_BH is not set
147# CONFIG_INLINE_READ_LOCK_IRQ is not set
148# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
149CONFIG_INLINE_READ_UNLOCK=y
150# CONFIG_INLINE_READ_UNLOCK_BH is not set
151CONFIG_INLINE_READ_UNLOCK_IRQ=y
152# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
153# CONFIG_INLINE_WRITE_TRYLOCK is not set
154# CONFIG_INLINE_WRITE_LOCK is not set
155# CONFIG_INLINE_WRITE_LOCK_BH is not set
156# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
158CONFIG_INLINE_WRITE_UNLOCK=y
159# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
160CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
161# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
162# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 163# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 164CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 165# CONFIG_PREEMPT is not set
@@ -254,8 +284,16 @@ CONFIG_HZ=250
254CONFIG_SCHED_HRTICK=y 284CONFIG_SCHED_HRTICK=y
255CONFIG_GENERIC_TIME=y 285CONFIG_GENERIC_TIME=y
256CONFIG_GENERIC_CLOCKEVENTS=y 286CONFIG_GENERIC_CLOCKEVENTS=y
287
288#
289# Clock event device
290#
257# CONFIG_TICKSOURCE_GPTMR0 is not set 291# CONFIG_TICKSOURCE_GPTMR0 is not set
258CONFIG_TICKSOURCE_CORETMR=y 292CONFIG_TICKSOURCE_CORETMR=y
293
294#
295# Clock souce
296#
259CONFIG_CYCLES_CLOCKSOURCE=y 297CONFIG_CYCLES_CLOCKSOURCE=y
260# CONFIG_GPTMR0_CLOCKSOURCE is not set 298# CONFIG_GPTMR0_CLOCKSOURCE is not set
261CONFIG_TICK_ONESHOT=y 299CONFIG_TICK_ONESHOT=y
@@ -287,12 +325,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
287CONFIG_ACCESS_OK_L1=y 325CONFIG_ACCESS_OK_L1=y
288CONFIG_MEMSET_L1=y 326CONFIG_MEMSET_L1=y
289CONFIG_MEMCPY_L1=y 327CONFIG_MEMCPY_L1=y
328CONFIG_STRCMP_L1=y
329CONFIG_STRNCMP_L1=y
330CONFIG_STRCPY_L1=y
331CONFIG_STRNCPY_L1=y
290CONFIG_SYS_BFIN_SPINLOCK_L1=y 332CONFIG_SYS_BFIN_SPINLOCK_L1=y
291# CONFIG_IP_CHECKSUM_L1 is not set 333# CONFIG_IP_CHECKSUM_L1 is not set
292CONFIG_CACHELINE_ALIGNED_L1=y 334CONFIG_CACHELINE_ALIGNED_L1=y
293# CONFIG_SYSCALL_TAB_L1 is not set 335# CONFIG_SYSCALL_TAB_L1 is not set
294# CONFIG_CPLB_SWITCH_TAB_L1 is not set 336# CONFIG_CPLB_SWITCH_TAB_L1 is not set
295CONFIG_APP_STACK_L1=y 337CONFIG_CACHE_FLUSH_L1=y
296 338
297# 339#
298# Speed Optimizations 340# Speed Optimizations
@@ -385,10 +427,10 @@ CONFIG_PM_SLEEP=y
385CONFIG_SUSPEND=y 427CONFIG_SUSPEND=y
386CONFIG_SUSPEND_FREEZER=y 428CONFIG_SUSPEND_FREEZER=y
387# CONFIG_PM_RUNTIME is not set 429# CONFIG_PM_RUNTIME is not set
430CONFIG_PM_OPS=y
388CONFIG_ARCH_SUSPEND_POSSIBLE=y 431CONFIG_ARCH_SUSPEND_POSSIBLE=y
389CONFIG_PM_BFIN_SLEEP_DEEPER=y 432CONFIG_PM_BFIN_SLEEP_DEEPER=y
390# CONFIG_PM_BFIN_SLEEP is not set 433# CONFIG_PM_BFIN_SLEEP is not set
391# CONFIG_PM_WAKEUP_BY_GPIO is not set
392 434
393# 435#
394# Possible Suspend Mem / Hibernate Wake-Up Sources 436# Possible Suspend Mem / Hibernate Wake-Up Sources
@@ -404,7 +446,6 @@ CONFIG_NET=y
404# Networking options 446# Networking options
405# 447#
406CONFIG_PACKET=y 448CONFIG_PACKET=y
407# CONFIG_PACKET_MMAP is not set
408CONFIG_UNIX=y 449CONFIG_UNIX=y
409# CONFIG_NET_KEY is not set 450# CONFIG_NET_KEY is not set
410CONFIG_INET=y 451CONFIG_INET=y
@@ -608,6 +649,10 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
608CONFIG_BLK_DEV=y 649CONFIG_BLK_DEV=y
609# CONFIG_BLK_DEV_COW_COMMON is not set 650# CONFIG_BLK_DEV_COW_COMMON is not set
610# CONFIG_BLK_DEV_LOOP is not set 651# CONFIG_BLK_DEV_LOOP is not set
652
653#
654# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
655#
611# CONFIG_BLK_DEV_NBD is not set 656# CONFIG_BLK_DEV_NBD is not set
612CONFIG_BLK_DEV_RAM=y 657CONFIG_BLK_DEV_RAM=y
613CONFIG_BLK_DEV_RAM_COUNT=16 658CONFIG_BLK_DEV_RAM_COUNT=16
@@ -617,7 +662,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
617# CONFIG_ATA_OVER_ETH is not set 662# CONFIG_ATA_OVER_ETH is not set
618# CONFIG_BLK_DEV_HD is not set 663# CONFIG_BLK_DEV_HD is not set
619CONFIG_MISC_DEVICES=y 664CONFIG_MISC_DEVICES=y
665# CONFIG_AD525X_DPOT is not set
620# CONFIG_ENCLOSURE_SERVICES is not set 666# CONFIG_ENCLOSURE_SERVICES is not set
667# CONFIG_TI_DAC7512 is not set
621# CONFIG_C2PORT is not set 668# CONFIG_C2PORT is not set
622 669
623# 670#
@@ -631,6 +678,7 @@ CONFIG_HAVE_IDE=y
631# 678#
632# SCSI device support 679# SCSI device support
633# 680#
681CONFIG_SCSI_MOD=y
634# CONFIG_RAID_ATTRS is not set 682# CONFIG_RAID_ATTRS is not set
635# CONFIG_SCSI is not set 683# CONFIG_SCSI is not set
636# CONFIG_SCSI_DMA is not set 684# CONFIG_SCSI_DMA is not set
@@ -687,6 +735,7 @@ CONFIG_SMC91X=y
687CONFIG_INPUT=m 735CONFIG_INPUT=m
688# CONFIG_INPUT_FF_MEMLESS is not set 736# CONFIG_INPUT_FF_MEMLESS is not set
689# CONFIG_INPUT_POLLDEV is not set 737# CONFIG_INPUT_POLLDEV is not set
738# CONFIG_INPUT_SPARSEKMAP is not set
690 739
691# 740#
692# Userland interfaces 741# Userland interfaces
@@ -744,6 +793,7 @@ CONFIG_SERIAL_BFIN_UART0=y
744CONFIG_SERIAL_CORE=y 793CONFIG_SERIAL_CORE=y
745CONFIG_SERIAL_CORE_CONSOLE=y 794CONFIG_SERIAL_CORE_CONSOLE=y
746# CONFIG_SERIAL_BFIN_SPORT is not set 795# CONFIG_SERIAL_BFIN_SPORT is not set
796# CONFIG_SERIAL_TIMBERDALE is not set
747CONFIG_UNIX98_PTYS=y 797CONFIG_UNIX98_PTYS=y
748# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 798# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
749# CONFIG_LEGACY_PTYS is not set 799# CONFIG_LEGACY_PTYS is not set
@@ -765,6 +815,8 @@ CONFIG_SPI_BFIN=y
765# CONFIG_SPI_BFIN_SPORT is not set 815# CONFIG_SPI_BFIN_SPORT is not set
766# CONFIG_SPI_BITBANG is not set 816# CONFIG_SPI_BITBANG is not set
767# CONFIG_SPI_GPIO is not set 817# CONFIG_SPI_GPIO is not set
818# CONFIG_SPI_XILINX is not set
819# CONFIG_SPI_DESIGNWARE is not set
768 820
769# 821#
770# SPI Protocol Masters 822# SPI Protocol Masters
@@ -784,6 +836,7 @@ CONFIG_GPIO_SYSFS=y
784# 836#
785# Memory mapped GPIO expanders: 837# Memory mapped GPIO expanders:
786# 838#
839# CONFIG_GPIO_IT8761E is not set
787 840
788# 841#
789# I2C GPIO expanders: 842# I2C GPIO expanders:
@@ -831,6 +884,7 @@ CONFIG_SSB_POSSIBLE=y
831# CONFIG_MFD_TMIO is not set 884# CONFIG_MFD_TMIO is not set
832# CONFIG_MFD_MC13783 is not set 885# CONFIG_MFD_MC13783 is not set
833# CONFIG_EZX_PCAP is not set 886# CONFIG_EZX_PCAP is not set
887# CONFIG_AB4500_CORE is not set
834# CONFIG_REGULATOR is not set 888# CONFIG_REGULATOR is not set
835# CONFIG_MEDIA_SUPPORT is not set 889# CONFIG_MEDIA_SUPPORT is not set
836 890
@@ -898,7 +952,9 @@ CONFIG_RTC_INTF_DEV=y
898# CONFIG_RTC_DRV_M48T86 is not set 952# CONFIG_RTC_DRV_M48T86 is not set
899# CONFIG_RTC_DRV_M48T35 is not set 953# CONFIG_RTC_DRV_M48T35 is not set
900# CONFIG_RTC_DRV_M48T59 is not set 954# CONFIG_RTC_DRV_M48T59 is not set
955# CONFIG_RTC_DRV_MSM6242 is not set
901# CONFIG_RTC_DRV_BQ4802 is not set 956# CONFIG_RTC_DRV_BQ4802 is not set
957# CONFIG_RTC_DRV_RP5C01 is not set
902# CONFIG_RTC_DRV_V3020 is not set 958# CONFIG_RTC_DRV_V3020 is not set
903 959
904# 960#
@@ -929,7 +985,6 @@ CONFIG_RTC_DRV_BFIN=y
929# CONFIG_JFS_FS is not set 985# CONFIG_JFS_FS is not set
930# CONFIG_FS_POSIX_ACL is not set 986# CONFIG_FS_POSIX_ACL is not set
931# CONFIG_XFS_FS is not set 987# CONFIG_XFS_FS is not set
932# CONFIG_GFS2_FS is not set
933# CONFIG_OCFS2_FS is not set 988# CONFIG_OCFS2_FS is not set
934# CONFIG_BTRFS_FS is not set 989# CONFIG_BTRFS_FS is not set
935# CONFIG_NILFS2_FS is not set 990# CONFIG_NILFS2_FS is not set
@@ -988,6 +1043,7 @@ CONFIG_JFFS2_ZLIB=y
988# CONFIG_JFFS2_LZO is not set 1043# CONFIG_JFFS2_LZO is not set
989CONFIG_JFFS2_RTIME=y 1044CONFIG_JFFS2_RTIME=y
990# CONFIG_JFFS2_RUBIN is not set 1045# CONFIG_JFFS2_RUBIN is not set
1046# CONFIG_LOGFS is not set
991# CONFIG_CRAMFS is not set 1047# CONFIG_CRAMFS is not set
992# CONFIG_SQUASHFS is not set 1048# CONFIG_SQUASHFS is not set
993# CONFIG_VXFS_FS is not set 1049# CONFIG_VXFS_FS is not set
@@ -1012,6 +1068,7 @@ CONFIG_SUNRPC=m
1012# CONFIG_RPCSEC_GSS_SPKM3 is not set 1068# CONFIG_RPCSEC_GSS_SPKM3 is not set
1013CONFIG_SMB_FS=m 1069CONFIG_SMB_FS=m
1014# CONFIG_SMB_NLS_DEFAULT is not set 1070# CONFIG_SMB_NLS_DEFAULT is not set
1071# CONFIG_CEPH_FS is not set
1015# CONFIG_CIFS is not set 1072# CONFIG_CIFS is not set
1016# CONFIG_NCP_FS is not set 1073# CONFIG_NCP_FS is not set
1017# CONFIG_CODA_FS is not set 1074# CONFIG_CODA_FS is not set
@@ -1113,17 +1170,18 @@ CONFIG_DEBUG_INFO=y
1113# CONFIG_RCU_TORTURE_TEST is not set 1170# CONFIG_RCU_TORTURE_TEST is not set
1114# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1171# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1115# CONFIG_BACKTRACE_SELF_TEST is not set 1172# CONFIG_BACKTRACE_SELF_TEST is not set
1173# CONFIG_TRACEHOOK_SELF_TEST is not set
1116# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1174# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1117# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1175# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1176# CONFIG_LKDTM is not set
1118# CONFIG_FAULT_INJECTION is not set 1177# CONFIG_FAULT_INJECTION is not set
1178# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1119# CONFIG_PAGE_POISONING is not set 1179# CONFIG_PAGE_POISONING is not set
1120CONFIG_HAVE_FUNCTION_TRACER=y 1180CONFIG_HAVE_FUNCTION_TRACER=y
1121CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1181CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1182CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1122CONFIG_TRACING_SUPPORT=y 1183CONFIG_TRACING_SUPPORT=y
1123# CONFIG_FTRACE is not set 1184# CONFIG_FTRACE is not set
1124# CONFIG_BRANCH_PROFILE_NONE is not set
1125# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1126# CONFIG_PROFILE_ALL_BRANCHES is not set
1127# CONFIG_DYNAMIC_DEBUG is not set 1185# CONFIG_DYNAMIC_DEBUG is not set
1128# CONFIG_SAMPLES is not set 1186# CONFIG_SAMPLES is not set
1129CONFIG_HAVE_ARCH_KGDB=y 1187CONFIG_HAVE_ARCH_KGDB=y
@@ -1150,6 +1208,7 @@ CONFIG_EARLY_PRINTK=y
1150CONFIG_CPLB_INFO=y 1208CONFIG_CPLB_INFO=y
1151CONFIG_ACCESS_CHECK=y 1209CONFIG_ACCESS_CHECK=y
1152# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1210# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1211# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1153 1212
1154# 1213#
1155# Security options 1214# Security options
@@ -1159,8 +1218,12 @@ CONFIG_SECURITY=y
1159# CONFIG_SECURITYFS is not set 1218# CONFIG_SECURITYFS is not set
1160# CONFIG_SECURITY_NETWORK is not set 1219# CONFIG_SECURITY_NETWORK is not set
1161# CONFIG_SECURITY_PATH is not set 1220# CONFIG_SECURITY_PATH is not set
1162# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1163# CONFIG_SECURITY_TOMOYO is not set 1221# CONFIG_SECURITY_TOMOYO is not set
1222# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1223# CONFIG_DEFAULT_SECURITY_SMACK is not set
1224# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1225CONFIG_DEFAULT_SECURITY_DAC=y
1226CONFIG_DEFAULT_SECURITY=""
1164CONFIG_CRYPTO=y 1227CONFIG_CRYPTO=y
1165 1228
1166# 1229#
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index c3fe6e5b612f..f65b5e21139b 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 109# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 113CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 114CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 115# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +126,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 126# IO Schedulers
123# 127#
124CONFIG_IOSCHED_NOOP=y 128CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y 130CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 131# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 132CONFIG_DEFAULT_CFQ=y
131# CONFIG_DEFAULT_NOOP is not set 133# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 134CONFIG_DEFAULT_IOSCHED="cfq"
135# CONFIG_INLINE_SPIN_TRYLOCK is not set
136# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
137# CONFIG_INLINE_SPIN_LOCK is not set
138# CONFIG_INLINE_SPIN_LOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
141CONFIG_INLINE_SPIN_UNLOCK=y
142# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
143CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
144# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
145# CONFIG_INLINE_READ_TRYLOCK is not set
146# CONFIG_INLINE_READ_LOCK is not set
147# CONFIG_INLINE_READ_LOCK_BH is not set
148# CONFIG_INLINE_READ_LOCK_IRQ is not set
149# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
150CONFIG_INLINE_READ_UNLOCK=y
151# CONFIG_INLINE_READ_UNLOCK_BH is not set
152CONFIG_INLINE_READ_UNLOCK_IRQ=y
153# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
154# CONFIG_INLINE_WRITE_TRYLOCK is not set
155# CONFIG_INLINE_WRITE_LOCK is not set
156# CONFIG_INLINE_WRITE_LOCK_BH is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
159CONFIG_INLINE_WRITE_UNLOCK=y
160# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
161CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
162# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
163# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 164# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 165CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
@@ -254,8 +285,16 @@ CONFIG_HZ=250
254CONFIG_SCHED_HRTICK=y 285CONFIG_SCHED_HRTICK=y
255CONFIG_GENERIC_TIME=y 286CONFIG_GENERIC_TIME=y
256CONFIG_GENERIC_CLOCKEVENTS=y 287CONFIG_GENERIC_CLOCKEVENTS=y
288
289#
290# Clock event device
291#
257# CONFIG_TICKSOURCE_GPTMR0 is not set 292# CONFIG_TICKSOURCE_GPTMR0 is not set
258CONFIG_TICKSOURCE_CORETMR=y 293CONFIG_TICKSOURCE_CORETMR=y
294
295#
296# Clock souce
297#
259CONFIG_CYCLES_CLOCKSOURCE=y 298CONFIG_CYCLES_CLOCKSOURCE=y
260# CONFIG_GPTMR0_CLOCKSOURCE is not set 299# CONFIG_GPTMR0_CLOCKSOURCE is not set
261CONFIG_TICK_ONESHOT=y 300CONFIG_TICK_ONESHOT=y
@@ -287,12 +326,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
287CONFIG_ACCESS_OK_L1=y 326CONFIG_ACCESS_OK_L1=y
288CONFIG_MEMSET_L1=y 327CONFIG_MEMSET_L1=y
289CONFIG_MEMCPY_L1=y 328CONFIG_MEMCPY_L1=y
329CONFIG_STRCMP_L1=y
330CONFIG_STRNCMP_L1=y
331CONFIG_STRCPY_L1=y
332CONFIG_STRNCPY_L1=y
290CONFIG_SYS_BFIN_SPINLOCK_L1=y 333CONFIG_SYS_BFIN_SPINLOCK_L1=y
291# CONFIG_IP_CHECKSUM_L1 is not set 334# CONFIG_IP_CHECKSUM_L1 is not set
292CONFIG_CACHELINE_ALIGNED_L1=y 335CONFIG_CACHELINE_ALIGNED_L1=y
293# CONFIG_SYSCALL_TAB_L1 is not set 336# CONFIG_SYSCALL_TAB_L1 is not set
294# CONFIG_CPLB_SWITCH_TAB_L1 is not set 337# CONFIG_CPLB_SWITCH_TAB_L1 is not set
295CONFIG_APP_STACK_L1=y 338CONFIG_CACHE_FLUSH_L1=y
296 339
297# 340#
298# Speed Optimizations 341# Speed Optimizations
@@ -385,10 +428,10 @@ CONFIG_PM_SLEEP=y
385CONFIG_SUSPEND=y 428CONFIG_SUSPEND=y
386CONFIG_SUSPEND_FREEZER=y 429CONFIG_SUSPEND_FREEZER=y
387# CONFIG_PM_RUNTIME is not set 430# CONFIG_PM_RUNTIME is not set
431CONFIG_PM_OPS=y
388CONFIG_ARCH_SUSPEND_POSSIBLE=y 432CONFIG_ARCH_SUSPEND_POSSIBLE=y
389CONFIG_PM_BFIN_SLEEP_DEEPER=y 433CONFIG_PM_BFIN_SLEEP_DEEPER=y
390# CONFIG_PM_BFIN_SLEEP is not set 434# CONFIG_PM_BFIN_SLEEP is not set
391# CONFIG_PM_WAKEUP_BY_GPIO is not set
392 435
393# 436#
394# Possible Suspend Mem / Hibernate Wake-Up Sources 437# Possible Suspend Mem / Hibernate Wake-Up Sources
@@ -404,7 +447,6 @@ CONFIG_NET=y
404# Networking options 447# Networking options
405# 448#
406CONFIG_PACKET=y 449CONFIG_PACKET=y
407# CONFIG_PACKET_MMAP is not set
408CONFIG_UNIX=y 450CONFIG_UNIX=y
409# CONFIG_NET_KEY is not set 451# CONFIG_NET_KEY is not set
410CONFIG_INET=y 452CONFIG_INET=y
@@ -612,6 +654,10 @@ CONFIG_MTD_BFIN_ASYNC=m
612CONFIG_BLK_DEV=y 654CONFIG_BLK_DEV=y
613# CONFIG_BLK_DEV_COW_COMMON is not set 655# CONFIG_BLK_DEV_COW_COMMON is not set
614# CONFIG_BLK_DEV_LOOP is not set 656# CONFIG_BLK_DEV_LOOP is not set
657
658#
659# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
660#
615# CONFIG_BLK_DEV_NBD is not set 661# CONFIG_BLK_DEV_NBD is not set
616CONFIG_BLK_DEV_RAM=y 662CONFIG_BLK_DEV_RAM=y
617CONFIG_BLK_DEV_RAM_COUNT=16 663CONFIG_BLK_DEV_RAM_COUNT=16
@@ -625,6 +671,9 @@ CONFIG_MISC_DEVICES=y
625# CONFIG_ICS932S401 is not set 671# CONFIG_ICS932S401 is not set
626# CONFIG_ENCLOSURE_SERVICES is not set 672# CONFIG_ENCLOSURE_SERVICES is not set
627# CONFIG_ISL29003 is not set 673# CONFIG_ISL29003 is not set
674# CONFIG_SENSORS_TSL2550 is not set
675# CONFIG_DS1682 is not set
676# CONFIG_TI_DAC7512 is not set
628# CONFIG_C2PORT is not set 677# CONFIG_C2PORT is not set
629 678
630# 679#
@@ -641,6 +690,7 @@ CONFIG_HAVE_IDE=y
641# 690#
642# SCSI device support 691# SCSI device support
643# 692#
693CONFIG_SCSI_MOD=y
644# CONFIG_RAID_ATTRS is not set 694# CONFIG_RAID_ATTRS is not set
645# CONFIG_SCSI is not set 695# CONFIG_SCSI is not set
646# CONFIG_SCSI_DMA is not set 696# CONFIG_SCSI_DMA is not set
@@ -697,6 +747,7 @@ CONFIG_SMC91X=y
697CONFIG_INPUT=y 747CONFIG_INPUT=y
698# CONFIG_INPUT_FF_MEMLESS is not set 748# CONFIG_INPUT_FF_MEMLESS is not set
699# CONFIG_INPUT_POLLDEV is not set 749# CONFIG_INPUT_POLLDEV is not set
750# CONFIG_INPUT_SPARSEKMAP is not set
700 751
701# 752#
702# Userland interfaces 753# Userland interfaces
@@ -715,11 +766,11 @@ CONFIG_INPUT_EVDEV=m
715# CONFIG_INPUT_TABLET is not set 766# CONFIG_INPUT_TABLET is not set
716# CONFIG_INPUT_TOUCHSCREEN is not set 767# CONFIG_INPUT_TOUCHSCREEN is not set
717CONFIG_INPUT_MISC=y 768CONFIG_INPUT_MISC=y
769# CONFIG_INPUT_AD714X is not set
718# CONFIG_INPUT_UINPUT is not set 770# CONFIG_INPUT_UINPUT is not set
771# CONFIG_INPUT_PCF8574 is not set
719# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 772# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
720# CONFIG_INPUT_AD714X is not set
721# CONFIG_INPUT_ADXL34X is not set 773# CONFIG_INPUT_ADXL34X is not set
722# CONFIG_INPUT_PCF8574 is not set
723 774
724# 775#
725# Hardware I/O ports 776# Hardware I/O ports
@@ -760,6 +811,7 @@ CONFIG_SERIAL_BFIN_UART0=y
760CONFIG_SERIAL_CORE=y 811CONFIG_SERIAL_CORE=y
761CONFIG_SERIAL_CORE_CONSOLE=y 812CONFIG_SERIAL_CORE_CONSOLE=y
762# CONFIG_SERIAL_BFIN_SPORT is not set 813# CONFIG_SERIAL_BFIN_SPORT is not set
814# CONFIG_SERIAL_TIMBERDALE is not set
763CONFIG_UNIX98_PTYS=y 815CONFIG_UNIX98_PTYS=y
764# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 816# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
765# CONFIG_LEGACY_PTYS is not set 817# CONFIG_LEGACY_PTYS is not set
@@ -781,9 +833,10 @@ CONFIG_I2C_HELPER_AUTO=y
781# 833#
782# I2C system bus drivers (mostly embedded / system-on-chip) 834# I2C system bus drivers (mostly embedded / system-on-chip)
783# 835#
784# CONFIG_I2C_GPIO is not set 836CONFIG_I2C_GPIO=m
785# CONFIG_I2C_OCORES is not set 837# CONFIG_I2C_OCORES is not set
786# CONFIG_I2C_SIMTEC is not set 838# CONFIG_I2C_SIMTEC is not set
839# CONFIG_I2C_XILINX is not set
787 840
788# 841#
789# External I2C/SMBus adapter drivers 842# External I2C/SMBus adapter drivers
@@ -796,16 +849,9 @@ CONFIG_I2C_HELPER_AUTO=y
796# 849#
797# CONFIG_I2C_PCA_PLATFORM is not set 850# CONFIG_I2C_PCA_PLATFORM is not set
798# CONFIG_I2C_STUB is not set 851# CONFIG_I2C_STUB is not set
799
800#
801# Miscellaneous I2C Chip support
802#
803# CONFIG_DS1682 is not set
804# CONFIG_SENSORS_TSL2550 is not set
805# CONFIG_I2C_DEBUG_CORE is not set 852# CONFIG_I2C_DEBUG_CORE is not set
806# CONFIG_I2C_DEBUG_ALGO is not set 853# CONFIG_I2C_DEBUG_ALGO is not set
807# CONFIG_I2C_DEBUG_BUS is not set 854# CONFIG_I2C_DEBUG_BUS is not set
808# CONFIG_I2C_DEBUG_CHIP is not set
809CONFIG_SPI=y 855CONFIG_SPI=y
810# CONFIG_SPI_DEBUG is not set 856# CONFIG_SPI_DEBUG is not set
811CONFIG_SPI_MASTER=y 857CONFIG_SPI_MASTER=y
@@ -818,6 +864,8 @@ CONFIG_SPI_BFIN=y
818# CONFIG_SPI_BFIN_SPORT is not set 864# CONFIG_SPI_BFIN_SPORT is not set
819# CONFIG_SPI_BITBANG is not set 865# CONFIG_SPI_BITBANG is not set
820# CONFIG_SPI_GPIO is not set 866# CONFIG_SPI_GPIO is not set
867# CONFIG_SPI_XILINX is not set
868# CONFIG_SPI_DESIGNWARE is not set
821 869
822# 870#
823# SPI Protocol Masters 871# SPI Protocol Masters
@@ -837,10 +885,12 @@ CONFIG_GPIO_SYSFS=y
837# 885#
838# Memory mapped GPIO expanders: 886# Memory mapped GPIO expanders:
839# 887#
888# CONFIG_GPIO_IT8761E is not set
840 889
841# 890#
842# I2C GPIO expanders: 891# I2C GPIO expanders:
843# 892#
893# CONFIG_GPIO_MAX7300 is not set
844# CONFIG_GPIO_MAX732X is not set 894# CONFIG_GPIO_MAX732X is not set
845# CONFIG_GPIO_PCA953X is not set 895# CONFIG_GPIO_PCA953X is not set
846# CONFIG_GPIO_PCF857X is not set 896# CONFIG_GPIO_PCF857X is not set
@@ -889,12 +939,11 @@ CONFIG_SSB_POSSIBLE=y
889# CONFIG_TPS65010 is not set 939# CONFIG_TPS65010 is not set
890# CONFIG_MFD_TMIO is not set 940# CONFIG_MFD_TMIO is not set
891# CONFIG_MFD_WM8400 is not set 941# CONFIG_MFD_WM8400 is not set
892# CONFIG_MFD_WM831X is not set 942# CONFIG_MFD_WM8994 is not set
893# CONFIG_MFD_WM8350_I2C is not set
894# CONFIG_MFD_PCF50633 is not set 943# CONFIG_MFD_PCF50633 is not set
895# CONFIG_MFD_MC13783 is not set 944# CONFIG_MFD_MC13783 is not set
896# CONFIG_AB3100_CORE is not set
897# CONFIG_EZX_PCAP is not set 945# CONFIG_EZX_PCAP is not set
946# CONFIG_AB4500_CORE is not set
898# CONFIG_REGULATOR is not set 947# CONFIG_REGULATOR is not set
899# CONFIG_MEDIA_SUPPORT is not set 948# CONFIG_MEDIA_SUPPORT is not set
900 949
@@ -977,22 +1026,18 @@ CONFIG_SND_DRIVERS=y
977# CONFIG_SND_SERIAL_U16550 is not set 1026# CONFIG_SND_SERIAL_U16550 is not set
978# CONFIG_SND_MPU401 is not set 1027# CONFIG_SND_MPU401 is not set
979CONFIG_SND_SPI=y 1028CONFIG_SND_SPI=y
980
981#
982# ALSA Blackfin devices
983#
984CONFIG_SND_BFIN_SPORT=0
985CONFIG_SND_BFIN_AD73322=m
986CONFIG_SND_BFIN_AD73322_SPORT0_SE=10
987CONFIG_SND_BFIN_AD73322_SPORT1_SE=14
988CONFIG_SND_BFIN_AD73322_RESET=12
989CONFIG_SND_SOC=m 1029CONFIG_SND_SOC=m
990CONFIG_SND_SOC_AC97_BUS=y 1030CONFIG_SND_SOC_AC97_BUS=y
991CONFIG_SND_BF5XX_I2S=m 1031CONFIG_SND_BF5XX_I2S=m
992# CONFIG_SND_BF5XX_SOC_SSM2602 is not set 1032# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
993CONFIG_SND_BF5XX_SOC_AD73311=m 1033CONFIG_SND_BF5XX_SOC_AD73311=m
1034CONFIG_SND_AD7XXXX_SELECT=0
994# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set 1035# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
995# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set 1036# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
1037# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
1038# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
1039# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
1040# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
996CONFIG_SND_BFIN_AD73311_SE=4 1041CONFIG_SND_BFIN_AD73311_SE=4
997# CONFIG_SND_BF5XX_TDM is not set 1042# CONFIG_SND_BF5XX_TDM is not set
998CONFIG_SND_BF5XX_AC97=m 1043CONFIG_SND_BF5XX_AC97=m
@@ -1051,6 +1096,7 @@ CONFIG_RTC_INTF_DEV=y
1051# CONFIG_RTC_DRV_PCF8563 is not set 1096# CONFIG_RTC_DRV_PCF8563 is not set
1052# CONFIG_RTC_DRV_PCF8583 is not set 1097# CONFIG_RTC_DRV_PCF8583 is not set
1053# CONFIG_RTC_DRV_M41T80 is not set 1098# CONFIG_RTC_DRV_M41T80 is not set
1099# CONFIG_RTC_DRV_BQ32K is not set
1054# CONFIG_RTC_DRV_S35390A is not set 1100# CONFIG_RTC_DRV_S35390A is not set
1055# CONFIG_RTC_DRV_FM3130 is not set 1101# CONFIG_RTC_DRV_FM3130 is not set
1056# CONFIG_RTC_DRV_RX8581 is not set 1102# CONFIG_RTC_DRV_RX8581 is not set
@@ -1079,7 +1125,9 @@ CONFIG_RTC_INTF_DEV=y
1079# CONFIG_RTC_DRV_M48T86 is not set 1125# CONFIG_RTC_DRV_M48T86 is not set
1080# CONFIG_RTC_DRV_M48T35 is not set 1126# CONFIG_RTC_DRV_M48T35 is not set
1081# CONFIG_RTC_DRV_M48T59 is not set 1127# CONFIG_RTC_DRV_M48T59 is not set
1128# CONFIG_RTC_DRV_MSM6242 is not set
1082# CONFIG_RTC_DRV_BQ4802 is not set 1129# CONFIG_RTC_DRV_BQ4802 is not set
1130# CONFIG_RTC_DRV_RP5C01 is not set
1083# CONFIG_RTC_DRV_V3020 is not set 1131# CONFIG_RTC_DRV_V3020 is not set
1084 1132
1085# 1133#
@@ -1111,7 +1159,6 @@ CONFIG_RTC_DRV_BFIN=y
1111# CONFIG_JFS_FS is not set 1159# CONFIG_JFS_FS is not set
1112# CONFIG_FS_POSIX_ACL is not set 1160# CONFIG_FS_POSIX_ACL is not set
1113# CONFIG_XFS_FS is not set 1161# CONFIG_XFS_FS is not set
1114# CONFIG_GFS2_FS is not set
1115# CONFIG_OCFS2_FS is not set 1162# CONFIG_OCFS2_FS is not set
1116# CONFIG_BTRFS_FS is not set 1163# CONFIG_BTRFS_FS is not set
1117# CONFIG_NILFS2_FS is not set 1164# CONFIG_NILFS2_FS is not set
@@ -1170,6 +1217,7 @@ CONFIG_JFFS2_ZLIB=y
1170# CONFIG_JFFS2_LZO is not set 1217# CONFIG_JFFS2_LZO is not set
1171CONFIG_JFFS2_RTIME=y 1218CONFIG_JFFS2_RTIME=y
1172# CONFIG_JFFS2_RUBIN is not set 1219# CONFIG_JFFS2_RUBIN is not set
1220# CONFIG_LOGFS is not set
1173# CONFIG_CRAMFS is not set 1221# CONFIG_CRAMFS is not set
1174# CONFIG_SQUASHFS is not set 1222# CONFIG_SQUASHFS is not set
1175# CONFIG_VXFS_FS is not set 1223# CONFIG_VXFS_FS is not set
@@ -1194,6 +1242,7 @@ CONFIG_SUNRPC=m
1194# CONFIG_RPCSEC_GSS_SPKM3 is not set 1242# CONFIG_RPCSEC_GSS_SPKM3 is not set
1195CONFIG_SMB_FS=m 1243CONFIG_SMB_FS=m
1196# CONFIG_SMB_NLS_DEFAULT is not set 1244# CONFIG_SMB_NLS_DEFAULT is not set
1245# CONFIG_CEPH_FS is not set
1197# CONFIG_CIFS is not set 1246# CONFIG_CIFS is not set
1198# CONFIG_NCP_FS is not set 1247# CONFIG_NCP_FS is not set
1199# CONFIG_CODA_FS is not set 1248# CONFIG_CODA_FS is not set
@@ -1272,6 +1321,8 @@ CONFIG_SCHED_DEBUG=y
1272# CONFIG_TIMER_STATS is not set 1321# CONFIG_TIMER_STATS is not set
1273# CONFIG_DEBUG_OBJECTS is not set 1322# CONFIG_DEBUG_OBJECTS is not set
1274# CONFIG_DEBUG_SLAB is not set 1323# CONFIG_DEBUG_SLAB is not set
1324# CONFIG_DEBUG_RT_MUTEXES is not set
1325# CONFIG_RT_MUTEX_TESTER is not set
1275# CONFIG_DEBUG_SPINLOCK is not set 1326# CONFIG_DEBUG_SPINLOCK is not set
1276# CONFIG_DEBUG_MUTEXES is not set 1327# CONFIG_DEBUG_MUTEXES is not set
1277# CONFIG_DEBUG_LOCK_ALLOC is not set 1328# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1295,17 +1346,18 @@ CONFIG_DEBUG_INFO=y
1295# CONFIG_RCU_TORTURE_TEST is not set 1346# CONFIG_RCU_TORTURE_TEST is not set
1296# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1347# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1297# CONFIG_BACKTRACE_SELF_TEST is not set 1348# CONFIG_BACKTRACE_SELF_TEST is not set
1349# CONFIG_TRACEHOOK_SELF_TEST is not set
1298# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1350# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1299# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1351# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1352# CONFIG_LKDTM is not set
1300# CONFIG_FAULT_INJECTION is not set 1353# CONFIG_FAULT_INJECTION is not set
1354# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1301# CONFIG_PAGE_POISONING is not set 1355# CONFIG_PAGE_POISONING is not set
1302CONFIG_HAVE_FUNCTION_TRACER=y 1356CONFIG_HAVE_FUNCTION_TRACER=y
1303CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1357CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1358CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1304CONFIG_TRACING_SUPPORT=y 1359CONFIG_TRACING_SUPPORT=y
1305# CONFIG_FTRACE is not set 1360# CONFIG_FTRACE is not set
1306# CONFIG_BRANCH_PROFILE_NONE is not set
1307# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1308# CONFIG_PROFILE_ALL_BRANCHES is not set
1309# CONFIG_DYNAMIC_DEBUG is not set 1361# CONFIG_DYNAMIC_DEBUG is not set
1310# CONFIG_SAMPLES is not set 1362# CONFIG_SAMPLES is not set
1311CONFIG_HAVE_ARCH_KGDB=y 1363CONFIG_HAVE_ARCH_KGDB=y
@@ -1332,6 +1384,7 @@ CONFIG_EARLY_PRINTK=y
1332CONFIG_CPLB_INFO=y 1384CONFIG_CPLB_INFO=y
1333CONFIG_ACCESS_CHECK=y 1385CONFIG_ACCESS_CHECK=y
1334# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1386# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1387# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1335 1388
1336# 1389#
1337# Security options 1390# Security options
@@ -1341,8 +1394,12 @@ CONFIG_SECURITY=y
1341# CONFIG_SECURITYFS is not set 1394# CONFIG_SECURITYFS is not set
1342# CONFIG_SECURITY_NETWORK is not set 1395# CONFIG_SECURITY_NETWORK is not set
1343# CONFIG_SECURITY_PATH is not set 1396# CONFIG_SECURITY_PATH is not set
1344# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1345# CONFIG_SECURITY_TOMOYO is not set 1397# CONFIG_SECURITY_TOMOYO is not set
1398# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1399# CONFIG_DEFAULT_SECURITY_SMACK is not set
1400# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1401CONFIG_DEFAULT_SECURITY_DAC=y
1402CONFIG_DEFAULT_SECURITY=""
1346CONFIG_CRYPTO=y 1403CONFIG_CRYPTO=y
1347 1404
1348# 1405#
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 7596cf7673f1..50cb9342f012 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 109# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 113CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 114CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 115# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +126,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 126# IO Schedulers
123# 127#
124CONFIG_IOSCHED_NOOP=y 128CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y 130CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 131# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 132CONFIG_DEFAULT_CFQ=y
131# CONFIG_DEFAULT_NOOP is not set 133# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 134CONFIG_DEFAULT_IOSCHED="cfq"
135# CONFIG_INLINE_SPIN_TRYLOCK is not set
136# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
137# CONFIG_INLINE_SPIN_LOCK is not set
138# CONFIG_INLINE_SPIN_LOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
141CONFIG_INLINE_SPIN_UNLOCK=y
142# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
143CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
144# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
145# CONFIG_INLINE_READ_TRYLOCK is not set
146# CONFIG_INLINE_READ_LOCK is not set
147# CONFIG_INLINE_READ_LOCK_BH is not set
148# CONFIG_INLINE_READ_LOCK_IRQ is not set
149# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
150CONFIG_INLINE_READ_UNLOCK=y
151# CONFIG_INLINE_READ_UNLOCK_BH is not set
152CONFIG_INLINE_READ_UNLOCK_IRQ=y
153# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
154# CONFIG_INLINE_WRITE_TRYLOCK is not set
155# CONFIG_INLINE_WRITE_LOCK is not set
156# CONFIG_INLINE_WRITE_LOCK_BH is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
159CONFIG_INLINE_WRITE_UNLOCK=y
160# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
161CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
162# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
163# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 164# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 165CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
@@ -230,7 +261,7 @@ CONFIG_BFIN537_STAMP=y
230# Priority 261# Priority
231# 262#
232CONFIG_IRQ_DMA_ERROR=7 263CONFIG_IRQ_DMA_ERROR=7
233CONFIG_IRQ_ERROR=7 264CONFIG_IRQ_ERROR=11
234CONFIG_IRQ_CAN_RX=11 265CONFIG_IRQ_CAN_RX=11
235CONFIG_IRQ_CAN_TX=11 266CONFIG_IRQ_CAN_TX=11
236CONFIG_IRQ_PROG_INTA=12 267CONFIG_IRQ_PROG_INTA=12
@@ -262,8 +293,16 @@ CONFIG_HZ=250
262CONFIG_SCHED_HRTICK=y 293CONFIG_SCHED_HRTICK=y
263CONFIG_GENERIC_TIME=y 294CONFIG_GENERIC_TIME=y
264CONFIG_GENERIC_CLOCKEVENTS=y 295CONFIG_GENERIC_CLOCKEVENTS=y
296
297#
298# Clock event device
299#
265# CONFIG_TICKSOURCE_GPTMR0 is not set 300# CONFIG_TICKSOURCE_GPTMR0 is not set
266CONFIG_TICKSOURCE_CORETMR=y 301CONFIG_TICKSOURCE_CORETMR=y
302
303#
304# Clock souce
305#
267CONFIG_CYCLES_CLOCKSOURCE=y 306CONFIG_CYCLES_CLOCKSOURCE=y
268# CONFIG_GPTMR0_CLOCKSOURCE is not set 307# CONFIG_GPTMR0_CLOCKSOURCE is not set
269CONFIG_TICK_ONESHOT=y 308CONFIG_TICK_ONESHOT=y
@@ -295,12 +334,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
295CONFIG_ACCESS_OK_L1=y 334CONFIG_ACCESS_OK_L1=y
296CONFIG_MEMSET_L1=y 335CONFIG_MEMSET_L1=y
297CONFIG_MEMCPY_L1=y 336CONFIG_MEMCPY_L1=y
337CONFIG_STRCMP_L1=y
338CONFIG_STRNCMP_L1=y
339CONFIG_STRCPY_L1=y
340CONFIG_STRNCPY_L1=y
298CONFIG_SYS_BFIN_SPINLOCK_L1=y 341CONFIG_SYS_BFIN_SPINLOCK_L1=y
299# CONFIG_IP_CHECKSUM_L1 is not set 342# CONFIG_IP_CHECKSUM_L1 is not set
300CONFIG_CACHELINE_ALIGNED_L1=y 343CONFIG_CACHELINE_ALIGNED_L1=y
301# CONFIG_SYSCALL_TAB_L1 is not set 344# CONFIG_SYSCALL_TAB_L1 is not set
302# CONFIG_CPLB_SWITCH_TAB_L1 is not set 345# CONFIG_CPLB_SWITCH_TAB_L1 is not set
303CONFIG_APP_STACK_L1=y 346CONFIG_CACHE_FLUSH_L1=y
304 347
305# 348#
306# Speed Optimizations 349# Speed Optimizations
@@ -393,10 +436,10 @@ CONFIG_PM_SLEEP=y
393CONFIG_SUSPEND=y 436CONFIG_SUSPEND=y
394CONFIG_SUSPEND_FREEZER=y 437CONFIG_SUSPEND_FREEZER=y
395# CONFIG_PM_RUNTIME is not set 438# CONFIG_PM_RUNTIME is not set
439CONFIG_PM_OPS=y
396CONFIG_ARCH_SUSPEND_POSSIBLE=y 440CONFIG_ARCH_SUSPEND_POSSIBLE=y
397CONFIG_PM_BFIN_SLEEP_DEEPER=y 441CONFIG_PM_BFIN_SLEEP_DEEPER=y
398# CONFIG_PM_BFIN_SLEEP is not set 442# CONFIG_PM_BFIN_SLEEP is not set
399# CONFIG_PM_WAKEUP_BY_GPIO is not set
400 443
401# 444#
402# Possible Suspend Mem / Hibernate Wake-Up Sources 445# Possible Suspend Mem / Hibernate Wake-Up Sources
@@ -413,7 +456,6 @@ CONFIG_NET=y
413# Networking options 456# Networking options
414# 457#
415CONFIG_PACKET=y 458CONFIG_PACKET=y
416# CONFIG_PACKET_MMAP is not set
417CONFIG_UNIX=y 459CONFIG_UNIX=y
418# CONFIG_NET_KEY is not set 460# CONFIG_NET_KEY is not set
419CONFIG_INET=y 461CONFIG_INET=y
@@ -482,13 +524,9 @@ CONFIG_CAN_BCM=m
482# CONFIG_CAN_VCAN is not set 524# CONFIG_CAN_VCAN is not set
483CONFIG_CAN_DEV=m 525CONFIG_CAN_DEV=m
484# CONFIG_CAN_CALC_BITTIMING is not set 526# CONFIG_CAN_CALC_BITTIMING is not set
527# CONFIG_CAN_MCP251X is not set
485CONFIG_CAN_BFIN=m 528CONFIG_CAN_BFIN=m
486# CONFIG_CAN_SJA1000 is not set 529# CONFIG_CAN_SJA1000 is not set
487
488#
489# CAN USB interfaces
490#
491# CONFIG_CAN_EMS_USB is not set
492# CONFIG_CAN_DEBUG_DEVICES is not set 530# CONFIG_CAN_DEBUG_DEVICES is not set
493CONFIG_IRDA=m 531CONFIG_IRDA=m
494 532
@@ -638,6 +676,10 @@ CONFIG_MTD_PHYSMAP=m
638CONFIG_BLK_DEV=y 676CONFIG_BLK_DEV=y
639# CONFIG_BLK_DEV_COW_COMMON is not set 677# CONFIG_BLK_DEV_COW_COMMON is not set
640# CONFIG_BLK_DEV_LOOP is not set 678# CONFIG_BLK_DEV_LOOP is not set
679
680#
681# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
682#
641# CONFIG_BLK_DEV_NBD is not set 683# CONFIG_BLK_DEV_NBD is not set
642CONFIG_BLK_DEV_RAM=y 684CONFIG_BLK_DEV_RAM=y
643CONFIG_BLK_DEV_RAM_COUNT=16 685CONFIG_BLK_DEV_RAM_COUNT=16
@@ -651,6 +693,9 @@ CONFIG_MISC_DEVICES=y
651# CONFIG_ICS932S401 is not set 693# CONFIG_ICS932S401 is not set
652# CONFIG_ENCLOSURE_SERVICES is not set 694# CONFIG_ENCLOSURE_SERVICES is not set
653# CONFIG_ISL29003 is not set 695# CONFIG_ISL29003 is not set
696# CONFIG_SENSORS_TSL2550 is not set
697# CONFIG_DS1682 is not set
698# CONFIG_TI_DAC7512 is not set
654# CONFIG_C2PORT is not set 699# CONFIG_C2PORT is not set
655 700
656# 701#
@@ -667,6 +712,7 @@ CONFIG_HAVE_IDE=y
667# 712#
668# SCSI device support 713# SCSI device support
669# 714#
715CONFIG_SCSI_MOD=y
670# CONFIG_RAID_ATTRS is not set 716# CONFIG_RAID_ATTRS is not set
671# CONFIG_SCSI is not set 717# CONFIG_SCSI is not set
672# CONFIG_SCSI_DMA is not set 718# CONFIG_SCSI_DMA is not set
@@ -698,6 +744,7 @@ CONFIG_SMSC_PHY=y
698# CONFIG_NATIONAL_PHY is not set 744# CONFIG_NATIONAL_PHY is not set
699# CONFIG_STE10XP is not set 745# CONFIG_STE10XP is not set
700# CONFIG_LSI_ET1011C_PHY is not set 746# CONFIG_LSI_ET1011C_PHY is not set
747# CONFIG_MICREL_PHY is not set
701# CONFIG_FIXED_PHY is not set 748# CONFIG_FIXED_PHY is not set
702# CONFIG_MDIO_BITBANG is not set 749# CONFIG_MDIO_BITBANG is not set
703CONFIG_NET_ETHERNET=y 750CONFIG_NET_ETHERNET=y
@@ -706,7 +753,6 @@ CONFIG_BFIN_MAC=y
706CONFIG_BFIN_MAC_USE_L1=y 753CONFIG_BFIN_MAC_USE_L1=y
707CONFIG_BFIN_TX_DESC_NUM=10 754CONFIG_BFIN_TX_DESC_NUM=10
708CONFIG_BFIN_RX_DESC_NUM=20 755CONFIG_BFIN_RX_DESC_NUM=20
709# CONFIG_BFIN_MAC_RMII is not set
710# CONFIG_SMC91X is not set 756# CONFIG_SMC91X is not set
711# CONFIG_DM9000 is not set 757# CONFIG_DM9000 is not set
712# CONFIG_ENC28J60 is not set 758# CONFIG_ENC28J60 is not set
@@ -747,6 +793,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
747CONFIG_INPUT=y 793CONFIG_INPUT=y
748# CONFIG_INPUT_FF_MEMLESS is not set 794# CONFIG_INPUT_FF_MEMLESS is not set
749# CONFIG_INPUT_POLLDEV is not set 795# CONFIG_INPUT_POLLDEV is not set
796# CONFIG_INPUT_SPARSEKMAP is not set
750 797
751# 798#
752# Userland interfaces 799# Userland interfaces
@@ -765,11 +812,11 @@ CONFIG_INPUT_EVDEV=m
765# CONFIG_INPUT_TABLET is not set 812# CONFIG_INPUT_TABLET is not set
766# CONFIG_INPUT_TOUCHSCREEN is not set 813# CONFIG_INPUT_TOUCHSCREEN is not set
767CONFIG_INPUT_MISC=y 814CONFIG_INPUT_MISC=y
815# CONFIG_INPUT_AD714X is not set
768# CONFIG_INPUT_UINPUT is not set 816# CONFIG_INPUT_UINPUT is not set
817# CONFIG_INPUT_PCF8574 is not set
769# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 818# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
770# CONFIG_INPUT_AD714X is not set
771# CONFIG_INPUT_ADXL34X is not set 819# CONFIG_INPUT_ADXL34X is not set
772# CONFIG_INPUT_PCF8574 is not set
773 820
774# 821#
775# Hardware I/O ports 822# Hardware I/O ports
@@ -811,6 +858,7 @@ CONFIG_SERIAL_BFIN_UART0=y
811CONFIG_SERIAL_CORE=y 858CONFIG_SERIAL_CORE=y
812CONFIG_SERIAL_CORE_CONSOLE=y 859CONFIG_SERIAL_CORE_CONSOLE=y
813# CONFIG_SERIAL_BFIN_SPORT is not set 860# CONFIG_SERIAL_BFIN_SPORT is not set
861# CONFIG_SERIAL_TIMBERDALE is not set
814CONFIG_UNIX98_PTYS=y 862CONFIG_UNIX98_PTYS=y
815# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 863# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
816# CONFIG_LEGACY_PTYS is not set 864# CONFIG_LEGACY_PTYS is not set
@@ -837,6 +885,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
837# CONFIG_I2C_GPIO is not set 885# CONFIG_I2C_GPIO is not set
838# CONFIG_I2C_OCORES is not set 886# CONFIG_I2C_OCORES is not set
839# CONFIG_I2C_SIMTEC is not set 887# CONFIG_I2C_SIMTEC is not set
888# CONFIG_I2C_XILINX is not set
840 889
841# 890#
842# External I2C/SMBus adapter drivers 891# External I2C/SMBus adapter drivers
@@ -849,16 +898,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
849# 898#
850# CONFIG_I2C_PCA_PLATFORM is not set 899# CONFIG_I2C_PCA_PLATFORM is not set
851# CONFIG_I2C_STUB is not set 900# CONFIG_I2C_STUB is not set
852
853#
854# Miscellaneous I2C Chip support
855#
856# CONFIG_DS1682 is not set
857# CONFIG_SENSORS_TSL2550 is not set
858# CONFIG_I2C_DEBUG_CORE is not set 901# CONFIG_I2C_DEBUG_CORE is not set
859# CONFIG_I2C_DEBUG_ALGO is not set 902# CONFIG_I2C_DEBUG_ALGO is not set
860# CONFIG_I2C_DEBUG_BUS is not set 903# CONFIG_I2C_DEBUG_BUS is not set
861# CONFIG_I2C_DEBUG_CHIP is not set
862CONFIG_SPI=y 904CONFIG_SPI=y
863# CONFIG_SPI_DEBUG is not set 905# CONFIG_SPI_DEBUG is not set
864CONFIG_SPI_MASTER=y 906CONFIG_SPI_MASTER=y
@@ -871,6 +913,8 @@ CONFIG_SPI_BFIN=y
871# CONFIG_SPI_BFIN_SPORT is not set 913# CONFIG_SPI_BFIN_SPORT is not set
872# CONFIG_SPI_BITBANG is not set 914# CONFIG_SPI_BITBANG is not set
873# CONFIG_SPI_GPIO is not set 915# CONFIG_SPI_GPIO is not set
916# CONFIG_SPI_XILINX is not set
917# CONFIG_SPI_DESIGNWARE is not set
874 918
875# 919#
876# SPI Protocol Masters 920# SPI Protocol Masters
@@ -890,10 +934,12 @@ CONFIG_GPIO_SYSFS=y
890# 934#
891# Memory mapped GPIO expanders: 935# Memory mapped GPIO expanders:
892# 936#
937# CONFIG_GPIO_IT8761E is not set
893 938
894# 939#
895# I2C GPIO expanders: 940# I2C GPIO expanders:
896# 941#
942# CONFIG_GPIO_MAX7300 is not set
897# CONFIG_GPIO_MAX732X is not set 943# CONFIG_GPIO_MAX732X is not set
898# CONFIG_GPIO_PCA953X is not set 944# CONFIG_GPIO_PCA953X is not set
899# CONFIG_GPIO_PCF857X is not set 945# CONFIG_GPIO_PCF857X is not set
@@ -942,12 +988,11 @@ CONFIG_SSB_POSSIBLE=y
942# CONFIG_TPS65010 is not set 988# CONFIG_TPS65010 is not set
943# CONFIG_MFD_TMIO is not set 989# CONFIG_MFD_TMIO is not set
944# CONFIG_MFD_WM8400 is not set 990# CONFIG_MFD_WM8400 is not set
945# CONFIG_MFD_WM831X is not set 991# CONFIG_MFD_WM8994 is not set
946# CONFIG_MFD_WM8350_I2C is not set
947# CONFIG_MFD_PCF50633 is not set 992# CONFIG_MFD_PCF50633 is not set
948# CONFIG_MFD_MC13783 is not set 993# CONFIG_MFD_MC13783 is not set
949# CONFIG_AB3100_CORE is not set
950# CONFIG_EZX_PCAP is not set 994# CONFIG_EZX_PCAP is not set
995# CONFIG_AB4500_CORE is not set
951# CONFIG_REGULATOR is not set 996# CONFIG_REGULATOR is not set
952# CONFIG_MEDIA_SUPPORT is not set 997# CONFIG_MEDIA_SUPPORT is not set
953 998
@@ -998,6 +1043,7 @@ CONFIG_ADV7393_1XMEM=y
998# CONFIG_FB_BROADSHEET is not set 1043# CONFIG_FB_BROADSHEET is not set
999CONFIG_BACKLIGHT_LCD_SUPPORT=y 1044CONFIG_BACKLIGHT_LCD_SUPPORT=y
1000CONFIG_LCD_CLASS_DEVICE=m 1045CONFIG_LCD_CLASS_DEVICE=m
1046# CONFIG_LCD_L4F00242T03 is not set
1001# CONFIG_LCD_LMS283GF05 is not set 1047# CONFIG_LCD_LMS283GF05 is not set
1002# CONFIG_LCD_LTV350QV is not set 1048# CONFIG_LCD_LTV350QV is not set
1003# CONFIG_LCD_ILI9320 is not set 1049# CONFIG_LCD_ILI9320 is not set
@@ -1006,6 +1052,7 @@ CONFIG_LCD_CLASS_DEVICE=m
1006# CONFIG_LCD_PLATFORM is not set 1052# CONFIG_LCD_PLATFORM is not set
1007CONFIG_BACKLIGHT_CLASS_DEVICE=m 1053CONFIG_BACKLIGHT_CLASS_DEVICE=m
1008CONFIG_BACKLIGHT_GENERIC=m 1054CONFIG_BACKLIGHT_GENERIC=m
1055# CONFIG_BACKLIGHT_ADP8860 is not set
1009# CONFIG_BACKLIGHT_ADP8870 is not set 1056# CONFIG_BACKLIGHT_ADP8870 is not set
1010 1057
1011# 1058#
@@ -1042,22 +1089,18 @@ CONFIG_SND_DRIVERS=y
1042# CONFIG_SND_SERIAL_U16550 is not set 1089# CONFIG_SND_SERIAL_U16550 is not set
1043# CONFIG_SND_MPU401 is not set 1090# CONFIG_SND_MPU401 is not set
1044CONFIG_SND_SPI=y 1091CONFIG_SND_SPI=y
1045
1046#
1047# ALSA Blackfin devices
1048#
1049CONFIG_SND_BFIN_SPORT=0
1050CONFIG_SND_BFIN_AD73322=m
1051CONFIG_SND_BFIN_AD73322_SPORT0_SE=10
1052CONFIG_SND_BFIN_AD73322_SPORT1_SE=14
1053CONFIG_SND_BFIN_AD73322_RESET=12
1054CONFIG_SND_SOC=m 1092CONFIG_SND_SOC=m
1055CONFIG_SND_SOC_AC97_BUS=y 1093CONFIG_SND_SOC_AC97_BUS=y
1056CONFIG_SND_BF5XX_I2S=m 1094CONFIG_SND_BF5XX_I2S=m
1057# CONFIG_SND_BF5XX_SOC_SSM2602 is not set 1095# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
1058CONFIG_SND_BF5XX_SOC_AD73311=m 1096CONFIG_SND_BF5XX_SOC_AD73311=m
1097CONFIG_SND_AD7XXXX_SELECT=0
1059# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set 1098# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
1060# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set 1099# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
1100# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
1101# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
1102# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
1103# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
1061CONFIG_SND_BFIN_AD73311_SE=4 1104CONFIG_SND_BFIN_AD73311_SE=4
1062# CONFIG_SND_BF5XX_TDM is not set 1105# CONFIG_SND_BF5XX_TDM is not set
1063CONFIG_SND_BF5XX_AC97=m 1106CONFIG_SND_BF5XX_AC97=m
@@ -1116,6 +1159,7 @@ CONFIG_RTC_INTF_DEV=y
1116# CONFIG_RTC_DRV_PCF8563 is not set 1159# CONFIG_RTC_DRV_PCF8563 is not set
1117# CONFIG_RTC_DRV_PCF8583 is not set 1160# CONFIG_RTC_DRV_PCF8583 is not set
1118# CONFIG_RTC_DRV_M41T80 is not set 1161# CONFIG_RTC_DRV_M41T80 is not set
1162# CONFIG_RTC_DRV_BQ32K is not set
1119# CONFIG_RTC_DRV_S35390A is not set 1163# CONFIG_RTC_DRV_S35390A is not set
1120# CONFIG_RTC_DRV_FM3130 is not set 1164# CONFIG_RTC_DRV_FM3130 is not set
1121# CONFIG_RTC_DRV_RX8581 is not set 1165# CONFIG_RTC_DRV_RX8581 is not set
@@ -1144,7 +1188,9 @@ CONFIG_RTC_INTF_DEV=y
1144# CONFIG_RTC_DRV_M48T86 is not set 1188# CONFIG_RTC_DRV_M48T86 is not set
1145# CONFIG_RTC_DRV_M48T35 is not set 1189# CONFIG_RTC_DRV_M48T35 is not set
1146# CONFIG_RTC_DRV_M48T59 is not set 1190# CONFIG_RTC_DRV_M48T59 is not set
1191# CONFIG_RTC_DRV_MSM6242 is not set
1147# CONFIG_RTC_DRV_BQ4802 is not set 1192# CONFIG_RTC_DRV_BQ4802 is not set
1193# CONFIG_RTC_DRV_RP5C01 is not set
1148# CONFIG_RTC_DRV_V3020 is not set 1194# CONFIG_RTC_DRV_V3020 is not set
1149 1195
1150# 1196#
@@ -1176,7 +1222,6 @@ CONFIG_RTC_DRV_BFIN=y
1176# CONFIG_JFS_FS is not set 1222# CONFIG_JFS_FS is not set
1177# CONFIG_FS_POSIX_ACL is not set 1223# CONFIG_FS_POSIX_ACL is not set
1178# CONFIG_XFS_FS is not set 1224# CONFIG_XFS_FS is not set
1179# CONFIG_GFS2_FS is not set
1180# CONFIG_OCFS2_FS is not set 1225# CONFIG_OCFS2_FS is not set
1181# CONFIG_BTRFS_FS is not set 1226# CONFIG_BTRFS_FS is not set
1182# CONFIG_NILFS2_FS is not set 1227# CONFIG_NILFS2_FS is not set
@@ -1235,6 +1280,7 @@ CONFIG_JFFS2_ZLIB=y
1235# CONFIG_JFFS2_LZO is not set 1280# CONFIG_JFFS2_LZO is not set
1236CONFIG_JFFS2_RTIME=y 1281CONFIG_JFFS2_RTIME=y
1237# CONFIG_JFFS2_RUBIN is not set 1282# CONFIG_JFFS2_RUBIN is not set
1283# CONFIG_LOGFS is not set
1238# CONFIG_CRAMFS is not set 1284# CONFIG_CRAMFS is not set
1239# CONFIG_SQUASHFS is not set 1285# CONFIG_SQUASHFS is not set
1240# CONFIG_VXFS_FS is not set 1286# CONFIG_VXFS_FS is not set
@@ -1259,6 +1305,7 @@ CONFIG_SUNRPC=m
1259# CONFIG_RPCSEC_GSS_SPKM3 is not set 1305# CONFIG_RPCSEC_GSS_SPKM3 is not set
1260CONFIG_SMB_FS=m 1306CONFIG_SMB_FS=m
1261# CONFIG_SMB_NLS_DEFAULT is not set 1307# CONFIG_SMB_NLS_DEFAULT is not set
1308# CONFIG_CEPH_FS is not set
1262# CONFIG_CIFS is not set 1309# CONFIG_CIFS is not set
1263# CONFIG_NCP_FS is not set 1310# CONFIG_NCP_FS is not set
1264# CONFIG_CODA_FS is not set 1311# CONFIG_CODA_FS is not set
@@ -1337,6 +1384,8 @@ CONFIG_SCHED_DEBUG=y
1337# CONFIG_TIMER_STATS is not set 1384# CONFIG_TIMER_STATS is not set
1338# CONFIG_DEBUG_OBJECTS is not set 1385# CONFIG_DEBUG_OBJECTS is not set
1339# CONFIG_DEBUG_SLAB is not set 1386# CONFIG_DEBUG_SLAB is not set
1387# CONFIG_DEBUG_RT_MUTEXES is not set
1388# CONFIG_RT_MUTEX_TESTER is not set
1340# CONFIG_DEBUG_SPINLOCK is not set 1389# CONFIG_DEBUG_SPINLOCK is not set
1341# CONFIG_DEBUG_MUTEXES is not set 1390# CONFIG_DEBUG_MUTEXES is not set
1342# CONFIG_DEBUG_LOCK_ALLOC is not set 1391# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1360,17 +1409,18 @@ CONFIG_DEBUG_INFO=y
1360# CONFIG_RCU_TORTURE_TEST is not set 1409# CONFIG_RCU_TORTURE_TEST is not set
1361# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1410# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1362# CONFIG_BACKTRACE_SELF_TEST is not set 1411# CONFIG_BACKTRACE_SELF_TEST is not set
1412# CONFIG_TRACEHOOK_SELF_TEST is not set
1363# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1413# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1364# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1414# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1415# CONFIG_LKDTM is not set
1365# CONFIG_FAULT_INJECTION is not set 1416# CONFIG_FAULT_INJECTION is not set
1417# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1366# CONFIG_PAGE_POISONING is not set 1418# CONFIG_PAGE_POISONING is not set
1367CONFIG_HAVE_FUNCTION_TRACER=y 1419CONFIG_HAVE_FUNCTION_TRACER=y
1368CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1420CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1421CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1369CONFIG_TRACING_SUPPORT=y 1422CONFIG_TRACING_SUPPORT=y
1370# CONFIG_FTRACE is not set 1423# CONFIG_FTRACE is not set
1371# CONFIG_BRANCH_PROFILE_NONE is not set
1372# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1373# CONFIG_PROFILE_ALL_BRANCHES is not set
1374# CONFIG_DYNAMIC_DEBUG is not set 1424# CONFIG_DYNAMIC_DEBUG is not set
1375# CONFIG_SAMPLES is not set 1425# CONFIG_SAMPLES is not set
1376CONFIG_HAVE_ARCH_KGDB=y 1426CONFIG_HAVE_ARCH_KGDB=y
@@ -1397,6 +1447,7 @@ CONFIG_EARLY_PRINTK=y
1397CONFIG_CPLB_INFO=y 1447CONFIG_CPLB_INFO=y
1398CONFIG_ACCESS_CHECK=y 1448CONFIG_ACCESS_CHECK=y
1399# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1449# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1450# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1400 1451
1401# 1452#
1402# Security options 1453# Security options
@@ -1406,8 +1457,12 @@ CONFIG_SECURITY=y
1406# CONFIG_SECURITYFS is not set 1457# CONFIG_SECURITYFS is not set
1407# CONFIG_SECURITY_NETWORK is not set 1458# CONFIG_SECURITY_NETWORK is not set
1408# CONFIG_SECURITY_PATH is not set 1459# CONFIG_SECURITY_PATH is not set
1409# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1410# CONFIG_SECURITY_TOMOYO is not set 1460# CONFIG_SECURITY_TOMOYO is not set
1461# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1462# CONFIG_DEFAULT_SECURITY_SMACK is not set
1463# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1464CONFIG_DEFAULT_SECURITY_DAC=y
1465CONFIG_DEFAULT_SECURITY=""
1411CONFIG_CRYPTO=y 1466CONFIG_CRYPTO=y
1412 1467
1413# 1468#
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index bc1871d89fd5..247cfae35af8 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
106# CONFIG_SLOW_WORK is not set 109# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
109CONFIG_BASE_SMALL=0 113CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y 114CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set 115# CONFIG_MODULE_FORCE_LOAD is not set
@@ -122,14 +126,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 126# IO Schedulers
123# 127#
124CONFIG_IOSCHED_NOOP=y 128CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y 130CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 131# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 132CONFIG_DEFAULT_CFQ=y
131# CONFIG_DEFAULT_NOOP is not set 133# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 134CONFIG_DEFAULT_IOSCHED="cfq"
135# CONFIG_INLINE_SPIN_TRYLOCK is not set
136# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
137# CONFIG_INLINE_SPIN_LOCK is not set
138# CONFIG_INLINE_SPIN_LOCK_BH is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
141CONFIG_INLINE_SPIN_UNLOCK=y
142# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
143CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
144# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
145# CONFIG_INLINE_READ_TRYLOCK is not set
146# CONFIG_INLINE_READ_LOCK is not set
147# CONFIG_INLINE_READ_LOCK_BH is not set
148# CONFIG_INLINE_READ_LOCK_IRQ is not set
149# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
150CONFIG_INLINE_READ_UNLOCK=y
151# CONFIG_INLINE_READ_UNLOCK_BH is not set
152CONFIG_INLINE_READ_UNLOCK_IRQ=y
153# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
154# CONFIG_INLINE_WRITE_TRYLOCK is not set
155# CONFIG_INLINE_WRITE_LOCK is not set
156# CONFIG_INLINE_WRITE_LOCK_BH is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
159CONFIG_INLINE_WRITE_UNLOCK=y
160# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
161CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
162# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
163# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 164# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 165CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
@@ -272,8 +303,16 @@ CONFIG_HZ=250
272CONFIG_SCHED_HRTICK=y 303CONFIG_SCHED_HRTICK=y
273CONFIG_GENERIC_TIME=y 304CONFIG_GENERIC_TIME=y
274CONFIG_GENERIC_CLOCKEVENTS=y 305CONFIG_GENERIC_CLOCKEVENTS=y
306
307#
308# Clock event device
309#
275# CONFIG_TICKSOURCE_GPTMR0 is not set 310# CONFIG_TICKSOURCE_GPTMR0 is not set
276CONFIG_TICKSOURCE_CORETMR=y 311CONFIG_TICKSOURCE_CORETMR=y
312
313#
314# Clock souce
315#
277CONFIG_CYCLES_CLOCKSOURCE=y 316CONFIG_CYCLES_CLOCKSOURCE=y
278# CONFIG_GPTMR0_CLOCKSOURCE is not set 317# CONFIG_GPTMR0_CLOCKSOURCE is not set
279CONFIG_TICK_ONESHOT=y 318CONFIG_TICK_ONESHOT=y
@@ -305,12 +344,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
305CONFIG_ACCESS_OK_L1=y 344CONFIG_ACCESS_OK_L1=y
306CONFIG_MEMSET_L1=y 345CONFIG_MEMSET_L1=y
307CONFIG_MEMCPY_L1=y 346CONFIG_MEMCPY_L1=y
347CONFIG_STRCMP_L1=y
348CONFIG_STRNCMP_L1=y
349CONFIG_STRCPY_L1=y
350CONFIG_STRNCPY_L1=y
308CONFIG_SYS_BFIN_SPINLOCK_L1=y 351CONFIG_SYS_BFIN_SPINLOCK_L1=y
309# CONFIG_IP_CHECKSUM_L1 is not set 352# CONFIG_IP_CHECKSUM_L1 is not set
310CONFIG_CACHELINE_ALIGNED_L1=y 353CONFIG_CACHELINE_ALIGNED_L1=y
311# CONFIG_SYSCALL_TAB_L1 is not set 354# CONFIG_SYSCALL_TAB_L1 is not set
312# CONFIG_CPLB_SWITCH_TAB_L1 is not set 355# CONFIG_CPLB_SWITCH_TAB_L1 is not set
313CONFIG_APP_STACK_L1=y 356CONFIG_CACHE_FLUSH_L1=y
314 357
315# 358#
316# Speed Optimizations 359# Speed Optimizations
@@ -410,7 +453,6 @@ CONFIG_NET=y
410# Networking options 453# Networking options
411# 454#
412CONFIG_PACKET=y 455CONFIG_PACKET=y
413# CONFIG_PACKET_MMAP is not set
414CONFIG_UNIX=y 456CONFIG_UNIX=y
415# CONFIG_NET_KEY is not set 457# CONFIG_NET_KEY is not set
416CONFIG_INET=y 458CONFIG_INET=y
@@ -479,13 +521,9 @@ CONFIG_CAN_BCM=m
479# CONFIG_CAN_VCAN is not set 521# CONFIG_CAN_VCAN is not set
480CONFIG_CAN_DEV=m 522CONFIG_CAN_DEV=m
481# CONFIG_CAN_CALC_BITTIMING is not set 523# CONFIG_CAN_CALC_BITTIMING is not set
524# CONFIG_CAN_MCP251X is not set
482CONFIG_CAN_BFIN=m 525CONFIG_CAN_BFIN=m
483# CONFIG_CAN_SJA1000 is not set 526# CONFIG_CAN_SJA1000 is not set
484
485#
486# CAN USB interfaces
487#
488# CONFIG_CAN_EMS_USB is not set
489# CONFIG_CAN_DEBUG_DEVICES is not set 527# CONFIG_CAN_DEBUG_DEVICES is not set
490CONFIG_IRDA=m 528CONFIG_IRDA=m
491 529
@@ -641,6 +679,10 @@ CONFIG_MTD_NAND_IDS=m
641CONFIG_BLK_DEV=y 679CONFIG_BLK_DEV=y
642# CONFIG_BLK_DEV_COW_COMMON is not set 680# CONFIG_BLK_DEV_COW_COMMON is not set
643# CONFIG_BLK_DEV_LOOP is not set 681# CONFIG_BLK_DEV_LOOP is not set
682
683#
684# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
685#
644# CONFIG_BLK_DEV_NBD is not set 686# CONFIG_BLK_DEV_NBD is not set
645CONFIG_BLK_DEV_RAM=y 687CONFIG_BLK_DEV_RAM=y
646CONFIG_BLK_DEV_RAM_COUNT=16 688CONFIG_BLK_DEV_RAM_COUNT=16
@@ -656,6 +698,7 @@ CONFIG_HAVE_IDE=y
656# 698#
657# SCSI device support 699# SCSI device support
658# 700#
701CONFIG_SCSI_MOD=y
659# CONFIG_RAID_ATTRS is not set 702# CONFIG_RAID_ATTRS is not set
660# CONFIG_SCSI is not set 703# CONFIG_SCSI is not set
661# CONFIG_SCSI_DMA is not set 704# CONFIG_SCSI_DMA is not set
@@ -687,6 +730,7 @@ CONFIG_SMSC_PHY=y
687# CONFIG_NATIONAL_PHY is not set 730# CONFIG_NATIONAL_PHY is not set
688# CONFIG_STE10XP is not set 731# CONFIG_STE10XP is not set
689# CONFIG_LSI_ET1011C_PHY is not set 732# CONFIG_LSI_ET1011C_PHY is not set
733# CONFIG_MICREL_PHY is not set
690# CONFIG_FIXED_PHY is not set 734# CONFIG_FIXED_PHY is not set
691# CONFIG_MDIO_BITBANG is not set 735# CONFIG_MDIO_BITBANG is not set
692CONFIG_NET_ETHERNET=y 736CONFIG_NET_ETHERNET=y
@@ -731,6 +775,7 @@ CONFIG_SMC91X=y
731CONFIG_INPUT=y 775CONFIG_INPUT=y
732# CONFIG_INPUT_FF_MEMLESS is not set 776# CONFIG_INPUT_FF_MEMLESS is not set
733# CONFIG_INPUT_POLLDEV is not set 777# CONFIG_INPUT_POLLDEV is not set
778# CONFIG_INPUT_SPARSEKMAP is not set
734 779
735# 780#
736# Userland interfaces 781# Userland interfaces
@@ -750,9 +795,11 @@ CONFIG_INPUT_EVDEV=m
750CONFIG_INPUT_TOUCHSCREEN=y 795CONFIG_INPUT_TOUCHSCREEN=y
751# CONFIG_TOUCHSCREEN_ADS7846 is not set 796# CONFIG_TOUCHSCREEN_ADS7846 is not set
752# CONFIG_TOUCHSCREEN_AD7877 is not set 797# CONFIG_TOUCHSCREEN_AD7877 is not set
798CONFIG_TOUCHSCREEN_AD7879=y
753# CONFIG_TOUCHSCREEN_AD7879_I2C is not set 799# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
754CONFIG_TOUCHSCREEN_AD7879_SPI=y 800CONFIG_TOUCHSCREEN_AD7879_SPI=y
755CONFIG_TOUCHSCREEN_AD7879=y 801# CONFIG_TOUCHSCREEN_AD7160 is not set
802# CONFIG_TOUCHSCREEN_DYNAPRO is not set
756# CONFIG_TOUCHSCREEN_EETI is not set 803# CONFIG_TOUCHSCREEN_EETI is not set
757# CONFIG_TOUCHSCREEN_FUJITSU is not set 804# CONFIG_TOUCHSCREEN_FUJITSU is not set
758# CONFIG_TOUCHSCREEN_GUNZE is not set 805# CONFIG_TOUCHSCREEN_GUNZE is not set
@@ -768,11 +815,11 @@ CONFIG_TOUCHSCREEN_AD7879=y
768# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set 815# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
769# CONFIG_TOUCHSCREEN_TSC2007 is not set 816# CONFIG_TOUCHSCREEN_TSC2007 is not set
770CONFIG_INPUT_MISC=y 817CONFIG_INPUT_MISC=y
818# CONFIG_INPUT_AD714X is not set
771# CONFIG_INPUT_UINPUT is not set 819# CONFIG_INPUT_UINPUT is not set
820# CONFIG_INPUT_PCF8574 is not set
772# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 821# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
773# CONFIG_INPUT_AD714X is not set
774# CONFIG_INPUT_ADXL34X is not set 822# CONFIG_INPUT_ADXL34X is not set
775# CONFIG_INPUT_PCF8574 is not set
776 823
777# 824#
778# Hardware I/O ports 825# Hardware I/O ports
@@ -817,6 +864,7 @@ CONFIG_SERIAL_BFIN_UART2=y
817CONFIG_SERIAL_CORE=y 864CONFIG_SERIAL_CORE=y
818CONFIG_SERIAL_CORE_CONSOLE=y 865CONFIG_SERIAL_CORE_CONSOLE=y
819# CONFIG_SERIAL_BFIN_SPORT is not set 866# CONFIG_SERIAL_BFIN_SPORT is not set
867# CONFIG_SERIAL_TIMBERDALE is not set
820CONFIG_UNIX98_PTYS=y 868CONFIG_UNIX98_PTYS=y
821# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 869# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
822# CONFIG_LEGACY_PTYS is not set 870# CONFIG_LEGACY_PTYS is not set
@@ -843,6 +891,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
843# CONFIG_I2C_GPIO is not set 891# CONFIG_I2C_GPIO is not set
844# CONFIG_I2C_OCORES is not set 892# CONFIG_I2C_OCORES is not set
845# CONFIG_I2C_SIMTEC is not set 893# CONFIG_I2C_SIMTEC is not set
894# CONFIG_I2C_XILINX is not set
846 895
847# 896#
848# External I2C/SMBus adapter drivers 897# External I2C/SMBus adapter drivers
@@ -855,16 +904,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
855# 904#
856# CONFIG_I2C_PCA_PLATFORM is not set 905# CONFIG_I2C_PCA_PLATFORM is not set
857# CONFIG_I2C_STUB is not set 906# CONFIG_I2C_STUB is not set
858
859#
860# Miscellaneous I2C Chip support
861#
862# CONFIG_DS1682 is not set
863# CONFIG_SENSORS_TSL2550 is not set
864# CONFIG_I2C_DEBUG_CORE is not set 907# CONFIG_I2C_DEBUG_CORE is not set
865# CONFIG_I2C_DEBUG_ALGO is not set 908# CONFIG_I2C_DEBUG_ALGO is not set
866# CONFIG_I2C_DEBUG_BUS is not set 909# CONFIG_I2C_DEBUG_BUS is not set
867# CONFIG_I2C_DEBUG_CHIP is not set
868CONFIG_SPI=y 910CONFIG_SPI=y
869# CONFIG_SPI_DEBUG is not set 911# CONFIG_SPI_DEBUG is not set
870CONFIG_SPI_MASTER=y 912CONFIG_SPI_MASTER=y
@@ -877,6 +919,8 @@ CONFIG_SPI_BFIN=y
877# CONFIG_SPI_BFIN_SPORT is not set 919# CONFIG_SPI_BFIN_SPORT is not set
878# CONFIG_SPI_BITBANG is not set 920# CONFIG_SPI_BITBANG is not set
879# CONFIG_SPI_GPIO is not set 921# CONFIG_SPI_GPIO is not set
922# CONFIG_SPI_XILINX is not set
923# CONFIG_SPI_DESIGNWARE is not set
880 924
881# 925#
882# SPI Protocol Masters 926# SPI Protocol Masters
@@ -896,10 +940,12 @@ CONFIG_GPIO_SYSFS=y
896# 940#
897# Memory mapped GPIO expanders: 941# Memory mapped GPIO expanders:
898# 942#
943# CONFIG_GPIO_IT8761E is not set
899 944
900# 945#
901# I2C GPIO expanders: 946# I2C GPIO expanders:
902# 947#
948# CONFIG_GPIO_MAX7300 is not set
903# CONFIG_GPIO_MAX732X is not set 949# CONFIG_GPIO_MAX732X is not set
904# CONFIG_GPIO_PCA953X is not set 950# CONFIG_GPIO_PCA953X is not set
905# CONFIG_GPIO_PCF857X is not set 951# CONFIG_GPIO_PCF857X is not set
@@ -947,12 +993,11 @@ CONFIG_SSB_POSSIBLE=y
947# CONFIG_TPS65010 is not set 993# CONFIG_TPS65010 is not set
948# CONFIG_MFD_TMIO is not set 994# CONFIG_MFD_TMIO is not set
949# CONFIG_MFD_WM8400 is not set 995# CONFIG_MFD_WM8400 is not set
950# CONFIG_MFD_WM831X is not set 996# CONFIG_MFD_WM8994 is not set
951# CONFIG_MFD_WM8350_I2C is not set
952# CONFIG_MFD_PCF50633 is not set 997# CONFIG_MFD_PCF50633 is not set
953# CONFIG_MFD_MC13783 is not set 998# CONFIG_MFD_MC13783 is not set
954# CONFIG_AB3100_CORE is not set
955# CONFIG_EZX_PCAP is not set 999# CONFIG_EZX_PCAP is not set
1000# CONFIG_AB4500_CORE is not set
956# CONFIG_REGULATOR is not set 1001# CONFIG_REGULATOR is not set
957# CONFIG_MEDIA_SUPPORT is not set 1002# CONFIG_MEDIA_SUPPORT is not set
958 1003
@@ -1040,6 +1085,7 @@ CONFIG_RTC_INTF_DEV=y
1040# CONFIG_RTC_DRV_PCF8563 is not set 1085# CONFIG_RTC_DRV_PCF8563 is not set
1041# CONFIG_RTC_DRV_PCF8583 is not set 1086# CONFIG_RTC_DRV_PCF8583 is not set
1042# CONFIG_RTC_DRV_M41T80 is not set 1087# CONFIG_RTC_DRV_M41T80 is not set
1088# CONFIG_RTC_DRV_BQ32K is not set
1043# CONFIG_RTC_DRV_S35390A is not set 1089# CONFIG_RTC_DRV_S35390A is not set
1044# CONFIG_RTC_DRV_FM3130 is not set 1090# CONFIG_RTC_DRV_FM3130 is not set
1045# CONFIG_RTC_DRV_RX8581 is not set 1091# CONFIG_RTC_DRV_RX8581 is not set
@@ -1068,7 +1114,9 @@ CONFIG_RTC_INTF_DEV=y
1068# CONFIG_RTC_DRV_M48T86 is not set 1114# CONFIG_RTC_DRV_M48T86 is not set
1069# CONFIG_RTC_DRV_M48T35 is not set 1115# CONFIG_RTC_DRV_M48T35 is not set
1070# CONFIG_RTC_DRV_M48T59 is not set 1116# CONFIG_RTC_DRV_M48T59 is not set
1117# CONFIG_RTC_DRV_MSM6242 is not set
1071# CONFIG_RTC_DRV_BQ4802 is not set 1118# CONFIG_RTC_DRV_BQ4802 is not set
1119# CONFIG_RTC_DRV_RP5C01 is not set
1072# CONFIG_RTC_DRV_V3020 is not set 1120# CONFIG_RTC_DRV_V3020 is not set
1073 1121
1074# 1122#
@@ -1100,7 +1148,6 @@ CONFIG_RTC_DRV_BFIN=y
1100# CONFIG_JFS_FS is not set 1148# CONFIG_JFS_FS is not set
1101# CONFIG_FS_POSIX_ACL is not set 1149# CONFIG_FS_POSIX_ACL is not set
1102# CONFIG_XFS_FS is not set 1150# CONFIG_XFS_FS is not set
1103# CONFIG_GFS2_FS is not set
1104# CONFIG_OCFS2_FS is not set 1151# CONFIG_OCFS2_FS is not set
1105# CONFIG_BTRFS_FS is not set 1152# CONFIG_BTRFS_FS is not set
1106# CONFIG_NILFS2_FS is not set 1153# CONFIG_NILFS2_FS is not set
@@ -1159,6 +1206,7 @@ CONFIG_JFFS2_ZLIB=y
1159# CONFIG_JFFS2_LZO is not set 1206# CONFIG_JFFS2_LZO is not set
1160CONFIG_JFFS2_RTIME=y 1207CONFIG_JFFS2_RTIME=y
1161# CONFIG_JFFS2_RUBIN is not set 1208# CONFIG_JFFS2_RUBIN is not set
1209# CONFIG_LOGFS is not set
1162# CONFIG_CRAMFS is not set 1210# CONFIG_CRAMFS is not set
1163# CONFIG_SQUASHFS is not set 1211# CONFIG_SQUASHFS is not set
1164# CONFIG_VXFS_FS is not set 1212# CONFIG_VXFS_FS is not set
@@ -1183,6 +1231,7 @@ CONFIG_SUNRPC=m
1183# CONFIG_RPCSEC_GSS_SPKM3 is not set 1231# CONFIG_RPCSEC_GSS_SPKM3 is not set
1184CONFIG_SMB_FS=m 1232CONFIG_SMB_FS=m
1185# CONFIG_SMB_NLS_DEFAULT is not set 1233# CONFIG_SMB_NLS_DEFAULT is not set
1234# CONFIG_CEPH_FS is not set
1186# CONFIG_CIFS is not set 1235# CONFIG_CIFS is not set
1187# CONFIG_NCP_FS is not set 1236# CONFIG_NCP_FS is not set
1188# CONFIG_CODA_FS is not set 1237# CONFIG_CODA_FS is not set
@@ -1261,6 +1310,8 @@ CONFIG_SCHED_DEBUG=y
1261# CONFIG_TIMER_STATS is not set 1310# CONFIG_TIMER_STATS is not set
1262# CONFIG_DEBUG_OBJECTS is not set 1311# CONFIG_DEBUG_OBJECTS is not set
1263# CONFIG_DEBUG_SLAB is not set 1312# CONFIG_DEBUG_SLAB is not set
1313# CONFIG_DEBUG_RT_MUTEXES is not set
1314# CONFIG_RT_MUTEX_TESTER is not set
1264# CONFIG_DEBUG_SPINLOCK is not set 1315# CONFIG_DEBUG_SPINLOCK is not set
1265# CONFIG_DEBUG_MUTEXES is not set 1316# CONFIG_DEBUG_MUTEXES is not set
1266# CONFIG_DEBUG_LOCK_ALLOC is not set 1317# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1284,17 +1335,18 @@ CONFIG_DEBUG_INFO=y
1284# CONFIG_RCU_TORTURE_TEST is not set 1335# CONFIG_RCU_TORTURE_TEST is not set
1285# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1336# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1286# CONFIG_BACKTRACE_SELF_TEST is not set 1337# CONFIG_BACKTRACE_SELF_TEST is not set
1338# CONFIG_TRACEHOOK_SELF_TEST is not set
1287# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1339# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1288# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1340# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1341# CONFIG_LKDTM is not set
1289# CONFIG_FAULT_INJECTION is not set 1342# CONFIG_FAULT_INJECTION is not set
1343# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1290# CONFIG_PAGE_POISONING is not set 1344# CONFIG_PAGE_POISONING is not set
1291CONFIG_HAVE_FUNCTION_TRACER=y 1345CONFIG_HAVE_FUNCTION_TRACER=y
1292CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1346CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1347CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1293CONFIG_TRACING_SUPPORT=y 1348CONFIG_TRACING_SUPPORT=y
1294# CONFIG_FTRACE is not set 1349# CONFIG_FTRACE is not set
1295# CONFIG_BRANCH_PROFILE_NONE is not set
1296# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1297# CONFIG_PROFILE_ALL_BRANCHES is not set
1298# CONFIG_DYNAMIC_DEBUG is not set 1350# CONFIG_DYNAMIC_DEBUG is not set
1299# CONFIG_SAMPLES is not set 1351# CONFIG_SAMPLES is not set
1300CONFIG_HAVE_ARCH_KGDB=y 1352CONFIG_HAVE_ARCH_KGDB=y
@@ -1321,6 +1373,7 @@ CONFIG_EARLY_PRINTK=y
1321CONFIG_CPLB_INFO=y 1373CONFIG_CPLB_INFO=y
1322CONFIG_ACCESS_CHECK=y 1374CONFIG_ACCESS_CHECK=y
1323# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1375# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1376# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1324 1377
1325# 1378#
1326# Security options 1379# Security options
@@ -1330,8 +1383,12 @@ CONFIG_SECURITY=y
1330# CONFIG_SECURITYFS is not set 1383# CONFIG_SECURITYFS is not set
1331# CONFIG_SECURITY_NETWORK is not set 1384# CONFIG_SECURITY_NETWORK is not set
1332# CONFIG_SECURITY_PATH is not set 1385# CONFIG_SECURITY_PATH is not set
1333# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1334# CONFIG_SECURITY_TOMOYO is not set 1386# CONFIG_SECURITY_TOMOYO is not set
1387# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1388# CONFIG_DEFAULT_SECURITY_SMACK is not set
1389# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1390CONFIG_DEFAULT_SECURITY_DAC=y
1391CONFIG_DEFAULT_SECURITY=""
1335CONFIG_CRYPTO=y 1392CONFIG_CRYPTO=y
1336 1393
1337# 1394#
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index ca309cfc6ac4..baca6660cf0b 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -107,6 +110,7 @@ CONFIG_SLOW_WORK=y
107# CONFIG_SLOW_WORK_DEBUG is not set 110# CONFIG_SLOW_WORK_DEBUG is not set
108# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 111# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
109CONFIG_SLABINFO=y 112CONFIG_SLABINFO=y
113CONFIG_RT_MUTEXES=y
110CONFIG_BASE_SMALL=0 114CONFIG_BASE_SMALL=0
111CONFIG_MODULES=y 115CONFIG_MODULES=y
112# CONFIG_MODULE_FORCE_LOAD is not set 116# CONFIG_MODULE_FORCE_LOAD is not set
@@ -123,14 +127,41 @@ CONFIG_BLOCK=y
123# IO Schedulers 127# IO Schedulers
124# 128#
125CONFIG_IOSCHED_NOOP=y 129CONFIG_IOSCHED_NOOP=y
126CONFIG_IOSCHED_AS=y
127# CONFIG_IOSCHED_DEADLINE is not set 130# CONFIG_IOSCHED_DEADLINE is not set
128# CONFIG_IOSCHED_CFQ is not set 131# CONFIG_IOSCHED_CFQ is not set
129CONFIG_DEFAULT_AS=y
130# CONFIG_DEFAULT_DEADLINE is not set 132# CONFIG_DEFAULT_DEADLINE is not set
131# CONFIG_DEFAULT_CFQ is not set 133# CONFIG_DEFAULT_CFQ is not set
132# CONFIG_DEFAULT_NOOP is not set 134CONFIG_DEFAULT_NOOP=y
133CONFIG_DEFAULT_IOSCHED="anticipatory" 135CONFIG_DEFAULT_IOSCHED="noop"
136# CONFIG_INLINE_SPIN_TRYLOCK is not set
137# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
138# CONFIG_INLINE_SPIN_LOCK is not set
139# CONFIG_INLINE_SPIN_LOCK_BH is not set
140# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
141# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
142CONFIG_INLINE_SPIN_UNLOCK=y
143# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
144CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
145# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
146# CONFIG_INLINE_READ_TRYLOCK is not set
147# CONFIG_INLINE_READ_LOCK is not set
148# CONFIG_INLINE_READ_LOCK_BH is not set
149# CONFIG_INLINE_READ_LOCK_IRQ is not set
150# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
151CONFIG_INLINE_READ_UNLOCK=y
152# CONFIG_INLINE_READ_UNLOCK_BH is not set
153CONFIG_INLINE_READ_UNLOCK_IRQ=y
154# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
155# CONFIG_INLINE_WRITE_TRYLOCK is not set
156# CONFIG_INLINE_WRITE_LOCK is not set
157# CONFIG_INLINE_WRITE_LOCK_BH is not set
158# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
159# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
160CONFIG_INLINE_WRITE_UNLOCK=y
161# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
162CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
163# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
164# CONFIG_MUTEX_SPIN_ON_OWNER is not set
134# CONFIG_PREEMPT_NONE is not set 165# CONFIG_PREEMPT_NONE is not set
135CONFIG_PREEMPT_VOLUNTARY=y 166CONFIG_PREEMPT_VOLUNTARY=y
136# CONFIG_PREEMPT is not set 167# CONFIG_PREEMPT is not set
@@ -330,8 +361,16 @@ CONFIG_HZ=250
330# CONFIG_SCHED_HRTICK is not set 361# CONFIG_SCHED_HRTICK is not set
331CONFIG_GENERIC_TIME=y 362CONFIG_GENERIC_TIME=y
332CONFIG_GENERIC_CLOCKEVENTS=y 363CONFIG_GENERIC_CLOCKEVENTS=y
364
365#
366# Clock event device
367#
333# CONFIG_TICKSOURCE_GPTMR0 is not set 368# CONFIG_TICKSOURCE_GPTMR0 is not set
334CONFIG_TICKSOURCE_CORETMR=y 369CONFIG_TICKSOURCE_CORETMR=y
370
371#
372# Clock souce
373#
335# CONFIG_CYCLES_CLOCKSOURCE is not set 374# CONFIG_CYCLES_CLOCKSOURCE is not set
336# CONFIG_GPTMR0_CLOCKSOURCE is not set 375# CONFIG_GPTMR0_CLOCKSOURCE is not set
337# CONFIG_NO_HZ is not set 376# CONFIG_NO_HZ is not set
@@ -362,12 +401,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
362CONFIG_ACCESS_OK_L1=y 401CONFIG_ACCESS_OK_L1=y
363# CONFIG_MEMSET_L1 is not set 402# CONFIG_MEMSET_L1 is not set
364# CONFIG_MEMCPY_L1 is not set 403# CONFIG_MEMCPY_L1 is not set
404CONFIG_STRCMP_L1=y
405CONFIG_STRNCMP_L1=y
406CONFIG_STRCPY_L1=y
407CONFIG_STRNCPY_L1=y
365# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set 408# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
366# CONFIG_IP_CHECKSUM_L1 is not set 409# CONFIG_IP_CHECKSUM_L1 is not set
367CONFIG_CACHELINE_ALIGNED_L1=y 410CONFIG_CACHELINE_ALIGNED_L1=y
368# CONFIG_SYSCALL_TAB_L1 is not set 411# CONFIG_SYSCALL_TAB_L1 is not set
369# CONFIG_CPLB_SWITCH_TAB_L1 is not set 412# CONFIG_CPLB_SWITCH_TAB_L1 is not set
370CONFIG_APP_STACK_L1=y 413CONFIG_CACHE_FLUSH_L1=y
371 414
372# 415#
373# Speed Optimizations 416# Speed Optimizations
@@ -472,7 +515,6 @@ CONFIG_NET=y
472# Networking options 515# Networking options
473# 516#
474CONFIG_PACKET=y 517CONFIG_PACKET=y
475# CONFIG_PACKET_MMAP is not set
476CONFIG_UNIX=y 518CONFIG_UNIX=y
477# CONFIG_NET_KEY is not set 519# CONFIG_NET_KEY is not set
478CONFIG_INET=y 520CONFIG_INET=y
@@ -540,6 +582,7 @@ CONFIG_CAN_BCM=m
540# CONFIG_CAN_VCAN is not set 582# CONFIG_CAN_VCAN is not set
541CONFIG_CAN_DEV=m 583CONFIG_CAN_DEV=m
542# CONFIG_CAN_CALC_BITTIMING is not set 584# CONFIG_CAN_CALC_BITTIMING is not set
585# CONFIG_CAN_MCP251X is not set
543CONFIG_CAN_BFIN=m 586CONFIG_CAN_BFIN=m
544# CONFIG_CAN_SJA1000 is not set 587# CONFIG_CAN_SJA1000 is not set
545 588
@@ -595,9 +638,14 @@ CONFIG_SIR_BFIN_DMA=y
595# CONFIG_MCS_FIR is not set 638# CONFIG_MCS_FIR is not set
596# CONFIG_BT is not set 639# CONFIG_BT is not set
597# CONFIG_AF_RXRPC is not set 640# CONFIG_AF_RXRPC is not set
598# CONFIG_WIRELESS is not set 641CONFIG_WIRELESS=y
599CONFIG_WIRELESS_EXT=y 642# CONFIG_CFG80211 is not set
600CONFIG_LIB80211=m 643CONFIG_LIB80211=m
644# CONFIG_LIB80211_DEBUG is not set
645
646#
647# CFG80211 needs to be enabled for MAC80211
648#
601# CONFIG_WIMAX is not set 649# CONFIG_WIMAX is not set
602# CONFIG_RFKILL is not set 650# CONFIG_RFKILL is not set
603# CONFIG_NET_9P is not set 651# CONFIG_NET_9P is not set
@@ -700,8 +748,7 @@ CONFIG_MTD_NAND=y
700# CONFIG_MTD_NAND_MUSEUM_IDS is not set 748# CONFIG_MTD_NAND_MUSEUM_IDS is not set
701CONFIG_MTD_NAND_IDS=y 749CONFIG_MTD_NAND_IDS=y
702CONFIG_MTD_NAND_BF5XX=y 750CONFIG_MTD_NAND_BF5XX=y
703CONFIG_MTD_NAND_BF5XX_HWECC=y 751# CONFIG_MTD_NAND_BF5XX_HWECC is not set
704# CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC is not set
705# CONFIG_MTD_NAND_DISKONCHIP is not set 752# CONFIG_MTD_NAND_DISKONCHIP is not set
706# CONFIG_MTD_NAND_NANDSIM is not set 753# CONFIG_MTD_NAND_NANDSIM is not set
707# CONFIG_MTD_NAND_PLATFORM is not set 754# CONFIG_MTD_NAND_PLATFORM is not set
@@ -721,6 +768,10 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y
721CONFIG_BLK_DEV=y 768CONFIG_BLK_DEV=y
722# CONFIG_BLK_DEV_COW_COMMON is not set 769# CONFIG_BLK_DEV_COW_COMMON is not set
723# CONFIG_BLK_DEV_LOOP is not set 770# CONFIG_BLK_DEV_LOOP is not set
771
772#
773# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
774#
724# CONFIG_BLK_DEV_NBD is not set 775# CONFIG_BLK_DEV_NBD is not set
725# CONFIG_BLK_DEV_UB is not set 776# CONFIG_BLK_DEV_UB is not set
726CONFIG_BLK_DEV_RAM=y 777CONFIG_BLK_DEV_RAM=y
@@ -735,6 +786,9 @@ CONFIG_MISC_DEVICES=y
735# CONFIG_ICS932S401 is not set 786# CONFIG_ICS932S401 is not set
736# CONFIG_ENCLOSURE_SERVICES is not set 787# CONFIG_ENCLOSURE_SERVICES is not set
737# CONFIG_ISL29003 is not set 788# CONFIG_ISL29003 is not set
789# CONFIG_SENSORS_TSL2550 is not set
790# CONFIG_DS1682 is not set
791# CONFIG_TI_DAC7512 is not set
738# CONFIG_C2PORT is not set 792# CONFIG_C2PORT is not set
739 793
740# 794#
@@ -745,12 +799,14 @@ CONFIG_MISC_DEVICES=y
745# CONFIG_EEPROM_LEGACY is not set 799# CONFIG_EEPROM_LEGACY is not set
746# CONFIG_EEPROM_MAX6875 is not set 800# CONFIG_EEPROM_MAX6875 is not set
747# CONFIG_EEPROM_93CX6 is not set 801# CONFIG_EEPROM_93CX6 is not set
802# CONFIG_IWMC3200TOP is not set
748CONFIG_HAVE_IDE=y 803CONFIG_HAVE_IDE=y
749# CONFIG_IDE is not set 804# CONFIG_IDE is not set
750 805
751# 806#
752# SCSI device support 807# SCSI device support
753# 808#
809CONFIG_SCSI_MOD=y
754# CONFIG_RAID_ATTRS is not set 810# CONFIG_RAID_ATTRS is not set
755CONFIG_SCSI=y 811CONFIG_SCSI=y
756CONFIG_SCSI_DMA=y 812CONFIG_SCSI_DMA=y
@@ -819,6 +875,7 @@ CONFIG_PHYLIB=y
819# CONFIG_NATIONAL_PHY is not set 875# CONFIG_NATIONAL_PHY is not set
820# CONFIG_STE10XP is not set 876# CONFIG_STE10XP is not set
821# CONFIG_LSI_ET1011C_PHY is not set 877# CONFIG_LSI_ET1011C_PHY is not set
878# CONFIG_MICREL_PHY is not set
822# CONFIG_FIXED_PHY is not set 879# CONFIG_FIXED_PHY is not set
823# CONFIG_MDIO_BITBANG is not set 880# CONFIG_MDIO_BITBANG is not set
824CONFIG_NET_ETHERNET=y 881CONFIG_NET_ETHERNET=y
@@ -844,14 +901,6 @@ CONFIG_SMSC911X=y
844# CONFIG_NETDEV_1000 is not set 901# CONFIG_NETDEV_1000 is not set
845# CONFIG_NETDEV_10000 is not set 902# CONFIG_NETDEV_10000 is not set
846CONFIG_WLAN=y 903CONFIG_WLAN=y
847# CONFIG_WLAN_PRE80211 is not set
848CONFIG_WLAN_80211=y
849CONFIG_LIBERTAS=m
850# CONFIG_LIBERTAS_USB is not set
851CONFIG_LIBERTAS_SDIO=m
852CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
853# CONFIG_LIBERTAS_SPI is not set
854# CONFIG_LIBERTAS_DEBUG is not set
855# CONFIG_USB_ZD1201 is not set 904# CONFIG_USB_ZD1201 is not set
856# CONFIG_HOSTAP is not set 905# CONFIG_HOSTAP is not set
857 906
@@ -867,6 +916,7 @@ CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
867# CONFIG_USB_PEGASUS is not set 916# CONFIG_USB_PEGASUS is not set
868# CONFIG_USB_RTL8150 is not set 917# CONFIG_USB_RTL8150 is not set
869# CONFIG_USB_USBNET is not set 918# CONFIG_USB_USBNET is not set
919# CONFIG_USB_IPHETH is not set
870# CONFIG_WAN is not set 920# CONFIG_WAN is not set
871# CONFIG_PPP is not set 921# CONFIG_PPP is not set
872# CONFIG_SLIP is not set 922# CONFIG_SLIP is not set
@@ -882,6 +932,7 @@ CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
882CONFIG_INPUT=y 932CONFIG_INPUT=y
883CONFIG_INPUT_FF_MEMLESS=m 933CONFIG_INPUT_FF_MEMLESS=m
884# CONFIG_INPUT_POLLDEV is not set 934# CONFIG_INPUT_POLLDEV is not set
935# CONFIG_INPUT_SPARSEKMAP is not set
885 936
886# 937#
887# Userland interfaces 938# Userland interfaces
@@ -914,9 +965,9 @@ CONFIG_KEYBOARD_BFIN=y
914CONFIG_INPUT_TOUCHSCREEN=y 965CONFIG_INPUT_TOUCHSCREEN=y
915# CONFIG_TOUCHSCREEN_ADS7846 is not set 966# CONFIG_TOUCHSCREEN_ADS7846 is not set
916CONFIG_TOUCHSCREEN_AD7877=m 967CONFIG_TOUCHSCREEN_AD7877=m
917# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
918# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
919# CONFIG_TOUCHSCREEN_AD7879 is not set 968# CONFIG_TOUCHSCREEN_AD7879 is not set
969# CONFIG_TOUCHSCREEN_AD7160 is not set
970# CONFIG_TOUCHSCREEN_DYNAPRO is not set
920# CONFIG_TOUCHSCREEN_EETI is not set 971# CONFIG_TOUCHSCREEN_EETI is not set
921# CONFIG_TOUCHSCREEN_FUJITSU is not set 972# CONFIG_TOUCHSCREEN_FUJITSU is not set
922# CONFIG_TOUCHSCREEN_GUNZE is not set 973# CONFIG_TOUCHSCREEN_GUNZE is not set
@@ -934,6 +985,7 @@ CONFIG_TOUCHSCREEN_AD7877=m
934# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set 985# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
935# CONFIG_TOUCHSCREEN_TSC2007 is not set 986# CONFIG_TOUCHSCREEN_TSC2007 is not set
936CONFIG_INPUT_MISC=y 987CONFIG_INPUT_MISC=y
988# CONFIG_INPUT_AD714X is not set
937# CONFIG_INPUT_ATI_REMOTE is not set 989# CONFIG_INPUT_ATI_REMOTE is not set
938# CONFIG_INPUT_ATI_REMOTE2 is not set 990# CONFIG_INPUT_ATI_REMOTE2 is not set
939# CONFIG_INPUT_KEYSPAN_REMOTE is not set 991# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@@ -941,11 +993,10 @@ CONFIG_INPUT_MISC=y
941# CONFIG_INPUT_YEALINK is not set 993# CONFIG_INPUT_YEALINK is not set
942# CONFIG_INPUT_CM109 is not set 994# CONFIG_INPUT_CM109 is not set
943# CONFIG_INPUT_UINPUT is not set 995# CONFIG_INPUT_UINPUT is not set
996# CONFIG_INPUT_PCF8574 is not set
944# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 997# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
945# CONFIG_INPUT_BFIN_ROTARY is not set 998# CONFIG_INPUT_BFIN_ROTARY is not set
946# CONFIG_INPUT_AD714X is not set
947# CONFIG_INPUT_ADXL34X is not set 999# CONFIG_INPUT_ADXL34X is not set
948# CONFIG_INPUT_PCF8574 is not set
949 1000
950# 1001#
951# Hardware I/O ports 1002# Hardware I/O ports
@@ -993,6 +1044,7 @@ CONFIG_SERIAL_BFIN_UART1=y
993CONFIG_SERIAL_CORE=y 1044CONFIG_SERIAL_CORE=y
994CONFIG_SERIAL_CORE_CONSOLE=y 1045CONFIG_SERIAL_CORE_CONSOLE=y
995# CONFIG_SERIAL_BFIN_SPORT is not set 1046# CONFIG_SERIAL_BFIN_SPORT is not set
1047# CONFIG_SERIAL_TIMBERDALE is not set
996CONFIG_UNIX98_PTYS=y 1048CONFIG_UNIX98_PTYS=y
997# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 1049# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
998# CONFIG_LEGACY_PTYS is not set 1050# CONFIG_LEGACY_PTYS is not set
@@ -1021,6 +1073,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
1021# CONFIG_I2C_GPIO is not set 1073# CONFIG_I2C_GPIO is not set
1022# CONFIG_I2C_OCORES is not set 1074# CONFIG_I2C_OCORES is not set
1023# CONFIG_I2C_SIMTEC is not set 1075# CONFIG_I2C_SIMTEC is not set
1076# CONFIG_I2C_XILINX is not set
1024 1077
1025# 1078#
1026# External I2C/SMBus adapter drivers 1079# External I2C/SMBus adapter drivers
@@ -1034,16 +1087,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
1034# 1087#
1035# CONFIG_I2C_PCA_PLATFORM is not set 1088# CONFIG_I2C_PCA_PLATFORM is not set
1036# CONFIG_I2C_STUB is not set 1089# CONFIG_I2C_STUB is not set
1037
1038#
1039# Miscellaneous I2C Chip support
1040#
1041# CONFIG_DS1682 is not set
1042# CONFIG_SENSORS_TSL2550 is not set
1043# CONFIG_I2C_DEBUG_CORE is not set 1090# CONFIG_I2C_DEBUG_CORE is not set
1044# CONFIG_I2C_DEBUG_ALGO is not set 1091# CONFIG_I2C_DEBUG_ALGO is not set
1045# CONFIG_I2C_DEBUG_BUS is not set 1092# CONFIG_I2C_DEBUG_BUS is not set
1046# CONFIG_I2C_DEBUG_CHIP is not set
1047CONFIG_SPI=y 1093CONFIG_SPI=y
1048# CONFIG_SPI_DEBUG is not set 1094# CONFIG_SPI_DEBUG is not set
1049CONFIG_SPI_MASTER=y 1095CONFIG_SPI_MASTER=y
@@ -1056,6 +1102,8 @@ CONFIG_SPI_BFIN=y
1056# CONFIG_SPI_BFIN_SPORT is not set 1102# CONFIG_SPI_BFIN_SPORT is not set
1057# CONFIG_SPI_BITBANG is not set 1103# CONFIG_SPI_BITBANG is not set
1058# CONFIG_SPI_GPIO is not set 1104# CONFIG_SPI_GPIO is not set
1105# CONFIG_SPI_XILINX is not set
1106# CONFIG_SPI_DESIGNWARE is not set
1059 1107
1060# 1108#
1061# SPI Protocol Masters 1109# SPI Protocol Masters
@@ -1075,10 +1123,12 @@ CONFIG_GPIO_SYSFS=y
1075# 1123#
1076# Memory mapped GPIO expanders: 1124# Memory mapped GPIO expanders:
1077# 1125#
1126# CONFIG_GPIO_IT8761E is not set
1078 1127
1079# 1128#
1080# I2C GPIO expanders: 1129# I2C GPIO expanders:
1081# 1130#
1131# CONFIG_GPIO_MAX7300 is not set
1082# CONFIG_GPIO_MAX732X is not set 1132# CONFIG_GPIO_MAX732X is not set
1083# CONFIG_GPIO_PCA953X is not set 1133# CONFIG_GPIO_PCA953X is not set
1084# CONFIG_GPIO_PCF857X is not set 1134# CONFIG_GPIO_PCF857X is not set
@@ -1126,21 +1176,26 @@ CONFIG_SSB_POSSIBLE=y
1126# Multifunction device drivers 1176# Multifunction device drivers
1127# 1177#
1128# CONFIG_MFD_CORE is not set 1178# CONFIG_MFD_CORE is not set
1179# CONFIG_MFD_88PM860X is not set
1129# CONFIG_MFD_SM501 is not set 1180# CONFIG_MFD_SM501 is not set
1130# CONFIG_HTC_PASIC3 is not set 1181# CONFIG_HTC_PASIC3 is not set
1182# CONFIG_HTC_I2CPLD is not set
1131# CONFIG_UCB1400_CORE is not set 1183# CONFIG_UCB1400_CORE is not set
1132# CONFIG_TPS65010 is not set 1184# CONFIG_TPS65010 is not set
1133# CONFIG_TWL4030_CORE is not set 1185# CONFIG_TWL4030_CORE is not set
1134# CONFIG_MFD_TMIO is not set 1186# CONFIG_MFD_TMIO is not set
1135# CONFIG_PMIC_DA903X is not set 1187# CONFIG_PMIC_DA903X is not set
1136# CONFIG_PMIC_ADP5520 is not set 1188# CONFIG_PMIC_ADP5520 is not set
1189# CONFIG_MFD_MAX8925 is not set
1137# CONFIG_MFD_WM8400 is not set 1190# CONFIG_MFD_WM8400 is not set
1138# CONFIG_MFD_WM831X is not set 1191# CONFIG_MFD_WM831X is not set
1139# CONFIG_MFD_WM8350_I2C is not set 1192# CONFIG_MFD_WM8350_I2C is not set
1193# CONFIG_MFD_WM8994 is not set
1140# CONFIG_MFD_PCF50633 is not set 1194# CONFIG_MFD_PCF50633 is not set
1141# CONFIG_MFD_MC13783 is not set 1195# CONFIG_MFD_MC13783 is not set
1142# CONFIG_AB3100_CORE is not set 1196# CONFIG_AB3100_CORE is not set
1143# CONFIG_EZX_PCAP is not set 1197# CONFIG_EZX_PCAP is not set
1198# CONFIG_AB4500_CORE is not set
1144# CONFIG_REGULATOR is not set 1199# CONFIG_REGULATOR is not set
1145# CONFIG_MEDIA_SUPPORT is not set 1200# CONFIG_MEDIA_SUPPORT is not set
1146 1201
@@ -1239,13 +1294,9 @@ CONFIG_SND_DRIVERS=y
1239# CONFIG_SND_SERIAL_U16550 is not set 1294# CONFIG_SND_SERIAL_U16550 is not set
1240# CONFIG_SND_MPU401 is not set 1295# CONFIG_SND_MPU401 is not set
1241CONFIG_SND_SPI=y 1296CONFIG_SND_SPI=y
1242
1243#
1244# ALSA Blackfin devices
1245#
1246# CONFIG_SND_BFIN_AD73322 is not set
1247CONFIG_SND_USB=y 1297CONFIG_SND_USB=y
1248# CONFIG_SND_USB_AUDIO is not set 1298# CONFIG_SND_USB_AUDIO is not set
1299# CONFIG_SND_USB_UA101 is not set
1249# CONFIG_SND_USB_CAIAQ is not set 1300# CONFIG_SND_USB_CAIAQ is not set
1250CONFIG_SND_SOC=y 1301CONFIG_SND_SOC=y
1251CONFIG_SND_SOC_AC97_BUS=y 1302CONFIG_SND_SOC_AC97_BUS=y
@@ -1279,6 +1330,7 @@ CONFIG_USB_HID=y
1279# 1330#
1280# Special HID drivers 1331# Special HID drivers
1281# 1332#
1333# CONFIG_HID_3M_PCT is not set
1282CONFIG_HID_A4TECH=y 1334CONFIG_HID_A4TECH=y
1283CONFIG_HID_APPLE=y 1335CONFIG_HID_APPLE=y
1284CONFIG_HID_BELKIN=y 1336CONFIG_HID_BELKIN=y
@@ -1294,14 +1346,19 @@ CONFIG_HID_GYRATION=y
1294CONFIG_HID_LOGITECH=y 1346CONFIG_HID_LOGITECH=y
1295# CONFIG_LOGITECH_FF is not set 1347# CONFIG_LOGITECH_FF is not set
1296# CONFIG_LOGIRUMBLEPAD2_FF is not set 1348# CONFIG_LOGIRUMBLEPAD2_FF is not set
1349# CONFIG_LOGIG940_FF is not set
1297CONFIG_HID_MICROSOFT=y 1350CONFIG_HID_MICROSOFT=y
1351# CONFIG_HID_MOSART is not set
1298CONFIG_HID_MONTEREY=y 1352CONFIG_HID_MONTEREY=y
1299# CONFIG_HID_NTRIG is not set 1353# CONFIG_HID_NTRIG is not set
1354# CONFIG_HID_ORTEK is not set
1300CONFIG_HID_PANTHERLORD=y 1355CONFIG_HID_PANTHERLORD=y
1301# CONFIG_PANTHERLORD_FF is not set 1356# CONFIG_PANTHERLORD_FF is not set
1302CONFIG_HID_PETALYNX=y 1357CONFIG_HID_PETALYNX=y
1358# CONFIG_HID_QUANTA is not set
1303CONFIG_HID_SAMSUNG=y 1359CONFIG_HID_SAMSUNG=y
1304CONFIG_HID_SONY=y 1360CONFIG_HID_SONY=y
1361# CONFIG_HID_STANTUM is not set
1305CONFIG_HID_SUNPLUS=y 1362CONFIG_HID_SUNPLUS=y
1306# CONFIG_HID_GREENASIA is not set 1363# CONFIG_HID_GREENASIA is not set
1307# CONFIG_HID_SMARTJOYPLUS is not set 1364# CONFIG_HID_SMARTJOYPLUS is not set
@@ -1322,7 +1379,6 @@ CONFIG_USB=y
1322CONFIG_USB_DEVICEFS=y 1379CONFIG_USB_DEVICEFS=y
1323# CONFIG_USB_DEVICE_CLASS is not set 1380# CONFIG_USB_DEVICE_CLASS is not set
1324# CONFIG_USB_DYNAMIC_MINORS is not set 1381# CONFIG_USB_DYNAMIC_MINORS is not set
1325# CONFIG_USB_OTG is not set
1326# CONFIG_USB_OTG_WHITELIST is not set 1382# CONFIG_USB_OTG_WHITELIST is not set
1327CONFIG_USB_OTG_BLACKLIST_HUB=y 1383CONFIG_USB_OTG_BLACKLIST_HUB=y
1328CONFIG_USB_MON=y 1384CONFIG_USB_MON=y
@@ -1406,7 +1462,6 @@ CONFIG_USB_STORAGE=y
1406# CONFIG_USB_RIO500 is not set 1462# CONFIG_USB_RIO500 is not set
1407# CONFIG_USB_LEGOTOWER is not set 1463# CONFIG_USB_LEGOTOWER is not set
1408# CONFIG_USB_LCD is not set 1464# CONFIG_USB_LCD is not set
1409# CONFIG_USB_BERRY_CHARGE is not set
1410# CONFIG_USB_LED is not set 1465# CONFIG_USB_LED is not set
1411# CONFIG_USB_CYPRESS_CY7C63 is not set 1466# CONFIG_USB_CYPRESS_CY7C63 is not set
1412# CONFIG_USB_CYTHERM is not set 1467# CONFIG_USB_CYTHERM is not set
@@ -1419,7 +1474,6 @@ CONFIG_USB_STORAGE=y
1419# CONFIG_USB_IOWARRIOR is not set 1474# CONFIG_USB_IOWARRIOR is not set
1420# CONFIG_USB_TEST is not set 1475# CONFIG_USB_TEST is not set
1421# CONFIG_USB_ISIGHTFW is not set 1476# CONFIG_USB_ISIGHTFW is not set
1422# CONFIG_USB_VST is not set
1423# CONFIG_USB_GADGET is not set 1477# CONFIG_USB_GADGET is not set
1424 1478
1425# 1479#
@@ -1444,11 +1498,9 @@ CONFIG_MMC_BLOCK_BOUNCE=y
1444# MMC/SD/SDIO Host Controller Drivers 1498# MMC/SD/SDIO Host Controller Drivers
1445# 1499#
1446# CONFIG_MMC_SDHCI is not set 1500# CONFIG_MMC_SDHCI is not set
1447# CONFIG_MMC_AT91 is not set
1448# CONFIG_MMC_ATMELMCI is not set
1449# CONFIG_MMC_SPI is not set 1501# CONFIG_MMC_SPI is not set
1450CONFIG_SDH_BFIN=y 1502CONFIG_SDH_BFIN=y
1451# CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set 1503CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
1452# CONFIG_MEMSTICK is not set 1504# CONFIG_MEMSTICK is not set
1453# CONFIG_NEW_LEDS is not set 1505# CONFIG_NEW_LEDS is not set
1454# CONFIG_ACCESSIBILITY is not set 1506# CONFIG_ACCESSIBILITY is not set
@@ -1480,6 +1532,7 @@ CONFIG_RTC_INTF_DEV=y
1480# CONFIG_RTC_DRV_PCF8563 is not set 1532# CONFIG_RTC_DRV_PCF8563 is not set
1481# CONFIG_RTC_DRV_PCF8583 is not set 1533# CONFIG_RTC_DRV_PCF8583 is not set
1482# CONFIG_RTC_DRV_M41T80 is not set 1534# CONFIG_RTC_DRV_M41T80 is not set
1535# CONFIG_RTC_DRV_BQ32K is not set
1483# CONFIG_RTC_DRV_S35390A is not set 1536# CONFIG_RTC_DRV_S35390A is not set
1484# CONFIG_RTC_DRV_FM3130 is not set 1537# CONFIG_RTC_DRV_FM3130 is not set
1485# CONFIG_RTC_DRV_RX8581 is not set 1538# CONFIG_RTC_DRV_RX8581 is not set
@@ -1508,7 +1561,9 @@ CONFIG_RTC_INTF_DEV=y
1508# CONFIG_RTC_DRV_M48T86 is not set 1561# CONFIG_RTC_DRV_M48T86 is not set
1509# CONFIG_RTC_DRV_M48T35 is not set 1562# CONFIG_RTC_DRV_M48T35 is not set
1510# CONFIG_RTC_DRV_M48T59 is not set 1563# CONFIG_RTC_DRV_M48T59 is not set
1564# CONFIG_RTC_DRV_MSM6242 is not set
1511# CONFIG_RTC_DRV_BQ4802 is not set 1565# CONFIG_RTC_DRV_BQ4802 is not set
1566# CONFIG_RTC_DRV_RP5C01 is not set
1512# CONFIG_RTC_DRV_V3020 is not set 1567# CONFIG_RTC_DRV_V3020 is not set
1513 1568
1514# 1569#
@@ -1609,6 +1664,7 @@ CONFIG_JFFS2_ZLIB=y
1609# CONFIG_JFFS2_LZO is not set 1664# CONFIG_JFFS2_LZO is not set
1610CONFIG_JFFS2_RTIME=y 1665CONFIG_JFFS2_RTIME=y
1611# CONFIG_JFFS2_RUBIN is not set 1666# CONFIG_JFFS2_RUBIN is not set
1667# CONFIG_LOGFS is not set
1612# CONFIG_CRAMFS is not set 1668# CONFIG_CRAMFS is not set
1613# CONFIG_SQUASHFS is not set 1669# CONFIG_SQUASHFS is not set
1614# CONFIG_VXFS_FS is not set 1670# CONFIG_VXFS_FS is not set
@@ -1638,6 +1694,7 @@ CONFIG_SUNRPC=m
1638CONFIG_SMB_FS=m 1694CONFIG_SMB_FS=m
1639CONFIG_SMB_NLS_DEFAULT=y 1695CONFIG_SMB_NLS_DEFAULT=y
1640CONFIG_SMB_NLS_REMOTE="cp437" 1696CONFIG_SMB_NLS_REMOTE="cp437"
1697# CONFIG_CEPH_FS is not set
1641CONFIG_CIFS=y 1698CONFIG_CIFS=y
1642# CONFIG_CIFS_STATS is not set 1699# CONFIG_CIFS_STATS is not set
1643# CONFIG_CIFS_WEAK_PW_HASH is not set 1700# CONFIG_CIFS_WEAK_PW_HASH is not set
@@ -1721,6 +1778,8 @@ CONFIG_SCHED_DEBUG=y
1721# CONFIG_TIMER_STATS is not set 1778# CONFIG_TIMER_STATS is not set
1722# CONFIG_DEBUG_OBJECTS is not set 1779# CONFIG_DEBUG_OBJECTS is not set
1723# CONFIG_DEBUG_SLAB is not set 1780# CONFIG_DEBUG_SLAB is not set
1781# CONFIG_DEBUG_RT_MUTEXES is not set
1782# CONFIG_RT_MUTEX_TESTER is not set
1724# CONFIG_DEBUG_SPINLOCK is not set 1783# CONFIG_DEBUG_SPINLOCK is not set
1725# CONFIG_DEBUG_MUTEXES is not set 1784# CONFIG_DEBUG_MUTEXES is not set
1726# CONFIG_DEBUG_LOCK_ALLOC is not set 1785# CONFIG_DEBUG_LOCK_ALLOC is not set
@@ -1744,12 +1803,16 @@ CONFIG_DEBUG_INFO=y
1744# CONFIG_RCU_TORTURE_TEST is not set 1803# CONFIG_RCU_TORTURE_TEST is not set
1745# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1804# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1746# CONFIG_BACKTRACE_SELF_TEST is not set 1805# CONFIG_BACKTRACE_SELF_TEST is not set
1806# CONFIG_TRACEHOOK_SELF_TEST is not set
1747# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1807# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1748# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1808# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1809# CONFIG_LKDTM is not set
1749# CONFIG_FAULT_INJECTION is not set 1810# CONFIG_FAULT_INJECTION is not set
1811# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1750# CONFIG_PAGE_POISONING is not set 1812# CONFIG_PAGE_POISONING is not set
1751CONFIG_HAVE_FUNCTION_TRACER=y 1813CONFIG_HAVE_FUNCTION_TRACER=y
1752CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1814CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1815CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1753CONFIG_TRACING_SUPPORT=y 1816CONFIG_TRACING_SUPPORT=y
1754# CONFIG_FTRACE is not set 1817# CONFIG_FTRACE is not set
1755# CONFIG_DYNAMIC_DEBUG is not set 1818# CONFIG_DYNAMIC_DEBUG is not set
@@ -1778,6 +1841,7 @@ CONFIG_EARLY_PRINTK=y
1778CONFIG_CPLB_INFO=y 1841CONFIG_CPLB_INFO=y
1779CONFIG_ACCESS_CHECK=y 1842CONFIG_ACCESS_CHECK=y
1780# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1843# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1844# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1781 1845
1782# 1846#
1783# Security options 1847# Security options
@@ -1785,7 +1849,11 @@ CONFIG_ACCESS_CHECK=y
1785# CONFIG_KEYS is not set 1849# CONFIG_KEYS is not set
1786# CONFIG_SECURITY is not set 1850# CONFIG_SECURITY is not set
1787# CONFIG_SECURITYFS is not set 1851# CONFIG_SECURITYFS is not set
1788# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1852# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1853# CONFIG_DEFAULT_SECURITY_SMACK is not set
1854# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1855CONFIG_DEFAULT_SECURITY_DAC=y
1856CONFIG_DEFAULT_SECURITY=""
1789CONFIG_CRYPTO=y 1857CONFIG_CRYPTO=y
1790 1858
1791# 1859#
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
index 6a776ce75e9c..d5ceeab7a906 100644
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
@@ -330,7 +330,6 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y
330CONFIG_CACHELINE_ALIGNED_L1=y 330CONFIG_CACHELINE_ALIGNED_L1=y
331# CONFIG_SYSCALL_TAB_L1 is not set 331# CONFIG_SYSCALL_TAB_L1 is not set
332# CONFIG_CPLB_SWITCH_TAB_L1 is not set 332# CONFIG_CPLB_SWITCH_TAB_L1 is not set
333CONFIG_APP_STACK_L1=y
334 333
335# 334#
336# Speed Optimizations 335# Speed Optimizations
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 792ff0938835..1a5808a9aed3 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
56CONFIG_IKCONFIG=y 59CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y 60CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14 61CONFIG_LOG_BUF_SHIFT=14
59# CONFIG_GROUP_SCHED is not set
60# CONFIG_CGROUPS is not set
61# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
62# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
63# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
@@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 67CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 68# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 69# CONFIG_RD_LZMA is not set
70# CONFIG_RD_LZO is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98CONFIG_MMAP_ALLOW_UNINITIALIZED=y 100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
99# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
100CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
101 104
102# 105#
103# GCOV-based kernel profiling 106# GCOV-based kernel profiling
@@ -122,14 +125,41 @@ CONFIG_BLOCK=y
122# IO Schedulers 125# IO Schedulers
123# 126#
124CONFIG_IOSCHED_NOOP=y 127CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set 128# CONFIG_IOSCHED_DEADLINE is not set
127# CONFIG_IOSCHED_CFQ is not set 129# CONFIG_IOSCHED_CFQ is not set
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set 130# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set 131# CONFIG_DEFAULT_CFQ is not set
131# CONFIG_DEFAULT_NOOP is not set 132CONFIG_DEFAULT_NOOP=y
132CONFIG_DEFAULT_IOSCHED="anticipatory" 133CONFIG_DEFAULT_IOSCHED="noop"
134# CONFIG_INLINE_SPIN_TRYLOCK is not set
135# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
136# CONFIG_INLINE_SPIN_LOCK is not set
137# CONFIG_INLINE_SPIN_LOCK_BH is not set
138# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
140CONFIG_INLINE_SPIN_UNLOCK=y
141# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
142CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
143# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
144# CONFIG_INLINE_READ_TRYLOCK is not set
145# CONFIG_INLINE_READ_LOCK is not set
146# CONFIG_INLINE_READ_LOCK_BH is not set
147# CONFIG_INLINE_READ_LOCK_IRQ is not set
148# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
149CONFIG_INLINE_READ_UNLOCK=y
150# CONFIG_INLINE_READ_UNLOCK_BH is not set
151CONFIG_INLINE_READ_UNLOCK_IRQ=y
152# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
153# CONFIG_INLINE_WRITE_TRYLOCK is not set
154# CONFIG_INLINE_WRITE_LOCK is not set
155# CONFIG_INLINE_WRITE_LOCK_BH is not set
156# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
158CONFIG_INLINE_WRITE_UNLOCK=y
159# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
160CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
161# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
162# CONFIG_MUTEX_SPIN_ON_OWNER is not set
133# CONFIG_PREEMPT_NONE is not set 163# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y 164CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 165# CONFIG_PREEMPT is not set
@@ -293,8 +323,16 @@ CONFIG_HZ=250
293CONFIG_SCHED_HRTICK=y 323CONFIG_SCHED_HRTICK=y
294CONFIG_GENERIC_TIME=y 324CONFIG_GENERIC_TIME=y
295CONFIG_GENERIC_CLOCKEVENTS=y 325CONFIG_GENERIC_CLOCKEVENTS=y
326
327#
328# Clock event device
329#
296# CONFIG_TICKSOURCE_GPTMR0 is not set 330# CONFIG_TICKSOURCE_GPTMR0 is not set
297CONFIG_TICKSOURCE_CORETMR=y 331CONFIG_TICKSOURCE_CORETMR=y
332
333#
334# Clock souce
335#
298CONFIG_CYCLES_CLOCKSOURCE=y 336CONFIG_CYCLES_CLOCKSOURCE=y
299# CONFIG_GPTMR0_CLOCKSOURCE is not set 337# CONFIG_GPTMR0_CLOCKSOURCE is not set
300CONFIG_TICK_ONESHOT=y 338CONFIG_TICK_ONESHOT=y
@@ -326,12 +364,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
326CONFIG_ACCESS_OK_L1=y 364CONFIG_ACCESS_OK_L1=y
327CONFIG_MEMSET_L1=y 365CONFIG_MEMSET_L1=y
328CONFIG_MEMCPY_L1=y 366CONFIG_MEMCPY_L1=y
367CONFIG_STRCMP_L1=y
368CONFIG_STRNCMP_L1=y
369CONFIG_STRCPY_L1=y
370CONFIG_STRNCPY_L1=y
329CONFIG_SYS_BFIN_SPINLOCK_L1=y 371CONFIG_SYS_BFIN_SPINLOCK_L1=y
330# CONFIG_IP_CHECKSUM_L1 is not set 372# CONFIG_IP_CHECKSUM_L1 is not set
331CONFIG_CACHELINE_ALIGNED_L1=y 373CONFIG_CACHELINE_ALIGNED_L1=y
332# CONFIG_SYSCALL_TAB_L1 is not set 374# CONFIG_SYSCALL_TAB_L1 is not set
333# CONFIG_CPLB_SWITCH_TAB_L1 is not set 375# CONFIG_CPLB_SWITCH_TAB_L1 is not set
334CONFIG_APP_STACK_L1=y 376CONFIG_CACHE_FLUSH_L1=y
335 377
336# 378#
337# Speed Optimizations 379# Speed Optimizations
@@ -439,7 +481,6 @@ CONFIG_NET=y
439# Networking options 481# Networking options
440# 482#
441CONFIG_PACKET=y 483CONFIG_PACKET=y
442# CONFIG_PACKET_MMAP is not set
443CONFIG_UNIX=y 484CONFIG_UNIX=y
444# CONFIG_NET_KEY is not set 485# CONFIG_NET_KEY is not set
445CONFIG_INET=y 486CONFIG_INET=y
@@ -643,6 +684,10 @@ CONFIG_MTD_PHYSMAP=m
643CONFIG_BLK_DEV=y 684CONFIG_BLK_DEV=y
644# CONFIG_BLK_DEV_COW_COMMON is not set 685# CONFIG_BLK_DEV_COW_COMMON is not set
645# CONFIG_BLK_DEV_LOOP is not set 686# CONFIG_BLK_DEV_LOOP is not set
687
688#
689# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
690#
646# CONFIG_BLK_DEV_NBD is not set 691# CONFIG_BLK_DEV_NBD is not set
647CONFIG_BLK_DEV_RAM=y 692CONFIG_BLK_DEV_RAM=y
648CONFIG_BLK_DEV_RAM_COUNT=16 693CONFIG_BLK_DEV_RAM_COUNT=16
@@ -652,7 +697,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
652# CONFIG_ATA_OVER_ETH is not set 697# CONFIG_ATA_OVER_ETH is not set
653# CONFIG_BLK_DEV_HD is not set 698# CONFIG_BLK_DEV_HD is not set
654CONFIG_MISC_DEVICES=y 699CONFIG_MISC_DEVICES=y
700# CONFIG_AD525X_DPOT is not set
655# CONFIG_ENCLOSURE_SERVICES is not set 701# CONFIG_ENCLOSURE_SERVICES is not set
702# CONFIG_TI_DAC7512 is not set
656# CONFIG_C2PORT is not set 703# CONFIG_C2PORT is not set
657 704
658# 705#
@@ -666,6 +713,7 @@ CONFIG_HAVE_IDE=y
666# 713#
667# SCSI device support 714# SCSI device support
668# 715#
716CONFIG_SCSI_MOD=y
669# CONFIG_RAID_ATTRS is not set 717# CONFIG_RAID_ATTRS is not set
670# CONFIG_SCSI is not set 718# CONFIG_SCSI is not set
671# CONFIG_SCSI_DMA is not set 719# CONFIG_SCSI_DMA is not set
@@ -722,6 +770,7 @@ CONFIG_SMC91X=y
722CONFIG_INPUT=m 770CONFIG_INPUT=m
723# CONFIG_INPUT_FF_MEMLESS is not set 771# CONFIG_INPUT_FF_MEMLESS is not set
724# CONFIG_INPUT_POLLDEV is not set 772# CONFIG_INPUT_POLLDEV is not set
773# CONFIG_INPUT_SPARSEKMAP is not set
725 774
726# 775#
727# Userland interfaces 776# Userland interfaces
@@ -779,6 +828,7 @@ CONFIG_SERIAL_BFIN_UART0=y
779CONFIG_SERIAL_CORE=y 828CONFIG_SERIAL_CORE=y
780CONFIG_SERIAL_CORE_CONSOLE=y 829CONFIG_SERIAL_CORE_CONSOLE=y
781# CONFIG_SERIAL_BFIN_SPORT is not set 830# CONFIG_SERIAL_BFIN_SPORT is not set
831# CONFIG_SERIAL_TIMBERDALE is not set
782CONFIG_UNIX98_PTYS=y 832CONFIG_UNIX98_PTYS=y
783# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 833# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
784# CONFIG_LEGACY_PTYS is not set 834# CONFIG_LEGACY_PTYS is not set
@@ -800,6 +850,8 @@ CONFIG_SPI_BFIN=y
800# CONFIG_SPI_BFIN_SPORT is not set 850# CONFIG_SPI_BFIN_SPORT is not set
801# CONFIG_SPI_BITBANG is not set 851# CONFIG_SPI_BITBANG is not set
802# CONFIG_SPI_GPIO is not set 852# CONFIG_SPI_GPIO is not set
853# CONFIG_SPI_XILINX is not set
854# CONFIG_SPI_DESIGNWARE is not set
803 855
804# 856#
805# SPI Protocol Masters 857# SPI Protocol Masters
@@ -819,6 +871,7 @@ CONFIG_GPIO_SYSFS=y
819# 871#
820# Memory mapped GPIO expanders: 872# Memory mapped GPIO expanders:
821# 873#
874# CONFIG_GPIO_IT8761E is not set
822 875
823# 876#
824# I2C GPIO expanders: 877# I2C GPIO expanders:
@@ -866,6 +919,7 @@ CONFIG_SSB_POSSIBLE=y
866# CONFIG_MFD_TMIO is not set 919# CONFIG_MFD_TMIO is not set
867# CONFIG_MFD_MC13783 is not set 920# CONFIG_MFD_MC13783 is not set
868# CONFIG_EZX_PCAP is not set 921# CONFIG_EZX_PCAP is not set
922# CONFIG_AB4500_CORE is not set
869# CONFIG_REGULATOR is not set 923# CONFIG_REGULATOR is not set
870# CONFIG_MEDIA_SUPPORT is not set 924# CONFIG_MEDIA_SUPPORT is not set
871 925
@@ -978,6 +1032,7 @@ CONFIG_JFFS2_ZLIB=y
978# CONFIG_JFFS2_LZO is not set 1032# CONFIG_JFFS2_LZO is not set
979CONFIG_JFFS2_RTIME=y 1033CONFIG_JFFS2_RTIME=y
980# CONFIG_JFFS2_RUBIN is not set 1034# CONFIG_JFFS2_RUBIN is not set
1035# CONFIG_LOGFS is not set
981# CONFIG_CRAMFS is not set 1036# CONFIG_CRAMFS is not set
982# CONFIG_SQUASHFS is not set 1037# CONFIG_SQUASHFS is not set
983# CONFIG_VXFS_FS is not set 1038# CONFIG_VXFS_FS is not set
@@ -1002,6 +1057,7 @@ CONFIG_SUNRPC=m
1002# CONFIG_RPCSEC_GSS_SPKM3 is not set 1057# CONFIG_RPCSEC_GSS_SPKM3 is not set
1003CONFIG_SMB_FS=m 1058CONFIG_SMB_FS=m
1004# CONFIG_SMB_NLS_DEFAULT is not set 1059# CONFIG_SMB_NLS_DEFAULT is not set
1060# CONFIG_CEPH_FS is not set
1005# CONFIG_CIFS is not set 1061# CONFIG_CIFS is not set
1006# CONFIG_NCP_FS is not set 1062# CONFIG_NCP_FS is not set
1007# CONFIG_CODA_FS is not set 1063# CONFIG_CODA_FS is not set
@@ -1103,12 +1159,16 @@ CONFIG_DEBUG_INFO=y
1103# CONFIG_RCU_TORTURE_TEST is not set 1159# CONFIG_RCU_TORTURE_TEST is not set
1104# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1160# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1105# CONFIG_BACKTRACE_SELF_TEST is not set 1161# CONFIG_BACKTRACE_SELF_TEST is not set
1162# CONFIG_TRACEHOOK_SELF_TEST is not set
1106# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1163# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1107# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1164# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1165# CONFIG_LKDTM is not set
1108# CONFIG_FAULT_INJECTION is not set 1166# CONFIG_FAULT_INJECTION is not set
1167# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1109# CONFIG_PAGE_POISONING is not set 1168# CONFIG_PAGE_POISONING is not set
1110CONFIG_HAVE_FUNCTION_TRACER=y 1169CONFIG_HAVE_FUNCTION_TRACER=y
1111CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1170CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1171CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1112CONFIG_TRACING_SUPPORT=y 1172CONFIG_TRACING_SUPPORT=y
1113# CONFIG_FTRACE is not set 1173# CONFIG_FTRACE is not set
1114# CONFIG_DYNAMIC_DEBUG is not set 1174# CONFIG_DYNAMIC_DEBUG is not set
@@ -1137,6 +1197,7 @@ CONFIG_EARLY_PRINTK=y
1137CONFIG_CPLB_INFO=y 1197CONFIG_CPLB_INFO=y
1138CONFIG_ACCESS_CHECK=y 1198CONFIG_ACCESS_CHECK=y
1139# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1199# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1200# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1140 1201
1141# 1202#
1142# Security options 1203# Security options
@@ -1144,7 +1205,11 @@ CONFIG_ACCESS_CHECK=y
1144# CONFIG_KEYS is not set 1205# CONFIG_KEYS is not set
1145# CONFIG_SECURITY is not set 1206# CONFIG_SECURITY is not set
1146# CONFIG_SECURITYFS is not set 1207# CONFIG_SECURITYFS is not set
1147# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1208# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1209# CONFIG_DEFAULT_SECURITY_SMACK is not set
1210# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1211CONFIG_DEFAULT_SECURITY_DAC=y
1212CONFIG_DEFAULT_SECURITY=""
1148CONFIG_CRYPTO=y 1213CONFIG_CRYPTO=y
1149 1214
1150# 1215#
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 4432150d89e3..1189095aaff5 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -319,7 +319,6 @@ CONFIG_ACCESS_OK_L1=y
319CONFIG_CACHELINE_ALIGNED_L1=y 319CONFIG_CACHELINE_ALIGNED_L1=y
320# CONFIG_SYSCALL_TAB_L1 is not set 320# CONFIG_SYSCALL_TAB_L1 is not set
321# CONFIG_CPLB_SWITCH_TAB_L1 is not set 321# CONFIG_CPLB_SWITCH_TAB_L1 is not set
322CONFIG_APP_STACK_L1=y
323 322
324# 323#
325# Speed Optimizations 324# Speed Optimizations
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index df56639ab2f2..feffba8f3237 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -279,7 +279,6 @@ CONFIG_IP_CHECKSUM_L1=y
279CONFIG_CACHELINE_ALIGNED_L1=y 279CONFIG_CACHELINE_ALIGNED_L1=y
280CONFIG_SYSCALL_TAB_L1=y 280CONFIG_SYSCALL_TAB_L1=y
281CONFIG_CPLB_SWITCH_TAB_L1=y 281CONFIG_CPLB_SWITCH_TAB_L1=y
282CONFIG_APP_STACK_L1=y
283 282
284# 283#
285# Speed Optimizations 284# Speed Optimizations
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index 22e565c51d66..c3c3a77819f8 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -288,7 +288,6 @@ CONFIG_IP_CHECKSUM_L1=y
288CONFIG_CACHELINE_ALIGNED_L1=y 288CONFIG_CACHELINE_ALIGNED_L1=y
289CONFIG_SYSCALL_TAB_L1=y 289CONFIG_SYSCALL_TAB_L1=y
290CONFIG_CPLB_SWITCH_TAB_L1=y 290CONFIG_CPLB_SWITCH_TAB_L1=y
291CONFIG_APP_STACK_L1=y
292 291
293# 292#
294# Speed Optimizations 293# Speed Optimizations
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index efcc90d2f345..f891d8400dd0 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -288,7 +288,6 @@ CONFIG_IP_CHECKSUM_L1=y
288CONFIG_CACHELINE_ALIGNED_L1=y 288CONFIG_CACHELINE_ALIGNED_L1=y
289CONFIG_SYSCALL_TAB_L1=y 289CONFIG_SYSCALL_TAB_L1=y
290CONFIG_CPLB_SWITCH_TAB_L1=y 290CONFIG_CPLB_SWITCH_TAB_L1=y
291CONFIG_APP_STACK_L1=y
292 291
293# 292#
294# Speed Optimizations 293# Speed Optimizations
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index 7f579cf51127..85ce6a90fe81 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -346,7 +346,6 @@ CONFIG_ACCESS_OK_L1=y
346CONFIG_CACHELINE_ALIGNED_L1=y 346CONFIG_CACHELINE_ALIGNED_L1=y
347# CONFIG_SYSCALL_TAB_L1 is not set 347# CONFIG_SYSCALL_TAB_L1 is not set
348# CONFIG_CPLB_SWITCH_TAB_L1 is not set 348# CONFIG_CPLB_SWITCH_TAB_L1 is not set
349CONFIG_APP_STACK_L1=y
350 349
351# 350#
352# Speed Optimizations 351# Speed Optimizations
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index a6df01dac98a..dfb530190af2 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -318,7 +318,6 @@ CONFIG_IP_CHECKSUM_L1=y
318CONFIG_CACHELINE_ALIGNED_L1=y 318CONFIG_CACHELINE_ALIGNED_L1=y
319CONFIG_SYSCALL_TAB_L1=y 319CONFIG_SYSCALL_TAB_L1=y
320CONFIG_CPLB_SWITCH_TAB_L1=y 320CONFIG_CPLB_SWITCH_TAB_L1=y
321CONFIG_APP_STACK_L1=y
322 321
323# 322#
324# Speed Optimizations 323# Speed Optimizations
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index ad58fede1f41..1c2072dddfa1 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -1,7 +1,8 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32.2 3# Linux kernel version: 2.6.34
4# 4#
5CONFIG_SYMBOL_PREFIX="_"
5# CONFIG_MMU is not set 6# CONFIG_MMU is not set
6# CONFIG_FPU is not set 7# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
@@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
37CONFIG_KERNEL_GZIP=y 38CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set 39# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set 40# CONFIG_KERNEL_LZMA is not set
41# CONFIG_KERNEL_LZO is not set
40CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
@@ -49,13 +51,13 @@ CONFIG_SYSVIPC_SYSCTL=y
49# 51#
50CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
51# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
52# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
53CONFIG_RCU_FANOUT=32 56CONFIG_RCU_FANOUT=32
54# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
55# CONFIG_TREE_RCU_TRACE is not set 58# CONFIG_TREE_RCU_TRACE is not set
56# CONFIG_IKCONFIG is not set 59# CONFIG_IKCONFIG is not set
57CONFIG_LOG_BUF_SHIFT=14 60CONFIG_LOG_BUF_SHIFT=14
58# CONFIG_GROUP_SCHED is not set
59# CONFIG_CGROUPS is not set 61# CONFIG_CGROUPS is not set
60# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
61# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
@@ -92,6 +94,7 @@ CONFIG_SLAB=y
92CONFIG_MMAP_ALLOW_UNINITIALIZED=y 94CONFIG_MMAP_ALLOW_UNINITIALIZED=y
93# CONFIG_PROFILING is not set 95# CONFIG_PROFILING is not set
94CONFIG_HAVE_OPROFILE=y 96CONFIG_HAVE_OPROFILE=y
97CONFIG_HAVE_ARCH_TRACEHOOK=y
95 98
96# 99#
97# GCOV-based kernel profiling 100# GCOV-based kernel profiling
@@ -99,6 +102,7 @@ CONFIG_HAVE_OPROFILE=y
99# CONFIG_SLOW_WORK is not set 102# CONFIG_SLOW_WORK is not set
100# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 103# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
101CONFIG_SLABINFO=y 104CONFIG_SLABINFO=y
105CONFIG_RT_MUTEXES=y
102CONFIG_BASE_SMALL=0 106CONFIG_BASE_SMALL=0
103CONFIG_MODULES=y 107CONFIG_MODULES=y
104# CONFIG_MODULE_FORCE_LOAD is not set 108# CONFIG_MODULE_FORCE_LOAD is not set
@@ -115,14 +119,41 @@ CONFIG_BLOCK=y
115# IO Schedulers 119# IO Schedulers
116# 120#
117CONFIG_IOSCHED_NOOP=y 121CONFIG_IOSCHED_NOOP=y
118CONFIG_IOSCHED_AS=y
119# CONFIG_IOSCHED_DEADLINE is not set 122# CONFIG_IOSCHED_DEADLINE is not set
120CONFIG_IOSCHED_CFQ=y 123CONFIG_IOSCHED_CFQ=y
121CONFIG_DEFAULT_AS=y
122# CONFIG_DEFAULT_DEADLINE is not set 124# CONFIG_DEFAULT_DEADLINE is not set
123# CONFIG_DEFAULT_CFQ is not set 125CONFIG_DEFAULT_CFQ=y
124# CONFIG_DEFAULT_NOOP is not set 126# CONFIG_DEFAULT_NOOP is not set
125CONFIG_DEFAULT_IOSCHED="anticipatory" 127CONFIG_DEFAULT_IOSCHED="cfq"
128# CONFIG_INLINE_SPIN_TRYLOCK is not set
129# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
130# CONFIG_INLINE_SPIN_LOCK is not set
131# CONFIG_INLINE_SPIN_LOCK_BH is not set
132# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
133# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
134CONFIG_INLINE_SPIN_UNLOCK=y
135# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
136CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
137# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
138# CONFIG_INLINE_READ_TRYLOCK is not set
139# CONFIG_INLINE_READ_LOCK is not set
140# CONFIG_INLINE_READ_LOCK_BH is not set
141# CONFIG_INLINE_READ_LOCK_IRQ is not set
142# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
143CONFIG_INLINE_READ_UNLOCK=y
144# CONFIG_INLINE_READ_UNLOCK_BH is not set
145CONFIG_INLINE_READ_UNLOCK_IRQ=y
146# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
147# CONFIG_INLINE_WRITE_TRYLOCK is not set
148# CONFIG_INLINE_WRITE_LOCK is not set
149# CONFIG_INLINE_WRITE_LOCK_BH is not set
150# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
151# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
152CONFIG_INLINE_WRITE_UNLOCK=y
153# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
154CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
155# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
156# CONFIG_MUTEX_SPIN_ON_OWNER is not set
126# CONFIG_PREEMPT_NONE is not set 157# CONFIG_PREEMPT_NONE is not set
127CONFIG_PREEMPT_VOLUNTARY=y 158CONFIG_PREEMPT_VOLUNTARY=y
128# CONFIG_PREEMPT is not set 159# CONFIG_PREEMPT is not set
@@ -255,8 +286,16 @@ CONFIG_HZ=250
255# CONFIG_SCHED_HRTICK is not set 286# CONFIG_SCHED_HRTICK is not set
256CONFIG_GENERIC_TIME=y 287CONFIG_GENERIC_TIME=y
257CONFIG_GENERIC_CLOCKEVENTS=y 288CONFIG_GENERIC_CLOCKEVENTS=y
289
290#
291# Clock event device
292#
258# CONFIG_TICKSOURCE_GPTMR0 is not set 293# CONFIG_TICKSOURCE_GPTMR0 is not set
259CONFIG_TICKSOURCE_CORETMR=y 294CONFIG_TICKSOURCE_CORETMR=y
295
296#
297# Clock souce
298#
260# CONFIG_CYCLES_CLOCKSOURCE is not set 299# CONFIG_CYCLES_CLOCKSOURCE is not set
261# CONFIG_GPTMR0_CLOCKSOURCE is not set 300# CONFIG_GPTMR0_CLOCKSOURCE is not set
262# CONFIG_NO_HZ is not set 301# CONFIG_NO_HZ is not set
@@ -287,12 +326,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
287CONFIG_ACCESS_OK_L1=y 326CONFIG_ACCESS_OK_L1=y
288CONFIG_MEMSET_L1=y 327CONFIG_MEMSET_L1=y
289CONFIG_MEMCPY_L1=y 328CONFIG_MEMCPY_L1=y
329CONFIG_STRCMP_L1=y
330CONFIG_STRNCMP_L1=y
331CONFIG_STRCPY_L1=y
332CONFIG_STRNCPY_L1=y
290CONFIG_SYS_BFIN_SPINLOCK_L1=y 333CONFIG_SYS_BFIN_SPINLOCK_L1=y
291CONFIG_IP_CHECKSUM_L1=y 334CONFIG_IP_CHECKSUM_L1=y
292CONFIG_CACHELINE_ALIGNED_L1=y 335CONFIG_CACHELINE_ALIGNED_L1=y
293CONFIG_SYSCALL_TAB_L1=y 336CONFIG_SYSCALL_TAB_L1=y
294CONFIG_CPLB_SWITCH_TAB_L1=y 337CONFIG_CPLB_SWITCH_TAB_L1=y
295CONFIG_APP_STACK_L1=y 338CONFIG_CACHE_FLUSH_L1=y
296 339
297# 340#
298# Speed Optimizations 341# Speed Optimizations
@@ -392,7 +435,6 @@ CONFIG_NET=y
392# Networking options 435# Networking options
393# 436#
394CONFIG_PACKET=y 437CONFIG_PACKET=y
395# CONFIG_PACKET_MMAP is not set
396CONFIG_UNIX=y 438CONFIG_UNIX=y
397# CONFIG_NET_KEY is not set 439# CONFIG_NET_KEY is not set
398CONFIG_INET=y 440CONFIG_INET=y
@@ -562,6 +604,10 @@ CONFIG_MTD_NAND_IDS=y
562CONFIG_BLK_DEV=y 604CONFIG_BLK_DEV=y
563# CONFIG_BLK_DEV_COW_COMMON is not set 605# CONFIG_BLK_DEV_COW_COMMON is not set
564# CONFIG_BLK_DEV_LOOP is not set 606# CONFIG_BLK_DEV_LOOP is not set
607
608#
609# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
610#
565# CONFIG_BLK_DEV_NBD is not set 611# CONFIG_BLK_DEV_NBD is not set
566CONFIG_BLK_DEV_RAM=y 612CONFIG_BLK_DEV_RAM=y
567CONFIG_BLK_DEV_RAM_COUNT=16 613CONFIG_BLK_DEV_RAM_COUNT=16
@@ -575,6 +621,9 @@ CONFIG_MISC_DEVICES=y
575# CONFIG_ICS932S401 is not set 621# CONFIG_ICS932S401 is not set
576# CONFIG_ENCLOSURE_SERVICES is not set 622# CONFIG_ENCLOSURE_SERVICES is not set
577# CONFIG_ISL29003 is not set 623# CONFIG_ISL29003 is not set
624# CONFIG_SENSORS_TSL2550 is not set
625# CONFIG_DS1682 is not set
626# CONFIG_TI_DAC7512 is not set
578# CONFIG_C2PORT is not set 627# CONFIG_C2PORT is not set
579 628
580# 629#
@@ -591,6 +640,7 @@ CONFIG_HAVE_IDE=y
591# 640#
592# SCSI device support 641# SCSI device support
593# 642#
643CONFIG_SCSI_MOD=y
594# CONFIG_RAID_ATTRS is not set 644# CONFIG_RAID_ATTRS is not set
595# CONFIG_SCSI is not set 645# CONFIG_SCSI is not set
596# CONFIG_SCSI_DMA is not set 646# CONFIG_SCSI_DMA is not set
@@ -622,6 +672,7 @@ CONFIG_PHYLIB=y
622# CONFIG_NATIONAL_PHY is not set 672# CONFIG_NATIONAL_PHY is not set
623# CONFIG_STE10XP is not set 673# CONFIG_STE10XP is not set
624# CONFIG_LSI_ET1011C_PHY is not set 674# CONFIG_LSI_ET1011C_PHY is not set
675# CONFIG_MICREL_PHY is not set
625# CONFIG_FIXED_PHY is not set 676# CONFIG_FIXED_PHY is not set
626# CONFIG_MDIO_BITBANG is not set 677# CONFIG_MDIO_BITBANG is not set
627CONFIG_NET_ETHERNET=y 678CONFIG_NET_ETHERNET=y
@@ -630,7 +681,6 @@ CONFIG_BFIN_MAC=y
630# CONFIG_BFIN_MAC_USE_L1 is not set 681# CONFIG_BFIN_MAC_USE_L1 is not set
631CONFIG_BFIN_TX_DESC_NUM=100 682CONFIG_BFIN_TX_DESC_NUM=100
632CONFIG_BFIN_RX_DESC_NUM=100 683CONFIG_BFIN_RX_DESC_NUM=100
633CONFIG_BFIN_MAC_RMII=y
634# CONFIG_SMC91X is not set 684# CONFIG_SMC91X is not set
635# CONFIG_DM9000 is not set 685# CONFIG_DM9000 is not set
636# CONFIG_ENC28J60 is not set 686# CONFIG_ENC28J60 is not set
@@ -671,6 +721,7 @@ CONFIG_BFIN_MAC_RMII=y
671CONFIG_INPUT=y 721CONFIG_INPUT=y
672# CONFIG_INPUT_FF_MEMLESS is not set 722# CONFIG_INPUT_FF_MEMLESS is not set
673# CONFIG_INPUT_POLLDEV is not set 723# CONFIG_INPUT_POLLDEV is not set
724# CONFIG_INPUT_SPARSEKMAP is not set
674 725
675# 726#
676# Userland interfaces 727# Userland interfaces
@@ -690,9 +741,9 @@ CONFIG_INPUT_EVDEV=y
690CONFIG_INPUT_TOUCHSCREEN=y 741CONFIG_INPUT_TOUCHSCREEN=y
691# CONFIG_TOUCHSCREEN_ADS7846 is not set 742# CONFIG_TOUCHSCREEN_ADS7846 is not set
692CONFIG_TOUCHSCREEN_AD7877=y 743CONFIG_TOUCHSCREEN_AD7877=y
693# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
694# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
695# CONFIG_TOUCHSCREEN_AD7879 is not set 744# CONFIG_TOUCHSCREEN_AD7879 is not set
745# CONFIG_TOUCHSCREEN_AD7160 is not set
746# CONFIG_TOUCHSCREEN_DYNAPRO is not set
696# CONFIG_TOUCHSCREEN_EETI is not set 747# CONFIG_TOUCHSCREEN_EETI is not set
697# CONFIG_TOUCHSCREEN_FUJITSU is not set 748# CONFIG_TOUCHSCREEN_FUJITSU is not set
698# CONFIG_TOUCHSCREEN_GUNZE is not set 749# CONFIG_TOUCHSCREEN_GUNZE is not set
@@ -709,6 +760,7 @@ CONFIG_TOUCHSCREEN_AD7877=y
709# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set 760# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
710# CONFIG_TOUCHSCREEN_TSC2007 is not set 761# CONFIG_TOUCHSCREEN_TSC2007 is not set
711CONFIG_INPUT_MISC=y 762CONFIG_INPUT_MISC=y
763# CONFIG_INPUT_AD714X is not set
712# CONFIG_INPUT_ATI_REMOTE is not set 764# CONFIG_INPUT_ATI_REMOTE is not set
713# CONFIG_INPUT_ATI_REMOTE2 is not set 765# CONFIG_INPUT_ATI_REMOTE2 is not set
714# CONFIG_INPUT_KEYSPAN_REMOTE is not set 766# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@@ -716,9 +768,8 @@ CONFIG_INPUT_MISC=y
716# CONFIG_INPUT_YEALINK is not set 768# CONFIG_INPUT_YEALINK is not set
717# CONFIG_INPUT_CM109 is not set 769# CONFIG_INPUT_CM109 is not set
718CONFIG_INPUT_UINPUT=y 770CONFIG_INPUT_UINPUT=y
719# CONFIG_INPUT_AD714X is not set
720# CONFIG_INPUT_ADXL34X is not set
721# CONFIG_INPUT_PCF8574 is not set 771# CONFIG_INPUT_PCF8574 is not set
772# CONFIG_INPUT_ADXL34X is not set
722 773
723# 774#
724# Hardware I/O ports 775# Hardware I/O ports
@@ -761,6 +812,7 @@ CONFIG_SERIAL_BFIN_UART1=y
761CONFIG_SERIAL_CORE=y 812CONFIG_SERIAL_CORE=y
762CONFIG_SERIAL_CORE_CONSOLE=y 813CONFIG_SERIAL_CORE_CONSOLE=y
763# CONFIG_SERIAL_BFIN_SPORT is not set 814# CONFIG_SERIAL_BFIN_SPORT is not set
815# CONFIG_SERIAL_TIMBERDALE is not set
764CONFIG_UNIX98_PTYS=y 816CONFIG_UNIX98_PTYS=y
765# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 817# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
766# CONFIG_LEGACY_PTYS is not set 818# CONFIG_LEGACY_PTYS is not set
@@ -788,6 +840,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
788# CONFIG_I2C_GPIO is not set 840# CONFIG_I2C_GPIO is not set
789# CONFIG_I2C_OCORES is not set 841# CONFIG_I2C_OCORES is not set
790# CONFIG_I2C_SIMTEC is not set 842# CONFIG_I2C_SIMTEC is not set
843# CONFIG_I2C_XILINX is not set
791 844
792# 845#
793# External I2C/SMBus adapter drivers 846# External I2C/SMBus adapter drivers
@@ -800,16 +853,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
800# 853#
801# CONFIG_I2C_PCA_PLATFORM is not set 854# CONFIG_I2C_PCA_PLATFORM is not set
802# CONFIG_I2C_STUB is not set 855# CONFIG_I2C_STUB is not set
803
804#
805# Miscellaneous I2C Chip support
806#
807# CONFIG_DS1682 is not set
808# CONFIG_SENSORS_TSL2550 is not set
809# CONFIG_I2C_DEBUG_CORE is not set 856# CONFIG_I2C_DEBUG_CORE is not set
810# CONFIG_I2C_DEBUG_ALGO is not set 857# CONFIG_I2C_DEBUG_ALGO is not set
811# CONFIG_I2C_DEBUG_BUS is not set 858# CONFIG_I2C_DEBUG_BUS is not set
812# CONFIG_I2C_DEBUG_CHIP is not set
813CONFIG_SPI=y 859CONFIG_SPI=y
814CONFIG_SPI_MASTER=y 860CONFIG_SPI_MASTER=y
815 861
@@ -821,6 +867,8 @@ CONFIG_SPI_BFIN=y
821# CONFIG_SPI_BFIN_SPORT is not set 867# CONFIG_SPI_BFIN_SPORT is not set
822# CONFIG_SPI_BITBANG is not set 868# CONFIG_SPI_BITBANG is not set
823# CONFIG_SPI_GPIO is not set 869# CONFIG_SPI_GPIO is not set
870# CONFIG_SPI_XILINX is not set
871# CONFIG_SPI_DESIGNWARE is not set
824 872
825# 873#
826# SPI Protocol Masters 874# SPI Protocol Masters
@@ -852,10 +900,11 @@ CONFIG_HWMON=y
852# CONFIG_SENSORS_ADM1029 is not set 900# CONFIG_SENSORS_ADM1029 is not set
853# CONFIG_SENSORS_ADM1031 is not set 901# CONFIG_SENSORS_ADM1031 is not set
854# CONFIG_SENSORS_ADM9240 is not set 902# CONFIG_SENSORS_ADM9240 is not set
903# CONFIG_SENSORS_ADT7411 is not set
855# CONFIG_SENSORS_ADT7462 is not set 904# CONFIG_SENSORS_ADT7462 is not set
856# CONFIG_SENSORS_ADT7470 is not set 905# CONFIG_SENSORS_ADT7470 is not set
857# CONFIG_SENSORS_ADT7473 is not set
858# CONFIG_SENSORS_ADT7475 is not set 906# CONFIG_SENSORS_ADT7475 is not set
907# CONFIG_SENSORS_ASC7621 is not set
859# CONFIG_SENSORS_ATXP1 is not set 908# CONFIG_SENSORS_ATXP1 is not set
860# CONFIG_SENSORS_DS1621 is not set 909# CONFIG_SENSORS_DS1621 is not set
861# CONFIG_SENSORS_F71805F is not set 910# CONFIG_SENSORS_F71805F is not set
@@ -867,6 +916,7 @@ CONFIG_HWMON=y
867# CONFIG_SENSORS_IT87 is not set 916# CONFIG_SENSORS_IT87 is not set
868# CONFIG_SENSORS_LM63 is not set 917# CONFIG_SENSORS_LM63 is not set
869# CONFIG_SENSORS_LM70 is not set 918# CONFIG_SENSORS_LM70 is not set
919# CONFIG_SENSORS_LM73 is not set
870# CONFIG_SENSORS_LM75 is not set 920# CONFIG_SENSORS_LM75 is not set
871# CONFIG_SENSORS_LM77 is not set 921# CONFIG_SENSORS_LM77 is not set
872# CONFIG_SENSORS_LM78 is not set 922# CONFIG_SENSORS_LM78 is not set
@@ -892,6 +942,7 @@ CONFIG_HWMON=y
892# CONFIG_SENSORS_SMSC47M192 is not set 942# CONFIG_SENSORS_SMSC47M192 is not set
893# CONFIG_SENSORS_SMSC47B397 is not set 943# CONFIG_SENSORS_SMSC47B397 is not set
894# CONFIG_SENSORS_ADS7828 is not set 944# CONFIG_SENSORS_ADS7828 is not set
945# CONFIG_SENSORS_AMC6821 is not set
895# CONFIG_SENSORS_THMC50 is not set 946# CONFIG_SENSORS_THMC50 is not set
896# CONFIG_SENSORS_TMP401 is not set 947# CONFIG_SENSORS_TMP401 is not set
897# CONFIG_SENSORS_TMP421 is not set 948# CONFIG_SENSORS_TMP421 is not set
@@ -905,6 +956,7 @@ CONFIG_HWMON=y
905# CONFIG_SENSORS_W83627HF is not set 956# CONFIG_SENSORS_W83627HF is not set
906# CONFIG_SENSORS_W83627EHF is not set 957# CONFIG_SENSORS_W83627EHF is not set
907# CONFIG_SENSORS_LIS3_SPI is not set 958# CONFIG_SENSORS_LIS3_SPI is not set
959# CONFIG_SENSORS_LIS3_I2C is not set
908# CONFIG_THERMAL is not set 960# CONFIG_THERMAL is not set
909# CONFIG_WATCHDOG is not set 961# CONFIG_WATCHDOG is not set
910CONFIG_SSB_POSSIBLE=y 962CONFIG_SSB_POSSIBLE=y
@@ -918,19 +970,23 @@ CONFIG_SSB_POSSIBLE=y
918# Multifunction device drivers 970# Multifunction device drivers
919# 971#
920# CONFIG_MFD_CORE is not set 972# CONFIG_MFD_CORE is not set
973# CONFIG_MFD_88PM860X is not set
921# CONFIG_MFD_SM501 is not set 974# CONFIG_MFD_SM501 is not set
922# CONFIG_HTC_PASIC3 is not set 975# CONFIG_HTC_PASIC3 is not set
923# CONFIG_TWL4030_CORE is not set 976# CONFIG_TWL4030_CORE is not set
924# CONFIG_MFD_TMIO is not set 977# CONFIG_MFD_TMIO is not set
925# CONFIG_PMIC_DA903X is not set 978# CONFIG_PMIC_DA903X is not set
926# CONFIG_PMIC_ADP5520 is not set 979# CONFIG_PMIC_ADP5520 is not set
980# CONFIG_MFD_MAX8925 is not set
927# CONFIG_MFD_WM8400 is not set 981# CONFIG_MFD_WM8400 is not set
928# CONFIG_MFD_WM831X is not set 982# CONFIG_MFD_WM831X is not set
929# CONFIG_MFD_WM8350_I2C is not set 983# CONFIG_MFD_WM8350_I2C is not set
984# CONFIG_MFD_WM8994 is not set
930# CONFIG_MFD_PCF50633 is not set 985# CONFIG_MFD_PCF50633 is not set
931# CONFIG_MFD_MC13783 is not set 986# CONFIG_MFD_MC13783 is not set
932# CONFIG_AB3100_CORE is not set 987# CONFIG_AB3100_CORE is not set
933# CONFIG_EZX_PCAP is not set 988# CONFIG_EZX_PCAP is not set
989# CONFIG_AB4500_CORE is not set
934# CONFIG_REGULATOR is not set 990# CONFIG_REGULATOR is not set
935# CONFIG_MEDIA_SUPPORT is not set 991# CONFIG_MEDIA_SUPPORT is not set
936 992
@@ -973,6 +1029,7 @@ CONFIG_FB_BF537_LQ035=y
973# CONFIG_FB_BROADSHEET is not set 1029# CONFIG_FB_BROADSHEET is not set
974CONFIG_BACKLIGHT_LCD_SUPPORT=y 1030CONFIG_BACKLIGHT_LCD_SUPPORT=y
975CONFIG_LCD_CLASS_DEVICE=y 1031CONFIG_LCD_CLASS_DEVICE=y
1032# CONFIG_LCD_L4F00242T03 is not set
976# CONFIG_LCD_LMS283GF05 is not set 1033# CONFIG_LCD_LMS283GF05 is not set
977# CONFIG_LCD_LTV350QV is not set 1034# CONFIG_LCD_LTV350QV is not set
978# CONFIG_LCD_ILI9320 is not set 1035# CONFIG_LCD_ILI9320 is not set
@@ -981,6 +1038,7 @@ CONFIG_LCD_CLASS_DEVICE=y
981# CONFIG_LCD_PLATFORM is not set 1038# CONFIG_LCD_PLATFORM is not set
982CONFIG_BACKLIGHT_CLASS_DEVICE=y 1039CONFIG_BACKLIGHT_CLASS_DEVICE=y
983CONFIG_BACKLIGHT_GENERIC=y 1040CONFIG_BACKLIGHT_GENERIC=y
1041# CONFIG_BACKLIGHT_ADP8860 is not set
984# CONFIG_BACKLIGHT_ADP8870 is not set 1042# CONFIG_BACKLIGHT_ADP8870 is not set
985 1043
986# 1044#
@@ -1011,11 +1069,6 @@ CONFIG_SND_DRIVERS=y
1011# CONFIG_SND_SERIAL_U16550 is not set 1069# CONFIG_SND_SERIAL_U16550 is not set
1012# CONFIG_SND_MPU401 is not set 1070# CONFIG_SND_MPU401 is not set
1013CONFIG_SND_SPI=y 1071CONFIG_SND_SPI=y
1014
1015#
1016# ALSA Blackfin devices
1017#
1018# CONFIG_SND_BFIN_AD73322 is not set
1019# CONFIG_SND_SOC is not set 1072# CONFIG_SND_SOC is not set
1020CONFIG_SOUND_PRIME=y 1073CONFIG_SOUND_PRIME=y
1021CONFIG_HID_SUPPORT=y 1074CONFIG_HID_SUPPORT=y
@@ -1073,6 +1126,7 @@ CONFIG_RTC_INTF_DEV=y
1073# CONFIG_RTC_DRV_PCF8563 is not set 1126# CONFIG_RTC_DRV_PCF8563 is not set
1074# CONFIG_RTC_DRV_PCF8583 is not set 1127# CONFIG_RTC_DRV_PCF8583 is not set
1075# CONFIG_RTC_DRV_M41T80 is not set 1128# CONFIG_RTC_DRV_M41T80 is not set
1129# CONFIG_RTC_DRV_BQ32K is not set
1076# CONFIG_RTC_DRV_S35390A is not set 1130# CONFIG_RTC_DRV_S35390A is not set
1077# CONFIG_RTC_DRV_FM3130 is not set 1131# CONFIG_RTC_DRV_FM3130 is not set
1078# CONFIG_RTC_DRV_RX8581 is not set 1132# CONFIG_RTC_DRV_RX8581 is not set
@@ -1101,7 +1155,9 @@ CONFIG_RTC_INTF_DEV=y
1101# CONFIG_RTC_DRV_M48T86 is not set 1155# CONFIG_RTC_DRV_M48T86 is not set
1102# CONFIG_RTC_DRV_M48T35 is not set 1156# CONFIG_RTC_DRV_M48T35 is not set
1103# CONFIG_RTC_DRV_M48T59 is not set 1157# CONFIG_RTC_DRV_M48T59 is not set
1158# CONFIG_RTC_DRV_MSM6242 is not set
1104# CONFIG_RTC_DRV_BQ4802 is not set 1159# CONFIG_RTC_DRV_BQ4802 is not set
1160# CONFIG_RTC_DRV_RP5C01 is not set
1105# CONFIG_RTC_DRV_V3020 is not set 1161# CONFIG_RTC_DRV_V3020 is not set
1106 1162
1107# 1163#
@@ -1137,7 +1193,6 @@ CONFIG_FS_MBCACHE=y
1137# CONFIG_JFS_FS is not set 1193# CONFIG_JFS_FS is not set
1138# CONFIG_FS_POSIX_ACL is not set 1194# CONFIG_FS_POSIX_ACL is not set
1139# CONFIG_XFS_FS is not set 1195# CONFIG_XFS_FS is not set
1140# CONFIG_GFS2_FS is not set
1141# CONFIG_OCFS2_FS is not set 1196# CONFIG_OCFS2_FS is not set
1142# CONFIG_BTRFS_FS is not set 1197# CONFIG_BTRFS_FS is not set
1143# CONFIG_NILFS2_FS is not set 1198# CONFIG_NILFS2_FS is not set
@@ -1186,6 +1241,7 @@ CONFIG_MISC_FILESYSTEMS=y
1186# CONFIG_BFS_FS is not set 1241# CONFIG_BFS_FS is not set
1187# CONFIG_EFS_FS is not set 1242# CONFIG_EFS_FS is not set
1188# CONFIG_JFFS2_FS is not set 1243# CONFIG_JFFS2_FS is not set
1244# CONFIG_LOGFS is not set
1189# CONFIG_CRAMFS is not set 1245# CONFIG_CRAMFS is not set
1190# CONFIG_SQUASHFS is not set 1246# CONFIG_SQUASHFS is not set
1191# CONFIG_VXFS_FS is not set 1247# CONFIG_VXFS_FS is not set
@@ -1210,6 +1266,7 @@ CONFIG_SUNRPC=m
1210# CONFIG_RPCSEC_GSS_SPKM3 is not set 1266# CONFIG_RPCSEC_GSS_SPKM3 is not set
1211CONFIG_SMB_FS=m 1267CONFIG_SMB_FS=m
1212# CONFIG_SMB_NLS_DEFAULT is not set 1268# CONFIG_SMB_NLS_DEFAULT is not set
1269# CONFIG_CEPH_FS is not set
1213# CONFIG_CIFS is not set 1270# CONFIG_CIFS is not set
1214# CONFIG_NCP_FS is not set 1271# CONFIG_NCP_FS is not set
1215# CONFIG_CODA_FS is not set 1272# CONFIG_CODA_FS is not set
@@ -1276,11 +1333,14 @@ CONFIG_FRAME_WARN=1024
1276# CONFIG_HEADERS_CHECK is not set 1333# CONFIG_HEADERS_CHECK is not set
1277CONFIG_DEBUG_SECTION_MISMATCH=y 1334CONFIG_DEBUG_SECTION_MISMATCH=y
1278# CONFIG_DEBUG_KERNEL is not set 1335# CONFIG_DEBUG_KERNEL is not set
1279# CONFIG_DEBUG_BUGVERBOSE is not set 1336CONFIG_DEBUG_BUGVERBOSE=y
1280# CONFIG_DEBUG_MEMORY_INIT is not set 1337# CONFIG_DEBUG_MEMORY_INIT is not set
1281# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1338# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1339# CONFIG_TRACEHOOK_SELF_TEST is not set
1340# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1282CONFIG_HAVE_FUNCTION_TRACER=y 1341CONFIG_HAVE_FUNCTION_TRACER=y
1283CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 1342CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1343CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1284CONFIG_TRACING_SUPPORT=y 1344CONFIG_TRACING_SUPPORT=y
1285# CONFIG_FTRACE is not set 1345# CONFIG_FTRACE is not set
1286# CONFIG_SAMPLES is not set 1346# CONFIG_SAMPLES is not set
@@ -1300,6 +1360,7 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1300# CONFIG_CPLB_INFO is not set 1360# CONFIG_CPLB_INFO is not set
1301# CONFIG_ACCESS_CHECK is not set 1361# CONFIG_ACCESS_CHECK is not set
1302# CONFIG_BFIN_ISRAM_SELF_TEST is not set 1362# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1363# CONFIG_BFIN_PSEUDODBG_INSNS is not set
1303 1364
1304# 1365#
1305# Security options 1366# Security options
@@ -1309,8 +1370,12 @@ CONFIG_SECURITY=y
1309# CONFIG_SECURITYFS is not set 1370# CONFIG_SECURITYFS is not set
1310# CONFIG_SECURITY_NETWORK is not set 1371# CONFIG_SECURITY_NETWORK is not set
1311# CONFIG_SECURITY_PATH is not set 1372# CONFIG_SECURITY_PATH is not set
1312# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1313# CONFIG_SECURITY_TOMOYO is not set 1373# CONFIG_SECURITY_TOMOYO is not set
1374# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1375# CONFIG_DEFAULT_SECURITY_SMACK is not set
1376# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1377CONFIG_DEFAULT_SECURITY_DAC=y
1378CONFIG_DEFAULT_SECURITY=""
1314CONFIG_CRYPTO=y 1379CONFIG_CRYPTO=y
1315 1380
1316# 1381#
diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig
index 4d31e2a4ed46..cdf4c00f2c49 100644
--- a/arch/blackfin/configs/TCM-BF518_defconfig
+++ b/arch/blackfin/configs/TCM-BF518_defconfig
@@ -333,7 +333,6 @@ CONFIG_ACCESS_OK_L1=y
333CONFIG_CACHELINE_ALIGNED_L1=y 333CONFIG_CACHELINE_ALIGNED_L1=y
334# CONFIG_SYSCALL_TAB_L1 is not set 334# CONFIG_SYSCALL_TAB_L1 is not set
335# CONFIG_CPLB_SWITCH_TAB_L1 is not set 335# CONFIG_CPLB_SWITCH_TAB_L1 is not set
336CONFIG_APP_STACK_L1=y
337 336
338# 337#
339# Speed Optimizations 338# Speed Optimizations
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index 60adfad54db9..00f221f0c724 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -287,7 +287,6 @@ CONFIG_IP_CHECKSUM_L1=y
287CONFIG_CACHELINE_ALIGNED_L1=y 287CONFIG_CACHELINE_ALIGNED_L1=y
288CONFIG_SYSCALL_TAB_L1=y 288CONFIG_SYSCALL_TAB_L1=y
289CONFIG_CPLB_SWITCH_TAB_L1=y 289CONFIG_CPLB_SWITCH_TAB_L1=y
290CONFIG_APP_STACK_L1=y
291 290
292# 291#
293# Speed Optimizations 292# Speed Optimizations
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
index abdb2af52902..0b6910bdc57f 100644
--- a/arch/blackfin/include/asm/bfin_rotary.h
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -2,7 +2,7 @@
2 * board initialization should put one of these structures into platform_data 2 * board initialization should put one of these structures into platform_data
3 * and place the bfin-rotary onto platform_bus named "bfin-rotary". 3 * and place the bfin-rotary onto platform_bus named "bfin-rotary".
4 * 4 *
5 * Copyright 2008 Analog Devices Inc. 5 * Copyright 2008-2010 Analog Devices Inc.
6 * 6 *
7 * Licensed under the GPL-2 or later. 7 * Licensed under the GPL-2 or later.
8 */ 8 */
@@ -40,4 +40,76 @@ struct bfin_rotary_platform_data {
40 unsigned short debounce; /* 0..17 */ 40 unsigned short debounce; /* 0..17 */
41 unsigned short mode; 41 unsigned short mode;
42}; 42};
43
44/* CNT_CONFIG bitmasks */
45#define CNTE (1 << 0) /* Counter Enable */
46#define DEBE (1 << 1) /* Debounce Enable */
47#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
48#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
49#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
50#define CNTMODE_SHIFT 8
51#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
52#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
53#define BNDMODE_SHIFT 12
54#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
55#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
56
57#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
58#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
59#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
60#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
61#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
62
63#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
64#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
65#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
66#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
67
68/* CNT_IMASK bitmasks */
69#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
70#define UCIE (1 << 1) /* Up count Interrupt Enable */
71#define DCIE (1 << 2) /* Down count Interrupt Enable */
72#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
73#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
74#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
75#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
76#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
77#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
78#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
79#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
80
81/* CNT_STATUS bitmasks */
82#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
83#define UCII (1 << 1) /* Up count Interrupt Identifier */
84#define DCII (1 << 2) /* Down count Interrupt Identifier */
85#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
86#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
87#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
88#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
89#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
90#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
91#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
92#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
93
94/* CNT_COMMAND bitmasks */
95#define W1LCNT 0xf /* Load Counter Register */
96#define W1LMIN 0xf0 /* Load Min Register */
97#define W1LMAX 0xf00 /* Load Max Register */
98#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
99
100#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
101#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
102#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
103
104#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
105#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
106#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
107
108#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
109#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
110#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
111
112/* CNT_DEBOUNCE bitmasks */
113#define DPRESCALE 0xf /* Load Counter Register */
114
43#endif 115#endif
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
index d61d5497c590..6a4cfe2d3367 100644
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ b/arch/blackfin/include/asm/bfin_sdh.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * bfin_sdh.h - Blackfin SDH definitions 2 * Blackfin Secure Digital Host (SDH) definitions
3 * 3 *
4 * Copyright 2008 Analog Devices Inc. 4 * Copyright 2008-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -9,6 +9,7 @@
9#ifndef __BFIN_SDH_H__ 9#ifndef __BFIN_SDH_H__
10#define __BFIN_SDH_H__ 10#define __BFIN_SDH_H__
11 11
12/* Platform resources */
12struct bfin_sd_host { 13struct bfin_sd_host {
13 int dma_chan; 14 int dma_chan;
14 int irq_int0; 15 int irq_int0;
@@ -16,4 +17,118 @@ struct bfin_sd_host {
16 u16 pin_req[7]; 17 u16 pin_req[7];
17}; 18};
18 19
20/* SDH_COMMAND bitmasks */
21#define CMD_IDX 0x3f /* Command Index */
22#define CMD_RSP (1 << 6) /* Response */
23#define CMD_L_RSP (1 << 7) /* Long Response */
24#define CMD_INT_E (1 << 8) /* Command Interrupt */
25#define CMD_PEND_E (1 << 9) /* Command Pending */
26#define CMD_E (1 << 10) /* Command Enable */
27
28/* SDH_PWR_CTL bitmasks */
29#define PWR_ON 0x3 /* Power On */
30#define SD_CMD_OD (1 << 6) /* Open Drain Output */
31#define ROD_CTL (1 << 7) /* Rod Control */
32
33/* SDH_CLK_CTL bitmasks */
34#define CLKDIV 0xff /* MC_CLK Divisor */
35#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
36#define PWR_SV_E (1 << 9) /* Power Save Enable */
37#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
38#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
39
40/* SDH_RESP_CMD bitmasks */
41#define RESP_CMD 0x3f /* Response Command */
42
43/* SDH_DATA_CTL bitmasks */
44#define DTX_E (1 << 0) /* Data Transfer Enable */
45#define DTX_DIR (1 << 1) /* Data Transfer Direction */
46#define DTX_MODE (1 << 2) /* Data Transfer Mode */
47#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
48#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
49
50/* SDH_STATUS bitmasks */
51#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
52#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
53#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
54#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
55#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
56#define RX_OVERRUN (1 << 5) /* Receive Overrun */
57#define CMD_RESP_END (1 << 6) /* CMD Response End */
58#define CMD_SENT (1 << 7) /* CMD Sent */
59#define DAT_END (1 << 8) /* Data End */
60#define START_BIT_ERR (1 << 9) /* Start Bit Error */
61#define DAT_BLK_END (1 << 10) /* Data Block End */
62#define CMD_ACT (1 << 11) /* CMD Active */
63#define TX_ACT (1 << 12) /* Transmit Active */
64#define RX_ACT (1 << 13) /* Receive Active */
65#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
66#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
67#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
68#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
69#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
70#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
71#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
72#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
73
74/* SDH_STATUS_CLR bitmasks */
75#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
76#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
77#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
78#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
79#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
80#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
81#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
82#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
83#define DAT_END_STAT (1 << 8) /* Data End Status */
84#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
85#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
86
87/* SDH_MASK0 bitmasks */
88#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
89#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
90#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
91#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
92#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
93#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
94#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
95#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
96#define DAT_END_MASK (1 << 8) /* Data End Mask */
97#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
98#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
99#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
100#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
101#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
102#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
103#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
104#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
105#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
106#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
107#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
108#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
109#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
110
111/* SDH_FIFO_CNT bitmasks */
112#define FIFO_COUNT 0x7fff /* FIFO Count */
113
114/* SDH_E_STATUS bitmasks */
115#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
116#define SD_CARD_DET (1 << 4) /* SD Card Detect */
117
118/* SDH_E_MASK bitmasks */
119#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
120#define SCD_MSK (1 << 6) /* Mask Card Detect */
121
122/* SDH_CFG bitmasks */
123#define CLKS_EN (1 << 0) /* Clocks Enable */
124#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
125#define MWE (1 << 3) /* Moving Window Enable */
126#define SD_RST (1 << 4) /* SDMMC Reset */
127#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
128#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
129#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
130
131/* SDH_RD_WAIT_EN bitmasks */
132#define RWR (1 << 0) /* Read Wait Request */
133
19#endif 134#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 605ba8e9b2e4..d5872cd967ab 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -119,7 +119,7 @@ static inline unsigned int hweight32(unsigned int w)
119{ 119{
120 unsigned int res; 120 unsigned int res;
121 121
122 __asm__ ("%0.l = ONES %0;" 122 __asm__ ("%0.l = ONES %1;"
123 "%0 = %0.l (Z);" 123 "%0 = %0.l (Z);"
124 : "=d" (res) : "d" (w)); 124 : "=d" (res) : "d" (w));
125 return res; 125 return res;
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
index 8778e0f03730..6c39d94b44d0 100644
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -216,12 +216,16 @@
216#define bfin_write_EVT14(val) bfin_write32(EVT14,val) 216#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
217#define bfin_read_EVT15() bfin_read32(EVT15) 217#define bfin_read_EVT15() bfin_read32(EVT15)
218#define bfin_write_EVT15(val) bfin_write32(EVT15,val) 218#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
219#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
220#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
219#define bfin_read_IMASK() bfin_read32(IMASK) 221#define bfin_read_IMASK() bfin_read32(IMASK)
220#define bfin_write_IMASK(val) bfin_write32(IMASK,val) 222#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
221#define bfin_read_IPEND() bfin_read32(IPEND) 223#define bfin_read_IPEND() bfin_read32(IPEND)
222#define bfin_write_IPEND(val) bfin_write32(IPEND,val) 224#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
223#define bfin_read_ILAT() bfin_read32(ILAT) 225#define bfin_read_ILAT() bfin_read32(ILAT)
224#define bfin_write_ILAT(val) bfin_write32(ILAT,val) 226#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
227#define bfin_read_IPRIO() bfin_read32(IPRIO)
228#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
225 229
226/*Core Timer Registers*/ 230/*Core Timer Registers*/
227#define bfin_read_TCNTL() bfin_read32(TCNTL) 231#define bfin_read_TCNTL() bfin_read32(TCNTL)
@@ -299,8 +303,4 @@
299#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) 303#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
300#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val) 304#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
301 305
302/*
303#define IPRIO 0xFFE02110
304*/
305
306#endif /* _CDEF_LPBLACKFIN_H */ 306#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index f342ff0319df..e3f0f4c49819 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -50,6 +50,23 @@
50#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) 50#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
51#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) 51#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
52 52
53#define bfin_read(addr) \
54({ \
55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
58 ({ BUG(); 0; }); \
59})
60#define bfin_write(addr, val) \
61({ \
62 switch (sizeof(*(addr))) { \
63 case 1: bfin_write8(addr, val); break; \
64 case 2: bfin_write16(addr, val); break; \
65 case 4: bfin_write32(addr, val); break; \
66 default: BUG(); \
67 } \
68})
69
53#endif /* __ASSEMBLY__ */ 70#endif /* __ASSEMBLY__ */
54 71
55/************************************************** 72/**************************************************
@@ -377,6 +394,7 @@
377#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ 394#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
378#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ 395#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
379#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ 396#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
397#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
380#define IMASK 0xFFE02104 /* Interrupt Mask Register */ 398#define IMASK 0xFFE02104 /* Interrupt Mask Register */
381#define IPEND 0xFFE02108 /* Interrupt Pending Register */ 399#define IPEND 0xFFE02108 /* Interrupt Pending Register */
382#define ILAT 0xFFE0210C /* Interrupt Latch Register */ 400#define ILAT 0xFFE0210C /* Interrupt Latch Register */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index 2c09b1d50ec9..eedf3ca65ba2 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -276,6 +276,7 @@ static inline void clear_dma_irqstat(unsigned int channel)
276} 276}
277 277
278void *dma_memcpy(void *dest, const void *src, size_t count); 278void *dma_memcpy(void *dest, const void *src, size_t count);
279void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
279void *safe_dma_memcpy(void *dest, const void *src, size_t count); 280void *safe_dma_memcpy(void *dest, const void *src, size_t count);
280void blackfin_dma_early_init(void); 281void blackfin_dma_early_init(void);
281void early_dma_memcpy(void *dest, const void *src, size_t count); 282void early_dma_memcpy(void *dest, const void *src, size_t count);
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index 117713adea7f..e6c6812a9abd 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -119,6 +119,7 @@ do { \
119#define ELF_CORE_COPY_REGS(pr_reg, regs) \ 119#define ELF_CORE_COPY_REGS(pr_reg, regs) \
120 memcpy((char *) &pr_reg, (char *)regs, \ 120 memcpy((char *) &pr_reg, (char *)regs, \
121 sizeof(struct pt_regs)); 121 sizeof(struct pt_regs));
122#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
122 123
123/* This yields a mask that user programs can use to figure out what 124/* This yields a mask that user programs can use to figure out what
124 instruction set this cpu supports. */ 125 instruction set this cpu supports. */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
index 4cfe2d9ba7e8..8a029505d7b7 100644
--- a/arch/blackfin/include/asm/ftrace.h
+++ b/arch/blackfin/include/asm/ftrace.h
@@ -12,6 +12,22 @@
12 12
13#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
14 14
15#ifdef CONFIG_DYNAMIC_FTRACE
16
17extern void _mcount(void);
18#define MCOUNT_ADDR ((unsigned long)_mcount)
19
20static inline unsigned long ftrace_call_adjust(unsigned long addr)
21{
22 return addr;
23}
24
25struct dyn_arch_ftrace {
26 /* No extra data needed for Blackfin */
27};
28
29#endif
30
15#ifdef CONFIG_FRAME_POINTER 31#ifdef CONFIG_FRAME_POINTER
16#include <linux/mm.h> 32#include <linux/mm.h>
17 33
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 01b19d0cf509..1ef8417f5d27 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -7,63 +7,63 @@
7#ifndef __ARCH_BLACKFIN_GPIO_H__ 7#ifndef __ARCH_BLACKFIN_GPIO_H__
8#define __ARCH_BLACKFIN_GPIO_H__ 8#define __ARCH_BLACKFIN_GPIO_H__
9 9
10#define gpio_bank(x) ((x) >> 4) 10#define gpio_bank(x) ((x) >> 4)
11#define gpio_bit(x) (1<<((x) & 0xF)) 11#define gpio_bit(x) (1<<((x) & 0xF))
12#define gpio_sub_n(x) ((x) & 0xF) 12#define gpio_sub_n(x) ((x) & 0xF)
13 13
14#define GPIO_BANKSIZE 16 14#define GPIO_BANKSIZE 16
15#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) 15#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
16 16
17#include <mach/gpio.h> 17#include <mach/gpio.h>
18 18
19#define GPIO_0 0 19#define GPIO_0 0
20#define GPIO_1 1 20#define GPIO_1 1
21#define GPIO_2 2 21#define GPIO_2 2
22#define GPIO_3 3 22#define GPIO_3 3
23#define GPIO_4 4 23#define GPIO_4 4
24#define GPIO_5 5 24#define GPIO_5 5
25#define GPIO_6 6 25#define GPIO_6 6
26#define GPIO_7 7 26#define GPIO_7 7
27#define GPIO_8 8 27#define GPIO_8 8
28#define GPIO_9 9 28#define GPIO_9 9
29#define GPIO_10 10 29#define GPIO_10 10
30#define GPIO_11 11 30#define GPIO_11 11
31#define GPIO_12 12 31#define GPIO_12 12
32#define GPIO_13 13 32#define GPIO_13 13
33#define GPIO_14 14 33#define GPIO_14 14
34#define GPIO_15 15 34#define GPIO_15 15
35#define GPIO_16 16 35#define GPIO_16 16
36#define GPIO_17 17 36#define GPIO_17 17
37#define GPIO_18 18 37#define GPIO_18 18
38#define GPIO_19 19 38#define GPIO_19 19
39#define GPIO_20 20 39#define GPIO_20 20
40#define GPIO_21 21 40#define GPIO_21 21
41#define GPIO_22 22 41#define GPIO_22 22
42#define GPIO_23 23 42#define GPIO_23 23
43#define GPIO_24 24 43#define GPIO_24 24
44#define GPIO_25 25 44#define GPIO_25 25
45#define GPIO_26 26 45#define GPIO_26 26
46#define GPIO_27 27 46#define GPIO_27 27
47#define GPIO_28 28 47#define GPIO_28 28
48#define GPIO_29 29 48#define GPIO_29 29
49#define GPIO_30 30 49#define GPIO_30 30
50#define GPIO_31 31 50#define GPIO_31 31
51#define GPIO_32 32 51#define GPIO_32 32
52#define GPIO_33 33 52#define GPIO_33 33
53#define GPIO_34 34 53#define GPIO_34 34
54#define GPIO_35 35 54#define GPIO_35 35
55#define GPIO_36 36 55#define GPIO_36 36
56#define GPIO_37 37 56#define GPIO_37 37
57#define GPIO_38 38 57#define GPIO_38 38
58#define GPIO_39 39 58#define GPIO_39 39
59#define GPIO_40 40 59#define GPIO_40 40
60#define GPIO_41 41 60#define GPIO_41 41
61#define GPIO_42 42 61#define GPIO_42 42
62#define GPIO_43 43 62#define GPIO_43 43
63#define GPIO_44 44 63#define GPIO_44 44
64#define GPIO_45 45 64#define GPIO_45 45
65#define GPIO_46 46 65#define GPIO_46 46
66#define GPIO_47 47 66#define GPIO_47 47
67 67
68#define PERIPHERAL_USAGE 1 68#define PERIPHERAL_USAGE 1
69#define GPIO_USAGE 0 69#define GPIO_USAGE 0
@@ -279,6 +279,11 @@ static inline int gpio_direction_output(unsigned gpio, int value)
279 return bfin_gpio_direction_output(gpio, value); 279 return bfin_gpio_direction_output(gpio, value);
280} 280}
281 281
282static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
283{
284 return -EINVAL;
285}
286
282static inline int gpio_get_value(unsigned gpio) 287static inline int gpio_get_value(unsigned gpio)
283{ 288{
284 return bfin_gpio_get_value(gpio); 289 return bfin_gpio_get_value(gpio);
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 29e55b9d88bc..234fbac17ec1 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -124,7 +124,13 @@ static inline unsigned int readl(const volatile void __iomem *addr)
124#define iowrite16(val, x) writew(val, x) 124#define iowrite16(val, x) writew(val, x)
125#define iowrite32(val, x) writel(val, x) 125#define iowrite32(val, x) writel(val, x)
126 126
127#define mmiowb() wmb() 127/**
128 * I/O write barrier
129 *
130 * Ensure ordering of I/O space writes. This will make sure that writes
131 * following the barrier will arrive after all previous writes.
132 */
133#define mmiowb() do { SSYNC(); wmb(); } while (0)
128 134
129#define IO_SPACE_LIMIT 0xffffffff 135#define IO_SPACE_LIMIT 0xffffffff
130 136
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 7c8fe834ff22..237579935e29 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -10,7 +10,6 @@
10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ 12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
13 defined(CONFIG_MEM_GENERIC_BOARD) || \
14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 13 defined(CONFIG_MEM_MT48LC32M8A2_75) || \
15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ 14 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
16 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 15 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
@@ -178,7 +177,6 @@
178 177
179#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 178#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
180 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 179 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
181 defined(CONFIG_MEM_GENERIC_BOARD) || \
182 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 180 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
183 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 181 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
184 defined(CONFIG_MEM_MT48LC32M8A2_75) 182 defined(CONFIG_MEM_MT48LC32M8A2_75)
@@ -248,22 +246,6 @@
248#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) 246#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
249#endif 247#endif
250 248
251#if defined(CONFIG_MEM_GENERIC_BOARD)
252#define DDR_SIZE DEVSZ_512
253#define DDR_WIDTH DEVWD_16
254#define DDR_MAX_tCK 13
255
256#define DDR_tRCD DDR_TRCD(3)
257#define DDR_tWTR DDR_TWTR(2)
258#define DDR_tWR DDR_TWR(2)
259#define DDR_tMRD DDR_TMRD(2)
260#define DDR_tRP DDR_TRP(3)
261#define DDR_tRAS DDR_TRAS(7)
262#define DDR_tRC DDR_TRC(10)
263#define DDR_tRFC DDR_TRFC(12)
264#define DDR_tREFI DDR_TREFI(1288)
265#endif
266
267#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) 249#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
268# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." 250# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
269#elif(CONFIG_SCLK_HZ <= 133333333) 251#elif(CONFIG_SCLK_HZ <= 133333333)
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index edd8ef3a3788..9b1e2c37b324 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common header file for Blackfin family of processors 2 * Common header file for Blackfin family of processors
3 * 3 *
4 * Copyright 2007-2008 Analog Devices Inc. 4 * Copyright 2007-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9#ifndef _PORTMUX_H_ 9#ifndef _PORTMUX_H_
@@ -1042,8 +1042,8 @@ void peripheral_free_list(const unsigned short per[]);
1042#define P_NOR_CLK P_UNDEF 1042#define P_NOR_CLK P_UNDEF
1043#endif 1043#endif
1044 1044
1045#ifndef P_TMRCLK 1045#ifndef P_TMRCLK
1046#define P_TMRCLK P_UNDEF 1046#define P_TMRCLK P_UNDEF
1047#endif 1047#endif
1048 1048
1049#ifndef P_AMC_ARDY_NOR_WAIT 1049#ifndef P_AMC_ARDY_NOR_WAIT
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 30d0d1f01dc7..ca5ccc777772 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -16,6 +16,7 @@ else
16 obj-y += time.o 16 obj-y += time.o
17endif 17endif
18 18
19obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
19obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o 20obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
20obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 21obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
21CFLAGS_REMOVE_ftrace.o = -pg 22CFLAGS_REMOVE_ftrace.o = -pg
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 26403d1c9e65..1e485dfdc9f2 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -450,7 +450,6 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
450{ 450{
451 unsigned long dst = (unsigned long)pdst; 451 unsigned long dst = (unsigned long)pdst;
452 unsigned long src = (unsigned long)psrc; 452 unsigned long src = (unsigned long)psrc;
453 size_t bulk, rest;
454 453
455 if (bfin_addr_dcacheable(src)) 454 if (bfin_addr_dcacheable(src))
456 blackfin_dcache_flush_range(src, src + size); 455 blackfin_dcache_flush_range(src, src + size);
@@ -458,6 +457,22 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
458 if (bfin_addr_dcacheable(dst)) 457 if (bfin_addr_dcacheable(dst))
459 blackfin_dcache_invalidate_range(dst, dst + size); 458 blackfin_dcache_invalidate_range(dst, dst + size);
460 459
460 return dma_memcpy_nocache(pdst, psrc, size);
461}
462EXPORT_SYMBOL(dma_memcpy);
463
464/**
465 * dma_memcpy_nocache - DMA memcpy under mutex lock
466 * - No cache flush/invalidate
467 *
468 * Do not check arguments before starting the DMA memcpy. Break the transfer
469 * up into two pieces. The first transfer is in multiples of 64k and the
470 * second transfer is the piece smaller than 64k.
471 */
472void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
473{
474 size_t bulk, rest;
475
461 bulk = size & ~0xffff; 476 bulk = size & ~0xffff;
462 rest = size - bulk; 477 rest = size - bulk;
463 if (bulk) 478 if (bulk)
@@ -465,7 +480,7 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
465 _dma_memcpy(pdst + bulk, psrc + bulk, rest); 480 _dma_memcpy(pdst + bulk, psrc + bulk, rest);
466 return pdst; 481 return pdst;
467} 482}
468EXPORT_SYMBOL(dma_memcpy); 483EXPORT_SYMBOL(dma_memcpy_nocache);
469 484
470/** 485/**
471 * safe_dma_memcpy - DMA memcpy w/argument checking 486 * safe_dma_memcpy - DMA memcpy w/argument checking
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 42833ee2b308..dc07ed08b37f 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -108,11 +108,7 @@ static unsigned short * const port_fer[] = {
108}; 108};
109#endif 109#endif
110 110
111static unsigned short reserved_gpio_map[GPIO_BANK_NUM]; 111#define RESOURCE_LABEL_SIZE 16
112static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
113static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
114
115#define RESOURCE_LABEL_SIZE 16
116 112
117static struct str_ident { 113static struct str_ident {
118 char name[RESOURCE_LABEL_SIZE]; 114 char name[RESOURCE_LABEL_SIZE];
@@ -122,19 +118,6 @@ static struct str_ident {
122static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM]; 118static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
123#endif 119#endif
124 120
125inline int check_gpio(unsigned gpio)
126{
127#if defined(CONFIG_BF54x)
128 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
129 || gpio == GPIO_PH14 || gpio == GPIO_PH15
130 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
131 return -EINVAL;
132#endif
133 if (gpio >= MAX_BLACKFIN_GPIOS)
134 return -EINVAL;
135 return 0;
136}
137
138static void gpio_error(unsigned gpio) 121static void gpio_error(unsigned gpio)
139{ 122{
140 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio); 123 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
@@ -167,6 +150,29 @@ static int cmp_label(unsigned short ident, const char *label)
167 return -EINVAL; 150 return -EINVAL;
168} 151}
169 152
153#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
154#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
155#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
156#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
157#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
158
159DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
160DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE));
161DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
162
163inline int check_gpio(unsigned gpio)
164{
165#if defined(CONFIG_BF54x)
166 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
167 || gpio == GPIO_PH14 || gpio == GPIO_PH15
168 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
169 return -EINVAL;
170#endif
171 if (gpio >= MAX_BLACKFIN_GPIOS)
172 return -EINVAL;
173 return 0;
174}
175
170static void port_setup(unsigned gpio, unsigned short usage) 176static void port_setup(unsigned gpio, unsigned short usage)
171{ 177{
172#if defined(BF538_FAMILY) 178#if defined(BF538_FAMILY)
@@ -475,7 +481,7 @@ GET_GPIO_P(maskb)
475 481
476 482
477#ifdef CONFIG_PM 483#ifdef CONFIG_PM
478static unsigned short wakeup_map[GPIO_BANK_NUM]; 484DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
479 485
480static const unsigned int sic_iwr_irqs[] = { 486static const unsigned int sic_iwr_irqs[] = {
481#if defined(BF533_FAMILY) 487#if defined(BF533_FAMILY)
@@ -521,9 +527,9 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
521 527
522 local_irq_save_hw(flags); 528 local_irq_save_hw(flags);
523 if (ctrl) 529 if (ctrl)
524 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); 530 reserve(wakeup, gpio);
525 else 531 else
526 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 532 unreserve(wakeup, gpio);
527 533
528 set_gpio_maskb(gpio, ctrl); 534 set_gpio_maskb(gpio, ctrl);
529 local_irq_restore_hw(flags); 535 local_irq_restore_hw(flags);
@@ -536,7 +542,7 @@ int bfin_pm_standby_ctrl(unsigned ctrl)
536 u16 bank, mask, i; 542 u16 bank, mask, i;
537 543
538 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { 544 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
539 mask = wakeup_map[gpio_bank(i)]; 545 mask = map_entry(wakeup, i);
540 bank = gpio_bank(i); 546 bank = gpio_bank(i);
541 547
542 if (mask) 548 if (mask)
@@ -653,7 +659,7 @@ EXPORT_SYMBOL(get_gpio_dir);
653 659
654/*********************************************************** 660/***********************************************************
655* 661*
656* FUNCTIONS: Blackfin Peripheral Resource Allocation 662* FUNCTIONS: Blackfin Peripheral Resource Allocation
657* and PortMux Setup 663* and PortMux Setup
658* 664*
659* INPUTS/OUTPUTS: 665* INPUTS/OUTPUTS:
@@ -689,8 +695,7 @@ int peripheral_request(unsigned short per, const char *label)
689 /* If a pin can be muxed as either GPIO or peripheral, make 695 /* If a pin can be muxed as either GPIO or peripheral, make
690 * sure it is not already a GPIO pin when we request it. 696 * sure it is not already a GPIO pin when we request it.
691 */ 697 */
692 if (unlikely(!check_gpio(ident) && 698 if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
693 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
694 if (system_state == SYSTEM_BOOTING) 699 if (system_state == SYSTEM_BOOTING)
695 dump_stack(); 700 dump_stack();
696 printk(KERN_ERR 701 printk(KERN_ERR
@@ -700,7 +705,7 @@ int peripheral_request(unsigned short per, const char *label)
700 return -EBUSY; 705 return -EBUSY;
701 } 706 }
702 707
703 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { 708 if (unlikely(is_reserved(peri, ident, 1))) {
704 709
705 /* 710 /*
706 * Pin functions like AMC address strobes my 711 * Pin functions like AMC address strobes my
@@ -731,7 +736,7 @@ int peripheral_request(unsigned short per, const char *label)
731 } 736 }
732 737
733 anyway: 738 anyway:
734 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); 739 reserve(peri, ident);
735 740
736 portmux_setup(per); 741 portmux_setup(per);
737 port_setup(ident, PERIPHERAL_USAGE); 742 port_setup(ident, PERIPHERAL_USAGE);
@@ -777,7 +782,7 @@ void peripheral_free(unsigned short per)
777 782
778 local_irq_save_hw(flags); 783 local_irq_save_hw(flags);
779 784
780 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { 785 if (unlikely(!is_reserved(peri, ident, 0))) {
781 local_irq_restore_hw(flags); 786 local_irq_restore_hw(flags);
782 return; 787 return;
783 } 788 }
@@ -785,7 +790,7 @@ void peripheral_free(unsigned short per)
785 if (!(per & P_MAYSHARE)) 790 if (!(per & P_MAYSHARE))
786 port_setup(ident, GPIO_USAGE); 791 port_setup(ident, GPIO_USAGE);
787 792
788 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident); 793 unreserve(peri, ident);
789 794
790 set_label(ident, "free"); 795 set_label(ident, "free");
791 796
@@ -836,7 +841,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
836 return 0; 841 return 0;
837 } 842 }
838 843
839 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 844 if (unlikely(is_reserved(gpio, gpio, 1))) {
840 if (system_state == SYSTEM_BOOTING) 845 if (system_state == SYSTEM_BOOTING)
841 dump_stack(); 846 dump_stack();
842 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", 847 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
@@ -844,7 +849,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
844 local_irq_restore_hw(flags); 849 local_irq_restore_hw(flags);
845 return -EBUSY; 850 return -EBUSY;
846 } 851 }
847 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 852 if (unlikely(is_reserved(peri, gpio, 1))) {
848 if (system_state == SYSTEM_BOOTING) 853 if (system_state == SYSTEM_BOOTING)
849 dump_stack(); 854 dump_stack();
850 printk(KERN_ERR 855 printk(KERN_ERR
@@ -853,7 +858,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
853 local_irq_restore_hw(flags); 858 local_irq_restore_hw(flags);
854 return -EBUSY; 859 return -EBUSY;
855 } 860 }
856 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 861 if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
857 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" 862 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
858 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); 863 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
859 } 864 }
@@ -863,7 +868,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
863 } 868 }
864#endif 869#endif
865 870
866 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); 871 reserve(gpio, gpio);
867 set_label(gpio, label); 872 set_label(gpio, label);
868 873
869 local_irq_restore_hw(flags); 874 local_irq_restore_hw(flags);
@@ -885,7 +890,7 @@ void bfin_gpio_free(unsigned gpio)
885 890
886 local_irq_save_hw(flags); 891 local_irq_save_hw(flags);
887 892
888 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 893 if (unlikely(!is_reserved(gpio, gpio, 0))) {
889 if (system_state == SYSTEM_BOOTING) 894 if (system_state == SYSTEM_BOOTING)
890 dump_stack(); 895 dump_stack();
891 gpio_error(gpio); 896 gpio_error(gpio);
@@ -893,7 +898,7 @@ void bfin_gpio_free(unsigned gpio)
893 return; 898 return;
894 } 899 }
895 900
896 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 901 unreserve(gpio, gpio);
897 902
898 set_label(gpio, "free"); 903 set_label(gpio, "free");
899 904
@@ -902,7 +907,7 @@ void bfin_gpio_free(unsigned gpio)
902EXPORT_SYMBOL(bfin_gpio_free); 907EXPORT_SYMBOL(bfin_gpio_free);
903 908
904#ifdef BFIN_SPECIAL_GPIO_BANKS 909#ifdef BFIN_SPECIAL_GPIO_BANKS
905static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)]; 910DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
906 911
907int bfin_special_gpio_request(unsigned gpio, const char *label) 912int bfin_special_gpio_request(unsigned gpio, const char *label)
908{ 913{
@@ -921,14 +926,14 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
921 return 0; 926 return 0;
922 } 927 }
923 928
924 if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 929 if (unlikely(is_reserved(special_gpio, gpio, 1))) {
925 local_irq_restore_hw(flags); 930 local_irq_restore_hw(flags);
926 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", 931 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
927 gpio, get_label(gpio)); 932 gpio, get_label(gpio));
928 933
929 return -EBUSY; 934 return -EBUSY;
930 } 935 }
931 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 936 if (unlikely(is_reserved(peri, gpio, 1))) {
932 local_irq_restore_hw(flags); 937 local_irq_restore_hw(flags);
933 printk(KERN_ERR 938 printk(KERN_ERR
934 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", 939 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
@@ -937,8 +942,8 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
937 return -EBUSY; 942 return -EBUSY;
938 } 943 }
939 944
940 reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); 945 reserve(special_gpio, gpio);
941 reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio); 946 reserve(peri, gpio);
942 947
943 set_label(gpio, label); 948 set_label(gpio, label);
944 local_irq_restore_hw(flags); 949 local_irq_restore_hw(flags);
@@ -956,14 +961,14 @@ void bfin_special_gpio_free(unsigned gpio)
956 961
957 local_irq_save_hw(flags); 962 local_irq_save_hw(flags);
958 963
959 if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 964 if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
960 gpio_error(gpio); 965 gpio_error(gpio);
961 local_irq_restore_hw(flags); 966 local_irq_restore_hw(flags);
962 return; 967 return;
963 } 968 }
964 969
965 reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 970 unreserve(special_gpio, gpio);
966 reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 971 unreserve(peri, gpio);
967 set_label(gpio, "free"); 972 set_label(gpio, "free");
968 local_irq_restore_hw(flags); 973 local_irq_restore_hw(flags);
969} 974}
@@ -980,7 +985,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
980 985
981 local_irq_save_hw(flags); 986 local_irq_save_hw(flags);
982 987
983 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 988 if (unlikely(is_reserved(peri, gpio, 1))) {
984 if (system_state == SYSTEM_BOOTING) 989 if (system_state == SYSTEM_BOOTING)
985 dump_stack(); 990 dump_stack();
986 printk(KERN_ERR 991 printk(KERN_ERR
@@ -989,12 +994,12 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
989 local_irq_restore_hw(flags); 994 local_irq_restore_hw(flags);
990 return -EBUSY; 995 return -EBUSY;
991 } 996 }
992 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) 997 if (unlikely(is_reserved(gpio, gpio, 1)))
993 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! " 998 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
994 "(Documentation/blackfin/bfin-gpio-notes.txt)\n", 999 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
995 gpio, get_label(gpio)); 1000 gpio, get_label(gpio));
996 1001
997 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio); 1002 reserve(gpio_irq, gpio);
998 set_label(gpio, label); 1003 set_label(gpio, label);
999 1004
1000 local_irq_restore_hw(flags); 1005 local_irq_restore_hw(flags);
@@ -1013,7 +1018,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1013 1018
1014 local_irq_save_hw(flags); 1019 local_irq_save_hw(flags);
1015 1020
1016 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 1021 if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
1017 if (system_state == SYSTEM_BOOTING) 1022 if (system_state == SYSTEM_BOOTING)
1018 dump_stack(); 1023 dump_stack();
1019 gpio_error(gpio); 1024 gpio_error(gpio);
@@ -1021,7 +1026,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1021 return; 1026 return;
1022 } 1027 }
1023 1028
1024 reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 1029 unreserve(gpio_irq, gpio);
1025 1030
1026 set_label(gpio, "free"); 1031 set_label(gpio, "free");
1027 1032
@@ -1042,7 +1047,7 @@ int bfin_gpio_direction_input(unsigned gpio)
1042{ 1047{
1043 unsigned long flags; 1048 unsigned long flags;
1044 1049
1045 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 1050 if (unlikely(!is_reserved(gpio, gpio, 0))) {
1046 gpio_error(gpio); 1051 gpio_error(gpio);
1047 return -EINVAL; 1052 return -EINVAL;
1048 } 1053 }
@@ -1084,7 +1089,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1084{ 1089{
1085 unsigned long flags; 1090 unsigned long flags;
1086 1091
1087 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 1092 if (unlikely(!is_reserved(gpio, gpio, 0))) {
1088 gpio_error(gpio); 1093 gpio_error(gpio);
1089 return -EINVAL; 1094 return -EINVAL;
1090 } 1095 }
@@ -1153,13 +1158,13 @@ static int gpio_proc_read(char *buf, char **start, off_t offset,
1153 int c, irq, gpio, outlen = 0; 1158 int c, irq, gpio, outlen = 0;
1154 1159
1155 for (c = 0; c < MAX_RESOURCES; c++) { 1160 for (c = 0; c < MAX_RESOURCES; c++) {
1156 irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c); 1161 irq = is_reserved(gpio_irq, c, 1);
1157 gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c); 1162 gpio = is_reserved(gpio, c, 1);
1158 if (!check_gpio(c) && (gpio || irq)) 1163 if (!check_gpio(c) && (gpio || irq))
1159 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c, 1164 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1160 get_label(c), (gpio && irq) ? " *" : "", 1165 get_label(c), (gpio && irq) ? " *" : "",
1161 get_gpio_dir(c) ? "OUTPUT" : "INPUT"); 1166 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1162 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c)) 1167 else if (is_reserved(peri, c, 1))
1163 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c)); 1168 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1164 else 1169 else
1165 continue; 1170 continue;
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index 30fd6417f069..c15fd05f0b09 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -13,10 +13,6 @@
13#include <asm/cplbinit.h> 13#include <asm/cplbinit.h>
14#include <asm/mem_map.h> 14#include <asm/mem_map.h>
15 15
16#if ANOMALY_05000263
17# error the MPU will not function safely while Anomaly 05000263 applies
18#endif
19
20struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; 16struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
21struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; 17struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
22 18
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S
index d66446b572c0..7eed00bbd26d 100644
--- a/arch/blackfin/kernel/ftrace-entry.S
+++ b/arch/blackfin/kernel/ftrace-entry.S
@@ -10,6 +10,18 @@
10 10
11.text 11.text
12 12
13#ifdef CONFIG_DYNAMIC_FTRACE
14
15/* Simple stub so we can boot the kernel until runtime patching has
16 * disabled all calls to this. Then it'll be unused.
17 */
18ENTRY(__mcount)
19# if ANOMALY_05000371
20 nop; nop; nop; nop;
21# endif
22 rts;
23ENDPROC(__mcount)
24
13/* GCC will have called us before setting up the function prologue, so we 25/* GCC will have called us before setting up the function prologue, so we
14 * can clobber the normal scratch registers, but we need to make sure to 26 * can clobber the normal scratch registers, but we need to make sure to
15 * save/restore the registers used for argument passing (R0-R2) in case 27 * save/restore the registers used for argument passing (R0-R2) in case
@@ -20,15 +32,65 @@
20 * function. And since GCC pushed the previous RETS for us, the previous 32 * function. And since GCC pushed the previous RETS for us, the previous
21 * function will be waiting there. mmmm pie. 33 * function will be waiting there. mmmm pie.
22 */ 34 */
35ENTRY(_ftrace_caller)
36# ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST
37 /* optional micro optimization: return if stopped */
38 p1.l = _function_trace_stop;
39 p1.h = _function_trace_stop;
40 r3 = [p1];
41 cc = r3 == 0;
42 if ! cc jump _ftrace_stub (bp);
43# endif
44
45 /* save first/second/third function arg and the return register */
46 [--sp] = r2;
47 [--sp] = r0;
48 [--sp] = r1;
49 [--sp] = rets;
50
51 /* function_trace_call(unsigned long ip, unsigned long parent_ip):
52 * ip: this point was called by ...
53 * parent_ip: ... this function
54 * the ip itself will need adjusting for the mcount call
55 */
56 r0 = rets;
57 r1 = [sp + 16]; /* skip the 4 local regs on stack */
58 r0 += -MCOUNT_INSN_SIZE;
59
60.globl _ftrace_call
61_ftrace_call:
62 call _ftrace_stub
63
64# ifdef CONFIG_FUNCTION_GRAPH_TRACER
65.globl _ftrace_graph_call
66_ftrace_graph_call:
67 nop; /* jump _ftrace_graph_caller; */
68# endif
69
70 /* restore state and get out of dodge */
71.Lfinish_trace:
72 rets = [sp++];
73 r1 = [sp++];
74 r0 = [sp++];
75 r2 = [sp++];
76
77.globl _ftrace_stub
78_ftrace_stub:
79 rts;
80ENDPROC(_ftrace_caller)
81
82#else
83
84/* See documentation for _ftrace_caller */
23ENTRY(__mcount) 85ENTRY(__mcount)
24#ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST 86# ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST
25 /* optional micro optimization: return if stopped */ 87 /* optional micro optimization: return if stopped */
26 p1.l = _function_trace_stop; 88 p1.l = _function_trace_stop;
27 p1.h = _function_trace_stop; 89 p1.h = _function_trace_stop;
28 r3 = [p1]; 90 r3 = [p1];
29 cc = r3 == 0; 91 cc = r3 == 0;
30 if ! cc jump _ftrace_stub (bp); 92 if ! cc jump _ftrace_stub (bp);
31#endif 93# endif
32 94
33 /* save third function arg early so we can do testing below */ 95 /* save third function arg early so we can do testing below */
34 [--sp] = r2; 96 [--sp] = r2;
@@ -44,7 +106,7 @@ ENTRY(__mcount)
44 cc = r2 == r3; 106 cc = r2 == r3;
45 if ! cc jump .Ldo_trace; 107 if ! cc jump .Ldo_trace;
46 108
47#ifdef CONFIG_FUNCTION_GRAPH_TRACER 109# ifdef CONFIG_FUNCTION_GRAPH_TRACER
48 /* if the ftrace_graph_return function pointer is not set to 110 /* if the ftrace_graph_return function pointer is not set to
49 * the ftrace_stub entry, call prepare_ftrace_return(). 111 * the ftrace_stub entry, call prepare_ftrace_return().
50 */ 112 */
@@ -64,7 +126,7 @@ ENTRY(__mcount)
64 r3 = [p0]; 126 r3 = [p0];
65 cc = r2 == r3; 127 cc = r2 == r3;
66 if ! cc jump _ftrace_graph_caller; 128 if ! cc jump _ftrace_graph_caller;
67#endif 129# endif
68 130
69 r2 = [sp++]; 131 r2 = [sp++];
70 rts; 132 rts;
@@ -103,6 +165,8 @@ _ftrace_stub:
103 rts; 165 rts;
104ENDPROC(__mcount) 166ENDPROC(__mcount)
105 167
168#endif
169
106#ifdef CONFIG_FUNCTION_GRAPH_TRACER 170#ifdef CONFIG_FUNCTION_GRAPH_TRACER
107/* The prepare_ftrace_return() function is similar to the trace function 171/* The prepare_ftrace_return() function is similar to the trace function
108 * except it takes a pointer to the location of the frompc. This is so 172 * except it takes a pointer to the location of the frompc. This is so
@@ -110,6 +174,7 @@ ENDPROC(__mcount)
110 * purposes. 174 * purposes.
111 */ 175 */
112ENTRY(_ftrace_graph_caller) 176ENTRY(_ftrace_graph_caller)
177# ifndef CONFIG_DYNAMIC_FTRACE
113 /* save first/second function arg and the return register */ 178 /* save first/second function arg and the return register */
114 [--sp] = r0; 179 [--sp] = r0;
115 [--sp] = r1; 180 [--sp] = r1;
@@ -118,9 +183,13 @@ ENTRY(_ftrace_graph_caller)
118 /* prepare_ftrace_return(parent, self_addr, frame_pointer) */ 183 /* prepare_ftrace_return(parent, self_addr, frame_pointer) */
119 r0 = sp; /* unsigned long *parent */ 184 r0 = sp; /* unsigned long *parent */
120 r1 = rets; /* unsigned long self_addr */ 185 r1 = rets; /* unsigned long self_addr */
121#ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST 186# else
187 r0 = sp; /* unsigned long *parent */
188 r1 = [sp]; /* unsigned long self_addr */
189# endif
190# ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST
122 r2 = fp; /* unsigned long frame_pointer */ 191 r2 = fp; /* unsigned long frame_pointer */
123#endif 192# endif
124 r0 += 16; /* skip the 4 local regs on stack */ 193 r0 += 16; /* skip the 4 local regs on stack */
125 r1 += -MCOUNT_INSN_SIZE; 194 r1 += -MCOUNT_INSN_SIZE;
126 call _prepare_ftrace_return; 195 call _prepare_ftrace_return;
@@ -139,9 +208,9 @@ ENTRY(_return_to_handler)
139 [--sp] = r1; 208 [--sp] = r1;
140 209
141 /* get original return address */ 210 /* get original return address */
142#ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST 211# ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST
143 r0 = fp; /* Blackfin is sane, so omit this */ 212 r0 = fp; /* Blackfin is sane, so omit this */
144#endif 213# endif
145 call _ftrace_return_to_handler; 214 call _ftrace_return_to_handler;
146 rets = r0; 215 rets = r0;
147 216
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
index a61d948ea925..48808a12b427 100644
--- a/arch/blackfin/kernel/ftrace.c
+++ b/arch/blackfin/kernel/ftrace.c
@@ -1,17 +1,101 @@
1/* 1/*
2 * ftrace graph code 2 * ftrace graph code
3 * 3 *
4 * Copyright (C) 2009 Analog Devices Inc. 4 * Copyright (C) 2009-2010 Analog Devices Inc.
5 * Licensed under the GPL-2 or later. 5 * Licensed under the GPL-2 or later.
6 */ 6 */
7 7
8#include <linux/ftrace.h> 8#include <linux/ftrace.h>
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/sched.h> 10#include <linux/sched.h>
11#include <linux/uaccess.h>
11#include <asm/atomic.h> 12#include <asm/atomic.h>
13#include <asm/cacheflush.h>
14
15#ifdef CONFIG_DYNAMIC_FTRACE
16
17static const unsigned char mnop[] = {
18 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
19 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
20};
21
22static void bfin_make_pcrel24(unsigned char *insn, unsigned long src,
23 unsigned long dst)
24{
25 uint32_t pcrel = (dst - src) >> 1;
26 insn[0] = pcrel >> 16;
27 insn[1] = 0xe3;
28 insn[2] = pcrel;
29 insn[3] = pcrel >> 8;
30}
31#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst))
32
33static int ftrace_modify_code(unsigned long ip, const unsigned char *code,
34 unsigned long len)
35{
36 int ret = probe_kernel_write((void *)ip, (void *)code, len);
37 flush_icache_range(ip, ip + len);
38 return ret;
39}
40
41int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
42 unsigned long addr)
43{
44 /* Turn the mcount call site into two MNOPs as those are 32bit insns */
45 return ftrace_modify_code(rec->ip, mnop, sizeof(mnop));
46}
47
48int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
49{
50 /* Restore the mcount call site */
51 unsigned char call[8];
52 call[0] = 0x67; /* [--SP] = RETS; */
53 call[1] = 0x01;
54 bfin_make_pcrel24(&call[2], rec->ip + 2, addr);
55 call[6] = 0x27; /* RETS = [SP++]; */
56 call[7] = 0x01;
57 return ftrace_modify_code(rec->ip, call, sizeof(call));
58}
59
60int ftrace_update_ftrace_func(ftrace_func_t func)
61{
62 unsigned char call[4];
63 unsigned long ip = (unsigned long)&ftrace_call;
64 bfin_make_pcrel24(call, ip, func);
65 return ftrace_modify_code(ip, call, sizeof(call));
66}
67
68int __init ftrace_dyn_arch_init(void *data)
69{
70 /* return value is done indirectly via data */
71 *(unsigned long *)data = 0;
72
73 return 0;
74}
75
76#endif
12 77
13#ifdef CONFIG_FUNCTION_GRAPH_TRACER 78#ifdef CONFIG_FUNCTION_GRAPH_TRACER
14 79
80# ifdef CONFIG_DYNAMIC_FTRACE
81
82extern void ftrace_graph_call(void);
83
84int ftrace_enable_ftrace_graph_caller(void)
85{
86 unsigned long ip = (unsigned long)&ftrace_graph_call;
87 uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1;
88 jump_pcrel12 |= 0x2000;
89 return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12));
90}
91
92int ftrace_disable_ftrace_graph_caller(void)
93{
94 return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2);
95}
96
97# endif
98
15/* 99/*
16 * Hook the return address and push it in the stack of return addrs 100 * Hook the return address and push it in the stack of return addrs
17 * in current thread info. 101 * in current thread info.
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index d37a397f43f5..ac71dc15cbdb 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -864,6 +864,13 @@ void __init setup_arch(char **cmdline_p)
864 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); 864 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
865 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); 865 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
866#endif 866#endif
867#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
868 bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
869 bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
870 bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
871 bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
872 ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
873#endif
867 874
868 cclk = get_cclk(); 875 cclk = get_cclk();
869 sclk = get_sclk(); 876 sclk = get_sclk();
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 984c78172397..4122678529c0 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -48,15 +48,10 @@ SECTIONS
48#if !L1_CODE_LENGTH 48#if !L1_CODE_LENGTH
49 *(.l1.text) 49 *(.l1.text)
50#endif 50#endif
51
52 . = ALIGN(16);
53 ___start___ex_table = .;
54 *(__ex_table)
55 ___stop___ex_table = .;
56
57 __etext = .; 51 __etext = .;
58 } 52 }
59 53
54 EXCEPTION_TABLE(4)
60 NOTES 55 NOTES
61 56
62 /* Just in case the first read only is a 32-bit access */ 57 /* Just in case the first read only is a 32-bit access */
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 4ab2d166c832..1d9f631a7f94 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -62,6 +62,67 @@ config BF518_UART1_PORTG
62 PORT G 62 PORT G
63endchoice 63endchoice
64 64
65comment "Hysteresis/Schmitt Trigger Control"
66config BFIN_HYSTERESIS_CONTROL
67 bool "Enable Hysteresis Control"
68 help
69 The ADSP-BF51x allows to control input hysteresis for Port F,
70 Port G and Port H and other processor signal inputs.
71 The Schmitt trigger enables can be set only for pin groups.
72 Saying Y will overwrite the default reset or boot loader
73 initialization.
74
75menu "PORT F"
76 depends on BFIN_HYSTERESIS_CONTROL
77config GPIO_HYST_PORTF_0_7
78 bool "Enable Hysteresis on PORTF {0...7}"
79config GPIO_HYST_PORTF_8_9
80 bool "Enable Hysteresis on PORTF {8, 9}"
81config GPIO_HYST_PORTF_10
82 bool "Enable Hysteresis on PORTF 10"
83config GPIO_HYST_PORTF_11
84 bool "Enable Hysteresis on PORTF 11"
85config GPIO_HYST_PORTF_12_13
86 bool "Enable Hysteresis on PORTF {12, 13}"
87config GPIO_HYST_PORTF_14_15
88 bool "Enable Hysteresis on PORTF {14, 15}"
89endmenu
90
91menu "PORT G"
92 depends on BFIN_HYSTERESIS_CONTROL
93config GPIO_HYST_PORTG_0
94 bool "Enable Hysteresis on PORTG 0"
95config GPIO_HYST_PORTG_1_4
96 bool "Enable Hysteresis on PORTG {1...4}"
97config GPIO_HYST_PORTG_5_6
98 bool "Enable Hysteresis on PORTG {5, 6}"
99config GPIO_HYST_PORTG_7_8
100 bool "Enable Hysteresis on PORTG {7, 8}"
101config GPIO_HYST_PORTG_9
102 bool "Enable Hysteresis on PORTG 9"
103config GPIO_HYST_PORTG_10
104 bool "Enable Hysteresis on PORTG 10"
105config GPIO_HYST_PORTG_11_13
106 bool "Enable Hysteresis on PORTG {11...13}"
107config GPIO_HYST_PORTG_14_15
108 bool "Enable Hysteresis on PORTG {14, 15}"
109endmenu
110
111menu "PORT H"
112 depends on BFIN_HYSTERESIS_CONTROL
113config GPIO_HYST_PORTH_0_7
114 bool "Enable Hysteresis on PORTH {0...7}"
115
116endmenu
117
118menu "None-GPIO"
119 depends on BFIN_HYSTERESIS_CONTROL
120config NONEGPIO_HYST_NMI_RST_BMODE
121 bool "Enable Hysteresis on {NMI, RESET, BMODE}"
122config NONEGPIO_HYST_JTAG
123 bool "Enable Hysteresis on JTAG"
124endmenu
125
65comment "Interrupt Priority Assignment" 126comment "Interrupt Priority Assignment"
66menu "Priority" 127menu "Priority"
67 128
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 2829dd0400f1..24918c5f7ea1 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List 14 * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ 17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
@@ -24,6 +24,8 @@
24 24
25/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 25/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
26#define ANOMALY_05000074 (1) 26#define ANOMALY_05000074 (1)
27/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
28#define ANOMALY_05000119 (1)
27/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
28#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
29/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 31/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -52,6 +54,8 @@
52#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) 54#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
53/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ 55/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
54#define ANOMALY_05000431 (1) 56#define ANOMALY_05000431 (1)
57/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
58#define ANOMALY_05000434 (1)
55/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 59/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
56#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) 60#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
57/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ 61/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
@@ -74,14 +78,21 @@
74#define ANOMALY_05000461 (1) 78#define ANOMALY_05000461 (1)
75/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 79/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
76#define ANOMALY_05000462 (1) 80#define ANOMALY_05000462 (1)
77/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 81/* PLL Latches Incorrect Settings During Reset */
82#define ANOMALY_05000469 (1)
83/* Incorrect Default MSEL Value in PLL_CTL */
84#define ANOMALY_05000472 (1)
85/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
78#define ANOMALY_05000473 (1) 86#define ANOMALY_05000473 (1)
79/* TESTSET Instruction Cannot Be Interrupted */ 87/* TESTSET Instruction Cannot Be Interrupted */
80#define ANOMALY_05000477 (1) 88#define ANOMALY_05000477 (1)
89/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
90#define ANOMALY_05000481 (1)
91/* IFLUSH sucks at life */
92#define ANOMALY_05000491 (1)
81 93
82/* Anomalies that don't exist on this proc */ 94/* Anomalies that don't exist on this proc */
83#define ANOMALY_05000099 (0) 95#define ANOMALY_05000099 (0)
84#define ANOMALY_05000119 (0)
85#define ANOMALY_05000120 (0) 96#define ANOMALY_05000120 (0)
86#define ANOMALY_05000125 (0) 97#define ANOMALY_05000125 (0)
87#define ANOMALY_05000149 (0) 98#define ANOMALY_05000149 (0)
@@ -94,6 +105,7 @@
94#define ANOMALY_05000198 (0) 105#define ANOMALY_05000198 (0)
95#define ANOMALY_05000202 (0) 106#define ANOMALY_05000202 (0)
96#define ANOMALY_05000215 (0) 107#define ANOMALY_05000215 (0)
108#define ANOMALY_05000219 (0)
97#define ANOMALY_05000220 (0) 109#define ANOMALY_05000220 (0)
98#define ANOMALY_05000227 (0) 110#define ANOMALY_05000227 (0)
99#define ANOMALY_05000230 (0) 111#define ANOMALY_05000230 (0)
@@ -143,5 +155,6 @@
143#define ANOMALY_05000467 (0) 155#define ANOMALY_05000467 (0)
144#define ANOMALY_05000474 (0) 156#define ANOMALY_05000474 (0)
145#define ANOMALY_05000475 (0) 157#define ANOMALY_05000475 (0)
158#define ANOMALY_05000485 (0)
146 159
147#endif 160#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
index 856b330ecf0b..6906dee4f4cc 100644
--- a/arch/blackfin/mach-bf518/include/mach/bf518.h
+++ b/arch/blackfin/mach-bf518/include/mach/bf518.h
@@ -85,6 +85,111 @@
85 85
86#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 86#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
87 87
88/**************************** Hysteresis Settings ****************************/
89
90#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
91#ifdef CONFIG_GPIO_HYST_PORTF_0_7
92#define HYST_PORTF_0_7 (1 << 0)
93#else
94#define HYST_PORTF_0_7 (0 << 0)
95#endif
96#ifdef CONFIG_GPIO_HYST_PORTF_8_9
97#define HYST_PORTF_8_9 (1 << 2)
98#else
99#define HYST_PORTF_8_9 (0 << 2)
100#endif
101#ifdef CONFIG_GPIO_HYST_PORTF_10
102#define HYST_PORTF_10 (1 << 4)
103#else
104#define HYST_PORTF_10 (0 << 4)
105#endif
106#ifdef CONFIG_GPIO_HYST_PORTF_11
107#define HYST_PORTF_11 (1 << 6)
108#else
109#define HYST_PORTF_11 (0 << 6)
110#endif
111#ifdef CONFIG_GPIO_HYST_PORTF_12_13
112#define HYST_PORTF_12_13 (1 << 8)
113#else
114#define HYST_PORTF_12_13 (0 << 8)
115#endif
116#ifdef CONFIG_GPIO_HYST_PORTF_14_15
117#define HYST_PORTF_14_15 (1 << 10)
118#else
119#define HYST_PORTF_14_15 (0 << 10)
120#endif
121
122#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
123 HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
124
125#ifdef CONFIG_GPIO_HYST_PORTG_0
126#define HYST_PORTG_0 (1 << 0)
127#else
128#define HYST_PORTG_0 (0 << 0)
129#endif
130#ifdef CONFIG_GPIO_HYST_PORTG_1_4
131#define HYST_PORTG_1_4 (1 << 2)
132#else
133#define HYST_PORTG_1_4 (0 << 2)
134#endif
135#ifdef CONFIG_GPIO_HYST_PORTG_5_6
136#define HYST_PORTG_5_6 (1 << 4)
137#else
138#define HYST_PORTG_5_6 (0 << 4)
139#endif
140#ifdef CONFIG_GPIO_HYST_PORTG_7_8
141#define HYST_PORTG_7_8 (1 << 6)
142#else
143#define HYST_PORTG_7_8 (0 << 6)
144#endif
145#ifdef CONFIG_GPIO_HYST_PORTG_9
146#define HYST_PORTG_9 (1 << 8)
147#else
148#define HYST_PORTG_9 (0 << 8)
149#endif
150#ifdef CONFIG_GPIO_HYST_PORTG_10
151#define HYST_PORTG_10 (1 << 10)
152#else
153#define HYST_PORTG_10 (0 << 10)
154#endif
155#ifdef CONFIG_GPIO_HYST_PORTG_11_13
156#define HYST_PORTG_11_13 (1 << 12)
157#else
158#define HYST_PORTG_11_13 (0 << 12)
159#endif
160#ifdef CONFIG_GPIO_HYST_PORTG_14_15
161#define HYST_PORTG_14_15 (1 << 14)
162#else
163#define HYST_PORTG_14_15 (0 << 14)
164#endif
165
166#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
167 HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
168 HYST_PORTG_11_13 | HYST_PORTG_14_15)
169
170#ifdef CONFIG_GPIO_HYST_PORTH_0_7
171#define HYST_PORTH_0_7 (1 << 0)
172#else
173#define HYST_PORTH_0_7 (0 << 0)
174#endif
175
176#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
177
178#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
179#define HYST_NMI_RST_BMODE (1 << 2)
180#else
181#define HYST_NMI_RST_BMODE (0 << 2)
182#endif
183#ifdef CONFIG_NONEGPIO_HYST_JTAG
184#define HYST_JTAG (1 << 4)
185#else
186#define HYST_JTAG (0 << 4)
187#endif
188
189#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
190#define HYST_NONEGPIO_MASK (0x3C)
191#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
192
88#ifdef CONFIG_BF518 193#ifdef CONFIG_BF518
89#define CPU "BF518" 194#define CPU "BF518"
90#define CPUID 0x27e8 195#define CPUID 0x27e8
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index 92e950d6e996..98a51c479290 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -45,139 +45,4 @@
45#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ 45#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
46#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ 46#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
47 47
48/* ********************************************************** */
49/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
50/* and MULTI BIT READ MACROS */
51/* ********************************************************** */
52
53/* Bit masks for SDH_COMMAND */
54
55#define CMD_IDX 0x3f /* Command Index */
56#define CMD_RSP 0x40 /* Response */
57#define CMD_L_RSP 0x80 /* Long Response */
58#define CMD_INT_E 0x100 /* Command Interrupt */
59#define CMD_PEND_E 0x200 /* Command Pending */
60#define CMD_E 0x400 /* Command Enable */
61
62/* Bit masks for SDH_PWR_CTL */
63
64#define PWR_ON 0x3 /* Power On */
65#if 0
66#define TBD 0x3c /* TBD */
67#endif
68#define SD_CMD_OD 0x40 /* Open Drain Output */
69#define ROD_CTL 0x80 /* Rod Control */
70
71/* Bit masks for SDH_CLK_CTL */
72
73#define CLKDIV 0xff /* MC_CLK Divisor */
74#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
75#define PWR_SV_E 0x200 /* Power Save Enable */
76#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
77#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
78
79/* Bit masks for SDH_RESP_CMD */
80
81#define RESP_CMD 0x3f /* Response Command */
82
83/* Bit masks for SDH_DATA_CTL */
84
85#define DTX_E 0x1 /* Data Transfer Enable */
86#define DTX_DIR 0x2 /* Data Transfer Direction */
87#define DTX_MODE 0x4 /* Data Transfer Mode */
88#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
89#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
90
91/* Bit masks for SDH_STATUS */
92
93#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
94#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
95#define CMD_TIME_OUT 0x4 /* CMD Time Out */
96#define DAT_TIME_OUT 0x8 /* Data Time Out */
97#define TX_UNDERRUN 0x10 /* Transmit Underrun */
98#define RX_OVERRUN 0x20 /* Receive Overrun */
99#define CMD_RESP_END 0x40 /* CMD Response End */
100#define CMD_SENT 0x80 /* CMD Sent */
101#define DAT_END 0x100 /* Data End */
102#define START_BIT_ERR 0x200 /* Start Bit Error */
103#define DAT_BLK_END 0x400 /* Data Block End */
104#define CMD_ACT 0x800 /* CMD Active */
105#define TX_ACT 0x1000 /* Transmit Active */
106#define RX_ACT 0x2000 /* Receive Active */
107#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
108#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
109#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
110#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
111#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
112#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
113#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
114#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
115
116/* Bit masks for SDH_STATUS_CLR */
117
118#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
119#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
120#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
121#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
122#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
123#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
124#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
125#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
126#define DAT_END_STAT 0x100 /* Data End Status */
127#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
128#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
129
130/* Bit masks for SDH_MASK0 */
131
132#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
133#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
134#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
135#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
136#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
137#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
138#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
139#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
140#define DAT_END_MASK 0x100 /* Data End Mask */
141#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
142#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
143#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
144#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
145#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
146#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
147#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
148#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
149#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
150#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
151#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
152#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
153#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
154
155/* Bit masks for SDH_FIFO_CNT */
156
157#define FIFO_COUNT 0x7fff /* FIFO Count */
158
159/* Bit masks for SDH_E_STATUS */
160
161#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
162#define SD_CARD_DET 0x10 /* SD Card Detect */
163
164/* Bit masks for SDH_E_MASK */
165
166#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
167#define SCD_MSK 0x40 /* Mask Card Detect */
168
169/* Bit masks for SDH_CFG */
170
171#define CLKS_EN 0x1 /* Clocks Enable */
172#define SD4E 0x4 /* SDIO 4-Bit Enable */
173#define MWE 0x8 /* Moving Window Enable */
174#define SD_RST 0x10 /* SDMMC Reset */
175#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
176#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
177#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
178
179/* Bit masks for SDH_RD_WAIT_EN */
180
181#define RWR 0x1 /* Read Wait Request */
182
183#endif /* _DEF_BF514_H */ 48#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 9241205fb992..2bc8f4f98011 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -458,22 +458,22 @@
458 458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400 460#define TWI0_REGBASE 0xFFC01400
461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 461#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 462#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 463#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 464#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 465#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 466#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 467#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 468#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ 469#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ 470#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 471#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 472#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 473#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 474#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 475#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 476#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477 477
478 478
479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
@@ -1319,7 +1319,7 @@
1319#define TWI_ENA 0x0080 /* TWI Enable */ 1319#define TWI_ENA 0x0080 /* TWI Enable */
1320#define SCCB 0x0200 /* SCCB Compatibility Enable */ 1320#define SCCB 0x0200 /* SCCB Compatibility Enable */
1321 1321
1322/* TWI_SLAVE_CTRL Masks */ 1322/* TWI_SLAVE_CTL Masks */
1323#define SEN 0x0001 /* Slave Enable */ 1323#define SEN 0x0001 /* Slave Enable */
1324#define SADD_LEN 0x0002 /* Slave Address Length */ 1324#define SADD_LEN 0x0002 /* Slave Address Length */
1325#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1325#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@@ -1330,7 +1330,7 @@
1330#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1330#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1331#define GCALL 0x0002 /* General Call Indicator */ 1331#define GCALL 0x0002 /* General Call Indicator */
1332 1332
1333/* TWI_MASTER_CTRL Masks */ 1333/* TWI_MASTER_CTL Masks */
1334#define MEN 0x0001 /* Master Mode Enable */ 1334#define MEN 0x0001 /* Master Mode Enable */
1335#define MADD_LEN 0x0002 /* Master Address Length */ 1335#define MADD_LEN 0x0002 /* Master Address Length */
1336#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 1336#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
@@ -1576,114 +1576,6 @@
1576 1576
1577#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ 1577#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1578 1578
1579/* Bit masks for CNT_CONFIG */
1580
1581#define CNTE 0x1 /* Counter Enable */
1582#define nCNTE 0x0
1583#define DEBE 0x2 /* Debounce Enable */
1584#define nDEBE 0x0
1585#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1586#define nCDGINV 0x0
1587#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1588#define nCUDINV 0x0
1589#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1590#define nCZMINV 0x0
1591#define CNTMODE 0x700 /* Counter Operating Mode */
1592#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1593#define nZMZC 0x0
1594#define BNDMODE 0x3000 /* Boundary register Mode */
1595#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1596#define nINPDIS 0x0
1597
1598/* Bit masks for CNT_IMASK */
1599
1600#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1601#define nICIE 0x0
1602#define UCIE 0x2 /* Up count Interrupt Enable */
1603#define nUCIE 0x0
1604#define DCIE 0x4 /* Down count Interrupt Enable */
1605#define nDCIE 0x0
1606#define MINCIE 0x8 /* Min Count Interrupt Enable */
1607#define nMINCIE 0x0
1608#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1609#define nMAXCIE 0x0
1610#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1611#define nCOV31IE 0x0
1612#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1613#define nCOV15IE 0x0
1614#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1615#define nCZEROIE 0x0
1616#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1617#define nCZMIE 0x0
1618#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1619#define nCZMEIE 0x0
1620#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1621#define nCZMZIE 0x0
1622
1623/* Bit masks for CNT_STATUS */
1624
1625#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1626#define nICII 0x0
1627#define UCII 0x2 /* Up count Interrupt Identifier */
1628#define nUCII 0x0
1629#define DCII 0x4 /* Down count Interrupt Identifier */
1630#define nDCII 0x0
1631#define MINCII 0x8 /* Min Count Interrupt Identifier */
1632#define nMINCII 0x0
1633#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1634#define nMAXCII 0x0
1635#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1636#define nCOV31II 0x0
1637#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1638#define nCOV15II 0x0
1639#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1640#define nCZEROII 0x0
1641#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1642#define nCZMII 0x0
1643#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1644#define nCZMEII 0x0
1645#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1646#define nCZMZII 0x0
1647
1648/* Bit masks for CNT_COMMAND */
1649
1650#define W1LCNT 0xf /* Load Counter Register */
1651#define W1LMIN 0xf0 /* Load Min Register */
1652#define W1LMAX 0xf00 /* Load Max Register */
1653#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1654#define nW1ZMONCE 0x0
1655
1656/* Bit masks for CNT_DEBOUNCE */
1657
1658#define DPRESCALE 0xf /* Load Counter Register */
1659
1660/* CNT_COMMAND bit field options */
1661
1662#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1663#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1664#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1665
1666#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1667#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1668#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1669
1670#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1671#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1672#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1673
1674/* CNT_CONFIG bit field options */
1675
1676#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1677#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1678#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1679#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1680#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1681
1682#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1683#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1684#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1685#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1686
1687/* Bit masks for SECURE_SYSSWT */ 1579/* Bit masks for SECURE_SYSSWT */
1688 1580
1689#define EMUDABL 0x1 /* Emulation Disable. */ 1581#define EMUDABL 0x1 /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
index bbab2d76499c..9af6ce0f6321 100644
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf518/include/mach/gpio.h
@@ -7,48 +7,49 @@
7#ifndef _MACH_GPIO_H_ 7#ifndef _MACH_GPIO_H_
8#define _MACH_GPIO_H_ 8#define _MACH_GPIO_H_
9 9
10#define MAX_BLACKFIN_GPIOS 40 10#define MAX_BLACKFIN_GPIOS 41
11 11
12#define GPIO_PF0 0 12#define GPIO_PF0 0
13#define GPIO_PF1 1 13#define GPIO_PF1 1
14#define GPIO_PF2 2 14#define GPIO_PF2 2
15#define GPIO_PF3 3 15#define GPIO_PF3 3
16#define GPIO_PF4 4 16#define GPIO_PF4 4
17#define GPIO_PF5 5 17#define GPIO_PF5 5
18#define GPIO_PF6 6 18#define GPIO_PF6 6
19#define GPIO_PF7 7 19#define GPIO_PF7 7
20#define GPIO_PF8 8 20#define GPIO_PF8 8
21#define GPIO_PF9 9 21#define GPIO_PF9 9
22#define GPIO_PF10 10 22#define GPIO_PF10 10
23#define GPIO_PF11 11 23#define GPIO_PF11 11
24#define GPIO_PF12 12 24#define GPIO_PF12 12
25#define GPIO_PF13 13 25#define GPIO_PF13 13
26#define GPIO_PF14 14 26#define GPIO_PF14 14
27#define GPIO_PF15 15 27#define GPIO_PF15 15
28#define GPIO_PG0 16 28#define GPIO_PG0 16
29#define GPIO_PG1 17 29#define GPIO_PG1 17
30#define GPIO_PG2 18 30#define GPIO_PG2 18
31#define GPIO_PG3 19 31#define GPIO_PG3 19
32#define GPIO_PG4 20 32#define GPIO_PG4 20
33#define GPIO_PG5 21 33#define GPIO_PG5 21
34#define GPIO_PG6 22 34#define GPIO_PG6 22
35#define GPIO_PG7 23 35#define GPIO_PG7 23
36#define GPIO_PG8 24 36#define GPIO_PG8 24
37#define GPIO_PG9 25 37#define GPIO_PG9 25
38#define GPIO_PG10 26 38#define GPIO_PG10 26
39#define GPIO_PG11 27 39#define GPIO_PG11 27
40#define GPIO_PG12 28 40#define GPIO_PG12 28
41#define GPIO_PG13 29 41#define GPIO_PG13 29
42#define GPIO_PG14 30 42#define GPIO_PG14 30
43#define GPIO_PG15 31 43#define GPIO_PG15 31
44#define GPIO_PH0 32 44#define GPIO_PH0 32
45#define GPIO_PH1 33 45#define GPIO_PH1 33
46#define GPIO_PH2 34 46#define GPIO_PH2 34
47#define GPIO_PH3 35 47#define GPIO_PH3 35
48#define GPIO_PH4 36 48#define GPIO_PH4 36
49#define GPIO_PH5 37 49#define GPIO_PH5 37
50#define GPIO_PH6 38 50#define GPIO_PH6 38
51#define GPIO_PH7 39 51#define GPIO_PH7 39
52#define GPIO_PH8 40
52 53
53#define PORT_F GPIO_PF0 54#define PORT_F GPIO_PF0
54#define PORT_G GPIO_PG0 55#define PORT_G GPIO_PG0
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
index e352910f7f99..cd84a569b04e 100644
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11 11
12/* EMAC MII/RMII Port Mux */ 12/* EMAC MII/RMII Port Mux */
13#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 13#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
@@ -95,7 +95,7 @@
95#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) 95#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
96#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) 96#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
97#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) 97#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
98#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) 98#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
99#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) 99#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
100 100
101#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) 101#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
@@ -109,6 +109,7 @@
109#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) 109#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
110#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) 110#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
111 111
112#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
112#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 113#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
113 114
114/* SPORT Port Mux */ 115/* SPORT Port Mux */
@@ -195,6 +196,6 @@
195#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) 196#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
196#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) 197#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
197 198
198#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1)) 199#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
199 200
200#endif /* _MACH_PORTMUX_H_ */ 201#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 1f8cbe9d6b9a..0ba54701af0b 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -79,6 +79,72 @@ config BF527_NAND_D_PORTH
79 PORT H 79 PORT H
80endchoice 80endchoice
81 81
82comment "Hysteresis/Schmitt Trigger Control"
83config BFIN_HYSTERESIS_CONTROL
84 bool "Enable Hysteresis Control"
85 help
86 The ADSP-BF52x allows to control input hysteresis for Port F,
87 Port G and Port H and other processor signal inputs.
88 The Schmitt trigger enables can be set only for pin groups.
89 Saying Y will overwrite the default reset or boot loader
90 initialization.
91
92menu "PORT F"
93 depends on BFIN_HYSTERESIS_CONTROL
94config GPIO_HYST_PORTF_0_7
95 bool "Enable Hysteresis on PORTF {0...7}"
96config GPIO_HYST_PORTF_8_9
97 bool "Enable Hysteresis on PORTF {8, 9}"
98config GPIO_HYST_PORTF_10
99 bool "Enable Hysteresis on PORTF 10"
100config GPIO_HYST_PORTF_11
101 bool "Enable Hysteresis on PORTF 11"
102config GPIO_HYST_PORTF_12_13
103 bool "Enable Hysteresis on PORTF {12, 13}"
104config GPIO_HYST_PORTF_14_15
105 bool "Enable Hysteresis on PORTF {14, 15}"
106endmenu
107
108menu "PORT G"
109 depends on BFIN_HYSTERESIS_CONTROL
110config GPIO_HYST_PORTG_0
111 bool "Enable Hysteresis on PORTG 0"
112config GPIO_HYST_PORTG_1_4
113 bool "Enable Hysteresis on PORTG {1...4}"
114config GPIO_HYST_PORTG_5_6
115 bool "Enable Hysteresis on PORTG {5, 6}"
116config GPIO_HYST_PORTG_7_8
117 bool "Enable Hysteresis on PORTG {7, 8}"
118config GPIO_HYST_PORTG_9
119 bool "Enable Hysteresis on PORTG 9"
120config GPIO_HYST_PORTG_10
121 bool "Enable Hysteresis on PORTG 10"
122config GPIO_HYST_PORTG_11_13
123 bool "Enable Hysteresis on PORTG {11...13}"
124config GPIO_HYST_PORTG_14_15
125 bool "Enable Hysteresis on PORTG {14, 15}"
126endmenu
127
128menu "PORT H"
129 depends on BFIN_HYSTERESIS_CONTROL
130config GPIO_HYST_PORTH_0_7
131 bool "Enable Hysteresis on PORTH {0...7}"
132config GPIO_HYST_PORTH_8
133 bool "Enable Hysteresis on PORTH 8"
134config GPIO_HYST_PORTH_9_15
135 bool "Enable Hysteresis on PORTH {9...15}"
136endmenu
137
138menu "None-GPIO"
139 depends on BFIN_HYSTERESIS_CONTROL
140config NONEGPIO_HYST_TMR0_FS1_PPICLK
141 bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
142config NONEGPIO_HYST_NMI_RST_BMODE
143 bool "Enable Hysteresis on {NMI, RESET, BMODE}"
144config NONEGPIO_HYST_JTAG
145 bool "Enable Hysteresis on JTAG"
146endmenu
147
82comment "Interrupt Priority Assignment" 148comment "Interrupt Priority Assignment"
83menu "Priority" 149menu "Priority"
84 150
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 02040df8ec80..9358afa05c90 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
@@ -41,7 +41,7 @@
41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
42#define ANOMALY_05000074 (1) 42#define ANOMALY_05000074 (1)
43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
44#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 44#define ANOMALY_05000119 (1)
45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
46#define ANOMALY_05000122 (1) 46#define ANOMALY_05000122 (1)
47/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 47/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -168,6 +168,8 @@
168#define ANOMALY_05000431 (1) 168#define ANOMALY_05000431 (1)
169/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ 169/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
170#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) 170#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
171/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
172#define ANOMALY_05000434 (1)
171/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 173/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
172#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) 174#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
173/* Preboot Cannot be Used to Alter the PLL_DIV Register */ 175/* Preboot Cannot be Used to Alter the PLL_DIV Register */
@@ -204,10 +206,22 @@
204#define ANOMALY_05000467 (1) 206#define ANOMALY_05000467 (1)
205/* PLL Latches Incorrect Settings During Reset */ 207/* PLL Latches Incorrect Settings During Reset */
206#define ANOMALY_05000469 (1) 208#define ANOMALY_05000469 (1)
209/* Incorrect Default MSEL Value in PLL_CTL */
210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
207/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 211/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
208#define ANOMALY_05000473 (1) 212#define ANOMALY_05000473 (1)
213/* Possible Lockup Condition whem Modifying PLL from External Memory */
214#define ANOMALY_05000475 (1)
209/* TESTSET Instruction Cannot Be Interrupted */ 215/* TESTSET Instruction Cannot Be Interrupted */
210#define ANOMALY_05000477 (1) 216#define ANOMALY_05000477 (1)
217/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
218#define ANOMALY_05000481 (1)
219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
223/* IFLUSH sucks at life */
224#define ANOMALY_05000491 (1)
211 225
212/* Anomalies that don't exist on this proc */ 226/* Anomalies that don't exist on this proc */
213#define ANOMALY_05000099 (0) 227#define ANOMALY_05000099 (0)
@@ -223,6 +237,7 @@
223#define ANOMALY_05000198 (0) 237#define ANOMALY_05000198 (0)
224#define ANOMALY_05000202 (0) 238#define ANOMALY_05000202 (0)
225#define ANOMALY_05000215 (0) 239#define ANOMALY_05000215 (0)
240#define ANOMALY_05000219 (0)
226#define ANOMALY_05000220 (0) 241#define ANOMALY_05000220 (0)
227#define ANOMALY_05000227 (0) 242#define ANOMALY_05000227 (0)
228#define ANOMALY_05000230 (0) 243#define ANOMALY_05000230 (0)
@@ -259,6 +274,5 @@
259#define ANOMALY_05000447 (0) 274#define ANOMALY_05000447 (0)
260#define ANOMALY_05000448 (0) 275#define ANOMALY_05000448 (0)
261#define ANOMALY_05000474 (0) 276#define ANOMALY_05000474 (0)
262#define ANOMALY_05000475 (0)
263 277
264#endif 278#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
index ff68c8897087..8ff155b34f64 100644
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -85,6 +85,126 @@
85 85
86#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 86#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
87 87
88/**************************** Hysteresis Settings ****************************/
89
90#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
91#ifdef CONFIG_GPIO_HYST_PORTF_0_7
92#define HYST_PORTF_0_7 (1 << 0)
93#else
94#define HYST_PORTF_0_7 (0 << 0)
95#endif
96#ifdef CONFIG_GPIO_HYST_PORTF_8_9
97#define HYST_PORTF_8_9 (1 << 2)
98#else
99#define HYST_PORTF_8_9 (0 << 2)
100#endif
101#ifdef CONFIG_GPIO_HYST_PORTF_10
102#define HYST_PORTF_10 (1 << 4)
103#else
104#define HYST_PORTF_10 (0 << 4)
105#endif
106#ifdef CONFIG_GPIO_HYST_PORTF_11
107#define HYST_PORTF_11 (1 << 6)
108#else
109#define HYST_PORTF_11 (0 << 6)
110#endif
111#ifdef CONFIG_GPIO_HYST_PORTF_12_13
112#define HYST_PORTF_12_13 (1 << 8)
113#else
114#define HYST_PORTF_12_13 (0 << 8)
115#endif
116#ifdef CONFIG_GPIO_HYST_PORTF_14_15
117#define HYST_PORTF_14_15 (1 << 10)
118#else
119#define HYST_PORTF_14_15 (0 << 10)
120#endif
121
122#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
123 HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
124
125#ifdef CONFIG_GPIO_HYST_PORTG_0
126#define HYST_PORTG_0 (1 << 0)
127#else
128#define HYST_PORTG_0 (0 << 0)
129#endif
130#ifdef CONFIG_GPIO_HYST_PORTG_1_4
131#define HYST_PORTG_1_4 (1 << 2)
132#else
133#define HYST_PORTG_1_4 (0 << 2)
134#endif
135#ifdef CONFIG_GPIO_HYST_PORTG_5_6
136#define HYST_PORTG_5_6 (1 << 4)
137#else
138#define HYST_PORTG_5_6 (0 << 4)
139#endif
140#ifdef CONFIG_GPIO_HYST_PORTG_7_8
141#define HYST_PORTG_7_8 (1 << 6)
142#else
143#define HYST_PORTG_7_8 (0 << 6)
144#endif
145#ifdef CONFIG_GPIO_HYST_PORTG_9
146#define HYST_PORTG_9 (1 << 8)
147#else
148#define HYST_PORTG_9 (0 << 8)
149#endif
150#ifdef CONFIG_GPIO_HYST_PORTG_10
151#define HYST_PORTG_10 (1 << 10)
152#else
153#define HYST_PORTG_10 (0 << 10)
154#endif
155#ifdef CONFIG_GPIO_HYST_PORTG_11_13
156#define HYST_PORTG_11_13 (1 << 12)
157#else
158#define HYST_PORTG_11_13 (0 << 12)
159#endif
160#ifdef CONFIG_GPIO_HYST_PORTG_14_15
161#define HYST_PORTG_14_15 (1 << 14)
162#else
163#define HYST_PORTG_14_15 (0 << 14)
164#endif
165
166#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
167 HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
168 HYST_PORTG_11_13 | HYST_PORTG_14_15)
169
170#ifdef CONFIG_GPIO_HYST_PORTH_0_7
171#define HYST_PORTH_0_7 (1 << 0)
172#else
173#define HYST_PORTH_0_7 (0 << 0)
174#endif
175#ifdef CONFIG_GPIO_HYST_PORTH_8
176#define HYST_PORTH_8 (1 << 2)
177#else
178#define HYST_PORTH_8 (0 << 2)
179#endif
180#ifdef CONFIG_GPIO_HYST_PORTH_9_15
181#define HYST_PORTH_9_15 (1 << 4)
182#else
183#define HYST_PORTH_9_15 (0 << 4)
184#endif
185
186#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
187
188#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
189#define HYST_TMR0_FS1_PPICLK (1 << 0)
190#else
191#define HYST_TMR0_FS1_PPICLK (0 << 0)
192#endif
193#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
194#define HYST_NMI_RST_BMODE (1 << 2)
195#else
196#define HYST_NMI_RST_BMODE (0 << 2)
197#endif
198#ifdef CONFIG_NONEGPIO_HYST_JTAG
199#define HYST_JTAG (1 << 4)
200#else
201#define HYST_JTAG (0 << 4)
202#endif
203
204#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
205#define HYST_NONEGPIO_MASK (0x3F)
206#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
207
88#ifdef CONFIG_BF527 208#ifdef CONFIG_BF527
89#define CPU "BF527" 209#define CPU "BF527"
90#define CPUID 0x27e0 210#define CPUID 0x27e0
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 8b18b5359210..5f97f01fcda6 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -458,22 +458,22 @@
458 458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400 460#define TWI0_REGBASE 0xFFC01400
461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 461#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 462#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 463#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 464#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 465#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 466#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 467#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 468#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ 469#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ 470#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 471#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 472#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 473#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 474#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 475#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 476#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477 477
478 478
479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
@@ -1328,7 +1328,7 @@
1328#define TWI_ENA 0x0080 /* TWI Enable */ 1328#define TWI_ENA 0x0080 /* TWI Enable */
1329#define SCCB 0x0200 /* SCCB Compatibility Enable */ 1329#define SCCB 0x0200 /* SCCB Compatibility Enable */
1330 1330
1331/* TWI_SLAVE_CTRL Masks */ 1331/* TWI_SLAVE_CTL Masks */
1332#define SEN 0x0001 /* Slave Enable */ 1332#define SEN 0x0001 /* Slave Enable */
1333#define SADD_LEN 0x0002 /* Slave Address Length */ 1333#define SADD_LEN 0x0002 /* Slave Address Length */
1334#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1334#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@@ -1339,7 +1339,7 @@
1339#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1339#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1340#define GCALL 0x0002 /* General Call Indicator */ 1340#define GCALL 0x0002 /* General Call Indicator */
1341 1341
1342/* TWI_MASTER_CTRL Masks */ 1342/* TWI_MASTER_CTL Masks */
1343#define MEN 0x0001 /* Master Mode Enable */ 1343#define MEN 0x0001 /* Master Mode Enable */
1344#define MADD_LEN 0x0002 /* Master Address Length */ 1344#define MADD_LEN 0x0002 /* Master Address Length */
1345#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 1345#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
@@ -1589,114 +1589,6 @@
1589 1589
1590#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ 1590#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1591 1591
1592/* Bit masks for CNT_CONFIG */
1593
1594#define CNTE 0x1 /* Counter Enable */
1595#define nCNTE 0x0
1596#define DEBE 0x2 /* Debounce Enable */
1597#define nDEBE 0x0
1598#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1599#define nCDGINV 0x0
1600#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1601#define nCUDINV 0x0
1602#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1603#define nCZMINV 0x0
1604#define CNTMODE 0x700 /* Counter Operating Mode */
1605#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1606#define nZMZC 0x0
1607#define BNDMODE 0x3000 /* Boundary register Mode */
1608#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1609#define nINPDIS 0x0
1610
1611/* Bit masks for CNT_IMASK */
1612
1613#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1614#define nICIE 0x0
1615#define UCIE 0x2 /* Up count Interrupt Enable */
1616#define nUCIE 0x0
1617#define DCIE 0x4 /* Down count Interrupt Enable */
1618#define nDCIE 0x0
1619#define MINCIE 0x8 /* Min Count Interrupt Enable */
1620#define nMINCIE 0x0
1621#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1622#define nMAXCIE 0x0
1623#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1624#define nCOV31IE 0x0
1625#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1626#define nCOV15IE 0x0
1627#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1628#define nCZEROIE 0x0
1629#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1630#define nCZMIE 0x0
1631#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1632#define nCZMEIE 0x0
1633#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1634#define nCZMZIE 0x0
1635
1636/* Bit masks for CNT_STATUS */
1637
1638#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1639#define nICII 0x0
1640#define UCII 0x2 /* Up count Interrupt Identifier */
1641#define nUCII 0x0
1642#define DCII 0x4 /* Down count Interrupt Identifier */
1643#define nDCII 0x0
1644#define MINCII 0x8 /* Min Count Interrupt Identifier */
1645#define nMINCII 0x0
1646#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1647#define nMAXCII 0x0
1648#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1649#define nCOV31II 0x0
1650#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1651#define nCOV15II 0x0
1652#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1653#define nCZEROII 0x0
1654#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1655#define nCZMII 0x0
1656#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1657#define nCZMEII 0x0
1658#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1659#define nCZMZII 0x0
1660
1661/* Bit masks for CNT_COMMAND */
1662
1663#define W1LCNT 0xf /* Load Counter Register */
1664#define W1LMIN 0xf0 /* Load Min Register */
1665#define W1LMAX 0xf00 /* Load Max Register */
1666#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1667#define nW1ZMONCE 0x0
1668
1669/* Bit masks for CNT_DEBOUNCE */
1670
1671#define DPRESCALE 0xf /* Load Counter Register */
1672
1673/* CNT_COMMAND bit field options */
1674
1675#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1676#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1677#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1678
1679#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1680#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1681#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1682
1683#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1684#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1685#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1686
1687/* CNT_CONFIG bit field options */
1688
1689#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1690#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1691#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1692#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1693#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1694
1695#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1696#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1697#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1698#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1699
1700/* Bit masks for SECURE_SYSSWT */ 1592/* Bit masks for SECURE_SYSSWT */
1701 1593
1702#define EMUDABL 0x1 /* Emulation Disable. */ 1594#define EMUDABL 0x1 /* Emulation Disable. */
@@ -1738,85 +1630,4 @@
1738#define nAFEXIT 0x0 1630#define nAFEXIT 0x0
1739#define SECSTAT 0xe0 /* Secure Status */ 1631#define SECSTAT 0xe0 /* Secure Status */
1740 1632
1741/* Bit masks for NFC_CTL */
1742
1743#define WR_DLY 0xf /* Write Strobe Delay */
1744#define RD_DLY 0xf0 /* Read Strobe Delay */
1745#define NWIDTH 0x100 /* NAND Data Width */
1746#define nNWIDTH 0x0
1747#define PG_SIZE 0x200 /* Page Size */
1748#define nPG_SIZE 0x0
1749
1750/* Bit masks for NFC_STAT */
1751
1752#define NBUSY 0x1 /* Not Busy */
1753#define nNBUSY 0x0
1754#define WB_FULL 0x2 /* Write Buffer Full */
1755#define nWB_FULL 0x0
1756#define PG_WR_STAT 0x4 /* Page Write Pending */
1757#define nPG_WR_STAT 0x0
1758#define PG_RD_STAT 0x8 /* Page Read Pending */
1759#define nPG_RD_STAT 0x0
1760#define WB_EMPTY 0x10 /* Write Buffer Empty */
1761#define nWB_EMPTY 0x0
1762
1763/* Bit masks for NFC_IRQSTAT */
1764
1765#define NBUSYIRQ 0x1 /* Not Busy IRQ */
1766#define nNBUSYIRQ 0x0
1767#define WB_OVF 0x2 /* Write Buffer Overflow */
1768#define nWB_OVF 0x0
1769#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
1770#define nWB_EDGE 0x0
1771#define RD_RDY 0x8 /* Read Data Ready */
1772#define nRD_RDY 0x0
1773#define WR_DONE 0x10 /* Page Write Done */
1774#define nWR_DONE 0x0
1775
1776/* Bit masks for NFC_IRQMASK */
1777
1778#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
1779#define nMASK_BUSYIRQ 0x0
1780#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
1781#define nMASK_WBOVF 0x0
1782#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
1783#define nMASK_WBEMPTY 0x0
1784#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
1785#define nMASK_RDRDY 0x0
1786#define MASK_WRDONE 0x10 /* Mask Write Done */
1787#define nMASK_WRDONE 0x0
1788
1789/* Bit masks for NFC_RST */
1790
1791#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
1792#define nECC_RST 0x0
1793
1794/* Bit masks for NFC_PGCTL */
1795
1796#define PG_RD_START 0x1 /* Page Read Start */
1797#define nPG_RD_START 0x0
1798#define PG_WR_START 0x2 /* Page Write Start */
1799#define nPG_WR_START 0x0
1800
1801/* Bit masks for NFC_ECC0 */
1802
1803#define ECC0 0x7ff /* Parity Calculation Result0 */
1804
1805/* Bit masks for NFC_ECC1 */
1806
1807#define ECC1 0x7ff /* Parity Calculation Result1 */
1808
1809/* Bit masks for NFC_ECC2 */
1810
1811#define ECC2 0x7ff /* Parity Calculation Result2 */
1812
1813/* Bit masks for NFC_ECC3 */
1814
1815#define ECC3 0x7ff /* Parity Calculation Result3 */
1816
1817/* Bit masks for NFC_COUNT */
1818
1819#define ECCCNT 0x3ff /* Transfer Count */
1820
1821
1822#endif /* _DEF_BF52X_H */ 1633#endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
index 104bff85290d..f80c2995efdb 100644
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -9,54 +9,54 @@
9 9
10#define MAX_BLACKFIN_GPIOS 48 10#define MAX_BLACKFIN_GPIOS 48
11 11
12#define GPIO_PF0 0 12#define GPIO_PF0 0
13#define GPIO_PF1 1 13#define GPIO_PF1 1
14#define GPIO_PF2 2 14#define GPIO_PF2 2
15#define GPIO_PF3 3 15#define GPIO_PF3 3
16#define GPIO_PF4 4 16#define GPIO_PF4 4
17#define GPIO_PF5 5 17#define GPIO_PF5 5
18#define GPIO_PF6 6 18#define GPIO_PF6 6
19#define GPIO_PF7 7 19#define GPIO_PF7 7
20#define GPIO_PF8 8 20#define GPIO_PF8 8
21#define GPIO_PF9 9 21#define GPIO_PF9 9
22#define GPIO_PF10 10 22#define GPIO_PF10 10
23#define GPIO_PF11 11 23#define GPIO_PF11 11
24#define GPIO_PF12 12 24#define GPIO_PF12 12
25#define GPIO_PF13 13 25#define GPIO_PF13 13
26#define GPIO_PF14 14 26#define GPIO_PF14 14
27#define GPIO_PF15 15 27#define GPIO_PF15 15
28#define GPIO_PG0 16 28#define GPIO_PG0 16
29#define GPIO_PG1 17 29#define GPIO_PG1 17
30#define GPIO_PG2 18 30#define GPIO_PG2 18
31#define GPIO_PG3 19 31#define GPIO_PG3 19
32#define GPIO_PG4 20 32#define GPIO_PG4 20
33#define GPIO_PG5 21 33#define GPIO_PG5 21
34#define GPIO_PG6 22 34#define GPIO_PG6 22
35#define GPIO_PG7 23 35#define GPIO_PG7 23
36#define GPIO_PG8 24 36#define GPIO_PG8 24
37#define GPIO_PG9 25 37#define GPIO_PG9 25
38#define GPIO_PG10 26 38#define GPIO_PG10 26
39#define GPIO_PG11 27 39#define GPIO_PG11 27
40#define GPIO_PG12 28 40#define GPIO_PG12 28
41#define GPIO_PG13 29 41#define GPIO_PG13 29
42#define GPIO_PG14 30 42#define GPIO_PG14 30
43#define GPIO_PG15 31 43#define GPIO_PG15 31
44#define GPIO_PH0 32 44#define GPIO_PH0 32
45#define GPIO_PH1 33 45#define GPIO_PH1 33
46#define GPIO_PH2 34 46#define GPIO_PH2 34
47#define GPIO_PH3 35 47#define GPIO_PH3 35
48#define GPIO_PH4 36 48#define GPIO_PH4 36
49#define GPIO_PH5 37 49#define GPIO_PH5 37
50#define GPIO_PH6 38 50#define GPIO_PH6 38
51#define GPIO_PH7 39 51#define GPIO_PH7 39
52#define GPIO_PH8 40 52#define GPIO_PH8 40
53#define GPIO_PH9 41 53#define GPIO_PH9 41
54#define GPIO_PH10 42 54#define GPIO_PH10 42
55#define GPIO_PH11 43 55#define GPIO_PH11 43
56#define GPIO_PH12 44 56#define GPIO_PH12 44
57#define GPIO_PH13 45 57#define GPIO_PH13 45
58#define GPIO_PH14 46 58#define GPIO_PH14 46
59#define GPIO_PH15 47 59#define GPIO_PH15 47
60 60
61#define PORT_F GPIO_PF0 61#define PORT_F GPIO_PF0
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
index d4518b6f4adf..08bae421f5c9 100644
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf527/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11 11
12#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 12#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
13#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 13#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
@@ -79,6 +79,7 @@
79 79
80#define P_HWAIT (P_DONTCARE) 80#define P_HWAIT (P_DONTCARE)
81 81
82#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
82#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 83#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
83 84
84#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) 85#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 9b3f7a27714d..78f872187918 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -208,8 +208,14 @@
208#define ANOMALY_05000461 (1) 208#define ANOMALY_05000461 (1)
209/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 209/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
210#define ANOMALY_05000473 (1) 210#define ANOMALY_05000473 (1)
211/* Possible Lockup Condition whem Modifying PLL from External Memory */
212#define ANOMALY_05000475 (1)
211/* TESTSET Instruction Cannot Be Interrupted */ 213/* TESTSET Instruction Cannot Be Interrupted */
212#define ANOMALY_05000477 (1) 214#define ANOMALY_05000477 (1)
215/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
216#define ANOMALY_05000481 (1)
217/* IFLUSH sucks at life */
218#define ANOMALY_05000491 (1)
213 219
214/* These anomalies have been "phased" out of analog.com anomaly sheets and are 220/* These anomalies have been "phased" out of analog.com anomaly sheets and are
215 * here to show running on older silicon just isn't feasible. 221 * here to show running on older silicon just isn't feasible.
@@ -358,6 +364,6 @@
358#define ANOMALY_05000465 (0) 364#define ANOMALY_05000465 (0)
359#define ANOMALY_05000467 (0) 365#define ANOMALY_05000467 (0)
360#define ANOMALY_05000474 (0) 366#define ANOMALY_05000474 (0)
361#define ANOMALY_05000475 (0) 367#define ANOMALY_05000485 (0)
362 368
363#endif 369#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
index 2af19d69a7a7..e02416db4b00 100644
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf533/include/mach/gpio.h
@@ -9,22 +9,22 @@
9 9
10#define MAX_BLACKFIN_GPIOS 16 10#define MAX_BLACKFIN_GPIOS 16
11 11
12#define GPIO_PF0 0 12#define GPIO_PF0 0
13#define GPIO_PF1 1 13#define GPIO_PF1 1
14#define GPIO_PF2 2 14#define GPIO_PF2 2
15#define GPIO_PF3 3 15#define GPIO_PF3 3
16#define GPIO_PF4 4 16#define GPIO_PF4 4
17#define GPIO_PF5 5 17#define GPIO_PF5 5
18#define GPIO_PF6 6 18#define GPIO_PF6 6
19#define GPIO_PF7 7 19#define GPIO_PF7 7
20#define GPIO_PF8 8 20#define GPIO_PF8 8
21#define GPIO_PF9 9 21#define GPIO_PF9 9
22#define GPIO_PF10 10 22#define GPIO_PF10 10
23#define GPIO_PF11 11 23#define GPIO_PF11 11
24#define GPIO_PF12 12 24#define GPIO_PF12 12
25#define GPIO_PF13 13 25#define GPIO_PF13 13
26#define GPIO_PF14 14 26#define GPIO_PF14 14
27#define GPIO_PF15 15 27#define GPIO_PF15 15
28 28
29#define PORT_F GPIO_PF0 29#define PORT_F GPIO_PF0
30 30
diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h
index 075dae1af164..96f5d9129f20 100644
--- a/arch/blackfin/mach-bf533/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf533/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11 11
12#define P_PPI0_CLK (P_DONTCARE) 12#define P_PPI0_CLK (P_DONTCARE)
13#define P_PPI0_FS1 (P_DONTCARE) 13#define P_PPI0_FS1 (P_DONTCARE)
@@ -60,6 +60,7 @@
60#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) 60#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
61#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) 61#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
62#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) 62#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
63#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
63#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 64#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
64 65
65#define P_TMR2 (P_DONTCARE) 66#define P_TMR2 (P_DONTCARE)
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index d2c427bc6656..43df6afd22ad 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -162,8 +162,14 @@
162#define ANOMALY_05000461 (1) 162#define ANOMALY_05000461 (1)
163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
164#define ANOMALY_05000473 (1) 164#define ANOMALY_05000473 (1)
165/* Possible Lockup Condition whem Modifying PLL from External Memory */
166#define ANOMALY_05000475 (1)
165/* TESTSET Instruction Cannot Be Interrupted */ 167/* TESTSET Instruction Cannot Be Interrupted */
166#define ANOMALY_05000477 (1) 168#define ANOMALY_05000477 (1)
169/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
170#define ANOMALY_05000481 (1)
171/* IFLUSH sucks at life */
172#define ANOMALY_05000491 (1)
167 173
168/* Anomalies that don't exist on this proc */ 174/* Anomalies that don't exist on this proc */
169#define ANOMALY_05000099 (0) 175#define ANOMALY_05000099 (0)
@@ -179,6 +185,7 @@
179#define ANOMALY_05000198 (0) 185#define ANOMALY_05000198 (0)
180#define ANOMALY_05000202 (0) 186#define ANOMALY_05000202 (0)
181#define ANOMALY_05000215 (0) 187#define ANOMALY_05000215 (0)
188#define ANOMALY_05000219 (0)
182#define ANOMALY_05000220 (0) 189#define ANOMALY_05000220 (0)
183#define ANOMALY_05000227 (0) 190#define ANOMALY_05000227 (0)
184#define ANOMALY_05000230 (0) 191#define ANOMALY_05000230 (0)
@@ -211,6 +218,6 @@
211#define ANOMALY_05000465 (0) 218#define ANOMALY_05000465 (0)
212#define ANOMALY_05000467 (0) 219#define ANOMALY_05000467 (0)
213#define ANOMALY_05000474 (0) 220#define ANOMALY_05000474 (0)
214#define ANOMALY_05000475 (0) 221#define ANOMALY_05000485 (0)
215 222
216#endif 223#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index cf396ea40092..aad61b887373 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -434,22 +434,22 @@
434 434
435/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 435/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
436#define TWI0_REGBASE 0xFFC01400 436#define TWI0_REGBASE 0xFFC01400
437#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 437#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
438#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 438#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
439#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 439#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
440#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 440#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
441#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 441#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
442#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 442#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
443#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 443#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
444#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 444#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
445#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ 445#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
446#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ 446#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
447#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 447#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
448#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 448#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
449#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 449#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
450#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 450#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
451#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 451#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
452#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 452#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
453 453
454/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 454/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
455#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ 455#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
@@ -1642,7 +1642,7 @@
1642#define TWI_ENA 0x0080 /* TWI Enable */ 1642#define TWI_ENA 0x0080 /* TWI Enable */
1643#define SCCB 0x0200 /* SCCB Compatibility Enable */ 1643#define SCCB 0x0200 /* SCCB Compatibility Enable */
1644 1644
1645/* TWI_SLAVE_CTRL Masks */ 1645/* TWI_SLAVE_CTL Masks */
1646#define SEN 0x0001 /* Slave Enable */ 1646#define SEN 0x0001 /* Slave Enable */
1647#define SADD_LEN 0x0002 /* Slave Address Length */ 1647#define SADD_LEN 0x0002 /* Slave Address Length */
1648#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1648#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@@ -1653,7 +1653,7 @@
1653#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1653#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1654#define GCALL 0x0002 /* General Call Indicator */ 1654#define GCALL 0x0002 /* General Call Indicator */
1655 1655
1656/* TWI_MASTER_CTRL Masks */ 1656/* TWI_MASTER_CTL Masks */
1657#define MEN 0x0001 /* Master Mode Enable */ 1657#define MEN 0x0001 /* Master Mode Enable */
1658#define MADD_LEN 0x0002 /* Master Address Length */ 1658#define MADD_LEN 0x0002 /* Master Address Length */
1659#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 1659#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index 104bff85290d..f80c2995efdb 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -9,54 +9,54 @@
9 9
10#define MAX_BLACKFIN_GPIOS 48 10#define MAX_BLACKFIN_GPIOS 48
11 11
12#define GPIO_PF0 0 12#define GPIO_PF0 0
13#define GPIO_PF1 1 13#define GPIO_PF1 1
14#define GPIO_PF2 2 14#define GPIO_PF2 2
15#define GPIO_PF3 3 15#define GPIO_PF3 3
16#define GPIO_PF4 4 16#define GPIO_PF4 4
17#define GPIO_PF5 5 17#define GPIO_PF5 5
18#define GPIO_PF6 6 18#define GPIO_PF6 6
19#define GPIO_PF7 7 19#define GPIO_PF7 7
20#define GPIO_PF8 8 20#define GPIO_PF8 8
21#define GPIO_PF9 9 21#define GPIO_PF9 9
22#define GPIO_PF10 10 22#define GPIO_PF10 10
23#define GPIO_PF11 11 23#define GPIO_PF11 11
24#define GPIO_PF12 12 24#define GPIO_PF12 12
25#define GPIO_PF13 13 25#define GPIO_PF13 13
26#define GPIO_PF14 14 26#define GPIO_PF14 14
27#define GPIO_PF15 15 27#define GPIO_PF15 15
28#define GPIO_PG0 16 28#define GPIO_PG0 16
29#define GPIO_PG1 17 29#define GPIO_PG1 17
30#define GPIO_PG2 18 30#define GPIO_PG2 18
31#define GPIO_PG3 19 31#define GPIO_PG3 19
32#define GPIO_PG4 20 32#define GPIO_PG4 20
33#define GPIO_PG5 21 33#define GPIO_PG5 21
34#define GPIO_PG6 22 34#define GPIO_PG6 22
35#define GPIO_PG7 23 35#define GPIO_PG7 23
36#define GPIO_PG8 24 36#define GPIO_PG8 24
37#define GPIO_PG9 25 37#define GPIO_PG9 25
38#define GPIO_PG10 26 38#define GPIO_PG10 26
39#define GPIO_PG11 27 39#define GPIO_PG11 27
40#define GPIO_PG12 28 40#define GPIO_PG12 28
41#define GPIO_PG13 29 41#define GPIO_PG13 29
42#define GPIO_PG14 30 42#define GPIO_PG14 30
43#define GPIO_PG15 31 43#define GPIO_PG15 31
44#define GPIO_PH0 32 44#define GPIO_PH0 32
45#define GPIO_PH1 33 45#define GPIO_PH1 33
46#define GPIO_PH2 34 46#define GPIO_PH2 34
47#define GPIO_PH3 35 47#define GPIO_PH3 35
48#define GPIO_PH4 36 48#define GPIO_PH4 36
49#define GPIO_PH5 37 49#define GPIO_PH5 37
50#define GPIO_PH6 38 50#define GPIO_PH6 38
51#define GPIO_PH7 39 51#define GPIO_PH7 39
52#define GPIO_PH8 40 52#define GPIO_PH8 40
53#define GPIO_PH9 41 53#define GPIO_PH9 41
54#define GPIO_PH10 42 54#define GPIO_PH10 42
55#define GPIO_PH11 43 55#define GPIO_PH11 43
56#define GPIO_PH12 44 56#define GPIO_PH12 44
57#define GPIO_PH13 45 57#define GPIO_PH13 45
58#define GPIO_PH14 46 58#define GPIO_PH14 46
59#define GPIO_PH15 47 59#define GPIO_PH15 47
60 60
61#define PORT_F GPIO_PF0 61#define PORT_F GPIO_PF0
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
index da9760329e49..71d9eaeb579e 100644
--- a/arch/blackfin/mach-bf537/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf537/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ 10#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
11 11
12#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 12#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
13#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 13#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
@@ -37,6 +37,7 @@
37#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) 37#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
38#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) 38#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
39#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) 39#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
40#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
40#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 41#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
41 42
42#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) 43#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
@@ -135,7 +136,6 @@
135 P_MDC, \ 136 P_MDC, \
136 P_MDIO, 0} 137 P_MDIO, 0}
137 138
138
139#define P_RMII0 {\ 139#define P_RMII0 {\
140 P_MII0_ETxD0, \ 140 P_MII0_ETxD0, \
141 P_MII0_ETxD1, \ 141 P_MII0_ETxD1, \
@@ -148,4 +148,5 @@
148 P_RMII0_CRS_DV, \ 148 P_RMII0_CRS_DV, \
149 P_MDC, \ 149 P_MDC, \
150 P_MDIO, 0} 150 P_MDIO, 0}
151#endif /* _MACH_PORTMUX_H_ */ 151
152#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index d882b7e6f59b..8774b481c78e 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -5,14 +5,14 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List 14 * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
15 * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List 15 * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -132,10 +132,18 @@
132#define ANOMALY_05000443 (1) 132#define ANOMALY_05000443 (1)
133/* False Hardware Error when RETI Points to Invalid Memory */ 133/* False Hardware Error when RETI Points to Invalid Memory */
134#define ANOMALY_05000461 (1) 134#define ANOMALY_05000461 (1)
135/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
136#define ANOMALY_05000462 (1)
135/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 137/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
136#define ANOMALY_05000473 (1) 138#define ANOMALY_05000473 (1)
139/* Possible Lockup Condition whem Modifying PLL from External Memory */
140#define ANOMALY_05000475 (1)
137/* TESTSET Instruction Cannot Be Interrupted */ 141/* TESTSET Instruction Cannot Be Interrupted */
138#define ANOMALY_05000477 (1) 142#define ANOMALY_05000477 (1)
143/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
144#define ANOMALY_05000481 (1)
145/* IFLUSH sucks at life */
146#define ANOMALY_05000491 (1)
139 147
140/* Anomalies that don't exist on this proc */ 148/* Anomalies that don't exist on this proc */
141#define ANOMALY_05000099 (0) 149#define ANOMALY_05000099 (0)
@@ -185,6 +193,6 @@
185#define ANOMALY_05000465 (0) 193#define ANOMALY_05000465 (0)
186#define ANOMALY_05000467 (0) 194#define ANOMALY_05000467 (0)
187#define ANOMALY_05000474 (0) 195#define ANOMALY_05000474 (0)
188#define ANOMALY_05000475 (0) 196#define ANOMALY_05000485 (0)
189 197
190#endif 198#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 401ebd79d0aa..66aa722cf6c8 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -1293,70 +1293,6 @@
1293#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) 1293#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
1294#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 1294#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
1295#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) 1295#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
1296#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
1297#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
1298#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
1299#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
1300#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
1301#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
1302#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
1303#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
1304#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
1305#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
1306#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
1307#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
1308#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
1309#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
1310#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
1311#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
1312#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
1313#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
1314#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
1315#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
1316#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
1317#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
1318#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
1319#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
1320#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
1321#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
1322#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
1323#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
1324#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
1325#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
1326#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
1327#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
1328#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
1329#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
1330#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
1331#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
1332#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
1333#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
1334#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
1335#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
1336#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
1337#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
1338#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
1339#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
1340#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
1341#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
1342#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
1343#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
1344#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
1345#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
1346#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
1347#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
1348#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
1349#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
1350#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
1351#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
1352#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
1353#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
1354#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
1355#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
1356#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
1357#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
1358#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
1359#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
1360#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) 1296#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
1361#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) 1297#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
1362#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) 1298#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index d7061d9f2a83..b674a1c4aef1 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -442,15 +442,15 @@
442/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ 442/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
443#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 443#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
444#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ 444#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
445#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ 445#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
446#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 446#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
447#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 447#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
448#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ 448#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
449#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 449#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
450#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 450#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
451#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ 451#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
452#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ 452#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
453#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ 453#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
454#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 454#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
455#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 455#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
456#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 456#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
@@ -761,15 +761,15 @@
761/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ 761/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
762#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ 762#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
763#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ 763#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
764#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ 764#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
765#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ 765#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
766#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ 766#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
767#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ 767#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
768#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ 768#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
769#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ 769#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
770#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ 770#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
771#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ 771#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
772#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ 772#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
773#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ 773#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
774#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ 774#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
775#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ 775#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
@@ -2401,7 +2401,7 @@
2401#define XMTSERV 0x0040 /* Transmit FIFO Service */ 2401#define XMTSERV 0x0040 /* Transmit FIFO Service */
2402#define RCVSERV 0x0080 /* Receive FIFO Service */ 2402#define RCVSERV 0x0080 /* Receive FIFO Service */
2403 2403
2404/* TWIx_FIFO_CTRL Masks */ 2404/* TWIx_FIFO_CTL Masks */
2405#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 2405#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
2406#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 2406#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
2407#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 2407#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 0c346fba9619..bd9adb7183da 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -10,60 +10,60 @@
10#define MAX_BLACKFIN_GPIOS 16 10#define MAX_BLACKFIN_GPIOS 16
11#define BFIN_SPECIAL_GPIO_BANKS 3 11#define BFIN_SPECIAL_GPIO_BANKS 3
12 12
13#define GPIO_PF0 0 /* PF */ 13#define GPIO_PF0 0 /* PF */
14#define GPIO_PF1 1 14#define GPIO_PF1 1
15#define GPIO_PF2 2 15#define GPIO_PF2 2
16#define GPIO_PF3 3 16#define GPIO_PF3 3
17#define GPIO_PF4 4 17#define GPIO_PF4 4
18#define GPIO_PF5 5 18#define GPIO_PF5 5
19#define GPIO_PF6 6 19#define GPIO_PF6 6
20#define GPIO_PF7 7 20#define GPIO_PF7 7
21#define GPIO_PF8 8 21#define GPIO_PF8 8
22#define GPIO_PF9 9 22#define GPIO_PF9 9
23#define GPIO_PF10 10 23#define GPIO_PF10 10
24#define GPIO_PF11 11 24#define GPIO_PF11 11
25#define GPIO_PF12 12 25#define GPIO_PF12 12
26#define GPIO_PF13 13 26#define GPIO_PF13 13
27#define GPIO_PF14 14 27#define GPIO_PF14 14
28#define GPIO_PF15 15 28#define GPIO_PF15 15
29#define GPIO_PC0 16 /* PC */ 29#define GPIO_PC0 16 /* PC */
30#define GPIO_PC1 17 30#define GPIO_PC1 17
31#define GPIO_PC4 20 31#define GPIO_PC4 20
32#define GPIO_PC5 21 32#define GPIO_PC5 21
33#define GPIO_PC6 22 33#define GPIO_PC6 22
34#define GPIO_PC7 23 34#define GPIO_PC7 23
35#define GPIO_PC8 24 35#define GPIO_PC8 24
36#define GPIO_PC9 25 36#define GPIO_PC9 25
37#define GPIO_PD0 32 /* PD */ 37#define GPIO_PD0 32 /* PD */
38#define GPIO_PD1 33 38#define GPIO_PD1 33
39#define GPIO_PD2 34 39#define GPIO_PD2 34
40#define GPIO_PD3 35 40#define GPIO_PD3 35
41#define GPIO_PD4 36 41#define GPIO_PD4 36
42#define GPIO_PD5 37 42#define GPIO_PD5 37
43#define GPIO_PD6 38 43#define GPIO_PD6 38
44#define GPIO_PD7 39 44#define GPIO_PD7 39
45#define GPIO_PD8 40 45#define GPIO_PD8 40
46#define GPIO_PD9 41 46#define GPIO_PD9 41
47#define GPIO_PD10 42 47#define GPIO_PD10 42
48#define GPIO_PD11 43 48#define GPIO_PD11 43
49#define GPIO_PD12 44 49#define GPIO_PD12 44
50#define GPIO_PD13 45 50#define GPIO_PD13 45
51#define GPIO_PE0 48 /* PE */ 51#define GPIO_PE0 48 /* PE */
52#define GPIO_PE1 49 52#define GPIO_PE1 49
53#define GPIO_PE2 50 53#define GPIO_PE2 50
54#define GPIO_PE3 51 54#define GPIO_PE3 51
55#define GPIO_PE4 52 55#define GPIO_PE4 52
56#define GPIO_PE5 53 56#define GPIO_PE5 53
57#define GPIO_PE6 54 57#define GPIO_PE6 54
58#define GPIO_PE7 55 58#define GPIO_PE7 55
59#define GPIO_PE8 56 59#define GPIO_PE8 56
60#define GPIO_PE9 57 60#define GPIO_PE9 57
61#define GPIO_PE10 58 61#define GPIO_PE10 58
62#define GPIO_PE11 59 62#define GPIO_PE11 59
63#define GPIO_PE12 60 63#define GPIO_PE12 60
64#define GPIO_PE13 61 64#define GPIO_PE13 61
65#define GPIO_PE14 62 65#define GPIO_PE14 62
66#define GPIO_PE15 63 66#define GPIO_PE15 63
67 67
68#define PORT_F GPIO_PF0 68#define PORT_F GPIO_PF0
69#define PORT_C GPIO_PC0 69#define PORT_C GPIO_PC0
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
index 0083ba13ee9e..b773c5fdbc72 100644
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf538/include/mach/portmux.h
@@ -108,6 +108,7 @@
108#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) 108#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
109#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) 109#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
110#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) 110#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
111#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
111#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 112#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
112 113
113#endif /* _MACH_PORTMUX_H_ */ 114#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 7d08c7524498..4070079e2c00 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -28,7 +28,7 @@
28#define ANOMALY_05000119 (1) 28#define ANOMALY_05000119 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
31/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ 31/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
32#define ANOMALY_05000220 (1) 32#define ANOMALY_05000220 (1)
33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
34#define ANOMALY_05000245 (1) 34#define ANOMALY_05000245 (1)
@@ -210,10 +210,16 @@
210#define ANOMALY_05000473 (1) 210#define ANOMALY_05000473 (1)
211/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ 211/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
212#define ANOMALY_05000474 (1) 212#define ANOMALY_05000474 (1)
213/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
214#define ANOMALY_05000475 (1)
215/* TESTSET Instruction Cannot Be Interrupted */ 213/* TESTSET Instruction Cannot Be Interrupted */
216#define ANOMALY_05000477 (1) 214#define ANOMALY_05000477 (1)
215/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
216#define ANOMALY_05000481 (1)
217/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
218#define ANOMALY_05000483 (1)
219/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
220#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
221/* IFLUSH sucks at life */
222#define ANOMALY_05000491 (1)
217 223
218/* Anomalies that don't exist on this proc */ 224/* Anomalies that don't exist on this proc */
219#define ANOMALY_05000099 (0) 225#define ANOMALY_05000099 (0)
@@ -229,6 +235,7 @@
229#define ANOMALY_05000198 (0) 235#define ANOMALY_05000198 (0)
230#define ANOMALY_05000202 (0) 236#define ANOMALY_05000202 (0)
231#define ANOMALY_05000215 (0) 237#define ANOMALY_05000215 (0)
238#define ANOMALY_05000219 (0)
232#define ANOMALY_05000227 (0) 239#define ANOMALY_05000227 (0)
233#define ANOMALY_05000230 (0) 240#define ANOMALY_05000230 (0)
234#define ANOMALY_05000231 (0) 241#define ANOMALY_05000231 (0)
@@ -263,5 +270,6 @@
263#define ANOMALY_05000412 (0) 270#define ANOMALY_05000412 (0)
264#define ANOMALY_05000432 (0) 271#define ANOMALY_05000432 (0)
265#define ANOMALY_05000435 (0) 272#define ANOMALY_05000435 (0)
273#define ANOMALY_05000475 (0)
266 274
267#endif 275#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 32f71e6a7c15..ea3ec4ea9e2b 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -301,10 +301,10 @@
301 301
302/* DMAC0 Registers */ 302/* DMAC0 Registers */
303 303
304#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) 304#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
305#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) 305#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
306#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) 306#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
307#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) 307#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
308 308
309/* DMA Channel 0 Registers */ 309/* DMA Channel 0 Registers */
310 310
@@ -1155,10 +1155,10 @@
1155 1155
1156/* DMAC1 Registers */ 1156/* DMAC1 Registers */
1157 1157
1158#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) 1158#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
1159#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) 1159#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
1160#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) 1160#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
1161#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) 1161#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
1162 1162
1163/* DMA Channel 12 Registers */ 1163/* DMA Channel 12 Registers */
1164 1164
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index d3bc6d1df547..abf5f750dd8b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -366,136 +366,6 @@
366 366
367#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 367#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
368 368
369/* Bit masks for SDH_COMMAND */
370
371#define CMD_IDX 0x3f /* Command Index */
372#define CMD_RSP 0x40 /* Response */
373#define CMD_L_RSP 0x80 /* Long Response */
374#define CMD_INT_E 0x100 /* Command Interrupt */
375#define CMD_PEND_E 0x200 /* Command Pending */
376#define CMD_E 0x400 /* Command Enable */
377
378/* Bit masks for SDH_PWR_CTL */
379
380#define PWR_ON 0x3 /* Power On */
381#if 0
382#define TBD 0x3c /* TBD */
383#endif
384#define SD_CMD_OD 0x40 /* Open Drain Output */
385#define ROD_CTL 0x80 /* Rod Control */
386
387/* Bit masks for SDH_CLK_CTL */
388
389#define CLKDIV 0xff /* MC_CLK Divisor */
390#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
391#define PWR_SV_E 0x200 /* Power Save Enable */
392#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
393#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
394
395/* Bit masks for SDH_RESP_CMD */
396
397#define RESP_CMD 0x3f /* Response Command */
398
399/* Bit masks for SDH_DATA_CTL */
400
401#define DTX_E 0x1 /* Data Transfer Enable */
402#define DTX_DIR 0x2 /* Data Transfer Direction */
403#define DTX_MODE 0x4 /* Data Transfer Mode */
404#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
405#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
406
407/* Bit masks for SDH_STATUS */
408
409#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
410#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
411#define CMD_TIME_OUT 0x4 /* CMD Time Out */
412#define DAT_TIME_OUT 0x8 /* Data Time Out */
413#define TX_UNDERRUN 0x10 /* Transmit Underrun */
414#define RX_OVERRUN 0x20 /* Receive Overrun */
415#define CMD_RESP_END 0x40 /* CMD Response End */
416#define CMD_SENT 0x80 /* CMD Sent */
417#define DAT_END 0x100 /* Data End */
418#define START_BIT_ERR 0x200 /* Start Bit Error */
419#define DAT_BLK_END 0x400 /* Data Block End */
420#define CMD_ACT 0x800 /* CMD Active */
421#define TX_ACT 0x1000 /* Transmit Active */
422#define RX_ACT 0x2000 /* Receive Active */
423#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
424#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
425#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
426#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
427#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
428#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
429#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
430#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
431
432/* Bit masks for SDH_STATUS_CLR */
433
434#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
435#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
436#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
437#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
438#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
439#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
440#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
441#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
442#define DAT_END_STAT 0x100 /* Data End Status */
443#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
444#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
445
446/* Bit masks for SDH_MASK0 */
447
448#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
449#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
450#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
451#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
452#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
453#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
454#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
455#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
456#define DAT_END_MASK 0x100 /* Data End Mask */
457#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
458#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
459#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
460#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
461#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
462#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
463#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
464#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
465#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
466#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
467#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
468#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
469#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
470
471/* Bit masks for SDH_FIFO_CNT */
472
473#define FIFO_COUNT 0x7fff /* FIFO Count */
474
475/* Bit masks for SDH_E_STATUS */
476
477#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
478#define SD_CARD_DET 0x10 /* SD Card Detect */
479
480/* Bit masks for SDH_E_MASK */
481
482#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
483#define SCD_MSK 0x40 /* Mask Card Detect */
484
485/* Bit masks for SDH_CFG */
486
487#define CLKS_EN 0x1 /* Clocks Enable */
488#define SD4E 0x4 /* SDIO 4-Bit Enable */
489#define MWE 0x8 /* Moving Window Enable */
490#define SD_RST 0x10 /* SDMMC Reset */
491#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
492#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
493#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
494
495/* Bit masks for SDH_RD_WAIT_EN */
496
497#define RWR 0x1 /* Read Wait Request */
498
499/* Bit masks for ATAPI_CONTROL */ 369/* Bit masks for ATAPI_CONTROL */
500 370
501#define PIO_START 0x1 /* Start PIO/Reg Op */ 371#define PIO_START 0x1 /* Start PIO/Reg Op */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index f916c52a148a..e2771094de02 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -60,15 +60,15 @@
60#define TWI1_REGBASE 0xffc02200 60#define TWI1_REGBASE 0xffc02200
61#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ 61#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
62#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ 62#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
63#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ 63#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
64#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ 64#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
65#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ 65#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
66#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ 66#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
67#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ 67#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
68#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ 68#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
69#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ 69#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
70#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ 70#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
71#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ 71#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
72#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ 72#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
73#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ 73#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
74#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ 74#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 72c343646b2a..be21ba5b3aa8 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
99#define TWI1_REGBASE 0xffc02200 99#define TWI1_REGBASE 0xffc02200
100#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ 100#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
101#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ 101#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
102#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ 102#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
103#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ 103#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
104#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ 104#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
105#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ 105#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
106#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ 106#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
107#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ 107#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
108#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ 108#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
109#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ 109#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
110#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ 110#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
111#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ 111#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
112#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ 112#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
113#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ 113#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
@@ -646,136 +646,6 @@
646 646
647#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 647#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
648 648
649/* Bit masks for SDH_COMMAND */
650
651#define CMD_IDX 0x3f /* Command Index */
652#define CMD_RSP 0x40 /* Response */
653#define CMD_L_RSP 0x80 /* Long Response */
654#define CMD_INT_E 0x100 /* Command Interrupt */
655#define CMD_PEND_E 0x200 /* Command Pending */
656#define CMD_E 0x400 /* Command Enable */
657
658/* Bit masks for SDH_PWR_CTL */
659
660#define PWR_ON 0x3 /* Power On */
661#if 0
662#define TBD 0x3c /* TBD */
663#endif
664#define SD_CMD_OD 0x40 /* Open Drain Output */
665#define ROD_CTL 0x80 /* Rod Control */
666
667/* Bit masks for SDH_CLK_CTL */
668
669#define CLKDIV 0xff /* MC_CLK Divisor */
670#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
671#define PWR_SV_E 0x200 /* Power Save Enable */
672#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
673#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
674
675/* Bit masks for SDH_RESP_CMD */
676
677#define RESP_CMD 0x3f /* Response Command */
678
679/* Bit masks for SDH_DATA_CTL */
680
681#define DTX_E 0x1 /* Data Transfer Enable */
682#define DTX_DIR 0x2 /* Data Transfer Direction */
683#define DTX_MODE 0x4 /* Data Transfer Mode */
684#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
685#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
686
687/* Bit masks for SDH_STATUS */
688
689#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
690#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
691#define CMD_TIME_OUT 0x4 /* CMD Time Out */
692#define DAT_TIME_OUT 0x8 /* Data Time Out */
693#define TX_UNDERRUN 0x10 /* Transmit Underrun */
694#define RX_OVERRUN 0x20 /* Receive Overrun */
695#define CMD_RESP_END 0x40 /* CMD Response End */
696#define CMD_SENT 0x80 /* CMD Sent */
697#define DAT_END 0x100 /* Data End */
698#define START_BIT_ERR 0x200 /* Start Bit Error */
699#define DAT_BLK_END 0x400 /* Data Block End */
700#define CMD_ACT 0x800 /* CMD Active */
701#define TX_ACT 0x1000 /* Transmit Active */
702#define RX_ACT 0x2000 /* Receive Active */
703#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
704#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
705#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
706#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
707#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
708#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
709#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
710#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
711
712/* Bit masks for SDH_STATUS_CLR */
713
714#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
715#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
716#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
717#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
718#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
719#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
720#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
721#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
722#define DAT_END_STAT 0x100 /* Data End Status */
723#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
724#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
725
726/* Bit masks for SDH_MASK0 */
727
728#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
729#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
730#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
731#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
732#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
733#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
734#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
735#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
736#define DAT_END_MASK 0x100 /* Data End Mask */
737#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
738#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
739#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
740#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
741#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
742#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
743#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
744#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
745#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
746#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
747#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
748#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
749#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
750
751/* Bit masks for SDH_FIFO_CNT */
752
753#define FIFO_COUNT 0x7fff /* FIFO Count */
754
755/* Bit masks for SDH_E_STATUS */
756
757#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
758#define SD_CARD_DET 0x10 /* SD Card Detect */
759
760/* Bit masks for SDH_E_MASK */
761
762#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
763#define SCD_MSK 0x40 /* Mask Card Detect */
764
765/* Bit masks for SDH_CFG */
766
767#define CLKS_EN 0x1 /* Clocks Enable */
768#define SD4E 0x4 /* SDIO 4-Bit Enable */
769#define MWE 0x8 /* Moving Window Enable */
770#define SD_RST 0x10 /* SDMMC Reset */
771#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
772#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
773#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
774
775/* Bit masks for SDH_RD_WAIT_EN */
776
777#define RWR 0x1 /* Read Wait Request */
778
779/* Bit masks for ATAPI_CONTROL */ 649/* Bit masks for ATAPI_CONTROL */
780 650
781#define PIO_START 0x1 /* Start PIO/Reg Op */ 651#define PIO_START 0x1 /* Start PIO/Reg Op */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 0ed06c2366fe..95ff44601fd1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -105,15 +105,15 @@
105#define TWI0_REGBASE 0xffc00700 105#define TWI0_REGBASE 0xffc00700
106#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ 106#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
107#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ 107#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
108#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ 108#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
109#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ 109#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
110#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ 110#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
111#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ 111#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
112#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ 112#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
113#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ 113#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
114#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ 114#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
115#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ 115#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
116#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ 116#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
117#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ 117#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
118#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ 118#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
119#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ 119#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
@@ -198,8 +198,8 @@
198 198
199/* DMAC0 Registers */ 199/* DMAC0 Registers */
200 200
201#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ 201#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
202#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ 202#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
203 203
204/* DMA Channel 0 Registers */ 204/* DMA Channel 0 Registers */
205 205
@@ -688,8 +688,8 @@
688 688
689/* DMAC1 Registers */ 689/* DMAC1 Registers */
690 690
691#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ 691#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
692#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ 692#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
693 693
694/* DMA Channel 12 Registers */ 694/* DMA Channel 12 Registers */
695 695
@@ -1958,57 +1958,6 @@
1958#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 1958#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1959#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 1959#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1960 1960
1961/* Bit masks for CNT_CONFIG */
1962
1963#define CNTE 0x1 /* Counter Enable */
1964#define DEBE 0x2 /* Debounce Enable */
1965#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1966#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1967#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1968#define CNTMODE 0x700 /* Counter Operating Mode */
1969#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1970#define BNDMODE 0x3000 /* Boundary register Mode */
1971#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1972
1973/* Bit masks for CNT_IMASK */
1974
1975#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1976#define UCIE 0x2 /* Up count Interrupt Enable */
1977#define DCIE 0x4 /* Down count Interrupt Enable */
1978#define MINCIE 0x8 /* Min Count Interrupt Enable */
1979#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1980#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1981#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1982#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1983#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1984#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1985#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1986
1987/* Bit masks for CNT_STATUS */
1988
1989#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1990#define UCII 0x2 /* Up count Interrupt Identifier */
1991#define DCII 0x4 /* Down count Interrupt Identifier */
1992#define MINCII 0x8 /* Min Count Interrupt Identifier */
1993#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1994#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1995#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1996#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1997#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1998#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1999#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
2000
2001/* Bit masks for CNT_COMMAND */
2002
2003#define W1LCNT 0xf /* Load Counter Register */
2004#define W1LMIN 0xf0 /* Load Min Register */
2005#define W1LMAX 0xf00 /* Load Max Register */
2006#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
2007
2008/* Bit masks for CNT_DEBOUNCE */
2009
2010#define DPRESCALE 0xf /* Load Counter Register */
2011
2012/* Bit masks for SECURE_SYSSWT */ 1961/* Bit masks for SECURE_SYSSWT */
2013 1962
2014#define EMUDABL 0x1 /* Emulation Disable. */ 1963#define EMUDABL 0x1 /* Emulation Disable. */
@@ -2044,66 +1993,6 @@
2044#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 1993#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2045#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1994#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2046 1995
2047/* Bit masks for NFC_CTL */
2048
2049#define WR_DLY 0xf /* Write Strobe Delay */
2050#define RD_DLY 0xf0 /* Read Strobe Delay */
2051#define NWIDTH 0x100 /* NAND Data Width */
2052#define PG_SIZE 0x200 /* Page Size */
2053
2054/* Bit masks for NFC_STAT */
2055
2056#define NBUSY 0x1 /* Not Busy */
2057#define WB_FULL 0x2 /* Write Buffer Full */
2058#define PG_WR_STAT 0x4 /* Page Write Pending */
2059#define PG_RD_STAT 0x8 /* Page Read Pending */
2060#define WB_EMPTY 0x10 /* Write Buffer Empty */
2061
2062/* Bit masks for NFC_IRQSTAT */
2063
2064#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2065#define WB_OVF 0x2 /* Write Buffer Overflow */
2066#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2067#define RD_RDY 0x8 /* Read Data Ready */
2068#define WR_DONE 0x10 /* Page Write Done */
2069
2070/* Bit masks for NFC_IRQMASK */
2071
2072#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2073#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2074#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2075#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2076#define MASK_WRDONE 0x10 /* Mask Write Done */
2077
2078/* Bit masks for NFC_RST */
2079
2080#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2081
2082/* Bit masks for NFC_PGCTL */
2083
2084#define PG_RD_START 0x1 /* Page Read Start */
2085#define PG_WR_START 0x2 /* Page Write Start */
2086
2087/* Bit masks for NFC_ECC0 */
2088
2089#define ECC0 0x7ff /* Parity Calculation Result0 */
2090
2091/* Bit masks for NFC_ECC1 */
2092
2093#define ECC1 0x7ff /* Parity Calculation Result1 */
2094
2095/* Bit masks for NFC_ECC2 */
2096
2097#define ECC2 0x7ff /* Parity Calculation Result2 */
2098
2099/* Bit masks for NFC_ECC3 */
2100
2101#define ECC3 0x7ff /* Parity Calculation Result3 */
2102
2103/* Bit masks for NFC_COUNT */
2104
2105#define ECCCNT 0x3ff /* Transfer Count */
2106
2107/* Bit masks for EPPIx_STATUS */ 1996/* Bit masks for EPPIx_STATUS */
2108 1997
2109#define CFIFO_ERR 0x1 /* Chroma FIFO Error */ 1998#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
@@ -2472,33 +2361,6 @@
2472#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ 2361#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
2473#define BCODE_NOBOOT 0x0030 /* always perform full boot */ 2362#define BCODE_NOBOOT 0x0030 /* always perform full boot */
2474 2363
2475/* CNT_COMMAND bit field options */
2476
2477#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
2478#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
2479#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
2480
2481#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
2482#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
2483#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
2484
2485#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
2486#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
2487#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
2488
2489/* CNT_CONFIG bit field options */
2490
2491#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
2492#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
2493#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
2494#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
2495#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
2496
2497#define BNDMODE_COMP 0x0000 /* boundary compare mode */
2498#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
2499#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
2500#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
2501
2502/* TMODE in TIMERx_CONFIG bit field options */ 2364/* TMODE in TIMERx_CONFIG bit field options */
2503 2365
2504#define PWM_OUT 0x0001 2366#define PWM_OUT 0x0001
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 850e39d193e3..28037e331964 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -3,6 +3,10 @@
3 * Licensed under the GPL-2 or later. 3 * Licensed under the GPL-2 or later.
4 */ 4 */
5 5
6
7#ifndef _MACH_GPIO_H_
8#define _MACH_GPIO_H_
9
6#define GPIO_PA0 0 10#define GPIO_PA0 0
7#define GPIO_PA1 1 11#define GPIO_PA1 1
8#define GPIO_PA2 2 12#define GPIO_PA2 2
@@ -166,6 +170,8 @@
166 170
167#define MAX_BLACKFIN_GPIOS 160 171#define MAX_BLACKFIN_GPIOS 160
168 172
173#ifndef __ASSEMBLY__
174
169struct gpio_port_t { 175struct gpio_port_t {
170 unsigned short port_fer; 176 unsigned short port_fer;
171 unsigned short dummy1; 177 unsigned short dummy1;
@@ -191,3 +197,7 @@ struct gpio_port_s {
191 unsigned short inen; 197 unsigned short inen;
192 unsigned int mux; 198 unsigned int mux;
193}; 199};
200
201#endif
202
203#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
index 89ad6a886362..e22246202730 100644
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf548/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11 11
12#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 12#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
13#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 13#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
@@ -131,6 +131,7 @@
131#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) 131#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
132#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) 132#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
133 133
134#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
134#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 135#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
135#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) 136#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
136#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) 137#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 5ddc981e9937..4c108c99cb6e 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -152,8 +152,8 @@
152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) 152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
153/* NMI Event at Boot Time Results in Unpredictable State */ 153/* NMI Event at Boot Time Results in Unpredictable State */
154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) 154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
155/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ 155/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
156#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) 156#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
157/* Incorrect Pulse-Width of UART Start Bit */ 157/* Incorrect Pulse-Width of UART Start Bit */
158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) 158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
159/* Scratchpad Memory Bank Reads May Return Incorrect Data */ 159/* Scratchpad Memory Bank Reads May Return Incorrect Data */
@@ -290,10 +290,14 @@
290#define ANOMALY_05000461 (1) 290#define ANOMALY_05000461 (1)
291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
292#define ANOMALY_05000473 (1) 292#define ANOMALY_05000473 (1)
293/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ 293/* Possible Lockup Condition whem Modifying PLL from External Memory */
294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) 294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
295/* TESTSET Instruction Cannot Be Interrupted */ 295/* TESTSET Instruction Cannot Be Interrupted */
296#define ANOMALY_05000477 (1) 296#define ANOMALY_05000477 (1)
297/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
298#define ANOMALY_05000481 (1)
299/* IFLUSH sucks at life */
300#define ANOMALY_05000491 (1)
297 301
298/* Anomalies that don't exist on this proc */ 302/* Anomalies that don't exist on this proc */
299#define ANOMALY_05000119 (0) 303#define ANOMALY_05000119 (0)
@@ -319,5 +323,6 @@
319#define ANOMALY_05000465 (0) 323#define ANOMALY_05000465 (0)
320#define ANOMALY_05000467 (0) 324#define ANOMALY_05000467 (0)
321#define ANOMALY_05000474 (0) 325#define ANOMALY_05000474 (0)
326#define ANOMALY_05000485 (0)
322 327
323#endif 328#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index a651a8cf805f..4f8aa5d08802 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -9,54 +9,54 @@
9 9
10#define MAX_BLACKFIN_GPIOS 48 10#define MAX_BLACKFIN_GPIOS 48
11 11
12#define GPIO_PF0 0 12#define GPIO_PF0 0
13#define GPIO_PF1 1 13#define GPIO_PF1 1
14#define GPIO_PF2 2 14#define GPIO_PF2 2
15#define GPIO_PF3 3 15#define GPIO_PF3 3
16#define GPIO_PF4 4 16#define GPIO_PF4 4
17#define GPIO_PF5 5 17#define GPIO_PF5 5
18#define GPIO_PF6 6 18#define GPIO_PF6 6
19#define GPIO_PF7 7 19#define GPIO_PF7 7
20#define GPIO_PF8 8 20#define GPIO_PF8 8
21#define GPIO_PF9 9 21#define GPIO_PF9 9
22#define GPIO_PF10 10 22#define GPIO_PF10 10
23#define GPIO_PF11 11 23#define GPIO_PF11 11
24#define GPIO_PF12 12 24#define GPIO_PF12 12
25#define GPIO_PF13 13 25#define GPIO_PF13 13
26#define GPIO_PF14 14 26#define GPIO_PF14 14
27#define GPIO_PF15 15 27#define GPIO_PF15 15
28#define GPIO_PF16 16 28#define GPIO_PF16 16
29#define GPIO_PF17 17 29#define GPIO_PF17 17
30#define GPIO_PF18 18 30#define GPIO_PF18 18
31#define GPIO_PF19 19 31#define GPIO_PF19 19
32#define GPIO_PF20 20 32#define GPIO_PF20 20
33#define GPIO_PF21 21 33#define GPIO_PF21 21
34#define GPIO_PF22 22 34#define GPIO_PF22 22
35#define GPIO_PF23 23 35#define GPIO_PF23 23
36#define GPIO_PF24 24 36#define GPIO_PF24 24
37#define GPIO_PF25 25 37#define GPIO_PF25 25
38#define GPIO_PF26 26 38#define GPIO_PF26 26
39#define GPIO_PF27 27 39#define GPIO_PF27 27
40#define GPIO_PF28 28 40#define GPIO_PF28 28
41#define GPIO_PF29 29 41#define GPIO_PF29 29
42#define GPIO_PF30 30 42#define GPIO_PF30 30
43#define GPIO_PF31 31 43#define GPIO_PF31 31
44#define GPIO_PF32 32 44#define GPIO_PF32 32
45#define GPIO_PF33 33 45#define GPIO_PF33 33
46#define GPIO_PF34 34 46#define GPIO_PF34 34
47#define GPIO_PF35 35 47#define GPIO_PF35 35
48#define GPIO_PF36 36 48#define GPIO_PF36 36
49#define GPIO_PF37 37 49#define GPIO_PF37 37
50#define GPIO_PF38 38 50#define GPIO_PF38 38
51#define GPIO_PF39 39 51#define GPIO_PF39 39
52#define GPIO_PF40 40 52#define GPIO_PF40 40
53#define GPIO_PF41 41 53#define GPIO_PF41 41
54#define GPIO_PF42 42 54#define GPIO_PF42 42
55#define GPIO_PF43 43 55#define GPIO_PF43 43
56#define GPIO_PF44 44 56#define GPIO_PF44 44
57#define GPIO_PF45 45 57#define GPIO_PF45 45
58#define GPIO_PF46 46 58#define GPIO_PF46 46
59#define GPIO_PF47 47 59#define GPIO_PF47 47
60 60
61#define PORT_FIO0 GPIO_0 61#define PORT_FIO0 GPIO_0
62#define PORT_FIO1 GPIO_16 62#define PORT_FIO1 GPIO_16
diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h
index 3a7b46bbe849..2339ffd0dde8 100644
--- a/arch/blackfin/mach-bf561/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf561/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11 11
12#define P_PPI0_CLK (P_DONTCARE) 12#define P_PPI0_CLK (P_DONTCARE)
13#define P_PPI0_FS1 (P_DONTCARE) 13#define P_PPI0_FS1 (P_DONTCARE)
@@ -91,6 +91,7 @@
91#define P_SPI0_MOSI (P_DONTCARE) 91#define P_SPI0_MOSI (P_DONTCARE)
92#define P_SPI0_MISO (P_DONTCARE) 92#define P_SPI0_MISO (P_DONTCARE)
93#define P_SPI0_SCK (P_DONTCARE) 93#define P_SPI0_SCK (P_DONTCARE)
94#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
94#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 95#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
95 96
96#endif /* _MACH_PORTMUX_H_ */ 97#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index f2ca211a76a0..bceb98126c21 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Do some checking to make sure things are OK 2 * Do some checking to make sure things are OK
3 * 3 *
4 * Copyright 2007-2009 Analog Devices Inc. 4 * Copyright 2007-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -47,18 +47,20 @@
47# error "The kernel load address is too high; keep it below 10meg for safety" 47# error "The kernel load address is too high; keep it below 10meg for safety"
48#endif 48#endif
49 49
50#if ANOMALY_05000263 && defined(CONFIG_MPU)
51# error the MPU will not function safely while Anomaly 05000263 applies
52#endif
53
50#if ANOMALY_05000448 54#if ANOMALY_05000448
51# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. 55# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
52#endif 56#endif
53 57
54/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ 58/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
55#if ANOMALY_05000220 && \ 59#if ANOMALY_05000220 && \
56 ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ 60 (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
57 (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) 61# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
58# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
59#endif 62#endif
60 63
61#if ANOMALY_05000475 && \ 64#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1)
62 (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) 65# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
63# error "Anomaly 475 does not allow you to use Write Back cache with L2 or External Memory"
64#endif 66#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index ea540318a228..790c767ca95a 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -11,7 +11,11 @@
11#include <asm/cache.h> 11#include <asm/cache.h>
12#include <asm/page.h> 12#include <asm/page.h>
13 13
14#ifdef CONFIG_CACHE_FLUSH_L1
15.section .l1.text
16#else
14.text 17.text
18#endif
15 19
16/* 05000443 - IFLUSH cannot be last instruction in hardware loop */ 20/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
17#if ANOMALY_05000443 21#if ANOMALY_05000443
@@ -64,17 +68,6 @@
64 68
65/* Invalidate all instruction cache lines assocoiated with this memory area */ 69/* Invalidate all instruction cache lines assocoiated with this memory area */
66ENTRY(_blackfin_icache_flush_range) 70ENTRY(_blackfin_icache_flush_range)
67/*
68 * Walkaround to avoid loading wrong instruction after invalidating icache
69 * and following sequence is met.
70 *
71 * 1) One instruction address is cached in the instruction cache.
72 * 2) This instruction in SDRAM is changed.
73 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
74 * 4) This instruction is executed again, but the old one is loaded.
75 */
76 P0 = R0;
77 IFLUSH[P0];
78 do_flush IFLUSH 71 do_flush IFLUSH
79ENDPROC(_blackfin_icache_flush_range) 72ENDPROC(_blackfin_icache_flush_range)
80 73
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index b03716896051..5969d86836a5 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -17,9 +17,6 @@ ENTRY(_sleep_mode)
17 17
18 call _set_sic_iwr; 18 call _set_sic_iwr;
19 19
20 R0 = 0xFFFF (Z);
21 call _set_rtc_istat;
22
23 P0.H = hi(PLL_CTL); 20 P0.H = hi(PLL_CTL);
24 P0.L = lo(PLL_CTL); 21 P0.L = lo(PLL_CTL);
25 R1 = W[P0](z); 22 R1 = W[P0](z);
@@ -65,9 +62,6 @@ ENTRY(_hibernate_mode)
65 call _set_dram_srfs; 62 call _set_dram_srfs;
66 SSYNC; 63 SSYNC;
67 64
68 R0 = 0xFFFF (Z);
69 call _set_rtc_istat;
70
71 P0.H = hi(VR_CTL); 65 P0.H = hi(VR_CTL);
72 P0.L = lo(VR_CTL); 66 P0.L = lo(VR_CTL);
73 67
@@ -95,9 +89,6 @@ ENTRY(_sleep_deeper)
95 call _set_sic_iwr; 89 call _set_sic_iwr;
96 call _set_dram_srfs; /* Set SDRAM Self Refresh */ 90 call _set_dram_srfs; /* Set SDRAM Self Refresh */
97 91
98 /* Clear all the interrupts,bits sticky */
99 R0 = 0xFFFF (Z);
100 call _set_rtc_istat;
101 P0.H = hi(PLL_DIV); 92 P0.H = hi(PLL_DIV);
102 P0.L = lo(PLL_DIV); 93 P0.L = lo(PLL_DIV);
103 R6 = W[P0](z); 94 R6 = W[P0](z);
@@ -269,21 +260,6 @@ ENTRY(_set_sic_iwr)
269 RTS; 260 RTS;
270ENDPROC(_set_sic_iwr) 261ENDPROC(_set_sic_iwr)
271 262
272ENTRY(_set_rtc_istat)
273#ifndef CONFIG_BF561
274 P0.H = hi(RTC_ISTAT);
275 P0.L = lo(RTC_ISTAT);
276 w[P0] = R0.L;
277 SSYNC;
278#elif (ANOMALY_05000371)
279 nop;
280 nop;
281 nop;
282 nop;
283#endif
284 RTS;
285ENDPROC(_set_rtc_istat)
286
287ENTRY(_test_pll_locked) 263ENTRY(_test_pll_locked)
288 P0.H = hi(PLL_STAT); 264 P0.H = hi(PLL_STAT);
289 P0.L = lo(PLL_STAT); 265 P0.L = lo(PLL_STAT);
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index ea7f95f6bb4c..09c1fb410748 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -61,10 +61,11 @@ void bfin_pm_suspend_standby_enter(void)
61 61
62int bf53x_suspend_l1_mem(unsigned char *memptr) 62int bf53x_suspend_l1_mem(unsigned char *memptr)
63{ 63{
64 dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH); 64 dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
65 dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START, 65 L1_CODE_LENGTH);
66 L1_DATA_A_LENGTH); 66 dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
67 dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, 67 (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
68 dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
68 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH); 69 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
69 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + 70 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
70 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START, 71 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
@@ -75,10 +76,10 @@ int bf53x_suspend_l1_mem(unsigned char *memptr)
75 76
76int bf53x_resume_l1_mem(unsigned char *memptr) 77int bf53x_resume_l1_mem(unsigned char *memptr)
77{ 78{
78 dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); 79 dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
79 dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, 80 dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
80 L1_DATA_A_LENGTH); 81 L1_DATA_A_LENGTH);
81 dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + 82 dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
82 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH); 83 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
83 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH + 84 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
84 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH); 85 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
@@ -167,7 +168,7 @@ int bfin_pm_suspend_mem_enter(void)
167 _disable_icplb(); 168 _disable_icplb();
168 bf53x_suspend_l1_mem(memptr); 169 bf53x_suspend_l1_mem(memptr);
169 170
170 do_hibernate(wakeup | vr_wakeup); /* Goodbye */ 171 do_hibernate(wakeup | vr_wakeup); /* See you later! */
171 172
172 bf53x_resume_l1_mem(memptr); 173 bf53x_resume_l1_mem(memptr);
173 174
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 22:04:47 -0500