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authorChris Metcalf <cmetcalf@tilera.com>2011-05-04 14:38:26 -0400
committerChris Metcalf <cmetcalf@tilera.com>2011-05-12 15:52:12 -0400
commit18aecc2b645bbb07851b196452a2af314222069b (patch)
tree959f765f69af01046c6e26db12b45c3390799d3e /arch
parentbe84cb43833ee40a42e08f5425d20310f16229c7 (diff)
arch/tile: finish enabling support for TILE-Gx 64-bit chip
This support was partially present in the existing code (look for "__tilegx__" ifdefs) but with this change you can build a working kernel using the TILE-Gx toolchain and ARCH=tilegx. Most of these files are new, generally adding a foo_64.c file where previously there was just a foo_32.c file. The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx, using the existing SRCARCH mechanism in the top-level Makefile. Changes to existing files: - <asm/bitops.h> and <asm/bitops_32.h> changed to factor the include of <asm-generic/bitops/non-atomic.h> in the common header. - <asm/compat.h> and arch/tile/kernel/compat.c changed to remove the "const" markers I had put on compat_sys_execve() when trying to match some recent similar changes to the non-compat execve. It turns out the compat version wasn't "upgraded" to use const. - <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were previously included accidentally, with the 32-bit contents. Now they have the proper 64-bit contents. Finally, I had to hack the existing hacky drivers/input/input-compat.h to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64). Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
Diffstat (limited to 'arch')
-rw-r--r--arch/tile/configs/tilegx_defconfig1776
-rw-r--r--arch/tile/include/arch/chip_tilegx.h258
-rw-r--r--arch/tile/include/arch/interrupts_64.h276
-rw-r--r--arch/tile/include/arch/spr_def_64.h173
-rw-r--r--arch/tile/include/asm/atomic_64.h169
-rw-r--r--arch/tile/include/asm/bitops.h1
-rw-r--r--arch/tile/include/asm/bitops_32.h1
-rw-r--r--arch/tile/include/asm/bitops_64.h105
-rw-r--r--arch/tile/include/asm/compat.h4
-rw-r--r--arch/tile/include/asm/opcode-tile_64.h1507
-rw-r--r--arch/tile/include/asm/opcode_constants_64.h1043
-rw-r--r--arch/tile/include/asm/pgtable_64.h175
-rw-r--r--arch/tile/include/asm/spinlock_64.h161
-rw-r--r--arch/tile/kernel/futex_64.S55
-rw-r--r--arch/tile/kernel/head_64.S269
-rw-r--r--arch/tile/kernel/intvec_64.S1231
-rw-r--r--arch/tile/kernel/process.c4
-rw-r--r--arch/tile/kernel/regs_64.S145
-rw-r--r--arch/tile/kernel/tile-desc_64.c2200
-rw-r--r--arch/tile/lib/memchr_64.c71
-rw-r--r--arch/tile/lib/memcpy_64.c220
-rw-r--r--arch/tile/lib/memcpy_user_64.c86
-rw-r--r--arch/tile/lib/memset_64.c145
-rw-r--r--arch/tile/lib/spinlock_64.c104
-rw-r--r--arch/tile/lib/strchr_64.c67
-rw-r--r--arch/tile/lib/strlen_64.c38
-rw-r--r--arch/tile/lib/usercopy_64.S196
-rw-r--r--arch/tile/mm/migrate_64.S187
28 files changed, 9319 insertions, 1348 deletions
diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig
new file mode 100644
index 000000000000..776ec0c5cba8
--- /dev/null
+++ b/arch/tile/configs/tilegx_defconfig
@@ -0,0 +1,1776 @@
1#
2# Automatically generated make config: don't edit
3# Linux/tilegx 2.6.39-rc5 Kernel Configuration
4# Wed May 4 11:08:04 2011
5#
6CONFIG_TILE=y
7CONFIG_MMU=y
8CONFIG_GENERIC_CSUM=y
9CONFIG_SEMAPHORE_SLEEPERS=y
10CONFIG_HAVE_ARCH_ALLOC_REMAP=y
11CONFIG_HAVE_SETUP_PER_CPU_AREA=y
12CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
13CONFIG_SYS_SUPPORTS_HUGETLBFS=y
14CONFIG_GENERIC_TIME=y
15CONFIG_GENERIC_CLOCKEVENTS=y
16CONFIG_RWSEM_GENERIC_SPINLOCK=y
17CONFIG_DEFAULT_MIGRATION_COST=10000000
18CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
19CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
20CONFIG_ARCH_DMA_ADDR_T_64BIT=y
21CONFIG_LOCKDEP_SUPPORT=y
22CONFIG_STACKTRACE_SUPPORT=y
23CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
24CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
25CONFIG_TRACE_IRQFLAGS_SUPPORT=y
26CONFIG_STRICT_DEVMEM=y
27CONFIG_SMP=y
28# CONFIG_DEBUG_COPY_FROM_USER is not set
29CONFIG_HVC_TILE=y
30CONFIG_TILEGX=y
31CONFIG_64BIT=y
32CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tilegx_defconfig"
33CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
34CONFIG_CONSTRUCTORS=y
35
36#
37# General setup
38#
39CONFIG_EXPERIMENTAL=y
40CONFIG_INIT_ENV_ARG_LIMIT=32
41CONFIG_CROSS_COMPILE=""
42CONFIG_LOCALVERSION=""
43# CONFIG_LOCALVERSION_AUTO is not set
44CONFIG_SWAP=y
45CONFIG_SYSVIPC=y
46CONFIG_SYSVIPC_SYSCTL=y
47CONFIG_POSIX_MQUEUE=y
48CONFIG_POSIX_MQUEUE_SYSCTL=y
49CONFIG_BSD_PROCESS_ACCT=y
50CONFIG_BSD_PROCESS_ACCT_V3=y
51# CONFIG_FHANDLE is not set
52CONFIG_TASKSTATS=y
53CONFIG_TASK_DELAY_ACCT=y
54CONFIG_TASK_XACCT=y
55CONFIG_TASK_IO_ACCOUNTING=y
56CONFIG_AUDIT=y
57CONFIG_HAVE_GENERIC_HARDIRQS=y
58
59#
60# IRQ subsystem
61#
62CONFIG_GENERIC_HARDIRQS=y
63CONFIG_GENERIC_IRQ_PROBE=y
64CONFIG_GENERIC_IRQ_SHOW=y
65CONFIG_GENERIC_PENDING_IRQ=y
66
67#
68# RCU Subsystem
69#
70CONFIG_TREE_RCU=y
71# CONFIG_PREEMPT_RCU is not set
72# CONFIG_RCU_TRACE is not set
73CONFIG_RCU_FANOUT=64
74# CONFIG_RCU_FANOUT_EXACT is not set
75# CONFIG_RCU_FAST_NO_HZ is not set
76# CONFIG_TREE_RCU_TRACE is not set
77# CONFIG_IKCONFIG is not set
78CONFIG_LOG_BUF_SHIFT=19
79CONFIG_CGROUPS=y
80CONFIG_CGROUP_DEBUG=y
81CONFIG_CGROUP_NS=y
82# CONFIG_CGROUP_FREEZER is not set
83CONFIG_CGROUP_DEVICE=y
84CONFIG_CPUSETS=y
85CONFIG_PROC_PID_CPUSET=y
86CONFIG_CGROUP_CPUACCT=y
87CONFIG_RESOURCE_COUNTERS=y
88CONFIG_CGROUP_MEM_RES_CTLR=y
89CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
90CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED=y
91CONFIG_CGROUP_SCHED=y
92CONFIG_FAIR_GROUP_SCHED=y
93CONFIG_RT_GROUP_SCHED=y
94CONFIG_BLK_CGROUP=y
95# CONFIG_DEBUG_BLK_CGROUP is not set
96CONFIG_NAMESPACES=y
97CONFIG_UTS_NS=y
98CONFIG_IPC_NS=y
99CONFIG_USER_NS=y
100CONFIG_PID_NS=y
101CONFIG_NET_NS=y
102# CONFIG_SCHED_AUTOGROUP is not set
103CONFIG_MM_OWNER=y
104# CONFIG_SYSFS_DEPRECATED is not set
105CONFIG_RELAY=y
106CONFIG_BLK_DEV_INITRD=y
107CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
108CONFIG_INITRAMFS_ROOT_UID=0
109CONFIG_INITRAMFS_ROOT_GID=0
110CONFIG_RD_GZIP=y
111# CONFIG_RD_BZIP2 is not set
112# CONFIG_RD_LZMA is not set
113# CONFIG_RD_XZ is not set
114# CONFIG_RD_LZO is not set
115CONFIG_INITRAMFS_COMPRESSION_NONE=y
116# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
117CONFIG_CC_OPTIMIZE_FOR_SIZE=y
118CONFIG_SYSCTL=y
119CONFIG_ANON_INODES=y
120CONFIG_EXPERT=y
121CONFIG_SYSCTL_SYSCALL=y
122CONFIG_KALLSYMS=y
123# CONFIG_KALLSYMS_ALL is not set
124# CONFIG_KALLSYMS_EXTRA_PASS is not set
125CONFIG_HOTPLUG=y
126CONFIG_PRINTK=y
127CONFIG_BUG=y
128CONFIG_ELF_CORE=y
129CONFIG_BASE_FULL=y
130CONFIG_FUTEX=y
131CONFIG_EPOLL=y
132CONFIG_SIGNALFD=y
133CONFIG_TIMERFD=y
134CONFIG_EVENTFD=y
135CONFIG_SHMEM=y
136CONFIG_AIO=y
137CONFIG_EMBEDDED=y
138
139#
140# Kernel Performance Events And Counters
141#
142CONFIG_VM_EVENT_COUNTERS=y
143CONFIG_PCI_QUIRKS=y
144CONFIG_SLUB_DEBUG=y
145# CONFIG_COMPAT_BRK is not set
146# CONFIG_SLAB is not set
147CONFIG_SLUB=y
148# CONFIG_SLOB is not set
149CONFIG_PROFILING=y
150CONFIG_USE_GENERIC_SMP_HELPERS=y
151
152#
153# GCOV-based kernel profiling
154#
155# CONFIG_GCOV_KERNEL is not set
156# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
157CONFIG_SLABINFO=y
158CONFIG_RT_MUTEXES=y
159CONFIG_BASE_SMALL=0
160CONFIG_MODULES=y
161CONFIG_MODULE_FORCE_LOAD=y
162CONFIG_MODULE_UNLOAD=y
163# CONFIG_MODULE_FORCE_UNLOAD is not set
164# CONFIG_MODVERSIONS is not set
165# CONFIG_MODULE_SRCVERSION_ALL is not set
166CONFIG_STOP_MACHINE=y
167CONFIG_BLOCK=y
168CONFIG_BLK_DEV_BSG=y
169CONFIG_BLK_DEV_INTEGRITY=y
170# CONFIG_BLK_DEV_THROTTLING is not set
171CONFIG_BLOCK_COMPAT=y
172
173#
174# IO Schedulers
175#
176CONFIG_IOSCHED_NOOP=y
177CONFIG_IOSCHED_DEADLINE=y
178CONFIG_IOSCHED_CFQ=y
179CONFIG_CFQ_GROUP_IOSCHED=y
180# CONFIG_DEFAULT_DEADLINE is not set
181CONFIG_DEFAULT_CFQ=y
182# CONFIG_DEFAULT_NOOP is not set
183CONFIG_DEFAULT_IOSCHED="cfq"
184CONFIG_PADATA=y
185# CONFIG_INLINE_SPIN_TRYLOCK is not set
186# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
187# CONFIG_INLINE_SPIN_LOCK is not set
188# CONFIG_INLINE_SPIN_LOCK_BH is not set
189# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
190# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
191CONFIG_INLINE_SPIN_UNLOCK=y
192# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
193CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
194# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
195# CONFIG_INLINE_READ_TRYLOCK is not set
196# CONFIG_INLINE_READ_LOCK is not set
197# CONFIG_INLINE_READ_LOCK_BH is not set
198# CONFIG_INLINE_READ_LOCK_IRQ is not set
199# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
200CONFIG_INLINE_READ_UNLOCK=y
201# CONFIG_INLINE_READ_UNLOCK_BH is not set
202CONFIG_INLINE_READ_UNLOCK_IRQ=y
203# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
204# CONFIG_INLINE_WRITE_TRYLOCK is not set
205# CONFIG_INLINE_WRITE_LOCK is not set
206# CONFIG_INLINE_WRITE_LOCK_BH is not set
207# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
208# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
209CONFIG_INLINE_WRITE_UNLOCK=y
210# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
211CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
212# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
213CONFIG_MUTEX_SPIN_ON_OWNER=y
214
215#
216# Tilera-specific configuration
217#
218CONFIG_NR_CPUS=100
219CONFIG_TICK_ONESHOT=y
220CONFIG_NO_HZ=y
221CONFIG_HIGH_RES_TIMERS=y
222CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
223CONFIG_HZ_100=y
224# CONFIG_HZ_250 is not set
225# CONFIG_HZ_300 is not set
226# CONFIG_HZ_1000 is not set
227CONFIG_HZ=100
228CONFIG_SCHED_HRTICK=y
229# CONFIG_KEXEC is not set
230CONFIG_COMPAT=y
231CONFIG_SYSVIPC_COMPAT=y
232# CONFIG_HIGHMEM is not set
233CONFIG_NUMA=y
234CONFIG_NODES_SHIFT=2
235CONFIG_PAGE_OFFSET=0xC0000000
236CONFIG_SELECT_MEMORY_MODEL=y
237CONFIG_DISCONTIGMEM_MANUAL=y
238CONFIG_DISCONTIGMEM=y
239CONFIG_FLAT_NODE_MEM_MAP=y
240CONFIG_NEED_MULTIPLE_NODES=y
241CONFIG_PAGEFLAGS_EXTENDED=y
242CONFIG_SPLIT_PTLOCK_CPUS=4
243# CONFIG_COMPACTION is not set
244CONFIG_MIGRATION=y
245CONFIG_PHYS_ADDR_T_64BIT=y
246CONFIG_ZONE_DMA_FLAG=0
247CONFIG_VIRT_TO_BUS=y
248# CONFIG_KSM is not set
249CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
250# CONFIG_CMDLINE_BOOL is not set
251CONFIG_VMALLOC_RESERVE=0x1000000
252CONFIG_HARDWALL=y
253CONFIG_KERNEL_PL=1
254
255#
256# Bus options
257#
258CONFIG_PCI=y
259CONFIG_PCI_DOMAINS=y
260# CONFIG_NO_IOMEM is not set
261# CONFIG_NO_IOPORT is not set
262# CONFIG_ARCH_SUPPORTS_MSI is not set
263CONFIG_PCI_DEBUG=y
264# CONFIG_PCI_STUB is not set
265# CONFIG_PCI_IOV is not set
266# CONFIG_HOTPLUG_PCI is not set
267
268#
269# Executable file formats
270#
271CONFIG_KCORE_ELF=y
272CONFIG_BINFMT_ELF=y
273CONFIG_COMPAT_BINFMT_ELF=y
274# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
275# CONFIG_HAVE_AOUT is not set
276CONFIG_BINFMT_MISC=y
277CONFIG_NET=y
278
279#
280# Networking options
281#
282CONFIG_PACKET=y
283CONFIG_UNIX=y
284CONFIG_XFRM=y
285CONFIG_XFRM_USER=y
286CONFIG_XFRM_SUB_POLICY=y
287CONFIG_XFRM_MIGRATE=y
288CONFIG_XFRM_STATISTICS=y
289CONFIG_XFRM_IPCOMP=m
290CONFIG_NET_KEY=m
291CONFIG_NET_KEY_MIGRATE=y
292CONFIG_INET=y
293CONFIG_IP_MULTICAST=y
294CONFIG_IP_ADVANCED_ROUTER=y
295# CONFIG_IP_FIB_TRIE_STATS is not set
296CONFIG_IP_MULTIPLE_TABLES=y
297CONFIG_IP_ROUTE_MULTIPATH=y
298CONFIG_IP_ROUTE_VERBOSE=y
299CONFIG_IP_ROUTE_CLASSID=y
300# CONFIG_IP_PNP is not set
301CONFIG_NET_IPIP=m
302# CONFIG_NET_IPGRE_DEMUX is not set
303CONFIG_IP_MROUTE=y
304# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
305CONFIG_IP_PIMSM_V1=y
306CONFIG_IP_PIMSM_V2=y
307# CONFIG_ARPD is not set
308CONFIG_SYN_COOKIES=y
309CONFIG_INET_AH=m
310CONFIG_INET_ESP=m
311CONFIG_INET_IPCOMP=m
312CONFIG_INET_XFRM_TUNNEL=m
313CONFIG_INET_TUNNEL=m
314CONFIG_INET_XFRM_MODE_TRANSPORT=m
315CONFIG_INET_XFRM_MODE_TUNNEL=m
316CONFIG_INET_XFRM_MODE_BEET=m
317CONFIG_INET_LRO=y
318CONFIG_INET_DIAG=m
319CONFIG_INET_TCP_DIAG=m
320CONFIG_TCP_CONG_ADVANCED=y
321CONFIG_TCP_CONG_BIC=m
322CONFIG_TCP_CONG_CUBIC=y
323CONFIG_TCP_CONG_WESTWOOD=m
324CONFIG_TCP_CONG_HTCP=m
325CONFIG_TCP_CONG_HSTCP=m
326CONFIG_TCP_CONG_HYBLA=m
327CONFIG_TCP_CONG_VEGAS=m
328CONFIG_TCP_CONG_SCALABLE=m
329CONFIG_TCP_CONG_LP=m
330CONFIG_TCP_CONG_VENO=m
331CONFIG_TCP_CONG_YEAH=m
332CONFIG_TCP_CONG_ILLINOIS=m
333CONFIG_DEFAULT_CUBIC=y
334# CONFIG_DEFAULT_RENO is not set
335CONFIG_DEFAULT_TCP_CONG="cubic"
336CONFIG_TCP_MD5SIG=y
337CONFIG_IPV6=y
338CONFIG_IPV6_PRIVACY=y
339CONFIG_IPV6_ROUTER_PREF=y
340CONFIG_IPV6_ROUTE_INFO=y
341CONFIG_IPV6_OPTIMISTIC_DAD=y
342CONFIG_INET6_AH=m
343CONFIG_INET6_ESP=m
344CONFIG_INET6_IPCOMP=m
345CONFIG_IPV6_MIP6=m
346CONFIG_INET6_XFRM_TUNNEL=m
347CONFIG_INET6_TUNNEL=m
348CONFIG_INET6_XFRM_MODE_TRANSPORT=m
349CONFIG_INET6_XFRM_MODE_TUNNEL=m
350CONFIG_INET6_XFRM_MODE_BEET=m
351CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
352CONFIG_IPV6_SIT=m
353# CONFIG_IPV6_SIT_6RD is not set
354CONFIG_IPV6_NDISC_NODETYPE=y
355CONFIG_IPV6_TUNNEL=m
356CONFIG_IPV6_MULTIPLE_TABLES=y
357# CONFIG_IPV6_SUBTREES is not set
358CONFIG_IPV6_MROUTE=y
359# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
360CONFIG_IPV6_PIMSM_V2=y
361CONFIG_NETLABEL=y
362CONFIG_NETWORK_SECMARK=y
363# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
364CONFIG_NETFILTER=y
365# CONFIG_NETFILTER_DEBUG is not set
366CONFIG_NETFILTER_ADVANCED=y
367CONFIG_BRIDGE_NETFILTER=y
368
369#
370# Core Netfilter Configuration
371#
372CONFIG_NETFILTER_NETLINK=m
373CONFIG_NETFILTER_NETLINK_QUEUE=m
374CONFIG_NETFILTER_NETLINK_LOG=m
375CONFIG_NF_CONNTRACK=y
376CONFIG_NF_CONNTRACK_MARK=y
377CONFIG_NF_CONNTRACK_SECMARK=y
378CONFIG_NF_CONNTRACK_ZONES=y
379CONFIG_NF_CONNTRACK_EVENTS=y
380# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
381CONFIG_NF_CT_PROTO_DCCP=m
382CONFIG_NF_CT_PROTO_GRE=m
383CONFIG_NF_CT_PROTO_SCTP=m
384CONFIG_NF_CT_PROTO_UDPLITE=m
385CONFIG_NF_CONNTRACK_AMANDA=m
386CONFIG_NF_CONNTRACK_FTP=m
387CONFIG_NF_CONNTRACK_H323=m
388CONFIG_NF_CONNTRACK_IRC=m
389CONFIG_NF_CONNTRACK_BROADCAST=m
390CONFIG_NF_CONNTRACK_NETBIOS_NS=m
391# CONFIG_NF_CONNTRACK_SNMP is not set
392CONFIG_NF_CONNTRACK_PPTP=m
393CONFIG_NF_CONNTRACK_SANE=m
394CONFIG_NF_CONNTRACK_SIP=m
395CONFIG_NF_CONNTRACK_TFTP=m
396# CONFIG_NF_CT_NETLINK is not set
397CONFIG_NETFILTER_TPROXY=m
398CONFIG_NETFILTER_XTABLES=y
399
400#
401# Xtables combined modules
402#
403CONFIG_NETFILTER_XT_MARK=m
404CONFIG_NETFILTER_XT_CONNMARK=m
405
406#
407# Xtables targets
408#
409# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
410# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
411CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
412CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
413CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
414CONFIG_NETFILTER_XT_TARGET_CT=m
415CONFIG_NETFILTER_XT_TARGET_DSCP=m
416CONFIG_NETFILTER_XT_TARGET_HL=m
417CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
418CONFIG_NETFILTER_XT_TARGET_MARK=m
419CONFIG_NETFILTER_XT_TARGET_NFLOG=m
420CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
421CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
422CONFIG_NETFILTER_XT_TARGET_RATEEST=m
423CONFIG_NETFILTER_XT_TARGET_TEE=m
424CONFIG_NETFILTER_XT_TARGET_TPROXY=m
425CONFIG_NETFILTER_XT_TARGET_TRACE=m
426CONFIG_NETFILTER_XT_TARGET_SECMARK=m
427CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
428CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
429
430#
431# Xtables matches
432#
433# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
434CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
435CONFIG_NETFILTER_XT_MATCH_COMMENT=m
436CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
437CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
438CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
439CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
440# CONFIG_NETFILTER_XT_MATCH_CPU is not set
441CONFIG_NETFILTER_XT_MATCH_DCCP=m
442# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
443CONFIG_NETFILTER_XT_MATCH_DSCP=m
444CONFIG_NETFILTER_XT_MATCH_ESP=m
445CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
446CONFIG_NETFILTER_XT_MATCH_HELPER=m
447CONFIG_NETFILTER_XT_MATCH_HL=m
448CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
449CONFIG_NETFILTER_XT_MATCH_IPVS=m
450CONFIG_NETFILTER_XT_MATCH_LENGTH=m
451CONFIG_NETFILTER_XT_MATCH_LIMIT=m
452CONFIG_NETFILTER_XT_MATCH_MAC=m
453CONFIG_NETFILTER_XT_MATCH_MARK=m
454CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
455CONFIG_NETFILTER_XT_MATCH_OSF=m
456CONFIG_NETFILTER_XT_MATCH_OWNER=m
457CONFIG_NETFILTER_XT_MATCH_POLICY=m
458CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
459CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
460CONFIG_NETFILTER_XT_MATCH_QUOTA=m
461CONFIG_NETFILTER_XT_MATCH_RATEEST=m
462CONFIG_NETFILTER_XT_MATCH_REALM=m
463CONFIG_NETFILTER_XT_MATCH_RECENT=m
464CONFIG_NETFILTER_XT_MATCH_SCTP=m
465CONFIG_NETFILTER_XT_MATCH_SOCKET=m
466CONFIG_NETFILTER_XT_MATCH_STATE=y
467CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
468CONFIG_NETFILTER_XT_MATCH_STRING=m
469CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
470CONFIG_NETFILTER_XT_MATCH_TIME=m
471CONFIG_NETFILTER_XT_MATCH_U32=m
472# CONFIG_IP_SET is not set
473CONFIG_IP_VS=m
474CONFIG_IP_VS_IPV6=y
475# CONFIG_IP_VS_DEBUG is not set
476CONFIG_IP_VS_TAB_BITS=12
477
478#
479# IPVS transport protocol load balancing support
480#
481CONFIG_IP_VS_PROTO_TCP=y
482CONFIG_IP_VS_PROTO_UDP=y
483CONFIG_IP_VS_PROTO_AH_ESP=y
484CONFIG_IP_VS_PROTO_ESP=y
485CONFIG_IP_VS_PROTO_AH=y
486CONFIG_IP_VS_PROTO_SCTP=y
487
488#
489# IPVS scheduler
490#
491CONFIG_IP_VS_RR=m
492CONFIG_IP_VS_WRR=m
493CONFIG_IP_VS_LC=m
494CONFIG_IP_VS_WLC=m
495CONFIG_IP_VS_LBLC=m
496CONFIG_IP_VS_LBLCR=m
497# CONFIG_IP_VS_DH is not set
498# CONFIG_IP_VS_SH is not set
499CONFIG_IP_VS_SED=m
500CONFIG_IP_VS_NQ=m
501
502#
503# IPVS application helper
504#
505# CONFIG_IP_VS_NFCT is not set
506# CONFIG_IP_VS_PE_SIP is not set
507
508#
509# IP: Netfilter Configuration
510#
511CONFIG_NF_DEFRAG_IPV4=y
512CONFIG_NF_CONNTRACK_IPV4=y
513# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
514CONFIG_IP_NF_QUEUE=m
515CONFIG_IP_NF_IPTABLES=y
516CONFIG_IP_NF_MATCH_AH=m
517CONFIG_IP_NF_MATCH_ECN=m
518CONFIG_IP_NF_MATCH_TTL=m
519CONFIG_IP_NF_FILTER=y
520CONFIG_IP_NF_TARGET_REJECT=y
521CONFIG_IP_NF_TARGET_LOG=m
522CONFIG_IP_NF_TARGET_ULOG=m
523# CONFIG_NF_NAT is not set
524CONFIG_IP_NF_MANGLE=m
525# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
526CONFIG_IP_NF_TARGET_ECN=m
527CONFIG_IP_NF_TARGET_TTL=m
528CONFIG_IP_NF_RAW=m
529CONFIG_IP_NF_SECURITY=m
530CONFIG_IP_NF_ARPTABLES=m
531CONFIG_IP_NF_ARPFILTER=m
532CONFIG_IP_NF_ARP_MANGLE=m
533
534#
535# IPv6: Netfilter Configuration
536#
537CONFIG_NF_DEFRAG_IPV6=m
538CONFIG_NF_CONNTRACK_IPV6=m
539CONFIG_IP6_NF_QUEUE=m
540CONFIG_IP6_NF_IPTABLES=m
541CONFIG_IP6_NF_MATCH_AH=m
542CONFIG_IP6_NF_MATCH_EUI64=m
543CONFIG_IP6_NF_MATCH_FRAG=m
544CONFIG_IP6_NF_MATCH_OPTS=m
545CONFIG_IP6_NF_MATCH_HL=m
546CONFIG_IP6_NF_MATCH_IPV6HEADER=m
547CONFIG_IP6_NF_MATCH_MH=m
548CONFIG_IP6_NF_MATCH_RT=m
549CONFIG_IP6_NF_TARGET_HL=m
550CONFIG_IP6_NF_TARGET_LOG=m
551CONFIG_IP6_NF_FILTER=m
552CONFIG_IP6_NF_TARGET_REJECT=m
553CONFIG_IP6_NF_MANGLE=m
554CONFIG_IP6_NF_RAW=m
555CONFIG_IP6_NF_SECURITY=m
556CONFIG_BRIDGE_NF_EBTABLES=m
557CONFIG_BRIDGE_EBT_BROUTE=m
558CONFIG_BRIDGE_EBT_T_FILTER=m
559CONFIG_BRIDGE_EBT_T_NAT=m
560CONFIG_BRIDGE_EBT_802_3=m
561CONFIG_BRIDGE_EBT_AMONG=m
562CONFIG_BRIDGE_EBT_ARP=m
563CONFIG_BRIDGE_EBT_IP=m
564CONFIG_BRIDGE_EBT_IP6=m
565CONFIG_BRIDGE_EBT_LIMIT=m
566CONFIG_BRIDGE_EBT_MARK=m
567CONFIG_BRIDGE_EBT_PKTTYPE=m
568CONFIG_BRIDGE_EBT_STP=m
569CONFIG_BRIDGE_EBT_VLAN=m
570CONFIG_BRIDGE_EBT_ARPREPLY=m
571CONFIG_BRIDGE_EBT_DNAT=m
572CONFIG_BRIDGE_EBT_MARK_T=m
573CONFIG_BRIDGE_EBT_REDIRECT=m
574CONFIG_BRIDGE_EBT_SNAT=m
575CONFIG_BRIDGE_EBT_LOG=m
576CONFIG_BRIDGE_EBT_ULOG=m
577CONFIG_BRIDGE_EBT_NFLOG=m
578# CONFIG_IP_DCCP is not set
579CONFIG_IP_SCTP=m
580# CONFIG_SCTP_DBG_MSG is not set
581# CONFIG_SCTP_DBG_OBJCNT is not set
582# CONFIG_SCTP_HMAC_NONE is not set
583# CONFIG_SCTP_HMAC_SHA1 is not set
584CONFIG_SCTP_HMAC_MD5=y
585CONFIG_RDS=m
586CONFIG_RDS_TCP=m
587# CONFIG_RDS_DEBUG is not set
588# CONFIG_TIPC is not set
589# CONFIG_ATM is not set
590# CONFIG_L2TP is not set
591CONFIG_STP=m
592CONFIG_GARP=m
593CONFIG_BRIDGE=m
594CONFIG_BRIDGE_IGMP_SNOOPING=y
595CONFIG_NET_DSA=y
596CONFIG_NET_DSA_TAG_DSA=y
597CONFIG_NET_DSA_TAG_EDSA=y
598CONFIG_NET_DSA_TAG_TRAILER=y
599CONFIG_NET_DSA_MV88E6XXX=y
600CONFIG_NET_DSA_MV88E6060=y
601CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
602CONFIG_NET_DSA_MV88E6131=y
603CONFIG_NET_DSA_MV88E6123_61_65=y
604CONFIG_VLAN_8021Q=m
605CONFIG_VLAN_8021Q_GVRP=y
606# CONFIG_DECNET is not set
607CONFIG_LLC=m
608# CONFIG_LLC2 is not set
609# CONFIG_IPX is not set
610# CONFIG_ATALK is not set
611# CONFIG_X25 is not set
612# CONFIG_LAPB is not set
613# CONFIG_ECONET is not set
614# CONFIG_WAN_ROUTER is not set
615CONFIG_PHONET=m
616# CONFIG_IEEE802154 is not set
617CONFIG_NET_SCHED=y
618
619#
620# Queueing/Scheduling
621#
622CONFIG_NET_SCH_CBQ=m
623CONFIG_NET_SCH_HTB=m
624CONFIG_NET_SCH_HFSC=m
625CONFIG_NET_SCH_PRIO=m
626CONFIG_NET_SCH_MULTIQ=m
627CONFIG_NET_SCH_RED=m
628# CONFIG_NET_SCH_SFB is not set
629CONFIG_NET_SCH_SFQ=m
630CONFIG_NET_SCH_TEQL=m
631CONFIG_NET_SCH_TBF=m
632CONFIG_NET_SCH_GRED=m
633CONFIG_NET_SCH_DSMARK=m
634CONFIG_NET_SCH_NETEM=m
635CONFIG_NET_SCH_DRR=m
636# CONFIG_NET_SCH_MQPRIO is not set
637# CONFIG_NET_SCH_CHOKE is not set
638CONFIG_NET_SCH_INGRESS=m
639
640#
641# Classification
642#
643CONFIG_NET_CLS=y
644CONFIG_NET_CLS_BASIC=m
645CONFIG_NET_CLS_TCINDEX=m
646CONFIG_NET_CLS_ROUTE4=m
647CONFIG_NET_CLS_FW=m
648CONFIG_NET_CLS_U32=m
649CONFIG_CLS_U32_PERF=y
650CONFIG_CLS_U32_MARK=y
651CONFIG_NET_CLS_RSVP=m
652CONFIG_NET_CLS_RSVP6=m
653CONFIG_NET_CLS_FLOW=m
654CONFIG_NET_CLS_CGROUP=y
655CONFIG_NET_EMATCH=y
656CONFIG_NET_EMATCH_STACK=32
657CONFIG_NET_EMATCH_CMP=m
658CONFIG_NET_EMATCH_NBYTE=m
659CONFIG_NET_EMATCH_U32=m
660CONFIG_NET_EMATCH_META=m
661CONFIG_NET_EMATCH_TEXT=m
662CONFIG_NET_CLS_ACT=y
663CONFIG_NET_ACT_POLICE=m
664CONFIG_NET_ACT_GACT=m
665CONFIG_GACT_PROB=y
666CONFIG_NET_ACT_MIRRED=m
667CONFIG_NET_ACT_IPT=m
668CONFIG_NET_ACT_NAT=m
669CONFIG_NET_ACT_PEDIT=m
670CONFIG_NET_ACT_SIMP=m
671CONFIG_NET_ACT_SKBEDIT=m
672# CONFIG_NET_ACT_CSUM is not set
673CONFIG_NET_CLS_IND=y
674CONFIG_NET_SCH_FIFO=y
675CONFIG_DCB=y
676CONFIG_DNS_RESOLVER=y
677# CONFIG_BATMAN_ADV is not set
678CONFIG_RPS=y
679CONFIG_RFS_ACCEL=y
680CONFIG_XPS=y
681
682#
683# Network testing
684#
685# CONFIG_NET_PKTGEN is not set
686# CONFIG_HAMRADIO is not set
687# CONFIG_CAN is not set
688# CONFIG_IRDA is not set
689# CONFIG_BT is not set
690# CONFIG_AF_RXRPC is not set
691CONFIG_FIB_RULES=y
692# CONFIG_WIRELESS is not set
693# CONFIG_WIMAX is not set
694# CONFIG_RFKILL is not set
695# CONFIG_NET_9P is not set
696# CONFIG_CAIF is not set
697# CONFIG_CEPH_LIB is not set
698
699#
700# Device Drivers
701#
702
703#
704# Generic Driver Options
705#
706CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
707CONFIG_DEVTMPFS=y
708CONFIG_DEVTMPFS_MOUNT=y
709CONFIG_STANDALONE=y
710CONFIG_PREVENT_FIRMWARE_BUILD=y
711CONFIG_FW_LOADER=y
712# CONFIG_FIRMWARE_IN_KERNEL is not set
713CONFIG_EXTRA_FIRMWARE=""
714# CONFIG_DEBUG_DRIVER is not set
715# CONFIG_DEBUG_DEVRES is not set
716# CONFIG_SYS_HYPERVISOR is not set
717CONFIG_CONNECTOR=y
718CONFIG_PROC_EVENTS=y
719# CONFIG_MTD is not set
720# CONFIG_PARPORT is not set
721CONFIG_BLK_DEV=y
722# CONFIG_BLK_CPQ_DA is not set
723# CONFIG_BLK_CPQ_CISS_DA is not set
724# CONFIG_BLK_DEV_DAC960 is not set
725# CONFIG_BLK_DEV_UMEM is not set
726# CONFIG_BLK_DEV_COW_COMMON is not set
727CONFIG_BLK_DEV_LOOP=y
728CONFIG_BLK_DEV_CRYPTOLOOP=m
729# CONFIG_BLK_DEV_DRBD is not set
730# CONFIG_BLK_DEV_NBD is not set
731CONFIG_BLK_DEV_SX8=m
732CONFIG_BLK_DEV_RAM=y
733CONFIG_BLK_DEV_RAM_COUNT=16
734CONFIG_BLK_DEV_RAM_SIZE=16384
735# CONFIG_BLK_DEV_XIP is not set
736# CONFIG_CDROM_PKTCDVD is not set
737CONFIG_ATA_OVER_ETH=y
738# CONFIG_BLK_DEV_RBD is not set
739# CONFIG_SENSORS_LIS3LV02D is not set
740CONFIG_MISC_DEVICES=y
741# CONFIG_AD525X_DPOT is not set
742# CONFIG_PHANTOM is not set
743# CONFIG_SGI_IOC4 is not set
744# CONFIG_TIFM_CORE is not set
745# CONFIG_ICS932S401 is not set
746# CONFIG_ENCLOSURE_SERVICES is not set
747# CONFIG_HP_ILO is not set
748# CONFIG_APDS9802ALS is not set
749# CONFIG_ISL29003 is not set
750# CONFIG_ISL29020 is not set
751# CONFIG_SENSORS_TSL2550 is not set
752# CONFIG_SENSORS_BH1780 is not set
753# CONFIG_SENSORS_BH1770 is not set
754# CONFIG_SENSORS_APDS990X is not set
755# CONFIG_HMC6352 is not set
756# CONFIG_DS1682 is not set
757# CONFIG_BMP085 is not set
758# CONFIG_PCH_PHUB is not set
759# CONFIG_C2PORT is not set
760
761#
762# EEPROM support
763#
764# CONFIG_EEPROM_AT24 is not set
765# CONFIG_EEPROM_LEGACY is not set
766# CONFIG_EEPROM_MAX6875 is not set
767# CONFIG_EEPROM_93CX6 is not set
768# CONFIG_CB710_CORE is not set
769
770#
771# Texas Instruments shared transport line discipline
772#
773# CONFIG_SENSORS_LIS3_I2C is not set
774
775#
776# SCSI device support
777#
778CONFIG_SCSI_MOD=m
779CONFIG_RAID_ATTRS=m
780CONFIG_SCSI=m
781CONFIG_SCSI_DMA=y
782CONFIG_SCSI_TGT=m
783# CONFIG_SCSI_NETLINK is not set
784CONFIG_SCSI_PROC_FS=y
785
786#
787# SCSI support type (disk, tape, CD-ROM)
788#
789CONFIG_BLK_DEV_SD=m
790# CONFIG_CHR_DEV_ST is not set
791# CONFIG_CHR_DEV_OSST is not set
792# CONFIG_BLK_DEV_SR is not set
793# CONFIG_CHR_DEV_SG is not set
794# CONFIG_CHR_DEV_SCH is not set
795# CONFIG_SCSI_MULTI_LUN is not set
796CONFIG_SCSI_CONSTANTS=y
797CONFIG_SCSI_LOGGING=y
798# CONFIG_SCSI_SCAN_ASYNC is not set
799CONFIG_SCSI_WAIT_SCAN=m
800
801#
802# SCSI Transports
803#
804# CONFIG_SCSI_SPI_ATTRS is not set
805# CONFIG_SCSI_FC_ATTRS is not set
806# CONFIG_SCSI_ISCSI_ATTRS is not set
807CONFIG_SCSI_SAS_ATTRS=m
808# CONFIG_SCSI_SAS_LIBSAS is not set
809# CONFIG_SCSI_SRP_ATTRS is not set
810CONFIG_SCSI_LOWLEVEL=y
811# CONFIG_ISCSI_TCP is not set
812# CONFIG_ISCSI_BOOT_SYSFS is not set
813# CONFIG_SCSI_CXGB3_ISCSI is not set
814# CONFIG_SCSI_CXGB4_ISCSI is not set
815# CONFIG_SCSI_BNX2_ISCSI is not set
816# CONFIG_SCSI_BNX2X_FCOE is not set
817# CONFIG_BE2ISCSI is not set
818# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
819# CONFIG_SCSI_HPSA is not set
820# CONFIG_SCSI_3W_9XXX is not set
821# CONFIG_SCSI_3W_SAS is not set
822# CONFIG_SCSI_ACARD is not set
823# CONFIG_SCSI_AACRAID is not set
824# CONFIG_SCSI_AIC7XXX is not set
825# CONFIG_SCSI_AIC7XXX_OLD is not set
826# CONFIG_SCSI_AIC79XX is not set
827# CONFIG_SCSI_AIC94XX is not set
828# CONFIG_SCSI_MVSAS is not set
829# CONFIG_SCSI_DPT_I2O is not set
830# CONFIG_SCSI_ADVANSYS is not set
831# CONFIG_SCSI_ARCMSR is not set
832# CONFIG_MEGARAID_NEWGEN is not set
833# CONFIG_MEGARAID_LEGACY is not set
834# CONFIG_MEGARAID_SAS is not set
835# CONFIG_SCSI_MPT2SAS is not set
836# CONFIG_SCSI_HPTIOP is not set
837# CONFIG_LIBFC is not set
838# CONFIG_LIBFCOE is not set
839# CONFIG_FCOE is not set
840# CONFIG_SCSI_DMX3191D is not set
841# CONFIG_SCSI_FUTURE_DOMAIN is not set
842# CONFIG_SCSI_IPS is not set
843# CONFIG_SCSI_INITIO is not set
844# CONFIG_SCSI_INIA100 is not set
845# CONFIG_SCSI_STEX is not set
846# CONFIG_SCSI_SYM53C8XX_2 is not set
847# CONFIG_SCSI_IPR is not set
848# CONFIG_SCSI_QLOGIC_1280 is not set
849# CONFIG_SCSI_QLA_FC is not set
850# CONFIG_SCSI_QLA_ISCSI is not set
851# CONFIG_SCSI_LPFC is not set
852# CONFIG_SCSI_DC395x is not set
853# CONFIG_SCSI_DC390T is not set
854# CONFIG_SCSI_DEBUG is not set
855# CONFIG_SCSI_PMCRAID is not set
856# CONFIG_SCSI_PM8001 is not set
857# CONFIG_SCSI_SRP is not set
858# CONFIG_SCSI_BFA_FC is not set
859# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
860# CONFIG_SCSI_DH is not set
861# CONFIG_SCSI_OSD_INITIATOR is not set
862CONFIG_ATA=m
863# CONFIG_ATA_NONSTANDARD is not set
864CONFIG_ATA_VERBOSE_ERROR=y
865CONFIG_SATA_PMP=y
866
867#
868# Controllers with non-SFF native interface
869#
870# CONFIG_SATA_AHCI is not set
871# CONFIG_SATA_AHCI_PLATFORM is not set
872# CONFIG_SATA_INIC162X is not set
873# CONFIG_SATA_ACARD_AHCI is not set
874CONFIG_SATA_SIL24=m
875CONFIG_ATA_SFF=y
876
877#
878# SFF controllers with custom DMA interface
879#
880# CONFIG_PDC_ADMA is not set
881# CONFIG_SATA_QSTOR is not set
882# CONFIG_SATA_SX4 is not set
883CONFIG_ATA_BMDMA=y
884
885#
886# SATA SFF controllers with BMDMA
887#
888# CONFIG_ATA_PIIX is not set
889# CONFIG_SATA_MV is not set
890# CONFIG_SATA_NV is not set
891# CONFIG_SATA_PROMISE is not set
892# CONFIG_SATA_SIL is not set
893# CONFIG_SATA_SIS is not set
894# CONFIG_SATA_SVW is not set
895# CONFIG_SATA_ULI is not set
896# CONFIG_SATA_VIA is not set
897# CONFIG_SATA_VITESSE is not set
898
899#
900# PATA SFF controllers with BMDMA
901#
902# CONFIG_PATA_ALI is not set
903# CONFIG_PATA_AMD is not set
904# CONFIG_PATA_ARASAN_CF is not set
905# CONFIG_PATA_ARTOP is not set
906# CONFIG_PATA_ATIIXP is not set
907# CONFIG_PATA_ATP867X is not set
908# CONFIG_PATA_CMD64X is not set
909# CONFIG_PATA_CS5520 is not set
910# CONFIG_PATA_CS5530 is not set
911# CONFIG_PATA_CS5536 is not set
912# CONFIG_PATA_CYPRESS is not set
913# CONFIG_PATA_EFAR is not set
914# CONFIG_PATA_HPT366 is not set
915# CONFIG_PATA_HPT37X is not set
916# CONFIG_PATA_HPT3X2N is not set
917# CONFIG_PATA_HPT3X3 is not set
918# CONFIG_PATA_IT8213 is not set
919# CONFIG_PATA_IT821X is not set
920# CONFIG_PATA_JMICRON is not set
921# CONFIG_PATA_MARVELL is not set
922# CONFIG_PATA_NETCELL is not set
923# CONFIG_PATA_NINJA32 is not set
924# CONFIG_PATA_NS87415 is not set
925# CONFIG_PATA_OLDPIIX is not set
926# CONFIG_PATA_OPTIDMA is not set
927# CONFIG_PATA_PDC2027X is not set
928# CONFIG_PATA_PDC_OLD is not set
929# CONFIG_PATA_RADISYS is not set
930# CONFIG_PATA_RDC is not set
931# CONFIG_PATA_SC1200 is not set
932# CONFIG_PATA_SCH is not set
933# CONFIG_PATA_SERVERWORKS is not set
934# CONFIG_PATA_SIL680 is not set
935# CONFIG_PATA_SIS is not set
936# CONFIG_PATA_TOSHIBA is not set
937# CONFIG_PATA_TRIFLEX is not set
938# CONFIG_PATA_VIA is not set
939# CONFIG_PATA_WINBOND is not set
940
941#
942# PIO-only SFF controllers
943#
944# CONFIG_PATA_CMD640_PCI is not set
945# CONFIG_PATA_MPIIX is not set
946# CONFIG_PATA_NS87410 is not set
947# CONFIG_PATA_OPTI is not set
948# CONFIG_PATA_PLATFORM is not set
949# CONFIG_PATA_RZ1000 is not set
950
951#
952# Generic fallback / legacy drivers
953#
954# CONFIG_ATA_GENERIC is not set
955# CONFIG_PATA_LEGACY is not set
956CONFIG_MD=y
957CONFIG_BLK_DEV_MD=y
958CONFIG_MD_AUTODETECT=y
959CONFIG_MD_LINEAR=m
960CONFIG_MD_RAID0=m
961CONFIG_MD_RAID1=m
962CONFIG_MD_RAID10=m
963CONFIG_MD_RAID456=m
964CONFIG_MULTICORE_RAID456=y
965# CONFIG_MD_MULTIPATH is not set
966CONFIG_MD_FAULTY=m
967CONFIG_BLK_DEV_DM=m
968CONFIG_DM_DEBUG=y
969CONFIG_DM_CRYPT=m
970CONFIG_DM_SNAPSHOT=m
971CONFIG_DM_MIRROR=m
972# CONFIG_DM_RAID is not set
973CONFIG_DM_LOG_USERSPACE=m
974CONFIG_DM_ZERO=m
975CONFIG_DM_MULTIPATH=m
976CONFIG_DM_MULTIPATH_QL=m
977CONFIG_DM_MULTIPATH_ST=m
978CONFIG_DM_DELAY=m
979CONFIG_DM_UEVENT=y
980# CONFIG_DM_FLAKEY is not set
981# CONFIG_TARGET_CORE is not set
982# CONFIG_FUSION is not set
983
984#
985# IEEE 1394 (FireWire) support
986#
987# CONFIG_FIREWIRE is not set
988# CONFIG_FIREWIRE_NOSY is not set
989# CONFIG_I2O is not set
990CONFIG_NETDEVICES=y
991CONFIG_IFB=m
992CONFIG_DUMMY=m
993CONFIG_BONDING=m
994CONFIG_MACVLAN=m
995CONFIG_MACVTAP=m
996# CONFIG_EQUALIZER is not set
997CONFIG_TUN=y
998CONFIG_VETH=m
999# CONFIG_ARCNET is not set
1000# CONFIG_MII is not set
1001CONFIG_PHYLIB=y
1002
1003#
1004# MII PHY device drivers
1005#
1006# CONFIG_MARVELL_PHY is not set
1007# CONFIG_DAVICOM_PHY is not set
1008# CONFIG_QSEMI_PHY is not set
1009# CONFIG_LXT_PHY is not set
1010# CONFIG_CICADA_PHY is not set
1011# CONFIG_VITESSE_PHY is not set
1012# CONFIG_SMSC_PHY is not set
1013# CONFIG_BROADCOM_PHY is not set
1014# CONFIG_BCM63XX_PHY is not set
1015# CONFIG_ICPLUS_PHY is not set
1016# CONFIG_REALTEK_PHY is not set
1017# CONFIG_NATIONAL_PHY is not set
1018# CONFIG_STE10XP is not set
1019# CONFIG_LSI_ET1011C_PHY is not set
1020# CONFIG_MICREL_PHY is not set
1021# CONFIG_FIXED_PHY is not set
1022# CONFIG_MDIO_BITBANG is not set
1023# CONFIG_NET_ETHERNET is not set
1024CONFIG_NETDEV_1000=y
1025# CONFIG_ACENIC is not set
1026# CONFIG_DL2K is not set
1027# CONFIG_E1000 is not set
1028CONFIG_E1000E=m
1029# CONFIG_IP1000 is not set
1030# CONFIG_IGB is not set
1031# CONFIG_IGBVF is not set
1032# CONFIG_NS83820 is not set
1033# CONFIG_HAMACHI is not set
1034# CONFIG_YELLOWFIN is not set
1035# CONFIG_R8169 is not set
1036# CONFIG_SIS190 is not set
1037# CONFIG_SKGE is not set
1038# CONFIG_SKY2 is not set
1039# CONFIG_VIA_VELOCITY is not set
1040# CONFIG_TIGON3 is not set
1041# CONFIG_BNX2 is not set
1042# CONFIG_CNIC is not set
1043# CONFIG_QLA3XXX is not set
1044# CONFIG_ATL1 is not set
1045# CONFIG_ATL1E is not set
1046# CONFIG_ATL1C is not set
1047# CONFIG_JME is not set
1048# CONFIG_STMMAC_ETH is not set
1049# CONFIG_PCH_GBE is not set
1050# CONFIG_NETDEV_10000 is not set
1051# CONFIG_TR is not set
1052# CONFIG_WLAN is not set
1053
1054#
1055# Enable WiMAX (Networking options) to see the WiMAX drivers
1056#
1057# CONFIG_WAN is not set
1058
1059#
1060# CAIF transport drivers
1061#
1062# CONFIG_TILE_NET is not set
1063# CONFIG_FDDI is not set
1064# CONFIG_HIPPI is not set
1065# CONFIG_PPP is not set
1066# CONFIG_SLIP is not set
1067# CONFIG_NET_FC is not set
1068# CONFIG_NETCONSOLE is not set
1069# CONFIG_NETPOLL is not set
1070# CONFIG_NET_POLL_CONTROLLER is not set
1071# CONFIG_VMXNET3 is not set
1072# CONFIG_ISDN is not set
1073# CONFIG_PHONE is not set
1074
1075#
1076# Input device support
1077#
1078CONFIG_INPUT=y
1079# CONFIG_INPUT_FF_MEMLESS is not set
1080# CONFIG_INPUT_POLLDEV is not set
1081# CONFIG_INPUT_SPARSEKMAP is not set
1082
1083#
1084# Userland interfaces
1085#
1086# CONFIG_INPUT_MOUSEDEV is not set
1087# CONFIG_INPUT_JOYDEV is not set
1088# CONFIG_INPUT_EVDEV is not set
1089# CONFIG_INPUT_EVBUG is not set
1090
1091#
1092# Input Device Drivers
1093#
1094# CONFIG_INPUT_KEYBOARD is not set
1095# CONFIG_INPUT_MOUSE is not set
1096# CONFIG_INPUT_JOYSTICK is not set
1097# CONFIG_INPUT_TABLET is not set
1098# CONFIG_INPUT_TOUCHSCREEN is not set
1099# CONFIG_INPUT_MISC is not set
1100
1101#
1102# Hardware I/O ports
1103#
1104# CONFIG_SERIO is not set
1105# CONFIG_GAMEPORT is not set
1106
1107#
1108# Character devices
1109#
1110# CONFIG_VT is not set
1111CONFIG_UNIX98_PTYS=y
1112# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1113# CONFIG_LEGACY_PTYS is not set
1114# CONFIG_SERIAL_NONSTANDARD is not set
1115# CONFIG_NOZOMI is not set
1116# CONFIG_N_GSM is not set
1117CONFIG_DEVKMEM=y
1118
1119#
1120# Serial drivers
1121#
1122# CONFIG_SERIAL_8250 is not set
1123
1124#
1125# Non-8250 serial port support
1126#
1127# CONFIG_SERIAL_MFD_HSU is not set
1128# CONFIG_SERIAL_JSM is not set
1129# CONFIG_SERIAL_TIMBERDALE is not set
1130# CONFIG_SERIAL_ALTERA_JTAGUART is not set
1131# CONFIG_SERIAL_ALTERA_UART is not set
1132# CONFIG_SERIAL_PCH_UART is not set
1133# CONFIG_TTY_PRINTK is not set
1134CONFIG_HVC_DRIVER=y
1135# CONFIG_IPMI_HANDLER is not set
1136CONFIG_HW_RANDOM=y
1137CONFIG_HW_RANDOM_TIMERIOMEM=m
1138# CONFIG_RTC is not set
1139# CONFIG_GEN_RTC is not set
1140# CONFIG_R3964 is not set
1141# CONFIG_APPLICOM is not set
1142
1143#
1144# PCMCIA character devices
1145#
1146# CONFIG_RAW_DRIVER is not set
1147# CONFIG_TCG_TPM is not set
1148CONFIG_DEVPORT=y
1149# CONFIG_RAMOOPS is not set
1150CONFIG_I2C=y
1151CONFIG_I2C_BOARDINFO=y
1152CONFIG_I2C_COMPAT=y
1153CONFIG_I2C_CHARDEV=y
1154# CONFIG_I2C_MUX is not set
1155CONFIG_I2C_HELPER_AUTO=y
1156
1157#
1158# I2C Hardware Bus support
1159#
1160
1161#
1162# PC SMBus host controller drivers
1163#
1164# CONFIG_I2C_ALI1535 is not set
1165# CONFIG_I2C_ALI1563 is not set
1166# CONFIG_I2C_ALI15X3 is not set
1167# CONFIG_I2C_AMD756 is not set
1168# CONFIG_I2C_AMD8111 is not set
1169# CONFIG_I2C_I801 is not set
1170# CONFIG_I2C_ISCH is not set
1171# CONFIG_I2C_PIIX4 is not set
1172# CONFIG_I2C_NFORCE2 is not set
1173# CONFIG_I2C_SIS5595 is not set
1174# CONFIG_I2C_SIS630 is not set
1175# CONFIG_I2C_SIS96X is not set
1176# CONFIG_I2C_VIA is not set
1177# CONFIG_I2C_VIAPRO is not set
1178
1179#
1180# I2C system bus drivers (mostly embedded / system-on-chip)
1181#
1182# CONFIG_I2C_INTEL_MID is not set
1183# CONFIG_I2C_OCORES is not set
1184# CONFIG_I2C_PCA_PLATFORM is not set
1185# CONFIG_I2C_PXA_PCI is not set
1186# CONFIG_I2C_SIMTEC is not set
1187# CONFIG_I2C_XILINX is not set
1188# CONFIG_I2C_EG20T is not set
1189
1190#
1191# External I2C/SMBus adapter drivers
1192#
1193# CONFIG_I2C_PARPORT_LIGHT is not set
1194# CONFIG_I2C_TAOS_EVM is not set
1195
1196#
1197# Other I2C/SMBus bus drivers
1198#
1199# CONFIG_I2C_STUB is not set
1200# CONFIG_I2C_DEBUG_CORE is not set
1201# CONFIG_I2C_DEBUG_ALGO is not set
1202# CONFIG_I2C_DEBUG_BUS is not set
1203# CONFIG_SPI is not set
1204
1205#
1206# PPS support
1207#
1208# CONFIG_PPS is not set
1209
1210#
1211# PPS generators support
1212#
1213# CONFIG_W1 is not set
1214# CONFIG_POWER_SUPPLY is not set
1215# CONFIG_HWMON is not set
1216# CONFIG_THERMAL is not set
1217# CONFIG_WATCHDOG is not set
1218CONFIG_SSB_POSSIBLE=y
1219
1220#
1221# Sonics Silicon Backplane
1222#
1223# CONFIG_SSB is not set
1224CONFIG_MFD_SUPPORT=y
1225# CONFIG_MFD_CORE is not set
1226# CONFIG_MFD_88PM860X is not set
1227# CONFIG_MFD_SM501 is not set
1228# CONFIG_HTC_PASIC3 is not set
1229# CONFIG_TPS6105X is not set
1230# CONFIG_TPS6507X is not set
1231# CONFIG_TWL4030_CORE is not set
1232# CONFIG_MFD_STMPE is not set
1233# CONFIG_MFD_TC3589X is not set
1234# CONFIG_MFD_TMIO is not set
1235# CONFIG_PMIC_DA903X is not set
1236# CONFIG_PMIC_ADP5520 is not set
1237# CONFIG_MFD_MAX8925 is not set
1238# CONFIG_MFD_MAX8997 is not set
1239# CONFIG_MFD_MAX8998 is not set
1240# CONFIG_MFD_WM8400 is not set
1241# CONFIG_MFD_WM831X_I2C is not set
1242# CONFIG_MFD_WM8350_I2C is not set
1243# CONFIG_MFD_WM8994 is not set
1244# CONFIG_MFD_PCF50633 is not set
1245# CONFIG_ABX500_CORE is not set
1246# CONFIG_LPC_SCH is not set
1247# CONFIG_MFD_RDC321X is not set
1248# CONFIG_MFD_JANZ_CMODIO is not set
1249# CONFIG_MFD_VX855 is not set
1250# CONFIG_MFD_WL1273_CORE is not set
1251# CONFIG_REGULATOR is not set
1252# CONFIG_MEDIA_SUPPORT is not set
1253
1254#
1255# Graphics support
1256#
1257# CONFIG_VGA_ARB is not set
1258# CONFIG_DRM is not set
1259# CONFIG_STUB_POULSBO is not set
1260# CONFIG_VGASTATE is not set
1261# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1262# CONFIG_FB is not set
1263# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1264
1265#
1266# Display device support
1267#
1268# CONFIG_DISPLAY_SUPPORT is not set
1269# CONFIG_SOUND is not set
1270# CONFIG_HID_SUPPORT is not set
1271# CONFIG_USB_SUPPORT is not set
1272# CONFIG_UWB is not set
1273# CONFIG_MMC is not set
1274# CONFIG_MEMSTICK is not set
1275# CONFIG_NEW_LEDS is not set
1276# CONFIG_NFC_DEVICES is not set
1277# CONFIG_ACCESSIBILITY is not set
1278# CONFIG_INFINIBAND is not set
1279# CONFIG_EDAC is not set
1280# CONFIG_RTC_CLASS is not set
1281# CONFIG_DMADEVICES is not set
1282# CONFIG_AUXDISPLAY is not set
1283# CONFIG_UIO is not set
1284# CONFIG_STAGING is not set
1285
1286#
1287# File systems
1288#
1289CONFIG_EXT2_FS=y
1290CONFIG_EXT2_FS_XATTR=y
1291CONFIG_EXT2_FS_POSIX_ACL=y
1292CONFIG_EXT2_FS_SECURITY=y
1293CONFIG_EXT2_FS_XIP=y
1294CONFIG_EXT3_FS=y
1295CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
1296CONFIG_EXT3_FS_XATTR=y
1297CONFIG_EXT3_FS_POSIX_ACL=y
1298CONFIG_EXT3_FS_SECURITY=y
1299CONFIG_EXT4_FS=y
1300CONFIG_EXT4_FS_XATTR=y
1301CONFIG_EXT4_FS_POSIX_ACL=y
1302CONFIG_EXT4_FS_SECURITY=y
1303# CONFIG_EXT4_DEBUG is not set
1304CONFIG_FS_XIP=y
1305CONFIG_JBD=y
1306# CONFIG_JBD_DEBUG is not set
1307CONFIG_JBD2=y
1308CONFIG_JBD2_DEBUG=y
1309CONFIG_FS_MBCACHE=y
1310# CONFIG_REISERFS_FS is not set
1311# CONFIG_JFS_FS is not set
1312CONFIG_XFS_FS=m
1313CONFIG_XFS_QUOTA=y
1314CONFIG_XFS_POSIX_ACL=y
1315# CONFIG_XFS_RT is not set
1316# CONFIG_XFS_DEBUG is not set
1317CONFIG_GFS2_FS=m
1318CONFIG_GFS2_FS_LOCKING_DLM=y
1319# CONFIG_OCFS2_FS is not set
1320CONFIG_BTRFS_FS=m
1321CONFIG_BTRFS_FS_POSIX_ACL=y
1322# CONFIG_NILFS2_FS is not set
1323CONFIG_FS_POSIX_ACL=y
1324CONFIG_EXPORTFS=y
1325CONFIG_FILE_LOCKING=y
1326CONFIG_FSNOTIFY=y
1327CONFIG_DNOTIFY=y
1328CONFIG_INOTIFY_USER=y
1329# CONFIG_FANOTIFY is not set
1330CONFIG_QUOTA=y
1331CONFIG_QUOTA_NETLINK_INTERFACE=y
1332# CONFIG_PRINT_QUOTA_WARNING is not set
1333# CONFIG_QUOTA_DEBUG is not set
1334CONFIG_QUOTA_TREE=y
1335# CONFIG_QFMT_V1 is not set
1336CONFIG_QFMT_V2=y
1337CONFIG_QUOTACTL=y
1338# CONFIG_AUTOFS4_FS is not set
1339CONFIG_FUSE_FS=y
1340CONFIG_CUSE=m
1341CONFIG_GENERIC_ACL=y
1342
1343#
1344# Caches
1345#
1346CONFIG_FSCACHE=m
1347CONFIG_FSCACHE_STATS=y
1348# CONFIG_FSCACHE_HISTOGRAM is not set
1349# CONFIG_FSCACHE_DEBUG is not set
1350# CONFIG_FSCACHE_OBJECT_LIST is not set
1351CONFIG_CACHEFILES=m
1352# CONFIG_CACHEFILES_DEBUG is not set
1353# CONFIG_CACHEFILES_HISTOGRAM is not set
1354
1355#
1356# CD-ROM/DVD Filesystems
1357#
1358CONFIG_ISO9660_FS=m
1359CONFIG_JOLIET=y
1360CONFIG_ZISOFS=y
1361CONFIG_UDF_FS=m
1362CONFIG_UDF_NLS=y
1363
1364#
1365# DOS/FAT/NT Filesystems
1366#
1367CONFIG_FAT_FS=m
1368CONFIG_MSDOS_FS=m
1369CONFIG_VFAT_FS=m
1370CONFIG_FAT_DEFAULT_CODEPAGE=437
1371CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1372# CONFIG_NTFS_FS is not set
1373
1374#
1375# Pseudo filesystems
1376#
1377CONFIG_PROC_FS=y
1378CONFIG_PROC_KCORE=y
1379CONFIG_PROC_SYSCTL=y
1380CONFIG_PROC_PAGE_MONITOR=y
1381CONFIG_SYSFS=y
1382CONFIG_TMPFS=y
1383CONFIG_TMPFS_POSIX_ACL=y
1384CONFIG_HUGETLBFS=y
1385CONFIG_HUGETLB_PAGE=y
1386CONFIG_CONFIGFS_FS=m
1387CONFIG_MISC_FILESYSTEMS=y
1388# CONFIG_ADFS_FS is not set
1389# CONFIG_AFFS_FS is not set
1390CONFIG_ECRYPT_FS=m
1391# CONFIG_HFS_FS is not set
1392# CONFIG_HFSPLUS_FS is not set
1393# CONFIG_BEFS_FS is not set
1394# CONFIG_BFS_FS is not set
1395# CONFIG_EFS_FS is not set
1396# CONFIG_LOGFS is not set
1397CONFIG_CRAMFS=m
1398CONFIG_SQUASHFS=m
1399# CONFIG_SQUASHFS_XATTR is not set
1400# CONFIG_SQUASHFS_LZO is not set
1401# CONFIG_SQUASHFS_XZ is not set
1402# CONFIG_SQUASHFS_EMBEDDED is not set
1403CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
1404# CONFIG_VXFS_FS is not set
1405# CONFIG_MINIX_FS is not set
1406# CONFIG_OMFS_FS is not set
1407# CONFIG_HPFS_FS is not set
1408# CONFIG_QNX4FS_FS is not set
1409# CONFIG_ROMFS_FS is not set
1410# CONFIG_PSTORE is not set
1411# CONFIG_SYSV_FS is not set
1412# CONFIG_UFS_FS is not set
1413CONFIG_NETWORK_FILESYSTEMS=y
1414CONFIG_NFS_FS=m
1415CONFIG_NFS_V3=y
1416CONFIG_NFS_V3_ACL=y
1417CONFIG_NFS_V4=y
1418CONFIG_NFS_V4_1=y
1419CONFIG_PNFS_FILE_LAYOUT=m
1420CONFIG_NFS_FSCACHE=y
1421# CONFIG_NFS_USE_LEGACY_DNS is not set
1422CONFIG_NFS_USE_KERNEL_DNS=y
1423# CONFIG_NFS_USE_NEW_IDMAPPER is not set
1424CONFIG_NFSD=m
1425CONFIG_NFSD_DEPRECATED=y
1426CONFIG_NFSD_V2_ACL=y
1427CONFIG_NFSD_V3=y
1428CONFIG_NFSD_V3_ACL=y
1429CONFIG_NFSD_V4=y
1430CONFIG_LOCKD=m
1431CONFIG_LOCKD_V4=y
1432CONFIG_NFS_ACL_SUPPORT=m
1433CONFIG_NFS_COMMON=y
1434CONFIG_SUNRPC=m
1435CONFIG_SUNRPC_GSS=m
1436CONFIG_RPCSEC_GSS_KRB5=m
1437# CONFIG_CEPH_FS is not set
1438CONFIG_CIFS=m
1439CONFIG_CIFS_STATS=y
1440# CONFIG_CIFS_STATS2 is not set
1441CONFIG_CIFS_WEAK_PW_HASH=y
1442CONFIG_CIFS_UPCALL=y
1443CONFIG_CIFS_XATTR=y
1444CONFIG_CIFS_POSIX=y
1445# CONFIG_CIFS_DEBUG2 is not set
1446CONFIG_CIFS_DFS_UPCALL=y
1447CONFIG_CIFS_FSCACHE=y
1448# CONFIG_CIFS_ACL is not set
1449CONFIG_CIFS_EXPERIMENTAL=y
1450# CONFIG_NCP_FS is not set
1451# CONFIG_CODA_FS is not set
1452# CONFIG_AFS_FS is not set
1453
1454#
1455# Partition Types
1456#
1457CONFIG_PARTITION_ADVANCED=y
1458# CONFIG_ACORN_PARTITION is not set
1459CONFIG_OSF_PARTITION=y
1460CONFIG_AMIGA_PARTITION=y
1461# CONFIG_ATARI_PARTITION is not set
1462CONFIG_MAC_PARTITION=y
1463CONFIG_MSDOS_PARTITION=y
1464CONFIG_BSD_DISKLABEL=y
1465CONFIG_MINIX_SUBPARTITION=y
1466CONFIG_SOLARIS_X86_PARTITION=y
1467CONFIG_UNIXWARE_DISKLABEL=y
1468# CONFIG_LDM_PARTITION is not set
1469CONFIG_SGI_PARTITION=y
1470# CONFIG_ULTRIX_PARTITION is not set
1471CONFIG_SUN_PARTITION=y
1472CONFIG_KARMA_PARTITION=y
1473CONFIG_EFI_PARTITION=y
1474# CONFIG_SYSV68_PARTITION is not set
1475CONFIG_NLS=y
1476CONFIG_NLS_DEFAULT="utf8"
1477CONFIG_NLS_CODEPAGE_437=y
1478CONFIG_NLS_CODEPAGE_737=m
1479CONFIG_NLS_CODEPAGE_775=m
1480CONFIG_NLS_CODEPAGE_850=m
1481CONFIG_NLS_CODEPAGE_852=m
1482CONFIG_NLS_CODEPAGE_855=m
1483CONFIG_NLS_CODEPAGE_857=m
1484CONFIG_NLS_CODEPAGE_860=m
1485CONFIG_NLS_CODEPAGE_861=m
1486CONFIG_NLS_CODEPAGE_862=m
1487CONFIG_NLS_CODEPAGE_863=m
1488CONFIG_NLS_CODEPAGE_864=m
1489CONFIG_NLS_CODEPAGE_865=m
1490CONFIG_NLS_CODEPAGE_866=m
1491CONFIG_NLS_CODEPAGE_869=m
1492CONFIG_NLS_CODEPAGE_936=m
1493CONFIG_NLS_CODEPAGE_950=m
1494CONFIG_NLS_CODEPAGE_932=m
1495CONFIG_NLS_CODEPAGE_949=m
1496CONFIG_NLS_CODEPAGE_874=m
1497CONFIG_NLS_ISO8859_8=m
1498CONFIG_NLS_CODEPAGE_1250=m
1499CONFIG_NLS_CODEPAGE_1251=m
1500CONFIG_NLS_ASCII=y
1501CONFIG_NLS_ISO8859_1=m
1502CONFIG_NLS_ISO8859_2=m
1503CONFIG_NLS_ISO8859_3=m
1504CONFIG_NLS_ISO8859_4=m
1505CONFIG_NLS_ISO8859_5=m
1506CONFIG_NLS_ISO8859_6=m
1507CONFIG_NLS_ISO8859_7=m
1508CONFIG_NLS_ISO8859_9=m
1509CONFIG_NLS_ISO8859_13=m
1510CONFIG_NLS_ISO8859_14=m
1511CONFIG_NLS_ISO8859_15=m
1512CONFIG_NLS_KOI8_R=m
1513CONFIG_NLS_KOI8_U=m
1514CONFIG_NLS_UTF8=m
1515CONFIG_DLM=m
1516CONFIG_DLM_DEBUG=y
1517
1518#
1519# Kernel hacking
1520#
1521# CONFIG_PRINTK_TIME is not set
1522CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
1523# CONFIG_ENABLE_WARN_DEPRECATED is not set
1524CONFIG_ENABLE_MUST_CHECK=y
1525CONFIG_FRAME_WARN=2048
1526CONFIG_MAGIC_SYSRQ=y
1527CONFIG_STRIP_ASM_SYMS=y
1528# CONFIG_UNUSED_SYMBOLS is not set
1529CONFIG_DEBUG_FS=y
1530CONFIG_HEADERS_CHECK=y
1531# CONFIG_DEBUG_SECTION_MISMATCH is not set
1532CONFIG_DEBUG_KERNEL=y
1533CONFIG_DEBUG_SHIRQ=y
1534CONFIG_LOCKUP_DETECTOR=y
1535# CONFIG_HARDLOCKUP_DETECTOR is not set
1536# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
1537CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
1538# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1539CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1540CONFIG_DETECT_HUNG_TASK=y
1541# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1542CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1543CONFIG_SCHED_DEBUG=y
1544CONFIG_SCHEDSTATS=y
1545CONFIG_TIMER_STATS=y
1546# CONFIG_DEBUG_OBJECTS is not set
1547# CONFIG_SLUB_DEBUG_ON is not set
1548# CONFIG_SLUB_STATS is not set
1549# CONFIG_DEBUG_KMEMLEAK is not set
1550# CONFIG_DEBUG_RT_MUTEXES is not set
1551# CONFIG_RT_MUTEX_TESTER is not set
1552# CONFIG_DEBUG_SPINLOCK is not set
1553# CONFIG_DEBUG_MUTEXES is not set
1554# CONFIG_DEBUG_LOCK_ALLOC is not set
1555# CONFIG_PROVE_LOCKING is not set
1556# CONFIG_SPARSE_RCU_POINTER is not set
1557# CONFIG_LOCK_STAT is not set
1558CONFIG_DEBUG_SPINLOCK_SLEEP=y
1559# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1560CONFIG_STACKTRACE=y
1561# CONFIG_DEBUG_KOBJECT is not set
1562CONFIG_DEBUG_INFO=y
1563CONFIG_DEBUG_INFO_REDUCED=y
1564CONFIG_DEBUG_VM=y
1565# CONFIG_DEBUG_WRITECOUNT is not set
1566CONFIG_DEBUG_MEMORY_INIT=y
1567CONFIG_DEBUG_LIST=y
1568# CONFIG_TEST_LIST_SORT is not set
1569# CONFIG_DEBUG_SG is not set
1570# CONFIG_DEBUG_NOTIFIERS is not set
1571CONFIG_DEBUG_CREDENTIALS=y
1572# CONFIG_RCU_TORTURE_TEST is not set
1573# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1574# CONFIG_BACKTRACE_SELF_TEST is not set
1575# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1576CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
1577# CONFIG_LKDTM is not set
1578# CONFIG_FAULT_INJECTION is not set
1579# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1580# CONFIG_DEBUG_PAGEALLOC is not set
1581CONFIG_TRACING_SUPPORT=y
1582CONFIG_FTRACE=y
1583# CONFIG_IRQSOFF_TRACER is not set
1584# CONFIG_SCHED_TRACER is not set
1585# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1586CONFIG_BRANCH_PROFILE_NONE=y
1587# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1588# CONFIG_PROFILE_ALL_BRANCHES is not set
1589# CONFIG_BLK_DEV_IO_TRACE is not set
1590# CONFIG_BUILD_DOCSRC is not set
1591CONFIG_DYNAMIC_DEBUG=y
1592# CONFIG_ATOMIC64_SELFTEST is not set
1593CONFIG_ASYNC_RAID6_TEST=m
1594# CONFIG_SAMPLES is not set
1595# CONFIG_TEST_KSTRTOX is not set
1596CONFIG_EARLY_PRINTK=y
1597CONFIG_DEBUG_STACKOVERFLOW=y
1598# CONFIG_DEBUG_STACK_USAGE is not set
1599CONFIG_DEBUG_EXTRA_FLAGS=""
1600
1601#
1602# Security options
1603#
1604CONFIG_KEYS=y
1605CONFIG_KEYS_DEBUG_PROC_KEYS=y
1606# CONFIG_SECURITY_DMESG_RESTRICT is not set
1607CONFIG_SECURITY=y
1608CONFIG_SECURITYFS=y
1609CONFIG_SECURITY_NETWORK=y
1610CONFIG_SECURITY_NETWORK_XFRM=y
1611# CONFIG_SECURITY_PATH is not set
1612CONFIG_LSM_MMAP_MIN_ADDR=65536
1613CONFIG_SECURITY_SELINUX=y
1614CONFIG_SECURITY_SELINUX_BOOTPARAM=y
1615CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
1616CONFIG_SECURITY_SELINUX_DISABLE=y
1617CONFIG_SECURITY_SELINUX_DEVELOP=y
1618CONFIG_SECURITY_SELINUX_AVC_STATS=y
1619CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
1620# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
1621# CONFIG_SECURITY_SMACK is not set
1622# CONFIG_SECURITY_TOMOYO is not set
1623# CONFIG_SECURITY_APPARMOR is not set
1624# CONFIG_IMA is not set
1625CONFIG_DEFAULT_SECURITY_SELINUX=y
1626# CONFIG_DEFAULT_SECURITY_DAC is not set
1627CONFIG_DEFAULT_SECURITY="selinux"
1628CONFIG_XOR_BLOCKS=m
1629CONFIG_ASYNC_CORE=m
1630CONFIG_ASYNC_MEMCPY=m
1631CONFIG_ASYNC_XOR=m
1632CONFIG_ASYNC_PQ=m
1633CONFIG_ASYNC_RAID6_RECOV=m
1634CONFIG_CRYPTO=y
1635
1636#
1637# Crypto core or helper
1638#
1639CONFIG_CRYPTO_ALGAPI=y
1640CONFIG_CRYPTO_ALGAPI2=y
1641CONFIG_CRYPTO_AEAD=m
1642CONFIG_CRYPTO_AEAD2=y
1643CONFIG_CRYPTO_BLKCIPHER=m
1644CONFIG_CRYPTO_BLKCIPHER2=y
1645CONFIG_CRYPTO_HASH=y
1646CONFIG_CRYPTO_HASH2=y
1647CONFIG_CRYPTO_RNG=m
1648CONFIG_CRYPTO_RNG2=y
1649CONFIG_CRYPTO_PCOMP=m
1650CONFIG_CRYPTO_PCOMP2=y
1651CONFIG_CRYPTO_MANAGER=y
1652CONFIG_CRYPTO_MANAGER2=y
1653CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
1654CONFIG_CRYPTO_GF128MUL=m
1655CONFIG_CRYPTO_NULL=m
1656CONFIG_CRYPTO_PCRYPT=m
1657CONFIG_CRYPTO_WORKQUEUE=y
1658CONFIG_CRYPTO_CRYPTD=m
1659CONFIG_CRYPTO_AUTHENC=m
1660CONFIG_CRYPTO_TEST=m
1661
1662#
1663# Authenticated Encryption with Associated Data
1664#
1665CONFIG_CRYPTO_CCM=m
1666CONFIG_CRYPTO_GCM=m
1667CONFIG_CRYPTO_SEQIV=m
1668
1669#
1670# Block modes
1671#
1672CONFIG_CRYPTO_CBC=m
1673CONFIG_CRYPTO_CTR=m
1674CONFIG_CRYPTO_CTS=m
1675CONFIG_CRYPTO_ECB=m
1676CONFIG_CRYPTO_LRW=m
1677CONFIG_CRYPTO_PCBC=m
1678CONFIG_CRYPTO_XTS=m
1679
1680#
1681# Hash modes
1682#
1683CONFIG_CRYPTO_HMAC=y
1684CONFIG_CRYPTO_XCBC=m
1685CONFIG_CRYPTO_VMAC=m
1686
1687#
1688# Digest
1689#
1690CONFIG_CRYPTO_CRC32C=y
1691CONFIG_CRYPTO_GHASH=m
1692CONFIG_CRYPTO_MD4=m
1693CONFIG_CRYPTO_MD5=y
1694CONFIG_CRYPTO_MICHAEL_MIC=m
1695CONFIG_CRYPTO_RMD128=m
1696CONFIG_CRYPTO_RMD160=m
1697CONFIG_CRYPTO_RMD256=m
1698CONFIG_CRYPTO_RMD320=m
1699CONFIG_CRYPTO_SHA1=y
1700CONFIG_CRYPTO_SHA256=m
1701CONFIG_CRYPTO_SHA512=m
1702CONFIG_CRYPTO_TGR192=m
1703CONFIG_CRYPTO_WP512=m
1704
1705#
1706# Ciphers
1707#
1708CONFIG_CRYPTO_AES=m
1709CONFIG_CRYPTO_ANUBIS=m
1710CONFIG_CRYPTO_ARC4=m
1711CONFIG_CRYPTO_BLOWFISH=m
1712CONFIG_CRYPTO_CAMELLIA=m
1713CONFIG_CRYPTO_CAST5=m
1714CONFIG_CRYPTO_CAST6=m
1715CONFIG_CRYPTO_DES=m
1716CONFIG_CRYPTO_FCRYPT=m
1717CONFIG_CRYPTO_KHAZAD=m
1718# CONFIG_CRYPTO_SALSA20 is not set
1719CONFIG_CRYPTO_SEED=m
1720CONFIG_CRYPTO_SERPENT=m
1721CONFIG_CRYPTO_TEA=m
1722CONFIG_CRYPTO_TWOFISH=m
1723CONFIG_CRYPTO_TWOFISH_COMMON=m
1724
1725#
1726# Compression
1727#
1728CONFIG_CRYPTO_DEFLATE=m
1729CONFIG_CRYPTO_ZLIB=m
1730CONFIG_CRYPTO_LZO=m
1731
1732#
1733# Random Number Generation
1734#
1735CONFIG_CRYPTO_ANSI_CPRNG=m
1736# CONFIG_CRYPTO_USER_API_HASH is not set
1737# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
1738CONFIG_CRYPTO_HW=y
1739CONFIG_CRYPTO_DEV_HIFN_795X=m
1740CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
1741# CONFIG_BINARY_PRINTF is not set
1742
1743#
1744# Library routines
1745#
1746CONFIG_RAID6_PQ=m
1747CONFIG_BITREVERSE=y
1748CONFIG_GENERIC_FIND_FIRST_BIT=y
1749CONFIG_GENERIC_FIND_NEXT_BIT=y
1750CONFIG_GENERIC_FIND_LAST_BIT=y
1751# CONFIG_CRC_CCITT is not set
1752CONFIG_CRC16=y
1753CONFIG_CRC_T10DIF=y
1754CONFIG_CRC_ITU_T=m
1755CONFIG_CRC32=y
1756# CONFIG_CRC7 is not set
1757CONFIG_LIBCRC32C=m
1758CONFIG_AUDIT_GENERIC=y
1759CONFIG_ZLIB_INFLATE=y
1760CONFIG_ZLIB_DEFLATE=m
1761CONFIG_LZO_COMPRESS=m
1762CONFIG_LZO_DECOMPRESS=m
1763# CONFIG_XZ_DEC is not set
1764# CONFIG_XZ_DEC_BCJ is not set
1765CONFIG_DECOMPRESS_GZIP=y
1766CONFIG_TEXTSEARCH=y
1767CONFIG_TEXTSEARCH_KMP=m
1768CONFIG_TEXTSEARCH_BM=m
1769CONFIG_TEXTSEARCH_FSM=m
1770CONFIG_HAS_IOMEM=y
1771CONFIG_HAS_IOPORT=y
1772CONFIG_HAS_DMA=y
1773CONFIG_CPU_RMAP=y
1774CONFIG_NLATTR=y
1775# CONFIG_AVERAGE is not set
1776# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/include/arch/chip_tilegx.h b/arch/tile/include/arch/chip_tilegx.h
new file mode 100644
index 000000000000..ea8e4f2c9483
--- /dev/null
+++ b/arch/tile/include/arch/chip_tilegx.h
@@ -0,0 +1,258 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * @file
17 * Global header file.
18 * This header file specifies defines for TILE-Gx.
19 */
20
21#ifndef __ARCH_CHIP_H__
22#define __ARCH_CHIP_H__
23
24/** Specify chip version.
25 * When possible, prefer the CHIP_xxx symbols below for future-proofing.
26 * This is intended for cross-compiling; native compilation should
27 * use the predefined __tile_chip__ symbol.
28 */
29#define TILE_CHIP 10
30
31/** Specify chip revision.
32 * This provides for the case of a respin of a particular chip type;
33 * the normal value for this symbol is "0".
34 * This is intended for cross-compiling; native compilation should
35 * use the predefined __tile_chip_rev__ symbol.
36 */
37#define TILE_CHIP_REV 0
38
39/** The name of this architecture. */
40#define CHIP_ARCH_NAME "tilegx"
41
42/** The ELF e_machine type for binaries for this chip. */
43#define CHIP_ELF_TYPE() EM_TILEGX
44
45/** The alternate ELF e_machine type for binaries for this chip. */
46#define CHIP_COMPAT_ELF_TYPE() 0x2597
47
48/** What is the native word size of the machine? */
49#define CHIP_WORD_SIZE() 64
50
51/** How many bits of a virtual address are used. Extra bits must be
52 * the sign extension of the low bits.
53 */
54#define CHIP_VA_WIDTH() 42
55
56/** How many bits are in a physical address? */
57#define CHIP_PA_WIDTH() 40
58
59/** Size of the L2 cache, in bytes. */
60#define CHIP_L2_CACHE_SIZE() 262144
61
62/** Log size of an L2 cache line in bytes. */
63#define CHIP_L2_LOG_LINE_SIZE() 6
64
65/** Size of an L2 cache line, in bytes. */
66#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
67
68/** Associativity of the L2 cache. */
69#define CHIP_L2_ASSOC() 8
70
71/** Size of the L1 data cache, in bytes. */
72#define CHIP_L1D_CACHE_SIZE() 32768
73
74/** Log size of an L1 data cache line in bytes. */
75#define CHIP_L1D_LOG_LINE_SIZE() 6
76
77/** Size of an L1 data cache line, in bytes. */
78#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
79
80/** Associativity of the L1 data cache. */
81#define CHIP_L1D_ASSOC() 2
82
83/** Size of the L1 instruction cache, in bytes. */
84#define CHIP_L1I_CACHE_SIZE() 32768
85
86/** Log size of an L1 instruction cache line in bytes. */
87#define CHIP_L1I_LOG_LINE_SIZE() 6
88
89/** Size of an L1 instruction cache line, in bytes. */
90#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
91
92/** Associativity of the L1 instruction cache. */
93#define CHIP_L1I_ASSOC() 2
94
95/** Stride with which flush instructions must be issued. */
96#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
97
98/** Stride with which inv instructions must be issued. */
99#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
100
101/** Stride with which finv instructions must be issued. */
102#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
103
104/** Can the local cache coherently cache data that is homed elsewhere? */
105#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
106
107/** How many simultaneous outstanding victims can the L2 cache have? */
108#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
109
110/** Does the TLB support the NC and NOALLOC bits? */
111#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
112
113/** Does the chip support hash-for-home caching? */
114#define CHIP_HAS_CBOX_HOME_MAP() 1
115
116/** Number of entries in the chip's home map tables. */
117#define CHIP_CBOX_HOME_MAP_SIZE() 128
118
119/** Do uncacheable requests miss in the cache regardless of whether
120 * there is matching data? */
121#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
122
123/** Does the mf instruction wait for victims? */
124#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
125
126/** Does the chip have an "inv" instruction that doesn't also flush? */
127#define CHIP_HAS_INV() 1
128
129/** Does the chip have a "wh64" instruction? */
130#define CHIP_HAS_WH64() 1
131
132/** Does this chip have a 'dword_align' instruction? */
133#define CHIP_HAS_DWORD_ALIGN() 0
134
135/** Number of performance counters. */
136#define CHIP_PERFORMANCE_COUNTERS() 4
137
138/** Does this chip have auxiliary performance counters? */
139#define CHIP_HAS_AUX_PERF_COUNTERS() 1
140
141/** Is the CBOX_MSR1 SPR supported? */
142#define CHIP_HAS_CBOX_MSR1() 0
143
144/** Is the TILE_RTF_HWM SPR supported? */
145#define CHIP_HAS_TILE_RTF_HWM() 1
146
147/** Is the TILE_WRITE_PENDING SPR supported? */
148#define CHIP_HAS_TILE_WRITE_PENDING() 0
149
150/** Is the PROC_STATUS SPR supported? */
151#define CHIP_HAS_PROC_STATUS_SPR() 1
152
153/** Is the DSTREAM_PF SPR supported? */
154#define CHIP_HAS_DSTREAM_PF() 1
155
156/** Log of the number of mshims we have. */
157#define CHIP_LOG_NUM_MSHIMS() 2
158
159/** Are the bases of the interrupt vector areas fixed? */
160#define CHIP_HAS_FIXED_INTVEC_BASE() 0
161
162/** Are the interrupt masks split up into 2 SPRs? */
163#define CHIP_HAS_SPLIT_INTR_MASK() 0
164
165/** Is the cycle count split up into 2 SPRs? */
166#define CHIP_HAS_SPLIT_CYCLE() 0
167
168/** Does the chip have a static network? */
169#define CHIP_HAS_SN() 0
170
171/** Does the chip have a static network processor? */
172#define CHIP_HAS_SN_PROC() 0
173
174/** Size of the L1 static network processor instruction cache, in bytes. */
175/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
176
177/** Does the chip have DMA support in each tile? */
178#define CHIP_HAS_TILE_DMA() 0
179
180/** Does the chip have the second revision of the directly accessible
181 * dynamic networks? This encapsulates a number of characteristics,
182 * including the absence of the catch-all, the absence of inline message
183 * tags, the absence of support for network context-switching, and so on.
184 */
185#define CHIP_HAS_REV1_XDN() 1
186
187/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
188#define CHIP_HAS_CMPEXCH() 1
189
190/** Does the chip have memory-mapped I/O support? */
191#define CHIP_HAS_MMIO() 1
192
193/** Does the chip have post-completion interrupts? */
194#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
195
196/** Does the chip have native single step support? */
197#define CHIP_HAS_SINGLE_STEP() 1
198
199#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
200
201/** How many entries are present in the instruction TLB? */
202#define CHIP_ITLB_ENTRIES() 16
203
204/** How many entries are present in the data TLB? */
205#define CHIP_DTLB_ENTRIES() 32
206
207/** How many MAF entries does the XAUI shim have? */
208#define CHIP_XAUI_MAF_ENTRIES() 32
209
210/** Does the memory shim have a source-id table? */
211#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
212
213/** Does the L1 instruction cache clear on reset? */
214#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
215
216/** Does the chip come out of reset with valid coordinates on all tiles?
217 * Note that if defined, this also implies that the upper left is 1,1.
218 */
219#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
220
221/** Does the chip have unified packet formats? */
222#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
223
224/** Does the chip support write reordering? */
225#define CHIP_HAS_WRITE_REORDERING() 1
226
227/** Does the chip support Y-X routing as well as X-Y? */
228#define CHIP_HAS_Y_X_ROUTING() 1
229
230/** Is INTCTRL_3 managed with the correct MPL? */
231#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
232
233/** Is it possible to configure the chip to be big-endian? */
234#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
235
236/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
237#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
238
239/** Is the DIAG_TRACE_WAY SPR supported? */
240#define CHIP_HAS_DIAG_TRACE_WAY() 0
241
242/** Is the MEM_STRIPE_CONFIG SPR supported? */
243#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
244
245/** Are the TLB_PERF SPRs supported? */
246#define CHIP_HAS_TLB_PERF() 1
247
248/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
249#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
250
251/** Does the chip support rev1 DMA packets? */
252#define CHIP_HAS_REV1_DMA_PACKETS() 1
253
254/** Does the chip have an IPI shim? */
255#define CHIP_HAS_IPI() 1
256
257#endif /* !__OPEN_SOURCE__ */
258#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/interrupts_64.h b/arch/tile/include/arch/interrupts_64.h
new file mode 100644
index 000000000000..5bb58b2e4e6f
--- /dev/null
+++ b/arch/tile/include/arch/interrupts_64.h
@@ -0,0 +1,276 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __ARCH_INTERRUPTS_H__
16#define __ARCH_INTERRUPTS_H__
17
18/** Mask for an interrupt. */
19#ifdef __ASSEMBLER__
20/* Note: must handle breaking interrupts into high and low words manually. */
21#define INT_MASK(intno) (1 << (intno))
22#else
23#define INT_MASK(intno) (1ULL << (intno))
24#endif
25
26
27/** Where a given interrupt executes */
28#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
29
30/** Where to store a vector for a given interrupt. */
31#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
32
33/** The base address of user-level interrupts. */
34#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
35
36
37/** Additional synthetic interrupt. */
38#define INT_BREAKPOINT (63)
39
40#define INT_MEM_ERROR 0
41#define INT_SINGLE_STEP_3 1
42#define INT_SINGLE_STEP_2 2
43#define INT_SINGLE_STEP_1 3
44#define INT_SINGLE_STEP_0 4
45#define INT_IDN_COMPLETE 5
46#define INT_UDN_COMPLETE 6
47#define INT_ITLB_MISS 7
48#define INT_ILL 8
49#define INT_GPV 9
50#define INT_IDN_ACCESS 10
51#define INT_UDN_ACCESS 11
52#define INT_SWINT_3 12
53#define INT_SWINT_2 13
54#define INT_SWINT_1 14
55#define INT_SWINT_0 15
56#define INT_ILL_TRANS 16
57#define INT_UNALIGN_DATA 17
58#define INT_DTLB_MISS 18
59#define INT_DTLB_ACCESS 19
60#define INT_IDN_FIREWALL 20
61#define INT_UDN_FIREWALL 21
62#define INT_TILE_TIMER 22
63#define INT_AUX_TILE_TIMER 23
64#define INT_IDN_TIMER 24
65#define INT_UDN_TIMER 25
66#define INT_IDN_AVAIL 26
67#define INT_UDN_AVAIL 27
68#define INT_IPI_3 28
69#define INT_IPI_2 29
70#define INT_IPI_1 30
71#define INT_IPI_0 31
72#define INT_PERF_COUNT 32
73#define INT_AUX_PERF_COUNT 33
74#define INT_INTCTRL_3 34
75#define INT_INTCTRL_2 35
76#define INT_INTCTRL_1 36
77#define INT_INTCTRL_0 37
78#define INT_BOOT_ACCESS 38
79#define INT_WORLD_ACCESS 39
80#define INT_I_ASID 40
81#define INT_D_ASID 41
82#define INT_DOUBLE_FAULT 42
83
84#define NUM_INTERRUPTS 43
85
86#ifndef __ASSEMBLER__
87#define QUEUED_INTERRUPTS ( \
88 INT_MASK(INT_MEM_ERROR) | \
89 INT_MASK(INT_IDN_COMPLETE) | \
90 INT_MASK(INT_UDN_COMPLETE) | \
91 INT_MASK(INT_IDN_FIREWALL) | \
92 INT_MASK(INT_UDN_FIREWALL) | \
93 INT_MASK(INT_TILE_TIMER) | \
94 INT_MASK(INT_AUX_TILE_TIMER) | \
95 INT_MASK(INT_IDN_TIMER) | \
96 INT_MASK(INT_UDN_TIMER) | \
97 INT_MASK(INT_IDN_AVAIL) | \
98 INT_MASK(INT_UDN_AVAIL) | \
99 INT_MASK(INT_IPI_3) | \
100 INT_MASK(INT_IPI_2) | \
101 INT_MASK(INT_IPI_1) | \
102 INT_MASK(INT_IPI_0) | \
103 INT_MASK(INT_PERF_COUNT) | \
104 INT_MASK(INT_AUX_PERF_COUNT) | \
105 INT_MASK(INT_INTCTRL_3) | \
106 INT_MASK(INT_INTCTRL_2) | \
107 INT_MASK(INT_INTCTRL_1) | \
108 INT_MASK(INT_INTCTRL_0) | \
109 INT_MASK(INT_BOOT_ACCESS) | \
110 INT_MASK(INT_WORLD_ACCESS) | \
111 INT_MASK(INT_I_ASID) | \
112 INT_MASK(INT_D_ASID) | \
113 INT_MASK(INT_DOUBLE_FAULT) | \
114 0)
115#define NONQUEUED_INTERRUPTS ( \
116 INT_MASK(INT_SINGLE_STEP_3) | \
117 INT_MASK(INT_SINGLE_STEP_2) | \
118 INT_MASK(INT_SINGLE_STEP_1) | \
119 INT_MASK(INT_SINGLE_STEP_0) | \
120 INT_MASK(INT_ITLB_MISS) | \
121 INT_MASK(INT_ILL) | \
122 INT_MASK(INT_GPV) | \
123 INT_MASK(INT_IDN_ACCESS) | \
124 INT_MASK(INT_UDN_ACCESS) | \
125 INT_MASK(INT_SWINT_3) | \
126 INT_MASK(INT_SWINT_2) | \
127 INT_MASK(INT_SWINT_1) | \
128 INT_MASK(INT_SWINT_0) | \
129 INT_MASK(INT_ILL_TRANS) | \
130 INT_MASK(INT_UNALIGN_DATA) | \
131 INT_MASK(INT_DTLB_MISS) | \
132 INT_MASK(INT_DTLB_ACCESS) | \
133 0)
134#define CRITICAL_MASKED_INTERRUPTS ( \
135 INT_MASK(INT_MEM_ERROR) | \
136 INT_MASK(INT_SINGLE_STEP_3) | \
137 INT_MASK(INT_SINGLE_STEP_2) | \
138 INT_MASK(INT_SINGLE_STEP_1) | \
139 INT_MASK(INT_SINGLE_STEP_0) | \
140 INT_MASK(INT_IDN_COMPLETE) | \
141 INT_MASK(INT_UDN_COMPLETE) | \
142 INT_MASK(INT_IDN_FIREWALL) | \
143 INT_MASK(INT_UDN_FIREWALL) | \
144 INT_MASK(INT_TILE_TIMER) | \
145 INT_MASK(INT_AUX_TILE_TIMER) | \
146 INT_MASK(INT_IDN_TIMER) | \
147 INT_MASK(INT_UDN_TIMER) | \
148 INT_MASK(INT_IDN_AVAIL) | \
149 INT_MASK(INT_UDN_AVAIL) | \
150 INT_MASK(INT_IPI_3) | \
151 INT_MASK(INT_IPI_2) | \
152 INT_MASK(INT_IPI_1) | \
153 INT_MASK(INT_IPI_0) | \
154 INT_MASK(INT_PERF_COUNT) | \
155 INT_MASK(INT_AUX_PERF_COUNT) | \
156 INT_MASK(INT_INTCTRL_3) | \
157 INT_MASK(INT_INTCTRL_2) | \
158 INT_MASK(INT_INTCTRL_1) | \
159 INT_MASK(INT_INTCTRL_0) | \
160 0)
161#define CRITICAL_UNMASKED_INTERRUPTS ( \
162 INT_MASK(INT_ITLB_MISS) | \
163 INT_MASK(INT_ILL) | \
164 INT_MASK(INT_GPV) | \
165 INT_MASK(INT_IDN_ACCESS) | \
166 INT_MASK(INT_UDN_ACCESS) | \
167 INT_MASK(INT_SWINT_3) | \
168 INT_MASK(INT_SWINT_2) | \
169 INT_MASK(INT_SWINT_1) | \
170 INT_MASK(INT_SWINT_0) | \
171 INT_MASK(INT_ILL_TRANS) | \
172 INT_MASK(INT_UNALIGN_DATA) | \
173 INT_MASK(INT_DTLB_MISS) | \
174 INT_MASK(INT_DTLB_ACCESS) | \
175 INT_MASK(INT_BOOT_ACCESS) | \
176 INT_MASK(INT_WORLD_ACCESS) | \
177 INT_MASK(INT_I_ASID) | \
178 INT_MASK(INT_D_ASID) | \
179 INT_MASK(INT_DOUBLE_FAULT) | \
180 0)
181#define MASKABLE_INTERRUPTS ( \
182 INT_MASK(INT_MEM_ERROR) | \
183 INT_MASK(INT_SINGLE_STEP_3) | \
184 INT_MASK(INT_SINGLE_STEP_2) | \
185 INT_MASK(INT_SINGLE_STEP_1) | \
186 INT_MASK(INT_SINGLE_STEP_0) | \
187 INT_MASK(INT_IDN_COMPLETE) | \
188 INT_MASK(INT_UDN_COMPLETE) | \
189 INT_MASK(INT_IDN_FIREWALL) | \
190 INT_MASK(INT_UDN_FIREWALL) | \
191 INT_MASK(INT_TILE_TIMER) | \
192 INT_MASK(INT_AUX_TILE_TIMER) | \
193 INT_MASK(INT_IDN_TIMER) | \
194 INT_MASK(INT_UDN_TIMER) | \
195 INT_MASK(INT_IDN_AVAIL) | \
196 INT_MASK(INT_UDN_AVAIL) | \
197 INT_MASK(INT_IPI_3) | \
198 INT_MASK(INT_IPI_2) | \
199 INT_MASK(INT_IPI_1) | \
200 INT_MASK(INT_IPI_0) | \
201 INT_MASK(INT_PERF_COUNT) | \
202 INT_MASK(INT_AUX_PERF_COUNT) | \
203 INT_MASK(INT_INTCTRL_3) | \
204 INT_MASK(INT_INTCTRL_2) | \
205 INT_MASK(INT_INTCTRL_1) | \
206 INT_MASK(INT_INTCTRL_0) | \
207 0)
208#define UNMASKABLE_INTERRUPTS ( \
209 INT_MASK(INT_ITLB_MISS) | \
210 INT_MASK(INT_ILL) | \
211 INT_MASK(INT_GPV) | \
212 INT_MASK(INT_IDN_ACCESS) | \
213 INT_MASK(INT_UDN_ACCESS) | \
214 INT_MASK(INT_SWINT_3) | \
215 INT_MASK(INT_SWINT_2) | \
216 INT_MASK(INT_SWINT_1) | \
217 INT_MASK(INT_SWINT_0) | \
218 INT_MASK(INT_ILL_TRANS) | \
219 INT_MASK(INT_UNALIGN_DATA) | \
220 INT_MASK(INT_DTLB_MISS) | \
221 INT_MASK(INT_DTLB_ACCESS) | \
222 INT_MASK(INT_BOOT_ACCESS) | \
223 INT_MASK(INT_WORLD_ACCESS) | \
224 INT_MASK(INT_I_ASID) | \
225 INT_MASK(INT_D_ASID) | \
226 INT_MASK(INT_DOUBLE_FAULT) | \
227 0)
228#define SYNC_INTERRUPTS ( \
229 INT_MASK(INT_SINGLE_STEP_3) | \
230 INT_MASK(INT_SINGLE_STEP_2) | \
231 INT_MASK(INT_SINGLE_STEP_1) | \
232 INT_MASK(INT_SINGLE_STEP_0) | \
233 INT_MASK(INT_IDN_COMPLETE) | \
234 INT_MASK(INT_UDN_COMPLETE) | \
235 INT_MASK(INT_ITLB_MISS) | \
236 INT_MASK(INT_ILL) | \
237 INT_MASK(INT_GPV) | \
238 INT_MASK(INT_IDN_ACCESS) | \
239 INT_MASK(INT_UDN_ACCESS) | \
240 INT_MASK(INT_SWINT_3) | \
241 INT_MASK(INT_SWINT_2) | \
242 INT_MASK(INT_SWINT_1) | \
243 INT_MASK(INT_SWINT_0) | \
244 INT_MASK(INT_ILL_TRANS) | \
245 INT_MASK(INT_UNALIGN_DATA) | \
246 INT_MASK(INT_DTLB_MISS) | \
247 INT_MASK(INT_DTLB_ACCESS) | \
248 0)
249#define NON_SYNC_INTERRUPTS ( \
250 INT_MASK(INT_MEM_ERROR) | \
251 INT_MASK(INT_IDN_FIREWALL) | \
252 INT_MASK(INT_UDN_FIREWALL) | \
253 INT_MASK(INT_TILE_TIMER) | \
254 INT_MASK(INT_AUX_TILE_TIMER) | \
255 INT_MASK(INT_IDN_TIMER) | \
256 INT_MASK(INT_UDN_TIMER) | \
257 INT_MASK(INT_IDN_AVAIL) | \
258 INT_MASK(INT_UDN_AVAIL) | \
259 INT_MASK(INT_IPI_3) | \
260 INT_MASK(INT_IPI_2) | \
261 INT_MASK(INT_IPI_1) | \
262 INT_MASK(INT_IPI_0) | \
263 INT_MASK(INT_PERF_COUNT) | \
264 INT_MASK(INT_AUX_PERF_COUNT) | \
265 INT_MASK(INT_INTCTRL_3) | \
266 INT_MASK(INT_INTCTRL_2) | \
267 INT_MASK(INT_INTCTRL_1) | \
268 INT_MASK(INT_INTCTRL_0) | \
269 INT_MASK(INT_BOOT_ACCESS) | \
270 INT_MASK(INT_WORLD_ACCESS) | \
271 INT_MASK(INT_I_ASID) | \
272 INT_MASK(INT_D_ASID) | \
273 INT_MASK(INT_DOUBLE_FAULT) | \
274 0)
275#endif /* !__ASSEMBLER__ */
276#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/spr_def_64.h b/arch/tile/include/arch/spr_def_64.h
new file mode 100644
index 000000000000..cd3e5f95d5fd
--- /dev/null
+++ b/arch/tile/include/arch/spr_def_64.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __DOXYGEN__
16
17#ifndef __ARCH_SPR_DEF_H__
18#define __ARCH_SPR_DEF_H__
19
20#define SPR_AUX_PERF_COUNT_0 0x2105
21#define SPR_AUX_PERF_COUNT_1 0x2106
22#define SPR_AUX_PERF_COUNT_CTL 0x2107
23#define SPR_AUX_PERF_COUNT_STS 0x2108
24#define SPR_CMPEXCH_VALUE 0x2780
25#define SPR_CYCLE 0x2781
26#define SPR_DONE 0x2705
27#define SPR_DSTREAM_PF 0x2706
28#define SPR_EVENT_BEGIN 0x2782
29#define SPR_EVENT_END 0x2783
30#define SPR_EX_CONTEXT_0_0 0x2580
31#define SPR_EX_CONTEXT_0_1 0x2581
32#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
33#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
34#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
35#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
36#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
37#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
38#define SPR_EX_CONTEXT_1_0 0x2480
39#define SPR_EX_CONTEXT_1_1 0x2481
40#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
41#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
42#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
43#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
44#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
45#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
46#define SPR_EX_CONTEXT_2_0 0x2380
47#define SPR_EX_CONTEXT_2_1 0x2381
48#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
49#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
50#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
51#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
52#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
53#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
54#define SPR_FAIL 0x2707
55#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
56#define SPR_INTCTRL_0_STATUS 0x2505
57#define SPR_INTCTRL_1_STATUS 0x2405
58#define SPR_INTCTRL_2_STATUS 0x2305
59#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
60#define SPR_INTERRUPT_MASK_0 0x2506
61#define SPR_INTERRUPT_MASK_1 0x2406
62#define SPR_INTERRUPT_MASK_2 0x2306
63#define SPR_INTERRUPT_MASK_RESET_0 0x2507
64#define SPR_INTERRUPT_MASK_RESET_1 0x2407
65#define SPR_INTERRUPT_MASK_RESET_2 0x2307
66#define SPR_INTERRUPT_MASK_SET_0 0x2508
67#define SPR_INTERRUPT_MASK_SET_1 0x2408
68#define SPR_INTERRUPT_MASK_SET_2 0x2308
69#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
70#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
71#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
72#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
73#define SPR_IPI_EVENT_0 0x1f05
74#define SPR_IPI_EVENT_1 0x1e05
75#define SPR_IPI_EVENT_2 0x1d05
76#define SPR_IPI_EVENT_RESET_0 0x1f06
77#define SPR_IPI_EVENT_RESET_1 0x1e06
78#define SPR_IPI_EVENT_RESET_2 0x1d06
79#define SPR_IPI_EVENT_SET_0 0x1f07
80#define SPR_IPI_EVENT_SET_1 0x1e07
81#define SPR_IPI_EVENT_SET_2 0x1d07
82#define SPR_IPI_MASK_0 0x1f08
83#define SPR_IPI_MASK_1 0x1e08
84#define SPR_IPI_MASK_2 0x1d08
85#define SPR_IPI_MASK_RESET_0 0x1f09
86#define SPR_IPI_MASK_RESET_1 0x1e09
87#define SPR_IPI_MASK_RESET_2 0x1d09
88#define SPR_IPI_MASK_SET_0 0x1f0a
89#define SPR_IPI_MASK_SET_1 0x1e0a
90#define SPR_IPI_MASK_SET_2 0x1d0a
91#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
92#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
93#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
94#define SPR_MPL_INTCTRL_0_SET_0 0x2500
95#define SPR_MPL_INTCTRL_0_SET_1 0x2501
96#define SPR_MPL_INTCTRL_0_SET_2 0x2502
97#define SPR_MPL_INTCTRL_1_SET_0 0x2400
98#define SPR_MPL_INTCTRL_1_SET_1 0x2401
99#define SPR_MPL_INTCTRL_1_SET_2 0x2402
100#define SPR_MPL_INTCTRL_2_SET_0 0x2300
101#define SPR_MPL_INTCTRL_2_SET_1 0x2301
102#define SPR_MPL_INTCTRL_2_SET_2 0x2302
103#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
104#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
105#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
106#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
107#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
108#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
109#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
110#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
111#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
112#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
113#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
114#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
115#define SPR_MPL_UDN_TIMER_SET_0 0x1900
116#define SPR_MPL_UDN_TIMER_SET_1 0x1901
117#define SPR_MPL_UDN_TIMER_SET_2 0x1902
118#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
119#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
120#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
121#define SPR_PASS 0x2709
122#define SPR_PERF_COUNT_0 0x2005
123#define SPR_PERF_COUNT_1 0x2006
124#define SPR_PERF_COUNT_CTL 0x2007
125#define SPR_PERF_COUNT_DN_CTL 0x2008
126#define SPR_PERF_COUNT_STS 0x2009
127#define SPR_PROC_STATUS 0x2784
128#define SPR_SIM_CONTROL 0x2785
129#define SPR_SINGLE_STEP_CONTROL_0 0x0405
130#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
131#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
132#define SPR_SINGLE_STEP_CONTROL_1 0x0305
133#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
134#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
135#define SPR_SINGLE_STEP_CONTROL_2 0x0205
136#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
137#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
138#define SPR_SINGLE_STEP_EN_0_0 0x250a
139#define SPR_SINGLE_STEP_EN_0_1 0x240a
140#define SPR_SINGLE_STEP_EN_0_2 0x230a
141#define SPR_SINGLE_STEP_EN_1_0 0x250b
142#define SPR_SINGLE_STEP_EN_1_1 0x240b
143#define SPR_SINGLE_STEP_EN_1_2 0x230b
144#define SPR_SINGLE_STEP_EN_2_0 0x250c
145#define SPR_SINGLE_STEP_EN_2_1 0x240c
146#define SPR_SINGLE_STEP_EN_2_2 0x230c
147#define SPR_SYSTEM_SAVE_0_0 0x2582
148#define SPR_SYSTEM_SAVE_0_1 0x2583
149#define SPR_SYSTEM_SAVE_0_2 0x2584
150#define SPR_SYSTEM_SAVE_0_3 0x2585
151#define SPR_SYSTEM_SAVE_1_0 0x2482
152#define SPR_SYSTEM_SAVE_1_1 0x2483
153#define SPR_SYSTEM_SAVE_1_2 0x2484
154#define SPR_SYSTEM_SAVE_1_3 0x2485
155#define SPR_SYSTEM_SAVE_2_0 0x2382
156#define SPR_SYSTEM_SAVE_2_1 0x2383
157#define SPR_SYSTEM_SAVE_2_2 0x2384
158#define SPR_SYSTEM_SAVE_2_3 0x2385
159#define SPR_TILE_COORD 0x270b
160#define SPR_TILE_RTF_HWM 0x270c
161#define SPR_TILE_TIMER_CONTROL 0x1605
162#define SPR_UDN_AVAIL_EN 0x1b05
163#define SPR_UDN_DATA_AVAIL 0x0b80
164#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
165#define SPR_UDN_DEMUX_COUNT_0 0x0b05
166#define SPR_UDN_DEMUX_COUNT_1 0x0b06
167#define SPR_UDN_DEMUX_COUNT_2 0x0b07
168#define SPR_UDN_DEMUX_COUNT_3 0x0b08
169#define SPR_UDN_DIRECTION_PROTECT 0x1505
170
171#endif /* !defined(__ARCH_SPR_DEF_H__) */
172
173#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
new file mode 100644
index 000000000000..321705294800
--- /dev/null
+++ b/arch/tile/include/asm/atomic_64.h
@@ -0,0 +1,169 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Do not include directly; use <asm/atomic.h>.
15 */
16
17#ifndef _ASM_TILE_ATOMIC_64_H
18#define _ASM_TILE_ATOMIC_64_H
19
20#ifndef __ASSEMBLY__
21
22#include <arch/spr_def.h>
23
24/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
25
26#define atomic_set(v, i) ((v)->counter = (i))
27
28/*
29 * The smp_mb() operations throughout are to support the fact that
30 * Linux requires memory barriers before and after the operation,
31 * on any routine which updates memory and returns a value.
32 */
33
34static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
35{
36 int val;
37 __insn_mtspr(SPR_CMPEXCH_VALUE, o);
38 smp_mb(); /* barrier for proper semantics */
39 val = __insn_cmpexch4((void *)&v->counter, n);
40 smp_mb(); /* barrier for proper semantics */
41 return val;
42}
43
44static inline int atomic_xchg(atomic_t *v, int n)
45{
46 int val;
47 smp_mb(); /* barrier for proper semantics */
48 val = __insn_exch4((void *)&v->counter, n);
49 smp_mb(); /* barrier for proper semantics */
50 return val;
51}
52
53static inline void atomic_add(int i, atomic_t *v)
54{
55 __insn_fetchadd4((void *)&v->counter, i);
56}
57
58static inline int atomic_add_return(int i, atomic_t *v)
59{
60 int val;
61 smp_mb(); /* barrier for proper semantics */
62 val = __insn_fetchadd4((void *)&v->counter, i) + i;
63 barrier(); /* the "+ i" above will wait on memory */
64 return val;
65}
66
67static inline int atomic_add_unless(atomic_t *v, int a, int u)
68{
69 int guess, oldval = v->counter;
70 do {
71 if (oldval == u)
72 break;
73 guess = oldval;
74 oldval = atomic_cmpxchg(v, guess, guess + a);
75 } while (guess != oldval);
76 return oldval != u;
77}
78
79/* Now the true 64-bit operations. */
80
81#define ATOMIC64_INIT(i) { (i) }
82
83#define atomic64_read(v) ((v)->counter)
84#define atomic64_set(v, i) ((v)->counter = (i))
85
86static inline long atomic64_cmpxchg(atomic64_t *v, long o, long n)
87{
88 long val;
89 smp_mb(); /* barrier for proper semantics */
90 __insn_mtspr(SPR_CMPEXCH_VALUE, o);
91 val = __insn_cmpexch((void *)&v->counter, n);
92 smp_mb(); /* barrier for proper semantics */
93 return val;
94}
95
96static inline long atomic64_xchg(atomic64_t *v, long n)
97{
98 long val;
99 smp_mb(); /* barrier for proper semantics */
100 val = __insn_exch((void *)&v->counter, n);
101 smp_mb(); /* barrier for proper semantics */
102 return val;
103}
104
105static inline void atomic64_add(long i, atomic64_t *v)
106{
107 __insn_fetchadd((void *)&v->counter, i);
108}
109
110static inline long atomic64_add_return(long i, atomic64_t *v)
111{
112 int val;
113 smp_mb(); /* barrier for proper semantics */
114 val = __insn_fetchadd((void *)&v->counter, i) + i;
115 barrier(); /* the "+ i" above will wait on memory */
116 return val;
117}
118
119static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
120{
121 long guess, oldval = v->counter;
122 do {
123 if (oldval == u)
124 break;
125 guess = oldval;
126 oldval = atomic64_cmpxchg(v, guess, guess + a);
127 } while (guess != oldval);
128 return oldval != u;
129}
130
131#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
132#define atomic64_sub(i, v) atomic64_add(-(i), (v))
133#define atomic64_inc_return(v) atomic64_add_return(1, (v))
134#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
135#define atomic64_inc(v) atomic64_add(1, (v))
136#define atomic64_dec(v) atomic64_sub(1, (v))
137
138#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
139#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
140#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
141#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
142
143#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
144
145/* Atomic dec and inc don't implement barrier, so provide them if needed. */
146#define smp_mb__before_atomic_dec() smp_mb()
147#define smp_mb__after_atomic_dec() smp_mb()
148#define smp_mb__before_atomic_inc() smp_mb()
149#define smp_mb__after_atomic_inc() smp_mb()
150
151#define xchg(ptr, x) \
152 ((typeof(*(ptr))) \
153 ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
154 atomic_xchg((atomic_t *)(ptr), (long)(x)) : \
155 (sizeof(*(ptr)) == sizeof(atomic_long_t)) ? \
156 atomic_long_xchg((atomic_long_t *)(ptr), (long)(x)) : \
157 __xchg_called_with_bad_pointer()))
158
159#define cmpxchg(ptr, o, n) \
160 ((typeof(*(ptr))) \
161 ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
162 atomic_cmpxchg((atomic_t *)(ptr), (long)(o), (long)(n)) : \
163 (sizeof(*(ptr)) == sizeof(atomic_long_t)) ? \
164 atomic_long_cmpxchg((atomic_long_t *)(ptr), (long)(o), (long)(n)) : \
165 __cmpxchg_called_with_bad_pointer()))
166
167#endif /* !__ASSEMBLY__ */
168
169#endif /* _ASM_TILE_ATOMIC_64_H */
diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
index 132e6bbd07e9..16f1fa51fea1 100644
--- a/arch/tile/include/asm/bitops.h
+++ b/arch/tile/include/asm/bitops.h
@@ -122,6 +122,7 @@ static inline unsigned long __arch_hweight64(__u64 w)
122#include <asm-generic/bitops/lock.h> 122#include <asm-generic/bitops/lock.h>
123#include <asm-generic/bitops/find.h> 123#include <asm-generic/bitops/find.h>
124#include <asm-generic/bitops/sched.h> 124#include <asm-generic/bitops/sched.h>
125#include <asm-generic/bitops/non-atomic.h>
125#include <asm-generic/bitops/le.h> 126#include <asm-generic/bitops/le.h>
126 127
127#endif /* _ASM_TILE_BITOPS_H */ 128#endif /* _ASM_TILE_BITOPS_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
index 2638be51a164..d31ab905cfa7 100644
--- a/arch/tile/include/asm/bitops_32.h
+++ b/arch/tile/include/asm/bitops_32.h
@@ -126,7 +126,6 @@ static inline int test_and_change_bit(unsigned nr,
126#define smp_mb__before_clear_bit() smp_mb() 126#define smp_mb__before_clear_bit() smp_mb()
127#define smp_mb__after_clear_bit() do {} while (0) 127#define smp_mb__after_clear_bit() do {} while (0)
128 128
129#include <asm-generic/bitops/non-atomic.h>
130#include <asm-generic/bitops/ext2-atomic.h> 129#include <asm-generic/bitops/ext2-atomic.h>
131 130
132#endif /* _ASM_TILE_BITOPS_32_H */ 131#endif /* _ASM_TILE_BITOPS_32_H */
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
new file mode 100644
index 000000000000..99615e8d2d8b
--- /dev/null
+++ b/arch/tile/include/asm/bitops_64.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_BITOPS_64_H
16#define _ASM_TILE_BITOPS_64_H
17
18#include <linux/compiler.h>
19#include <asm/atomic.h>
20#include <asm/system.h>
21
22/* See <asm/bitops.h> for API comments. */
23
24static inline void set_bit(unsigned nr, volatile unsigned long *addr)
25{
26 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
27 __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
28}
29
30static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
31{
32 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
33 __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
34}
35
36#define smp_mb__before_clear_bit() smp_mb()
37#define smp_mb__after_clear_bit() smp_mb()
38
39
40static inline void change_bit(unsigned nr, volatile unsigned long *addr)
41{
42 unsigned long old, mask = (1UL << (nr % BITS_PER_LONG));
43 long guess, oldval;
44 addr += nr / BITS_PER_LONG;
45 old = *addr;
46 do {
47 guess = oldval;
48 oldval = atomic64_cmpxchg((atomic64_t *)addr,
49 guess, guess ^ mask);
50 } while (guess != oldval);
51}
52
53
54/*
55 * The test_and_xxx_bit() routines require a memory fence before we
56 * start the operation, and after the operation completes. We use
57 * smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
58 * barrier(), to block until the atomic op is complete.
59 */
60
61static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
62{
63 int val;
64 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
65 smp_mb(); /* barrier for proper semantics */
66 val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
67 & mask) != 0;
68 barrier();
69 return val;
70}
71
72
73static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
74{
75 int val;
76 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
77 smp_mb(); /* barrier for proper semantics */
78 val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
79 & mask) != 0;
80 barrier();
81 return val;
82}
83
84
85static inline int test_and_change_bit(unsigned nr,
86 volatile unsigned long *addr)
87{
88 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
89 long guess, oldval = *addr;
90 addr += nr / BITS_PER_LONG;
91 oldval = *addr;
92 do {
93 guess = oldval;
94 oldval = atomic64_cmpxchg((atomic64_t *)addr,
95 guess, guess ^ mask);
96 } while (guess != oldval);
97 return (oldval & mask) != 0;
98}
99
100#define ext2_set_bit_atomic(lock, nr, addr) \
101 test_and_set_bit((nr), (unsigned long *)(addr))
102#define ext2_clear_bit_atomic(lock, nr, addr) \
103 test_and_clear_bit((nr), (unsigned long *)(addr))
104
105#endif /* _ASM_TILE_BITOPS_64_H */
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index c3ae570c0a5d..bf95f55b82b0 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -215,8 +215,8 @@ struct compat_sigaction;
215struct compat_siginfo; 215struct compat_siginfo;
216struct compat_sigaltstack; 216struct compat_sigaltstack;
217long compat_sys_execve(const char __user *path, 217long compat_sys_execve(const char __user *path,
218 const compat_uptr_t __user *argv, 218 compat_uptr_t __user *argv,
219 const compat_uptr_t __user *envp, struct pt_regs *); 219 compat_uptr_t __user *envp, struct pt_regs *);
220long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act, 220long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act,
221 struct compat_sigaction __user *oact, 221 struct compat_sigaction __user *oact,
222 size_t sigsetsize); 222 size_t sigsetsize);
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
index 03df7b1e77bf..c0633466cd5c 100644
--- a/arch/tile/include/asm/opcode-tile_64.h
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -5,863 +5,711 @@
5#ifndef opcode_tile_h 5#ifndef opcode_tile_h
6#define opcode_tile_h 6#define opcode_tile_h
7 7
8typedef unsigned long long tile_bundle_bits; 8typedef unsigned long long tilegx_bundle_bits;
9 9
10 10
11enum 11enum
12{ 12{
13 TILE_MAX_OPERANDS = 5 /* mm */ 13 TILEGX_MAX_OPERANDS = 4 /* bfexts */
14}; 14};
15 15
16typedef enum 16typedef enum
17{ 17{
18 TILE_OPC_BPT, 18 TILEGX_OPC_BPT,
19 TILE_OPC_INFO, 19 TILEGX_OPC_INFO,
20 TILE_OPC_INFOL, 20 TILEGX_OPC_INFOL,
21 TILE_OPC_J, 21 TILEGX_OPC_MOVE,
22 TILE_OPC_JAL, 22 TILEGX_OPC_MOVEI,
23 TILE_OPC_MOVE, 23 TILEGX_OPC_MOVELI,
24 TILE_OPC_MOVE_SN, 24 TILEGX_OPC_PREFETCH,
25 TILE_OPC_MOVEI, 25 TILEGX_OPC_PREFETCH_ADD_L1,
26 TILE_OPC_MOVEI_SN, 26 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
27 TILE_OPC_MOVELI, 27 TILEGX_OPC_PREFETCH_ADD_L2,
28 TILE_OPC_MOVELI_SN, 28 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
29 TILE_OPC_MOVELIS, 29 TILEGX_OPC_PREFETCH_ADD_L3,
30 TILE_OPC_PREFETCH, 30 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
31 TILE_OPC_RAISE, 31 TILEGX_OPC_PREFETCH_L1,
32 TILE_OPC_ADD, 32 TILEGX_OPC_PREFETCH_L1_FAULT,
33 TILE_OPC_ADD_SN, 33 TILEGX_OPC_PREFETCH_L2,
34 TILE_OPC_ADDB, 34 TILEGX_OPC_PREFETCH_L2_FAULT,
35 TILE_OPC_ADDB_SN, 35 TILEGX_OPC_PREFETCH_L3,
36 TILE_OPC_ADDBS_U, 36 TILEGX_OPC_PREFETCH_L3_FAULT,
37 TILE_OPC_ADDBS_U_SN, 37 TILEGX_OPC_RAISE,
38 TILE_OPC_ADDH, 38 TILEGX_OPC_ADD,
39 TILE_OPC_ADDH_SN, 39 TILEGX_OPC_ADDI,
40 TILE_OPC_ADDHS, 40 TILEGX_OPC_ADDLI,
41 TILE_OPC_ADDHS_SN, 41 TILEGX_OPC_ADDX,
42 TILE_OPC_ADDI, 42 TILEGX_OPC_ADDXI,
43 TILE_OPC_ADDI_SN, 43 TILEGX_OPC_ADDXLI,
44 TILE_OPC_ADDIB, 44 TILEGX_OPC_ADDXSC,
45 TILE_OPC_ADDIB_SN, 45 TILEGX_OPC_AND,
46 TILE_OPC_ADDIH, 46 TILEGX_OPC_ANDI,
47 TILE_OPC_ADDIH_SN, 47 TILEGX_OPC_BEQZ,
48 TILE_OPC_ADDLI, 48 TILEGX_OPC_BEQZT,
49 TILE_OPC_ADDLI_SN, 49 TILEGX_OPC_BFEXTS,
50 TILE_OPC_ADDLIS, 50 TILEGX_OPC_BFEXTU,
51 TILE_OPC_ADDS, 51 TILEGX_OPC_BFINS,
52 TILE_OPC_ADDS_SN, 52 TILEGX_OPC_BGEZ,
53 TILE_OPC_ADIFFB_U, 53 TILEGX_OPC_BGEZT,
54 TILE_OPC_ADIFFB_U_SN, 54 TILEGX_OPC_BGTZ,
55 TILE_OPC_ADIFFH, 55 TILEGX_OPC_BGTZT,
56 TILE_OPC_ADIFFH_SN, 56 TILEGX_OPC_BLBC,
57 TILE_OPC_AND, 57 TILEGX_OPC_BLBCT,
58 TILE_OPC_AND_SN, 58 TILEGX_OPC_BLBS,
59 TILE_OPC_ANDI, 59 TILEGX_OPC_BLBST,
60 TILE_OPC_ANDI_SN, 60 TILEGX_OPC_BLEZ,
61 TILE_OPC_AULI, 61 TILEGX_OPC_BLEZT,
62 TILE_OPC_AVGB_U, 62 TILEGX_OPC_BLTZ,
63 TILE_OPC_AVGB_U_SN, 63 TILEGX_OPC_BLTZT,
64 TILE_OPC_AVGH, 64 TILEGX_OPC_BNEZ,
65 TILE_OPC_AVGH_SN, 65 TILEGX_OPC_BNEZT,
66 TILE_OPC_BBNS, 66 TILEGX_OPC_CLZ,
67 TILE_OPC_BBNS_SN, 67 TILEGX_OPC_CMOVEQZ,
68 TILE_OPC_BBNST, 68 TILEGX_OPC_CMOVNEZ,
69 TILE_OPC_BBNST_SN, 69 TILEGX_OPC_CMPEQ,
70 TILE_OPC_BBS, 70 TILEGX_OPC_CMPEQI,
71 TILE_OPC_BBS_SN, 71 TILEGX_OPC_CMPEXCH,
72 TILE_OPC_BBST, 72 TILEGX_OPC_CMPEXCH4,
73 TILE_OPC_BBST_SN, 73 TILEGX_OPC_CMPLES,
74 TILE_OPC_BGEZ, 74 TILEGX_OPC_CMPLEU,
75 TILE_OPC_BGEZ_SN, 75 TILEGX_OPC_CMPLTS,
76 TILE_OPC_BGEZT, 76 TILEGX_OPC_CMPLTSI,
77 TILE_OPC_BGEZT_SN, 77 TILEGX_OPC_CMPLTU,
78 TILE_OPC_BGZ, 78 TILEGX_OPC_CMPLTUI,
79 TILE_OPC_BGZ_SN, 79 TILEGX_OPC_CMPNE,
80 TILE_OPC_BGZT, 80 TILEGX_OPC_CMUL,
81 TILE_OPC_BGZT_SN, 81 TILEGX_OPC_CMULA,
82 TILE_OPC_BITX, 82 TILEGX_OPC_CMULAF,
83 TILE_OPC_BITX_SN, 83 TILEGX_OPC_CMULF,
84 TILE_OPC_BLEZ, 84 TILEGX_OPC_CMULFR,
85 TILE_OPC_BLEZ_SN, 85 TILEGX_OPC_CMULH,
86 TILE_OPC_BLEZT, 86 TILEGX_OPC_CMULHR,
87 TILE_OPC_BLEZT_SN, 87 TILEGX_OPC_CRC32_32,
88 TILE_OPC_BLZ, 88 TILEGX_OPC_CRC32_8,
89 TILE_OPC_BLZ_SN, 89 TILEGX_OPC_CTZ,
90 TILE_OPC_BLZT, 90 TILEGX_OPC_DBLALIGN,
91 TILE_OPC_BLZT_SN, 91 TILEGX_OPC_DBLALIGN2,
92 TILE_OPC_BNZ, 92 TILEGX_OPC_DBLALIGN4,
93 TILE_OPC_BNZ_SN, 93 TILEGX_OPC_DBLALIGN6,
94 TILE_OPC_BNZT, 94 TILEGX_OPC_DRAIN,
95 TILE_OPC_BNZT_SN, 95 TILEGX_OPC_DTLBPR,
96 TILE_OPC_BYTEX, 96 TILEGX_OPC_EXCH,
97 TILE_OPC_BYTEX_SN, 97 TILEGX_OPC_EXCH4,
98 TILE_OPC_BZ, 98 TILEGX_OPC_FDOUBLE_ADD_FLAGS,
99 TILE_OPC_BZ_SN, 99 TILEGX_OPC_FDOUBLE_ADDSUB,
100 TILE_OPC_BZT, 100 TILEGX_OPC_FDOUBLE_MUL_FLAGS,
101 TILE_OPC_BZT_SN, 101 TILEGX_OPC_FDOUBLE_PACK1,
102 TILE_OPC_CLZ, 102 TILEGX_OPC_FDOUBLE_PACK2,
103 TILE_OPC_CLZ_SN, 103 TILEGX_OPC_FDOUBLE_SUB_FLAGS,
104 TILE_OPC_CRC32_32, 104 TILEGX_OPC_FDOUBLE_UNPACK_MAX,
105 TILE_OPC_CRC32_32_SN, 105 TILEGX_OPC_FDOUBLE_UNPACK_MIN,
106 TILE_OPC_CRC32_8, 106 TILEGX_OPC_FETCHADD,
107 TILE_OPC_CRC32_8_SN, 107 TILEGX_OPC_FETCHADD4,
108 TILE_OPC_CTZ, 108 TILEGX_OPC_FETCHADDGEZ,
109 TILE_OPC_CTZ_SN, 109 TILEGX_OPC_FETCHADDGEZ4,
110 TILE_OPC_DRAIN, 110 TILEGX_OPC_FETCHAND,
111 TILE_OPC_DTLBPR, 111 TILEGX_OPC_FETCHAND4,
112 TILE_OPC_DWORD_ALIGN, 112 TILEGX_OPC_FETCHOR,
113 TILE_OPC_DWORD_ALIGN_SN, 113 TILEGX_OPC_FETCHOR4,
114 TILE_OPC_FINV, 114 TILEGX_OPC_FINV,
115 TILE_OPC_FLUSH, 115 TILEGX_OPC_FLUSH,
116 TILE_OPC_FNOP, 116 TILEGX_OPC_FLUSHWB,
117 TILE_OPC_ICOH, 117 TILEGX_OPC_FNOP,
118 TILE_OPC_ILL, 118 TILEGX_OPC_FSINGLE_ADD1,
119 TILE_OPC_INTHB, 119 TILEGX_OPC_FSINGLE_ADDSUB2,
120 TILE_OPC_INTHB_SN, 120 TILEGX_OPC_FSINGLE_MUL1,
121 TILE_OPC_INTHH, 121 TILEGX_OPC_FSINGLE_MUL2,
122 TILE_OPC_INTHH_SN, 122 TILEGX_OPC_FSINGLE_PACK1,
123 TILE_OPC_INTLB, 123 TILEGX_OPC_FSINGLE_PACK2,
124 TILE_OPC_INTLB_SN, 124 TILEGX_OPC_FSINGLE_SUB1,
125 TILE_OPC_INTLH, 125 TILEGX_OPC_ICOH,
126 TILE_OPC_INTLH_SN, 126 TILEGX_OPC_ILL,
127 TILE_OPC_INV, 127 TILEGX_OPC_INV,
128 TILE_OPC_IRET, 128 TILEGX_OPC_IRET,
129 TILE_OPC_JALB, 129 TILEGX_OPC_J,
130 TILE_OPC_JALF, 130 TILEGX_OPC_JAL,
131 TILE_OPC_JALR, 131 TILEGX_OPC_JALR,
132 TILE_OPC_JALRP, 132 TILEGX_OPC_JALRP,
133 TILE_OPC_JB, 133 TILEGX_OPC_JR,
134 TILE_OPC_JF, 134 TILEGX_OPC_JRP,
135 TILE_OPC_JR, 135 TILEGX_OPC_LD,
136 TILE_OPC_JRP, 136 TILEGX_OPC_LD1S,
137 TILE_OPC_LB, 137 TILEGX_OPC_LD1S_ADD,
138 TILE_OPC_LB_SN, 138 TILEGX_OPC_LD1U,
139 TILE_OPC_LB_U, 139 TILEGX_OPC_LD1U_ADD,
140 TILE_OPC_LB_U_SN, 140 TILEGX_OPC_LD2S,
141 TILE_OPC_LBADD, 141 TILEGX_OPC_LD2S_ADD,
142 TILE_OPC_LBADD_SN, 142 TILEGX_OPC_LD2U,
143 TILE_OPC_LBADD_U, 143 TILEGX_OPC_LD2U_ADD,
144 TILE_OPC_LBADD_U_SN, 144 TILEGX_OPC_LD4S,
145 TILE_OPC_LH, 145 TILEGX_OPC_LD4S_ADD,
146 TILE_OPC_LH_SN, 146 TILEGX_OPC_LD4U,
147 TILE_OPC_LH_U, 147 TILEGX_OPC_LD4U_ADD,
148 TILE_OPC_LH_U_SN, 148 TILEGX_OPC_LD_ADD,
149 TILE_OPC_LHADD, 149 TILEGX_OPC_LDNA,
150 TILE_OPC_LHADD_SN, 150 TILEGX_OPC_LDNA_ADD,
151 TILE_OPC_LHADD_U, 151 TILEGX_OPC_LDNT,
152 TILE_OPC_LHADD_U_SN, 152 TILEGX_OPC_LDNT1S,
153 TILE_OPC_LNK, 153 TILEGX_OPC_LDNT1S_ADD,
154 TILE_OPC_LNK_SN, 154 TILEGX_OPC_LDNT1U,
155 TILE_OPC_LW, 155 TILEGX_OPC_LDNT1U_ADD,
156 TILE_OPC_LW_SN, 156 TILEGX_OPC_LDNT2S,
157 TILE_OPC_LW_NA, 157 TILEGX_OPC_LDNT2S_ADD,
158 TILE_OPC_LW_NA_SN, 158 TILEGX_OPC_LDNT2U,
159 TILE_OPC_LWADD, 159 TILEGX_OPC_LDNT2U_ADD,
160 TILE_OPC_LWADD_SN, 160 TILEGX_OPC_LDNT4S,
161 TILE_OPC_LWADD_NA, 161 TILEGX_OPC_LDNT4S_ADD,
162 TILE_OPC_LWADD_NA_SN, 162 TILEGX_OPC_LDNT4U,
163 TILE_OPC_MAXB_U, 163 TILEGX_OPC_LDNT4U_ADD,
164 TILE_OPC_MAXB_U_SN, 164 TILEGX_OPC_LDNT_ADD,
165 TILE_OPC_MAXH, 165 TILEGX_OPC_LNK,
166 TILE_OPC_MAXH_SN, 166 TILEGX_OPC_MF,
167 TILE_OPC_MAXIB_U, 167 TILEGX_OPC_MFSPR,
168 TILE_OPC_MAXIB_U_SN, 168 TILEGX_OPC_MM,
169 TILE_OPC_MAXIH, 169 TILEGX_OPC_MNZ,
170 TILE_OPC_MAXIH_SN, 170 TILEGX_OPC_MTSPR,
171 TILE_OPC_MF, 171 TILEGX_OPC_MUL_HS_HS,
172 TILE_OPC_MFSPR, 172 TILEGX_OPC_MUL_HS_HU,
173 TILE_OPC_MINB_U, 173 TILEGX_OPC_MUL_HS_LS,
174 TILE_OPC_MINB_U_SN, 174 TILEGX_OPC_MUL_HS_LU,
175 TILE_OPC_MINH, 175 TILEGX_OPC_MUL_HU_HU,
176 TILE_OPC_MINH_SN, 176 TILEGX_OPC_MUL_HU_LS,
177 TILE_OPC_MINIB_U, 177 TILEGX_OPC_MUL_HU_LU,
178 TILE_OPC_MINIB_U_SN, 178 TILEGX_OPC_MUL_LS_LS,
179 TILE_OPC_MINIH, 179 TILEGX_OPC_MUL_LS_LU,
180 TILE_OPC_MINIH_SN, 180 TILEGX_OPC_MUL_LU_LU,
181 TILE_OPC_MM, 181 TILEGX_OPC_MULA_HS_HS,
182 TILE_OPC_MNZ, 182 TILEGX_OPC_MULA_HS_HU,
183 TILE_OPC_MNZ_SN, 183 TILEGX_OPC_MULA_HS_LS,
184 TILE_OPC_MNZB, 184 TILEGX_OPC_MULA_HS_LU,
185 TILE_OPC_MNZB_SN, 185 TILEGX_OPC_MULA_HU_HU,
186 TILE_OPC_MNZH, 186 TILEGX_OPC_MULA_HU_LS,
187 TILE_OPC_MNZH_SN, 187 TILEGX_OPC_MULA_HU_LU,
188 TILE_OPC_MTSPR, 188 TILEGX_OPC_MULA_LS_LS,
189 TILE_OPC_MULHH_SS, 189 TILEGX_OPC_MULA_LS_LU,
190 TILE_OPC_MULHH_SS_SN, 190 TILEGX_OPC_MULA_LU_LU,
191 TILE_OPC_MULHH_SU, 191 TILEGX_OPC_MULAX,
192 TILE_OPC_MULHH_SU_SN, 192 TILEGX_OPC_MULX,
193 TILE_OPC_MULHH_UU, 193 TILEGX_OPC_MZ,
194 TILE_OPC_MULHH_UU_SN, 194 TILEGX_OPC_NAP,
195 TILE_OPC_MULHHA_SS, 195 TILEGX_OPC_NOP,
196 TILE_OPC_MULHHA_SS_SN, 196 TILEGX_OPC_NOR,
197 TILE_OPC_MULHHA_SU, 197 TILEGX_OPC_OR,
198 TILE_OPC_MULHHA_SU_SN, 198 TILEGX_OPC_ORI,
199 TILE_OPC_MULHHA_UU, 199 TILEGX_OPC_PCNT,
200 TILE_OPC_MULHHA_UU_SN, 200 TILEGX_OPC_REVBITS,
201 TILE_OPC_MULHHSA_UU, 201 TILEGX_OPC_REVBYTES,
202 TILE_OPC_MULHHSA_UU_SN, 202 TILEGX_OPC_ROTL,
203 TILE_OPC_MULHL_SS, 203 TILEGX_OPC_ROTLI,
204 TILE_OPC_MULHL_SS_SN, 204 TILEGX_OPC_SHL,
205 TILE_OPC_MULHL_SU, 205 TILEGX_OPC_SHL16INSLI,
206 TILE_OPC_MULHL_SU_SN, 206 TILEGX_OPC_SHL1ADD,
207 TILE_OPC_MULHL_US, 207 TILEGX_OPC_SHL1ADDX,
208 TILE_OPC_MULHL_US_SN, 208 TILEGX_OPC_SHL2ADD,
209 TILE_OPC_MULHL_UU, 209 TILEGX_OPC_SHL2ADDX,
210 TILE_OPC_MULHL_UU_SN, 210 TILEGX_OPC_SHL3ADD,
211 TILE_OPC_MULHLA_SS, 211 TILEGX_OPC_SHL3ADDX,
212 TILE_OPC_MULHLA_SS_SN, 212 TILEGX_OPC_SHLI,
213 TILE_OPC_MULHLA_SU, 213 TILEGX_OPC_SHLX,
214 TILE_OPC_MULHLA_SU_SN, 214 TILEGX_OPC_SHLXI,
215 TILE_OPC_MULHLA_US, 215 TILEGX_OPC_SHRS,
216 TILE_OPC_MULHLA_US_SN, 216 TILEGX_OPC_SHRSI,
217 TILE_OPC_MULHLA_UU, 217 TILEGX_OPC_SHRU,
218 TILE_OPC_MULHLA_UU_SN, 218 TILEGX_OPC_SHRUI,
219 TILE_OPC_MULHLSA_UU, 219 TILEGX_OPC_SHRUX,
220 TILE_OPC_MULHLSA_UU_SN, 220 TILEGX_OPC_SHRUXI,
221 TILE_OPC_MULLL_SS, 221 TILEGX_OPC_SHUFFLEBYTES,
222 TILE_OPC_MULLL_SS_SN, 222 TILEGX_OPC_ST,
223 TILE_OPC_MULLL_SU, 223 TILEGX_OPC_ST1,
224 TILE_OPC_MULLL_SU_SN, 224 TILEGX_OPC_ST1_ADD,
225 TILE_OPC_MULLL_UU, 225 TILEGX_OPC_ST2,
226 TILE_OPC_MULLL_UU_SN, 226 TILEGX_OPC_ST2_ADD,
227 TILE_OPC_MULLLA_SS, 227 TILEGX_OPC_ST4,
228 TILE_OPC_MULLLA_SS_SN, 228 TILEGX_OPC_ST4_ADD,
229 TILE_OPC_MULLLA_SU, 229 TILEGX_OPC_ST_ADD,
230 TILE_OPC_MULLLA_SU_SN, 230 TILEGX_OPC_STNT,
231 TILE_OPC_MULLLA_UU, 231 TILEGX_OPC_STNT1,
232 TILE_OPC_MULLLA_UU_SN, 232 TILEGX_OPC_STNT1_ADD,
233 TILE_OPC_MULLLSA_UU, 233 TILEGX_OPC_STNT2,
234 TILE_OPC_MULLLSA_UU_SN, 234 TILEGX_OPC_STNT2_ADD,
235 TILE_OPC_MVNZ, 235 TILEGX_OPC_STNT4,
236 TILE_OPC_MVNZ_SN, 236 TILEGX_OPC_STNT4_ADD,
237 TILE_OPC_MVZ, 237 TILEGX_OPC_STNT_ADD,
238 TILE_OPC_MVZ_SN, 238 TILEGX_OPC_SUB,
239 TILE_OPC_MZ, 239 TILEGX_OPC_SUBX,
240 TILE_OPC_MZ_SN, 240 TILEGX_OPC_SUBXSC,
241 TILE_OPC_MZB, 241 TILEGX_OPC_SWINT0,
242 TILE_OPC_MZB_SN, 242 TILEGX_OPC_SWINT1,
243 TILE_OPC_MZH, 243 TILEGX_OPC_SWINT2,
244 TILE_OPC_MZH_SN, 244 TILEGX_OPC_SWINT3,
245 TILE_OPC_NAP, 245 TILEGX_OPC_TBLIDXB0,
246 TILE_OPC_NOP, 246 TILEGX_OPC_TBLIDXB1,
247 TILE_OPC_NOR, 247 TILEGX_OPC_TBLIDXB2,
248 TILE_OPC_NOR_SN, 248 TILEGX_OPC_TBLIDXB3,
249 TILE_OPC_OR, 249 TILEGX_OPC_V1ADD,
250 TILE_OPC_OR_SN, 250 TILEGX_OPC_V1ADDI,
251 TILE_OPC_ORI, 251 TILEGX_OPC_V1ADDUC,
252 TILE_OPC_ORI_SN, 252 TILEGX_OPC_V1ADIFFU,
253 TILE_OPC_PACKBS_U, 253 TILEGX_OPC_V1AVGU,
254 TILE_OPC_PACKBS_U_SN, 254 TILEGX_OPC_V1CMPEQ,
255 TILE_OPC_PACKHB, 255 TILEGX_OPC_V1CMPEQI,
256 TILE_OPC_PACKHB_SN, 256 TILEGX_OPC_V1CMPLES,
257 TILE_OPC_PACKHS, 257 TILEGX_OPC_V1CMPLEU,
258 TILE_OPC_PACKHS_SN, 258 TILEGX_OPC_V1CMPLTS,
259 TILE_OPC_PACKLB, 259 TILEGX_OPC_V1CMPLTSI,
260 TILE_OPC_PACKLB_SN, 260 TILEGX_OPC_V1CMPLTU,
261 TILE_OPC_PCNT, 261 TILEGX_OPC_V1CMPLTUI,
262 TILE_OPC_PCNT_SN, 262 TILEGX_OPC_V1CMPNE,
263 TILE_OPC_RL, 263 TILEGX_OPC_V1DDOTPU,
264 TILE_OPC_RL_SN, 264 TILEGX_OPC_V1DDOTPUA,
265 TILE_OPC_RLI, 265 TILEGX_OPC_V1DDOTPUS,
266 TILE_OPC_RLI_SN, 266 TILEGX_OPC_V1DDOTPUSA,
267 TILE_OPC_S1A, 267 TILEGX_OPC_V1DOTP,
268 TILE_OPC_S1A_SN, 268 TILEGX_OPC_V1DOTPA,
269 TILE_OPC_S2A, 269 TILEGX_OPC_V1DOTPU,
270 TILE_OPC_S2A_SN, 270 TILEGX_OPC_V1DOTPUA,
271 TILE_OPC_S3A, 271 TILEGX_OPC_V1DOTPUS,
272 TILE_OPC_S3A_SN, 272 TILEGX_OPC_V1DOTPUSA,
273 TILE_OPC_SADAB_U, 273 TILEGX_OPC_V1INT_H,
274 TILE_OPC_SADAB_U_SN, 274 TILEGX_OPC_V1INT_L,
275 TILE_OPC_SADAH, 275 TILEGX_OPC_V1MAXU,
276 TILE_OPC_SADAH_SN, 276 TILEGX_OPC_V1MAXUI,
277 TILE_OPC_SADAH_U, 277 TILEGX_OPC_V1MINU,
278 TILE_OPC_SADAH_U_SN, 278 TILEGX_OPC_V1MINUI,
279 TILE_OPC_SADB_U, 279 TILEGX_OPC_V1MNZ,
280 TILE_OPC_SADB_U_SN, 280 TILEGX_OPC_V1MULTU,
281 TILE_OPC_SADH, 281 TILEGX_OPC_V1MULU,
282 TILE_OPC_SADH_SN, 282 TILEGX_OPC_V1MULUS,
283 TILE_OPC_SADH_U, 283 TILEGX_OPC_V1MZ,
284 TILE_OPC_SADH_U_SN, 284 TILEGX_OPC_V1SADAU,
285 TILE_OPC_SB, 285 TILEGX_OPC_V1SADU,
286 TILE_OPC_SBADD, 286 TILEGX_OPC_V1SHL,
287 TILE_OPC_SEQ, 287 TILEGX_OPC_V1SHLI,
288 TILE_OPC_SEQ_SN, 288 TILEGX_OPC_V1SHRS,
289 TILE_OPC_SEQB, 289 TILEGX_OPC_V1SHRSI,
290 TILE_OPC_SEQB_SN, 290 TILEGX_OPC_V1SHRU,
291 TILE_OPC_SEQH, 291 TILEGX_OPC_V1SHRUI,
292 TILE_OPC_SEQH_SN, 292 TILEGX_OPC_V1SUB,
293 TILE_OPC_SEQI, 293 TILEGX_OPC_V1SUBUC,
294 TILE_OPC_SEQI_SN, 294 TILEGX_OPC_V2ADD,
295 TILE_OPC_SEQIB, 295 TILEGX_OPC_V2ADDI,
296 TILE_OPC_SEQIB_SN, 296 TILEGX_OPC_V2ADDSC,
297 TILE_OPC_SEQIH, 297 TILEGX_OPC_V2ADIFFS,
298 TILE_OPC_SEQIH_SN, 298 TILEGX_OPC_V2AVGS,
299 TILE_OPC_SH, 299 TILEGX_OPC_V2CMPEQ,
300 TILE_OPC_SHADD, 300 TILEGX_OPC_V2CMPEQI,
301 TILE_OPC_SHL, 301 TILEGX_OPC_V2CMPLES,
302 TILE_OPC_SHL_SN, 302 TILEGX_OPC_V2CMPLEU,
303 TILE_OPC_SHLB, 303 TILEGX_OPC_V2CMPLTS,
304 TILE_OPC_SHLB_SN, 304 TILEGX_OPC_V2CMPLTSI,
305 TILE_OPC_SHLH, 305 TILEGX_OPC_V2CMPLTU,
306 TILE_OPC_SHLH_SN, 306 TILEGX_OPC_V2CMPLTUI,
307 TILE_OPC_SHLI, 307 TILEGX_OPC_V2CMPNE,
308 TILE_OPC_SHLI_SN, 308 TILEGX_OPC_V2DOTP,
309 TILE_OPC_SHLIB, 309 TILEGX_OPC_V2DOTPA,
310 TILE_OPC_SHLIB_SN, 310 TILEGX_OPC_V2INT_H,
311 TILE_OPC_SHLIH, 311 TILEGX_OPC_V2INT_L,
312 TILE_OPC_SHLIH_SN, 312 TILEGX_OPC_V2MAXS,
313 TILE_OPC_SHR, 313 TILEGX_OPC_V2MAXSI,
314 TILE_OPC_SHR_SN, 314 TILEGX_OPC_V2MINS,
315 TILE_OPC_SHRB, 315 TILEGX_OPC_V2MINSI,
316 TILE_OPC_SHRB_SN, 316 TILEGX_OPC_V2MNZ,
317 TILE_OPC_SHRH, 317 TILEGX_OPC_V2MULFSC,
318 TILE_OPC_SHRH_SN, 318 TILEGX_OPC_V2MULS,
319 TILE_OPC_SHRI, 319 TILEGX_OPC_V2MULTS,
320 TILE_OPC_SHRI_SN, 320 TILEGX_OPC_V2MZ,
321 TILE_OPC_SHRIB, 321 TILEGX_OPC_V2PACKH,
322 TILE_OPC_SHRIB_SN, 322 TILEGX_OPC_V2PACKL,
323 TILE_OPC_SHRIH, 323 TILEGX_OPC_V2PACKUC,
324 TILE_OPC_SHRIH_SN, 324 TILEGX_OPC_V2SADAS,
325 TILE_OPC_SLT, 325 TILEGX_OPC_V2SADAU,
326 TILE_OPC_SLT_SN, 326 TILEGX_OPC_V2SADS,
327 TILE_OPC_SLT_U, 327 TILEGX_OPC_V2SADU,
328 TILE_OPC_SLT_U_SN, 328 TILEGX_OPC_V2SHL,
329 TILE_OPC_SLTB, 329 TILEGX_OPC_V2SHLI,
330 TILE_OPC_SLTB_SN, 330 TILEGX_OPC_V2SHLSC,
331 TILE_OPC_SLTB_U, 331 TILEGX_OPC_V2SHRS,
332 TILE_OPC_SLTB_U_SN, 332 TILEGX_OPC_V2SHRSI,
333 TILE_OPC_SLTE, 333 TILEGX_OPC_V2SHRU,
334 TILE_OPC_SLTE_SN, 334 TILEGX_OPC_V2SHRUI,
335 TILE_OPC_SLTE_U, 335 TILEGX_OPC_V2SUB,
336 TILE_OPC_SLTE_U_SN, 336 TILEGX_OPC_V2SUBSC,
337 TILE_OPC_SLTEB, 337 TILEGX_OPC_V4ADD,
338 TILE_OPC_SLTEB_SN, 338 TILEGX_OPC_V4ADDSC,
339 TILE_OPC_SLTEB_U, 339 TILEGX_OPC_V4INT_H,
340 TILE_OPC_SLTEB_U_SN, 340 TILEGX_OPC_V4INT_L,
341 TILE_OPC_SLTEH, 341 TILEGX_OPC_V4PACKSC,
342 TILE_OPC_SLTEH_SN, 342 TILEGX_OPC_V4SHL,
343 TILE_OPC_SLTEH_U, 343 TILEGX_OPC_V4SHLSC,
344 TILE_OPC_SLTEH_U_SN, 344 TILEGX_OPC_V4SHRS,
345 TILE_OPC_SLTH, 345 TILEGX_OPC_V4SHRU,
346 TILE_OPC_SLTH_SN, 346 TILEGX_OPC_V4SUB,
347 TILE_OPC_SLTH_U, 347 TILEGX_OPC_V4SUBSC,
348 TILE_OPC_SLTH_U_SN, 348 TILEGX_OPC_WH64,
349 TILE_OPC_SLTI, 349 TILEGX_OPC_XOR,
350 TILE_OPC_SLTI_SN, 350 TILEGX_OPC_XORI,
351 TILE_OPC_SLTI_U, 351 TILEGX_OPC_NONE
352 TILE_OPC_SLTI_U_SN, 352} tilegx_mnemonic;
353 TILE_OPC_SLTIB,
354 TILE_OPC_SLTIB_SN,
355 TILE_OPC_SLTIB_U,
356 TILE_OPC_SLTIB_U_SN,
357 TILE_OPC_SLTIH,
358 TILE_OPC_SLTIH_SN,
359 TILE_OPC_SLTIH_U,
360 TILE_OPC_SLTIH_U_SN,
361 TILE_OPC_SNE,
362 TILE_OPC_SNE_SN,
363 TILE_OPC_SNEB,
364 TILE_OPC_SNEB_SN,
365 TILE_OPC_SNEH,
366 TILE_OPC_SNEH_SN,
367 TILE_OPC_SRA,
368 TILE_OPC_SRA_SN,
369 TILE_OPC_SRAB,
370 TILE_OPC_SRAB_SN,
371 TILE_OPC_SRAH,
372 TILE_OPC_SRAH_SN,
373 TILE_OPC_SRAI,
374 TILE_OPC_SRAI_SN,
375 TILE_OPC_SRAIB,
376 TILE_OPC_SRAIB_SN,
377 TILE_OPC_SRAIH,
378 TILE_OPC_SRAIH_SN,
379 TILE_OPC_SUB,
380 TILE_OPC_SUB_SN,
381 TILE_OPC_SUBB,
382 TILE_OPC_SUBB_SN,
383 TILE_OPC_SUBBS_U,
384 TILE_OPC_SUBBS_U_SN,
385 TILE_OPC_SUBH,
386 TILE_OPC_SUBH_SN,
387 TILE_OPC_SUBHS,
388 TILE_OPC_SUBHS_SN,
389 TILE_OPC_SUBS,
390 TILE_OPC_SUBS_SN,
391 TILE_OPC_SW,
392 TILE_OPC_SWADD,
393 TILE_OPC_SWINT0,
394 TILE_OPC_SWINT1,
395 TILE_OPC_SWINT2,
396 TILE_OPC_SWINT3,
397 TILE_OPC_TBLIDXB0,
398 TILE_OPC_TBLIDXB0_SN,
399 TILE_OPC_TBLIDXB1,
400 TILE_OPC_TBLIDXB1_SN,
401 TILE_OPC_TBLIDXB2,
402 TILE_OPC_TBLIDXB2_SN,
403 TILE_OPC_TBLIDXB3,
404 TILE_OPC_TBLIDXB3_SN,
405 TILE_OPC_TNS,
406 TILE_OPC_TNS_SN,
407 TILE_OPC_WH64,
408 TILE_OPC_XOR,
409 TILE_OPC_XOR_SN,
410 TILE_OPC_XORI,
411 TILE_OPC_XORI_SN,
412 TILE_OPC_NONE
413} tile_mnemonic;
414 353
415/* 64-bit pattern for a { bpt ; nop } bundle. */ 354/* 64-bit pattern for a { bpt ; nop } bundle. */
416#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL 355#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
417 356
418 357
419#define TILE_ELF_MACHINE_CODE EM_TILEPRO 358#define TILE_ELF_MACHINE_CODE EM_TILE64
420 359
421#define TILE_ELF_NAME "elf32-tilepro" 360#define TILE_ELF_NAME "elf32-tile64"
422 361
423 362
424static __inline unsigned int 363static __inline unsigned int
425get_BrOff_SN(tile_bundle_bits num) 364get_BFEnd_X0(tilegx_bundle_bits num)
426{ 365{
427 const unsigned int n = (unsigned int)num; 366 const unsigned int n = (unsigned int)num;
428 return (((n >> 0)) & 0x3ff); 367 return (((n >> 12)) & 0x3f);
429} 368}
430 369
431static __inline unsigned int 370static __inline unsigned int
432get_BrOff_X1(tile_bundle_bits n) 371get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
433{ 372{
434 return (((unsigned int)(n >> 43)) & 0x00007fff) | 373 const unsigned int n = (unsigned int)num;
435 (((unsigned int)(n >> 20)) & 0x00018000); 374 return (((n >> 24)) & 0xf);
436} 375}
437 376
438static __inline unsigned int 377static __inline unsigned int
439get_BrType_X1(tile_bundle_bits n) 378get_BFStart_X0(tilegx_bundle_bits num)
440{ 379{
441 return (((unsigned int)(n >> 31)) & 0xf); 380 const unsigned int n = (unsigned int)num;
381 return (((n >> 18)) & 0x3f);
442} 382}
443 383
444static __inline unsigned int 384static __inline unsigned int
445get_Dest_Imm8_X1(tile_bundle_bits n) 385get_BrOff_X1(tilegx_bundle_bits n)
446{ 386{
447 return (((unsigned int)(n >> 31)) & 0x0000003f) | 387 return (((unsigned int)(n >> 31)) & 0x0000003f) |
448 (((unsigned int)(n >> 43)) & 0x000000c0); 388 (((unsigned int)(n >> 37)) & 0x0001ffc0);
449} 389}
450 390
451static __inline unsigned int 391static __inline unsigned int
452get_Dest_SN(tile_bundle_bits num) 392get_BrType_X1(tilegx_bundle_bits n)
453{ 393{
454 const unsigned int n = (unsigned int)num; 394 return (((unsigned int)(n >> 54)) & 0x1f);
455 return (((n >> 2)) & 0x3);
456} 395}
457 396
458static __inline unsigned int 397static __inline unsigned int
459get_Dest_X0(tile_bundle_bits num) 398get_Dest_Imm8_X1(tilegx_bundle_bits n)
399{
400 return (((unsigned int)(n >> 31)) & 0x0000003f) |
401 (((unsigned int)(n >> 43)) & 0x000000c0);
402}
403
404static __inline unsigned int
405get_Dest_X0(tilegx_bundle_bits num)
460{ 406{
461 const unsigned int n = (unsigned int)num; 407 const unsigned int n = (unsigned int)num;
462 return (((n >> 0)) & 0x3f); 408 return (((n >> 0)) & 0x3f);
463} 409}
464 410
465static __inline unsigned int 411static __inline unsigned int
466get_Dest_X1(tile_bundle_bits n) 412get_Dest_X1(tilegx_bundle_bits n)
467{ 413{
468 return (((unsigned int)(n >> 31)) & 0x3f); 414 return (((unsigned int)(n >> 31)) & 0x3f);
469} 415}
470 416
471static __inline unsigned int 417static __inline unsigned int
472get_Dest_Y0(tile_bundle_bits num) 418get_Dest_Y0(tilegx_bundle_bits num)
473{ 419{
474 const unsigned int n = (unsigned int)num; 420 const unsigned int n = (unsigned int)num;
475 return (((n >> 0)) & 0x3f); 421 return (((n >> 0)) & 0x3f);
476} 422}
477 423
478static __inline unsigned int 424static __inline unsigned int
479get_Dest_Y1(tile_bundle_bits n) 425get_Dest_Y1(tilegx_bundle_bits n)
480{ 426{
481 return (((unsigned int)(n >> 31)) & 0x3f); 427 return (((unsigned int)(n >> 31)) & 0x3f);
482} 428}
483 429
484static __inline unsigned int 430static __inline unsigned int
485get_Imm16_X0(tile_bundle_bits num) 431get_Imm16_X0(tilegx_bundle_bits num)
486{ 432{
487 const unsigned int n = (unsigned int)num; 433 const unsigned int n = (unsigned int)num;
488 return (((n >> 12)) & 0xffff); 434 return (((n >> 12)) & 0xffff);
489} 435}
490 436
491static __inline unsigned int 437static __inline unsigned int
492get_Imm16_X1(tile_bundle_bits n) 438get_Imm16_X1(tilegx_bundle_bits n)
493{ 439{
494 return (((unsigned int)(n >> 43)) & 0xffff); 440 return (((unsigned int)(n >> 43)) & 0xffff);
495} 441}
496 442
497static __inline unsigned int 443static __inline unsigned int
498get_Imm8_SN(tile_bundle_bits num) 444get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
499{
500 const unsigned int n = (unsigned int)num;
501 return (((n >> 0)) & 0xff);
502}
503
504static __inline unsigned int
505get_Imm8_X0(tile_bundle_bits num)
506{ 445{
507 const unsigned int n = (unsigned int)num; 446 const unsigned int n = (unsigned int)num;
508 return (((n >> 12)) & 0xff); 447 return (((n >> 20)) & 0xff);
509} 448}
510 449
511static __inline unsigned int 450static __inline unsigned int
512get_Imm8_X1(tile_bundle_bits n) 451get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
513{ 452{
514 return (((unsigned int)(n >> 43)) & 0xff); 453 return (((unsigned int)(n >> 51)) & 0xff);
515} 454}
516 455
517static __inline unsigned int 456static __inline unsigned int
518get_Imm8_Y0(tile_bundle_bits num) 457get_Imm8_X0(tilegx_bundle_bits num)
519{ 458{
520 const unsigned int n = (unsigned int)num; 459 const unsigned int n = (unsigned int)num;
521 return (((n >> 12)) & 0xff); 460 return (((n >> 12)) & 0xff);
522} 461}
523 462
524static __inline unsigned int 463static __inline unsigned int
525get_Imm8_Y1(tile_bundle_bits n) 464get_Imm8_X1(tilegx_bundle_bits n)
526{ 465{
527 return (((unsigned int)(n >> 43)) & 0xff); 466 return (((unsigned int)(n >> 43)) & 0xff);
528} 467}
529 468
530static __inline unsigned int 469static __inline unsigned int
531get_ImmOpcodeExtension_X0(tile_bundle_bits num) 470get_Imm8_Y0(tilegx_bundle_bits num)
532{
533 const unsigned int n = (unsigned int)num;
534 return (((n >> 20)) & 0x7f);
535}
536
537static __inline unsigned int
538get_ImmOpcodeExtension_X1(tile_bundle_bits n)
539{
540 return (((unsigned int)(n >> 51)) & 0x7f);
541}
542
543static __inline unsigned int
544get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
545{ 471{
546 const unsigned int n = (unsigned int)num; 472 const unsigned int n = (unsigned int)num;
547 return (((n >> 8)) & 0x3); 473 return (((n >> 12)) & 0xff);
548}
549
550static __inline unsigned int
551get_JOffLong_X1(tile_bundle_bits n)
552{
553 return (((unsigned int)(n >> 43)) & 0x00007fff) |
554 (((unsigned int)(n >> 20)) & 0x00018000) |
555 (((unsigned int)(n >> 14)) & 0x001e0000) |
556 (((unsigned int)(n >> 16)) & 0x07e00000) |
557 (((unsigned int)(n >> 31)) & 0x18000000);
558}
559
560static __inline unsigned int
561get_JOff_X1(tile_bundle_bits n)
562{
563 return (((unsigned int)(n >> 43)) & 0x00007fff) |
564 (((unsigned int)(n >> 20)) & 0x00018000) |
565 (((unsigned int)(n >> 14)) & 0x001e0000) |
566 (((unsigned int)(n >> 16)) & 0x07e00000) |
567 (((unsigned int)(n >> 31)) & 0x08000000);
568}
569
570static __inline unsigned int
571get_MF_Imm15_X1(tile_bundle_bits n)
572{
573 return (((unsigned int)(n >> 37)) & 0x00003fff) |
574 (((unsigned int)(n >> 44)) & 0x00004000);
575} 474}
576 475
577static __inline unsigned int 476static __inline unsigned int
578get_MMEnd_X0(tile_bundle_bits num) 477get_Imm8_Y1(tilegx_bundle_bits n)
579{ 478{
580 const unsigned int n = (unsigned int)num; 479 return (((unsigned int)(n >> 43)) & 0xff);
581 return (((n >> 18)) & 0x1f);
582} 480}
583 481
584static __inline unsigned int 482static __inline unsigned int
585get_MMEnd_X1(tile_bundle_bits n) 483get_JumpOff_X1(tilegx_bundle_bits n)
586{ 484{
587 return (((unsigned int)(n >> 49)) & 0x1f); 485 return (((unsigned int)(n >> 31)) & 0x7ffffff);
588} 486}
589 487
590static __inline unsigned int 488static __inline unsigned int
591get_MMStart_X0(tile_bundle_bits num) 489get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
592{ 490{
593 const unsigned int n = (unsigned int)num; 491 return (((unsigned int)(n >> 58)) & 0x1);
594 return (((n >> 23)) & 0x1f);
595} 492}
596 493
597static __inline unsigned int 494static __inline unsigned int
598get_MMStart_X1(tile_bundle_bits n) 495get_MF_Imm14_X1(tilegx_bundle_bits n)
599{ 496{
600 return (((unsigned int)(n >> 54)) & 0x1f); 497 return (((unsigned int)(n >> 37)) & 0x3fff);
601} 498}
602 499
603static __inline unsigned int 500static __inline unsigned int
604get_MT_Imm15_X1(tile_bundle_bits n) 501get_MT_Imm14_X1(tilegx_bundle_bits n)
605{ 502{
606 return (((unsigned int)(n >> 31)) & 0x0000003f) | 503 return (((unsigned int)(n >> 31)) & 0x0000003f) |
607 (((unsigned int)(n >> 37)) & 0x00003fc0) | 504 (((unsigned int)(n >> 37)) & 0x00003fc0);
608 (((unsigned int)(n >> 44)) & 0x00004000);
609}
610
611static __inline unsigned int
612get_Mode(tile_bundle_bits n)
613{
614 return (((unsigned int)(n >> 63)) & 0x1);
615}
616
617static __inline unsigned int
618get_NoRegOpcodeExtension_SN(tile_bundle_bits num)
619{
620 const unsigned int n = (unsigned int)num;
621 return (((n >> 0)) & 0xf);
622} 505}
623 506
624static __inline unsigned int 507static __inline unsigned int
625get_Opcode_SN(tile_bundle_bits num) 508get_Mode(tilegx_bundle_bits n)
626{ 509{
627 const unsigned int n = (unsigned int)num; 510 return (((unsigned int)(n >> 62)) & 0x3);
628 return (((n >> 10)) & 0x3f);
629} 511}
630 512
631static __inline unsigned int 513static __inline unsigned int
632get_Opcode_X0(tile_bundle_bits num) 514get_Opcode_X0(tilegx_bundle_bits num)
633{ 515{
634 const unsigned int n = (unsigned int)num; 516 const unsigned int n = (unsigned int)num;
635 return (((n >> 28)) & 0x7); 517 return (((n >> 28)) & 0x7);
636} 518}
637 519
638static __inline unsigned int 520static __inline unsigned int
639get_Opcode_X1(tile_bundle_bits n) 521get_Opcode_X1(tilegx_bundle_bits n)
640{ 522{
641 return (((unsigned int)(n >> 59)) & 0xf); 523 return (((unsigned int)(n >> 59)) & 0x7);
642} 524}
643 525
644static __inline unsigned int 526static __inline unsigned int
645get_Opcode_Y0(tile_bundle_bits num) 527get_Opcode_Y0(tilegx_bundle_bits num)
646{ 528{
647 const unsigned int n = (unsigned int)num; 529 const unsigned int n = (unsigned int)num;
648 return (((n >> 27)) & 0xf); 530 return (((n >> 27)) & 0xf);
649} 531}
650 532
651static __inline unsigned int 533static __inline unsigned int
652get_Opcode_Y1(tile_bundle_bits n) 534get_Opcode_Y1(tilegx_bundle_bits n)
653{ 535{
654 return (((unsigned int)(n >> 59)) & 0xf); 536 return (((unsigned int)(n >> 58)) & 0xf);
655} 537}
656 538
657static __inline unsigned int 539static __inline unsigned int
658get_Opcode_Y2(tile_bundle_bits n) 540get_Opcode_Y2(tilegx_bundle_bits n)
659{ 541{
660 return (((unsigned int)(n >> 56)) & 0x7); 542 return (((n >> 26)) & 0x00000001) |
661} 543 (((unsigned int)(n >> 56)) & 0x00000002);
662
663static __inline unsigned int
664get_RROpcodeExtension_SN(tile_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 4)) & 0xf);
668} 544}
669 545
670static __inline unsigned int 546static __inline unsigned int
671get_RRROpcodeExtension_X0(tile_bundle_bits num) 547get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
672{ 548{
673 const unsigned int n = (unsigned int)num; 549 const unsigned int n = (unsigned int)num;
674 return (((n >> 18)) & 0x1ff); 550 return (((n >> 18)) & 0x3ff);
675} 551}
676 552
677static __inline unsigned int 553static __inline unsigned int
678get_RRROpcodeExtension_X1(tile_bundle_bits n) 554get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
679{ 555{
680 return (((unsigned int)(n >> 49)) & 0x1ff); 556 return (((unsigned int)(n >> 49)) & 0x3ff);
681} 557}
682 558
683static __inline unsigned int 559static __inline unsigned int
684get_RRROpcodeExtension_Y0(tile_bundle_bits num) 560get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
685{ 561{
686 const unsigned int n = (unsigned int)num; 562 const unsigned int n = (unsigned int)num;
687 return (((n >> 18)) & 0x3); 563 return (((n >> 18)) & 0x3);
688} 564}
689 565
690static __inline unsigned int 566static __inline unsigned int
691get_RRROpcodeExtension_Y1(tile_bundle_bits n) 567get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
692{ 568{
693 return (((unsigned int)(n >> 49)) & 0x3); 569 return (((unsigned int)(n >> 49)) & 0x3);
694} 570}
695 571
696static __inline unsigned int 572static __inline unsigned int
697get_RouteOpcodeExtension_SN(tile_bundle_bits num) 573get_ShAmt_X0(tilegx_bundle_bits num)
698{
699 const unsigned int n = (unsigned int)num;
700 return (((n >> 0)) & 0x3ff);
701}
702
703static __inline unsigned int
704get_S_X0(tile_bundle_bits num)
705{ 574{
706 const unsigned int n = (unsigned int)num; 575 const unsigned int n = (unsigned int)num;
707 return (((n >> 27)) & 0x1); 576 return (((n >> 12)) & 0x3f);
708} 577}
709 578
710static __inline unsigned int 579static __inline unsigned int
711get_S_X1(tile_bundle_bits n) 580get_ShAmt_X1(tilegx_bundle_bits n)
712{ 581{
713 return (((unsigned int)(n >> 58)) & 0x1); 582 return (((unsigned int)(n >> 43)) & 0x3f);
714} 583}
715 584
716static __inline unsigned int 585static __inline unsigned int
717get_ShAmt_X0(tile_bundle_bits num) 586get_ShAmt_Y0(tilegx_bundle_bits num)
718{ 587{
719 const unsigned int n = (unsigned int)num; 588 const unsigned int n = (unsigned int)num;
720 return (((n >> 12)) & 0x1f); 589 return (((n >> 12)) & 0x3f);
721} 590}
722 591
723static __inline unsigned int 592static __inline unsigned int
724get_ShAmt_X1(tile_bundle_bits n) 593get_ShAmt_Y1(tilegx_bundle_bits n)
725{ 594{
726 return (((unsigned int)(n >> 43)) & 0x1f); 595 return (((unsigned int)(n >> 43)) & 0x3f);
727} 596}
728 597
729static __inline unsigned int 598static __inline unsigned int
730get_ShAmt_Y0(tile_bundle_bits num) 599get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
731{ 600{
732 const unsigned int n = (unsigned int)num; 601 const unsigned int n = (unsigned int)num;
733 return (((n >> 12)) & 0x1f); 602 return (((n >> 18)) & 0x3ff);
734} 603}
735 604
736static __inline unsigned int 605static __inline unsigned int
737get_ShAmt_Y1(tile_bundle_bits n) 606get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
738{ 607{
739 return (((unsigned int)(n >> 43)) & 0x1f); 608 return (((unsigned int)(n >> 49)) & 0x3ff);
740} 609}
741 610
742static __inline unsigned int 611static __inline unsigned int
743get_SrcA_X0(tile_bundle_bits num) 612get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
744{ 613{
745 const unsigned int n = (unsigned int)num; 614 const unsigned int n = (unsigned int)num;
746 return (((n >> 6)) & 0x3f); 615 return (((n >> 18)) & 0x3);
747} 616}
748 617
749static __inline unsigned int 618static __inline unsigned int
750get_SrcA_X1(tile_bundle_bits n) 619get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
751{ 620{
752 return (((unsigned int)(n >> 37)) & 0x3f); 621 return (((unsigned int)(n >> 49)) & 0x3);
753} 622}
754 623
755static __inline unsigned int 624static __inline unsigned int
756get_SrcA_Y0(tile_bundle_bits num) 625get_SrcA_X0(tilegx_bundle_bits num)
757{ 626{
758 const unsigned int n = (unsigned int)num; 627 const unsigned int n = (unsigned int)num;
759 return (((n >> 6)) & 0x3f); 628 return (((n >> 6)) & 0x3f);
760} 629}
761 630
762static __inline unsigned int 631static __inline unsigned int
763get_SrcA_Y1(tile_bundle_bits n) 632get_SrcA_X1(tilegx_bundle_bits n)
764{ 633{
765 return (((unsigned int)(n >> 37)) & 0x3f); 634 return (((unsigned int)(n >> 37)) & 0x3f);
766} 635}
767 636
768static __inline unsigned int 637static __inline unsigned int
769get_SrcA_Y2(tile_bundle_bits n) 638get_SrcA_Y0(tilegx_bundle_bits num)
770{ 639{
771 return (((n >> 26)) & 0x00000001) | 640 const unsigned int n = (unsigned int)num;
772 (((unsigned int)(n >> 50)) & 0x0000003e); 641 return (((n >> 6)) & 0x3f);
773} 642}
774 643
775static __inline unsigned int 644static __inline unsigned int
776get_SrcBDest_Y2(tile_bundle_bits num) 645get_SrcA_Y1(tilegx_bundle_bits n)
777{ 646{
778 const unsigned int n = (unsigned int)num; 647 return (((unsigned int)(n >> 37)) & 0x3f);
779 return (((n >> 20)) & 0x3f);
780} 648}
781 649
782static __inline unsigned int 650static __inline unsigned int
783get_SrcB_X0(tile_bundle_bits num) 651get_SrcA_Y2(tilegx_bundle_bits num)
784{ 652{
785 const unsigned int n = (unsigned int)num; 653 const unsigned int n = (unsigned int)num;
786 return (((n >> 12)) & 0x3f); 654 return (((n >> 20)) & 0x3f);
787} 655}
788 656
789static __inline unsigned int 657static __inline unsigned int
790get_SrcB_X1(tile_bundle_bits n) 658get_SrcBDest_Y2(tilegx_bundle_bits n)
791{ 659{
792 return (((unsigned int)(n >> 43)) & 0x3f); 660 return (((unsigned int)(n >> 51)) & 0x3f);
793} 661}
794 662
795static __inline unsigned int 663static __inline unsigned int
796get_SrcB_Y0(tile_bundle_bits num) 664get_SrcB_X0(tilegx_bundle_bits num)
797{ 665{
798 const unsigned int n = (unsigned int)num; 666 const unsigned int n = (unsigned int)num;
799 return (((n >> 12)) & 0x3f); 667 return (((n >> 12)) & 0x3f);
800} 668}
801 669
802static __inline unsigned int 670static __inline unsigned int
803get_SrcB_Y1(tile_bundle_bits n) 671get_SrcB_X1(tilegx_bundle_bits n)
804{ 672{
805 return (((unsigned int)(n >> 43)) & 0x3f); 673 return (((unsigned int)(n >> 43)) & 0x3f);
806} 674}
807 675
808static __inline unsigned int 676static __inline unsigned int
809get_Src_SN(tile_bundle_bits num) 677get_SrcB_Y0(tilegx_bundle_bits num)
810{
811 const unsigned int n = (unsigned int)num;
812 return (((n >> 0)) & 0x3);
813}
814
815static __inline unsigned int
816get_UnOpcodeExtension_X0(tile_bundle_bits num)
817{
818 const unsigned int n = (unsigned int)num;
819 return (((n >> 12)) & 0x1f);
820}
821
822static __inline unsigned int
823get_UnOpcodeExtension_X1(tile_bundle_bits n)
824{
825 return (((unsigned int)(n >> 43)) & 0x1f);
826}
827
828static __inline unsigned int
829get_UnOpcodeExtension_Y0(tile_bundle_bits num)
830{ 678{
831 const unsigned int n = (unsigned int)num; 679 const unsigned int n = (unsigned int)num;
832 return (((n >> 12)) & 0x1f); 680 return (((n >> 12)) & 0x3f);
833} 681}
834 682
835static __inline unsigned int 683static __inline unsigned int
836get_UnOpcodeExtension_Y1(tile_bundle_bits n) 684get_SrcB_Y1(tilegx_bundle_bits n)
837{ 685{
838 return (((unsigned int)(n >> 43)) & 0x1f); 686 return (((unsigned int)(n >> 43)) & 0x3f);
839} 687}
840 688
841static __inline unsigned int 689static __inline unsigned int
842get_UnShOpcodeExtension_X0(tile_bundle_bits num) 690get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
843{ 691{
844 const unsigned int n = (unsigned int)num; 692 const unsigned int n = (unsigned int)num;
845 return (((n >> 17)) & 0x3ff); 693 return (((n >> 12)) & 0x3f);
846} 694}
847 695
848static __inline unsigned int 696static __inline unsigned int
849get_UnShOpcodeExtension_X1(tile_bundle_bits n) 697get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
850{ 698{
851 return (((unsigned int)(n >> 48)) & 0x3ff); 699 return (((unsigned int)(n >> 43)) & 0x3f);
852} 700}
853 701
854static __inline unsigned int 702static __inline unsigned int
855get_UnShOpcodeExtension_Y0(tile_bundle_bits num) 703get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
856{ 704{
857 const unsigned int n = (unsigned int)num; 705 const unsigned int n = (unsigned int)num;
858 return (((n >> 17)) & 0x7); 706 return (((n >> 12)) & 0x3f);
859} 707}
860 708
861static __inline unsigned int 709static __inline unsigned int
862get_UnShOpcodeExtension_Y1(tile_bundle_bits n) 710get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
863{ 711{
864 return (((unsigned int)(n >> 48)) & 0x7); 712 return (((unsigned int)(n >> 43)) & 0x3f);
865} 713}
866 714
867 715
@@ -874,546 +722,441 @@ sign_extend(int n, int num_bits)
874 722
875 723
876 724
877static __inline tile_bundle_bits 725static __inline tilegx_bundle_bits
878create_BrOff_SN(int num) 726create_BFEnd_X0(int num)
879{ 727{
880 const unsigned int n = (unsigned int)num; 728 const unsigned int n = (unsigned int)num;
881 return ((n & 0x3ff) << 0); 729 return ((n & 0x3f) << 12);
882} 730}
883 731
884static __inline tile_bundle_bits 732static __inline tilegx_bundle_bits
885create_BrOff_X1(int num) 733create_BFOpcodeExtension_X0(int num)
886{ 734{
887 const unsigned int n = (unsigned int)num; 735 const unsigned int n = (unsigned int)num;
888 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | 736 return ((n & 0xf) << 24);
889 (((tile_bundle_bits)(n & 0x00018000)) << 20);
890} 737}
891 738
892static __inline tile_bundle_bits 739static __inline tilegx_bundle_bits
893create_BrType_X1(int num) 740create_BFStart_X0(int num)
894{ 741{
895 const unsigned int n = (unsigned int)num; 742 const unsigned int n = (unsigned int)num;
896 return (((tile_bundle_bits)(n & 0xf)) << 31); 743 return ((n & 0x3f) << 18);
897} 744}
898 745
899static __inline tile_bundle_bits 746static __inline tilegx_bundle_bits
900create_Dest_Imm8_X1(int num) 747create_BrOff_X1(int num)
901{ 748{
902 const unsigned int n = (unsigned int)num; 749 const unsigned int n = (unsigned int)num;
903 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | 750 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
904 (((tile_bundle_bits)(n & 0x000000c0)) << 43); 751 (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
905} 752}
906 753
907static __inline tile_bundle_bits 754static __inline tilegx_bundle_bits
908create_Dest_SN(int num) 755create_BrType_X1(int num)
909{ 756{
910 const unsigned int n = (unsigned int)num; 757 const unsigned int n = (unsigned int)num;
911 return ((n & 0x3) << 2); 758 return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
912} 759}
913 760
914static __inline tile_bundle_bits 761static __inline tilegx_bundle_bits
762create_Dest_Imm8_X1(int num)
763{
764 const unsigned int n = (unsigned int)num;
765 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
766 (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
767}
768
769static __inline tilegx_bundle_bits
915create_Dest_X0(int num) 770create_Dest_X0(int num)
916{ 771{
917 const unsigned int n = (unsigned int)num; 772 const unsigned int n = (unsigned int)num;
918 return ((n & 0x3f) << 0); 773 return ((n & 0x3f) << 0);
919} 774}
920 775
921static __inline tile_bundle_bits 776static __inline tilegx_bundle_bits
922create_Dest_X1(int num) 777create_Dest_X1(int num)
923{ 778{
924 const unsigned int n = (unsigned int)num; 779 const unsigned int n = (unsigned int)num;
925 return (((tile_bundle_bits)(n & 0x3f)) << 31); 780 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
926} 781}
927 782
928static __inline tile_bundle_bits 783static __inline tilegx_bundle_bits
929create_Dest_Y0(int num) 784create_Dest_Y0(int num)
930{ 785{
931 const unsigned int n = (unsigned int)num; 786 const unsigned int n = (unsigned int)num;
932 return ((n & 0x3f) << 0); 787 return ((n & 0x3f) << 0);
933} 788}
934 789
935static __inline tile_bundle_bits 790static __inline tilegx_bundle_bits
936create_Dest_Y1(int num) 791create_Dest_Y1(int num)
937{ 792{
938 const unsigned int n = (unsigned int)num; 793 const unsigned int n = (unsigned int)num;
939 return (((tile_bundle_bits)(n & 0x3f)) << 31); 794 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
940} 795}
941 796
942static __inline tile_bundle_bits 797static __inline tilegx_bundle_bits
943create_Imm16_X0(int num) 798create_Imm16_X0(int num)
944{ 799{
945 const unsigned int n = (unsigned int)num; 800 const unsigned int n = (unsigned int)num;
946 return ((n & 0xffff) << 12); 801 return ((n & 0xffff) << 12);
947} 802}
948 803
949static __inline tile_bundle_bits 804static __inline tilegx_bundle_bits
950create_Imm16_X1(int num) 805create_Imm16_X1(int num)
951{ 806{
952 const unsigned int n = (unsigned int)num; 807 const unsigned int n = (unsigned int)num;
953 return (((tile_bundle_bits)(n & 0xffff)) << 43); 808 return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
809}
810
811static __inline tilegx_bundle_bits
812create_Imm8OpcodeExtension_X0(int num)
813{
814 const unsigned int n = (unsigned int)num;
815 return ((n & 0xff) << 20);
954} 816}
955 817
956static __inline tile_bundle_bits 818static __inline tilegx_bundle_bits
957create_Imm8_SN(int num) 819create_Imm8OpcodeExtension_X1(int num)
958{ 820{
959 const unsigned int n = (unsigned int)num; 821 const unsigned int n = (unsigned int)num;
960 return ((n & 0xff) << 0); 822 return (((tilegx_bundle_bits)(n & 0xff)) << 51);
961} 823}
962 824
963static __inline tile_bundle_bits 825static __inline tilegx_bundle_bits
964create_Imm8_X0(int num) 826create_Imm8_X0(int num)
965{ 827{
966 const unsigned int n = (unsigned int)num; 828 const unsigned int n = (unsigned int)num;
967 return ((n & 0xff) << 12); 829 return ((n & 0xff) << 12);
968} 830}
969 831
970static __inline tile_bundle_bits 832static __inline tilegx_bundle_bits
971create_Imm8_X1(int num) 833create_Imm8_X1(int num)
972{ 834{
973 const unsigned int n = (unsigned int)num; 835 const unsigned int n = (unsigned int)num;
974 return (((tile_bundle_bits)(n & 0xff)) << 43); 836 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
975} 837}
976 838
977static __inline tile_bundle_bits 839static __inline tilegx_bundle_bits
978create_Imm8_Y0(int num) 840create_Imm8_Y0(int num)
979{ 841{
980 const unsigned int n = (unsigned int)num; 842 const unsigned int n = (unsigned int)num;
981 return ((n & 0xff) << 12); 843 return ((n & 0xff) << 12);
982} 844}
983 845
984static __inline tile_bundle_bits 846static __inline tilegx_bundle_bits
985create_Imm8_Y1(int num) 847create_Imm8_Y1(int num)
986{ 848{
987 const unsigned int n = (unsigned int)num; 849 const unsigned int n = (unsigned int)num;
988 return (((tile_bundle_bits)(n & 0xff)) << 43); 850 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
989}
990
991static __inline tile_bundle_bits
992create_ImmOpcodeExtension_X0(int num)
993{
994 const unsigned int n = (unsigned int)num;
995 return ((n & 0x7f) << 20);
996}
997
998static __inline tile_bundle_bits
999create_ImmOpcodeExtension_X1(int num)
1000{
1001 const unsigned int n = (unsigned int)num;
1002 return (((tile_bundle_bits)(n & 0x7f)) << 51);
1003}
1004
1005static __inline tile_bundle_bits
1006create_ImmRROpcodeExtension_SN(int num)
1007{
1008 const unsigned int n = (unsigned int)num;
1009 return ((n & 0x3) << 8);
1010}
1011
1012static __inline tile_bundle_bits
1013create_JOffLong_X1(int num)
1014{
1015 const unsigned int n = (unsigned int)num;
1016 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1017 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1018 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1019 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1020 (((tile_bundle_bits)(n & 0x18000000)) << 31);
1021}
1022
1023static __inline tile_bundle_bits
1024create_JOff_X1(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1028 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1029 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1030 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1031 (((tile_bundle_bits)(n & 0x08000000)) << 31);
1032}
1033
1034static __inline tile_bundle_bits
1035create_MF_Imm15_X1(int num)
1036{
1037 const unsigned int n = (unsigned int)num;
1038 return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
1039 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1040} 851}
1041 852
1042static __inline tile_bundle_bits 853static __inline tilegx_bundle_bits
1043create_MMEnd_X0(int num) 854create_JumpOff_X1(int num)
1044{ 855{
1045 const unsigned int n = (unsigned int)num; 856 const unsigned int n = (unsigned int)num;
1046 return ((n & 0x1f) << 18); 857 return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
1047} 858}
1048 859
1049static __inline tile_bundle_bits 860static __inline tilegx_bundle_bits
1050create_MMEnd_X1(int num) 861create_JumpOpcodeExtension_X1(int num)
1051{ 862{
1052 const unsigned int n = (unsigned int)num; 863 const unsigned int n = (unsigned int)num;
1053 return (((tile_bundle_bits)(n & 0x1f)) << 49); 864 return (((tilegx_bundle_bits)(n & 0x1)) << 58);
1054} 865}
1055 866
1056static __inline tile_bundle_bits 867static __inline tilegx_bundle_bits
1057create_MMStart_X0(int num) 868create_MF_Imm14_X1(int num)
1058{ 869{
1059 const unsigned int n = (unsigned int)num; 870 const unsigned int n = (unsigned int)num;
1060 return ((n & 0x1f) << 23); 871 return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
1061} 872}
1062 873
1063static __inline tile_bundle_bits 874static __inline tilegx_bundle_bits
1064create_MMStart_X1(int num) 875create_MT_Imm14_X1(int num)
1065{ 876{
1066 const unsigned int n = (unsigned int)num; 877 const unsigned int n = (unsigned int)num;
1067 return (((tile_bundle_bits)(n & 0x1f)) << 54); 878 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
879 (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
1068} 880}
1069 881
1070static __inline tile_bundle_bits 882static __inline tilegx_bundle_bits
1071create_MT_Imm15_X1(int num)
1072{
1073 const unsigned int n = (unsigned int)num;
1074 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
1075 (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
1076 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1077}
1078
1079static __inline tile_bundle_bits
1080create_Mode(int num) 883create_Mode(int num)
1081{ 884{
1082 const unsigned int n = (unsigned int)num; 885 const unsigned int n = (unsigned int)num;
1083 return (((tile_bundle_bits)(n & 0x1)) << 63); 886 return (((tilegx_bundle_bits)(n & 0x3)) << 62);
1084}
1085
1086static __inline tile_bundle_bits
1087create_NoRegOpcodeExtension_SN(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return ((n & 0xf) << 0);
1091}
1092
1093static __inline tile_bundle_bits
1094create_Opcode_SN(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 10);
1098} 887}
1099 888
1100static __inline tile_bundle_bits 889static __inline tilegx_bundle_bits
1101create_Opcode_X0(int num) 890create_Opcode_X0(int num)
1102{ 891{
1103 const unsigned int n = (unsigned int)num; 892 const unsigned int n = (unsigned int)num;
1104 return ((n & 0x7) << 28); 893 return ((n & 0x7) << 28);
1105} 894}
1106 895
1107static __inline tile_bundle_bits 896static __inline tilegx_bundle_bits
1108create_Opcode_X1(int num) 897create_Opcode_X1(int num)
1109{ 898{
1110 const unsigned int n = (unsigned int)num; 899 const unsigned int n = (unsigned int)num;
1111 return (((tile_bundle_bits)(n & 0xf)) << 59); 900 return (((tilegx_bundle_bits)(n & 0x7)) << 59);
1112} 901}
1113 902
1114static __inline tile_bundle_bits 903static __inline tilegx_bundle_bits
1115create_Opcode_Y0(int num) 904create_Opcode_Y0(int num)
1116{ 905{
1117 const unsigned int n = (unsigned int)num; 906 const unsigned int n = (unsigned int)num;
1118 return ((n & 0xf) << 27); 907 return ((n & 0xf) << 27);
1119} 908}
1120 909
1121static __inline tile_bundle_bits 910static __inline tilegx_bundle_bits
1122create_Opcode_Y1(int num) 911create_Opcode_Y1(int num)
1123{ 912{
1124 const unsigned int n = (unsigned int)num; 913 const unsigned int n = (unsigned int)num;
1125 return (((tile_bundle_bits)(n & 0xf)) << 59); 914 return (((tilegx_bundle_bits)(n & 0xf)) << 58);
1126} 915}
1127 916
1128static __inline tile_bundle_bits 917static __inline tilegx_bundle_bits
1129create_Opcode_Y2(int num) 918create_Opcode_Y2(int num)
1130{ 919{
1131 const unsigned int n = (unsigned int)num; 920 const unsigned int n = (unsigned int)num;
1132 return (((tile_bundle_bits)(n & 0x7)) << 56); 921 return ((n & 0x00000001) << 26) |
1133} 922 (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
1134
1135static __inline tile_bundle_bits
1136create_RROpcodeExtension_SN(int num)
1137{
1138 const unsigned int n = (unsigned int)num;
1139 return ((n & 0xf) << 4);
1140} 923}
1141 924
1142static __inline tile_bundle_bits 925static __inline tilegx_bundle_bits
1143create_RRROpcodeExtension_X0(int num) 926create_RRROpcodeExtension_X0(int num)
1144{ 927{
1145 const unsigned int n = (unsigned int)num; 928 const unsigned int n = (unsigned int)num;
1146 return ((n & 0x1ff) << 18); 929 return ((n & 0x3ff) << 18);
1147} 930}
1148 931
1149static __inline tile_bundle_bits 932static __inline tilegx_bundle_bits
1150create_RRROpcodeExtension_X1(int num) 933create_RRROpcodeExtension_X1(int num)
1151{ 934{
1152 const unsigned int n = (unsigned int)num; 935 const unsigned int n = (unsigned int)num;
1153 return (((tile_bundle_bits)(n & 0x1ff)) << 49); 936 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1154} 937}
1155 938
1156static __inline tile_bundle_bits 939static __inline tilegx_bundle_bits
1157create_RRROpcodeExtension_Y0(int num) 940create_RRROpcodeExtension_Y0(int num)
1158{ 941{
1159 const unsigned int n = (unsigned int)num; 942 const unsigned int n = (unsigned int)num;
1160 return ((n & 0x3) << 18); 943 return ((n & 0x3) << 18);
1161} 944}
1162 945
1163static __inline tile_bundle_bits 946static __inline tilegx_bundle_bits
1164create_RRROpcodeExtension_Y1(int num) 947create_RRROpcodeExtension_Y1(int num)
1165{ 948{
1166 const unsigned int n = (unsigned int)num; 949 const unsigned int n = (unsigned int)num;
1167 return (((tile_bundle_bits)(n & 0x3)) << 49); 950 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1168} 951}
1169 952
1170static __inline tile_bundle_bits 953static __inline tilegx_bundle_bits
1171create_RouteOpcodeExtension_SN(int num) 954create_ShAmt_X0(int num)
1172{ 955{
1173 const unsigned int n = (unsigned int)num; 956 const unsigned int n = (unsigned int)num;
1174 return ((n & 0x3ff) << 0); 957 return ((n & 0x3f) << 12);
1175} 958}
1176 959
1177static __inline tile_bundle_bits 960static __inline tilegx_bundle_bits
1178create_S_X0(int num) 961create_ShAmt_X1(int num)
1179{ 962{
1180 const unsigned int n = (unsigned int)num; 963 const unsigned int n = (unsigned int)num;
1181 return ((n & 0x1) << 27); 964 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1182} 965}
1183 966
1184static __inline tile_bundle_bits 967static __inline tilegx_bundle_bits
1185create_S_X1(int num) 968create_ShAmt_Y0(int num)
1186{ 969{
1187 const unsigned int n = (unsigned int)num; 970 const unsigned int n = (unsigned int)num;
1188 return (((tile_bundle_bits)(n & 0x1)) << 58); 971 return ((n & 0x3f) << 12);
1189} 972}
1190 973
1191static __inline tile_bundle_bits 974static __inline tilegx_bundle_bits
1192create_ShAmt_X0(int num) 975create_ShAmt_Y1(int num)
1193{ 976{
1194 const unsigned int n = (unsigned int)num; 977 const unsigned int n = (unsigned int)num;
1195 return ((n & 0x1f) << 12); 978 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1196} 979}
1197 980
1198static __inline tile_bundle_bits 981static __inline tilegx_bundle_bits
1199create_ShAmt_X1(int num) 982create_ShiftOpcodeExtension_X0(int num)
1200{ 983{
1201 const unsigned int n = (unsigned int)num; 984 const unsigned int n = (unsigned int)num;
1202 return (((tile_bundle_bits)(n & 0x1f)) << 43); 985 return ((n & 0x3ff) << 18);
1203} 986}
1204 987
1205static __inline tile_bundle_bits 988static __inline tilegx_bundle_bits
1206create_ShAmt_Y0(int num) 989create_ShiftOpcodeExtension_X1(int num)
1207{ 990{
1208 const unsigned int n = (unsigned int)num; 991 const unsigned int n = (unsigned int)num;
1209 return ((n & 0x1f) << 12); 992 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1210} 993}
1211 994
1212static __inline tile_bundle_bits 995static __inline tilegx_bundle_bits
1213create_ShAmt_Y1(int num) 996create_ShiftOpcodeExtension_Y0(int num)
997{
998 const unsigned int n = (unsigned int)num;
999 return ((n & 0x3) << 18);
1000}
1001
1002static __inline tilegx_bundle_bits
1003create_ShiftOpcodeExtension_Y1(int num)
1214{ 1004{
1215 const unsigned int n = (unsigned int)num; 1005 const unsigned int n = (unsigned int)num;
1216 return (((tile_bundle_bits)(n & 0x1f)) << 43); 1006 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1217} 1007}
1218 1008
1219static __inline tile_bundle_bits 1009static __inline tilegx_bundle_bits
1220create_SrcA_X0(int num) 1010create_SrcA_X0(int num)
1221{ 1011{
1222 const unsigned int n = (unsigned int)num; 1012 const unsigned int n = (unsigned int)num;
1223 return ((n & 0x3f) << 6); 1013 return ((n & 0x3f) << 6);
1224} 1014}
1225 1015
1226static __inline tile_bundle_bits 1016static __inline tilegx_bundle_bits
1227create_SrcA_X1(int num) 1017create_SrcA_X1(int num)
1228{ 1018{
1229 const unsigned int n = (unsigned int)num; 1019 const unsigned int n = (unsigned int)num;
1230 return (((tile_bundle_bits)(n & 0x3f)) << 37); 1020 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1231} 1021}
1232 1022
1233static __inline tile_bundle_bits 1023static __inline tilegx_bundle_bits
1234create_SrcA_Y0(int num) 1024create_SrcA_Y0(int num)
1235{ 1025{
1236 const unsigned int n = (unsigned int)num; 1026 const unsigned int n = (unsigned int)num;
1237 return ((n & 0x3f) << 6); 1027 return ((n & 0x3f) << 6);
1238} 1028}
1239 1029
1240static __inline tile_bundle_bits 1030static __inline tilegx_bundle_bits
1241create_SrcA_Y1(int num) 1031create_SrcA_Y1(int num)
1242{ 1032{
1243 const unsigned int n = (unsigned int)num; 1033 const unsigned int n = (unsigned int)num;
1244 return (((tile_bundle_bits)(n & 0x3f)) << 37); 1034 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1245} 1035}
1246 1036
1247static __inline tile_bundle_bits 1037static __inline tilegx_bundle_bits
1248create_SrcA_Y2(int num) 1038create_SrcA_Y2(int num)
1249{ 1039{
1250 const unsigned int n = (unsigned int)num; 1040 const unsigned int n = (unsigned int)num;
1251 return ((n & 0x00000001) << 26) | 1041 return ((n & 0x3f) << 20);
1252 (((tile_bundle_bits)(n & 0x0000003e)) << 50);
1253} 1042}
1254 1043
1255static __inline tile_bundle_bits 1044static __inline tilegx_bundle_bits
1256create_SrcBDest_Y2(int num) 1045create_SrcBDest_Y2(int num)
1257{ 1046{
1258 const unsigned int n = (unsigned int)num; 1047 const unsigned int n = (unsigned int)num;
1259 return ((n & 0x3f) << 20); 1048 return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
1260} 1049}
1261 1050
1262static __inline tile_bundle_bits 1051static __inline tilegx_bundle_bits
1263create_SrcB_X0(int num) 1052create_SrcB_X0(int num)
1264{ 1053{
1265 const unsigned int n = (unsigned int)num; 1054 const unsigned int n = (unsigned int)num;
1266 return ((n & 0x3f) << 12); 1055 return ((n & 0x3f) << 12);
1267} 1056}
1268 1057
1269static __inline tile_bundle_bits 1058static __inline tilegx_bundle_bits
1270create_SrcB_X1(int num) 1059create_SrcB_X1(int num)
1271{ 1060{
1272 const unsigned int n = (unsigned int)num; 1061 const unsigned int n = (unsigned int)num;
1273 return (((tile_bundle_bits)(n & 0x3f)) << 43); 1062 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1274} 1063}
1275 1064
1276static __inline tile_bundle_bits 1065static __inline tilegx_bundle_bits
1277create_SrcB_Y0(int num) 1066create_SrcB_Y0(int num)
1278{ 1067{
1279 const unsigned int n = (unsigned int)num; 1068 const unsigned int n = (unsigned int)num;
1280 return ((n & 0x3f) << 12); 1069 return ((n & 0x3f) << 12);
1281} 1070}
1282 1071
1283static __inline tile_bundle_bits 1072static __inline tilegx_bundle_bits
1284create_SrcB_Y1(int num) 1073create_SrcB_Y1(int num)
1285{ 1074{
1286 const unsigned int n = (unsigned int)num; 1075 const unsigned int n = (unsigned int)num;
1287 return (((tile_bundle_bits)(n & 0x3f)) << 43); 1076 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1288}
1289
1290static __inline tile_bundle_bits
1291create_Src_SN(int num)
1292{
1293 const unsigned int n = (unsigned int)num;
1294 return ((n & 0x3) << 0);
1295}
1296
1297static __inline tile_bundle_bits
1298create_UnOpcodeExtension_X0(int num)
1299{
1300 const unsigned int n = (unsigned int)num;
1301 return ((n & 0x1f) << 12);
1302}
1303
1304static __inline tile_bundle_bits
1305create_UnOpcodeExtension_X1(int num)
1306{
1307 const unsigned int n = (unsigned int)num;
1308 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1309}
1310
1311static __inline tile_bundle_bits
1312create_UnOpcodeExtension_Y0(int num)
1313{
1314 const unsigned int n = (unsigned int)num;
1315 return ((n & 0x1f) << 12);
1316} 1077}
1317 1078
1318static __inline tile_bundle_bits 1079static __inline tilegx_bundle_bits
1319create_UnOpcodeExtension_Y1(int num) 1080create_UnaryOpcodeExtension_X0(int num)
1320{ 1081{
1321 const unsigned int n = (unsigned int)num; 1082 const unsigned int n = (unsigned int)num;
1322 return (((tile_bundle_bits)(n & 0x1f)) << 43); 1083 return ((n & 0x3f) << 12);
1323}
1324
1325static __inline tile_bundle_bits
1326create_UnShOpcodeExtension_X0(int num)
1327{
1328 const unsigned int n = (unsigned int)num;
1329 return ((n & 0x3ff) << 17);
1330} 1084}
1331 1085
1332static __inline tile_bundle_bits 1086static __inline tilegx_bundle_bits
1333create_UnShOpcodeExtension_X1(int num) 1087create_UnaryOpcodeExtension_X1(int num)
1334{ 1088{
1335 const unsigned int n = (unsigned int)num; 1089 const unsigned int n = (unsigned int)num;
1336 return (((tile_bundle_bits)(n & 0x3ff)) << 48); 1090 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1337} 1091}
1338 1092
1339static __inline tile_bundle_bits 1093static __inline tilegx_bundle_bits
1340create_UnShOpcodeExtension_Y0(int num) 1094create_UnaryOpcodeExtension_Y0(int num)
1341{ 1095{
1342 const unsigned int n = (unsigned int)num; 1096 const unsigned int n = (unsigned int)num;
1343 return ((n & 0x7) << 17); 1097 return ((n & 0x3f) << 12);
1344} 1098}
1345 1099
1346static __inline tile_bundle_bits 1100static __inline tilegx_bundle_bits
1347create_UnShOpcodeExtension_Y1(int num) 1101create_UnaryOpcodeExtension_Y1(int num)
1348{ 1102{
1349 const unsigned int n = (unsigned int)num; 1103 const unsigned int n = (unsigned int)num;
1350 return (((tile_bundle_bits)(n & 0x7)) << 48); 1104 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1351} 1105}
1352 1106
1353 1107
1354
1355typedef enum 1108typedef enum
1356{ 1109{
1357 TILE_PIPELINE_X0, 1110 TILEGX_PIPELINE_X0,
1358 TILE_PIPELINE_X1, 1111 TILEGX_PIPELINE_X1,
1359 TILE_PIPELINE_Y0, 1112 TILEGX_PIPELINE_Y0,
1360 TILE_PIPELINE_Y1, 1113 TILEGX_PIPELINE_Y1,
1361 TILE_PIPELINE_Y2, 1114 TILEGX_PIPELINE_Y2,
1362} tile_pipeline; 1115} tilegx_pipeline;
1363 1116
1364#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1) 1117#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
1365 1118
1366typedef enum 1119typedef enum
1367{ 1120{
1368 TILE_OP_TYPE_REGISTER, 1121 TILEGX_OP_TYPE_REGISTER,
1369 TILE_OP_TYPE_IMMEDIATE, 1122 TILEGX_OP_TYPE_IMMEDIATE,
1370 TILE_OP_TYPE_ADDRESS, 1123 TILEGX_OP_TYPE_ADDRESS,
1371 TILE_OP_TYPE_SPR 1124 TILEGX_OP_TYPE_SPR
1372} tile_operand_type; 1125} tilegx_operand_type;
1373 1126
1374/* This is the bit that determines if a bundle is in the Y encoding. */ 1127/* These are the bits that determine if a bundle is in the X encoding. */
1375#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63) 1128#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
1376 1129
1377enum 1130enum
1378{ 1131{
1379 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 1132 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1380 TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 1133 TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1381 1134
1382 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 1135 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1383 TILE_NUM_PIPELINE_ENCODINGS = 5, 1136 TILEGX_NUM_PIPELINE_ENCODINGS = 5,
1384 1137
1385 /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */ 1138 /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
1386 TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 1139 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1387 1140
1388 /* Instructions take this many bytes. */ 1141 /* Instructions take this many bytes. */
1389 TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES, 1142 TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
1390 1143
1391 /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */ 1144 /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
1392 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 1145 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1393 1146
1394 /* Bundles should be aligned modulo this number of bytes. */ 1147 /* Bundles should be aligned modulo this number of bytes. */
1395 TILE_BUNDLE_ALIGNMENT_IN_BYTES = 1148 TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
1396 (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 1149 (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1397
1398 /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
1399 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
1400
1401 /* Static network instructions take this many bytes. */
1402 TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
1403 (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
1404 1150
1405 /* Number of registers (some are magic, such as network I/O). */ 1151 /* Number of registers (some are magic, such as network I/O). */
1406 TILE_NUM_REGISTERS = 64, 1152 TILEGX_NUM_REGISTERS = 64,
1407
1408 /* Number of static network registers. */
1409 TILE_NUM_SN_REGISTERS = 4
1410}; 1153};
1411 1154
1412 1155
1413struct tile_operand 1156struct tilegx_operand
1414{ 1157{
1415 /* Is this operand a register, immediate or address? */ 1158 /* Is this operand a register, immediate or address? */
1416 tile_operand_type type; 1159 tilegx_operand_type type;
1417 1160
1418 /* The default relocation type for this operand. */ 1161 /* The default relocation type for this operand. */
1419 signed int default_reloc : 16; 1162 signed int default_reloc : 16;
@@ -1437,27 +1180,27 @@ struct tile_operand
1437 unsigned int rightshift : 2; 1180 unsigned int rightshift : 2;
1438 1181
1439 /* Return the bits for this operand to be ORed into an existing bundle. */ 1182 /* Return the bits for this operand to be ORed into an existing bundle. */
1440 tile_bundle_bits (*insert) (int op); 1183 tilegx_bundle_bits (*insert) (int op);
1441 1184
1442 /* Extract this operand and return it. */ 1185 /* Extract this operand and return it. */
1443 unsigned int (*extract) (tile_bundle_bits bundle); 1186 unsigned int (*extract) (tilegx_bundle_bits bundle);
1444}; 1187};
1445 1188
1446 1189
1447extern const struct tile_operand tile_operands[]; 1190extern const struct tilegx_operand tilegx_operands[];
1448 1191
1449/* One finite-state machine per pipe for rapid instruction decoding. */ 1192/* One finite-state machine per pipe for rapid instruction decoding. */
1450extern const unsigned short * const 1193extern const unsigned short * const
1451tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS]; 1194tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
1452 1195
1453 1196
1454struct tile_opcode 1197struct tilegx_opcode
1455{ 1198{
1456 /* The opcode mnemonic, e.g. "add" */ 1199 /* The opcode mnemonic, e.g. "add" */
1457 const char *name; 1200 const char *name;
1458 1201
1459 /* The enum value for this mnemonic. */ 1202 /* The enum value for this mnemonic. */
1460 tile_mnemonic mnemonic; 1203 tilegx_mnemonic mnemonic;
1461 1204
1462 /* A bit mask of which of the five pipes this instruction 1205 /* A bit mask of which of the five pipes this instruction
1463 is compatible with: 1206 is compatible with:
@@ -1478,36 +1221,28 @@ struct tile_opcode
1478 unsigned char can_bundle; 1221 unsigned char can_bundle;
1479 1222
1480 /* The description of the operands. Each of these is an 1223 /* The description of the operands. Each of these is an
1481 * index into the tile_operands[] table. */ 1224 * index into the tilegx_operands[] table. */
1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; 1225 unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
1483 1226
1484}; 1227};
1485 1228
1486extern const struct tile_opcode tile_opcodes[]; 1229extern const struct tilegx_opcode tilegx_opcodes[];
1487
1488 1230
1489/* Used for non-textual disassembly into structs. */ 1231/* Used for non-textual disassembly into structs. */
1490struct tile_decoded_instruction 1232struct tilegx_decoded_instruction
1491{ 1233{
1492 const struct tile_opcode *opcode; 1234 const struct tilegx_opcode *opcode;
1493 const struct tile_operand *operands[TILE_MAX_OPERANDS]; 1235 const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
1494 int operand_values[TILE_MAX_OPERANDS]; 1236 long long operand_values[TILEGX_MAX_OPERANDS];
1495}; 1237};
1496 1238
1497 1239
1498/* Disassemble a bundle into a struct for machine processing. */ 1240/* Disassemble a bundle into a struct for machine processing. */
1499extern int parse_insn_tile(tile_bundle_bits bits, 1241extern int parse_insn_tilegx(tilegx_bundle_bits bits,
1500 unsigned int pc, 1242 unsigned long long pc,
1501 struct tile_decoded_instruction 1243 struct tilegx_decoded_instruction
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1244 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503
1504
1505/* Given a set of bundle bits and a specific pipe, returns which
1506 * instruction the bundle contains in that pipe.
1507 */
1508extern const struct tile_opcode *
1509find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
1510 1245
1511 1246
1512 1247
1513#endif /* opcode_tile_h */ 1248#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
index 227d033b180c..710192869476 100644
--- a/arch/tile/include/asm/opcode_constants_64.h
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -19,462 +19,591 @@
19#define _TILE_OPCODE_CONSTANTS_H 19#define _TILE_OPCODE_CONSTANTS_H
20enum 20enum
21{ 21{
22 ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, 22 ADDI_IMM8_OPCODE_X0 = 1,
23 ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, 23 ADDI_IMM8_OPCODE_X1 = 1,
24 ADDB_SPECIAL_0_OPCODE_X0 = 1, 24 ADDI_OPCODE_Y0 = 0,
25 ADDB_SPECIAL_0_OPCODE_X1 = 1, 25 ADDI_OPCODE_Y1 = 1,
26 ADDHS_SPECIAL_0_OPCODE_X0 = 99, 26 ADDLI_OPCODE_X0 = 1,
27 ADDHS_SPECIAL_0_OPCODE_X1 = 69, 27 ADDLI_OPCODE_X1 = 0,
28 ADDH_SPECIAL_0_OPCODE_X0 = 2, 28 ADDXI_IMM8_OPCODE_X0 = 2,
29 ADDH_SPECIAL_0_OPCODE_X1 = 2, 29 ADDXI_IMM8_OPCODE_X1 = 2,
30 ADDIB_IMM_0_OPCODE_X0 = 1, 30 ADDXI_OPCODE_Y0 = 1,
31 ADDIB_IMM_0_OPCODE_X1 = 1, 31 ADDXI_OPCODE_Y1 = 2,
32 ADDIH_IMM_0_OPCODE_X0 = 2, 32 ADDXLI_OPCODE_X0 = 2,
33 ADDIH_IMM_0_OPCODE_X1 = 2, 33 ADDXLI_OPCODE_X1 = 1,
34 ADDI_IMM_0_OPCODE_X0 = 3, 34 ADDXSC_RRR_0_OPCODE_X0 = 1,
35 ADDI_IMM_0_OPCODE_X1 = 3, 35 ADDXSC_RRR_0_OPCODE_X1 = 1,
36 ADDI_IMM_1_OPCODE_SN = 1, 36 ADDX_RRR_0_OPCODE_X0 = 2,
37 ADDI_OPCODE_Y0 = 9, 37 ADDX_RRR_0_OPCODE_X1 = 2,
38 ADDI_OPCODE_Y1 = 7, 38 ADDX_RRR_0_OPCODE_Y0 = 0,
39 ADDLIS_OPCODE_X0 = 1, 39 ADDX_SPECIAL_0_OPCODE_Y1 = 0,
40 ADDLIS_OPCODE_X1 = 2, 40 ADD_RRR_0_OPCODE_X0 = 3,
41 ADDLI_OPCODE_X0 = 2, 41 ADD_RRR_0_OPCODE_X1 = 3,
42 ADDLI_OPCODE_X1 = 3, 42 ADD_RRR_0_OPCODE_Y0 = 1,
43 ADDS_SPECIAL_0_OPCODE_X0 = 96, 43 ADD_SPECIAL_0_OPCODE_Y1 = 1,
44 ADDS_SPECIAL_0_OPCODE_X1 = 66, 44 ANDI_IMM8_OPCODE_X0 = 3,
45 ADD_SPECIAL_0_OPCODE_X0 = 3, 45 ANDI_IMM8_OPCODE_X1 = 3,
46 ADD_SPECIAL_0_OPCODE_X1 = 3, 46 ANDI_OPCODE_Y0 = 2,
47 ADD_SPECIAL_0_OPCODE_Y0 = 0, 47 ANDI_OPCODE_Y1 = 3,
48 ADD_SPECIAL_0_OPCODE_Y1 = 0, 48 AND_RRR_0_OPCODE_X0 = 4,
49 ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, 49 AND_RRR_0_OPCODE_X1 = 4,
50 ADIFFH_SPECIAL_0_OPCODE_X0 = 5, 50 AND_RRR_5_OPCODE_Y0 = 0,
51 ANDI_IMM_0_OPCODE_X0 = 1, 51 AND_RRR_5_OPCODE_Y1 = 0,
52 ANDI_IMM_0_OPCODE_X1 = 4, 52 BEQZT_BRANCH_OPCODE_X1 = 16,
53 ANDI_OPCODE_Y0 = 10, 53 BEQZ_BRANCH_OPCODE_X1 = 17,
54 ANDI_OPCODE_Y1 = 8, 54 BFEXTS_BF_OPCODE_X0 = 4,
55 AND_SPECIAL_0_OPCODE_X0 = 6, 55 BFEXTU_BF_OPCODE_X0 = 5,
56 AND_SPECIAL_0_OPCODE_X1 = 4, 56 BFINS_BF_OPCODE_X0 = 6,
57 AND_SPECIAL_2_OPCODE_Y0 = 0, 57 BF_OPCODE_X0 = 3,
58 AND_SPECIAL_2_OPCODE_Y1 = 0, 58 BGEZT_BRANCH_OPCODE_X1 = 18,
59 AULI_OPCODE_X0 = 3, 59 BGEZ_BRANCH_OPCODE_X1 = 19,
60 AULI_OPCODE_X1 = 4, 60 BGTZT_BRANCH_OPCODE_X1 = 20,
61 AVGB_U_SPECIAL_0_OPCODE_X0 = 7, 61 BGTZ_BRANCH_OPCODE_X1 = 21,
62 AVGH_SPECIAL_0_OPCODE_X0 = 8, 62 BLBCT_BRANCH_OPCODE_X1 = 22,
63 BBNST_BRANCH_OPCODE_X1 = 15, 63 BLBC_BRANCH_OPCODE_X1 = 23,
64 BBNS_BRANCH_OPCODE_X1 = 14, 64 BLBST_BRANCH_OPCODE_X1 = 24,
65 BBNS_OPCODE_SN = 63, 65 BLBS_BRANCH_OPCODE_X1 = 25,
66 BBST_BRANCH_OPCODE_X1 = 13, 66 BLEZT_BRANCH_OPCODE_X1 = 26,
67 BBS_BRANCH_OPCODE_X1 = 12, 67 BLEZ_BRANCH_OPCODE_X1 = 27,
68 BBS_OPCODE_SN = 62, 68 BLTZT_BRANCH_OPCODE_X1 = 28,
69 BGEZT_BRANCH_OPCODE_X1 = 7, 69 BLTZ_BRANCH_OPCODE_X1 = 29,
70 BGEZ_BRANCH_OPCODE_X1 = 6, 70 BNEZT_BRANCH_OPCODE_X1 = 30,
71 BGEZ_OPCODE_SN = 61, 71 BNEZ_BRANCH_OPCODE_X1 = 31,
72 BGZT_BRANCH_OPCODE_X1 = 5, 72 BRANCH_OPCODE_X1 = 2,
73 BGZ_BRANCH_OPCODE_X1 = 4, 73 CMOVEQZ_RRR_0_OPCODE_X0 = 5,
74 BGZ_OPCODE_SN = 58, 74 CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
75 BITX_UN_0_SHUN_0_OPCODE_X0 = 1, 75 CMOVNEZ_RRR_0_OPCODE_X0 = 6,
76 BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, 76 CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
77 BLEZT_BRANCH_OPCODE_X1 = 11, 77 CMPEQI_IMM8_OPCODE_X0 = 4,
78 BLEZ_BRANCH_OPCODE_X1 = 10, 78 CMPEQI_IMM8_OPCODE_X1 = 4,
79 BLEZ_OPCODE_SN = 59, 79 CMPEQI_OPCODE_Y0 = 3,
80 BLZT_BRANCH_OPCODE_X1 = 9, 80 CMPEQI_OPCODE_Y1 = 4,
81 BLZ_BRANCH_OPCODE_X1 = 8, 81 CMPEQ_RRR_0_OPCODE_X0 = 7,
82 BLZ_OPCODE_SN = 60, 82 CMPEQ_RRR_0_OPCODE_X1 = 5,
83 BNZT_BRANCH_OPCODE_X1 = 3, 83 CMPEQ_RRR_3_OPCODE_Y0 = 0,
84 BNZ_BRANCH_OPCODE_X1 = 2, 84 CMPEQ_RRR_3_OPCODE_Y1 = 2,
85 BNZ_OPCODE_SN = 57, 85 CMPEXCH4_RRR_0_OPCODE_X1 = 6,
86 BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, 86 CMPEXCH_RRR_0_OPCODE_X1 = 7,
87 BRANCH_OPCODE_X1 = 5, 87 CMPLES_RRR_0_OPCODE_X0 = 8,
88 BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, 88 CMPLES_RRR_0_OPCODE_X1 = 8,
89 BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, 89 CMPLES_RRR_2_OPCODE_Y0 = 0,
90 BZT_BRANCH_OPCODE_X1 = 1, 90 CMPLES_RRR_2_OPCODE_Y1 = 0,
91 BZ_BRANCH_OPCODE_X1 = 0, 91 CMPLEU_RRR_0_OPCODE_X0 = 9,
92 BZ_OPCODE_SN = 56, 92 CMPLEU_RRR_0_OPCODE_X1 = 9,
93 CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, 93 CMPLEU_RRR_2_OPCODE_Y0 = 1,
94 CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, 94 CMPLEU_RRR_2_OPCODE_Y1 = 1,
95 CRC32_32_SPECIAL_0_OPCODE_X0 = 9, 95 CMPLTSI_IMM8_OPCODE_X0 = 5,
96 CRC32_8_SPECIAL_0_OPCODE_X0 = 10, 96 CMPLTSI_IMM8_OPCODE_X1 = 5,
97 CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, 97 CMPLTSI_OPCODE_Y0 = 4,
98 CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, 98 CMPLTSI_OPCODE_Y1 = 5,
99 DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, 99 CMPLTS_RRR_0_OPCODE_X0 = 10,
100 DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, 100 CMPLTS_RRR_0_OPCODE_X1 = 10,
101 DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, 101 CMPLTS_RRR_2_OPCODE_Y0 = 2,
102 FINV_UN_0_SHUN_0_OPCODE_X1 = 3, 102 CMPLTS_RRR_2_OPCODE_Y1 = 2,
103 FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, 103 CMPLTUI_IMM8_OPCODE_X0 = 6,
104 FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, 104 CMPLTUI_IMM8_OPCODE_X1 = 6,
105 FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, 105 CMPLTU_RRR_0_OPCODE_X0 = 11,
106 FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, 106 CMPLTU_RRR_0_OPCODE_X1 = 11,
107 FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, 107 CMPLTU_RRR_2_OPCODE_Y0 = 3,
108 FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, 108 CMPLTU_RRR_2_OPCODE_Y1 = 3,
109 HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, 109 CMPNE_RRR_0_OPCODE_X0 = 12,
110 ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, 110 CMPNE_RRR_0_OPCODE_X1 = 12,
111 ILL_UN_0_SHUN_0_OPCODE_X1 = 7, 111 CMPNE_RRR_3_OPCODE_Y0 = 1,
112 ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, 112 CMPNE_RRR_3_OPCODE_Y1 = 3,
113 IMM_0_OPCODE_SN = 0, 113 CMULAF_RRR_0_OPCODE_X0 = 13,
114 IMM_0_OPCODE_X0 = 4, 114 CMULA_RRR_0_OPCODE_X0 = 14,
115 IMM_0_OPCODE_X1 = 6, 115 CMULFR_RRR_0_OPCODE_X0 = 15,
116 IMM_1_OPCODE_SN = 1, 116 CMULF_RRR_0_OPCODE_X0 = 16,
117 IMM_OPCODE_0_X0 = 5, 117 CMULHR_RRR_0_OPCODE_X0 = 17,
118 INTHB_SPECIAL_0_OPCODE_X0 = 11, 118 CMULH_RRR_0_OPCODE_X0 = 18,
119 INTHB_SPECIAL_0_OPCODE_X1 = 5, 119 CMUL_RRR_0_OPCODE_X0 = 19,
120 INTHH_SPECIAL_0_OPCODE_X0 = 12, 120 CNTLZ_UNARY_OPCODE_X0 = 1,
121 INTHH_SPECIAL_0_OPCODE_X1 = 6, 121 CNTLZ_UNARY_OPCODE_Y0 = 1,
122 INTLB_SPECIAL_0_OPCODE_X0 = 13, 122 CNTTZ_UNARY_OPCODE_X0 = 2,
123 INTLB_SPECIAL_0_OPCODE_X1 = 7, 123 CNTTZ_UNARY_OPCODE_Y0 = 2,
124 INTLH_SPECIAL_0_OPCODE_X0 = 14, 124 CRC32_32_RRR_0_OPCODE_X0 = 20,
125 INTLH_SPECIAL_0_OPCODE_X1 = 8, 125 CRC32_8_RRR_0_OPCODE_X0 = 21,
126 INV_UN_0_SHUN_0_OPCODE_X1 = 8, 126 DBLALIGN2_RRR_0_OPCODE_X0 = 22,
127 IRET_UN_0_SHUN_0_OPCODE_X1 = 9, 127 DBLALIGN2_RRR_0_OPCODE_X1 = 13,
128 JALB_OPCODE_X1 = 13, 128 DBLALIGN4_RRR_0_OPCODE_X0 = 23,
129 JALF_OPCODE_X1 = 12, 129 DBLALIGN4_RRR_0_OPCODE_X1 = 14,
130 JALRP_SPECIAL_0_OPCODE_X1 = 9, 130 DBLALIGN6_RRR_0_OPCODE_X0 = 24,
131 JALRR_IMM_1_OPCODE_SN = 3, 131 DBLALIGN6_RRR_0_OPCODE_X1 = 15,
132 JALR_RR_IMM_0_OPCODE_SN = 5, 132 DBLALIGN_RRR_0_OPCODE_X0 = 25,
133 JALR_SPECIAL_0_OPCODE_X1 = 10, 133 DRAIN_UNARY_OPCODE_X1 = 1,
134 JB_OPCODE_X1 = 11, 134 DTLBPR_UNARY_OPCODE_X1 = 2,
135 JF_OPCODE_X1 = 10, 135 EXCH4_RRR_0_OPCODE_X1 = 16,
136 JRP_SPECIAL_0_OPCODE_X1 = 11, 136 EXCH_RRR_0_OPCODE_X1 = 17,
137 JRR_IMM_1_OPCODE_SN = 2, 137 FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
138 JR_RR_IMM_0_OPCODE_SN = 4, 138 FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
139 JR_SPECIAL_0_OPCODE_X1 = 12, 139 FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
140 LBADD_IMM_0_OPCODE_X1 = 22, 140 FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
141 LBADD_U_IMM_0_OPCODE_X1 = 23, 141 FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
142 LB_OPCODE_Y2 = 0, 142 FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
143 LB_UN_0_SHUN_0_OPCODE_X1 = 10, 143 FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
144 LB_U_OPCODE_Y2 = 1, 144 FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
145 LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, 145 FETCHADD4_RRR_0_OPCODE_X1 = 18,
146 LHADD_IMM_0_OPCODE_X1 = 24, 146 FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
147 LHADD_U_IMM_0_OPCODE_X1 = 25, 147 FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
148 LH_OPCODE_Y2 = 2, 148 FETCHADD_RRR_0_OPCODE_X1 = 21,
149 LH_UN_0_SHUN_0_OPCODE_X1 = 12, 149 FETCHAND4_RRR_0_OPCODE_X1 = 22,
150 LH_U_OPCODE_Y2 = 3, 150 FETCHAND_RRR_0_OPCODE_X1 = 23,
151 LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, 151 FETCHOR4_RRR_0_OPCODE_X1 = 24,
152 LNK_SPECIAL_0_OPCODE_X1 = 13, 152 FETCHOR_RRR_0_OPCODE_X1 = 25,
153 LWADD_IMM_0_OPCODE_X1 = 26, 153 FINV_UNARY_OPCODE_X1 = 3,
154 LWADD_NA_IMM_0_OPCODE_X1 = 27, 154 FLUSHWB_UNARY_OPCODE_X1 = 4,
155 LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, 155 FLUSH_UNARY_OPCODE_X1 = 5,
156 LW_OPCODE_Y2 = 4, 156 FNOP_UNARY_OPCODE_X0 = 3,
157 LW_UN_0_SHUN_0_OPCODE_X1 = 14, 157 FNOP_UNARY_OPCODE_X1 = 6,
158 MAXB_U_SPECIAL_0_OPCODE_X0 = 15, 158 FNOP_UNARY_OPCODE_Y0 = 3,
159 MAXB_U_SPECIAL_0_OPCODE_X1 = 14, 159 FNOP_UNARY_OPCODE_Y1 = 8,
160 MAXH_SPECIAL_0_OPCODE_X0 = 16, 160 FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
161 MAXH_SPECIAL_0_OPCODE_X1 = 15, 161 FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
162 MAXIB_U_IMM_0_OPCODE_X0 = 4, 162 FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
163 MAXIB_U_IMM_0_OPCODE_X1 = 5, 163 FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
164 MAXIH_IMM_0_OPCODE_X0 = 5, 164 FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
165 MAXIH_IMM_0_OPCODE_X1 = 6, 165 FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
166 MFSPR_IMM_0_OPCODE_X1 = 7, 166 FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
167 MF_UN_0_SHUN_0_OPCODE_X1 = 15, 167 FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
168 MINB_U_SPECIAL_0_OPCODE_X0 = 17, 168 ICOH_UNARY_OPCODE_X1 = 7,
169 MINB_U_SPECIAL_0_OPCODE_X1 = 16, 169 ILL_UNARY_OPCODE_X1 = 8,
170 MINH_SPECIAL_0_OPCODE_X0 = 18, 170 ILL_UNARY_OPCODE_Y1 = 9,
171 MINH_SPECIAL_0_OPCODE_X1 = 17, 171 IMM8_OPCODE_X0 = 4,
172 MINIB_U_IMM_0_OPCODE_X0 = 6, 172 IMM8_OPCODE_X1 = 3,
173 MINIB_U_IMM_0_OPCODE_X1 = 8, 173 INV_UNARY_OPCODE_X1 = 9,
174 MINIH_IMM_0_OPCODE_X0 = 7, 174 IRET_UNARY_OPCODE_X1 = 10,
175 MINIH_IMM_0_OPCODE_X1 = 9, 175 JALRP_UNARY_OPCODE_X1 = 11,
176 MM_OPCODE_X0 = 6, 176 JALRP_UNARY_OPCODE_Y1 = 10,
177 MM_OPCODE_X1 = 7, 177 JALR_UNARY_OPCODE_X1 = 12,
178 MNZB_SPECIAL_0_OPCODE_X0 = 19, 178 JALR_UNARY_OPCODE_Y1 = 11,
179 MNZB_SPECIAL_0_OPCODE_X1 = 18, 179 JAL_JUMP_OPCODE_X1 = 0,
180 MNZH_SPECIAL_0_OPCODE_X0 = 20, 180 JRP_UNARY_OPCODE_X1 = 13,
181 MNZH_SPECIAL_0_OPCODE_X1 = 19, 181 JRP_UNARY_OPCODE_Y1 = 12,
182 MNZ_SPECIAL_0_OPCODE_X0 = 21, 182 JR_UNARY_OPCODE_X1 = 14,
183 MNZ_SPECIAL_0_OPCODE_X1 = 20, 183 JR_UNARY_OPCODE_Y1 = 13,
184 MNZ_SPECIAL_1_OPCODE_Y0 = 0, 184 JUMP_OPCODE_X1 = 4,
185 MNZ_SPECIAL_1_OPCODE_Y1 = 1, 185 J_JUMP_OPCODE_X1 = 1,
186 MOVEI_IMM_1_OPCODE_SN = 0, 186 LD1S_ADD_IMM8_OPCODE_X1 = 7,
187 MOVE_RR_IMM_0_OPCODE_SN = 8, 187 LD1S_OPCODE_Y2 = 0,
188 MTSPR_IMM_0_OPCODE_X1 = 10, 188 LD1S_UNARY_OPCODE_X1 = 15,
189 MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, 189 LD1U_ADD_IMM8_OPCODE_X1 = 8,
190 MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, 190 LD1U_OPCODE_Y2 = 1,
191 MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, 191 LD1U_UNARY_OPCODE_X1 = 16,
192 MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, 192 LD2S_ADD_IMM8_OPCODE_X1 = 9,
193 MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, 193 LD2S_OPCODE_Y2 = 2,
194 MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, 194 LD2S_UNARY_OPCODE_X1 = 17,
195 MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, 195 LD2U_ADD_IMM8_OPCODE_X1 = 10,
196 MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, 196 LD2U_OPCODE_Y2 = 3,
197 MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, 197 LD2U_UNARY_OPCODE_X1 = 18,
198 MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, 198 LD4S_ADD_IMM8_OPCODE_X1 = 11,
199 MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, 199 LD4S_OPCODE_Y2 = 1,
200 MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, 200 LD4S_UNARY_OPCODE_X1 = 19,
201 MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, 201 LD4U_ADD_IMM8_OPCODE_X1 = 12,
202 MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, 202 LD4U_OPCODE_Y2 = 2,
203 MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, 203 LD4U_UNARY_OPCODE_X1 = 20,
204 MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, 204 LDNA_UNARY_OPCODE_X1 = 21,
205 MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, 205 LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
206 MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, 206 LDNT1S_UNARY_OPCODE_X1 = 22,
207 MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, 207 LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
208 MULHL_US_SPECIAL_0_OPCODE_X0 = 36, 208 LDNT1U_UNARY_OPCODE_X1 = 23,
209 MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, 209 LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
210 MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, 210 LDNT2S_UNARY_OPCODE_X1 = 24,
211 MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, 211 LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
212 MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, 212 LDNT2U_UNARY_OPCODE_X1 = 25,
213 MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, 213 LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
214 MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, 214 LDNT4S_UNARY_OPCODE_X1 = 26,
215 MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, 215 LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
216 MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, 216 LDNT4U_UNARY_OPCODE_X1 = 27,
217 MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, 217 LDNT_ADD_IMM8_OPCODE_X1 = 19,
218 MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, 218 LDNT_UNARY_OPCODE_X1 = 28,
219 MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, 219 LD_ADD_IMM8_OPCODE_X1 = 20,
220 MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, 220 LD_OPCODE_Y2 = 3,
221 MVNZ_SPECIAL_0_OPCODE_X0 = 45, 221 LD_UNARY_OPCODE_X1 = 29,
222 MVNZ_SPECIAL_1_OPCODE_Y0 = 1, 222 LNK_UNARY_OPCODE_X1 = 30,
223 MVZ_SPECIAL_0_OPCODE_X0 = 46, 223 LNK_UNARY_OPCODE_Y1 = 14,
224 MVZ_SPECIAL_1_OPCODE_Y0 = 2, 224 LWNA_ADD_IMM8_OPCODE_X1 = 21,
225 MZB_SPECIAL_0_OPCODE_X0 = 47, 225 MFSPR_IMM8_OPCODE_X1 = 22,
226 MZB_SPECIAL_0_OPCODE_X1 = 21, 226 MF_UNARY_OPCODE_X1 = 31,
227 MZH_SPECIAL_0_OPCODE_X0 = 48, 227 MM_BF_OPCODE_X0 = 7,
228 MZH_SPECIAL_0_OPCODE_X1 = 22, 228 MNZ_RRR_0_OPCODE_X0 = 40,
229 MZ_SPECIAL_0_OPCODE_X0 = 49, 229 MNZ_RRR_0_OPCODE_X1 = 26,
230 MZ_SPECIAL_0_OPCODE_X1 = 23, 230 MNZ_RRR_4_OPCODE_Y0 = 2,
231 MZ_SPECIAL_1_OPCODE_Y0 = 3, 231 MNZ_RRR_4_OPCODE_Y1 = 2,
232 MZ_SPECIAL_1_OPCODE_Y1 = 2, 232 MODE_OPCODE_YA2 = 1,
233 NAP_UN_0_SHUN_0_OPCODE_X1 = 16, 233 MODE_OPCODE_YB2 = 2,
234 NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, 234 MODE_OPCODE_YC2 = 3,
235 NOP_UN_0_SHUN_0_OPCODE_X0 = 6, 235 MTSPR_IMM8_OPCODE_X1 = 23,
236 NOP_UN_0_SHUN_0_OPCODE_X1 = 17, 236 MULAX_RRR_0_OPCODE_X0 = 41,
237 NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, 237 MULAX_RRR_3_OPCODE_Y0 = 2,
238 NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, 238 MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
239 NOREG_RR_IMM_0_OPCODE_SN = 0, 239 MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
240 NOR_SPECIAL_0_OPCODE_X0 = 50, 240 MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
241 NOR_SPECIAL_0_OPCODE_X1 = 24, 241 MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
242 NOR_SPECIAL_2_OPCODE_Y0 = 1, 242 MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
243 NOR_SPECIAL_2_OPCODE_Y1 = 1, 243 MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
244 ORI_IMM_0_OPCODE_X0 = 8, 244 MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
245 ORI_IMM_0_OPCODE_X1 = 11, 245 MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
246 ORI_OPCODE_Y0 = 11, 246 MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
247 ORI_OPCODE_Y1 = 9, 247 MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
248 OR_SPECIAL_0_OPCODE_X0 = 51, 248 MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
249 OR_SPECIAL_0_OPCODE_X1 = 25, 249 MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
250 OR_SPECIAL_2_OPCODE_Y0 = 2, 250 MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
251 OR_SPECIAL_2_OPCODE_Y1 = 2, 251 MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
252 PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, 252 MULX_RRR_0_OPCODE_X0 = 52,
253 PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, 253 MULX_RRR_3_OPCODE_Y0 = 3,
254 PACKHB_SPECIAL_0_OPCODE_X0 = 52, 254 MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
255 PACKHB_SPECIAL_0_OPCODE_X1 = 26, 255 MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
256 PACKHS_SPECIAL_0_OPCODE_X0 = 102, 256 MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
257 PACKHS_SPECIAL_0_OPCODE_X1 = 72, 257 MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
258 PACKLB_SPECIAL_0_OPCODE_X0 = 53, 258 MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
259 PACKLB_SPECIAL_0_OPCODE_X1 = 27, 259 MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
260 PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, 260 MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
261 PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, 261 MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
262 RLI_SHUN_0_OPCODE_X0 = 1, 262 MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
263 RLI_SHUN_0_OPCODE_X1 = 1, 263 MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
264 RLI_SHUN_0_OPCODE_Y0 = 1, 264 MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
265 RLI_SHUN_0_OPCODE_Y1 = 1, 265 MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
266 RL_SPECIAL_0_OPCODE_X0 = 54, 266 MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
267 RL_SPECIAL_0_OPCODE_X1 = 28, 267 MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
268 RL_SPECIAL_3_OPCODE_Y0 = 0, 268 MZ_RRR_0_OPCODE_X0 = 63,
269 RL_SPECIAL_3_OPCODE_Y1 = 0, 269 MZ_RRR_0_OPCODE_X1 = 27,
270 RR_IMM_0_OPCODE_SN = 0, 270 MZ_RRR_4_OPCODE_Y0 = 3,
271 S1A_SPECIAL_0_OPCODE_X0 = 55, 271 MZ_RRR_4_OPCODE_Y1 = 3,
272 S1A_SPECIAL_0_OPCODE_X1 = 29, 272 NAP_UNARY_OPCODE_X1 = 32,
273 S1A_SPECIAL_0_OPCODE_Y0 = 1, 273 NOP_UNARY_OPCODE_X0 = 5,
274 S1A_SPECIAL_0_OPCODE_Y1 = 1, 274 NOP_UNARY_OPCODE_X1 = 33,
275 S2A_SPECIAL_0_OPCODE_X0 = 56, 275 NOP_UNARY_OPCODE_Y0 = 5,
276 S2A_SPECIAL_0_OPCODE_X1 = 30, 276 NOP_UNARY_OPCODE_Y1 = 15,
277 S2A_SPECIAL_0_OPCODE_Y0 = 2, 277 NOR_RRR_0_OPCODE_X0 = 64,
278 S2A_SPECIAL_0_OPCODE_Y1 = 2, 278 NOR_RRR_0_OPCODE_X1 = 28,
279 S3A_SPECIAL_0_OPCODE_X0 = 57, 279 NOR_RRR_5_OPCODE_Y0 = 1,
280 S3A_SPECIAL_0_OPCODE_X1 = 31, 280 NOR_RRR_5_OPCODE_Y1 = 1,
281 S3A_SPECIAL_5_OPCODE_Y0 = 1, 281 ORI_IMM8_OPCODE_X0 = 7,
282 S3A_SPECIAL_5_OPCODE_Y1 = 1, 282 ORI_IMM8_OPCODE_X1 = 24,
283 SADAB_U_SPECIAL_0_OPCODE_X0 = 58, 283 OR_RRR_0_OPCODE_X0 = 65,
284 SADAH_SPECIAL_0_OPCODE_X0 = 59, 284 OR_RRR_0_OPCODE_X1 = 29,
285 SADAH_U_SPECIAL_0_OPCODE_X0 = 60, 285 OR_RRR_5_OPCODE_Y0 = 2,
286 SADB_U_SPECIAL_0_OPCODE_X0 = 61, 286 OR_RRR_5_OPCODE_Y1 = 2,
287 SADH_SPECIAL_0_OPCODE_X0 = 62, 287 PCNT_UNARY_OPCODE_X0 = 6,
288 SADH_U_SPECIAL_0_OPCODE_X0 = 63, 288 PCNT_UNARY_OPCODE_Y0 = 6,
289 SBADD_IMM_0_OPCODE_X1 = 28, 289 REVBITS_UNARY_OPCODE_X0 = 7,
290 SB_OPCODE_Y2 = 5, 290 REVBITS_UNARY_OPCODE_Y0 = 7,
291 SB_SPECIAL_0_OPCODE_X1 = 32, 291 REVBYTES_UNARY_OPCODE_X0 = 8,
292 SEQB_SPECIAL_0_OPCODE_X0 = 64, 292 REVBYTES_UNARY_OPCODE_Y0 = 8,
293 SEQB_SPECIAL_0_OPCODE_X1 = 33, 293 ROTLI_SHIFT_OPCODE_X0 = 1,
294 SEQH_SPECIAL_0_OPCODE_X0 = 65, 294 ROTLI_SHIFT_OPCODE_X1 = 1,
295 SEQH_SPECIAL_0_OPCODE_X1 = 34, 295 ROTLI_SHIFT_OPCODE_Y0 = 0,
296 SEQIB_IMM_0_OPCODE_X0 = 9, 296 ROTLI_SHIFT_OPCODE_Y1 = 0,
297 SEQIB_IMM_0_OPCODE_X1 = 12, 297 ROTL_RRR_0_OPCODE_X0 = 66,
298 SEQIH_IMM_0_OPCODE_X0 = 10, 298 ROTL_RRR_0_OPCODE_X1 = 30,
299 SEQIH_IMM_0_OPCODE_X1 = 13, 299 ROTL_RRR_6_OPCODE_Y0 = 0,
300 SEQI_IMM_0_OPCODE_X0 = 11, 300 ROTL_RRR_6_OPCODE_Y1 = 0,
301 SEQI_IMM_0_OPCODE_X1 = 14, 301 RRR_0_OPCODE_X0 = 5,
302 SEQI_OPCODE_Y0 = 12, 302 RRR_0_OPCODE_X1 = 5,
303 SEQI_OPCODE_Y1 = 10, 303 RRR_0_OPCODE_Y0 = 5,
304 SEQ_SPECIAL_0_OPCODE_X0 = 66, 304 RRR_0_OPCODE_Y1 = 6,
305 SEQ_SPECIAL_0_OPCODE_X1 = 35, 305 RRR_1_OPCODE_Y0 = 6,
306 SEQ_SPECIAL_5_OPCODE_Y0 = 2, 306 RRR_1_OPCODE_Y1 = 7,
307 SEQ_SPECIAL_5_OPCODE_Y1 = 2, 307 RRR_2_OPCODE_Y0 = 7,
308 SHADD_IMM_0_OPCODE_X1 = 29, 308 RRR_2_OPCODE_Y1 = 8,
309 SHL8II_IMM_0_OPCODE_SN = 3, 309 RRR_3_OPCODE_Y0 = 8,
310 SHLB_SPECIAL_0_OPCODE_X0 = 67, 310 RRR_3_OPCODE_Y1 = 9,
311 SHLB_SPECIAL_0_OPCODE_X1 = 36, 311 RRR_4_OPCODE_Y0 = 9,
312 SHLH_SPECIAL_0_OPCODE_X0 = 68, 312 RRR_4_OPCODE_Y1 = 10,
313 SHLH_SPECIAL_0_OPCODE_X1 = 37, 313 RRR_5_OPCODE_Y0 = 10,
314 SHLIB_SHUN_0_OPCODE_X0 = 2, 314 RRR_5_OPCODE_Y1 = 11,
315 SHLIB_SHUN_0_OPCODE_X1 = 2, 315 RRR_6_OPCODE_Y0 = 11,
316 SHLIH_SHUN_0_OPCODE_X0 = 3, 316 RRR_6_OPCODE_Y1 = 12,
317 SHLIH_SHUN_0_OPCODE_X1 = 3, 317 RRR_7_OPCODE_Y0 = 12,
318 SHLI_SHUN_0_OPCODE_X0 = 4, 318 RRR_7_OPCODE_Y1 = 13,
319 SHLI_SHUN_0_OPCODE_X1 = 4, 319 RRR_8_OPCODE_Y0 = 13,
320 SHLI_SHUN_0_OPCODE_Y0 = 2, 320 RRR_9_OPCODE_Y0 = 14,
321 SHLI_SHUN_0_OPCODE_Y1 = 2, 321 SHIFT_OPCODE_X0 = 6,
322 SHL_SPECIAL_0_OPCODE_X0 = 69, 322 SHIFT_OPCODE_X1 = 6,
323 SHL_SPECIAL_0_OPCODE_X1 = 38, 323 SHIFT_OPCODE_Y0 = 15,
324 SHL_SPECIAL_3_OPCODE_Y0 = 1, 324 SHIFT_OPCODE_Y1 = 14,
325 SHL_SPECIAL_3_OPCODE_Y1 = 1, 325 SHL16INSLI_OPCODE_X0 = 7,
326 SHR1_RR_IMM_0_OPCODE_SN = 9, 326 SHL16INSLI_OPCODE_X1 = 7,
327 SHRB_SPECIAL_0_OPCODE_X0 = 70, 327 SHL1ADDX_RRR_0_OPCODE_X0 = 67,
328 SHRB_SPECIAL_0_OPCODE_X1 = 39, 328 SHL1ADDX_RRR_0_OPCODE_X1 = 31,
329 SHRH_SPECIAL_0_OPCODE_X0 = 71, 329 SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
330 SHRH_SPECIAL_0_OPCODE_X1 = 40, 330 SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
331 SHRIB_SHUN_0_OPCODE_X0 = 5, 331 SHL1ADD_RRR_0_OPCODE_X0 = 68,
332 SHRIB_SHUN_0_OPCODE_X1 = 5, 332 SHL1ADD_RRR_0_OPCODE_X1 = 32,
333 SHRIH_SHUN_0_OPCODE_X0 = 6, 333 SHL1ADD_RRR_1_OPCODE_Y0 = 0,
334 SHRIH_SHUN_0_OPCODE_X1 = 6, 334 SHL1ADD_RRR_1_OPCODE_Y1 = 0,
335 SHRI_SHUN_0_OPCODE_X0 = 7, 335 SHL2ADDX_RRR_0_OPCODE_X0 = 69,
336 SHRI_SHUN_0_OPCODE_X1 = 7, 336 SHL2ADDX_RRR_0_OPCODE_X1 = 33,
337 SHRI_SHUN_0_OPCODE_Y0 = 3, 337 SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
338 SHRI_SHUN_0_OPCODE_Y1 = 3, 338 SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
339 SHR_SPECIAL_0_OPCODE_X0 = 72, 339 SHL2ADD_RRR_0_OPCODE_X0 = 70,
340 SHR_SPECIAL_0_OPCODE_X1 = 41, 340 SHL2ADD_RRR_0_OPCODE_X1 = 34,
341 SHR_SPECIAL_3_OPCODE_Y0 = 2, 341 SHL2ADD_RRR_1_OPCODE_Y0 = 1,
342 SHR_SPECIAL_3_OPCODE_Y1 = 2, 342 SHL2ADD_RRR_1_OPCODE_Y1 = 1,
343 SHUN_0_OPCODE_X0 = 7, 343 SHL3ADDX_RRR_0_OPCODE_X0 = 71,
344 SHUN_0_OPCODE_X1 = 8, 344 SHL3ADDX_RRR_0_OPCODE_X1 = 35,
345 SHUN_0_OPCODE_Y0 = 13, 345 SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
346 SHUN_0_OPCODE_Y1 = 11, 346 SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
347 SH_OPCODE_Y2 = 6, 347 SHL3ADD_RRR_0_OPCODE_X0 = 72,
348 SH_SPECIAL_0_OPCODE_X1 = 42, 348 SHL3ADD_RRR_0_OPCODE_X1 = 36,
349 SLTB_SPECIAL_0_OPCODE_X0 = 73, 349 SHL3ADD_RRR_1_OPCODE_Y0 = 2,
350 SLTB_SPECIAL_0_OPCODE_X1 = 43, 350 SHL3ADD_RRR_1_OPCODE_Y1 = 2,
351 SLTB_U_SPECIAL_0_OPCODE_X0 = 74, 351 SHLI_SHIFT_OPCODE_X0 = 2,
352 SLTB_U_SPECIAL_0_OPCODE_X1 = 44, 352 SHLI_SHIFT_OPCODE_X1 = 2,
353 SLTEB_SPECIAL_0_OPCODE_X0 = 75, 353 SHLI_SHIFT_OPCODE_Y0 = 1,
354 SLTEB_SPECIAL_0_OPCODE_X1 = 45, 354 SHLI_SHIFT_OPCODE_Y1 = 1,
355 SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, 355 SHLXI_SHIFT_OPCODE_X0 = 3,
356 SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, 356 SHLXI_SHIFT_OPCODE_X1 = 3,
357 SLTEH_SPECIAL_0_OPCODE_X0 = 77, 357 SHLX_RRR_0_OPCODE_X0 = 73,
358 SLTEH_SPECIAL_0_OPCODE_X1 = 47, 358 SHLX_RRR_0_OPCODE_X1 = 37,
359 SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, 359 SHL_RRR_0_OPCODE_X0 = 74,
360 SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, 360 SHL_RRR_0_OPCODE_X1 = 38,
361 SLTE_SPECIAL_0_OPCODE_X0 = 79, 361 SHL_RRR_6_OPCODE_Y0 = 1,
362 SLTE_SPECIAL_0_OPCODE_X1 = 49, 362 SHL_RRR_6_OPCODE_Y1 = 1,
363 SLTE_SPECIAL_4_OPCODE_Y0 = 0, 363 SHRSI_SHIFT_OPCODE_X0 = 4,
364 SLTE_SPECIAL_4_OPCODE_Y1 = 0, 364 SHRSI_SHIFT_OPCODE_X1 = 4,
365 SLTE_U_SPECIAL_0_OPCODE_X0 = 80, 365 SHRSI_SHIFT_OPCODE_Y0 = 2,
366 SLTE_U_SPECIAL_0_OPCODE_X1 = 50, 366 SHRSI_SHIFT_OPCODE_Y1 = 2,
367 SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, 367 SHRS_RRR_0_OPCODE_X0 = 75,
368 SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, 368 SHRS_RRR_0_OPCODE_X1 = 39,
369 SLTH_SPECIAL_0_OPCODE_X0 = 81, 369 SHRS_RRR_6_OPCODE_Y0 = 2,
370 SLTH_SPECIAL_0_OPCODE_X1 = 51, 370 SHRS_RRR_6_OPCODE_Y1 = 2,
371 SLTH_U_SPECIAL_0_OPCODE_X0 = 82, 371 SHRUI_SHIFT_OPCODE_X0 = 5,
372 SLTH_U_SPECIAL_0_OPCODE_X1 = 52, 372 SHRUI_SHIFT_OPCODE_X1 = 5,
373 SLTIB_IMM_0_OPCODE_X0 = 12, 373 SHRUI_SHIFT_OPCODE_Y0 = 3,
374 SLTIB_IMM_0_OPCODE_X1 = 15, 374 SHRUI_SHIFT_OPCODE_Y1 = 3,
375 SLTIB_U_IMM_0_OPCODE_X0 = 13, 375 SHRUXI_SHIFT_OPCODE_X0 = 6,
376 SLTIB_U_IMM_0_OPCODE_X1 = 16, 376 SHRUXI_SHIFT_OPCODE_X1 = 6,
377 SLTIH_IMM_0_OPCODE_X0 = 14, 377 SHRUX_RRR_0_OPCODE_X0 = 76,
378 SLTIH_IMM_0_OPCODE_X1 = 17, 378 SHRUX_RRR_0_OPCODE_X1 = 40,
379 SLTIH_U_IMM_0_OPCODE_X0 = 15, 379 SHRU_RRR_0_OPCODE_X0 = 77,
380 SLTIH_U_IMM_0_OPCODE_X1 = 18, 380 SHRU_RRR_0_OPCODE_X1 = 41,
381 SLTI_IMM_0_OPCODE_X0 = 16, 381 SHRU_RRR_6_OPCODE_Y0 = 3,
382 SLTI_IMM_0_OPCODE_X1 = 19, 382 SHRU_RRR_6_OPCODE_Y1 = 3,
383 SLTI_OPCODE_Y0 = 14, 383 SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
384 SLTI_OPCODE_Y1 = 12, 384 ST1_ADD_IMM8_OPCODE_X1 = 25,
385 SLTI_U_IMM_0_OPCODE_X0 = 17, 385 ST1_OPCODE_Y2 = 0,
386 SLTI_U_IMM_0_OPCODE_X1 = 20, 386 ST1_RRR_0_OPCODE_X1 = 42,
387 SLTI_U_OPCODE_Y0 = 15, 387 ST2_ADD_IMM8_OPCODE_X1 = 26,
388 SLTI_U_OPCODE_Y1 = 13, 388 ST2_OPCODE_Y2 = 1,
389 SLT_SPECIAL_0_OPCODE_X0 = 83, 389 ST2_RRR_0_OPCODE_X1 = 43,
390 SLT_SPECIAL_0_OPCODE_X1 = 53, 390 ST4_ADD_IMM8_OPCODE_X1 = 27,
391 SLT_SPECIAL_4_OPCODE_Y0 = 2, 391 ST4_OPCODE_Y2 = 2,
392 SLT_SPECIAL_4_OPCODE_Y1 = 2, 392 ST4_RRR_0_OPCODE_X1 = 44,
393 SLT_U_SPECIAL_0_OPCODE_X0 = 84, 393 STNT1_ADD_IMM8_OPCODE_X1 = 28,
394 SLT_U_SPECIAL_0_OPCODE_X1 = 54, 394 STNT1_RRR_0_OPCODE_X1 = 45,
395 SLT_U_SPECIAL_4_OPCODE_Y0 = 3, 395 STNT2_ADD_IMM8_OPCODE_X1 = 29,
396 SLT_U_SPECIAL_4_OPCODE_Y1 = 3, 396 STNT2_RRR_0_OPCODE_X1 = 46,
397 SNEB_SPECIAL_0_OPCODE_X0 = 85, 397 STNT4_ADD_IMM8_OPCODE_X1 = 30,
398 SNEB_SPECIAL_0_OPCODE_X1 = 55, 398 STNT4_RRR_0_OPCODE_X1 = 47,
399 SNEH_SPECIAL_0_OPCODE_X0 = 86, 399 STNT_ADD_IMM8_OPCODE_X1 = 31,
400 SNEH_SPECIAL_0_OPCODE_X1 = 56, 400 STNT_RRR_0_OPCODE_X1 = 48,
401 SNE_SPECIAL_0_OPCODE_X0 = 87, 401 ST_ADD_IMM8_OPCODE_X1 = 32,
402 SNE_SPECIAL_0_OPCODE_X1 = 57, 402 ST_OPCODE_Y2 = 3,
403 SNE_SPECIAL_5_OPCODE_Y0 = 3, 403 ST_RRR_0_OPCODE_X1 = 49,
404 SNE_SPECIAL_5_OPCODE_Y1 = 3, 404 SUBXSC_RRR_0_OPCODE_X0 = 79,
405 SPECIAL_0_OPCODE_X0 = 0, 405 SUBXSC_RRR_0_OPCODE_X1 = 50,
406 SPECIAL_0_OPCODE_X1 = 1, 406 SUBX_RRR_0_OPCODE_X0 = 80,
407 SPECIAL_0_OPCODE_Y0 = 1, 407 SUBX_RRR_0_OPCODE_X1 = 51,
408 SPECIAL_0_OPCODE_Y1 = 1, 408 SUBX_RRR_0_OPCODE_Y0 = 2,
409 SPECIAL_1_OPCODE_Y0 = 2, 409 SUBX_RRR_0_OPCODE_Y1 = 2,
410 SPECIAL_1_OPCODE_Y1 = 2, 410 SUB_RRR_0_OPCODE_X0 = 81,
411 SPECIAL_2_OPCODE_Y0 = 3, 411 SUB_RRR_0_OPCODE_X1 = 52,
412 SPECIAL_2_OPCODE_Y1 = 3, 412 SUB_RRR_0_OPCODE_Y0 = 3,
413 SPECIAL_3_OPCODE_Y0 = 4, 413 SUB_RRR_0_OPCODE_Y1 = 3,
414 SPECIAL_3_OPCODE_Y1 = 4, 414 SWINT0_UNARY_OPCODE_X1 = 34,
415 SPECIAL_4_OPCODE_Y0 = 5, 415 SWINT1_UNARY_OPCODE_X1 = 35,
416 SPECIAL_4_OPCODE_Y1 = 5, 416 SWINT2_UNARY_OPCODE_X1 = 36,
417 SPECIAL_5_OPCODE_Y0 = 6, 417 SWINT3_UNARY_OPCODE_X1 = 37,
418 SPECIAL_5_OPCODE_Y1 = 6, 418 TBLIDXB0_UNARY_OPCODE_X0 = 9,
419 SPECIAL_6_OPCODE_Y0 = 7, 419 TBLIDXB0_UNARY_OPCODE_Y0 = 9,
420 SPECIAL_7_OPCODE_Y0 = 8, 420 TBLIDXB1_UNARY_OPCODE_X0 = 10,
421 SRAB_SPECIAL_0_OPCODE_X0 = 88, 421 TBLIDXB1_UNARY_OPCODE_Y0 = 10,
422 SRAB_SPECIAL_0_OPCODE_X1 = 58, 422 TBLIDXB2_UNARY_OPCODE_X0 = 11,
423 SRAH_SPECIAL_0_OPCODE_X0 = 89, 423 TBLIDXB2_UNARY_OPCODE_Y0 = 11,
424 SRAH_SPECIAL_0_OPCODE_X1 = 59, 424 TBLIDXB3_UNARY_OPCODE_X0 = 12,
425 SRAIB_SHUN_0_OPCODE_X0 = 8, 425 TBLIDXB3_UNARY_OPCODE_Y0 = 12,
426 SRAIB_SHUN_0_OPCODE_X1 = 8, 426 UNARY_RRR_0_OPCODE_X0 = 82,
427 SRAIH_SHUN_0_OPCODE_X0 = 9, 427 UNARY_RRR_0_OPCODE_X1 = 53,
428 SRAIH_SHUN_0_OPCODE_X1 = 9, 428 UNARY_RRR_1_OPCODE_Y0 = 3,
429 SRAI_SHUN_0_OPCODE_X0 = 10, 429 UNARY_RRR_1_OPCODE_Y1 = 3,
430 SRAI_SHUN_0_OPCODE_X1 = 10, 430 V1ADDI_IMM8_OPCODE_X0 = 8,
431 SRAI_SHUN_0_OPCODE_Y0 = 4, 431 V1ADDI_IMM8_OPCODE_X1 = 33,
432 SRAI_SHUN_0_OPCODE_Y1 = 4, 432 V1ADDUC_RRR_0_OPCODE_X0 = 83,
433 SRA_SPECIAL_0_OPCODE_X0 = 90, 433 V1ADDUC_RRR_0_OPCODE_X1 = 54,
434 SRA_SPECIAL_0_OPCODE_X1 = 60, 434 V1ADD_RRR_0_OPCODE_X0 = 84,
435 SRA_SPECIAL_3_OPCODE_Y0 = 3, 435 V1ADD_RRR_0_OPCODE_X1 = 55,
436 SRA_SPECIAL_3_OPCODE_Y1 = 3, 436 V1ADIFFU_RRR_0_OPCODE_X0 = 85,
437 SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, 437 V1AVGU_RRR_0_OPCODE_X0 = 86,
438 SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, 438 V1CMPEQI_IMM8_OPCODE_X0 = 9,
439 SUBB_SPECIAL_0_OPCODE_X0 = 91, 439 V1CMPEQI_IMM8_OPCODE_X1 = 34,
440 SUBB_SPECIAL_0_OPCODE_X1 = 61, 440 V1CMPEQ_RRR_0_OPCODE_X0 = 87,
441 SUBHS_SPECIAL_0_OPCODE_X0 = 101, 441 V1CMPEQ_RRR_0_OPCODE_X1 = 56,
442 SUBHS_SPECIAL_0_OPCODE_X1 = 71, 442 V1CMPLES_RRR_0_OPCODE_X0 = 88,
443 SUBH_SPECIAL_0_OPCODE_X0 = 92, 443 V1CMPLES_RRR_0_OPCODE_X1 = 57,
444 SUBH_SPECIAL_0_OPCODE_X1 = 62, 444 V1CMPLEU_RRR_0_OPCODE_X0 = 89,
445 SUBS_SPECIAL_0_OPCODE_X0 = 97, 445 V1CMPLEU_RRR_0_OPCODE_X1 = 58,
446 SUBS_SPECIAL_0_OPCODE_X1 = 67, 446 V1CMPLTSI_IMM8_OPCODE_X0 = 10,
447 SUB_SPECIAL_0_OPCODE_X0 = 93, 447 V1CMPLTSI_IMM8_OPCODE_X1 = 35,
448 SUB_SPECIAL_0_OPCODE_X1 = 63, 448 V1CMPLTS_RRR_0_OPCODE_X0 = 90,
449 SUB_SPECIAL_0_OPCODE_Y0 = 3, 449 V1CMPLTS_RRR_0_OPCODE_X1 = 59,
450 SUB_SPECIAL_0_OPCODE_Y1 = 3, 450 V1CMPLTUI_IMM8_OPCODE_X0 = 11,
451 SWADD_IMM_0_OPCODE_X1 = 30, 451 V1CMPLTUI_IMM8_OPCODE_X1 = 36,
452 SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, 452 V1CMPLTU_RRR_0_OPCODE_X0 = 91,
453 SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, 453 V1CMPLTU_RRR_0_OPCODE_X1 = 60,
454 SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, 454 V1CMPNE_RRR_0_OPCODE_X0 = 92,
455 SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, 455 V1CMPNE_RRR_0_OPCODE_X1 = 61,
456 SW_OPCODE_Y2 = 7, 456 V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
457 SW_SPECIAL_0_OPCODE_X1 = 64, 457 V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
458 TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, 458 V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
459 TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, 459 V1DDOTPU_RRR_0_OPCODE_X0 = 162,
460 TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, 460 V1DOTPA_RRR_0_OPCODE_X0 = 95,
461 TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, 461 V1DOTPUA_RRR_0_OPCODE_X0 = 163,
462 TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, 462 V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
463 TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, 463 V1DOTPUS_RRR_0_OPCODE_X0 = 97,
464 TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, 464 V1DOTPU_RRR_0_OPCODE_X0 = 164,
465 TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, 465 V1DOTP_RRR_0_OPCODE_X0 = 98,
466 TNS_UN_0_SHUN_0_OPCODE_X1 = 22, 466 V1INT_H_RRR_0_OPCODE_X0 = 99,
467 UN_0_SHUN_0_OPCODE_X0 = 11, 467 V1INT_H_RRR_0_OPCODE_X1 = 62,
468 UN_0_SHUN_0_OPCODE_X1 = 11, 468 V1INT_L_RRR_0_OPCODE_X0 = 100,
469 UN_0_SHUN_0_OPCODE_Y0 = 5, 469 V1INT_L_RRR_0_OPCODE_X1 = 63,
470 UN_0_SHUN_0_OPCODE_Y1 = 5, 470 V1MAXUI_IMM8_OPCODE_X0 = 12,
471 WH64_UN_0_SHUN_0_OPCODE_X1 = 23, 471 V1MAXUI_IMM8_OPCODE_X1 = 37,
472 XORI_IMM_0_OPCODE_X0 = 2, 472 V1MAXU_RRR_0_OPCODE_X0 = 101,
473 XORI_IMM_0_OPCODE_X1 = 21, 473 V1MAXU_RRR_0_OPCODE_X1 = 64,
474 XOR_SPECIAL_0_OPCODE_X0 = 94, 474 V1MINUI_IMM8_OPCODE_X0 = 13,
475 XOR_SPECIAL_0_OPCODE_X1 = 65, 475 V1MINUI_IMM8_OPCODE_X1 = 38,
476 XOR_SPECIAL_2_OPCODE_Y0 = 3, 476 V1MINU_RRR_0_OPCODE_X0 = 102,
477 XOR_SPECIAL_2_OPCODE_Y1 = 3 477 V1MINU_RRR_0_OPCODE_X1 = 65,
478 V1MNZ_RRR_0_OPCODE_X0 = 103,
479 V1MNZ_RRR_0_OPCODE_X1 = 66,
480 V1MULTU_RRR_0_OPCODE_X0 = 104,
481 V1MULUS_RRR_0_OPCODE_X0 = 105,
482 V1MULU_RRR_0_OPCODE_X0 = 106,
483 V1MZ_RRR_0_OPCODE_X0 = 107,
484 V1MZ_RRR_0_OPCODE_X1 = 67,
485 V1SADAU_RRR_0_OPCODE_X0 = 108,
486 V1SADU_RRR_0_OPCODE_X0 = 109,
487 V1SHLI_SHIFT_OPCODE_X0 = 7,
488 V1SHLI_SHIFT_OPCODE_X1 = 7,
489 V1SHL_RRR_0_OPCODE_X0 = 110,
490 V1SHL_RRR_0_OPCODE_X1 = 68,
491 V1SHRSI_SHIFT_OPCODE_X0 = 8,
492 V1SHRSI_SHIFT_OPCODE_X1 = 8,
493 V1SHRS_RRR_0_OPCODE_X0 = 111,
494 V1SHRS_RRR_0_OPCODE_X1 = 69,
495 V1SHRUI_SHIFT_OPCODE_X0 = 9,
496 V1SHRUI_SHIFT_OPCODE_X1 = 9,
497 V1SHRU_RRR_0_OPCODE_X0 = 112,
498 V1SHRU_RRR_0_OPCODE_X1 = 70,
499 V1SUBUC_RRR_0_OPCODE_X0 = 113,
500 V1SUBUC_RRR_0_OPCODE_X1 = 71,
501 V1SUB_RRR_0_OPCODE_X0 = 114,
502 V1SUB_RRR_0_OPCODE_X1 = 72,
503 V2ADDI_IMM8_OPCODE_X0 = 14,
504 V2ADDI_IMM8_OPCODE_X1 = 39,
505 V2ADDSC_RRR_0_OPCODE_X0 = 115,
506 V2ADDSC_RRR_0_OPCODE_X1 = 73,
507 V2ADD_RRR_0_OPCODE_X0 = 116,
508 V2ADD_RRR_0_OPCODE_X1 = 74,
509 V2ADIFFS_RRR_0_OPCODE_X0 = 117,
510 V2AVGS_RRR_0_OPCODE_X0 = 118,
511 V2CMPEQI_IMM8_OPCODE_X0 = 15,
512 V2CMPEQI_IMM8_OPCODE_X1 = 40,
513 V2CMPEQ_RRR_0_OPCODE_X0 = 119,
514 V2CMPEQ_RRR_0_OPCODE_X1 = 75,
515 V2CMPLES_RRR_0_OPCODE_X0 = 120,
516 V2CMPLES_RRR_0_OPCODE_X1 = 76,
517 V2CMPLEU_RRR_0_OPCODE_X0 = 121,
518 V2CMPLEU_RRR_0_OPCODE_X1 = 77,
519 V2CMPLTSI_IMM8_OPCODE_X0 = 16,
520 V2CMPLTSI_IMM8_OPCODE_X1 = 41,
521 V2CMPLTS_RRR_0_OPCODE_X0 = 122,
522 V2CMPLTS_RRR_0_OPCODE_X1 = 78,
523 V2CMPLTUI_IMM8_OPCODE_X0 = 17,
524 V2CMPLTUI_IMM8_OPCODE_X1 = 42,
525 V2CMPLTU_RRR_0_OPCODE_X0 = 123,
526 V2CMPLTU_RRR_0_OPCODE_X1 = 79,
527 V2CMPNE_RRR_0_OPCODE_X0 = 124,
528 V2CMPNE_RRR_0_OPCODE_X1 = 80,
529 V2DOTPA_RRR_0_OPCODE_X0 = 125,
530 V2DOTP_RRR_0_OPCODE_X0 = 126,
531 V2INT_H_RRR_0_OPCODE_X0 = 127,
532 V2INT_H_RRR_0_OPCODE_X1 = 81,
533 V2INT_L_RRR_0_OPCODE_X0 = 128,
534 V2INT_L_RRR_0_OPCODE_X1 = 82,
535 V2MAXSI_IMM8_OPCODE_X0 = 18,
536 V2MAXSI_IMM8_OPCODE_X1 = 43,
537 V2MAXS_RRR_0_OPCODE_X0 = 129,
538 V2MAXS_RRR_0_OPCODE_X1 = 83,
539 V2MINSI_IMM8_OPCODE_X0 = 19,
540 V2MINSI_IMM8_OPCODE_X1 = 44,
541 V2MINS_RRR_0_OPCODE_X0 = 130,
542 V2MINS_RRR_0_OPCODE_X1 = 84,
543 V2MNZ_RRR_0_OPCODE_X0 = 131,
544 V2MNZ_RRR_0_OPCODE_X1 = 85,
545 V2MULFSC_RRR_0_OPCODE_X0 = 132,
546 V2MULS_RRR_0_OPCODE_X0 = 133,
547 V2MULTS_RRR_0_OPCODE_X0 = 134,
548 V2MZ_RRR_0_OPCODE_X0 = 135,
549 V2MZ_RRR_0_OPCODE_X1 = 86,
550 V2PACKH_RRR_0_OPCODE_X0 = 136,
551 V2PACKH_RRR_0_OPCODE_X1 = 87,
552 V2PACKL_RRR_0_OPCODE_X0 = 137,
553 V2PACKL_RRR_0_OPCODE_X1 = 88,
554 V2PACKUC_RRR_0_OPCODE_X0 = 138,
555 V2PACKUC_RRR_0_OPCODE_X1 = 89,
556 V2SADAS_RRR_0_OPCODE_X0 = 139,
557 V2SADAU_RRR_0_OPCODE_X0 = 140,
558 V2SADS_RRR_0_OPCODE_X0 = 141,
559 V2SADU_RRR_0_OPCODE_X0 = 142,
560 V2SHLI_SHIFT_OPCODE_X0 = 10,
561 V2SHLI_SHIFT_OPCODE_X1 = 10,
562 V2SHLSC_RRR_0_OPCODE_X0 = 143,
563 V2SHLSC_RRR_0_OPCODE_X1 = 90,
564 V2SHL_RRR_0_OPCODE_X0 = 144,
565 V2SHL_RRR_0_OPCODE_X1 = 91,
566 V2SHRSI_SHIFT_OPCODE_X0 = 11,
567 V2SHRSI_SHIFT_OPCODE_X1 = 11,
568 V2SHRS_RRR_0_OPCODE_X0 = 145,
569 V2SHRS_RRR_0_OPCODE_X1 = 92,
570 V2SHRUI_SHIFT_OPCODE_X0 = 12,
571 V2SHRUI_SHIFT_OPCODE_X1 = 12,
572 V2SHRU_RRR_0_OPCODE_X0 = 146,
573 V2SHRU_RRR_0_OPCODE_X1 = 93,
574 V2SUBSC_RRR_0_OPCODE_X0 = 147,
575 V2SUBSC_RRR_0_OPCODE_X1 = 94,
576 V2SUB_RRR_0_OPCODE_X0 = 148,
577 V2SUB_RRR_0_OPCODE_X1 = 95,
578 V4ADDSC_RRR_0_OPCODE_X0 = 149,
579 V4ADDSC_RRR_0_OPCODE_X1 = 96,
580 V4ADD_RRR_0_OPCODE_X0 = 150,
581 V4ADD_RRR_0_OPCODE_X1 = 97,
582 V4INT_H_RRR_0_OPCODE_X0 = 151,
583 V4INT_H_RRR_0_OPCODE_X1 = 98,
584 V4INT_L_RRR_0_OPCODE_X0 = 152,
585 V4INT_L_RRR_0_OPCODE_X1 = 99,
586 V4PACKSC_RRR_0_OPCODE_X0 = 153,
587 V4PACKSC_RRR_0_OPCODE_X1 = 100,
588 V4SHLSC_RRR_0_OPCODE_X0 = 154,
589 V4SHLSC_RRR_0_OPCODE_X1 = 101,
590 V4SHL_RRR_0_OPCODE_X0 = 155,
591 V4SHL_RRR_0_OPCODE_X1 = 102,
592 V4SHRS_RRR_0_OPCODE_X0 = 156,
593 V4SHRS_RRR_0_OPCODE_X1 = 103,
594 V4SHRU_RRR_0_OPCODE_X0 = 157,
595 V4SHRU_RRR_0_OPCODE_X1 = 104,
596 V4SUBSC_RRR_0_OPCODE_X0 = 158,
597 V4SUBSC_RRR_0_OPCODE_X1 = 105,
598 V4SUB_RRR_0_OPCODE_X0 = 159,
599 V4SUB_RRR_0_OPCODE_X1 = 106,
600 WH64_UNARY_OPCODE_X1 = 38,
601 XORI_IMM8_OPCODE_X0 = 20,
602 XORI_IMM8_OPCODE_X1 = 45,
603 XOR_RRR_0_OPCODE_X0 = 160,
604 XOR_RRR_0_OPCODE_X1 = 107,
605 XOR_RRR_5_OPCODE_Y0 = 3,
606 XOR_RRR_5_OPCODE_Y1 = 3
478}; 607};
479 608
480#endif /* !_TILE_OPCODE_CONSTANTS_H */ 609#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/pgtable_64.h b/arch/tile/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..fd80328523b4
--- /dev/null
+++ b/arch/tile/include/asm/pgtable_64.h
@@ -0,0 +1,175 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#ifndef _ASM_TILE_PGTABLE_64_H
17#define _ASM_TILE_PGTABLE_64_H
18
19/* The level-0 page table breaks the address space into 32-bit chunks. */
20#define PGDIR_SHIFT HV_LOG2_L1_SPAN
21#define PGDIR_SIZE HV_L1_SPAN
22#define PGDIR_MASK (~(PGDIR_SIZE-1))
23#define PTRS_PER_PGD HV_L0_ENTRIES
24#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
25
26/*
27 * The level-1 index is defined by the huge page size. A PMD is composed
28 * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
29 */
30#define PMD_SHIFT HV_LOG2_PAGE_SIZE_LARGE
31#define PMD_SIZE HV_PAGE_SIZE_LARGE
32#define PMD_MASK (~(PMD_SIZE-1))
33#define PTRS_PER_PMD (1 << (PGDIR_SHIFT - PMD_SHIFT))
34#define SIZEOF_PMD (PTRS_PER_PMD * sizeof(pmd_t))
35
36/*
37 * The level-2 index is defined by the difference between the huge
38 * page size and the normal page size. A PTE is composed of
39 * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
40 * Note that the hypervisor docs use PTE for what we call pte_t, so
41 * this nomenclature is somewhat confusing.
42 */
43#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
44#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
45
46/*
47 * Align the vmalloc area to an L2 page table, and leave a guard page
48 * at the beginning and end. The vmalloc code also puts in an internal
49 * guard page between each allocation.
50 */
51#define _VMALLOC_END HUGE_VMAP_BASE
52#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
53#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
54
55#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
56
57#ifndef __ASSEMBLY__
58
59/* We have no pud since we are a three-level page table. */
60#include <asm-generic/pgtable-nopud.h>
61
62static inline int pud_none(pud_t pud)
63{
64 return pud_val(pud) == 0;
65}
66
67static inline int pud_present(pud_t pud)
68{
69 return pud_val(pud) & _PAGE_PRESENT;
70}
71
72#define pmd_ERROR(e) \
73 pr_err("%s:%d: bad pmd 0x%016llx.\n", __FILE__, __LINE__, pmd_val(e))
74
75static inline void pud_clear(pud_t *pudp)
76{
77 __pte_clear(&pudp->pgd);
78}
79
80static inline int pud_bad(pud_t pud)
81{
82 return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
83}
84
85/* Return the page-table frame number (ptfn) that a pud_t points at. */
86#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
87
88/*
89 * A given kernel pud_t maps to a kernel pmd_t table at a specific
90 * virtual address. Since kernel pmd_t tables can be aligned at
91 * sub-page granularity, this macro can return non-page-aligned
92 * pointers, despite its name.
93 */
94#define pud_page_vaddr(pud) \
95 (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
96
97/*
98 * A pud_t points to a pmd_t array. Since we can have multiple per
99 * page, we don't have a one-to-one mapping of pud_t's to pages.
100 */
101#define pud_page(pud) pfn_to_page(HV_PTFN_TO_PFN(pud_ptfn(pud)))
102
103static inline unsigned long pud_index(unsigned long address)
104{
105 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
106}
107
108#define pmd_offset(pud, address) \
109 ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
110
111static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
112{
113 set_pte(pmdp, pmdval);
114}
115
116/* Create a pmd from a PTFN and pgprot. */
117static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
118{
119 return hv_pte_set_ptfn(prot, ptfn);
120}
121
122/* Return the page-table frame number (ptfn) that a pmd_t points at. */
123static inline unsigned long pmd_ptfn(pmd_t pmd)
124{
125 return hv_pte_get_ptfn(pmd);
126}
127
128static inline void pmd_clear(pmd_t *pmdp)
129{
130 __pte_clear(pmdp);
131}
132
133/* Normalize an address to having the correct high bits set. */
134#define pgd_addr_normalize pgd_addr_normalize
135static inline unsigned long pgd_addr_normalize(unsigned long addr)
136{
137 return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
138 (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
139}
140
141/* We don't define any pgds for these addresses. */
142static inline int pgd_addr_invalid(unsigned long addr)
143{
144 return addr >= MEM_HV_START ||
145 (addr > MEM_LOW_END && addr < MEM_HIGH_START);
146}
147
148/*
149 * Use atomic instructions to provide atomicity against the hypervisor.
150 */
151#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
152static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
153 unsigned long addr, pte_t *ptep)
154{
155 return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
156 HV_PTE_INDEX_ACCESSED) & 0x1;
157}
158
159#define __HAVE_ARCH_PTEP_SET_WRPROTECT
160static inline void ptep_set_wrprotect(struct mm_struct *mm,
161 unsigned long addr, pte_t *ptep)
162{
163 __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
164}
165
166#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
167static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
168 unsigned long addr, pte_t *ptep)
169{
170 return hv_pte(__insn_exch(&ptep->val, 0UL));
171}
172
173#endif /* __ASSEMBLY__ */
174
175#endif /* _ASM_TILE_PGTABLE_64_H */
diff --git a/arch/tile/include/asm/spinlock_64.h b/arch/tile/include/asm/spinlock_64.h
new file mode 100644
index 000000000000..72be5904e020
--- /dev/null
+++ b/arch/tile/include/asm/spinlock_64.h
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
15 * (the type definitions are in asm/spinlock_types.h)
16 */
17
18#ifndef _ASM_TILE_SPINLOCK_64_H
19#define _ASM_TILE_SPINLOCK_64_H
20
21/* Shifts and masks for the various fields in "lock". */
22#define __ARCH_SPIN_CURRENT_SHIFT 17
23#define __ARCH_SPIN_NEXT_MASK 0x7fff
24#define __ARCH_SPIN_NEXT_OVERFLOW 0x8000
25
26/*
27 * Return the "current" portion of a ticket lock value,
28 * i.e. the number that currently owns the lock.
29 */
30static inline int arch_spin_current(u32 val)
31{
32 return val >> __ARCH_SPIN_CURRENT_SHIFT;
33}
34
35/*
36 * Return the "next" portion of a ticket lock value,
37 * i.e. the number that the next task to try to acquire the lock will get.
38 */
39static inline int arch_spin_next(u32 val)
40{
41 return val & __ARCH_SPIN_NEXT_MASK;
42}
43
44/* The lock is locked if a task would have to wait to get it. */
45static inline int arch_spin_is_locked(arch_spinlock_t *lock)
46{
47 u32 val = lock->lock;
48 return arch_spin_current(val) != arch_spin_next(val);
49}
50
51/* Bump the current ticket so the next task owns the lock. */
52static inline void arch_spin_unlock(arch_spinlock_t *lock)
53{
54 wmb(); /* guarantee anything modified under the lock is visible */
55 __insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
56}
57
58void arch_spin_unlock_wait(arch_spinlock_t *lock);
59
60void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
61
62/* Grab the "next" ticket number and bump it atomically.
63 * If the current ticket is not ours, go to the slow path.
64 * We also take the slow path if the "next" value overflows.
65 */
66static inline void arch_spin_lock(arch_spinlock_t *lock)
67{
68 u32 val = __insn_fetchadd4(&lock->lock, 1);
69 u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
70 if (unlikely(arch_spin_current(val) != ticket))
71 arch_spin_lock_slow(lock, ticket);
72}
73
74/* Try to get the lock, and return whether we succeeded. */
75int arch_spin_trylock(arch_spinlock_t *lock);
76
77/* We cannot take an interrupt after getting a ticket, so don't enable them. */
78#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
79
80/*
81 * Read-write spinlocks, allowing multiple readers
82 * but only one writer.
83 *
84 * We use fetchadd() for readers, and fetchor() with the sign bit
85 * for writers.
86 */
87
88#define __WRITE_LOCK_BIT (1 << 31)
89
90static inline int arch_write_val_locked(int val)
91{
92 return val < 0; /* Optimize "val & __WRITE_LOCK_BIT". */
93}
94
95/**
96 * read_can_lock - would read_trylock() succeed?
97 * @lock: the rwlock in question.
98 */
99static inline int arch_read_can_lock(arch_rwlock_t *rw)
100{
101 return !arch_write_val_locked(rw->lock);
102}
103
104/**
105 * write_can_lock - would write_trylock() succeed?
106 * @lock: the rwlock in question.
107 */
108static inline int arch_write_can_lock(arch_rwlock_t *rw)
109{
110 return rw->lock == 0;
111}
112
113extern void __read_lock_failed(arch_rwlock_t *rw);
114
115static inline void arch_read_lock(arch_rwlock_t *rw)
116{
117 u32 val = __insn_fetchaddgez4(&rw->lock, 1);
118 if (unlikely(arch_write_val_locked(val)))
119 __read_lock_failed(rw);
120}
121
122extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
123
124static inline void arch_write_lock(arch_rwlock_t *rw)
125{
126 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
127 if (unlikely(val != 0))
128 __write_lock_failed(rw, val);
129}
130
131static inline void arch_read_unlock(arch_rwlock_t *rw)
132{
133 __insn_mf();
134 __insn_fetchadd4(&rw->lock, -1);
135}
136
137static inline void arch_write_unlock(arch_rwlock_t *rw)
138{
139 __insn_mf();
140 rw->lock = 0;
141}
142
143static inline int arch_read_trylock(arch_rwlock_t *rw)
144{
145 return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
146}
147
148static inline int arch_write_trylock(arch_rwlock_t *rw)
149{
150 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
151 if (likely(val == 0))
152 return 1;
153 if (!arch_write_val_locked(val))
154 __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
155 return 0;
156}
157
158#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
159#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
160
161#endif /* _ASM_TILE_SPINLOCK_64_H */
diff --git a/arch/tile/kernel/futex_64.S b/arch/tile/kernel/futex_64.S
new file mode 100644
index 000000000000..f465d1eda20f
--- /dev/null
+++ b/arch/tile/kernel/futex_64.S
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Atomically access user memory, but use MMU to avoid propagating
15 * kernel exceptions.
16 */
17
18#include <linux/linkage.h>
19#include <asm/errno.h>
20#include <asm/futex.h>
21#include <asm/page.h>
22#include <asm/processor.h>
23
24/*
25 * Provide a set of atomic memory operations supporting <asm/futex.h>.
26 *
27 * r0: user address to manipulate
28 * r1: new value to write, or for cmpxchg, old value to compare against
29 * r2: (cmpxchg only) new value to write
30 *
31 * Return __get_user struct, r0 with value, r1 with error.
32 */
33#define FUTEX_OP(name, ...) \
34STD_ENTRY(futex_##name) \
35 __VA_ARGS__; \
36 { \
37 move r1, zero; \
38 jrp lr \
39 }; \
40 STD_ENDPROC(futex_##name); \
41 .pushsection __ex_table,"a"; \
42 .quad 1b, get_user_fault; \
43 .popsection
44
45 .pushsection .fixup,"ax"
46get_user_fault:
47 { movei r1, -EFAULT; jrp lr }
48 ENDPROC(get_user_fault)
49 .popsection
50
51FUTEX_OP(cmpxchg, mtspr CMPEXCH_VALUE, r1; 1: cmpexch4 r0, r0, r2)
52FUTEX_OP(set, 1: exch4 r0, r0, r1)
53FUTEX_OP(add, 1: fetchadd4 r0, r0, r1)
54FUTEX_OP(or, 1: fetchor4 r0, r0, r1)
55FUTEX_OP(andn, nor r1, r1, zero; 1: fetchand4 r0, r0, r1)
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S
new file mode 100644
index 000000000000..6bc3a932fe45
--- /dev/null
+++ b/arch/tile/kernel/head_64.S
@@ -0,0 +1,269 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * TILE startup code.
15 */
16
17#include <linux/linkage.h>
18#include <linux/init.h>
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/thread_info.h>
22#include <asm/processor.h>
23#include <asm/asm-offsets.h>
24#include <hv/hypervisor.h>
25#include <arch/chip.h>
26#include <arch/spr_def.h>
27
28/*
29 * This module contains the entry code for kernel images. It performs the
30 * minimal setup needed to call the generic C routines.
31 */
32
33 __HEAD
34ENTRY(_start)
35 /* Notify the hypervisor of what version of the API we want */
36 {
37 movei r1, TILE_CHIP
38 movei r2, TILE_CHIP_REV
39 }
40 {
41 moveli r0, _HV_VERSION
42 jal hv_init
43 }
44 /* Get a reasonable default ASID in r0 */
45 {
46 move r0, zero
47 jal hv_inquire_asid
48 }
49
50 /*
51 * Install the default page table. The relocation required to
52 * statically define the table is a bit too complex, so we have
53 * to plug in the pointer from the L0 to the L1 table by hand.
54 * We only do this on the first cpu to boot, though, since the
55 * other CPUs should see a properly-constructed page table.
56 */
57 {
58 v4int_l r2, zero, r0 /* ASID for hv_install_context */
59 moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
60 }
61 {
62 shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
63 }
64 {
65 ld r1, r4 /* access_pte for hv_install_context */
66 }
67 {
68 moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
69 moveli r6, hw1_last(temp_data_pmd - PAGE_OFFSET)
70 }
71 {
72 /* After initializing swapper_pgprot, HV_PTE_GLOBAL is set. */
73 bfextu r7, r1, HV_PTE_INDEX_GLOBAL, HV_PTE_INDEX_GLOBAL
74 inv r4
75 }
76 bnez r7, .Lno_write
77 {
78 shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
79 shl16insli r6, r6, hw0(temp_data_pmd - PAGE_OFFSET)
80 }
81 {
82 /* Cut off the low bits of the PT address. */
83 shrui r6, r6, HV_LOG2_PAGE_TABLE_ALIGN
84 /* Start with our access pte. */
85 move r5, r1
86 }
87 {
88 /* Stuff the address into the page table pointer slot of the PTE. */
89 bfins r5, r6, HV_PTE_INDEX_PTFN, \
90 HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
91 }
92 {
93 /* Store the L0 data PTE. */
94 st r0, r5
95 addli r6, r6, (temp_code_pmd - temp_data_pmd) >> \
96 HV_LOG2_PAGE_TABLE_ALIGN
97 }
98 {
99 addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
100 bfins r5, r6, HV_PTE_INDEX_PTFN, \
101 HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
102 }
103 /* Store the L0 code PTE. */
104 st r0, r5
105
106.Lno_write:
107 moveli lr, hw2_last(1f)
108 {
109 shl16insli lr, lr, hw1(1f)
110 moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
111 }
112 {
113 shl16insli lr, lr, hw0(1f)
114 shl16insli r0, r0, hw0(swapper_pg_dir - PAGE_OFFSET)
115 }
116 {
117 move r3, zero
118 j hv_install_context
119 }
1201:
121
122 /* Install the interrupt base. */
123 moveli r0, hw2_last(MEM_SV_START)
124 shl16insli r0, r0, hw1(MEM_SV_START)
125 shl16insli r0, r0, hw0(MEM_SV_START)
126 mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0
127
128 /*
129 * Get our processor number and save it away in SAVE_K_0.
130 * Extract stuff from the topology structure: r4 = y, r6 = x,
131 * r5 = width. FIXME: consider whether we want to just make these
132 * 64-bit values (and if so fix smp_topology write below, too).
133 */
134 jal hv_inquire_topology
135 {
136 v4int_l r5, zero, r1 /* r5 = width */
137 shrui r4, r0, 32 /* r4 = y */
138 }
139 {
140 v4int_l r6, zero, r0 /* r6 = x */
141 mul_lu_lu r4, r4, r5
142 }
143 {
144 add r4, r4, r6 /* r4 == cpu == y*width + x */
145 }
146
147#ifdef CONFIG_SMP
148 /*
149 * Load up our per-cpu offset. When the first (master) tile
150 * boots, this value is still zero, so we will load boot_pc
151 * with start_kernel, and boot_sp with init_stack + THREAD_SIZE.
152 * The master tile initializes the per-cpu offset array, so that
153 * when subsequent (secondary) tiles boot, they will instead load
154 * from their per-cpu versions of boot_sp and boot_pc.
155 */
156 moveli r5, hw2_last(__per_cpu_offset)
157 shl16insli r5, r5, hw1(__per_cpu_offset)
158 shl16insli r5, r5, hw0(__per_cpu_offset)
159 shl3add r5, r4, r5
160 ld r5, r5
161 bnez r5, 1f
162
163 /*
164 * Save the width and height to the smp_topology variable
165 * for later use.
166 */
167 moveli r0, hw2_last(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
168 shl16insli r0, r0, hw1(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
169 shl16insli r0, r0, hw0(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
170 st r0, r1
1711:
172#else
173 move r5, zero
174#endif
175
176 /* Load and go with the correct pc and sp. */
177 {
178 moveli r1, hw2_last(boot_sp)
179 moveli r0, hw2_last(boot_pc)
180 }
181 {
182 shl16insli r1, r1, hw1(boot_sp)
183 shl16insli r0, r0, hw1(boot_pc)
184 }
185 {
186 shl16insli r1, r1, hw0(boot_sp)
187 shl16insli r0, r0, hw0(boot_pc)
188 }
189 {
190 add r1, r1, r5
191 add r0, r0, r5
192 }
193 ld r0, r0
194 ld sp, r1
195 or r4, sp, r4
196 mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
197 addi sp, sp, -STACK_TOP_DELTA
198 {
199 move lr, zero /* stop backtraces in the called function */
200 jr r0
201 }
202 ENDPROC(_start)
203
204__PAGE_ALIGNED_BSS
205 .align PAGE_SIZE
206ENTRY(empty_zero_page)
207 .fill PAGE_SIZE,1,0
208 END(empty_zero_page)
209
210 .macro PTE cpa, bits1
211 .quad HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED |\
212 HV_PTE_GLOBAL | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) |\
213 (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN)
214 .endm
215
216__PAGE_ALIGNED_DATA
217 .align PAGE_SIZE
218ENTRY(swapper_pg_dir)
219 .org swapper_pg_dir + HV_L0_INDEX(PAGE_OFFSET) * HV_PTE_SIZE
220.Lsv_data_pmd:
221 .quad 0 /* PTE temp_data_pmd - PAGE_OFFSET, 0 */
222 .org swapper_pg_dir + HV_L0_INDEX(MEM_SV_START) * HV_PTE_SIZE
223.Lsv_code_pmd:
224 .quad 0 /* PTE temp_code_pmd - PAGE_OFFSET, 0 */
225 .org swapper_pg_dir + HV_L0_SIZE
226 END(swapper_pg_dir)
227
228 .align HV_PAGE_TABLE_ALIGN
229ENTRY(temp_data_pmd)
230 /*
231 * We fill the PAGE_OFFSET pmd with huge pages with
232 * VA = PA + PAGE_OFFSET. We remap things with more precise access
233 * permissions later.
234 */
235 .set addr, 0
236 .rept HV_L1_ENTRIES
237 PTE addr, HV_PTE_READABLE | HV_PTE_WRITABLE
238 .set addr, addr + HV_PAGE_SIZE_LARGE
239 .endr
240 .org temp_data_pmd + HV_L1_SIZE
241 END(temp_data_pmd)
242
243 .align HV_PAGE_TABLE_ALIGN
244ENTRY(temp_code_pmd)
245 /*
246 * We fill the MEM_SV_START pmd with huge pages with
247 * VA = PA + PAGE_OFFSET. We remap things with more precise access
248 * permissions later.
249 */
250 .set addr, 0
251 .rept HV_L1_ENTRIES
252 PTE addr, HV_PTE_READABLE | HV_PTE_EXECUTABLE
253 .set addr, addr + HV_PAGE_SIZE_LARGE
254 .endr
255 .org temp_code_pmd + HV_L1_SIZE
256 END(temp_code_pmd)
257
258 /*
259 * Isolate swapper_pgprot to its own cache line, since each cpu
260 * starting up will read it using VA-is-PA and local homing.
261 * This would otherwise likely conflict with other data on the cache
262 * line, once we have set its permanent home in the page tables.
263 */
264 __INITDATA
265 .align CHIP_L2_LINE_SIZE()
266ENTRY(swapper_pgprot)
267 .quad HV_PTE_PRESENT | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
268 .align CHIP_L2_LINE_SIZE()
269 END(swapper_pgprot)
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
new file mode 100644
index 000000000000..79c93e10ba27
--- /dev/null
+++ b/arch/tile/kernel/intvec_64.S
@@ -0,0 +1,1231 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Linux interrupt vectors.
15 */
16
17#include <linux/linkage.h>
18#include <linux/errno.h>
19#include <linux/unistd.h>
20#include <asm/ptrace.h>
21#include <asm/thread_info.h>
22#include <asm/irqflags.h>
23#include <asm/asm-offsets.h>
24#include <asm/types.h>
25#include <hv/hypervisor.h>
26#include <arch/abi.h>
27#include <arch/interrupts.h>
28#include <arch/spr_def.h>
29
30#ifdef CONFIG_PREEMPT
31# error "No support for kernel preemption currently"
32#endif
33
34#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
35
36#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
37
38
39 .macro push_reg reg, ptr=sp, delta=-8
40 {
41 st \ptr, \reg
42 addli \ptr, \ptr, \delta
43 }
44 .endm
45
46 .macro pop_reg reg, ptr=sp, delta=8
47 {
48 ld \reg, \ptr
49 addli \ptr, \ptr, \delta
50 }
51 .endm
52
53 .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
54 {
55 move \zreg, zero
56 ld \reg, \ptr
57 addi \ptr, \ptr, \delta
58 }
59 .endm
60
61 .macro push_extra_callee_saves reg
62 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
63 push_reg r51, \reg
64 push_reg r50, \reg
65 push_reg r49, \reg
66 push_reg r48, \reg
67 push_reg r47, \reg
68 push_reg r46, \reg
69 push_reg r45, \reg
70 push_reg r44, \reg
71 push_reg r43, \reg
72 push_reg r42, \reg
73 push_reg r41, \reg
74 push_reg r40, \reg
75 push_reg r39, \reg
76 push_reg r38, \reg
77 push_reg r37, \reg
78 push_reg r36, \reg
79 push_reg r35, \reg
80 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
81 .endm
82
83 .macro panic str
84 .pushsection .rodata, "a"
851:
86 .asciz "\str"
87 .popsection
88 {
89 moveli r0, hw2_last(1b)
90 }
91 {
92 shl16insli r0, r0, hw1(1b)
93 }
94 {
95 shl16insli r0, r0, hw0(1b)
96 jal panic
97 }
98 .endm
99
100
101#ifdef __COLLECT_LINKER_FEEDBACK__
102 .pushsection .text.intvec_feedback,"ax"
103intvec_feedback:
104 .popsection
105#endif
106
107 /*
108 * Default interrupt handler.
109 *
110 * vecnum is where we'll put this code.
111 * c_routine is the C routine we'll call.
112 *
113 * The C routine is passed two arguments:
114 * - A pointer to the pt_regs state.
115 * - The interrupt vector number.
116 *
117 * The "processing" argument specifies the code for processing
118 * the interrupt. Defaults to "handle_interrupt".
119 */
120 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
121 .org (\vecnum << 8)
122intvec_\vecname:
123 /* Temporarily save a register so we have somewhere to work. */
124
125 mtspr SPR_SYSTEM_SAVE_K_1, r0
126 mfspr r0, SPR_EX_CONTEXT_K_1
127
128 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
129
130 .ifc \vecnum, INT_DOUBLE_FAULT
131 /*
132 * For double-faults from user-space, fall through to the normal
133 * register save and stack setup path. Otherwise, it's the
134 * hypervisor giving us one last chance to dump diagnostics, and we
135 * branch to the kernel_double_fault routine to do so.
136 */
137 beqz r0, 1f
138 j _kernel_double_fault
1391:
140 .else
141 /*
142 * If we're coming from user-space, then set sp to the top of
143 * the kernel stack. Otherwise, assume sp is already valid.
144 */
145 {
146 bnez r0, 0f
147 move r0, sp
148 }
149 .endif
150
151 .ifc \c_routine, do_page_fault
152 /*
153 * The page_fault handler may be downcalled directly by the
154 * hypervisor even when Linux is running and has ICS set.
155 *
156 * In this case the contents of EX_CONTEXT_K_1 reflect the
157 * previous fault and can't be relied on to choose whether or
158 * not to reinitialize the stack pointer. So we add a test
159 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
160 * and if so we don't reinitialize sp, since we must be coming
161 * from Linux. (In fact the precise case is !(val & ~1),
162 * but any Linux PC has to have the high bit set.)
163 *
164 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
165 * any path that turns into a downcall to one of our TLB handlers.
166 *
167 * FIXME: if we end up never using this path, perhaps we should
168 * prevent the hypervisor from generating downcalls in this case.
169 * The advantage of getting a downcall is we can panic in Linux.
170 */
171 mfspr r0, SPR_SYSTEM_SAVE_K_2
172 {
173 bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
174 move r0, sp
175 }
176 .endif
177
178
179 /*
180 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
181 * the current stack top in the higher bits. So we recover
182 * our stack top by just masking off the low bits, then
183 * point sp at the top aligned address on the actual stack page.
184 */
185 mfspr r0, SPR_SYSTEM_SAVE_K_0
186 mm r0, zero, LOG2_THREAD_SIZE, 63
187
1880:
189 /*
190 * Align the stack mod 64 so we can properly predict what
191 * cache lines we need to write-hint to reduce memory fetch
192 * latency as we enter the kernel. The layout of memory is
193 * as follows, with cache line 0 at the lowest VA, and cache
194 * line 8 just below the r0 value this "andi" computes.
195 * Note that we never write to cache line 8, and we skip
196 * cache lines 1-3 for syscalls.
197 *
198 * cache line 8: ptregs padding (two words)
199 * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
200 * cache line 6: r46...r53 (tp)
201 * cache line 5: r38...r45
202 * cache line 4: r30...r37
203 * cache line 3: r22...r29
204 * cache line 2: r14...r21
205 * cache line 1: r6...r13
206 * cache line 0: 2 x frame, r0..r5
207 */
208 andi r0, r0, -64
209
210 /*
211 * Push the first four registers on the stack, so that we can set
212 * them to vector-unique values before we jump to the common code.
213 *
214 * Registers are pushed on the stack as a struct pt_regs,
215 * with the sp initially just above the struct, and when we're
216 * done, sp points to the base of the struct, minus
217 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
218 *
219 * This routine saves just the first four registers, plus the
220 * stack context so we can do proper backtracing right away,
221 * and defers to handle_interrupt to save the rest.
222 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.
223 */
224 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
225 wh64 r0 /* cache line 7 */
226 {
227 st r0, lr
228 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
229 }
230 {
231 st r0, sp
232 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
233 }
234 wh64 sp /* cache line 6 */
235 {
236 st sp, r52
237 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
238 }
239 wh64 sp /* cache line 0 */
240 {
241 st sp, r1
242 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
243 }
244 {
245 st sp, r2
246 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
247 }
248 {
249 st sp, r3
250 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
251 }
252 mfspr r0, SPR_EX_CONTEXT_K_0
253 .ifc \processing,handle_syscall
254 /*
255 * Bump the saved PC by one bundle so that when we return, we won't
256 * execute the same swint instruction again. We need to do this while
257 * we're in the critical section.
258 */
259 addi r0, r0, 8
260 .endif
261 {
262 st sp, r0
263 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
264 }
265 mfspr r0, SPR_EX_CONTEXT_K_1
266 {
267 st sp, r0
268 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
269 /*
270 * Use r0 for syscalls so it's a temporary; use r1 for interrupts
271 * so that it gets passed through unchanged to the handler routine.
272 * Note that the .if conditional confusingly spans bundles.
273 */
274 .ifc \processing,handle_syscall
275 movei r0, \vecnum
276 }
277 {
278 st sp, r0
279 .else
280 movei r1, \vecnum
281 }
282 {
283 st sp, r1
284 .endif
285 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
286 }
287 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
288 {
289 st sp, r0
290 addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
291 }
292 {
293 st sp, zero /* write zero into "Next SP" frame pointer */
294 addi sp, sp, -8 /* leave SP pointing at bottom of frame */
295 }
296 .ifc \processing,handle_syscall
297 j handle_syscall
298 .else
299 /* Capture per-interrupt SPR context to registers. */
300 .ifc \c_routine, do_page_fault
301 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
302 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
303 .else
304 .ifc \vecnum, INT_ILL_TRANS
305 mfspr r2, ILL_TRANS_REASON
306 .else
307 .ifc \vecnum, INT_DOUBLE_FAULT
308 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
309 .else
310 .ifc \c_routine, do_trap
311 mfspr r2, GPV_REASON
312 .else
313 .ifc \c_routine, op_handle_perf_interrupt
314 mfspr r2, PERF_COUNT_STS
315#if CHIP_HAS_AUX_PERF_COUNTERS()
316 .else
317 .ifc \c_routine, op_handle_aux_perf_interrupt
318 mfspr r2, AUX_PERF_COUNT_STS
319 .endif
320#endif
321 .endif
322 .endif
323 .endif
324 .endif
325 .endif
326 /* Put function pointer in r0 */
327 moveli r0, hw2_last(\c_routine)
328 shl16insli r0, r0, hw1(\c_routine)
329 {
330 shl16insli r0, r0, hw0(\c_routine)
331 j \processing
332 }
333 .endif
334 ENDPROC(intvec_\vecname)
335
336#ifdef __COLLECT_LINKER_FEEDBACK__
337 .pushsection .text.intvec_feedback,"ax"
338 .org (\vecnum << 5)
339 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
340 jrp lr
341 .popsection
342#endif
343
344 .endm
345
346
347 /*
348 * Save the rest of the registers that we didn't save in the actual
349 * vector itself. We can't use r0-r10 inclusive here.
350 */
351 .macro finish_interrupt_save, function
352
353 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
354 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
355 {
356 .ifc \function,handle_syscall
357 st r52, r0
358 .else
359 st r52, zero
360 .endif
361 PTREGS_PTR(r52, PTREGS_OFFSET_TP)
362 }
363 st r52, tp
364 {
365 mfspr tp, CMPEXCH_VALUE
366 PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
367 }
368
369 /*
370 * For ordinary syscalls, we save neither caller- nor callee-
371 * save registers, since the syscall invoker doesn't expect the
372 * caller-saves to be saved, and the called kernel functions will
373 * take care of saving the callee-saves for us.
374 *
375 * For interrupts we save just the caller-save registers. Saving
376 * them is required (since the "caller" can't save them). Again,
377 * the called kernel functions will restore the callee-save
378 * registers for us appropriately.
379 *
380 * On return, we normally restore nothing special for syscalls,
381 * and just the caller-save registers for interrupts.
382 *
383 * However, there are some important caveats to all this:
384 *
385 * - We always save a few callee-save registers to give us
386 * some scratchpad registers to carry across function calls.
387 *
388 * - fork/vfork/etc require us to save all the callee-save
389 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
390 *
391 * - We always save r0..r5 and r10 for syscalls, since we need
392 * to reload them a bit later for the actual kernel call, and
393 * since we might need them for -ERESTARTNOINTR, etc.
394 *
395 * - Before invoking a signal handler, we save the unsaved
396 * callee-save registers so they are visible to the
397 * signal handler or any ptracer.
398 *
399 * - If the unsaved callee-save registers are modified, we set
400 * a bit in pt_regs so we know to reload them from pt_regs
401 * and not just rely on the kernel function unwinding.
402 * (Done for ptrace register writes and SA_SIGINFO handler.)
403 */
404 {
405 st r52, tp
406 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
407 }
408 wh64 r52 /* cache line 4 */
409 push_reg r33, r52
410 push_reg r32, r52
411 push_reg r31, r52
412 .ifc \function,handle_syscall
413 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
414 push_reg TREG_SYSCALL_NR_NAME, r52, \
415 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
416 .else
417
418 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
419 wh64 r52 /* cache line 3 */
420 push_reg r29, r52
421 push_reg r28, r52
422 push_reg r27, r52
423 push_reg r26, r52
424 push_reg r25, r52
425 push_reg r24, r52
426 push_reg r23, r52
427 push_reg r22, r52
428 wh64 r52 /* cache line 2 */
429 push_reg r21, r52
430 push_reg r20, r52
431 push_reg r19, r52
432 push_reg r18, r52
433 push_reg r17, r52
434 push_reg r16, r52
435 push_reg r15, r52
436 push_reg r14, r52
437 wh64 r52 /* cache line 1 */
438 push_reg r13, r52
439 push_reg r12, r52
440 push_reg r11, r52
441 push_reg r10, r52
442 push_reg r9, r52
443 push_reg r8, r52
444 push_reg r7, r52
445 push_reg r6, r52
446
447 .endif
448
449 push_reg r5, r52
450 st r52, r4
451
452 /* Load tp with our per-cpu offset. */
453#ifdef CONFIG_SMP
454 {
455 mfspr r20, SPR_SYSTEM_SAVE_K_0
456 moveli r21, hw2_last(__per_cpu_offset)
457 }
458 {
459 shl16insli r21, r21, hw1(__per_cpu_offset)
460 bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
461 }
462 shl16insli r21, r21, hw0(__per_cpu_offset)
463 shl3add r20, r20, r21
464 ld tp, r20
465#else
466 move tp, zero
467#endif
468
469 /*
470 * If we will be returning to the kernel, we will need to
471 * reset the interrupt masks to the state they had before.
472 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
473 */
474 mfspr r32, SPR_EX_CONTEXT_K_1
475 {
476 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
477 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
478 }
479 beqzt r32, 1f /* zero if from user space */
480 IRQS_DISABLED(r32) /* zero if irqs enabled */
481#if PT_FLAGS_DISABLE_IRQ != 1
482# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
483#endif
4841:
485 .ifnc \function,handle_syscall
486 /* Record the fact that we saved the caller-save registers above. */
487 ori r32, r32, PT_FLAGS_CALLER_SAVES
488 .endif
489 st r21, r32
490
491#ifdef __COLLECT_LINKER_FEEDBACK__
492 /*
493 * Notify the feedback routines that we were in the
494 * appropriate fixed interrupt vector area. Note that we
495 * still have ICS set at this point, so we can't invoke any
496 * atomic operations or we will panic. The feedback
497 * routines internally preserve r0..r10 and r30 up.
498 */
499 .ifnc \function,handle_syscall
500 shli r20, r1, 5
501 .else
502 moveli r20, INT_SWINT_1 << 5
503 .endif
504 moveli r21, hw2_last(intvec_feedback)
505 shl16insli r21, r21, hw1(intvec_feedback)
506 shl16insli r21, r21, hw0(intvec_feedback)
507 add r20, r20, r21
508 jalr r20
509
510 /* And now notify the feedback routines that we are here. */
511 FEEDBACK_ENTER(\function)
512#endif
513
514 /*
515 * we've captured enough state to the stack (including in
516 * particular our EX_CONTEXT state) that we can now release
517 * the interrupt critical section and replace it with our
518 * standard "interrupts disabled" mask value. This allows
519 * synchronous interrupts (and profile interrupts) to punch
520 * through from this point onwards.
521 */
522 .ifc \function,handle_nmi
523 IRQ_DISABLE_ALL(r20)
524 .else
525 IRQ_DISABLE(r20, r21)
526 .endif
527 mtspr INTERRUPT_CRITICAL_SECTION, zero
528
529 /*
530 * Prepare the first 256 stack bytes to be rapidly accessible
531 * without having to fetch the background data.
532 */
533 addi r52, sp, -64
534 {
535 wh64 r52
536 addi r52, r52, -64
537 }
538 {
539 wh64 r52
540 addi r52, r52, -64
541 }
542 {
543 wh64 r52
544 addi r52, r52, -64
545 }
546 wh64 r52
547
548#ifdef CONFIG_TRACE_IRQFLAGS
549 .ifnc \function,handle_nmi
550 /*
551 * We finally have enough state set up to notify the irq
552 * tracing code that irqs were disabled on entry to the handler.
553 * The TRACE_IRQS_OFF call clobbers registers r0-r29.
554 * For syscalls, we already have the register state saved away
555 * on the stack, so we don't bother to do any register saves here,
556 * and later we pop the registers back off the kernel stack.
557 * For interrupt handlers, save r0-r3 in callee-saved registers.
558 */
559 .ifnc \function,handle_syscall
560 { move r30, r0; move r31, r1 }
561 { move r32, r2; move r33, r3 }
562 .endif
563 TRACE_IRQS_OFF
564 .ifnc \function,handle_syscall
565 { move r0, r30; move r1, r31 }
566 { move r2, r32; move r3, r33 }
567 .endif
568 .endif
569#endif
570
571 .endm
572
573 /*
574 * Redispatch a downcall.
575 */
576 .macro dc_dispatch vecnum, vecname
577 .org (\vecnum << 8)
578intvec_\vecname:
579 j hv_downcall_dispatch
580 ENDPROC(intvec_\vecname)
581 .endm
582
583 /*
584 * Common code for most interrupts. The C function we're eventually
585 * going to is in r0, and the faultnum is in r1; the original
586 * values for those registers are on the stack.
587 */
588 .pushsection .text.handle_interrupt,"ax"
589handle_interrupt:
590 finish_interrupt_save handle_interrupt
591
592 /* Jump to the C routine; it should enable irqs as soon as possible. */
593 {
594 jalr r0
595 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
596 }
597 FEEDBACK_REENTER(handle_interrupt)
598 {
599 movei r30, 0 /* not an NMI */
600 j interrupt_return
601 }
602 STD_ENDPROC(handle_interrupt)
603
604/*
605 * This routine takes a boolean in r30 indicating if this is an NMI.
606 * If so, we also expect a boolean in r31 indicating whether to
607 * re-enable the oprofile interrupts.
608 */
609STD_ENTRY(interrupt_return)
610 /* If we're resuming to kernel space, don't check thread flags. */
611 {
612 bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
613 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
614 }
615 ld r29, r29
616 andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
617 {
618 beqzt r29, .Lresume_userspace
619 PTREGS_PTR(r29, PTREGS_OFFSET_PC)
620 }
621
622 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
623 moveli r27, hw2_last(_cpu_idle_nap)
624 {
625 ld r28, r29
626 shl16insli r27, r27, hw1(_cpu_idle_nap)
627 }
628 {
629 shl16insli r27, r27, hw0(_cpu_idle_nap)
630 }
631 {
632 cmpeq r27, r27, r28
633 }
634 {
635 blbc r27, .Lrestore_all
636 addi r28, r28, 8
637 }
638 st r29, r28
639 j .Lrestore_all
640
641.Lresume_userspace:
642 FEEDBACK_REENTER(interrupt_return)
643
644 /*
645 * Disable interrupts so as to make sure we don't
646 * miss an interrupt that sets any of the thread flags (like
647 * need_resched or sigpending) between sampling and the iret.
648 * Routines like schedule() or do_signal() may re-enable
649 * interrupts before returning.
650 */
651 IRQ_DISABLE(r20, r21)
652 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
653
654 /* Get base of stack in r32; note r30/31 are used as arguments here. */
655 GET_THREAD_INFO(r32)
656
657
658 /* Check to see if there is any work to do before returning to user. */
659 {
660 addi r29, r32, THREAD_INFO_FLAGS_OFFSET
661 moveli r1, hw1_last(_TIF_ALLWORK_MASK)
662 }
663 {
664 ld r29, r29
665 shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
666 }
667 and r1, r29, r1
668 beqzt r1, .Lrestore_all
669
670 /*
671 * Make sure we have all the registers saved for signal
672 * handling or single-step. Call out to C code to figure out
673 * exactly what we need to do for each flag bit, then if
674 * necessary, reload the flags and recheck.
675 */
676 push_extra_callee_saves r0
677 {
678 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
679 jal do_work_pending
680 }
681 bnez r0, .Lresume_userspace
682
683 /*
684 * In the NMI case we
685 * omit the call to single_process_check_nohz, which normally checks
686 * to see if we should start or stop the scheduler tick, because
687 * we can't call arbitrary Linux code from an NMI context.
688 * We always call the homecache TLB deferral code to re-trigger
689 * the deferral mechanism.
690 *
691 * The other chunk of responsibility this code has is to reset the
692 * interrupt masks appropriately to reset irqs and NMIs. We have
693 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
694 * lockdep-type stuff, but we can't set ICS until afterwards, since
695 * ICS can only be used in very tight chunks of code to avoid
696 * tripping over various assertions that it is off.
697 */
698.Lrestore_all:
699 PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
700 {
701 ld r0, r0
702 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
703 }
704 {
705 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
706 ld r32, r32
707 }
708 bnez r0, 1f
709 j 2f
710#if PT_FLAGS_DISABLE_IRQ != 1
711# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
712#endif
7131: blbct r32, 2f
714 IRQ_DISABLE(r20,r21)
715 TRACE_IRQS_OFF
716 movei r0, 1
717 mtspr INTERRUPT_CRITICAL_SECTION, r0
718 beqzt r30, .Lrestore_regs
719 j 3f
7202: TRACE_IRQS_ON
721 movei r0, 1
722 mtspr INTERRUPT_CRITICAL_SECTION, r0
723 IRQ_ENABLE(r20, r21)
724 beqzt r30, .Lrestore_regs
7253:
726
727
728 /*
729 * We now commit to returning from this interrupt, since we will be
730 * doing things like setting EX_CONTEXT SPRs and unwinding the stack
731 * frame. No calls should be made to any other code after this point.
732 * This code should only be entered with ICS set.
733 * r32 must still be set to ptregs.flags.
734 * We launch loads to each cache line separately first, so we can
735 * get some parallelism out of the memory subsystem.
736 * We start zeroing caller-saved registers throughout, since
737 * that will save some cycles if this turns out to be a syscall.
738 */
739.Lrestore_regs:
740 FEEDBACK_REENTER(interrupt_return) /* called from elsewhere */
741
742 /*
743 * Rotate so we have one high bit and one low bit to test.
744 * - low bit says whether to restore all the callee-saved registers,
745 * or just r30-r33, and r52 up.
746 * - high bit (i.e. sign bit) says whether to restore all the
747 * caller-saved registers, or just r0.
748 */
749#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
750# error Rotate trick does not work :-)
751#endif
752 {
753 rotli r20, r32, 62
754 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
755 }
756
757 /*
758 * Load cache lines 0, 4, 6 and 7, in that order, then use
759 * the last loaded value, which makes it likely that the other
760 * cache lines have also loaded, at which point we should be
761 * able to safely read all the remaining words on those cache
762 * lines without waiting for the memory subsystem.
763 */
764 pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
765 pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
766 pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
767 pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
768 pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
769 {
770 mtspr CMPEXCH_VALUE, r21
771 move r4, zero
772 }
773 pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
774 {
775 mtspr SPR_EX_CONTEXT_K_1, lr
776 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
777 }
778 {
779 mtspr SPR_EX_CONTEXT_K_0, r21
780 move r5, zero
781 }
782
783 /* Restore callee-saveds that we actually use. */
784 pop_reg_zero r31, r6
785 pop_reg_zero r32, r7
786 pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
787
788 /*
789 * If we modified other callee-saveds, restore them now.
790 * This is rare, but could be via ptrace or signal handler.
791 */
792 {
793 move r9, zero
794 blbs r20, .Lrestore_callees
795 }
796.Lcontinue_restore_regs:
797
798 /* Check if we're returning from a syscall. */
799 {
800 move r10, zero
801 bltzt r20, 1f /* no, so go restore callee-save registers */
802 }
803
804 /*
805 * Check if we're returning to userspace.
806 * Note that if we're not, we don't worry about zeroing everything.
807 */
808 {
809 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
810 bnez lr, .Lkernel_return
811 }
812
813 /*
814 * On return from syscall, we've restored r0 from pt_regs, but we
815 * clear the remainder of the caller-saved registers. We could
816 * restore the syscall arguments, but there's not much point,
817 * and it ensures user programs aren't trying to use the
818 * caller-saves if we clear them, as well as avoiding leaking
819 * kernel pointers into userspace.
820 */
821 pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
822 pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
823 {
824 ld sp, sp
825 move r13, zero
826 move r14, zero
827 }
828 { move r15, zero; move r16, zero }
829 { move r17, zero; move r18, zero }
830 { move r19, zero; move r20, zero }
831 { move r21, zero; move r22, zero }
832 { move r23, zero; move r24, zero }
833 { move r25, zero; move r26, zero }
834
835 /* Set r1 to errno if we are returning an error, otherwise zero. */
836 {
837 moveli r29, 4096
838 sub r1, zero, r0
839 }
840 {
841 move r28, zero
842 cmpltu r29, r1, r29
843 }
844 {
845 mnz r1, r29, r1
846 move r29, zero
847 }
848 iret
849
850 /*
851 * Not a syscall, so restore caller-saved registers.
852 * First kick off loads for cache lines 1-3, which we're touching
853 * for the first time here.
854 */
855 .align 64
8561: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
857 pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
858 pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
859 pop_reg r1
860 pop_reg r2
861 pop_reg r3
862 pop_reg r4
863 pop_reg r5
864 pop_reg r6
865 pop_reg r7
866 pop_reg r8
867 pop_reg r9
868 pop_reg r10
869 pop_reg r11
870 pop_reg r12, sp, 16
871 /* r13 already restored above */
872 pop_reg r14
873 pop_reg r15
874 pop_reg r16
875 pop_reg r17
876 pop_reg r18
877 pop_reg r19
878 pop_reg r20, sp, 16
879 /* r21 already restored above */
880 pop_reg r22
881 pop_reg r23
882 pop_reg r24
883 pop_reg r25
884 pop_reg r26
885 pop_reg r27
886 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
887 /* r29 already restored above */
888 bnez lr, .Lkernel_return
889 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
890 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
891 ld sp, sp
892 iret
893
894 /*
895 * We can't restore tp when in kernel mode, since a thread might
896 * have migrated from another cpu and brought a stale tp value.
897 */
898.Lkernel_return:
899 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
900 ld sp, sp
901 iret
902
903 /* Restore callee-saved registers from r34 to r51. */
904.Lrestore_callees:
905 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
906 pop_reg r34
907 pop_reg r35
908 pop_reg r36
909 pop_reg r37
910 pop_reg r38
911 pop_reg r39
912 pop_reg r40
913 pop_reg r41
914 pop_reg r42
915 pop_reg r43
916 pop_reg r44
917 pop_reg r45
918 pop_reg r46
919 pop_reg r47
920 pop_reg r48
921 pop_reg r49
922 pop_reg r50
923 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
924 j .Lcontinue_restore_regs
925 STD_ENDPROC(interrupt_return)
926
927 /*
928 * "NMI" interrupts mask ALL interrupts before calling the
929 * handler, and don't check thread flags, etc., on the way
930 * back out. In general, the only things we do here for NMIs
931 * are register save/restore and dataplane kernel-TLB management.
932 * We don't (for example) deal with start/stop of the sched tick.
933 */
934 .pushsection .text.handle_nmi,"ax"
935handle_nmi:
936 finish_interrupt_save handle_nmi
937 {
938 jalr r0
939 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
940 }
941 FEEDBACK_REENTER(handle_nmi)
942 {
943 movei r30, 1
944 move r31, r0
945 }
946 j interrupt_return
947 STD_ENDPROC(handle_nmi)
948
949 /*
950 * Parallel code for syscalls to handle_interrupt.
951 */
952 .pushsection .text.handle_syscall,"ax"
953handle_syscall:
954 finish_interrupt_save handle_syscall
955
956 /* Enable irqs. */
957 TRACE_IRQS_ON
958 IRQ_ENABLE(r20, r21)
959
960 /* Bump the counter for syscalls made on this tile. */
961 moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
962 shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
963 shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
964 add r20, r20, tp
965 ld4s r21, r20
966 addi r21, r21, 1
967 st4 r20, r21
968
969 /* Trace syscalls, if requested. */
970 GET_THREAD_INFO(r31)
971 addi r31, r31, THREAD_INFO_FLAGS_OFFSET
972 ld r30, r31
973 andi r30, r30, _TIF_SYSCALL_TRACE
974 {
975 addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
976 beqzt r30, .Lrestore_syscall_regs
977 }
978 jal do_syscall_trace
979 FEEDBACK_REENTER(handle_syscall)
980
981 /*
982 * We always reload our registers from the stack at this
983 * point. They might be valid, if we didn't build with
984 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
985 * doing syscall tracing, but there are enough cases now that it
986 * seems simplest just to do the reload unconditionally.
987 */
988.Lrestore_syscall_regs:
989 {
990 ld r30, r30
991 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
992 }
993 pop_reg r0, r11
994 pop_reg r1, r11
995 pop_reg r2, r11
996 pop_reg r3, r11
997 pop_reg r4, r11
998 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
999 {
1000 ld TREG_SYSCALL_NR_NAME, r11
1001 moveli r21, __NR_syscalls
1002 }
1003
1004 /* Ensure that the syscall number is within the legal range. */
1005 {
1006 moveli r20, hw2(sys_call_table)
1007 blbs r30, .Lcompat_syscall
1008 }
1009 {
1010 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1011 shl16insli r20, r20, hw1(sys_call_table)
1012 }
1013 {
1014 blbc r21, .Linvalid_syscall
1015 shl16insli r20, r20, hw0(sys_call_table)
1016 }
1017.Lload_syscall_pointer:
1018 shl3add r20, TREG_SYSCALL_NR_NAME, r20
1019 ld r20, r20
1020
1021 /* Jump to syscall handler. */
1022 jalr r20
1023.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1024
1025 /*
1026 * Write our r0 onto the stack so it gets restored instead
1027 * of whatever the user had there before.
1028 * In compat mode, sign-extend r0 before storing it.
1029 */
1030 {
1031 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1032 blbct r30, 1f
1033 }
1034 addxi r0, r0, 0
10351: st r29, r0
1036
1037.Lsyscall_sigreturn_skip:
1038 FEEDBACK_REENTER(handle_syscall)
1039
1040 /* Do syscall trace again, if requested. */
1041 ld r30, r31
1042 andi r30, r30, _TIF_SYSCALL_TRACE
1043 beqzt r30, 1f
1044 jal do_syscall_trace
1045 FEEDBACK_REENTER(handle_syscall)
10461: j .Lresume_userspace /* jump into middle of interrupt_return */
1047
1048.Lcompat_syscall:
1049 /*
1050 * Load the base of the compat syscall table in r20, and
1051 * range-check the syscall number (duplicated from 64-bit path).
1052 * Sign-extend all the user's passed arguments to make them consistent.
1053 * Also save the original "r(n)" values away in "r(11+n)" in
1054 * case the syscall table entry wants to validate them.
1055 */
1056 moveli r20, hw2(compat_sys_call_table)
1057 {
1058 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1059 shl16insli r20, r20, hw1(compat_sys_call_table)
1060 }
1061 {
1062 blbc r21, .Linvalid_syscall
1063 shl16insli r20, r20, hw0(compat_sys_call_table)
1064 }
1065 { move r11, r0; addxi r0, r0, 0 }
1066 { move r12, r1; addxi r1, r1, 0 }
1067 { move r13, r2; addxi r2, r2, 0 }
1068 { move r14, r3; addxi r3, r3, 0 }
1069 { move r15, r4; addxi r4, r4, 0 }
1070 { move r16, r5; addxi r5, r5, 0 }
1071 j .Lload_syscall_pointer
1072
1073.Linvalid_syscall:
1074 /* Report an invalid syscall back to the user program */
1075 {
1076 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1077 movei r28, -ENOSYS
1078 }
1079 st r29, r28
1080 j .Lresume_userspace /* jump into middle of interrupt_return */
1081 STD_ENDPROC(handle_syscall)
1082
1083 /* Return the address for oprofile to suppress in backtraces. */
1084STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
1085 lnk r0
1086 {
1087 addli r0, r0, .Lhandle_syscall_link - .
1088 jrp lr
1089 }
1090 STD_ENDPROC(handle_syscall_link_address)
1091
1092STD_ENTRY(ret_from_fork)
1093 jal sim_notify_fork
1094 jal schedule_tail
1095 FEEDBACK_REENTER(ret_from_fork)
1096 j .Lresume_userspace
1097 STD_ENDPROC(ret_from_fork)
1098
1099/* Various stub interrupt handlers and syscall handlers */
1100
1101STD_ENTRY_LOCAL(_kernel_double_fault)
1102 mfspr r1, SPR_EX_CONTEXT_K_0
1103 move r2, lr
1104 move r3, sp
1105 move r4, r52
1106 addi sp, sp, -C_ABI_SAVE_AREA_SIZE
1107 j kernel_double_fault
1108 STD_ENDPROC(_kernel_double_fault)
1109
1110STD_ENTRY_LOCAL(bad_intr)
1111 mfspr r2, SPR_EX_CONTEXT_K_0
1112 panic "Unhandled interrupt %#x: PC %#lx"
1113 STD_ENDPROC(bad_intr)
1114
1115/* Put address of pt_regs in reg and jump. */
1116#define PTREGS_SYSCALL(x, reg) \
1117 STD_ENTRY(_##x); \
1118 { \
1119 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1120 j x \
1121 }; \
1122 STD_ENDPROC(_##x)
1123
1124/*
1125 * Special-case sigreturn to not write r0 to the stack on return.
1126 * This is technically more efficient, but it also avoids difficulties
1127 * in the 64-bit OS when handling 32-bit compat code, since we must not
1128 * sign-extend r0 for the sigreturn return-value case.
1129 */
1130#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1131 STD_ENTRY(_##x); \
1132 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1133 { \
1134 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1135 j x \
1136 }; \
1137 STD_ENDPROC(_##x)
1138
1139PTREGS_SYSCALL(sys_execve, r3)
1140PTREGS_SYSCALL(sys_sigaltstack, r2)
1141PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1142#ifdef CONFIG_COMPAT
1143PTREGS_SYSCALL(compat_sys_execve, r3)
1144PTREGS_SYSCALL(compat_sys_sigaltstack, r2)
1145PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
1146#endif
1147
1148/* Save additional callee-saves to pt_regs, put address in r4 and jump. */
1149STD_ENTRY(_sys_clone)
1150 push_extra_callee_saves r4
1151 j sys_clone
1152 STD_ENDPROC(_sys_clone)
1153
1154/* The single-step support may need to read all the registers. */
1155int_unalign:
1156 push_extra_callee_saves r0
1157 j do_trap
1158
1159/* Include .intrpt1 array of interrupt vectors */
1160 .section ".intrpt1", "ax"
1161
1162#define op_handle_perf_interrupt bad_intr
1163#define op_handle_aux_perf_interrupt bad_intr
1164
1165#ifndef CONFIG_HARDWALL
1166#define do_hardwall_trap bad_intr
1167#endif
1168
1169 int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr
1170 int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
1171#if CONFIG_KERNEL_PL == 2
1172 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
1173 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
1174#else
1175 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
1176 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
1177#endif
1178 int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
1179 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
1180 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
1181 int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
1182 int_hand INT_ILL, ILL, do_trap
1183 int_hand INT_GPV, GPV, do_trap
1184 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
1185 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
1186 int_hand INT_SWINT_3, SWINT_3, do_trap
1187 int_hand INT_SWINT_2, SWINT_2, do_trap
1188 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
1189 int_hand INT_SWINT_0, SWINT_0, do_trap
1190 int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
1191 int_hand INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign
1192 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
1193 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
1194 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr
1195 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
1196 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
1197 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
1198 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
1199 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
1200 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
1201 int_hand INT_IPI_3, IPI_3, bad_intr
1202#if CONFIG_KERNEL_PL == 2
1203 int_hand INT_IPI_2, IPI_2, tile_dev_intr
1204 int_hand INT_IPI_1, IPI_1, bad_intr
1205#else
1206 int_hand INT_IPI_2, IPI_2, bad_intr
1207 int_hand INT_IPI_1, IPI_1, tile_dev_intr
1208#endif
1209 int_hand INT_IPI_0, IPI_0, bad_intr
1210 int_hand INT_PERF_COUNT, PERF_COUNT, \
1211 op_handle_perf_interrupt, handle_nmi
1212 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
1213 op_handle_perf_interrupt, handle_nmi
1214 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
1215#if CONFIG_KERNEL_PL == 2
1216 dc_dispatch INT_INTCTRL_2, INTCTRL_2
1217 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
1218#else
1219 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
1220 dc_dispatch INT_INTCTRL_1, INTCTRL_1
1221#endif
1222 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
1223 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
1224 hv_message_intr
1225 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
1226 int_hand INT_I_ASID, I_ASID, bad_intr
1227 int_hand INT_D_ASID, D_ASID, bad_intr
1228 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
1229
1230 /* Synthetic interrupt delivered only by the simulator */
1231 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 8e8633490f8b..9c45d8bbdf57 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -630,8 +630,8 @@ out:
630 630
631#ifdef CONFIG_COMPAT 631#ifdef CONFIG_COMPAT
632long compat_sys_execve(const char __user *path, 632long compat_sys_execve(const char __user *path,
633 const compat_uptr_t __user *argv, 633 compat_uptr_t __user *argv,
634 const compat_uptr_t __user *envp, 634 compat_uptr_t __user *envp,
635 struct pt_regs *regs) 635 struct pt_regs *regs)
636{ 636{
637 long error; 637 long error;
diff --git a/arch/tile/kernel/regs_64.S b/arch/tile/kernel/regs_64.S
new file mode 100644
index 000000000000..f748c1e85285
--- /dev/null
+++ b/arch/tile/kernel/regs_64.S
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/linkage.h>
16#include <asm/system.h>
17#include <asm/ptrace.h>
18#include <asm/asm-offsets.h>
19#include <arch/spr_def.h>
20#include <asm/processor.h>
21
22/*
23 * See <asm/system.h>; called with prev and next task_struct pointers.
24 * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
25 *
26 * We want to save pc/sp in "prev", and get the new pc/sp from "next".
27 * We also need to save all the callee-saved registers on the stack.
28 *
29 * Intel enables/disables access to the hardware cycle counter in
30 * seccomp (secure computing) environments if necessary, based on
31 * has_secure_computing(). We might want to do this at some point,
32 * though it would require virtualizing the other SPRs under WORLD_ACCESS.
33 *
34 * Since we're saving to the stack, we omit sp from this list.
35 * And for parallels with other architectures, we save lr separately,
36 * in the thread_struct itself (as the "pc" field).
37 *
38 * This code also needs to be aligned with process.c copy_thread()
39 */
40
41#if CALLEE_SAVED_REGS_COUNT != 24
42# error Mismatch between <asm/system.h> and kernel/entry.S
43#endif
44#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
45
46#define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
47#define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
48#define FOR_EACH_CALLEE_SAVED_REG(f) \
49 f(r30); f(r31); \
50 f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
51 f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
52 f(r48); f(r49); f(r50); f(r51); f(r52);
53
54STD_ENTRY_SECTION(__switch_to, .sched.text)
55 {
56 move r10, sp
57 st sp, lr
58 }
59 {
60 addli r11, sp, -FRAME_SIZE + 8
61 addli sp, sp, -FRAME_SIZE
62 }
63 {
64 st r11, r10
65 addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
66 }
67 {
68 ld r13, r4 /* Load new sp to a temp register early. */
69 addi r12, sp, 16
70 }
71 FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
72 addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
73 {
74 st r3, sp
75 addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
76 }
77 {
78 st r3, lr
79 addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
80 }
81 {
82 ld lr, r4
83 addi r12, r13, 16
84 }
85 {
86 /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
87 move sp, r13
88 mtspr SPR_SYSTEM_SAVE_K_0, r2
89 }
90 FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
91.L__switch_to_pc:
92 {
93 addli sp, sp, FRAME_SIZE
94 jrp lr /* r0 is still valid here, so return it */
95 }
96 STD_ENDPROC(__switch_to)
97
98/* Return a suitable address for the backtracer for suspended threads */
99STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
100 lnk r0
101 {
102 addli r0, r0, .L__switch_to_pc - .
103 jrp lr
104 }
105 STD_ENDPROC(get_switch_to_pc)
106
107STD_ENTRY(get_pt_regs)
108 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
109 r8, r9, r10, r11, r12, r13, r14, r15, \
110 r16, r17, r18, r19, r20, r21, r22, r23, \
111 r24, r25, r26, r27, r28, r29, r30, r31, \
112 r32, r33, r34, r35, r36, r37, r38, r39, \
113 r40, r41, r42, r43, r44, r45, r46, r47, \
114 r48, r49, r50, r51, r52, tp, sp
115 {
116 st r0, \reg
117 addi r0, r0, 8
118 }
119 .endr
120 {
121 st r0, lr
122 addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
123 }
124 lnk r1
125 {
126 st r0, r1
127 addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
128 }
129 mfspr r1, INTERRUPT_CRITICAL_SECTION
130 shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
131 ori r1, r1, KERNEL_PL
132 {
133 st r0, r1
134 addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
135 }
136 {
137 st r0, zero /* clear faultnum */
138 addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
139 }
140 {
141 st r0, zero /* clear orig_r0 */
142 addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
143 }
144 jrp lr
145 STD_ENDPROC(get_pt_regs)
diff --git a/arch/tile/kernel/tile-desc_64.c b/arch/tile/kernel/tile-desc_64.c
new file mode 100644
index 000000000000..d57007bed77f
--- /dev/null
+++ b/arch/tile/kernel/tile-desc_64.c
@@ -0,0 +1,2200 @@
1/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
2#define BFD_RELOC(x) -1
3
4/* Special registers. */
5#define TREG_LR 55
6#define TREG_SN 56
7#define TREG_ZERO 63
8
9/* FIXME: Rename this. */
10#include <asm/opcode-tile_64.h>
11
12#include <linux/stddef.h>
13
14const struct tilegx_opcode tilegx_opcodes[334] =
15{
16 { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
17 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
18 },
19 { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
20 { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
21 },
22 { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
23 { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
24 },
25 { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
26 { { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } },
27 },
28 { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
29 { { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
30 },
31 { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
32 { { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } },
33 },
34 { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
35 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
36 },
37 { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
38 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
39 },
40 { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
41 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
42 },
43 { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
44 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
45 },
46 { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
47 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
48 },
49 { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
50 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
51 },
52 { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
53 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
54 },
55 { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
56 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
57 },
58 { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
59 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
60 },
61 { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
62 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
63 },
64 { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
65 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
66 },
67 { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
68 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
69 },
70 { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
71 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
72 },
73 { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
74 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
75 },
76 { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
77 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
78 },
79 { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
80 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
81 },
82 { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
83 { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
84 },
85 { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
86 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
87 },
88 { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
89 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
90 },
91 { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
92 { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
93 },
94 { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
95 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
96 },
97 { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
98 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
99 },
100 { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
101 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
102 },
103 { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
104 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
105 },
106 { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
107 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
108 },
109 { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
110 { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
111 },
112 { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
113 { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
114 },
115 { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
116 { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
117 },
118 { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
119 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
120 },
121 { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
122 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
123 },
124 { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
125 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
126 },
127 { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
128 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
129 },
130 { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
131 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
132 },
133 { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
134 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
135 },
136 { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
137 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
138 },
139 { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
140 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
141 },
142 { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
143 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
144 },
145 { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
146 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
147 },
148 { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
149 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
150 },
151 { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
152 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
153 },
154 { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
155 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
156 },
157 { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
158 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
159 },
160 { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
161 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
162 },
163 { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
164 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
165 },
166 { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
167 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
168 },
169 { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
170 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
171 },
172 { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
173 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
174 },
175 { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
176 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
177 },
178 { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
179 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
180 },
181 { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
182 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
183 },
184 { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
185 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
186 },
187 { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
188 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
189 },
190 { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
191 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
192 },
193 { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
194 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
195 },
196 { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
197 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
198 },
199 { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
200 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
201 },
202 { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
203 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
204 },
205 { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
206 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
207 },
208 { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
209 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
210 },
211 { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
212 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
213 },
214 { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
215 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
216 },
217 { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
218 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
219 },
220 { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
221 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
222 },
223 { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
224 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
225 },
226 { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
227 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
228 },
229 { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
230 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
231 },
232 { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
233 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
234 },
235 { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
236 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
237 },
238 { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
239 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
240 },
241 { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
242 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
243 },
244 { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
245 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
246 },
247 { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
248 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
249 },
250 { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
251 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
252 },
253 { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
254 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
255 },
256 { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
257 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
258 },
259 { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
260 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
261 },
262 { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
263 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
264 },
265 { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
266 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
267 },
268 { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
269 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
270 },
271 { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
272 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
273 },
274 { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
275 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
276 },
277 { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
278 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
279 },
280 { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
281 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
282 },
283 { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
284 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
285 },
286 { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
287 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
288 },
289 { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
290 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
291 },
292 { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
293 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
294 },
295 { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
296 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
297 },
298 { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
299 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
300 },
301 { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
302 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
303 },
304 { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
305 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
306 },
307 { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
308 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
309 },
310 { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
311 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
312 },
313 { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
314 { { }, { }, { }, { }, { 0, } },
315 },
316 { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
317 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
318 },
319 { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
320 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
321 },
322 { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
323 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
324 },
325 { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
326 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
327 },
328 { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
329 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
330 },
331 { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
332 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
333 },
334 { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
335 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
336 },
337 { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
338 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
339 },
340 { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
341 { { 0, }, { }, { 0, }, { }, { 0, } },
342 },
343 { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
344 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
345 },
346 { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
347 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
348 },
349 { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
350 { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
351 },
352 { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
353 { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
354 },
355 { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
356 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
357 },
358 { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
359 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
360 },
361 { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
362 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
363 },
364 { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
365 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
366 },
367 { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
368 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
369 },
370 { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
371 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
372 },
373 { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
374 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
375 },
376 { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
377 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
378 },
379 { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
380 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
381 },
382 { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
383 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
384 },
385 { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
386 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
387 },
388 { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
389 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
390 },
391 { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
392 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
393 },
394 { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
395 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
396 },
397 { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
398 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
399 },
400 { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
401 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
402 },
403 { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
404 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
405 },
406 { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
407 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
408 },
409 { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
410 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
411 },
412 { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
413 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
414 },
415 { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
416 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
417 },
418 { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
419 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
420 },
421 { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
422 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
423 },
424 { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
425 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
426 },
427 { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
428 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
429 },
430 { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
431 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
432 },
433 { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
434 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
435 },
436 { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
437 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
438 },
439 { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
440 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
441 },
442 { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
443 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
444 },
445 { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
446 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
447 },
448 { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
449 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
450 },
451 { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
452 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
453 },
454 { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
455 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
456 },
457 { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
458 { { 0, }, { 8 }, { 0, }, { 12 }, { 0, } },
459 },
460 { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
461 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
462 },
463 { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
464 { { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } },
465 },
466 { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
467 { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
468 },
469 { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
470 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
471 },
472 { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
473 { { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } },
474 },
475 { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
476 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
477 },
478 { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
479 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
480 },
481 { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
482 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
483 },
484 { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
485 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
486 },
487 { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
488 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
489 },
490 { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
491 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
492 },
493 { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
494 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
495 },
496 { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
497 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
498 },
499 { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
500 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
501 },
502 { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
503 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
504 },
505 { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
506 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
507 },
508 { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
509 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
510 },
511 { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
512 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
513 },
514 { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
515 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
516 },
517 { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
518 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
519 },
520 { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
521 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
522 },
523 { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
524 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
525 },
526 { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
527 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
528 },
529 { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
530 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
531 },
532 { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
533 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
534 },
535 { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
536 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
537 },
538 { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
539 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
540 },
541 { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
542 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
543 },
544 { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
545 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
546 },
547 { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
548 { { }, { }, { }, { }, { 0, } },
549 },
550 { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
551 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
552 },
553 { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
554 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
555 },
556 { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
557 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
558 },
559 { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
560 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
561 },
562 { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
563 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
564 },
565 { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
566 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
567 },
568 { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
569 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
570 },
571 { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
572 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
573 },
574 { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
575 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
576 },
577 { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
578 { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
579 },
580 { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
581 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
582 },
583 { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
584 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
585 },
586 { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
587 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
588 },
589 { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
590 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
591 },
592 { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
593 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
594 },
595 { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
596 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
597 },
598 { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
599 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
600 },
601 { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
602 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
603 },
604 { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
605 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
606 },
607 { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
608 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
609 },
610 { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
611 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
612 },
613 { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
614 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
615 },
616 { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
617 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
618 },
619 { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
620 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
621 },
622 { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
623 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
624 },
625 { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
626 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
627 },
628 { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
629 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
630 },
631 { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
632 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
633 },
634 { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
635 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
636 },
637 { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
638 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
639 },
640 { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
641 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
642 },
643 { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
644 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
645 },
646 { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
647 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
648 },
649 { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
650 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
651 },
652 { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
653 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
654 },
655 { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
656 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
657 },
658 { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
659 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
660 },
661 { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
662 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
663 },
664 { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
665 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
666 },
667 { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
668 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
669 },
670 { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
671 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
672 },
673 { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
674 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
675 },
676 { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
677 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
678 },
679 { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
680 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
681 },
682 { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
683 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
684 },
685 { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
686 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
687 },
688 { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
689 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
690 },
691 { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
692 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
693 },
694 { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
695 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
696 },
697 { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
698 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
699 },
700 { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
701 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
702 },
703 { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
704 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
705 },
706 { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
707 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
708 },
709 { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
710 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
711 },
712 { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
713 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
714 },
715 { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
716 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
717 },
718 { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
719 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
720 },
721 { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
722 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
723 },
724 { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
725 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
726 },
727 { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
728 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
729 },
730 { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
731 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
732 },
733 { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
734 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
735 },
736 { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
737 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
738 },
739 { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
740 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
741 },
742 { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
743 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
744 },
745 { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
746 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
747 },
748 { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
749 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
750 },
751 { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
752 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
753 },
754 { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
755 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
756 },
757 { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
758 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
759 },
760 { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
761 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
762 },
763 { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
764 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
765 },
766 { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
767 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
768 },
769 { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
770 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
771 },
772 { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
773 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
774 },
775 { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
776 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
777 },
778 { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
779 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
780 },
781 { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
782 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
783 },
784 { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
785 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
786 },
787 { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
788 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
789 },
790 { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
791 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
792 },
793 { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
794 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
795 },
796 { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
797 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
798 },
799 { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
800 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
801 },
802 { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
803 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
804 },
805 { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
806 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
807 },
808 { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
809 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
810 },
811 { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
812 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
813 },
814 { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
815 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
816 },
817 { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
818 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
819 },
820 { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
821 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
822 },
823 { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
824 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
825 },
826 { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
827 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
828 },
829 { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
830 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
831 },
832 { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
833 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
834 },
835 { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
836 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
837 },
838 { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
839 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
840 },
841 { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
842 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
843 },
844 { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
845 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
846 },
847 { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
848 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
849 },
850 { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
851 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
852 },
853 { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
854 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
855 },
856 { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
857 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
858 },
859 { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
860 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
861 },
862 { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
863 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
864 },
865 { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
866 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
867 },
868 { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
869 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
870 },
871 { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
872 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
873 },
874 { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
875 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
876 },
877 { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
878 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
879 },
880 { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
881 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
882 },
883 { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
884 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
885 },
886 { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
887 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
888 },
889 { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
890 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
891 },
892 { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
893 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
894 },
895 { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
896 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
897 },
898 { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
899 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
900 },
901 { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
902 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
903 },
904 { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
905 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
906 },
907 { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
908 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
909 },
910 { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
911 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
912 },
913 { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
914 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
915 },
916 { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
917 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
918 },
919 { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
920 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
921 },
922 { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
923 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
924 },
925 { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
926 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
927 },
928 { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
929 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
930 },
931 { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
932 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
933 },
934 { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
935 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
936 },
937 { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
938 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
939 },
940 { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
941 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
942 },
943 { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
944 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
945 },
946 { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
947 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
948 },
949 { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
950 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
951 },
952 { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
953 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
954 },
955 { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
956 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
957 },
958 { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
959 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
960 },
961 { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
962 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
963 },
964 { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
965 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
966 },
967 { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
968 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
969 },
970 { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
971 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
972 },
973 { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
974 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
975 },
976 { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
977 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
978 },
979 { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
980 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
981 },
982 { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
983 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
984 },
985 { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
986 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
987 },
988 { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
989 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
990 },
991 { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
992 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
993 },
994 { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
995 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
996 },
997 { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
998 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
999 },
1000 { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
1001 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
1002 },
1003 { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
1004 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
1005 },
1006 { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
1007 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
1008 },
1009 { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
1010 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
1011 },
1012 { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
1013 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
1014 },
1015 { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
1016 }
1017};
1018#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
1019#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
1020
1021static const unsigned short decode_X0_fsm[936] =
1022{
1023 BITFIELD(22, 9) /* index 0 */,
1024 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1025 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1026 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1027 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1028 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1029 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1030 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1031 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1032 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1033 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1034 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1035 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1036 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1037 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1038 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1039 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1040 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1041 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1042 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1043 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1044 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1045 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1046 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1047 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1048 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1049 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1050 CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
1051 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1052 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1053 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1054 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1055 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1056 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1057 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1058 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1059 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1060 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1061 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1062 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1063 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1064 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1065 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1066 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
1067 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1068 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1069 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1070 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
1071 TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
1072 TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
1073 TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
1074 TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
1075 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1076 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1077 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1078 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1079 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1080 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1081 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1082 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
1083 CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
1084 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1085 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1086 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1087 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1088 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1089 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1090 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1091 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1092 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1093 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1094 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1095 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1096 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1097 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1098 TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
1099 CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
1100 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1101 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1102 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1103 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1104 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1105 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1106 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1107 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1108 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1109 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1110 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1111 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1112 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1113 TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1114 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1115 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1116 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1117 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1118 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1119 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1120 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1121 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1122 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1123 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1124 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1125 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1126 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1127 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1128 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1129 TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1130 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1131 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1132 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1133 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1134 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1135 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1136 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1137 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1138 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1139 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1140 BITFIELD(6, 2) /* index 513 */,
1141 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
1142 BITFIELD(8, 2) /* index 518 */,
1143 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
1144 BITFIELD(10, 2) /* index 523 */,
1145 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
1146 BITFIELD(20, 2) /* index 528 */,
1147 TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
1148 BITFIELD(6, 2) /* index 533 */,
1149 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
1150 BITFIELD(8, 2) /* index 538 */,
1151 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
1152 BITFIELD(10, 2) /* index 543 */,
1153 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1154 BITFIELD(0, 2) /* index 548 */,
1155 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
1156 BITFIELD(2, 2) /* index 553 */,
1157 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
1158 BITFIELD(4, 2) /* index 558 */,
1159 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
1160 BITFIELD(6, 2) /* index 563 */,
1161 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
1162 BITFIELD(8, 2) /* index 568 */,
1163 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
1164 BITFIELD(10, 2) /* index 573 */,
1165 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1166 BITFIELD(20, 2) /* index 578 */,
1167 TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
1168 BITFIELD(20, 2) /* index 583 */,
1169 TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
1170 TILEGX_OPC_V1CMPLTUI,
1171 BITFIELD(20, 2) /* index 588 */,
1172 TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
1173 TILEGX_OPC_V2CMPEQI,
1174 BITFIELD(20, 2) /* index 593 */,
1175 TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
1176 TILEGX_OPC_V2MINSI,
1177 BITFIELD(20, 2) /* index 598 */,
1178 TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1179 BITFIELD(18, 4) /* index 603 */,
1180 TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
1181 TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
1182 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1183 TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
1184 BITFIELD(18, 4) /* index 620 */,
1185 TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
1186 TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
1187 TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
1188 TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
1189 TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
1190 TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
1191 BITFIELD(18, 4) /* index 637 */,
1192 TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
1193 TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
1194 TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
1195 TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
1196 TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
1197 TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
1198 BITFIELD(18, 4) /* index 654 */,
1199 TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
1200 TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
1201 TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
1202 TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
1203 TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
1204 TILEGX_OPC_MZ,
1205 BITFIELD(18, 4) /* index 671 */,
1206 TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
1207 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
1208 TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
1209 TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
1210 TILEGX_OPC_SUBXSC,
1211 BITFIELD(12, 2) /* index 688 */,
1212 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
1213 BITFIELD(14, 2) /* index 693 */,
1214 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
1215 BITFIELD(16, 2) /* index 698 */,
1216 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1217 BITFIELD(18, 4) /* index 703 */,
1218 TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
1219 TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
1220 TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
1221 TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
1222 TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
1223 BITFIELD(12, 4) /* index 720 */,
1224 TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
1225 CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
1226 CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1227 BITFIELD(16, 2) /* index 737 */,
1228 TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1229 BITFIELD(16, 2) /* index 742 */,
1230 TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1231 BITFIELD(16, 2) /* index 747 */,
1232 TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1233 BITFIELD(16, 2) /* index 752 */,
1234 TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1235 BITFIELD(16, 2) /* index 757 */,
1236 TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1237 BITFIELD(16, 2) /* index 762 */,
1238 TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1239 BITFIELD(16, 2) /* index 767 */,
1240 TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1241 BITFIELD(16, 2) /* index 772 */,
1242 TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1243 BITFIELD(16, 2) /* index 777 */,
1244 TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1245 BITFIELD(16, 2) /* index 782 */,
1246 TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1247 BITFIELD(16, 2) /* index 787 */,
1248 TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1249 BITFIELD(16, 2) /* index 792 */,
1250 TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1251 BITFIELD(18, 4) /* index 797 */,
1252 TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
1253 TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
1254 TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
1255 TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
1256 TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
1257 BITFIELD(18, 4) /* index 814 */,
1258 TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
1259 TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
1260 TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
1261 TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
1262 TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
1263 BITFIELD(18, 4) /* index 831 */,
1264 TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
1265 TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
1266 TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
1267 TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
1268 TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
1269 BITFIELD(18, 4) /* index 848 */,
1270 TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
1271 TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
1272 TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
1273 TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
1274 TILEGX_OPC_V4SUB,
1275 BITFIELD(18, 3) /* index 865 */,
1276 CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
1277 TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1278 BITFIELD(21, 1) /* index 874 */,
1279 TILEGX_OPC_XOR, TILEGX_OPC_NONE,
1280 BITFIELD(21, 1) /* index 877 */,
1281 TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
1282 BITFIELD(21, 1) /* index 880 */,
1283 TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
1284 BITFIELD(21, 1) /* index 883 */,
1285 TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
1286 BITFIELD(21, 1) /* index 886 */,
1287 TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
1288 BITFIELD(18, 4) /* index 889 */,
1289 TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
1290 TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
1291 TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
1292 TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1293 TILEGX_OPC_NONE,
1294 BITFIELD(0, 2) /* index 906 */,
1295 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1296 CHILD(911),
1297 BITFIELD(2, 2) /* index 911 */,
1298 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1299 CHILD(916),
1300 BITFIELD(4, 2) /* index 916 */,
1301 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1302 CHILD(921),
1303 BITFIELD(6, 2) /* index 921 */,
1304 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1305 CHILD(926),
1306 BITFIELD(8, 2) /* index 926 */,
1307 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1308 CHILD(931),
1309 BITFIELD(10, 2) /* index 931 */,
1310 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1311 TILEGX_OPC_INFOL,
1312};
1313
1314static const unsigned short decode_X1_fsm[1206] =
1315{
1316 BITFIELD(53, 9) /* index 0 */,
1317 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1318 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1319 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1320 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1321 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1322 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1323 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1324 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1325 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1326 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1327 CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
1328 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1329 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1330 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1331 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1332 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1333 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1334 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1335 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1336 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1337 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1338 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1339 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1340 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1341 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1342 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1343 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
1344 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1345 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1346 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1347 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1348 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1349 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1350 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1351 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
1352 TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
1353 TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
1354 TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
1355 TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
1356 TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
1357 TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
1358 TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
1359 TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
1360 CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698),
1361 CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE,
1362 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1363 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1364 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1365 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1366 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1367 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1368 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1369 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1370 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1371 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1372 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1373 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1374 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
1375 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1376 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1377 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1378 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1379 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1380 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1381 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1382 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
1383 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1384 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1385 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1386 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1387 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1388 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1389 CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125),
1390 CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1391 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1392 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1393 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1394 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1395 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1396 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1397 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1398 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1399 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1400 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1401 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1402 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1403 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1404 TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE,
1405 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1406 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1407 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1408 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1409 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1410 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1411 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1412 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1413 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1414 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1415 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1416 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1417 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1418 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1419 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1420 TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176),
1421 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1422 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1423 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1424 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1425 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1426 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1427 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1428 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1429 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1430 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1431 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1432 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1433 CHILD(1176),
1434 BITFIELD(37, 2) /* index 513 */,
1435 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
1436 BITFIELD(39, 2) /* index 518 */,
1437 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
1438 BITFIELD(41, 2) /* index 523 */,
1439 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
1440 BITFIELD(51, 2) /* index 528 */,
1441 TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
1442 BITFIELD(37, 2) /* index 533 */,
1443 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
1444 BITFIELD(39, 2) /* index 538 */,
1445 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
1446 BITFIELD(41, 2) /* index 543 */,
1447 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1448 BITFIELD(31, 2) /* index 548 */,
1449 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
1450 BITFIELD(33, 2) /* index 553 */,
1451 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
1452 BITFIELD(35, 2) /* index 558 */,
1453 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
1454 BITFIELD(37, 2) /* index 563 */,
1455 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
1456 BITFIELD(39, 2) /* index 568 */,
1457 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
1458 BITFIELD(41, 2) /* index 573 */,
1459 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1460 BITFIELD(51, 2) /* index 578 */,
1461 TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
1462 BITFIELD(31, 2) /* index 583 */,
1463 TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
1464 BITFIELD(33, 2) /* index 588 */,
1465 TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
1466 BITFIELD(35, 2) /* index 593 */,
1467 TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
1468 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
1469 BITFIELD(51, 2) /* index 598 */,
1470 CHILD(603), CHILD(618), CHILD(633), CHILD(648),
1471 BITFIELD(31, 2) /* index 603 */,
1472 TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
1473 BITFIELD(33, 2) /* index 608 */,
1474 TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
1475 BITFIELD(35, 2) /* index 613 */,
1476 TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
1477 TILEGX_OPC_PREFETCH_ADD_L1,
1478 BITFIELD(31, 2) /* index 618 */,
1479 TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
1480 BITFIELD(33, 2) /* index 623 */,
1481 TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
1482 BITFIELD(35, 2) /* index 628 */,
1483 TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
1484 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
1485 BITFIELD(31, 2) /* index 633 */,
1486 TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
1487 BITFIELD(33, 2) /* index 638 */,
1488 TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
1489 BITFIELD(35, 2) /* index 643 */,
1490 TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
1491 TILEGX_OPC_PREFETCH_ADD_L2,
1492 BITFIELD(31, 2) /* index 648 */,
1493 TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653),
1494 BITFIELD(33, 2) /* index 653 */,
1495 TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658),
1496 BITFIELD(35, 2) /* index 658 */,
1497 TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
1498 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
1499 BITFIELD(51, 2) /* index 663 */,
1500 CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
1501 TILEGX_OPC_LDNT2S_ADD,
1502 BITFIELD(31, 2) /* index 668 */,
1503 TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673),
1504 BITFIELD(33, 2) /* index 673 */,
1505 TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678),
1506 BITFIELD(35, 2) /* index 678 */,
1507 TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
1508 TILEGX_OPC_PREFETCH_ADD_L3,
1509 BITFIELD(51, 2) /* index 683 */,
1510 TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
1511 TILEGX_OPC_LDNT_ADD,
1512 BITFIELD(51, 2) /* index 688 */,
1513 TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
1514 BITFIELD(51, 2) /* index 693 */,
1515 TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
1516 BITFIELD(51, 2) /* index 698 */,
1517 TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
1518 TILEGX_OPC_STNT_ADD,
1519 BITFIELD(51, 2) /* index 703 */,
1520 TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
1521 TILEGX_OPC_V1CMPLTSI,
1522 BITFIELD(51, 2) /* index 708 */,
1523 TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
1524 TILEGX_OPC_V2ADDI,
1525 BITFIELD(51, 2) /* index 713 */,
1526 TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
1527 TILEGX_OPC_V2MAXSI,
1528 BITFIELD(51, 2) /* index 718 */,
1529 TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1530 BITFIELD(49, 4) /* index 723 */,
1531 TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
1532 TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
1533 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1534 TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
1535 TILEGX_OPC_DBLALIGN6,
1536 BITFIELD(49, 4) /* index 740 */,
1537 TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
1538 TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
1539 TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
1540 TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
1541 CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
1542 BITFIELD(43, 2) /* index 757 */,
1543 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762),
1544 BITFIELD(45, 2) /* index 762 */,
1545 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767),
1546 BITFIELD(47, 2) /* index 767 */,
1547 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1548 BITFIELD(49, 4) /* index 772 */,
1549 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
1550 TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
1551 TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
1552 TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
1553 TILEGX_OPC_STNT4,
1554 BITFIELD(46, 7) /* index 789 */,
1555 TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
1556 TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
1557 TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
1558 TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
1559 TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
1560 TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
1561 TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
1562 TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
1563 TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
1564 TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927),
1565 CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1566 TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
1567 TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
1568 TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
1569 TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
1570 TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
1571 TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
1572 TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
1573 TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
1574 TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
1575 TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
1576 TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
1577 TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
1578 TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
1579 TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
1580 TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
1581 TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
1582 TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
1583 TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
1584 TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
1585 TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
1586 TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
1587 TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
1588 TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
1589 TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
1590 TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
1591 TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
1592 BITFIELD(43, 3) /* index 918 */,
1593 TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
1594 TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
1595 BITFIELD(43, 3) /* index 927 */,
1596 CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
1597 TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991),
1598 BITFIELD(31, 2) /* index 936 */,
1599 CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1600 BITFIELD(33, 2) /* index 941 */,
1601 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946),
1602 BITFIELD(35, 2) /* index 946 */,
1603 TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1604 BITFIELD(37, 2) /* index 951 */,
1605 TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1606 BITFIELD(39, 2) /* index 956 */,
1607 TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1608 BITFIELD(41, 2) /* index 961 */,
1609 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
1610 BITFIELD(33, 2) /* index 966 */,
1611 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971),
1612 BITFIELD(35, 2) /* index 971 */,
1613 TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1614 BITFIELD(37, 2) /* index 976 */,
1615 TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1616 BITFIELD(39, 2) /* index 981 */,
1617 TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1618 BITFIELD(41, 2) /* index 986 */,
1619 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
1620 BITFIELD(31, 2) /* index 991 */,
1621 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996),
1622 BITFIELD(33, 2) /* index 996 */,
1623 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001),
1624 BITFIELD(35, 2) /* index 1001 */,
1625 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
1626 TILEGX_OPC_PREFETCH_L1_FAULT,
1627 BITFIELD(43, 3) /* index 1006 */,
1628 CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075),
1629 TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
1630 BITFIELD(31, 2) /* index 1015 */,
1631 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020),
1632 BITFIELD(33, 2) /* index 1020 */,
1633 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025),
1634 BITFIELD(35, 2) /* index 1025 */,
1635 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
1636 BITFIELD(31, 2) /* index 1030 */,
1637 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035),
1638 BITFIELD(33, 2) /* index 1035 */,
1639 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040),
1640 BITFIELD(35, 2) /* index 1040 */,
1641 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
1642 TILEGX_OPC_PREFETCH_L2_FAULT,
1643 BITFIELD(31, 2) /* index 1045 */,
1644 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050),
1645 BITFIELD(33, 2) /* index 1050 */,
1646 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055),
1647 BITFIELD(35, 2) /* index 1055 */,
1648 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
1649 BITFIELD(31, 2) /* index 1060 */,
1650 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065),
1651 BITFIELD(33, 2) /* index 1065 */,
1652 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070),
1653 BITFIELD(35, 2) /* index 1070 */,
1654 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
1655 TILEGX_OPC_PREFETCH_L3_FAULT,
1656 BITFIELD(31, 2) /* index 1075 */,
1657 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080),
1658 BITFIELD(33, 2) /* index 1080 */,
1659 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085),
1660 BITFIELD(35, 2) /* index 1085 */,
1661 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
1662 BITFIELD(43, 3) /* index 1090 */,
1663 TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
1664 TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
1665 BITFIELD(43, 3) /* index 1099 */,
1666 TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
1667 TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
1668 BITFIELD(49, 4) /* index 1108 */,
1669 TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
1670 TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
1671 TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
1672 TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
1673 TILEGX_OPC_V2CMPLTU,
1674 BITFIELD(49, 4) /* index 1125 */,
1675 TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
1676 TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
1677 TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
1678 TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
1679 TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
1680 BITFIELD(49, 4) /* index 1142 */,
1681 TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
1682 TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
1683 TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
1684 TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1685 TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1686 BITFIELD(49, 4) /* index 1159 */,
1687 TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
1688 TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
1689 TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
1690 TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1691 TILEGX_OPC_NONE,
1692 BITFIELD(31, 2) /* index 1176 */,
1693 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1694 CHILD(1181),
1695 BITFIELD(33, 2) /* index 1181 */,
1696 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1697 CHILD(1186),
1698 BITFIELD(35, 2) /* index 1186 */,
1699 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1700 CHILD(1191),
1701 BITFIELD(37, 2) /* index 1191 */,
1702 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1703 CHILD(1196),
1704 BITFIELD(39, 2) /* index 1196 */,
1705 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1706 CHILD(1201),
1707 BITFIELD(41, 2) /* index 1201 */,
1708 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1709 TILEGX_OPC_INFOL,
1710};
1711
1712static const unsigned short decode_Y0_fsm[178] =
1713{
1714 BITFIELD(27, 4) /* index 0 */,
1715 CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
1716 TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
1717 CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
1718 CHILD(173),
1719 BITFIELD(6, 2) /* index 17 */,
1720 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
1721 BITFIELD(8, 2) /* index 22 */,
1722 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
1723 BITFIELD(10, 2) /* index 27 */,
1724 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1725 BITFIELD(0, 2) /* index 32 */,
1726 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
1727 BITFIELD(2, 2) /* index 37 */,
1728 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
1729 BITFIELD(4, 2) /* index 42 */,
1730 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
1731 BITFIELD(6, 2) /* index 47 */,
1732 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
1733 BITFIELD(8, 2) /* index 52 */,
1734 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
1735 BITFIELD(10, 2) /* index 57 */,
1736 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1737 BITFIELD(18, 2) /* index 62 */,
1738 TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
1739 BITFIELD(15, 5) /* index 67 */,
1740 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
1741 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
1742 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
1743 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
1744 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
1745 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
1746 TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
1747 TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
1748 CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1749 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1750 BITFIELD(12, 3) /* index 100 */,
1751 TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
1752 TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
1753 TILEGX_OPC_REVBITS,
1754 BITFIELD(12, 3) /* index 109 */,
1755 TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
1756 TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1757 TILEGX_OPC_NONE,
1758 BITFIELD(18, 2) /* index 118 */,
1759 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1760 BITFIELD(18, 2) /* index 123 */,
1761 TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
1762 BITFIELD(18, 2) /* index 128 */,
1763 TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
1764 BITFIELD(18, 2) /* index 133 */,
1765 TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
1766 BITFIELD(12, 2) /* index 138 */,
1767 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
1768 BITFIELD(14, 2) /* index 143 */,
1769 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
1770 BITFIELD(16, 2) /* index 148 */,
1771 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1772 BITFIELD(18, 2) /* index 153 */,
1773 TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
1774 BITFIELD(18, 2) /* index 158 */,
1775 TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
1776 TILEGX_OPC_SHL3ADDX,
1777 BITFIELD(18, 2) /* index 163 */,
1778 TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
1779 TILEGX_OPC_MUL_LU_LU,
1780 BITFIELD(18, 2) /* index 168 */,
1781 TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
1782 TILEGX_OPC_MULA_LU_LU,
1783 BITFIELD(18, 2) /* index 173 */,
1784 TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
1785};
1786
1787static const unsigned short decode_Y1_fsm[167] =
1788{
1789 BITFIELD(58, 4) /* index 0 */,
1790 TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
1791 TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
1792 CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
1793 BITFIELD(37, 2) /* index 17 */,
1794 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
1795 BITFIELD(39, 2) /* index 22 */,
1796 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
1797 BITFIELD(41, 2) /* index 27 */,
1798 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1799 BITFIELD(31, 2) /* index 32 */,
1800 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
1801 BITFIELD(33, 2) /* index 37 */,
1802 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
1803 BITFIELD(35, 2) /* index 42 */,
1804 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
1805 BITFIELD(37, 2) /* index 47 */,
1806 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
1807 BITFIELD(39, 2) /* index 52 */,
1808 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
1809 BITFIELD(41, 2) /* index 57 */,
1810 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1811 BITFIELD(49, 2) /* index 62 */,
1812 TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
1813 BITFIELD(47, 4) /* index 67 */,
1814 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
1815 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
1816 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
1817 TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
1818 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1819 BITFIELD(43, 3) /* index 84 */,
1820 CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
1821 CHILD(111), CHILD(114),
1822 BITFIELD(46, 1) /* index 93 */,
1823 TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
1824 BITFIELD(46, 1) /* index 96 */,
1825 TILEGX_OPC_NONE, TILEGX_OPC_ILL,
1826 BITFIELD(46, 1) /* index 99 */,
1827 TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
1828 BITFIELD(46, 1) /* index 102 */,
1829 TILEGX_OPC_NONE, TILEGX_OPC_JALR,
1830 BITFIELD(46, 1) /* index 105 */,
1831 TILEGX_OPC_NONE, TILEGX_OPC_JRP,
1832 BITFIELD(46, 1) /* index 108 */,
1833 TILEGX_OPC_NONE, TILEGX_OPC_JR,
1834 BITFIELD(46, 1) /* index 111 */,
1835 TILEGX_OPC_NONE, TILEGX_OPC_LNK,
1836 BITFIELD(46, 1) /* index 114 */,
1837 TILEGX_OPC_NONE, TILEGX_OPC_NOP,
1838 BITFIELD(49, 2) /* index 117 */,
1839 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1840 BITFIELD(49, 2) /* index 122 */,
1841 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
1842 BITFIELD(49, 2) /* index 127 */,
1843 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
1844 BITFIELD(49, 2) /* index 132 */,
1845 TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
1846 BITFIELD(43, 2) /* index 137 */,
1847 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
1848 BITFIELD(45, 2) /* index 142 */,
1849 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
1850 BITFIELD(47, 2) /* index 147 */,
1851 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1852 BITFIELD(49, 2) /* index 152 */,
1853 TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
1854 BITFIELD(49, 2) /* index 157 */,
1855 TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
1856 TILEGX_OPC_SHL3ADDX,
1857 BITFIELD(49, 2) /* index 162 */,
1858 TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
1859};
1860
1861static const unsigned short decode_Y2_fsm[118] =
1862{
1863 BITFIELD(62, 2) /* index 0 */,
1864 TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
1865 BITFIELD(55, 3) /* index 5 */,
1866 CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
1867 CHILD(43),
1868 BITFIELD(26, 1) /* index 14 */,
1869 TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
1870 BITFIELD(26, 1) /* index 17 */,
1871 CHILD(20), CHILD(30),
1872 BITFIELD(51, 2) /* index 20 */,
1873 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
1874 BITFIELD(53, 2) /* index 25 */,
1875 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
1876 TILEGX_OPC_PREFETCH_L1_FAULT,
1877 BITFIELD(51, 2) /* index 30 */,
1878 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
1879 BITFIELD(53, 2) /* index 35 */,
1880 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
1881 BITFIELD(26, 1) /* index 40 */,
1882 TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
1883 BITFIELD(26, 1) /* index 43 */,
1884 CHILD(46), CHILD(56),
1885 BITFIELD(51, 2) /* index 46 */,
1886 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
1887 BITFIELD(53, 2) /* index 51 */,
1888 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
1889 TILEGX_OPC_PREFETCH_L2_FAULT,
1890 BITFIELD(51, 2) /* index 56 */,
1891 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
1892 BITFIELD(53, 2) /* index 61 */,
1893 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
1894 BITFIELD(56, 2) /* index 66 */,
1895 CHILD(71), CHILD(74), CHILD(90), CHILD(93),
1896 BITFIELD(26, 1) /* index 71 */,
1897 TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
1898 BITFIELD(26, 1) /* index 74 */,
1899 TILEGX_OPC_NONE, CHILD(77),
1900 BITFIELD(51, 2) /* index 77 */,
1901 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
1902 BITFIELD(53, 2) /* index 82 */,
1903 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
1904 BITFIELD(55, 1) /* index 87 */,
1905 TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
1906 BITFIELD(26, 1) /* index 90 */,
1907 TILEGX_OPC_LD4U, TILEGX_OPC_LD,
1908 BITFIELD(26, 1) /* index 93 */,
1909 CHILD(96), TILEGX_OPC_LD,
1910 BITFIELD(51, 2) /* index 96 */,
1911 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
1912 BITFIELD(53, 2) /* index 101 */,
1913 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
1914 BITFIELD(55, 1) /* index 106 */,
1915 TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
1916 BITFIELD(26, 1) /* index 109 */,
1917 CHILD(112), CHILD(115),
1918 BITFIELD(57, 1) /* index 112 */,
1919 TILEGX_OPC_ST1, TILEGX_OPC_ST4,
1920 BITFIELD(57, 1) /* index 115 */,
1921 TILEGX_OPC_ST2, TILEGX_OPC_ST,
1922};
1923
1924#undef BITFIELD
1925#undef CHILD
1926const unsigned short * const
1927tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
1928{
1929 decode_X0_fsm,
1930 decode_X1_fsm,
1931 decode_Y0_fsm,
1932 decode_Y1_fsm,
1933 decode_Y2_fsm
1934};
1935const struct tilegx_operand tilegx_operands[35] =
1936{
1937 {
1938 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
1939 8, 1, 0, 0, 0, 0,
1940 create_Imm8_X0, get_Imm8_X0
1941 },
1942 {
1943 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
1944 8, 1, 0, 0, 0, 0,
1945 create_Imm8_X1, get_Imm8_X1
1946 },
1947 {
1948 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
1949 8, 1, 0, 0, 0, 0,
1950 create_Imm8_Y0, get_Imm8_Y0
1951 },
1952 {
1953 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
1954 8, 1, 0, 0, 0, 0,
1955 create_Imm8_Y1, get_Imm8_Y1
1956 },
1957 {
1958 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
1959 16, 1, 0, 0, 0, 0,
1960 create_Imm16_X0, get_Imm16_X0
1961 },
1962 {
1963 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
1964 16, 1, 0, 0, 0, 0,
1965 create_Imm16_X1, get_Imm16_X1
1966 },
1967 {
1968 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1969 6, 0, 0, 1, 0, 0,
1970 create_Dest_X0, get_Dest_X0
1971 },
1972 {
1973 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1974 6, 0, 1, 0, 0, 0,
1975 create_SrcA_X0, get_SrcA_X0
1976 },
1977 {
1978 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1979 6, 0, 0, 1, 0, 0,
1980 create_Dest_X1, get_Dest_X1
1981 },
1982 {
1983 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1984 6, 0, 1, 0, 0, 0,
1985 create_SrcA_X1, get_SrcA_X1
1986 },
1987 {
1988 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1989 6, 0, 0, 1, 0, 0,
1990 create_Dest_Y0, get_Dest_Y0
1991 },
1992 {
1993 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1994 6, 0, 1, 0, 0, 0,
1995 create_SrcA_Y0, get_SrcA_Y0
1996 },
1997 {
1998 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1999 6, 0, 0, 1, 0, 0,
2000 create_Dest_Y1, get_Dest_Y1
2001 },
2002 {
2003 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2004 6, 0, 1, 0, 0, 0,
2005 create_SrcA_Y1, get_SrcA_Y1
2006 },
2007 {
2008 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2009 6, 0, 1, 0, 0, 0,
2010 create_SrcA_Y2, get_SrcA_Y2
2011 },
2012 {
2013 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2014 6, 0, 1, 1, 0, 0,
2015 create_SrcA_X1, get_SrcA_X1
2016 },
2017 {
2018 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2019 6, 0, 1, 0, 0, 0,
2020 create_SrcB_X0, get_SrcB_X0
2021 },
2022 {
2023 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2024 6, 0, 1, 0, 0, 0,
2025 create_SrcB_X1, get_SrcB_X1
2026 },
2027 {
2028 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2029 6, 0, 1, 0, 0, 0,
2030 create_SrcB_Y0, get_SrcB_Y0
2031 },
2032 {
2033 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2034 6, 0, 1, 0, 0, 0,
2035 create_SrcB_Y1, get_SrcB_Y1
2036 },
2037 {
2038 TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
2039 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
2040 create_BrOff_X1, get_BrOff_X1
2041 },
2042 {
2043 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
2044 6, 0, 0, 0, 0, 0,
2045 create_BFStart_X0, get_BFStart_X0
2046 },
2047 {
2048 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
2049 6, 0, 0, 0, 0, 0,
2050 create_BFEnd_X0, get_BFEnd_X0
2051 },
2052 {
2053 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2054 6, 0, 1, 1, 0, 0,
2055 create_Dest_X0, get_Dest_X0
2056 },
2057 {
2058 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2059 6, 0, 1, 1, 0, 0,
2060 create_Dest_Y0, get_Dest_Y0
2061 },
2062 {
2063 TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
2064 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
2065 create_JumpOff_X1, get_JumpOff_X1
2066 },
2067 {
2068 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2069 6, 0, 0, 1, 0, 0,
2070 create_SrcBDest_Y2, get_SrcBDest_Y2
2071 },
2072 {
2073 TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
2074 14, 0, 0, 0, 0, 0,
2075 create_MF_Imm14_X1, get_MF_Imm14_X1
2076 },
2077 {
2078 TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
2079 14, 0, 0, 0, 0, 0,
2080 create_MT_Imm14_X1, get_MT_Imm14_X1
2081 },
2082 {
2083 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
2084 6, 0, 0, 0, 0, 0,
2085 create_ShAmt_X0, get_ShAmt_X0
2086 },
2087 {
2088 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
2089 6, 0, 0, 0, 0, 0,
2090 create_ShAmt_X1, get_ShAmt_X1
2091 },
2092 {
2093 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
2094 6, 0, 0, 0, 0, 0,
2095 create_ShAmt_Y0, get_ShAmt_Y0
2096 },
2097 {
2098 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
2099 6, 0, 0, 0, 0, 0,
2100 create_ShAmt_Y1, get_ShAmt_Y1
2101 },
2102 {
2103 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2104 6, 0, 1, 0, 0, 0,
2105 create_SrcBDest_Y2, get_SrcBDest_Y2
2106 },
2107 {
2108 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
2109 8, 1, 0, 0, 0, 0,
2110 create_Dest_Imm8_X1, get_Dest_Imm8_X1
2111 }
2112};
2113
2114
2115
2116
2117/* Given a set of bundle bits and the lookup FSM for a specific pipe,
2118 * returns which instruction the bundle contains in that pipe.
2119 */
2120static const struct tilegx_opcode *
2121find_opcode(tilegx_bundle_bits bits, const unsigned short *table)
2122{
2123 int index = 0;
2124
2125 while (1)
2126 {
2127 unsigned short bitspec = table[index];
2128 unsigned int bitfield =
2129 ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
2130
2131 unsigned short next = table[index + 1 + bitfield];
2132 if (next <= TILEGX_OPC_NONE)
2133 return &tilegx_opcodes[next];
2134
2135 index = next - TILEGX_OPC_NONE;
2136 }
2137}
2138
2139
2140int
2141parse_insn_tilegx(tilegx_bundle_bits bits,
2142 unsigned long long pc,
2143 struct tilegx_decoded_instruction
2144 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])
2145{
2146 int num_instructions = 0;
2147 int pipe;
2148
2149 int min_pipe, max_pipe;
2150 if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
2151 {
2152 min_pipe = TILEGX_PIPELINE_X0;
2153 max_pipe = TILEGX_PIPELINE_X1;
2154 }
2155 else
2156 {
2157 min_pipe = TILEGX_PIPELINE_Y0;
2158 max_pipe = TILEGX_PIPELINE_Y2;
2159 }
2160
2161 /* For each pipe, find an instruction that fits. */
2162 for (pipe = min_pipe; pipe <= max_pipe; pipe++)
2163 {
2164 const struct tilegx_opcode *opc;
2165 struct tilegx_decoded_instruction *d;
2166 int i;
2167
2168 d = &decoded[num_instructions++];
2169 opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]);
2170 d->opcode = opc;
2171
2172 /* Decode each operand, sign extending, etc. as appropriate. */
2173 for (i = 0; i < opc->num_operands; i++)
2174 {
2175 const struct tilegx_operand *op =
2176 &tilegx_operands[opc->operands[pipe][i]];
2177 int raw_opval = op->extract (bits);
2178 long long opval;
2179
2180 if (op->is_signed)
2181 {
2182 /* Sign-extend the operand. */
2183 int shift = (int)((sizeof(int) * 8) - op->num_bits);
2184 raw_opval = (raw_opval << shift) >> shift;
2185 }
2186
2187 /* Adjust PC-relative scaled branch offsets. */
2188 if (op->type == TILEGX_OP_TYPE_ADDRESS)
2189 opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
2190 else
2191 opval = raw_opval;
2192
2193 /* Record the final value. */
2194 d->operands[i] = op;
2195 d->operand_values[i] = opval;
2196 }
2197 }
2198
2199 return num_instructions;
2200}
diff --git a/arch/tile/lib/memchr_64.c b/arch/tile/lib/memchr_64.c
new file mode 100644
index 000000000000..84fdc8d8e735
--- /dev/null
+++ b/arch/tile/lib/memchr_64.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18
19void *memchr(const void *s, int c, size_t n)
20{
21 const uint64_t *last_word_ptr;
22 const uint64_t *p;
23 const char *last_byte_ptr;
24 uintptr_t s_int;
25 uint64_t goal, before_mask, v, bits;
26 char *ret;
27
28 if (__builtin_expect(n == 0, 0)) {
29 /* Don't dereference any memory if the array is empty. */
30 return NULL;
31 }
32
33 /* Get an aligned pointer. */
34 s_int = (uintptr_t) s;
35 p = (const uint64_t *)(s_int & -8);
36
37 /* Create eight copies of the byte for which we are looking. */
38 goal = 0x0101010101010101ULL * (uint8_t) c;
39
40 /* Read the first word, but munge it so that bytes before the array
41 * will not match goal.
42 *
43 * Note that this shift count expression works because we know
44 * shift counts are taken mod 64.
45 */
46 before_mask = (1ULL << (s_int << 3)) - 1;
47 v = (*p | before_mask) ^ (goal & before_mask);
48
49 /* Compute the address of the last byte. */
50 last_byte_ptr = (const char *)s + n - 1;
51
52 /* Compute the address of the word containing the last byte. */
53 last_word_ptr = (const uint64_t *)((uintptr_t) last_byte_ptr & -8);
54
55 while ((bits = __insn_v1cmpeq(v, goal)) == 0) {
56 if (__builtin_expect(p == last_word_ptr, 0)) {
57 /* We already read the last word in the array,
58 * so give up.
59 */
60 return NULL;
61 }
62 v = *++p;
63 }
64
65 /* We found a match, but it might be in a byte past the end
66 * of the array.
67 */
68 ret = ((char *)p) + (__insn_ctz(bits) >> 3);
69 return (ret <= last_byte_ptr) ? ret : NULL;
70}
71EXPORT_SYMBOL(memchr);
diff --git a/arch/tile/lib/memcpy_64.c b/arch/tile/lib/memcpy_64.c
new file mode 100644
index 000000000000..3fab9a6a2bbe
--- /dev/null
+++ b/arch/tile/lib/memcpy_64.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18#define __memcpy memcpy
19/* EXPORT_SYMBOL() is in arch/tile/lib/exports.c since this should be asm. */
20
21/* Must be 8 bytes in size. */
22#define word_t uint64_t
23
24#if CHIP_L2_LINE_SIZE() != 64 && CHIP_L2_LINE_SIZE() != 128
25#error "Assumes 64 or 128 byte line size"
26#endif
27
28/* How many cache lines ahead should we prefetch? */
29#define PREFETCH_LINES_AHEAD 3
30
31/*
32 * Provide "base versions" of load and store for the normal code path.
33 * The kernel provides other versions for userspace copies.
34 */
35#define ST(p, v) (*(p) = (v))
36#define LD(p) (*(p))
37
38#ifndef USERCOPY_FUNC
39#define ST1 ST
40#define ST2 ST
41#define ST4 ST
42#define ST8 ST
43#define LD1 LD
44#define LD2 LD
45#define LD4 LD
46#define LD8 LD
47#define RETVAL dstv
48void *memcpy(void *__restrict dstv, const void *__restrict srcv, size_t n)
49#else
50/*
51 * Special kernel version will provide implementation of the LDn/STn
52 * macros to return a count of uncopied bytes due to mm fault.
53 */
54#define RETVAL 0
55int USERCOPY_FUNC(void *__restrict dstv, const void *__restrict srcv, size_t n)
56#endif
57{
58 char *__restrict dst1 = (char *)dstv;
59 const char *__restrict src1 = (const char *)srcv;
60 const char *__restrict src1_end;
61 const char *__restrict prefetch;
62 word_t *__restrict dst8; /* 8-byte pointer to destination memory. */
63 word_t final; /* Final bytes to write to trailing word, if any */
64 long i;
65
66 if (n < 16) {
67 for (; n; n--)
68 ST1(dst1++, LD1(src1++));
69 return RETVAL;
70 }
71
72 /*
73 * Locate the end of source memory we will copy. Don't
74 * prefetch past this.
75 */
76 src1_end = src1 + n - 1;
77
78 /* Prefetch ahead a few cache lines, but not past the end. */
79 prefetch = src1;
80 for (i = 0; i < PREFETCH_LINES_AHEAD; i++) {
81 __insn_prefetch(prefetch);
82 prefetch += CHIP_L2_LINE_SIZE();
83 prefetch = (prefetch > src1_end) ? prefetch : src1;
84 }
85
86 /* Copy bytes until dst is word-aligned. */
87 for (; (uintptr_t)dst1 & (sizeof(word_t) - 1); n--)
88 ST1(dst1++, LD1(src1++));
89
90 /* 8-byte pointer to destination memory. */
91 dst8 = (word_t *)dst1;
92
93 if (__builtin_expect((uintptr_t)src1 & (sizeof(word_t) - 1), 0)) {
94 /*
95 * Misaligned copy. Copy 8 bytes at a time, but don't
96 * bother with other fanciness.
97 *
98 * TODO: Consider prefetching and using wh64 as well.
99 */
100
101 /* Create an aligned src8. */
102 const word_t *__restrict src8 =
103 (const word_t *)((uintptr_t)src1 & -sizeof(word_t));
104 word_t b;
105
106 word_t a = LD8(src8++);
107 for (; n >= sizeof(word_t); n -= sizeof(word_t)) {
108 b = LD8(src8++);
109 a = __insn_dblalign(a, b, src1);
110 ST8(dst8++, a);
111 a = b;
112 }
113
114 if (n == 0)
115 return RETVAL;
116
117 b = ((const char *)src8 <= src1_end) ? *src8 : 0;
118
119 /*
120 * Final source bytes to write to trailing partial
121 * word, if any.
122 */
123 final = __insn_dblalign(a, b, src1);
124 } else {
125 /* Aligned copy. */
126
127 const word_t* __restrict src8 = (const word_t *)src1;
128
129 /* src8 and dst8 are both word-aligned. */
130 if (n >= CHIP_L2_LINE_SIZE()) {
131 /* Copy until 'dst' is cache-line-aligned. */
132 for (; (uintptr_t)dst8 & (CHIP_L2_LINE_SIZE() - 1);
133 n -= sizeof(word_t))
134 ST8(dst8++, LD8(src8++));
135
136 for (; n >= CHIP_L2_LINE_SIZE(); ) {
137 __insn_wh64(dst8);
138
139 /*
140 * Prefetch and advance to next line
141 * to prefetch, but don't go past the end
142 */
143 __insn_prefetch(prefetch);
144 prefetch += CHIP_L2_LINE_SIZE();
145 prefetch = (prefetch > src1_end) ? prefetch :
146 (const char *)src8;
147
148 /*
149 * Copy an entire cache line. Manually
150 * unrolled to avoid idiosyncracies of
151 * compiler unrolling.
152 */
153#define COPY_WORD(offset) ({ ST8(dst8+offset, LD8(src8+offset)); n -= 8; })
154 COPY_WORD(0);
155 COPY_WORD(1);
156 COPY_WORD(2);
157 COPY_WORD(3);
158 COPY_WORD(4);
159 COPY_WORD(5);
160 COPY_WORD(6);
161 COPY_WORD(7);
162#if CHIP_L2_LINE_SIZE() == 128
163 COPY_WORD(8);
164 COPY_WORD(9);
165 COPY_WORD(10);
166 COPY_WORD(11);
167 COPY_WORD(12);
168 COPY_WORD(13);
169 COPY_WORD(14);
170 COPY_WORD(15);
171#elif CHIP_L2_LINE_SIZE() != 64
172# error Fix code that assumes particular L2 cache line sizes
173#endif
174
175 dst8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
176 src8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
177 }
178 }
179
180 for (; n >= sizeof(word_t); n -= sizeof(word_t))
181 ST8(dst8++, LD8(src8++));
182
183 if (__builtin_expect(n == 0, 1))
184 return RETVAL;
185
186 final = LD8(src8);
187 }
188
189 /* n != 0 if we get here. Write out any trailing bytes. */
190 dst1 = (char *)dst8;
191 if (n & 4) {
192 ST4((uint32_t *)dst1, final);
193 dst1 += 4;
194 final >>= 32;
195 n &= 3;
196 }
197 if (n & 2) {
198 ST2((uint16_t *)dst1, final);
199 dst1 += 2;
200 final >>= 16;
201 n &= 1;
202 }
203 if (n)
204 ST1((uint8_t *)dst1, final);
205
206 return RETVAL;
207}
208
209
210#ifdef USERCOPY_FUNC
211#undef ST1
212#undef ST2
213#undef ST4
214#undef ST8
215#undef LD1
216#undef LD2
217#undef LD4
218#undef LD8
219#undef USERCOPY_FUNC
220#endif
diff --git a/arch/tile/lib/memcpy_user_64.c b/arch/tile/lib/memcpy_user_64.c
new file mode 100644
index 000000000000..4763b3aff1cc
--- /dev/null
+++ b/arch/tile/lib/memcpy_user_64.c
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Do memcpy(), but trap and return "n" when a load or store faults.
15 *
16 * Note: this idiom only works when memcpy() compiles to a leaf function.
17 * If "sp" is updated during memcpy, the "jrp lr" will be incorrect.
18 *
19 * Also note that we are capturing "n" from the containing scope here.
20 */
21
22#define _ST(p, inst, v) \
23 ({ \
24 asm("1: " #inst " %0, %1;" \
25 ".pushsection .coldtext.memcpy,\"ax\";" \
26 "2: { move r0, %2; jrp lr };" \
27 ".section __ex_table,\"a\";" \
28 ".quad 1b, 2b;" \
29 ".popsection" \
30 : "=m" (*(p)) : "r" (v), "r" (n)); \
31 })
32
33#define _LD(p, inst) \
34 ({ \
35 unsigned long __v; \
36 asm("1: " #inst " %0, %1;" \
37 ".pushsection .coldtext.memcpy,\"ax\";" \
38 "2: { move r0, %2; jrp lr };" \
39 ".section __ex_table,\"a\";" \
40 ".quad 1b, 2b;" \
41 ".popsection" \
42 : "=r" (__v) : "m" (*(p)), "r" (n)); \
43 __v; \
44 })
45
46#define USERCOPY_FUNC __copy_to_user_inatomic
47#define ST1(p, v) _ST((p), st1, (v))
48#define ST2(p, v) _ST((p), st2, (v))
49#define ST4(p, v) _ST((p), st4, (v))
50#define ST8(p, v) _ST((p), st, (v))
51#define LD1 LD
52#define LD2 LD
53#define LD4 LD
54#define LD8 LD
55#include "memcpy_64.c"
56
57#define USERCOPY_FUNC __copy_from_user_inatomic
58#define ST1 ST
59#define ST2 ST
60#define ST4 ST
61#define ST8 ST
62#define LD1(p) _LD((p), ld1u)
63#define LD2(p) _LD((p), ld2u)
64#define LD4(p) _LD((p), ld4u)
65#define LD8(p) _LD((p), ld)
66#include "memcpy_64.c"
67
68#define USERCOPY_FUNC __copy_in_user_inatomic
69#define ST1(p, v) _ST((p), st1, (v))
70#define ST2(p, v) _ST((p), st2, (v))
71#define ST4(p, v) _ST((p), st4, (v))
72#define ST8(p, v) _ST((p), st, (v))
73#define LD1(p) _LD((p), ld1u)
74#define LD2(p) _LD((p), ld2u)
75#define LD4(p) _LD((p), ld4u)
76#define LD8(p) _LD((p), ld)
77#include "memcpy_64.c"
78
79unsigned long __copy_from_user_zeroing(void *to, const void __user *from,
80 unsigned long n)
81{
82 unsigned long rc = __copy_from_user_inatomic(to, from, n);
83 if (unlikely(rc))
84 memset(to + n - rc, 0, rc);
85 return rc;
86}
diff --git a/arch/tile/lib/memset_64.c b/arch/tile/lib/memset_64.c
new file mode 100644
index 000000000000..3873085711d5
--- /dev/null
+++ b/arch/tile/lib/memset_64.c
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <arch/chip.h>
16
17#include <linux/types.h>
18#include <linux/string.h>
19#include <linux/module.h>
20
21#undef memset
22
23void *memset(void *s, int c, size_t n)
24{
25 uint64_t *out64;
26 int n64, to_align64;
27 uint64_t v64;
28 uint8_t *out8 = s;
29
30 /* Experimentation shows that a trivial tight loop is a win up until
31 * around a size of 20, where writing a word at a time starts to win.
32 */
33#define BYTE_CUTOFF 20
34
35#if BYTE_CUTOFF < 7
36 /* This must be at least at least this big, or some code later
37 * on doesn't work.
38 */
39#error "BYTE_CUTOFF is too small"
40#endif
41
42 if (n < BYTE_CUTOFF) {
43 /* Strangely, this turns out to be the tightest way to
44 * write this loop.
45 */
46 if (n != 0) {
47 do {
48 /* Strangely, combining these into one line
49 * performs worse.
50 */
51 *out8 = c;
52 out8++;
53 } while (--n != 0);
54 }
55
56 return s;
57 }
58
59 /* Align 'out8'. We know n >= 7 so this won't write past the end. */
60 while (((uintptr_t) out8 & 7) != 0) {
61 *out8++ = c;
62 --n;
63 }
64
65 /* Align 'n'. */
66 while (n & 7)
67 out8[--n] = c;
68
69 out64 = (uint64_t *) out8;
70 n64 = n >> 3;
71
72 /* Tile input byte out to 64 bits. */
73 /* KLUDGE */
74 v64 = 0x0101010101010101ULL * (uint8_t)c;
75
76 /* This must be at least 8 or the following loop doesn't work. */
77#define CACHE_LINE_SIZE_IN_DOUBLEWORDS (CHIP_L2_LINE_SIZE() / 8)
78
79 /* Determine how many words we need to emit before the 'out32'
80 * pointer becomes aligned modulo the cache line size.
81 */
82 to_align64 = (-((uintptr_t)out64 >> 3)) &
83 (CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1);
84
85 /* Only bother aligning and using wh64 if there is at least
86 * one full cache line to process. This check also prevents
87 * overrunning the end of the buffer with alignment words.
88 */
89 if (to_align64 <= n64 - CACHE_LINE_SIZE_IN_DOUBLEWORDS) {
90 int lines_left;
91
92 /* Align out64 mod the cache line size so we can use wh64. */
93 n64 -= to_align64;
94 for (; to_align64 != 0; to_align64--) {
95 *out64 = v64;
96 out64++;
97 }
98
99 /* Use unsigned divide to turn this into a right shift. */
100 lines_left = (unsigned)n64 / CACHE_LINE_SIZE_IN_DOUBLEWORDS;
101
102 do {
103 /* Only wh64 a few lines at a time, so we don't
104 * exceed the maximum number of victim lines.
105 */
106 int x = ((lines_left < CHIP_MAX_OUTSTANDING_VICTIMS())
107 ? lines_left
108 : CHIP_MAX_OUTSTANDING_VICTIMS());
109 uint64_t *wh = out64;
110 int i = x;
111 int j;
112
113 lines_left -= x;
114
115 do {
116 __insn_wh64(wh);
117 wh += CACHE_LINE_SIZE_IN_DOUBLEWORDS;
118 } while (--i);
119
120 for (j = x * (CACHE_LINE_SIZE_IN_DOUBLEWORDS / 4);
121 j != 0; j--) {
122 *out64++ = v64;
123 *out64++ = v64;
124 *out64++ = v64;
125 *out64++ = v64;
126 }
127 } while (lines_left != 0);
128
129 /* We processed all full lines above, so only this many
130 * words remain to be processed.
131 */
132 n64 &= CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1;
133 }
134
135 /* Now handle any leftover values. */
136 if (n64 != 0) {
137 do {
138 *out64 = v64;
139 out64++;
140 } while (--n64 != 0);
141 }
142
143 return s;
144}
145EXPORT_SYMBOL(memset);
diff --git a/arch/tile/lib/spinlock_64.c b/arch/tile/lib/spinlock_64.c
new file mode 100644
index 000000000000..d6fb9581e980
--- /dev/null
+++ b/arch/tile/lib/spinlock_64.c
@@ -0,0 +1,104 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/spinlock.h>
16#include <linux/module.h>
17#include <asm/processor.h>
18
19#include "spinlock_common.h"
20
21/*
22 * Read the spinlock value without allocating in our cache and without
23 * causing an invalidation to another cpu with a copy of the cacheline.
24 * This is important when we are spinning waiting for the lock.
25 */
26static inline u32 arch_spin_read_noalloc(void *lock)
27{
28 return atomic_cmpxchg((atomic_t *)lock, -1, -1);
29}
30
31/*
32 * Wait until the high bits (current) match my ticket.
33 * If we notice the overflow bit set on entry, we clear it.
34 */
35void arch_spin_lock_slow(arch_spinlock_t *lock, u32 my_ticket)
36{
37 if (unlikely(my_ticket & __ARCH_SPIN_NEXT_OVERFLOW)) {
38 __insn_fetchand4(&lock->lock, ~__ARCH_SPIN_NEXT_OVERFLOW);
39 my_ticket &= ~__ARCH_SPIN_NEXT_OVERFLOW;
40 }
41
42 for (;;) {
43 u32 val = arch_spin_read_noalloc(lock);
44 u32 delta = my_ticket - arch_spin_current(val);
45 if (delta == 0)
46 return;
47 relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
48 }
49}
50EXPORT_SYMBOL(arch_spin_lock_slow);
51
52/*
53 * Check the lock to see if it is plausible, and try to get it with cmpxchg().
54 */
55int arch_spin_trylock(arch_spinlock_t *lock)
56{
57 u32 val = arch_spin_read_noalloc(lock);
58 if (unlikely(arch_spin_current(val) != arch_spin_next(val)))
59 return 0;
60 return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW)
61 == val;
62}
63EXPORT_SYMBOL(arch_spin_trylock);
64
65void arch_spin_unlock_wait(arch_spinlock_t *lock)
66{
67 u32 iterations = 0;
68 while (arch_spin_is_locked(lock))
69 delay_backoff(iterations++);
70}
71EXPORT_SYMBOL(arch_spin_unlock_wait);
72
73/*
74 * If the read lock fails due to a writer, we retry periodically
75 * until the value is positive and we write our incremented reader count.
76 */
77void __read_lock_failed(arch_rwlock_t *rw)
78{
79 u32 val;
80 int iterations = 0;
81 do {
82 delay_backoff(iterations++);
83 val = __insn_fetchaddgez4(&rw->lock, 1);
84 } while (unlikely(arch_write_val_locked(val)));
85}
86EXPORT_SYMBOL(__read_lock_failed);
87
88/*
89 * If we failed because there were readers, clear the "writer" bit
90 * so we don't block additional readers. Otherwise, there was another
91 * writer anyway, so our "fetchor" made no difference. Then wait,
92 * issuing periodic fetchor instructions, till we get the lock.
93 */
94void __write_lock_failed(arch_rwlock_t *rw, u32 val)
95{
96 int iterations = 0;
97 do {
98 if (!arch_write_val_locked(val))
99 val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
100 delay_backoff(iterations++);
101 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
102 } while (val != 0);
103}
104EXPORT_SYMBOL(__write_lock_failed);
diff --git a/arch/tile/lib/strchr_64.c b/arch/tile/lib/strchr_64.c
new file mode 100644
index 000000000000..617a9273aaa8
--- /dev/null
+++ b/arch/tile/lib/strchr_64.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18
19#undef strchr
20
21char *strchr(const char *s, int c)
22{
23 int z, g;
24
25 /* Get an aligned pointer. */
26 const uintptr_t s_int = (uintptr_t) s;
27 const uint64_t *p = (const uint64_t *)(s_int & -8);
28
29 /* Create eight copies of the byte for which we are looking. */
30 const uint64_t goal = 0x0101010101010101ULL * (uint8_t) c;
31
32 /* Read the first aligned word, but force bytes before the string to
33 * match neither zero nor goal (we make sure the high bit of each
34 * byte is 1, and the low 7 bits are all the opposite of the goal
35 * byte).
36 *
37 * Note that this shift count expression works because we know shift
38 * counts are taken mod 64.
39 */
40 const uint64_t before_mask = (1ULL << (s_int << 3)) - 1;
41 uint64_t v = (*p | before_mask) ^
42 (goal & __insn_v1shrsi(before_mask, 1));
43
44 uint64_t zero_matches, goal_matches;
45 while (1) {
46 /* Look for a terminating '\0'. */
47 zero_matches = __insn_v1cmpeqi(v, 0);
48
49 /* Look for the goal byte. */
50 goal_matches = __insn_v1cmpeq(v, goal);
51
52 if (__builtin_expect((zero_matches | goal_matches) != 0, 0))
53 break;
54
55 v = *++p;
56 }
57
58 z = __insn_ctz(zero_matches);
59 g = __insn_ctz(goal_matches);
60
61 /* If we found c before '\0' we got a match. Note that if c == '\0'
62 * then g == z, and we correctly return the address of the '\0'
63 * rather than NULL.
64 */
65 return (g <= z) ? ((char *)p) + (g >> 3) : NULL;
66}
67EXPORT_SYMBOL(strchr);
diff --git a/arch/tile/lib/strlen_64.c b/arch/tile/lib/strlen_64.c
new file mode 100644
index 000000000000..1c92d46202a8
--- /dev/null
+++ b/arch/tile/lib/strlen_64.c
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18
19#undef strlen
20
21size_t strlen(const char *s)
22{
23 /* Get an aligned pointer. */
24 const uintptr_t s_int = (uintptr_t) s;
25 const uint64_t *p = (const uint64_t *)(s_int & -8);
26
27 /* Read the first word, but force bytes before the string to be nonzero.
28 * This expression works because we know shift counts are taken mod 64.
29 */
30 uint64_t v = *p | ((1ULL << (s_int << 3)) - 1);
31
32 uint64_t bits;
33 while ((bits = __insn_v1cmpeqi(v, 0)) == 0)
34 v = *++p;
35
36 return ((const char *)p) + (__insn_ctz(bits) >> 3) - s;
37}
38EXPORT_SYMBOL(strlen);
diff --git a/arch/tile/lib/usercopy_64.S b/arch/tile/lib/usercopy_64.S
new file mode 100644
index 000000000000..2ff44f87b78e
--- /dev/null
+++ b/arch/tile/lib/usercopy_64.S
@@ -0,0 +1,196 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/linkage.h>
16#include <asm/errno.h>
17#include <asm/cache.h>
18#include <arch/chip.h>
19
20/* Access user memory, but use MMU to avoid propagating kernel exceptions. */
21
22 .pushsection .fixup,"ax"
23
24get_user_fault:
25 { movei r1, -EFAULT; move r0, zero }
26 jrp lr
27 ENDPROC(get_user_fault)
28
29put_user_fault:
30 { movei r0, -EFAULT; jrp lr }
31 ENDPROC(put_user_fault)
32
33 .popsection
34
35/*
36 * __get_user_N functions take a pointer in r0, and return 0 in r1
37 * on success, with the value in r0; or else -EFAULT in r1.
38 */
39#define __get_user_N(bytes, LOAD) \
40 STD_ENTRY(__get_user_##bytes); \
411: { LOAD r0, r0; move r1, zero }; \
42 jrp lr; \
43 STD_ENDPROC(__get_user_##bytes); \
44 .pushsection __ex_table,"a"; \
45 .quad 1b, get_user_fault; \
46 .popsection
47
48__get_user_N(1, ld1u)
49__get_user_N(2, ld2u)
50__get_user_N(4, ld4u)
51__get_user_N(8, ld)
52
53/*
54 * __put_user_N functions take a value in r0 and a pointer in r1,
55 * and return 0 in r0 on success or -EFAULT on failure.
56 */
57#define __put_user_N(bytes, STORE) \
58 STD_ENTRY(__put_user_##bytes); \
591: { STORE r1, r0; move r0, zero }; \
60 jrp lr; \
61 STD_ENDPROC(__put_user_##bytes); \
62 .pushsection __ex_table,"a"; \
63 .quad 1b, put_user_fault; \
64 .popsection
65
66__put_user_N(1, st1)
67__put_user_N(2, st2)
68__put_user_N(4, st4)
69__put_user_N(8, st)
70
71/*
72 * strnlen_user_asm takes the pointer in r0, and the length bound in r1.
73 * It returns the length, including the terminating NUL, or zero on exception.
74 * If length is greater than the bound, returns one plus the bound.
75 */
76STD_ENTRY(strnlen_user_asm)
77 { beqz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
781: { ld1u r4, r0; addi r1, r1, -1 }
79 beqz r4, 2f
80 { bnezt r1, 1b; addi r0, r0, 1 }
812: { sub r0, r0, r3; jrp lr }
82 STD_ENDPROC(strnlen_user_asm)
83 .pushsection .fixup,"ax"
84strnlen_user_fault:
85 { move r0, zero; jrp lr }
86 ENDPROC(strnlen_user_fault)
87 .section __ex_table,"a"
88 .quad 1b, strnlen_user_fault
89 .popsection
90
91/*
92 * strncpy_from_user_asm takes the kernel target pointer in r0,
93 * the userspace source pointer in r1, and the length bound (including
94 * the trailing NUL) in r2. On success, it returns the string length
95 * (not including the trailing NUL), or -EFAULT on failure.
96 */
97STD_ENTRY(strncpy_from_user_asm)
98 { beqz r2, 2f; move r3, r0 }
991: { ld1u r4, r1; addi r1, r1, 1; addi r2, r2, -1 }
100 { st1 r0, r4; addi r0, r0, 1 }
101 beqz r2, 2f
102 bnezt r4, 1b
103 addi r0, r0, -1 /* don't count the trailing NUL */
1042: { sub r0, r0, r3; jrp lr }
105 STD_ENDPROC(strncpy_from_user_asm)
106 .pushsection .fixup,"ax"
107strncpy_from_user_fault:
108 { movei r0, -EFAULT; jrp lr }
109 ENDPROC(strncpy_from_user_fault)
110 .section __ex_table,"a"
111 .quad 1b, strncpy_from_user_fault
112 .popsection
113
114/*
115 * clear_user_asm takes the user target address in r0 and the
116 * number of bytes to zero in r1.
117 * It returns the number of uncopiable bytes (hopefully zero) in r0.
118 * Note that we don't use a separate .fixup section here since we fall
119 * through into the "fixup" code as the last straight-line bundle anyway.
120 */
121STD_ENTRY(clear_user_asm)
122 { beqz r1, 2f; or r2, r0, r1 }
123 andi r2, r2, 7
124 beqzt r2, .Lclear_aligned_user_asm
1251: { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
126 bnezt r1, 1b
1272: { move r0, r1; jrp lr }
128 .pushsection __ex_table,"a"
129 .quad 1b, 2b
130 .popsection
131
132.Lclear_aligned_user_asm:
1331: { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
134 bnezt r1, 1b
1352: { move r0, r1; jrp lr }
136 STD_ENDPROC(clear_user_asm)
137 .pushsection __ex_table,"a"
138 .quad 1b, 2b
139 .popsection
140
141/*
142 * flush_user_asm takes the user target address in r0 and the
143 * number of bytes to flush in r1.
144 * It returns the number of unflushable bytes (hopefully zero) in r0.
145 */
146STD_ENTRY(flush_user_asm)
147 beqz r1, 2f
148 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
149 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
150 { and r0, r0, r2; and r1, r1, r2 }
151 { sub r1, r1, r0 }
1521: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
153 { addi r0, r0, CHIP_FLUSH_STRIDE(); bnezt r1, 1b }
1542: { move r0, r1; jrp lr }
155 STD_ENDPROC(flush_user_asm)
156 .pushsection __ex_table,"a"
157 .quad 1b, 2b
158 .popsection
159
160/*
161 * inv_user_asm takes the user target address in r0 and the
162 * number of bytes to invalidate in r1.
163 * It returns the number of not inv'able bytes (hopefully zero) in r0.
164 */
165STD_ENTRY(inv_user_asm)
166 beqz r1, 2f
167 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
168 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
169 { and r0, r0, r2; and r1, r1, r2 }
170 { sub r1, r1, r0 }
1711: { inv r0; addi r1, r1, -CHIP_INV_STRIDE() }
172 { addi r0, r0, CHIP_INV_STRIDE(); bnezt r1, 1b }
1732: { move r0, r1; jrp lr }
174 STD_ENDPROC(inv_user_asm)
175 .pushsection __ex_table,"a"
176 .quad 1b, 2b
177 .popsection
178
179/*
180 * finv_user_asm takes the user target address in r0 and the
181 * number of bytes to flush-invalidate in r1.
182 * It returns the number of not finv'able bytes (hopefully zero) in r0.
183 */
184STD_ENTRY(finv_user_asm)
185 beqz r1, 2f
186 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
187 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
188 { and r0, r0, r2; and r1, r1, r2 }
189 { sub r1, r1, r0 }
1901: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
191 { addi r0, r0, CHIP_FINV_STRIDE(); bnezt r1, 1b }
1922: { move r0, r1; jrp lr }
193 STD_ENDPROC(finv_user_asm)
194 .pushsection __ex_table,"a"
195 .quad 1b, 2b
196 .popsection
diff --git a/arch/tile/mm/migrate_64.S b/arch/tile/mm/migrate_64.S
new file mode 100644
index 000000000000..e76fea688beb
--- /dev/null
+++ b/arch/tile/mm/migrate_64.S
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * This routine is a helper for migrating the home of a set of pages to
15 * a new cpu. See the documentation in homecache.c for more information.
16 */
17
18#include <linux/linkage.h>
19#include <linux/threads.h>
20#include <asm/page.h>
21#include <asm/thread_info.h>
22#include <asm/types.h>
23#include <asm/asm-offsets.h>
24#include <hv/hypervisor.h>
25
26 .text
27
28/*
29 * First, some definitions that apply to all the code in the file.
30 */
31
32/* Locals (caller-save) */
33#define r_tmp r10
34#define r_save_sp r11
35
36/* What we save where in the stack frame; must include all callee-saves. */
37#define FRAME_SP 8
38#define FRAME_R30 16
39#define FRAME_R31 24
40#define FRAME_R32 32
41#define FRAME_R33 40
42#define FRAME_SIZE 48
43
44
45
46
47/*
48 * On entry:
49 *
50 * r0 the new context PA to install (moved to r_context)
51 * r1 PTE to use for context access (moved to r_access)
52 * r2 ASID to use for new context (moved to r_asid)
53 * r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
54 */
55
56/* Arguments (caller-save) */
57#define r_context_in r0
58#define r_access_in r1
59#define r_asid_in r2
60#define r_my_cpumask r3
61
62/* Locals (callee-save); must not be more than FRAME_xxx above. */
63#define r_save_ics r30
64#define r_context r31
65#define r_access r32
66#define r_asid r33
67
68/*
69 * Caller-save locals and frame constants are the same as
70 * for homecache_migrate_stack_and_flush.
71 */
72
73STD_ENTRY(flush_and_install_context)
74 /*
75 * Create a stack frame; we can't touch it once we flush the
76 * cache until we install the new page table and flush the TLB.
77 */
78 {
79 move r_save_sp, sp
80 st sp, lr
81 addi sp, sp, -FRAME_SIZE
82 }
83 addi r_tmp, sp, FRAME_SP
84 {
85 st r_tmp, r_save_sp
86 addi r_tmp, sp, FRAME_R30
87 }
88 {
89 st r_tmp, r30
90 addi r_tmp, sp, FRAME_R31
91 }
92 {
93 st r_tmp, r31
94 addi r_tmp, sp, FRAME_R32
95 }
96 {
97 st r_tmp, r32
98 addi r_tmp, sp, FRAME_R33
99 }
100 st r_tmp, r33
101
102 /* Move some arguments to callee-save registers. */
103 {
104 move r_context, r_context_in
105 move r_access, r_access_in
106 }
107 move r_asid, r_asid_in
108
109 /* Disable interrupts, since we can't use our stack. */
110 {
111 mfspr r_save_ics, INTERRUPT_CRITICAL_SECTION
112 movei r_tmp, 1
113 }
114 mtspr INTERRUPT_CRITICAL_SECTION, r_tmp
115
116 /* First, flush our L2 cache. */
117 {
118 move r0, zero /* cache_pa */
119 moveli r1, hw2_last(HV_FLUSH_EVICT_L2) /* cache_control */
120 }
121 {
122 shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
123 move r2, r_my_cpumask /* cache_cpumask */
124 }
125 {
126 shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
127 move r3, zero /* tlb_va */
128 }
129 {
130 move r4, zero /* tlb_length */
131 move r5, zero /* tlb_pgsize */
132 }
133 {
134 move r6, zero /* tlb_cpumask */
135 move r7, zero /* asids */
136 }
137 {
138 move r8, zero /* asidcount */
139 jal hv_flush_remote
140 }
141 bnez r0, 1f
142
143 /* Now install the new page table. */
144 {
145 move r0, r_context
146 move r1, r_access
147 }
148 {
149 move r2, r_asid
150 movei r3, HV_CTX_DIRECTIO
151 }
152 jal hv_install_context
153 bnez r0, 1f
154
155 /* Finally, flush the TLB. */
156 {
157 movei r0, 0 /* preserve_global */
158 jal hv_flush_all
159 }
160
1611: /* Reset interrupts back how they were before. */
162 mtspr INTERRUPT_CRITICAL_SECTION, r_save_ics
163
164 /* Restore the callee-saved registers and return. */
165 addli lr, sp, FRAME_SIZE
166 {
167 ld lr, lr
168 addli r_tmp, sp, FRAME_R30
169 }
170 {
171 ld r30, r_tmp
172 addli r_tmp, sp, FRAME_R31
173 }
174 {
175 ld r31, r_tmp
176 addli r_tmp, sp, FRAME_R32
177 }
178 {
179 ld r32, r_tmp
180 addli r_tmp, sp, FRAME_R33
181 }
182 {
183 ld r33, r_tmp
184 addi sp, sp, FRAME_SIZE
185 }
186 jrp lr
187 STD_ENDPROC(flush_and_install_context)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 07:42:46 -0500