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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-26 18:46:22 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-26 18:46:22 -0400
commite8b374bb6c888a70530d800c9e2fcd153e2c325d (patch)
treeab6f8ef88d3526ff00eb60e15371a3eaa303a456 /arch
parentf5f0e17a8475dee913f362510e6a8ab987d27b9f (diff)
parent1288b670e6cb3745392de617f223672396f98d73 (diff)
Merge branch 'next-s3c64xx-regs' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s3c6400/include/mach/map.h3
-rw-r--r--arch/arm/plat-s3c64xx/cpu.c5
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h25
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-gpio.h186
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-modem.h31
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-sys.h4
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h116
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c14
8 files changed, 353 insertions, 31 deletions
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index cff27d813fc6..baf1c0f1ea5a 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -52,6 +52,9 @@
52#define S3C64XX_PA_VIC0 (0x71200000) 52#define S3C64XX_PA_VIC0 (0x71200000)
53#define S3C64XX_PA_VIC1 (0x71300000) 53#define S3C64XX_PA_VIC1 (0x71300000)
54 54
55#define S3C64XX_PA_MODEM (0x74108000)
56#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
57
55/* place VICs close together */ 58/* place VICs close together */
56#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) 59#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
57#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 60#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index fbde183a4560..91f49a3a665d 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -96,6 +96,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
96 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), 96 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
97 .length = SZ_4K, 97 .length = SZ_4K,
98 .type = MT_DEVICE, 98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S3C64XX_VA_MODEM,
101 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
99 }, 104 },
100}; 105};
101 106
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
new file mode 100644
index 000000000000..82342f6fd27d
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO memory port register definitions
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
12#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
13
14#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
16
17#define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18#define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19#define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
20
21#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
23
24#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
25
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
index 75b873d82808..81f7f6e6832e 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
@@ -13,23 +13,175 @@
13 13
14/* Base addresses for each of the banks */ 14/* Base addresses for each of the banks */
15 15
16#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) 16#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg))
17#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) 17
18#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) 18#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
19#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) 19#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
20#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) 20#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
21#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) 21#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
22#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) 22#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
23#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) 23#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
24#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) 24#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
25#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) 25#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
26#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) 26#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
27#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) 27#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
28#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) 28#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800)
29#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) 29#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810)
30#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) 30#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820)
31#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) 31#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830)
32#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) 32#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140)
33#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160)
34#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180)
35
36/* SPCON */
37
38#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0)
39
40#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30)
41#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30)
42#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30)
43#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30)
44#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30)
45#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30)
46
47#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28)
48#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28)
49#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28)
50#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28)
51#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28)
52#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28)
53
54#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26)
55#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26)
56#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26)
57#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26)
58#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26)
59#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26)
60
61#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24)
62#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24)
63#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24)
64#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24)
65#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24)
66#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24)
67
68#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22)
69#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22)
70#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22)
71#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22)
72#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22)
73#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22)
74
75#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21)
76
77#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18)
78#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18)
79#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18)
80#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18)
81#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18)
82#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18)
83
84#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16)
85#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16)
86#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16)
87#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16)
88#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16)
89
90#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14)
91#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14)
92#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14)
93#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14)
94#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14)
95
96#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12)
97#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12)
98#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12)
99#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12)
100#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12)
101
102#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8)
103#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8)
104#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8)
105#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8)
106#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8)
107
108#define S3C64XX_SPCON_USBH_DMPD (1 << 7)
109#define S3C64XX_SPCON_USBH_DPPD (1 << 6)
110#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5)
111#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4)
112#define S3C64XX_SPCON_USBH_SUSPND (1 << 3)
113
114#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0)
115#define S3C64XX_SPCON_LCD_SEL_SHIFT (0)
116#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0)
117#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0)
118#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0)
119
120
121/* External interrupt registers */
122
123#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200)
124#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204)
125#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208)
126#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C)
127#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210)
128
129#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220)
130#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224)
131#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228)
132#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C)
133#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230)
134
135#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240)
136#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244)
137#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248)
138#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C)
139#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250)
140
141#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260)
142#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264)
143#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268)
144#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C)
145#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270)
146
147#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280)
148#define S3C64XX_PRIORITY_ARB(x) (1 << (x))
149
150#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284)
151#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288)
152
153#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
154#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
155#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
156#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
157#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
158#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
159
160#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
161#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
162
163/* GPIO sleep configuration */
164
165#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880)
166
167#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14)
168#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5)
169
170#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12)
171#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12)
172#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12)
173#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12)
174
175#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0)
176#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0)
177#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0)
178#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0)
179
180
181#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930)
182
183#define S3C64XX_SLPEN_USE_xSLP (1 << 0)
184#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1)
33 185
34#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ 186#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
35 187
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-modem.h b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
new file mode 100644
index 000000000000..49f7759dedfa
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
@@ -0,0 +1,31 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - modem block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_MODEM_H
16#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
17
18#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x))
19
20#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0)
21#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4)
22#define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8)
23#define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC)
24#define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10)
25#define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14)
26#define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18)
27
28#define MIFPCON_INT2M_LEVEL (1 << 4)
29#define MIFPCON_LCD_BYPASS (1 << 3)
30
31#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
index d8ed82917096..69b78d9f83b8 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
@@ -17,6 +17,10 @@
17 17
18#define S3C_SYSREG(x) (S3C_VA_SYS + (x)) 18#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
19 19
20#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
23
20#define S3C64XX_OTHERS S3C_SYSREG(0x900) 24#define S3C64XX_OTHERS S3C_SYSREG(0x900)
21 25
22#define S3C64XX_OTHERS_USBMASK (1 << 16) 26#define S3C64XX_OTHERS_USBMASK (1 << 16)
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
new file mode 100644
index 000000000000..270d96ac9705
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
@@ -0,0 +1,116 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - syscon power and sleep control registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
16#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
17
18#define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
19
20#define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17)
21#define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16)
22#define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15)
23#define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14)
24#define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13)
25#define S3C64XX_PWRCFG_TS_DISABLE (1 << 12)
26#define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11)
27#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10)
28#define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9)
29#define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8)
30#define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7)
31
32#define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
33#define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5)
34#define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
35#define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
36#define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
37#define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
38
39#define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
40#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3)
41#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
42#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
43#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
44
45#define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2)
46#define S3C64XX_PWRCFG_OSC27_EN (1 << 0)
47
48#define S3C64XX_EINT_MASK S3C_SYSREG(0x808)
49
50#define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810)
51
52#define S3C64XX_NORMALCFG_IROM_ON (1 << 30)
53#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16)
54#define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15)
55#define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14)
56#define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13)
57#define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12)
58#define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10)
59#define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9)
60
61#define S3C64XX_STOP_CFG S3C_SYSREG(0x814)
62
63#define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29)
64#define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20)
65#define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17)
66#define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8)
67#define S3C64XX_STOPCFG_OSC_EN (1 << 0)
68
69#define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818)
70
71#define S3C64XX_SLEEPCFG_OSC_EN (1 << 0)
72
73#define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c)
74
75#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6)
76#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5)
77#define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4)
78#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3)
79#define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2)
80#define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1)
81#define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0)
82
83#define S3C64XX_OSC_STABLE S3C_SYSREG(0x824)
84#define S3C64XX_PWR_STABLE S3C_SYSREG(0x828)
85
86#define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908)
87
88#define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11)
89#define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10)
90#define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9)
91#define S3C64XX_WAKEUPSTAT_HSI (1 << 8)
92#define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6)
93#define S3C64XX_WAKEUPSTAT_MSM (1 << 5)
94#define S3C64XX_WAKEUPSTAT_KEY (1 << 4)
95#define S3C64XX_WAKEUPSTAT_TS (1 << 3)
96#define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2)
97#define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1)
98#define S3C64XX_WAKEUPSTAT_EINT (1 << 0)
99
100#define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c)
101
102#define S3C64XX_BLKPWRSTAT_G (1 << 7)
103#define S3C64XX_BLKPWRSTAT_ETM (1 << 6)
104#define S3C64XX_BLKPWRSTAT_S (1 << 5)
105#define S3C64XX_BLKPWRSTAT_F (1 << 4)
106#define S3C64XX_BLKPWRSTAT_P (1 << 3)
107#define S3C64XX_BLKPWRSTAT_I (1 << 2)
108#define S3C64XX_BLKPWRSTAT_V (1 << 1)
109#define S3C64XX_BLKPWRSTAT_TOP (1 << 0)
110
111#define S3C64XX_INFORM0 S3C_SYSREG(0xA00)
112#define S3C64XX_INFORM1 S3C_SYSREG(0xA04)
113#define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
114#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
115
116#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index cf524826c93a..47e5155bb13e 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -27,20 +27,6 @@
27#include <mach/map.h> 27#include <mach/map.h>
28#include <plat/cpu.h> 28#include <plat/cpu.h>
29 29
30/* GPIO is 0x7F008xxx, */
31#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
32
33#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
34#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
35#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
36#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
37#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
38#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
39
40#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
41#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
42
43
44#define eint_offset(irq) ((irq) - IRQ_EINT(0)) 30#define eint_offset(irq) ((irq) - IRQ_EINT(0))
45#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) 31#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
46 32