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authorJames Bottomley <James.Bottomley@SteelEye.com>2006-06-27 05:53:49 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-27 20:32:38 -0400
commit96c52749036eca2b131f435d3895a3c6aba92e76 (patch)
tree77b92dfa86d4d81b3ee11f2517e118c6025026c6 /arch
parent4031ff388138b58e5cd472dccce38828bcb8c706 (diff)
[PATCH] fix subarchitecture breakage with CONFIG_SCHED_SMT
Commit 1e9f28fa1eb9773bf65bae08288c6a0a38eef4a7 ("[PATCH] sched: new sched domain for representing multi-core") incorrectly made SCHED_SMT and some of the structures it uses dependent on SMP. However, this is wrong, the structures are only defined if X86_HT, so SCHED_SMT has to depend on that as well. The patch broke voyager, since it doesn't provide any of the multi-core or hyperthreading structures. Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/i386/Kconfig4
-rw-r--r--arch/i386/kernel/cpu/common.c2
-rw-r--r--arch/i386/kernel/cpu/intel_cacheinfo.c6
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig
index 47c08bcd9b24..6662f8c44798 100644
--- a/arch/i386/Kconfig
+++ b/arch/i386/Kconfig
@@ -233,7 +233,7 @@ config NR_CPUS
233 233
234config SCHED_SMT 234config SCHED_SMT
235 bool "SMT (Hyperthreading) scheduler support" 235 bool "SMT (Hyperthreading) scheduler support"
236 depends on SMP 236 depends on X86_HT
237 help 237 help
238 SMT scheduler support improves the CPU scheduler's decision making 238 SMT scheduler support improves the CPU scheduler's decision making
239 when dealing with Intel Pentium 4 chips with HyperThreading at a 239 when dealing with Intel Pentium 4 chips with HyperThreading at a
@@ -242,7 +242,7 @@ config SCHED_SMT
242 242
243config SCHED_MC 243config SCHED_MC
244 bool "Multi-core scheduler support" 244 bool "Multi-core scheduler support"
245 depends on SMP 245 depends on X86_HT
246 default y 246 default y
247 help 247 help
248 Multi-core scheduler support improves the CPU scheduler's decision 248 Multi-core scheduler support improves the CPU scheduler's decision
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 2fa401f19f37..70c87de582c7 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -294,7 +294,7 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
294 if (c->x86 >= 0x6) 294 if (c->x86 >= 0x6)
295 c->x86_model += ((tfms >> 16) & 0xF) << 4; 295 c->x86_model += ((tfms >> 16) & 0xF) << 4;
296 c->x86_mask = tfms & 15; 296 c->x86_mask = tfms & 15;
297#ifdef CONFIG_SMP 297#ifdef CONFIG_X86_HT
298 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); 298 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
299#else 299#else
300 c->apicid = (ebx >> 24) & 0xFF; 300 c->apicid = (ebx >> 24) & 0xFF;
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index f24a0145024c..8a92642ea590 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -261,7 +261,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
261 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ 261 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
262 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ 262 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
263 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb; 263 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
264#ifdef CONFIG_SMP 264#ifdef CONFIG_X86_HT
265 unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data); 265 unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data);
266#endif 266#endif
267 267
@@ -383,14 +383,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
383 383
384 if (new_l2) { 384 if (new_l2) {
385 l2 = new_l2; 385 l2 = new_l2;
386#ifdef CONFIG_SMP 386#ifdef CONFIG_X86_HT
387 cpu_llc_id[cpu] = l2_id; 387 cpu_llc_id[cpu] = l2_id;
388#endif 388#endif
389 } 389 }
390 390
391 if (new_l3) { 391 if (new_l3) {
392 l3 = new_l3; 392 l3 = new_l3;
393#ifdef CONFIG_SMP 393#ifdef CONFIG_X86_HT
394 cpu_llc_id[cpu] = l3_id; 394 cpu_llc_id[cpu] = l3_id;
395#endif 395#endif
396 } 396 }