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authorMuli Ben-Yehuda <muli@il.ibm.com>2007-07-21 11:10:55 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-21 21:37:11 -0400
commit8cb32dc748571fb474018172e6b59e5a06123192 (patch)
tree7b9352dd6fa3adc230e241b547f38f0fdac03966 /arch
parent00be3fa42f164f7e2783a5acf9766fb07fb64e68 (diff)
x86_64: make dump_error_regs a chip op
Provide seperate versions for Calgary and CalIOC2 Also print out the PCIe Root Complex Status on CalIOC2 errors Signed-off-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86_64/kernel/pci-calgary.c42
1 files changed, 34 insertions, 8 deletions
diff --git a/arch/x86_64/kernel/pci-calgary.c b/arch/x86_64/kernel/pci-calgary.c
index 765c521dd85f..f5828db15220 100644
--- a/arch/x86_64/kernel/pci-calgary.c
+++ b/arch/x86_64/kernel/pci-calgary.c
@@ -83,6 +83,7 @@ int use_calgary __read_mostly = 0;
83#define PHB_SAVIOR_L2 0x0DB0 83#define PHB_SAVIOR_L2 0x0DB0
84#define PHB_PAGE_MIG_CTRL 0x0DA8 84#define PHB_PAGE_MIG_CTRL 0x0DA8
85#define PHB_PAGE_MIG_DEBUG 0x0DA0 85#define PHB_PAGE_MIG_DEBUG 0x0DA0
86#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
86 87
87/* PHB_CONFIG_RW */ 88/* PHB_CONFIG_RW */
88#define PHB_TCE_ENABLE 0x20000000 89#define PHB_TCE_ENABLE 0x20000000
@@ -165,17 +166,21 @@ struct calgary_bus_info {
165 166
166static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); 167static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
167static void calgary_tce_cache_blast(struct iommu_table *tbl); 168static void calgary_tce_cache_blast(struct iommu_table *tbl);
169static void calgary_dump_error_regs(struct iommu_table *tbl);
168static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); 170static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
169static void calioc2_tce_cache_blast(struct iommu_table *tbl); 171static void calioc2_tce_cache_blast(struct iommu_table *tbl);
172static void calioc2_dump_error_regs(struct iommu_table *tbl);
170 173
171static struct cal_chipset_ops calgary_chip_ops = { 174static struct cal_chipset_ops calgary_chip_ops = {
172 .handle_quirks = calgary_handle_quirks, 175 .handle_quirks = calgary_handle_quirks,
173 .tce_cache_blast = calgary_tce_cache_blast 176 .tce_cache_blast = calgary_tce_cache_blast,
177 .dump_error_regs = calgary_dump_error_regs
174}; 178};
175 179
176static struct cal_chipset_ops calioc2_chip_ops = { 180static struct cal_chipset_ops calioc2_chip_ops = {
177 .handle_quirks = calioc2_handle_quirks, 181 .handle_quirks = calioc2_handle_quirks,
178 .tce_cache_blast = calioc2_tce_cache_blast 182 .tce_cache_blast = calioc2_tce_cache_blast,
183 .dump_error_regs = calioc2_dump_error_regs
179}; 184};
180 185
181static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; 186static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
@@ -895,7 +900,21 @@ static void __init calgary_free_bus(struct pci_dev *dev)
895static void calgary_dump_error_regs(struct iommu_table *tbl) 900static void calgary_dump_error_regs(struct iommu_table *tbl)
896{ 901{
897 void __iomem *bbar = tbl->bbar; 902 void __iomem *bbar = tbl->bbar;
898 u32 csr, csmr, plssr, mck; 903 u32 val32;
904 void __iomem *target;
905
906 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
907 val32 = be32_to_cpu(readl(target));
908
909 /* If no error, the agent ID in the CSR is not valid */
910 printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
911 "CSR = 0x%08x\n", tbl->it_busno, val32);
912}
913
914static void calioc2_dump_error_regs(struct iommu_table *tbl)
915{
916 void __iomem *bbar = tbl->bbar;
917 u32 csr, csmr, plssr, mck, rcstat;
899 void __iomem *target; 918 void __iomem *target;
900 unsigned long phboff = phb_offset(tbl->it_busno); 919 unsigned long phboff = phb_offset(tbl->it_busno);
901 unsigned long erroff; 920 unsigned long erroff;
@@ -915,8 +934,11 @@ static void calgary_dump_error_regs(struct iommu_table *tbl)
915 target = calgary_reg(bbar, phboff | 0x800); 934 target = calgary_reg(bbar, phboff | 0x800);
916 mck = be32_to_cpu(readl(target)); 935 mck = be32_to_cpu(readl(target));
917 936
918 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR " 937 printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
919 "0x%08x@MCK\n", csr, plssr, csmr, mck); 938 tbl->it_busno);
939
940 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
941 csr, plssr, csmr, mck);
920 942
921 /* dump rest of error regs */ 943 /* dump rest of error regs */
922 printk(KERN_EMERG "Calgary: "); 944 printk(KERN_EMERG "Calgary: ");
@@ -927,6 +949,12 @@ static void calgary_dump_error_regs(struct iommu_table *tbl)
927 printk("0x%08x@0x%lx ", errregs[i], erroff); 949 printk("0x%08x@0x%lx ", errregs[i], erroff);
928 } 950 }
929 printk("\n"); 951 printk("\n");
952
953 /* root complex status */
954 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
955 rcstat = be32_to_cpu(readl(target));
956 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
957 PHB_ROOT_COMPLEX_STATUS);
930} 958}
931 959
932static void calgary_watchdog(unsigned long data) 960static void calgary_watchdog(unsigned long data)
@@ -942,9 +970,7 @@ static void calgary_watchdog(unsigned long data)
942 970
943 /* If no error, the agent ID in the CSR is not valid */ 971 /* If no error, the agent ID in the CSR is not valid */
944 if (val32 & CSR_AGENT_MASK) { 972 if (val32 & CSR_AGENT_MASK) {
945 printk(KERN_EMERG "Calgary: DMA error on PHB %#x\n", 973 tbl->chip_ops->dump_error_regs(tbl);
946 dev->bus->number);
947 calgary_dump_error_regs(tbl);
948 974
949 /* reset error */ 975 /* reset error */
950 writel(0, target); 976 writel(0, target);