diff options
author | Eric Bénard <eric@eukrea.com> | 2010-10-11 15:55:24 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-10-19 12:44:59 -0400 |
commit | 0076232d54b3fb2908c7fcf19bf699c4e8376213 (patch) | |
tree | b57f940e887e4d9049e56d81e910de8af3235182 /arch | |
parent | c0550c4bf1a6b868ac98b63f88ffd1a7ebdbeaeb (diff) |
clock-mx51: factorize clk_set_parent and clk_get_rate
Signed-off-by: Eric Bénard <eric@eukrea.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx5/clock-mx51.c | 142 |
1 files changed, 48 insertions, 94 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 21cecc040172..7deb6837937a 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c | |||
@@ -544,35 +544,6 @@ static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) | |||
544 | return 0; | 544 | return 0; |
545 | } | 545 | } |
546 | 546 | ||
547 | static unsigned long clk_uart_get_rate(struct clk *clk) | ||
548 | { | ||
549 | u32 reg, prediv, podf; | ||
550 | unsigned long parent_rate; | ||
551 | |||
552 | parent_rate = clk_get_rate(clk->parent); | ||
553 | |||
554 | reg = __raw_readl(MXC_CCM_CSCDR1); | ||
555 | prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> | ||
556 | MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; | ||
557 | podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> | ||
558 | MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; | ||
559 | |||
560 | return parent_rate / (prediv * podf); | ||
561 | } | ||
562 | |||
563 | static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) | ||
564 | { | ||
565 | u32 reg, mux; | ||
566 | |||
567 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, | ||
568 | &lp_apm_clk); | ||
569 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; | ||
570 | reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; | ||
571 | __raw_writel(reg, MXC_CCM_CSCMR1); | ||
572 | |||
573 | return 0; | ||
574 | } | ||
575 | |||
576 | #define clk_nfc_set_parent NULL | 547 | #define clk_nfc_set_parent NULL |
577 | 548 | ||
578 | static unsigned long clk_nfc_get_rate(struct clk *clk) | 549 | static unsigned long clk_nfc_get_rate(struct clk *clk) |
@@ -631,35 +602,6 @@ static int clk_nfc_set_rate(struct clk *clk, unsigned long rate) | |||
631 | return 0; | 602 | return 0; |
632 | } | 603 | } |
633 | 604 | ||
634 | static unsigned long clk_usboh3_get_rate(struct clk *clk) | ||
635 | { | ||
636 | u32 reg, prediv, podf; | ||
637 | unsigned long parent_rate; | ||
638 | |||
639 | parent_rate = clk_get_rate(clk->parent); | ||
640 | |||
641 | reg = __raw_readl(MXC_CCM_CSCDR1); | ||
642 | prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> | ||
643 | MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; | ||
644 | podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> | ||
645 | MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; | ||
646 | |||
647 | return parent_rate / (prediv * podf); | ||
648 | } | ||
649 | |||
650 | static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) | ||
651 | { | ||
652 | u32 reg, mux; | ||
653 | |||
654 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, | ||
655 | &lp_apm_clk); | ||
656 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; | ||
657 | reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; | ||
658 | __raw_writel(reg, MXC_CCM_CSCMR1); | ||
659 | |||
660 | return 0; | ||
661 | } | ||
662 | |||
663 | static unsigned long get_high_reference_clock_rate(struct clk *clk) | 605 | static unsigned long get_high_reference_clock_rate(struct clk *clk) |
664 | { | 606 | { |
665 | return external_high_reference; | 607 | return external_high_reference; |
@@ -786,18 +728,6 @@ static struct clk ipg_perclk = { | |||
786 | .set_parent = _clk_ipg_per_set_parent, | 728 | .set_parent = _clk_ipg_per_set_parent, |
787 | }; | 729 | }; |
788 | 730 | ||
789 | static struct clk uart_root_clk = { | ||
790 | .parent = &pll2_sw_clk, | ||
791 | .get_rate = clk_uart_get_rate, | ||
792 | .set_parent = _clk_uart_set_parent, | ||
793 | }; | ||
794 | |||
795 | static struct clk usboh3_clk = { | ||
796 | .parent = &pll2_sw_clk, | ||
797 | .get_rate = clk_usboh3_get_rate, | ||
798 | .set_parent = _clk_usboh3_set_parent, | ||
799 | }; | ||
800 | |||
801 | static struct clk ahb_max_clk = { | 731 | static struct clk ahb_max_clk = { |
802 | .parent = &ahb_clk, | 732 | .parent = &ahb_clk, |
803 | .enable_reg = MXC_CCM_CCGR0, | 733 | .enable_reg = MXC_CCM_CCGR0, |
@@ -857,35 +787,59 @@ static struct clk emi_slow_clk = { | |||
857 | .secondary = s, \ | 787 | .secondary = s, \ |
858 | } | 788 | } |
859 | 789 | ||
860 | /* eCSPI */ | 790 | #define CLK_GET_RATE(name, nr, bitsname) \ |
861 | static unsigned long clk_ecspi_get_rate(struct clk *clk) | 791 | static unsigned long clk_##name##_get_rate(struct clk *clk) \ |
862 | { | 792 | { \ |
863 | u32 reg, pred, podf; | 793 | u32 reg, pred, podf; \ |
864 | 794 | \ | |
865 | reg = __raw_readl(MXC_CCM_CSCDR2); | 795 | reg = __raw_readl(MXC_CCM_CSCDR##nr); \ |
866 | 796 | pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \ | |
867 | pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> | 797 | >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \ |
868 | MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; | 798 | podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \ |
869 | podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> | 799 | >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \ |
870 | MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; | 800 | \ |
871 | 801 | return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \ | |
872 | return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), | 802 | (pred + 1) * (podf + 1)); \ |
873 | (pred + 1) * (podf + 1)); | 803 | } |
804 | |||
805 | #define CLK_SET_PARENT(name, nr, bitsname) \ | ||
806 | static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \ | ||
807 | { \ | ||
808 | u32 reg, mux; \ | ||
809 | \ | ||
810 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \ | ||
811 | &pll3_sw_clk, &lp_apm_clk); \ | ||
812 | reg = __raw_readl(MXC_CCM_CSCMR##nr) & \ | ||
813 | ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \ | ||
814 | reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \ | ||
815 | __raw_writel(reg, MXC_CCM_CSCMR##nr); \ | ||
816 | \ | ||
817 | return 0; \ | ||
874 | } | 818 | } |
875 | 819 | ||
876 | static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent) | 820 | /* UART */ |
877 | { | 821 | CLK_GET_RATE(uart, 1, UART) |
878 | u32 reg, mux; | 822 | CLK_SET_PARENT(uart, 1, UART) |
879 | 823 | ||
880 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, | 824 | static struct clk uart_root_clk = { |
881 | &lp_apm_clk); | 825 | .parent = &pll2_sw_clk, |
826 | .get_rate = clk_uart_get_rate, | ||
827 | .set_parent = clk_uart_set_parent, | ||
828 | }; | ||
882 | 829 | ||
883 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; | 830 | /* USBOH3 */ |
884 | reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; | 831 | CLK_GET_RATE(usboh3, 1, USBOH3) |
885 | __raw_writel(reg, MXC_CCM_CSCMR1); | 832 | CLK_SET_PARENT(usboh3, 1, USBOH3) |
886 | 833 | ||
887 | return 0; | 834 | static struct clk usboh3_clk = { |
888 | } | 835 | .parent = &pll2_sw_clk, |
836 | .get_rate = clk_usboh3_get_rate, | ||
837 | .set_parent = clk_usboh3_set_parent, | ||
838 | }; | ||
839 | |||
840 | /* eCSPI */ | ||
841 | CLK_GET_RATE(ecspi, 2, CSPI) | ||
842 | CLK_SET_PARENT(ecspi, 1, CSPI) | ||
889 | 843 | ||
890 | static struct clk ecspi_main_clk = { | 844 | static struct clk ecspi_main_clk = { |
891 | .parent = &pll3_sw_clk, | 845 | .parent = &pll3_sw_clk, |