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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-12 17:19:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-12 17:19:51 -0400
commitd93a881dd7d71ad0e6504af232be2795044ab686 (patch)
tree71fc6918e676a0cf53d585f5a253646a49b60c83 /arch
parentd1ca1a004822983e2fc702d5382b4b9a5527cfbe (diff)
parent24109afd17426e1a2b72141e4a2b730057e1a0ea (diff)
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: pcmcia: pxa2xx/vpac270: free gpios on exist rather than requesting ARM: pxa/raumfeld: fix device name for codec ak4104 ARM: pxa/raumfeld: display initialisation fixes ARM: pxa/raumfeld: adapt to upcoming hardware change ARM: pxa: fix gpio_to_chip() clash with gpiolib namespace genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd) arm: mach-vt8500: add forgotten irq_data conversion ARM: pxa168: correct nand pmu setting ARM: pxa910: correct nand pmu setting ARM: pxa: fix PGSR register address calculation
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/irq.c2
-rw-r--r--arch/arm/mach-mmp/pxa168.c2
-rw-r--r--arch/arm/mach-mmp/pxa910.c2
-rw-r--r--arch/arm/mach-pxa/mfp-pxa2xx.c4
-rw-r--r--arch/arm/mach-pxa/raumfeld.c36
-rw-r--r--arch/arm/plat-orion/gpio.c2
-rw-r--r--arch/arm/plat-pxa/gpio.c10
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c2
-rw-r--r--arch/arm/plat-samsung/irq-uart.c2
9 files changed, 32 insertions, 30 deletions
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index bfe68ec4e1a6..d8c1af025931 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -53,7 +53,7 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
53 53
54 gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); 54 gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
55 ct = gc->chip_types; 55 ct = gc->chip_types;
56 ct->chip.irq_ack = irq_gc_ack; 56 ct->chip.irq_ack = irq_gc_ack_set_bit;
57 ct->chip.irq_mask = irq_gc_mask_clr_bit; 57 ct->chip.irq_mask = irq_gc_mask_clr_bit;
58 ct->chip.irq_unmask = irq_gc_mask_set_bit; 58 ct->chip.irq_unmask = irq_gc_mask_set_bit;
59 59
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 72b4e7631583..ab9f999106c7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); 79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
80static APBC_CLK(keypad, PXA168_KPC, 0, 32000); 80static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
81 81
82static APMU_CLK(nand, NAND, 0x01db, 208000000); 82static APMU_CLK(nand, NAND, 0x19b, 156000000);
83static APMU_CLK(lcd, LCD, 0x7f, 312000000); 83static APMU_CLK(lcd, LCD, 0x7f, 312000000);
84 84
85/* device and clock bindings */ 85/* device and clock bindings */
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 8f92ccd26edf..1464607aa60d 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
110static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); 110static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
111static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); 111static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
112 112
113static APMU_CLK(nand, NAND, 0x01db, 208000000); 113static APMU_CLK(nand, NAND, 0x19b, 156000000);
114static APMU_CLK(u2o, USB, 0x1b, 480000000); 114static APMU_CLK(u2o, USB, 0x1b, 480000000);
115 115
116/* device and clock bindings */ 116/* device and clock bindings */
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 87ae3129f4f7..b27544bcafcb 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -347,9 +347,9 @@ static int pxa2xx_mfp_suspend(void)
347 if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && 347 if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
348 (GPDR(i) & GPIO_bit(i))) { 348 (GPDR(i) & GPIO_bit(i))) {
349 if (GPLR(i) & GPIO_bit(i)) 349 if (GPLR(i) & GPIO_bit(i))
350 PGSR(i) |= GPIO_bit(i); 350 PGSR(gpio_to_bank(i)) |= GPIO_bit(i);
351 else 351 else
352 PGSR(i) &= ~GPIO_bit(i); 352 PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
353 } 353 }
354 } 354 }
355 355
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d130f77b6d11..2f37d43f51b6 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -573,10 +573,10 @@ static struct pxafb_mode_info sharp_lq043t3dx02_mode = {
573 .xres = 480, 573 .xres = 480,
574 .yres = 272, 574 .yres = 272,
575 .bpp = 16, 575 .bpp = 16,
576 .hsync_len = 4, 576 .hsync_len = 41,
577 .left_margin = 2, 577 .left_margin = 2,
578 .right_margin = 1, 578 .right_margin = 1,
579 .vsync_len = 1, 579 .vsync_len = 10,
580 .upper_margin = 3, 580 .upper_margin = 3,
581 .lower_margin = 1, 581 .lower_margin = 1,
582 .sync = 0, 582 .sync = 0,
@@ -596,29 +596,31 @@ static void __init raumfeld_lcd_init(void)
596{ 596{
597 int ret; 597 int ret;
598 598
599 pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
600
601 /* Earlier devices had the backlight regulator controlled
602 * via PWM, later versions use another controller for that */
603 if ((system_rev & 0xff) < 2) {
604 mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
605 pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
606 platform_device_register(&raumfeld_pwm_backlight_device);
607 } else
608 platform_device_register(&raumfeld_lt3593_device);
609
610 ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable"); 599 ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable");
611 if (ret < 0) 600 if (ret < 0)
612 pr_warning("Unable to request GPIO_TFT_VA_EN\n"); 601 pr_warning("Unable to request GPIO_TFT_VA_EN\n");
613 else 602 else
614 gpio_direction_output(GPIO_TFT_VA_EN, 1); 603 gpio_direction_output(GPIO_TFT_VA_EN, 1);
615 604
605 msleep(100);
606
616 ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable"); 607 ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable");
617 if (ret < 0) 608 if (ret < 0)
618 pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); 609 pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n");
619 else 610 else
620 gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); 611 gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
621 612
613 /* Hardware revision 2 has the backlight regulator controlled
614 * by an LT3593, earlier and later devices use PWM for that. */
615 if ((system_rev & 0xff) == 2) {
616 platform_device_register(&raumfeld_lt3593_device);
617 } else {
618 mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
619 pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
620 platform_device_register(&raumfeld_pwm_backlight_device);
621 }
622
623 pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
622 platform_device_register(&pxa3xx_device_gcu); 624 platform_device_register(&pxa3xx_device_gcu);
623} 625}
624 626
@@ -657,10 +659,10 @@ static struct lis3lv02d_platform_data lis3_pdata = {
657 659
658#define SPI_AK4104 \ 660#define SPI_AK4104 \
659{ \ 661{ \
660 .modalias = "ak4104", \ 662 .modalias = "ak4104-codec", \
661 .max_speed_hz = 10000, \ 663 .max_speed_hz = 10000, \
662 .bus_num = 0, \ 664 .bus_num = 0, \
663 .chip_select = 0, \ 665 .chip_select = 0, \
664 .controller_data = (void *) GPIO_SPDIF_CS, \ 666 .controller_data = (void *) GPIO_SPDIF_CS, \
665} 667}
666 668
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5b4fffab1eb4..41ab97ebe4cf 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -432,7 +432,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
432 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; 432 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
433 ct->regs.ack = GPIO_EDGE_CAUSE_OFF; 433 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
434 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 434 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
435 ct->chip.irq_ack = irq_gc_ack; 435 ct->chip.irq_ack = irq_gc_ack_clr_bit;
436 ct->chip.irq_mask = irq_gc_mask_clr_bit; 436 ct->chip.irq_mask = irq_gc_mask_clr_bit;
437 ct->chip.irq_unmask = irq_gc_mask_set_bit; 437 ct->chip.irq_unmask = irq_gc_mask_set_bit;
438 ct->chip.irq_set_type = gpio_irq_set_type; 438 ct->chip.irq_set_type = gpio_irq_set_type;
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index 48ebb9479b61..a11dc3670505 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -50,7 +50,7 @@ static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
50 return container_of(c, struct pxa_gpio_chip, chip)->regbase; 50 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
51} 51}
52 52
53static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) 53static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
54{ 54{
55 return &pxa_gpio_chips[gpio_to_bank(gpio)]; 55 return &pxa_gpio_chips[gpio_to_bank(gpio)];
56} 56}
@@ -161,7 +161,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
161 int gpio = irq_to_gpio(d->irq); 161 int gpio = irq_to_gpio(d->irq);
162 unsigned long gpdr, mask = GPIO_bit(gpio); 162 unsigned long gpdr, mask = GPIO_bit(gpio);
163 163
164 c = gpio_to_chip(gpio); 164 c = gpio_to_pxachip(gpio);
165 165
166 if (type == IRQ_TYPE_PROBE) { 166 if (type == IRQ_TYPE_PROBE) {
167 /* Don't mess with enabled GPIOs using preconfigured edges or 167 /* Don't mess with enabled GPIOs using preconfigured edges or
@@ -230,7 +230,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
230static void pxa_ack_muxed_gpio(struct irq_data *d) 230static void pxa_ack_muxed_gpio(struct irq_data *d)
231{ 231{
232 int gpio = irq_to_gpio(d->irq); 232 int gpio = irq_to_gpio(d->irq);
233 struct pxa_gpio_chip *c = gpio_to_chip(gpio); 233 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
234 234
235 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); 235 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
236} 236}
@@ -238,7 +238,7 @@ static void pxa_ack_muxed_gpio(struct irq_data *d)
238static void pxa_mask_muxed_gpio(struct irq_data *d) 238static void pxa_mask_muxed_gpio(struct irq_data *d)
239{ 239{
240 int gpio = irq_to_gpio(d->irq); 240 int gpio = irq_to_gpio(d->irq);
241 struct pxa_gpio_chip *c = gpio_to_chip(gpio); 241 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
242 uint32_t grer, gfer; 242 uint32_t grer, gfer;
243 243
244 c->irq_mask &= ~GPIO_bit(gpio); 244 c->irq_mask &= ~GPIO_bit(gpio);
@@ -252,7 +252,7 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)
252static void pxa_unmask_muxed_gpio(struct irq_data *d) 252static void pxa_unmask_muxed_gpio(struct irq_data *d)
253{ 253{
254 int gpio = irq_to_gpio(d->irq); 254 int gpio = irq_to_gpio(d->irq);
255 struct pxa_gpio_chip *c = gpio_to_chip(gpio); 255 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
256 256
257 c->irq_mask |= GPIO_bit(gpio); 257 c->irq_mask |= GPIO_bit(gpio);
258 update_edge_detect(c); 258 update_edge_detect(c);
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 135abda31c9a..327ab9f662e8 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -152,7 +152,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
152 if (!gc) 152 if (!gc)
153 return -ENOMEM; 153 return -ENOMEM;
154 ct = gc->chip_types; 154 ct = gc->chip_types;
155 ct->chip.irq_ack = irq_gc_ack; 155 ct->chip.irq_ack = irq_gc_ack_set_bit;
156 ct->chip.irq_mask = irq_gc_mask_set_bit; 156 ct->chip.irq_mask = irq_gc_mask_set_bit;
157 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 157 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
158 ct->chip.irq_set_type = s5p_gpioint_set_type, 158 ct->chip.irq_set_type = s5p_gpioint_set_type,
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 32582c0958e3..0e46588d847b 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -55,7 +55,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
55 gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, 55 gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
56 handle_level_irq); 56 handle_level_irq);
57 ct = gc->chip_types; 57 ct = gc->chip_types;
58 ct->chip.irq_ack = irq_gc_ack; 58 ct->chip.irq_ack = irq_gc_ack_set_bit;
59 ct->chip.irq_mask = irq_gc_mask_set_bit; 59 ct->chip.irq_mask = irq_gc_mask_set_bit;
60 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 60 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
61 ct->regs.ack = S3C64XX_UINTP; 61 ct->regs.ack = S3C64XX_UINTP;