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authorKukjin Kim <kgene.kim@samsung.com>2011-03-11 20:20:07 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-03-11 20:20:07 -0500
commitbe7004f73d0b42cca29cf9f1cc86f32038fd140c (patch)
tree906bfde445dd4d94e1487888440dfc31391dae30 /arch
parent604eefeb2308cda72325fd8754aecb55075ae866 (diff)
parent30fe76437bc2463b25e9a64ff1b28f293e3f3413 (diff)
Merge branch 'next-exynos4-pm' into for-next
Conflicts: arch/arm/mach-exynos4/include/mach/regs-pmu.h
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos4/Makefile1
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h49
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h22
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h157
-rw-r--r--arch/arm/mach-exynos4/pm.c420
-rw-r--r--arch/arm/mach-exynos4/sleep.S76
-rw-r--r--arch/arm/mach-exynos4/time.c16
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h1
8 files changed, 724 insertions, 18 deletions
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 69a4a28dc95e..9473adbb6c19 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -14,6 +14,7 @@ obj- :=
14 14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o 16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_PM) += pm.o sleep.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o 18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
18 19
19obj-$(CONFIG_SMP) += platsmp.o headsmp.o 20obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
new file mode 100644
index 000000000000..f26e46bc06ca
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -0,0 +1,49 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17#include <mach/regs-pmu.h>
18
19static inline void s3c_pm_debug_init_uart(void)
20{
21 /* nothing here yet */
22}
23
24static inline void s3c_pm_arch_prepare_irqs(void)
25{
26 unsigned int tmp;
27 tmp = __raw_readl(S5P_WAKEUP_MASK);
28 tmp &= ~(1 << 31);
29 __raw_writel(tmp, S5P_WAKEUP_MASK);
30
31 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
32 __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
33}
34
35static inline void s3c_pm_arch_stop_clocks(void)
36{
37 /* nothing here yet */
38}
39
40static inline void s3c_pm_arch_show_resume_irqs(void)
41{
42 /* nothing here yet */
43}
44
45static inline void s3c_pm_arch_update_uart(void __iomem *regs,
46 struct pm_uart_save *save)
47{
48 /* nothing here yet */
49}
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 38dee94fc7ae..c91f93054589 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -17,13 +17,13 @@
17 17
18#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) 18#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
19 19
20#define S5P_INFORM0 S5P_CLKREG(0x800)
21
22#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) 20#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
23#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) 21#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
22#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
24 23
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) 24#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
27 27
28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
@@ -33,18 +33,24 @@
33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
36#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
36#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 37#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
37#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 38#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
38#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 39#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
40#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
39#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) 41#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
40#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 42#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
41#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) 43#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
42 44
43#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 45#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
44#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) 46#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
47#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
48#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
49#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
45#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) 50#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
46#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) 51#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
47#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) 52#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
53#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
48#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) 54#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
49#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) 55#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
50#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) 56#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
@@ -58,25 +64,36 @@
58 64
59#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 65#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
60#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 66#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
67#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
61#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) 68#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
62#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) 69#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
70#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
63#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) 71#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
64#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 72#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
65#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) 73#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
66 74
67#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) 75#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
68 76
77#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
69#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) 78#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
79#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
80#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
81#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
70#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) 82#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
71#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 83#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
72#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) 84#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
73#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) 85#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
86#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
74#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 87#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
75#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) 88#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
89#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
76 90
91#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
77#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) 92#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
78#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) 93#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
94#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
79#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) 95#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
96#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
80 97
81#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 98#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
82#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) 99#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
@@ -94,6 +111,7 @@
94#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) 111#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
95 112
96#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 113#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
114#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
97 115
98/* APLL_LOCK */ 116/* APLL_LOCK */
99#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ 117#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index 985416d1085f..fa1da9451689 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -15,21 +15,146 @@
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) 18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19 19
20#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) 20#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
21#define S5P_MIPI_DPHY_ENABLE (1 << 0) 21
22#define S5P_MIPI_DPHY_SRESETN (1 << 1) 22#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
23#define S5P_MIPI_DPHY_MRESETN (1 << 2) 23
24 24#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
25#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) 25
26#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) 26#define S5P_USE_STANDBY_WFI0 (1 << 16)
27#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) 27#define S5P_USE_STANDBY_WFI1 (1 << 17)
28#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) 28#define S5P_USE_STANDBY_WFE0 (1 << 24)
29#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) 29#define S5P_USE_STANDBY_WFE1 (1 << 25)
30#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) 30#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
31#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) 31
32 32#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
33#define S5P_INT_LOCAL_PWR_EN 0x7 33#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
34#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
35
36#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
37#define S5P_MIPI_DPHY_ENABLE (1 << 0)
38#define S5P_MIPI_DPHY_SRESETN (1 << 1)
39#define S5P_MIPI_DPHY_MRESETN (1 << 2)
40
41#define S5P_INFORM0 S5P_PMUREG(0x0800)
42#define S5P_INFORM1 S5P_PMUREG(0x0804)
43#define S5P_INFORM2 S5P_PMUREG(0x0808)
44#define S5P_INFORM3 S5P_PMUREG(0x080C)
45#define S5P_INFORM4 S5P_PMUREG(0x0810)
46#define S5P_INFORM5 S5P_PMUREG(0x0814)
47#define S5P_INFORM6 S5P_PMUREG(0x0818)
48#define S5P_INFORM7 S5P_PMUREG(0x081C)
49
50#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
51#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
52#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
53#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
54#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
55#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
56#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
57#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
58#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
59#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
60#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
61#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
62#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
63#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
64#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
65#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
66#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
67#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
68#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
69#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
70#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
71#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
72#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
73#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
74#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
75#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
76#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
77#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
78#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
79#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
80#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
81#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
82#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
83#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
84#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
85#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
86#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
87#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
88#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
89#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
90#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
91#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
92#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
93#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
94#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
95#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
96#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
97#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
98#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
99#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
100#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
101#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
102#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
103#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
104#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
105#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
106#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
107#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
108#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
109#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
110#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
111#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
112#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
113#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
114#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
115#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
116#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
117#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
118#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
119#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
120#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
121
122#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
123#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
124#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
125#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
126#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
127
128#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
129#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
130#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
131#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
132#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
133#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
134#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
135#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
136#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
137#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
138#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
139
140#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
141#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
142#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
143#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
144#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
145#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
146#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
147
148#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
149#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
150#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
151#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
152#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
153#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
154#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
155
156#define S5P_INT_LOCAL_PWR_EN 0x7
157
158#define S5P_CHECK_SLEEP 0x00000BAD
34 159
35#endif /* __ASM_ARCH_REGS_PMU_H */ 160#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
new file mode 100644
index 000000000000..10d917d9e3ad
--- /dev/null
+++ b/arch/arm/mach-exynos4/pm.c
@@ -0,0 +1,420 @@
1/* linux/arch/arm/mach-exynos4/pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4210 - Power Management support
7 *
8 * Based on arch/arm/mach-s3c2410/pm.c
9 * Copyright (c) 2006 Simtec Electronics
10 * Ben Dooks <ben@simtec.co.uk>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#include <linux/init.h>
18#include <linux/suspend.h>
19#include <linux/io.h>
20
21#include <asm/cacheflush.h>
22#include <asm/hardware/cache-l2x0.h>
23
24#include <plat/cpu.h>
25#include <plat/pm.h>
26
27#include <mach/regs-irq.h>
28#include <mach/regs-gpio.h>
29#include <mach/regs-clock.h>
30#include <mach/regs-pmu.h>
31#include <mach/pm-core.h>
32
33static struct sleep_save exynos4_sleep[] = {
34 { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
35 { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
36 { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
37 { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
38 { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
39 { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
40 { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
41 { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
42 { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
43 { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
44 { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
45 { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
46 { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
47 { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
48 { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
49 { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
50 { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
51 { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
52 { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
53 { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
54 { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
55 { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
56 { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
57 { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
58 { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
59 { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
60 { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
61 { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
62 { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
63 { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
64 { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
65 { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
66 { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
67 { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
68 { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
69 { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
70 { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
71 { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
72 { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
73 { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
74 { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
75 { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
76 { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
77 { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
78 { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
79 { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
80 { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
81 { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
82 { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
83 { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
84 { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
85 { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
86 { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
87 { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
88 { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
89 { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
90 { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
91 { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
92 { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
93 { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
94 { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
95 { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
96 { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
97 { .reg = S5P_TV_LOWPWR , .val = 0x0, },
98 { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
99 { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
100 { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
101 { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
102 { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
103 { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
104 { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
105};
106
107static struct sleep_save exynos4_set_clksrc[] = {
108 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
109 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
110 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
111 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
112 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
113 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
114 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
115 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
116 { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
117 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
118};
119
120static struct sleep_save exynos4_core_save[] = {
121 /* CMU side */
122 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
123 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
124 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
125 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
126 SAVE_ITEM(S5P_EPLL_CON0),
127 SAVE_ITEM(S5P_EPLL_CON1),
128 SAVE_ITEM(S5P_VPLL_CON0),
129 SAVE_ITEM(S5P_VPLL_CON1),
130 SAVE_ITEM(S5P_CLKSRC_TOP0),
131 SAVE_ITEM(S5P_CLKSRC_TOP1),
132 SAVE_ITEM(S5P_CLKSRC_CAM),
133 SAVE_ITEM(S5P_CLKSRC_MFC),
134 SAVE_ITEM(S5P_CLKSRC_IMAGE),
135 SAVE_ITEM(S5P_CLKSRC_LCD0),
136 SAVE_ITEM(S5P_CLKSRC_LCD1),
137 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
138 SAVE_ITEM(S5P_CLKSRC_FSYS),
139 SAVE_ITEM(S5P_CLKSRC_PERIL0),
140 SAVE_ITEM(S5P_CLKSRC_PERIL1),
141 SAVE_ITEM(S5P_CLKDIV_CAM),
142 SAVE_ITEM(S5P_CLKDIV_TV),
143 SAVE_ITEM(S5P_CLKDIV_MFC),
144 SAVE_ITEM(S5P_CLKDIV_G3D),
145 SAVE_ITEM(S5P_CLKDIV_IMAGE),
146 SAVE_ITEM(S5P_CLKDIV_LCD0),
147 SAVE_ITEM(S5P_CLKDIV_LCD1),
148 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
149 SAVE_ITEM(S5P_CLKDIV_FSYS0),
150 SAVE_ITEM(S5P_CLKDIV_FSYS1),
151 SAVE_ITEM(S5P_CLKDIV_FSYS2),
152 SAVE_ITEM(S5P_CLKDIV_FSYS3),
153 SAVE_ITEM(S5P_CLKDIV_PERIL0),
154 SAVE_ITEM(S5P_CLKDIV_PERIL1),
155 SAVE_ITEM(S5P_CLKDIV_PERIL2),
156 SAVE_ITEM(S5P_CLKDIV_PERIL3),
157 SAVE_ITEM(S5P_CLKDIV_PERIL4),
158 SAVE_ITEM(S5P_CLKDIV_PERIL5),
159 SAVE_ITEM(S5P_CLKDIV_TOP),
160 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
161 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
162 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
163 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
164 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
165 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
166 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
167 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
168 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
169 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
170 SAVE_ITEM(S5P_CLKGATE_IP_TV),
171 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
172 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
173 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
174 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
175 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
176 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
177 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
178 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
179 SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
180 SAVE_ITEM(S5P_CLKGATE_BLOCK),
181 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
182 SAVE_ITEM(S5P_CLKSRC_DMC),
183 SAVE_ITEM(S5P_CLKDIV_DMC0),
184 SAVE_ITEM(S5P_CLKDIV_DMC1),
185 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
186 SAVE_ITEM(S5P_CLKSRC_CPU),
187 SAVE_ITEM(S5P_CLKDIV_CPU),
188 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
189 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
190 /* GIC side */
191 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
192 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
193 SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
194 SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
195 SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
196 SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
197 SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
198 SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
199 SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
200 SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
201 SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
202 SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
203 SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
204 SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
205 SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
206 SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
207 SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
208 SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
209 SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
210 SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
211 SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
212 SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
213 SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
214 SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
215 SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
216 SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
217 SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
218 SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
219 SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
220 SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
221 SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
222 SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
223 SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
224 SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
225 SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
226 SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
227 SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
228 SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
229
230 SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
231 SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
232 SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
233 SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
234 SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
235 SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
236 SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
237 SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
238 SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
239 SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
240 SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
241 SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
242 SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
243 SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
244 SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
245 SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
246 SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
247 SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
248 SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
249 SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
250 SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
251 SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
252 SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
253 SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
254
255 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
256 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
257 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
258 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
259 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
260 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
261
262 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
263 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
264 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
265 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
266 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
267 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
268 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
269 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
270 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
271 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
272};
273
274static struct sleep_save exynos4_l2cc_save[] = {
275 SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
276 SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
277 SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
278 SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
279 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
280};
281
282void exynos4_cpu_suspend(void)
283{
284 unsigned long tmp;
285 unsigned long mask = 0xFFFFFFFF;
286
287 /* Setting Central Sequence Register for power down mode */
288
289 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
290 tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
291 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
292
293 /* Setting Central Sequence option Register */
294
295 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
296 tmp &= ~(S5P_USE_MASK);
297 tmp |= S5P_USE_STANDBY_WFI0;
298 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
299
300 /* Clear all interrupt pending to avoid early wakeup */
301
302 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
303 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
304 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
305
306 /* Disable all interrupt */
307
308 __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
309 __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
310 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
311 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
312
313 outer_flush_all();
314
315 /* issue the standby signal into the pm unit. */
316 cpu_do_idle();
317
318 /* we should never get past here */
319 panic("sleep resumed to originator?");
320}
321
322static void exynos4_pm_prepare(void)
323{
324 u32 tmp;
325
326 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
327 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
328
329 tmp = __raw_readl(S5P_INFORM1);
330
331 /* Set value of power down register for sleep mode */
332
333 s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
334 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
335
336 /* ensure at least INFORM0 has the resume address */
337
338 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
339
340 /* Before enter central sequence mode, clock src register have to set */
341
342 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
343
344}
345
346static int exynos4_pm_add(struct sys_device *sysdev)
347{
348 pm_cpu_prep = exynos4_pm_prepare;
349 pm_cpu_sleep = exynos4_cpu_suspend;
350
351 return 0;
352}
353
354/* This function copy from linux/arch/arm/kernel/smp_scu.c */
355
356void exynos4_scu_enable(void __iomem *scu_base)
357{
358 u32 scu_ctrl;
359
360 scu_ctrl = __raw_readl(scu_base);
361 /* already enabled? */
362 if (scu_ctrl & 1)
363 return;
364
365 scu_ctrl |= 1;
366 __raw_writel(scu_ctrl, scu_base);
367
368 /*
369 * Ensure that the data accessed by CPU0 before the SCU was
370 * initialised is visible to the other CPUs.
371 */
372 flush_cache_all();
373}
374
375static int exynos4_pm_resume(struct sys_device *dev)
376{
377 /* For release retention */
378
379 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
380 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
381 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
382 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
383 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
384 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
385 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
386
387 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
388
389 exynos4_scu_enable(S5P_VA_SCU);
390
391#ifdef CONFIG_CACHE_L2X0
392 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
393 outer_inv_all();
394 /* enable L2X0*/
395 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
396#endif
397
398 return 0;
399}
400
401static struct sysdev_driver exynos4_pm_driver = {
402 .add = exynos4_pm_add,
403 .resume = exynos4_pm_resume,
404};
405
406static __init int exynos4_pm_drvinit(void)
407{
408 unsigned int tmp;
409
410 s3c_pm_init();
411
412 /* All wakeup disable */
413
414 tmp = __raw_readl(S5P_WAKEUP_MASK);
415 tmp |= ((0xFF << 8) | (0x1F << 1));
416 __raw_writel(tmp, S5P_WAKEUP_MASK);
417
418 return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
419}
420arch_initcall(exynos4_pm_drvinit);
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
new file mode 100644
index 000000000000..6b62425417a6
--- /dev/null
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -0,0 +1,76 @@
1/* linux/arch/arm/mach-exynos4/sleep.S
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4210 power Manager (Suspend-To-RAM) support
7 * Based on S3C2410 sleep code by:
8 * Ben Dooks, (c) 2004 Simtec Electronics
9 *
10 * Based on PXA/SA1100 sleep code by:
11 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
12 * Cliff Brake, (c) 2001
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <asm/memory.h>
32
33 .text
34
35 /*
36 * s3c_cpu_save
37 *
38 * entry:
39 * r1 = v:p offset
40 */
41
42ENTRY(s3c_cpu_save)
43
44 stmfd sp!, { r3 - r12, lr }
45 ldr r3, =resume_with_mmu
46 bl cpu_suspend
47
48 ldr r0, =pm_cpu_sleep
49 ldr r0, [ r0 ]
50 mov pc, r0
51
52resume_with_mmu:
53 ldmfd sp!, { r3 - r12, pc }
54
55 .ltorg
56
57 /*
58 * sleep magic, to allow the bootloader to check for an valid
59 * image to resume to. Must be the first word before the
60 * s3c_cpu_resume entry.
61 */
62
63 .word 0x2bedf00d
64
65 /*
66 * s3c_cpu_resume
67 *
68 * resume code entry for bootloader to call
69 *
70 * we must put this code here in the data segment as we have no
71 * other way of restoring the stack pointer after sleep, and we
72 * must not write to the code segment (code is read-only)
73 */
74
75ENTRY(s3c_cpu_resume)
76 b cpu_resume
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
index e30ac7043095..86b9fa0d3639 100644
--- a/arch/arm/mach-exynos4/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -206,12 +206,28 @@ static cycle_t exynos4_pwm4_read(struct clocksource *cs)
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40)); 206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207} 207}
208 208
209static void exynos4_pwm4_resume(struct clocksource *cs)
210{
211 unsigned long pclk;
212
213 pclk = clk_get_rate(timerclk);
214
215 clk_set_rate(tdiv4, pclk / 2);
216 clk_set_parent(tin4, tdiv4);
217
218 exynos4_pwm_init(4, ~0);
219 exynos4_pwm_start(4, 1);
220}
221
209struct clocksource pwm_clocksource = { 222struct clocksource pwm_clocksource = {
210 .name = "pwm_timer4", 223 .name = "pwm_timer4",
211 .rating = 250, 224 .rating = 250,
212 .read = exynos4_pwm4_read, 225 .read = exynos4_pwm4_read,
213 .mask = CLOCKSOURCE_MASK(32), 226 .mask = CLOCKSOURCE_MASK(32),
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS , 227 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
228#ifdef CONFIG_PM
229 .resume = exynos4_pwm4_resume,
230#endif
215}; 231};
216 232
217static void __init exynos4_clocksource_init(void) 233static void __init exynos4_clocksource_init(void)
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 9addb3dfb4bc..cedfff51c82b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -82,6 +82,7 @@ extern struct sysdev_class s3c64xx_sysclass;
82extern struct sysdev_class s5p64x0_sysclass; 82extern struct sysdev_class s5p64x0_sysclass;
83extern struct sysdev_class s5p6442_sysclass; 83extern struct sysdev_class s5p6442_sysclass;
84extern struct sysdev_class s5pv210_sysclass; 84extern struct sysdev_class s5pv210_sysclass;
85extern struct sysdev_class exynos4_sysclass;
85 86
86extern void (*s5pc1xx_idle)(void); 87extern void (*s5pc1xx_idle)(void);
87 88
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 15:57:10 -0500