ARM: 6184/2: ux500: use neutral PRCMU base

The MTU wallclock timing fix-up patch was hardwired to the DB8500
causing a regression. This makes it work on the DB5500 as well.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 2 insertions, 1 deletions

diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index fe84b9021c7a..0a1318fc8e2b 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -131,7 +131,7 @@ EXPORT_SYMBOL(clk_disable);
  */
 static unsigned long clk_mtu_get_rate(struct clk *clk)
 {
-        void __iomem *addr = __io_address(U8500_PRCMU_BASE)
+        void __iomem *addr = __io_address(UX500_PRCMU_BASE)
                 + PRCM_TCR;
         u32 tcr = readl(addr);
         int mtu = (int) clk->data;
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 6a3ac4539f16..e9278f6d67aa 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -21,6 +21,7 @@ static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
 };
 
 static struct platform_device *u5500_platform_devs[] __initdata = {