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authorMagnus Damm <damm@opensource.se>2010-03-10 00:17:24 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-03-14 23:06:46 -0400
commitc57a31abf0b469b9cab6810f4e1895bb7ef1c482 (patch)
treed1cfaff2234ec0d69ea97678536f4eb92e0b9efa /arch
parentc148abfc2d807b2734e7ecd0e00c71ef7d4b7f42 (diff)
ARM: mach-shmobile: sh7372 SDHI vector merge
Merge the SDHI vectors for sh7372 using the recently merged INTC force_enable/disable feature. With this in place SDHI hotplug is supported using the drivers sh_mobile_sdhi and tmio_mmc. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c46
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index c57a923f97a6..3ce9d9bd5899 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -27,6 +27,8 @@
27 27
28enum { 28enum {
29 UNUSED_INTCA = 0, 29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
30 32
31 /* interrupt sources INTCA */ 33 /* interrupt sources INTCA */
32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -47,14 +49,14 @@ enum {
47 MSIOF2, MSIOF1, 49 MSIOF2, MSIOF1,
48 SCIFA4, SCIFA5, SCIFB, 50 SCIFA4, SCIFA5, SCIFB,
49 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 51 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
50 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, 52 SDHI0,
51 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, 53 SDHI1,
52 IRREM, 54 IRREM,
53 IRDA, 55 IRDA,
54 TPU0, 56 TPU0,
55 TTI20, 57 TTI20,
56 DDM, 58 DDM,
57 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, 59 SDHI2,
58 RWDT0, 60 RWDT0,
59 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, 61 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
60 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, 62 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
@@ -82,7 +84,7 @@ enum {
82 84
83 /* interrupt groups INTCA */ 85 /* interrupt groups INTCA */
84 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, 86 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
85 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 87 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
86}; 88};
87 89
88static struct intc_vect intca_vectors[] __initdata = { 90static struct intc_vect intca_vectors[] __initdata = {
@@ -123,17 +125,17 @@ static struct intc_vect intca_vectors[] __initdata = {
123 INTC_VECT(SCIFB, 0x0d60), 125 INTC_VECT(SCIFB, 0x0d60),
124 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 126 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
125 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 127 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
126 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), 128 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
127 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), 129 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
128 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), 130 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
129 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), 131 INTC_VECT(SDHI1, 0x0ec0),
130 INTC_VECT(IRREM, 0x0f60), 132 INTC_VECT(IRREM, 0x0f60),
131 INTC_VECT(IRDA, 0x0480), 133 INTC_VECT(IRDA, 0x0480),
132 INTC_VECT(TPU0, 0x04a0), 134 INTC_VECT(TPU0, 0x04a0),
133 INTC_VECT(TTI20, 0x1100), 135 INTC_VECT(TTI20, 0x1100),
134 INTC_VECT(DDM, 0x1140), 136 INTC_VECT(DDM, 0x1140),
135 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), 137 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
136 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), 138 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
137 INTC_VECT(RWDT0, 0x1280), 139 INTC_VECT(RWDT0, 0x1280),
138 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), 140 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
139 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), 141 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
@@ -193,12 +195,6 @@ static struct intc_group intca_groups[] __initdata = {
193 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 195 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
194 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 196 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
195 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 197 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
196 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
197 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
198 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
199 SDHI1_SDHI1I2),
200 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
201 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
202 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), 198 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
203}; 199};
204 200
@@ -234,10 +230,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
234 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 230 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
235 0, 0, MSIOF2, 0 } }, 231 0, 0, MSIOF2, 0 } },
236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 232 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
237 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, 233 { DISABLED, DISABLED, ENABLED, ENABLED,
238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 234 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 235 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
240 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, 236 { 0, DISABLED, ENABLED, ENABLED,
241 TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, 237 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 238 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 239 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -252,7 +248,7 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
252 { 0, 0, TPU0, 0, 248 { 0, 0, TPU0, 0,
253 0, 0, 0, 0 } }, 249 0, 0, 0, 0 } },
254 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 250 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
255 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, 251 { DISABLED, DISABLED, ENABLED, ENABLED,
256 0, CMT3, 0, RWDT0 } }, 252 0, CMT3, 0, RWDT0 } },
257 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ 253 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
258 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, 254 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
@@ -358,10 +354,14 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
358 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 354 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
359}; 355};
360 356
361static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca", 357static struct intc_desc intca_desc __initdata = {
362 intca_vectors, intca_groups, 358 .name = "sh7372-intca",
363 intca_mask_registers, intca_prio_registers, 359 .force_enable = ENABLED,
364 intca_sense_registers, intca_ack_registers); 360 .force_disable = DISABLED,
361 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
362 intca_mask_registers, intca_prio_registers,
363 intca_sense_registers, intca_ack_registers),
364};
365 365
366void __init sh7372_init_irq(void) 366void __init sh7372_init_irq(void)
367{ 367{