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authorKumar Gala <galak@kernel.crashing.org>2008-04-17 02:28:15 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-04-17 02:28:15 -0400
commit32f960e9439bbe72c45f8cd854049254122fc198 (patch)
tree7773600dbe67df8bd07b35e865a7a7c1b7a863fd /arch
parenta5dc66e2ab2e2cf641346b056a69a67cfcf9458c (diff)
[POWERPC] 85xx: Convert dts to v1 syntax
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts173
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts161
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts279
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts289
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts161
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts209
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts283
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts383
8 files changed, 973 insertions, 965 deletions
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 975248491b7b..18033ed0b535 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8540 ADS Device Tree Source 2 * MPC8540 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8540ADS"; 15 model = "MPC8540ADS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8540@0 { 33 PowerPC,8540@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8540@e0000000 { 51 soc8540@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00100000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,8540-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,24 +87,24 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 phy3: ethernet-phy@3 { 104 phy3: ethernet-phy@3 {
104 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
105 interrupts = <7 1>; 106 interrupts = <7 1>;
106 reg = <3>; 107 reg = <0x3>;
107 device_type = "ethernet-phy"; 108 device_type = "ethernet-phy";
108 }; 109 };
109 }; 110 };
@@ -113,9 +114,9 @@
113 device_type = "network"; 114 device_type = "network";
114 model = "TSEC"; 115 model = "TSEC";
115 compatible = "gianfar"; 116 compatible = "gianfar";
116 reg = <24000 1000>; 117 reg = <0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ]; 118 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <1d 2 1e 2 22 2>; 119 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>; 120 interrupt-parent = <&mpic>;
120 phy-handle = <&phy0>; 121 phy-handle = <&phy0>;
121 }; 122 };
@@ -125,9 +126,9 @@
125 device_type = "network"; 126 device_type = "network";
126 model = "TSEC"; 127 model = "TSEC";
127 compatible = "gianfar"; 128 compatible = "gianfar";
128 reg = <25000 1000>; 129 reg = <0x25000 0x1000>;
129 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
130 interrupts = <23 2 24 2 28 2>; 131 interrupts = <35 2 36 2 40 2>;
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 phy-handle = <&phy1>; 133 phy-handle = <&phy1>;
133 }; 134 };
@@ -137,9 +138,9 @@
137 device_type = "network"; 138 device_type = "network";
138 model = "FEC"; 139 model = "FEC";
139 compatible = "gianfar"; 140 compatible = "gianfar";
140 reg = <26000 1000>; 141 reg = <0x26000 0x1000>;
141 local-mac-address = [ 00 00 00 00 00 00 ]; 142 local-mac-address = [ 00 00 00 00 00 00 ];
142 interrupts = <29 2>; 143 interrupts = <41 2>;
143 interrupt-parent = <&mpic>; 144 interrupt-parent = <&mpic>;
144 phy-handle = <&phy3>; 145 phy-handle = <&phy3>;
145 }; 146 };
@@ -148,9 +149,9 @@
148 cell-index = <0>; 149 cell-index = <0>;
149 device_type = "serial"; 150 device_type = "serial";
150 compatible = "ns16550"; 151 compatible = "ns16550";
151 reg = <4500 100>; // reg base, size 152 reg = <0x4500 0x100>; // reg base, size
152 clock-frequency = <0>; // should we fill in in uboot? 153 clock-frequency = <0>; // should we fill in in uboot?
153 interrupts = <2a 2>; 154 interrupts = <42 2>;
154 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
155 }; 156 };
156 157
@@ -158,9 +159,9 @@
158 cell-index = <1>; 159 cell-index = <1>;
159 device_type = "serial"; 160 device_type = "serial";
160 compatible = "ns16550"; 161 compatible = "ns16550";
161 reg = <4600 100>; // reg base, size 162 reg = <0x4600 0x100>; // reg base, size
162 clock-frequency = <0>; // should we fill in in uboot? 163 clock-frequency = <0>; // should we fill in in uboot?
163 interrupts = <2a 2>; 164 interrupts = <42 2>;
164 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>;
165 }; 166 };
166 mpic: pic@40000 { 167 mpic: pic@40000 {
@@ -168,7 +169,7 @@
168 interrupt-controller; 169 interrupt-controller;
169 #address-cells = <0>; 170 #address-cells = <0>;
170 #interrupt-cells = <2>; 171 #interrupt-cells = <2>;
171 reg = <40000 40000>; 172 reg = <0x40000 0x40000>;
172 compatible = "chrp,open-pic"; 173 compatible = "chrp,open-pic";
173 device_type = "open-pic"; 174 device_type = "open-pic";
174 big-endian; 175 big-endian;
@@ -177,90 +178,90 @@
177 178
178 pci0: pci@e0008000 { 179 pci0: pci@e0008000 {
179 cell-index = <0>; 180 cell-index = <0>;
180 interrupt-map-mask = <f800 0 0 7>; 181 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
181 interrupt-map = < 182 interrupt-map = <
182 183
183 /* IDSEL 0x02 */ 184 /* IDSEL 0x02 */
184 1000 0 0 1 &mpic 1 1 185 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
185 1000 0 0 2 &mpic 2 1 186 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
186 1000 0 0 3 &mpic 3 1 187 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
187 1000 0 0 4 &mpic 4 1 188 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
188 189
189 /* IDSEL 0x03 */ 190 /* IDSEL 0x03 */
190 1800 0 0 1 &mpic 4 1 191 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
191 1800 0 0 2 &mpic 1 1 192 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
192 1800 0 0 3 &mpic 2 1 193 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
193 1800 0 0 4 &mpic 3 1 194 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
194 195
195 /* IDSEL 0x04 */ 196 /* IDSEL 0x04 */
196 2000 0 0 1 &mpic 3 1 197 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
197 2000 0 0 2 &mpic 4 1 198 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
198 2000 0 0 3 &mpic 1 1 199 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
199 2000 0 0 4 &mpic 2 1 200 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
200 201
201 /* IDSEL 0x05 */ 202 /* IDSEL 0x05 */
202 2800 0 0 1 &mpic 2 1 203 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
203 2800 0 0 2 &mpic 3 1 204 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
204 2800 0 0 3 &mpic 4 1 205 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
205 2800 0 0 4 &mpic 1 1 206 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
206 207
207 /* IDSEL 0x0c */ 208 /* IDSEL 0x0c */
208 6000 0 0 1 &mpic 1 1 209 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
209 6000 0 0 2 &mpic 2 1 210 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
210 6000 0 0 3 &mpic 3 1 211 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
211 6000 0 0 4 &mpic 4 1 212 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
212 213
213 /* IDSEL 0x0d */ 214 /* IDSEL 0x0d */
214 6800 0 0 1 &mpic 4 1 215 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
215 6800 0 0 2 &mpic 1 1 216 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
216 6800 0 0 3 &mpic 2 1 217 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
217 6800 0 0 4 &mpic 3 1 218 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
218 219
219 /* IDSEL 0x0e */ 220 /* IDSEL 0x0e */
220 7000 0 0 1 &mpic 3 1 221 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
221 7000 0 0 2 &mpic 4 1 222 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
222 7000 0 0 3 &mpic 1 1 223 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
223 7000 0 0 4 &mpic 2 1 224 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
224 225
225 /* IDSEL 0x0f */ 226 /* IDSEL 0x0f */
226 7800 0 0 1 &mpic 2 1 227 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
227 7800 0 0 2 &mpic 3 1 228 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
228 7800 0 0 3 &mpic 4 1 229 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
229 7800 0 0 4 &mpic 1 1 230 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
230 231
231 /* IDSEL 0x12 */ 232 /* IDSEL 0x12 */
232 9000 0 0 1 &mpic 1 1 233 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
233 9000 0 0 2 &mpic 2 1 234 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
234 9000 0 0 3 &mpic 3 1 235 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
235 9000 0 0 4 &mpic 4 1 236 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
236 237
237 /* IDSEL 0x13 */ 238 /* IDSEL 0x13 */
238 9800 0 0 1 &mpic 4 1 239 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
239 9800 0 0 2 &mpic 1 1 240 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
240 9800 0 0 3 &mpic 2 1 241 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
241 9800 0 0 4 &mpic 3 1 242 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
242 243
243 /* IDSEL 0x14 */ 244 /* IDSEL 0x14 */
244 a000 0 0 1 &mpic 3 1 245 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
245 a000 0 0 2 &mpic 4 1 246 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
246 a000 0 0 3 &mpic 1 1 247 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
247 a000 0 0 4 &mpic 2 1 248 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
248 249
249 /* IDSEL 0x15 */ 250 /* IDSEL 0x15 */
250 a800 0 0 1 &mpic 2 1 251 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
251 a800 0 0 2 &mpic 3 1 252 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
252 a800 0 0 3 &mpic 4 1 253 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
253 a800 0 0 4 &mpic 1 1>; 254 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
254 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
255 interrupts = <18 2>; 256 interrupts = <24 2>;
256 bus-range = <0 0>; 257 bus-range = <0 0>;
257 ranges = <02000000 0 80000000 80000000 0 20000000 258 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
258 01000000 0 00000000 e2000000 0 00100000>; 259 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
259 clock-frequency = <3f940aa>; 260 clock-frequency = <66666666>;
260 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
261 #size-cells = <2>; 262 #size-cells = <2>;
262 #address-cells = <3>; 263 #address-cells = <3>;
263 reg = <e0008000 1000>; 264 reg = <0xe0008000 0x1000>;
264 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
265 device_type = "pci"; 266 device_type = "pci";
266 }; 267 };
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fa8d9aaad157..663c7c50ca45 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8541 CDS Device Tree Source 2 * MPC8541 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8541CDS"; 15 model = "MPC8541CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8541@0 { 33 PowerPC,8541@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8541@e0000000 { 51 soc8541@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8541-memory-controller"; 60 compatible = "fsl,8541-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8541-l2-cache-controller"; 67 compatible = "fsl,8541-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8541-brg", 180 compatible = "fsl,mpc8541-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 131ffaae2b5d..e238ebb4596e 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8544 DS Device Tree Source 2 * MPC8544 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "MPC8544DS"; 14 model = "MPC8544DS";
14 compatible = "MPC8544DS", "MPC85xxDS"; 15 compatible = "MPC8544DS", "MPC85xxDS";
@@ -27,17 +28,17 @@
27 }; 28 };
28 29
29 cpus { 30 cpus {
30 #cpus = <1>; 31 #cpus = <0x1>;
31 #address-cells = <1>; 32 #address-cells = <1>;
32 #size-cells = <0>; 33 #size-cells = <0>;
33 34
34 PowerPC,8544@0 { 35 PowerPC,8544@0 {
35 device_type = "cpu"; 36 device_type = "cpu";
36 reg = <0>; 37 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 42 timebase-frequency = <0>;
42 bus-frequency = <0>; 43 bus-frequency = <0>;
43 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -46,7 +47,7 @@
46 47
47 memory { 48 memory {
48 device_type = "memory"; 49 device_type = "memory";
49 reg = <00000000 00000000>; // Filled by U-Boot 50 reg = <0x0 0x0>; // Filled by U-Boot
50 }; 51 };
51 52
52 soc8544@e0000000 { 53 soc8544@e0000000 {
@@ -54,24 +55,24 @@
54 #size-cells = <1>; 55 #size-cells = <1>;
55 device_type = "soc"; 56 device_type = "soc";
56 57
57 ranges = <00000000 e0000000 00100000>; 58 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <e0000000 00001000>; // CCSRBAR 1M 59 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled out by uboot. 60 bus-frequency = <0>; // Filled out by uboot.
60 61
61 memory-controller@2000 { 62 memory-controller@2000 {
62 compatible = "fsl,8544-memory-controller"; 63 compatible = "fsl,8544-memory-controller";
63 reg = <2000 1000>; 64 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 65 interrupt-parent = <&mpic>;
65 interrupts = <12 2>; 66 interrupts = <18 2>;
66 }; 67 };
67 68
68 l2-cache-controller@20000 { 69 l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller"; 70 compatible = "fsl,8544-l2-cache-controller";
70 reg = <20000 1000>; 71 reg = <0x20000 0x1000>;
71 cache-line-size = <20>; // 32 bytes 72 cache-line-size = <32>; // 32 bytes
72 cache-size = <40000>; // L2, 256K 73 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>; 74 interrupt-parent = <&mpic>;
74 interrupts = <10 2>; 75 interrupts = <16 2>;
75 }; 76 };
76 77
77 i2c@3000 { 78 i2c@3000 {
@@ -79,8 +80,8 @@
79 #size-cells = <0>; 80 #size-cells = <0>;
80 cell-index = <0>; 81 cell-index = <0>;
81 compatible = "fsl-i2c"; 82 compatible = "fsl-i2c";
82 reg = <3000 100>; 83 reg = <0x3000 0x100>;
83 interrupts = <2b 2>; 84 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
85 dfsrr; 86 dfsrr;
86 }; 87 };
@@ -90,8 +91,8 @@
90 #size-cells = <0>; 91 #size-cells = <0>;
91 cell-index = <1>; 92 cell-index = <1>;
92 compatible = "fsl-i2c"; 93 compatible = "fsl-i2c";
93 reg = <3100 100>; 94 reg = <0x3100 0x100>;
94 interrupts = <2b 2>; 95 interrupts = <43 2>;
95 interrupt-parent = <&mpic>; 96 interrupt-parent = <&mpic>;
96 dfsrr; 97 dfsrr;
97 }; 98 };
@@ -100,18 +101,18 @@
100 #address-cells = <1>; 101 #address-cells = <1>;
101 #size-cells = <0>; 102 #size-cells = <0>;
102 compatible = "fsl,gianfar-mdio"; 103 compatible = "fsl,gianfar-mdio";
103 reg = <24520 20>; 104 reg = <0x24520 0x20>;
104 105
105 phy0: ethernet-phy@0 { 106 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>; 107 interrupt-parent = <&mpic>;
107 interrupts = <a 1>; 108 interrupts = <10 1>;
108 reg = <0>; 109 reg = <0x0>;
109 device_type = "ethernet-phy"; 110 device_type = "ethernet-phy";
110 }; 111 };
111 phy1: ethernet-phy@1 { 112 phy1: ethernet-phy@1 {
112 interrupt-parent = <&mpic>; 113 interrupt-parent = <&mpic>;
113 interrupts = <a 1>; 114 interrupts = <10 1>;
114 reg = <1>; 115 reg = <0x1>;
115 device_type = "ethernet-phy"; 116 device_type = "ethernet-phy";
116 }; 117 };
117 }; 118 };
@@ -120,40 +121,40 @@
120 #address-cells = <1>; 121 #address-cells = <1>;
121 #size-cells = <1>; 122 #size-cells = <1>;
122 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma"; 123 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
123 reg = <21300 4>; 124 reg = <0x21300 0x4>;
124 ranges = <0 21100 200>; 125 ranges = <0x0 0x21100 0x200>;
125 cell-index = <0>; 126 cell-index = <0>;
126 dma-channel@0 { 127 dma-channel@0 {
127 compatible = "fsl,mpc8544-dma-channel", 128 compatible = "fsl,mpc8544-dma-channel",
128 "fsl,eloplus-dma-channel"; 129 "fsl,eloplus-dma-channel";
129 reg = <0 80>; 130 reg = <0x0 0x80>;
130 cell-index = <0>; 131 cell-index = <0>;
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 interrupts = <14 2>; 133 interrupts = <20 2>;
133 }; 134 };
134 dma-channel@80 { 135 dma-channel@80 {
135 compatible = "fsl,mpc8544-dma-channel", 136 compatible = "fsl,mpc8544-dma-channel",
136 "fsl,eloplus-dma-channel"; 137 "fsl,eloplus-dma-channel";
137 reg = <80 80>; 138 reg = <0x80 0x80>;
138 cell-index = <1>; 139 cell-index = <1>;
139 interrupt-parent = <&mpic>; 140 interrupt-parent = <&mpic>;
140 interrupts = <15 2>; 141 interrupts = <21 2>;
141 }; 142 };
142 dma-channel@100 { 143 dma-channel@100 {
143 compatible = "fsl,mpc8544-dma-channel", 144 compatible = "fsl,mpc8544-dma-channel",
144 "fsl,eloplus-dma-channel"; 145 "fsl,eloplus-dma-channel";
145 reg = <100 80>; 146 reg = <0x100 0x80>;
146 cell-index = <2>; 147 cell-index = <2>;
147 interrupt-parent = <&mpic>; 148 interrupt-parent = <&mpic>;
148 interrupts = <16 2>; 149 interrupts = <22 2>;
149 }; 150 };
150 dma-channel@180 { 151 dma-channel@180 {
151 compatible = "fsl,mpc8544-dma-channel", 152 compatible = "fsl,mpc8544-dma-channel",
152 "fsl,eloplus-dma-channel"; 153 "fsl,eloplus-dma-channel";
153 reg = <180 80>; 154 reg = <0x180 0x80>;
154 cell-index = <3>; 155 cell-index = <3>;
155 interrupt-parent = <&mpic>; 156 interrupt-parent = <&mpic>;
156 interrupts = <17 2>; 157 interrupts = <23 2>;
157 }; 158 };
158 }; 159 };
159 160
@@ -162,9 +163,9 @@
162 device_type = "network"; 163 device_type = "network";
163 model = "TSEC"; 164 model = "TSEC";
164 compatible = "gianfar"; 165 compatible = "gianfar";
165 reg = <24000 1000>; 166 reg = <0x24000 0x1000>;
166 local-mac-address = [ 00 00 00 00 00 00 ]; 167 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <1d 2 1e 2 22 2>; 168 interrupts = <29 2 30 2 34 2>;
168 interrupt-parent = <&mpic>; 169 interrupt-parent = <&mpic>;
169 phy-handle = <&phy0>; 170 phy-handle = <&phy0>;
170 phy-connection-type = "rgmii-id"; 171 phy-connection-type = "rgmii-id";
@@ -175,9 +176,9 @@
175 device_type = "network"; 176 device_type = "network";
176 model = "TSEC"; 177 model = "TSEC";
177 compatible = "gianfar"; 178 compatible = "gianfar";
178 reg = <26000 1000>; 179 reg = <0x26000 0x1000>;
179 local-mac-address = [ 00 00 00 00 00 00 ]; 180 local-mac-address = [ 00 00 00 00 00 00 ];
180 interrupts = <1f 2 20 2 21 2>; 181 interrupts = <31 2 32 2 33 2>;
181 interrupt-parent = <&mpic>; 182 interrupt-parent = <&mpic>;
182 phy-handle = <&phy1>; 183 phy-handle = <&phy1>;
183 phy-connection-type = "rgmii-id"; 184 phy-connection-type = "rgmii-id";
@@ -187,9 +188,9 @@
187 cell-index = <0>; 188 cell-index = <0>;
188 device_type = "serial"; 189 device_type = "serial";
189 compatible = "ns16550"; 190 compatible = "ns16550";
190 reg = <4500 100>; 191 reg = <0x4500 0x100>;
191 clock-frequency = <0>; 192 clock-frequency = <0>;
192 interrupts = <2a 2>; 193 interrupts = <42 2>;
193 interrupt-parent = <&mpic>; 194 interrupt-parent = <&mpic>;
194 }; 195 };
195 196
@@ -197,15 +198,15 @@
197 cell-index = <1>; 198 cell-index = <1>;
198 device_type = "serial"; 199 device_type = "serial";
199 compatible = "ns16550"; 200 compatible = "ns16550";
200 reg = <4600 100>; 201 reg = <0x4600 0x100>;
201 clock-frequency = <0>; 202 clock-frequency = <0>;
202 interrupts = <2a 2>; 203 interrupts = <42 2>;
203 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>;
204 }; 205 };
205 206
206 global-utilities@e0000 { //global utilities block 207 global-utilities@e0000 { //global utilities block
207 compatible = "fsl,mpc8548-guts"; 208 compatible = "fsl,mpc8548-guts";
208 reg = <e0000 1000>; 209 reg = <0xe0000 0x1000>;
209 fsl,has-rstcr; 210 fsl,has-rstcr;
210 }; 211 };
211 212
@@ -214,7 +215,7 @@
214 interrupt-controller; 215 interrupt-controller;
215 #address-cells = <0>; 216 #address-cells = <0>;
216 #interrupt-cells = <2>; 217 #interrupt-cells = <2>;
217 reg = <40000 40000>; 218 reg = <0x40000 0x40000>;
218 compatible = "chrp,open-pic"; 219 compatible = "chrp,open-pic";
219 device_type = "open-pic"; 220 device_type = "open-pic";
220 big-endian; 221 big-endian;
@@ -225,32 +226,32 @@
225 cell-index = <0>; 226 cell-index = <0>;
226 compatible = "fsl,mpc8540-pci"; 227 compatible = "fsl,mpc8540-pci";
227 device_type = "pci"; 228 device_type = "pci";
228 interrupt-map-mask = <f800 0 0 7>; 229 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
229 interrupt-map = < 230 interrupt-map = <
230 231
231 /* IDSEL 0x11 J17 Slot 1 */ 232 /* IDSEL 0x11 J17 Slot 1 */
232 8800 0 0 1 &mpic 2 1 233 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
233 8800 0 0 2 &mpic 3 1 234 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
234 8800 0 0 3 &mpic 4 1 235 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
235 8800 0 0 4 &mpic 1 1 236 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
236 237
237 /* IDSEL 0x12 J16 Slot 2 */ 238 /* IDSEL 0x12 J16 Slot 2 */
238 239
239 9000 0 0 1 &mpic 3 1 240 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
240 9000 0 0 2 &mpic 4 1 241 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
241 9000 0 0 3 &mpic 2 1 242 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
242 9000 0 0 4 &mpic 1 1>; 243 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
243 244
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 ff>; 247 bus-range = <0 255>;
247 ranges = <02000000 0 c0000000 c0000000 0 20000000 248 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
248 01000000 0 00000000 e1000000 0 00010000>; 249 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 }; 255 };
255 256
256 pci1: pcie@e0009000 { 257 pci1: pcie@e0009000 {
@@ -260,33 +261,33 @@
260 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
261 #size-cells = <2>; 262 #size-cells = <2>;
262 #address-cells = <3>; 263 #address-cells = <3>;
263 reg = <e0009000 1000>; 264 reg = <0xe0009000 0x1000>;
264 bus-range = <0 ff>; 265 bus-range = <0 255>;
265 ranges = <02000000 0 80000000 80000000 0 20000000 266 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
266 01000000 0 00000000 e1010000 0 00010000>; 267 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
267 clock-frequency = <1fca055>; 268 clock-frequency = <33333333>;
268 interrupt-parent = <&mpic>; 269 interrupt-parent = <&mpic>;
269 interrupts = <1a 2>; 270 interrupts = <26 2>;
270 interrupt-map-mask = <f800 0 0 7>; 271 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
271 interrupt-map = < 272 interrupt-map = <
272 /* IDSEL 0x0 */ 273 /* IDSEL 0x0 */
273 0000 0 0 1 &mpic 4 1 274 0000 0x0 0x0 0x1 &mpic 0x4 0x1
274 0000 0 0 2 &mpic 5 1 275 0000 0x0 0x0 0x2 &mpic 0x5 0x1
275 0000 0 0 3 &mpic 6 1 276 0000 0x0 0x0 0x3 &mpic 0x6 0x1
276 0000 0 0 4 &mpic 7 1 277 0000 0x0 0x0 0x4 &mpic 0x7 0x1
277 >; 278 >;
278 pcie@0 { 279 pcie@0 {
279 reg = <0 0 0 0 0>; 280 reg = <0x0 0x0 0x0 0x0 0x0>;
280 #size-cells = <2>; 281 #size-cells = <2>;
281 #address-cells = <3>; 282 #address-cells = <3>;
282 device_type = "pci"; 283 device_type = "pci";
283 ranges = <02000000 0 80000000 284 ranges = <0x2000000 0x0 0x80000000
284 02000000 0 80000000 285 0x2000000 0x0 0x80000000
285 0 20000000 286 0x0 0x20000000
286 287
287 01000000 0 00000000 288 0x1000000 0x0 0x0
288 01000000 0 00000000 289 0x1000000 0x0 0x0
289 0 00010000>; 290 0x0 0x10000>;
290 }; 291 };
291 }; 292 };
292 293
@@ -297,33 +298,33 @@
297 #interrupt-cells = <1>; 298 #interrupt-cells = <1>;
298 #size-cells = <2>; 299 #size-cells = <2>;
299 #address-cells = <3>; 300 #address-cells = <3>;
300 reg = <e000a000 1000>; 301 reg = <0xe000a000 0x1000>;
301 bus-range = <0 ff>; 302 bus-range = <0 255>;
302 ranges = <02000000 0 a0000000 a0000000 0 10000000 303 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
303 01000000 0 00000000 e1020000 0 00010000>; 304 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
304 clock-frequency = <1fca055>; 305 clock-frequency = <33333333>;
305 interrupt-parent = <&mpic>; 306 interrupt-parent = <&mpic>;
306 interrupts = <19 2>; 307 interrupts = <25 2>;
307 interrupt-map-mask = <f800 0 0 7>; 308 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
308 interrupt-map = < 309 interrupt-map = <
309 /* IDSEL 0x0 */ 310 /* IDSEL 0x0 */
310 0000 0 0 1 &mpic 0 1 311 0000 0x0 0x0 0x1 &mpic 0x0 0x1
311 0000 0 0 2 &mpic 1 1 312 0000 0x0 0x0 0x2 &mpic 0x1 0x1
312 0000 0 0 3 &mpic 2 1 313 0000 0x0 0x0 0x3 &mpic 0x2 0x1
313 0000 0 0 4 &mpic 3 1 314 0000 0x0 0x0 0x4 &mpic 0x3 0x1
314 >; 315 >;
315 pcie@0 { 316 pcie@0 {
316 reg = <0 0 0 0 0>; 317 reg = <0x0 0x0 0x0 0x0 0x0>;
317 #size-cells = <2>; 318 #size-cells = <2>;
318 #address-cells = <3>; 319 #address-cells = <3>;
319 device_type = "pci"; 320 device_type = "pci";
320 ranges = <02000000 0 a0000000 321 ranges = <0x2000000 0x0 0xa0000000
321 02000000 0 a0000000 322 0x2000000 0x0 0xa0000000
322 0 10000000 323 0x0 0x10000000
323 324
324 01000000 0 00000000 325 0x1000000 0x0 0x0
325 01000000 0 00000000 326 0x1000000 0x0 0x0
326 0 00010000>; 327 0x0 0x10000>;
327 }; 328 };
328 }; 329 };
329 330
@@ -334,72 +335,72 @@
334 #interrupt-cells = <1>; 335 #interrupt-cells = <1>;
335 #size-cells = <2>; 336 #size-cells = <2>;
336 #address-cells = <3>; 337 #address-cells = <3>;
337 reg = <e000b000 1000>; 338 reg = <0xe000b000 0x1000>;
338 bus-range = <0 ff>; 339 bus-range = <0 255>;
339 ranges = <02000000 0 b0000000 b0000000 0 00100000 340 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
340 01000000 0 00000000 b0100000 0 00100000>; 341 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
341 clock-frequency = <1fca055>; 342 clock-frequency = <33333333>;
342 interrupt-parent = <&mpic>; 343 interrupt-parent = <&mpic>;
343 interrupts = <1b 2>; 344 interrupts = <27 2>;
344 interrupt-map-mask = <ff00 0 0 1>; 345 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
345 interrupt-map = < 346 interrupt-map = <
346 // IDSEL 0x1c USB 347 // IDSEL 0x1c USB
347 e000 0 0 1 &i8259 c 2 348 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
348 e100 0 0 2 &i8259 9 2 349 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
349 e200 0 0 3 &i8259 a 2 350 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
350 e300 0 0 4 &i8259 b 2 351 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
351 352
352 // IDSEL 0x1d Audio 353 // IDSEL 0x1d Audio
353 e800 0 0 1 &i8259 6 2 354 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
354 355
355 // IDSEL 0x1e Legacy 356 // IDSEL 0x1e Legacy
356 f000 0 0 1 &i8259 7 2 357 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
357 f100 0 0 1 &i8259 7 2 358 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
358 359
359 // IDSEL 0x1f IDE/SATA 360 // IDSEL 0x1f IDE/SATA
360 f800 0 0 1 &i8259 e 2 361 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
361 f900 0 0 1 &i8259 5 2 362 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
362 >; 363 >;
363 364
364 pcie@0 { 365 pcie@0 {
365 reg = <0 0 0 0 0>; 366 reg = <0x0 0x0 0x0 0x0 0x0>;
366 #size-cells = <2>; 367 #size-cells = <2>;
367 #address-cells = <3>; 368 #address-cells = <3>;
368 device_type = "pci"; 369 device_type = "pci";
369 ranges = <02000000 0 b0000000 370 ranges = <0x2000000 0x0 0xb0000000
370 02000000 0 b0000000 371 0x2000000 0x0 0xb0000000
371 0 00100000 372 0x0 0x100000
372 373
373 01000000 0 00000000 374 0x1000000 0x0 0x0
374 01000000 0 00000000 375 0x1000000 0x0 0x0
375 0 00100000>; 376 0x0 0x100000>;
376 377
377 uli1575@0 { 378 uli1575@0 {
378 reg = <0 0 0 0 0>; 379 reg = <0x0 0x0 0x0 0x0 0x0>;
379 #size-cells = <2>; 380 #size-cells = <2>;
380 #address-cells = <3>; 381 #address-cells = <3>;
381 ranges = <02000000 0 b0000000 382 ranges = <0x2000000 0x0 0xb0000000
382 02000000 0 b0000000 383 0x2000000 0x0 0xb0000000
383 0 00100000 384 0x0 0x100000
384 385
385 01000000 0 00000000 386 0x1000000 0x0 0x0
386 01000000 0 00000000 387 0x1000000 0x0 0x0
387 0 00100000>; 388 0x0 0x100000>;
388 isa@1e { 389 isa@1e {
389 device_type = "isa"; 390 device_type = "isa";
390 #interrupt-cells = <2>; 391 #interrupt-cells = <2>;
391 #size-cells = <1>; 392 #size-cells = <1>;
392 #address-cells = <2>; 393 #address-cells = <2>;
393 reg = <f000 0 0 0 0>; 394 reg = <0xf000 0x0 0x0 0x0 0x0>;
394 ranges = <1 0 395 ranges = <0x1 0x0
395 01000000 0 0 396 0x1000000 0x0 0x0
396 00001000>; 397 0x1000>;
397 interrupt-parent = <&i8259>; 398 interrupt-parent = <&i8259>;
398 399
399 i8259: interrupt-controller@20 { 400 i8259: interrupt-controller@20 {
400 reg = <1 20 2 401 reg = <0x1 0x20 0x2
401 1 a0 2 402 0x1 0xa0 0x2
402 1 4d0 2>; 403 0x1 0x4d0 0x2>;
403 interrupt-controller; 404 interrupt-controller;
404 device_type = "interrupt-controller"; 405 device_type = "interrupt-controller";
405 #address-cells = <0>; 406 #address-cells = <0>;
@@ -412,28 +413,28 @@
412 i8042@60 { 413 i8042@60 {
413 #size-cells = <0>; 414 #size-cells = <0>;
414 #address-cells = <1>; 415 #address-cells = <1>;
415 reg = <1 60 1 1 64 1>; 416 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
416 interrupts = <1 3 c 3>; 417 interrupts = <1 3 12 3>;
417 interrupt-parent = <&i8259>; 418 interrupt-parent = <&i8259>;
418 419
419 keyboard@0 { 420 keyboard@0 {
420 reg = <0>; 421 reg = <0x0>;
421 compatible = "pnpPNP,303"; 422 compatible = "pnpPNP,303";
422 }; 423 };
423 424
424 mouse@1 { 425 mouse@1 {
425 reg = <1>; 426 reg = <0x1>;
426 compatible = "pnpPNP,f03"; 427 compatible = "pnpPNP,f03";
427 }; 428 };
428 }; 429 };
429 430
430 rtc@70 { 431 rtc@70 {
431 compatible = "pnpPNP,b00"; 432 compatible = "pnpPNP,b00";
432 reg = <1 70 2>; 433 reg = <0x1 0x70 0x2>;
433 }; 434 };
434 435
435 gpio@400 { 436 gpio@400 {
436 reg = <1 400 80>; 437 reg = <0x1 0x400 0x80>;
437 }; 438 };
438 }; 439 };
439 }; 440 };
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 1f470c6a1c63..fa298a8c81cc 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8548 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
@@ -36,11 +37,11 @@
36 37
37 PowerPC,8548@0 { 38 PowerPC,8548@0 {
38 device_type = "cpu"; 39 device_type = "cpu";
39 reg = <0>; 40 reg = <0x0>;
40 d-cache-line-size = <20>; // 32 bytes 41 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <20>; // 32 bytes 42 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <8000>; // L1, 32K 43 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <8000>; // L1, 32K 44 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>; // 33 MHz, from uboot 45 timebase-frequency = <0>; // 33 MHz, from uboot
45 bus-frequency = <0>; // 166 MHz 46 bus-frequency = <0>; // 166 MHz
46 clock-frequency = <0>; // 825 MHz, from uboot 47 clock-frequency = <0>; // 825 MHz, from uboot
@@ -49,31 +50,31 @@
49 50
50 memory { 51 memory {
51 device_type = "memory"; 52 device_type = "memory";
52 reg = <00000000 08000000>; // 128M at 0x0 53 reg = <0x0 0x8000000>; // 128M at 0x0
53 }; 54 };
54 55
55 soc8548@e0000000 { 56 soc8548@e0000000 {
56 #address-cells = <1>; 57 #address-cells = <1>;
57 #size-cells = <1>; 58 #size-cells = <1>;
58 device_type = "soc"; 59 device_type = "soc";
59 ranges = <00000000 e0000000 00100000>; 60 ranges = <0x0 0xe0000000 0x100000>;
60 reg = <e0000000 00001000>; // CCSRBAR 61 reg = <0xe0000000 0x1000>; // CCSRBAR
61 bus-frequency = <0>; 62 bus-frequency = <0>;
62 63
63 memory-controller@2000 { 64 memory-controller@2000 {
64 compatible = "fsl,8548-memory-controller"; 65 compatible = "fsl,8548-memory-controller";
65 reg = <2000 1000>; 66 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 67 interrupt-parent = <&mpic>;
67 interrupts = <12 2>; 68 interrupts = <18 2>;
68 }; 69 };
69 70
70 l2-cache-controller@20000 { 71 l2-cache-controller@20000 {
71 compatible = "fsl,8548-l2-cache-controller"; 72 compatible = "fsl,8548-l2-cache-controller";
72 reg = <20000 1000>; 73 reg = <0x20000 0x1000>;
73 cache-line-size = <20>; // 32 bytes 74 cache-line-size = <32>; // 32 bytes
74 cache-size = <80000>; // L2, 512K 75 cache-size = <0x80000>; // L2, 512K
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <10 2>; 77 interrupts = <16 2>;
77 }; 78 };
78 79
79 i2c@3000 { 80 i2c@3000 {
@@ -81,8 +82,8 @@
81 #size-cells = <0>; 82 #size-cells = <0>;
82 cell-index = <0>; 83 cell-index = <0>;
83 compatible = "fsl-i2c"; 84 compatible = "fsl-i2c";
84 reg = <3000 100>; 85 reg = <0x3000 0x100>;
85 interrupts = <2b 2>; 86 interrupts = <43 2>;
86 interrupt-parent = <&mpic>; 87 interrupt-parent = <&mpic>;
87 dfsrr; 88 dfsrr;
88 }; 89 };
@@ -92,8 +93,8 @@
92 #size-cells = <0>; 93 #size-cells = <0>;
93 cell-index = <1>; 94 cell-index = <1>;
94 compatible = "fsl-i2c"; 95 compatible = "fsl-i2c";
95 reg = <3100 100>; 96 reg = <0x3100 0x100>;
96 interrupts = <2b 2>; 97 interrupts = <43 2>;
97 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>;
98 dfsrr; 99 dfsrr;
99 }; 100 };
@@ -102,30 +103,30 @@
102 #address-cells = <1>; 103 #address-cells = <1>;
103 #size-cells = <0>; 104 #size-cells = <0>;
104 compatible = "fsl,gianfar-mdio"; 105 compatible = "fsl,gianfar-mdio";
105 reg = <24520 20>; 106 reg = <0x24520 0x20>;
106 107
107 phy0: ethernet-phy@0 { 108 phy0: ethernet-phy@0 {
108 interrupt-parent = <&mpic>; 109 interrupt-parent = <&mpic>;
109 interrupts = <5 1>; 110 interrupts = <5 1>;
110 reg = <0>; 111 reg = <0x0>;
111 device_type = "ethernet-phy"; 112 device_type = "ethernet-phy";
112 }; 113 };
113 phy1: ethernet-phy@1 { 114 phy1: ethernet-phy@1 {
114 interrupt-parent = <&mpic>; 115 interrupt-parent = <&mpic>;
115 interrupts = <5 1>; 116 interrupts = <5 1>;
116 reg = <1>; 117 reg = <0x1>;
117 device_type = "ethernet-phy"; 118 device_type = "ethernet-phy";
118 }; 119 };
119 phy2: ethernet-phy@2 { 120 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>;
121 interrupts = <5 1>; 122 interrupts = <5 1>;
122 reg = <2>; 123 reg = <0x2>;
123 device_type = "ethernet-phy"; 124 device_type = "ethernet-phy";
124 }; 125 };
125 phy3: ethernet-phy@3 { 126 phy3: ethernet-phy@3 {
126 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
127 interrupts = <5 1>; 128 interrupts = <5 1>;
128 reg = <3>; 129 reg = <0x3>;
129 device_type = "ethernet-phy"; 130 device_type = "ethernet-phy";
130 }; 131 };
131 }; 132 };
@@ -135,9 +136,9 @@
135 device_type = "network"; 136 device_type = "network";
136 model = "eTSEC"; 137 model = "eTSEC";
137 compatible = "gianfar"; 138 compatible = "gianfar";
138 reg = <24000 1000>; 139 reg = <0x24000 0x1000>;
139 local-mac-address = [ 00 00 00 00 00 00 ]; 140 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <1d 2 1e 2 22 2>; 141 interrupts = <29 2 30 2 34 2>;
141 interrupt-parent = <&mpic>; 142 interrupt-parent = <&mpic>;
142 phy-handle = <&phy0>; 143 phy-handle = <&phy0>;
143 }; 144 };
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <25000 1000>; 151 reg = <0x25000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <23 2 24 2 28 2>; 153 interrupts = <35 2 36 2 40 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy1>; 155 phy-handle = <&phy1>;
155 }; 156 };
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <26000 1000>; 164 reg = <0x26000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <1f 2 20 2 21 2>; 166 interrupts = <31 2 32 2 33 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy2>; 168 phy-handle = <&phy2>;
168 }; 169 };
@@ -172,9 +173,9 @@
172 device_type = "network"; 173 device_type = "network";
173 model = "eTSEC"; 174 model = "eTSEC";
174 compatible = "gianfar"; 175 compatible = "gianfar";
175 reg = <27000 1000>; 176 reg = <0x27000 0x1000>;
176 local-mac-address = [ 00 00 00 00 00 00 ]; 177 local-mac-address = [ 00 00 00 00 00 00 ];
177 interrupts = <25 2 26 2 27 2>; 178 interrupts = <37 2 38 2 39 2>;
178 interrupt-parent = <&mpic>; 179 interrupt-parent = <&mpic>;
179 phy-handle = <&phy3>; 180 phy-handle = <&phy3>;
180 }; 181 };
@@ -184,9 +185,9 @@
184 cell-index = <0>; 185 cell-index = <0>;
185 device_type = "serial"; 186 device_type = "serial";
186 compatible = "ns16550"; 187 compatible = "ns16550";
187 reg = <4500 100>; // reg base, size 188 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot? 189 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <2a 2>; 190 interrupts = <42 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 }; 192 };
192 193
@@ -194,15 +195,15 @@
194 cell-index = <1>; 195 cell-index = <1>;
195 device_type = "serial"; 196 device_type = "serial";
196 compatible = "ns16550"; 197 compatible = "ns16550";
197 reg = <4600 100>; // reg base, size 198 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot? 199 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <2a 2>; 200 interrupts = <42 2>;
200 interrupt-parent = <&mpic>; 201 interrupt-parent = <&mpic>;
201 }; 202 };
202 203
203 global-utilities@e0000 { //global utilities reg 204 global-utilities@e0000 { //global utilities reg
204 compatible = "fsl,mpc8548-guts"; 205 compatible = "fsl,mpc8548-guts";
205 reg = <e0000 1000>; 206 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr; 207 fsl,has-rstcr;
207 }; 208 };
208 209
@@ -211,7 +212,7 @@
211 interrupt-controller; 212 interrupt-controller;
212 #address-cells = <0>; 213 #address-cells = <0>;
213 #interrupt-cells = <2>; 214 #interrupt-cells = <2>;
214 reg = <40000 40000>; 215 reg = <0x40000 0x40000>;
215 compatible = "chrp,open-pic"; 216 compatible = "chrp,open-pic";
216 device_type = "open-pic"; 217 device_type = "open-pic";
217 big-endian; 218 big-endian;
@@ -220,139 +221,139 @@
220 221
221 pci0: pci@e0008000 { 222 pci0: pci@e0008000 {
222 cell-index = <0>; 223 cell-index = <0>;
223 interrupt-map-mask = <f800 0 0 7>; 224 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
224 interrupt-map = < 225 interrupt-map = <
225 /* IDSEL 0x4 (PCIX Slot 2) */ 226 /* IDSEL 0x4 (PCIX Slot 2) */
226 02000 0 0 1 &mpic 0 1 227 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
227 02000 0 0 2 &mpic 1 1 228 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
228 02000 0 0 3 &mpic 2 1 229 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
229 02000 0 0 4 &mpic 3 1 230 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
230 231
231 /* IDSEL 0x5 (PCIX Slot 3) */ 232 /* IDSEL 0x5 (PCIX Slot 3) */
232 02800 0 0 1 &mpic 1 1 233 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
233 02800 0 0 2 &mpic 2 1 234 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
234 02800 0 0 3 &mpic 3 1 235 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
235 02800 0 0 4 &mpic 0 1 236 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
236 237
237 /* IDSEL 0x6 (PCIX Slot 4) */ 238 /* IDSEL 0x6 (PCIX Slot 4) */
238 03000 0 0 1 &mpic 2 1 239 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
239 03000 0 0 2 &mpic 3 1 240 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
240 03000 0 0 3 &mpic 0 1 241 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
241 03000 0 0 4 &mpic 1 1 242 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
242 243
243 /* IDSEL 0x8 (PCIX Slot 5) */ 244 /* IDSEL 0x8 (PCIX Slot 5) */
244 04000 0 0 1 &mpic 0 1 245 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
245 04000 0 0 2 &mpic 1 1 246 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
246 04000 0 0 3 &mpic 2 1 247 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
247 04000 0 0 4 &mpic 3 1 248 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0xC (Tsi310 bridge) */ 250 /* IDSEL 0xC (Tsi310 bridge) */
250 06000 0 0 1 &mpic 0 1 251 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
251 06000 0 0 2 &mpic 1 1 252 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
252 06000 0 0 3 &mpic 2 1 253 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
253 06000 0 0 4 &mpic 3 1 254 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
254 255
255 /* IDSEL 0x14 (Slot 2) */ 256 /* IDSEL 0x14 (Slot 2) */
256 0a000 0 0 1 &mpic 0 1 257 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
257 0a000 0 0 2 &mpic 1 1 258 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
258 0a000 0 0 3 &mpic 2 1 259 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
259 0a000 0 0 4 &mpic 3 1 260 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
260 261
261 /* IDSEL 0x15 (Slot 3) */ 262 /* IDSEL 0x15 (Slot 3) */
262 0a800 0 0 1 &mpic 1 1 263 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
263 0a800 0 0 2 &mpic 2 1 264 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
264 0a800 0 0 3 &mpic 3 1 265 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
265 0a800 0 0 4 &mpic 0 1 266 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
266 267
267 /* IDSEL 0x16 (Slot 4) */ 268 /* IDSEL 0x16 (Slot 4) */
268 0b000 0 0 1 &mpic 2 1 269 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
269 0b000 0 0 2 &mpic 3 1 270 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
270 0b000 0 0 3 &mpic 0 1 271 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
271 0b000 0 0 4 &mpic 1 1 272 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
272 273
273 /* IDSEL 0x18 (Slot 5) */ 274 /* IDSEL 0x18 (Slot 5) */
274 0c000 0 0 1 &mpic 0 1 275 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
275 0c000 0 0 2 &mpic 1 1 276 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
276 0c000 0 0 3 &mpic 2 1 277 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
277 0c000 0 0 4 &mpic 3 1 278 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
278 279
279 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 280 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
280 0E000 0 0 1 &mpic 0 1 281 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
281 0E000 0 0 2 &mpic 1 1 282 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
282 0E000 0 0 3 &mpic 2 1 283 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
283 0E000 0 0 4 &mpic 3 1>; 284 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
284 285
285 interrupt-parent = <&mpic>; 286 interrupt-parent = <&mpic>;
286 interrupts = <18 2>; 287 interrupts = <24 2>;
287 bus-range = <0 0>; 288 bus-range = <0 0>;
288 ranges = <02000000 0 80000000 80000000 0 10000000 289 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
289 01000000 0 00000000 e2000000 0 00800000>; 290 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
290 clock-frequency = <3f940aa>; 291 clock-frequency = <66666666>;
291 #interrupt-cells = <1>; 292 #interrupt-cells = <1>;
292 #size-cells = <2>; 293 #size-cells = <2>;
293 #address-cells = <3>; 294 #address-cells = <3>;
294 reg = <e0008000 1000>; 295 reg = <0xe0008000 0x1000>;
295 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 296 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
296 device_type = "pci"; 297 device_type = "pci";
297 298
298 pci_bridge@1c { 299 pci_bridge@1c {
299 interrupt-map-mask = <f800 0 0 7>; 300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
300 interrupt-map = < 301 interrupt-map = <
301 302
302 /* IDSEL 0x00 (PrPMC Site) */ 303 /* IDSEL 0x00 (PrPMC Site) */
303 0000 0 0 1 &mpic 0 1 304 0000 0x0 0x0 0x1 &mpic 0x0 0x1
304 0000 0 0 2 &mpic 1 1 305 0000 0x0 0x0 0x2 &mpic 0x1 0x1
305 0000 0 0 3 &mpic 2 1 306 0000 0x0 0x0 0x3 &mpic 0x2 0x1
306 0000 0 0 4 &mpic 3 1 307 0000 0x0 0x0 0x4 &mpic 0x3 0x1
307 308
308 /* IDSEL 0x04 (VIA chip) */ 309 /* IDSEL 0x04 (VIA chip) */
309 2000 0 0 1 &mpic 0 1 310 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
310 2000 0 0 2 &mpic 1 1 311 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
311 2000 0 0 3 &mpic 2 1 312 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
312 2000 0 0 4 &mpic 3 1 313 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
313 314
314 /* IDSEL 0x05 (8139) */ 315 /* IDSEL 0x05 (8139) */
315 2800 0 0 1 &mpic 1 1 316 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
316 317
317 /* IDSEL 0x06 (Slot 6) */ 318 /* IDSEL 0x06 (Slot 6) */
318 3000 0 0 1 &mpic 2 1 319 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
319 3000 0 0 2 &mpic 3 1 320 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
320 3000 0 0 3 &mpic 0 1 321 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
321 3000 0 0 4 &mpic 1 1 322 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
322 323
323 /* IDESL 0x07 (Slot 7) */ 324 /* IDESL 0x07 (Slot 7) */
324 3800 0 0 1 &mpic 3 1 325 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
325 3800 0 0 2 &mpic 0 1 326 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
326 3800 0 0 3 &mpic 1 1 327 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
327 3800 0 0 4 &mpic 2 1>; 328 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
328 329
329 reg = <e000 0 0 0 0>; 330 reg = <0xe000 0x0 0x0 0x0 0x0>;
330 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
331 #size-cells = <2>; 332 #size-cells = <2>;
332 #address-cells = <3>; 333 #address-cells = <3>;
333 ranges = <02000000 0 80000000 334 ranges = <0x2000000 0x0 0x80000000
334 02000000 0 80000000 335 0x2000000 0x0 0x80000000
335 0 20000000 336 0x0 0x20000000
336 01000000 0 00000000 337 0x1000000 0x0 0x0
337 01000000 0 00000000 338 0x1000000 0x0 0x0
338 0 00080000>; 339 0x0 0x80000>;
339 clock-frequency = <1fca055>; 340 clock-frequency = <33333333>;
340 341
341 isa@4 { 342 isa@4 {
342 device_type = "isa"; 343 device_type = "isa";
343 #interrupt-cells = <2>; 344 #interrupt-cells = <2>;
344 #size-cells = <1>; 345 #size-cells = <1>;
345 #address-cells = <2>; 346 #address-cells = <2>;
346 reg = <2000 0 0 0 0>; 347 reg = <0x2000 0x0 0x0 0x0 0x0>;
347 ranges = <1 0 01000000 0 0 00001000>; 348 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
348 interrupt-parent = <&i8259>; 349 interrupt-parent = <&i8259>;
349 350
350 i8259: interrupt-controller@20 { 351 i8259: interrupt-controller@20 {
351 interrupt-controller; 352 interrupt-controller;
352 device_type = "interrupt-controller"; 353 device_type = "interrupt-controller";
353 reg = <1 20 2 354 reg = <0x1 0x20 0x2
354 1 a0 2 355 0x1 0xa0 0x2
355 1 4d0 2>; 356 0x1 0x4d0 0x2>;
356 #address-cells = <0>; 357 #address-cells = <0>;
357 #interrupt-cells = <2>; 358 #interrupt-cells = <2>;
358 compatible = "chrp,iic"; 359 compatible = "chrp,iic";
@@ -362,7 +363,7 @@
362 363
363 rtc@70 { 364 rtc@70 {
364 compatible = "pnpPNP,b00"; 365 compatible = "pnpPNP,b00";
365 reg = <1 70 2>; 366 reg = <0x1 0x70 0x2>;
366 }; 367 };
367 }; 368 };
368 }; 369 };
@@ -370,64 +371,64 @@
370 371
371 pci1: pci@e0009000 { 372 pci1: pci@e0009000 {
372 cell-index = <1>; 373 cell-index = <1>;
373 interrupt-map-mask = <f800 0 0 7>; 374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 interrupt-map = < 375 interrupt-map = <
375 376
376 /* IDSEL 0x15 */ 377 /* IDSEL 0x15 */
377 a800 0 0 1 &mpic b 1 378 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
378 a800 0 0 2 &mpic 1 1 379 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
379 a800 0 0 3 &mpic 2 1 380 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
380 a800 0 0 4 &mpic 3 1>; 381 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
381 382
382 interrupt-parent = <&mpic>; 383 interrupt-parent = <&mpic>;
383 interrupts = <19 2>; 384 interrupts = <25 2>;
384 bus-range = <0 0>; 385 bus-range = <0 0>;
385 ranges = <02000000 0 90000000 90000000 0 10000000 386 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 01000000 0 00000000 e2800000 0 00800000>; 387 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
387 clock-frequency = <3f940aa>; 388 clock-frequency = <66666666>;
388 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
389 #size-cells = <2>; 390 #size-cells = <2>;
390 #address-cells = <3>; 391 #address-cells = <3>;
391 reg = <e0009000 1000>; 392 reg = <0xe0009000 0x1000>;
392 compatible = "fsl,mpc8540-pci"; 393 compatible = "fsl,mpc8540-pci";
393 device_type = "pci"; 394 device_type = "pci";
394 }; 395 };
395 396
396 pci2: pcie@e000a000 { 397 pci2: pcie@e000a000 {
397 cell-index = <2>; 398 cell-index = <2>;
398 interrupt-map-mask = <f800 0 0 7>; 399 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 400 interrupt-map = <
400 401
401 /* IDSEL 0x0 (PEX) */ 402 /* IDSEL 0x0 (PEX) */
402 00000 0 0 1 &mpic 0 1 403 00000 0x0 0x0 0x1 &mpic 0x0 0x1
403 00000 0 0 2 &mpic 1 1 404 00000 0x0 0x0 0x2 &mpic 0x1 0x1
404 00000 0 0 3 &mpic 2 1 405 00000 0x0 0x0 0x3 &mpic 0x2 0x1
405 00000 0 0 4 &mpic 3 1>; 406 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
406 407
407 interrupt-parent = <&mpic>; 408 interrupt-parent = <&mpic>;
408 interrupts = <1a 2>; 409 interrupts = <26 2>;
409 bus-range = <0 ff>; 410 bus-range = <0 255>;
410 ranges = <02000000 0 a0000000 a0000000 0 20000000 411 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
411 01000000 0 00000000 e3000000 0 08000000>; 412 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
412 clock-frequency = <1fca055>; 413 clock-frequency = <33333333>;
413 #interrupt-cells = <1>; 414 #interrupt-cells = <1>;
414 #size-cells = <2>; 415 #size-cells = <2>;
415 #address-cells = <3>; 416 #address-cells = <3>;
416 reg = <e000a000 1000>; 417 reg = <0xe000a000 0x1000>;
417 compatible = "fsl,mpc8548-pcie"; 418 compatible = "fsl,mpc8548-pcie";
418 device_type = "pci"; 419 device_type = "pci";
419 pcie@0 { 420 pcie@0 {
420 reg = <0 0 0 0 0>; 421 reg = <0x0 0x0 0x0 0x0 0x0>;
421 #size-cells = <2>; 422 #size-cells = <2>;
422 #address-cells = <3>; 423 #address-cells = <3>;
423 device_type = "pci"; 424 device_type = "pci";
424 ranges = <02000000 0 a0000000 425 ranges = <0x2000000 0x0 0xa0000000
425 02000000 0 a0000000 426 0x2000000 0x0 0xa0000000
426 0 20000000 427 0x0 0x20000000
427 428
428 01000000 0 00000000 429 0x1000000 0x0 0x0
429 01000000 0 00000000 430 0x1000000 0x0 0x0
430 0 08000000>; 431 0x0 0x8000000>;
431 }; 432 };
432 }; 433 };
433}; 434};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 4538f3c38862..b025c566c10d 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8555 CDS Device Tree Source 2 * MPC8555 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8555CDS"; 15 model = "MPC8555CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8555@0 { 33 PowerPC,8555@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8555@e0000000 { 51 soc8555@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8555-memory-controller"; 60 compatible = "fsl,8555-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8555-l2-cache-controller"; 67 compatible = "fsl,8555-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8555-brg", 180 compatible = "fsl,mpc8555-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 639ce8a709a6..0cc16ab305d1 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8560 ADS Device Tree Source 2 * MPC8560 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8560ADS"; 15 model = "MPC8560ADS";
@@ -32,74 +33,74 @@
32 33
33 PowerPC,8560@0 { 34 PowerPC,8560@0 {
34 device_type = "cpu"; 35 device_type = "cpu";
35 reg = <0>; 36 reg = <0x0>;
36 d-cache-line-size = <20>; // 32 bytes 37 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <20>; // 32 bytes 38 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <8000>; // L1, 32K 39 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <04ead9a0>; 41 timebase-frequency = <82500000>;
41 bus-frequency = <13ab6680>; 42 bus-frequency = <330000000>;
42 clock-frequency = <312c8040>; 43 clock-frequency = <825000000>;
43 }; 44 };
44 }; 45 };
45 46
46 memory { 47 memory {
47 device_type = "memory"; 48 device_type = "memory";
48 reg = <00000000 10000000>; 49 reg = <0x0 0x10000000>;
49 }; 50 };
50 51
51 soc8560@e0000000 { 52 soc8560@e0000000 {
52 #address-cells = <1>; 53 #address-cells = <1>;
53 #size-cells = <1>; 54 #size-cells = <1>;
54 device_type = "soc"; 55 device_type = "soc";
55 ranges = <0 e0000000 00100000>; 56 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <e0000000 00000200>; 57 reg = <0xe0000000 0x200>;
57 bus-frequency = <13ab6680>; 58 bus-frequency = <330000000>;
58 59
59 memory-controller@2000 { 60 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,8540-memory-controller";
61 reg = <2000 1000>; 62 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
63 interrupts = <12 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <20000 1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <20>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
70 cache-size = <40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
71 interrupt-parent = <&mpic>; 72 interrupt-parent = <&mpic>;
72 interrupts = <10 2>; 73 interrupts = <16 2>;
73 }; 74 };
74 75
75 mdio@24520 { 76 mdio@24520 {
76 #address-cells = <1>; 77 #address-cells = <1>;
77 #size-cells = <0>; 78 #size-cells = <0>;
78 compatible = "fsl,gianfar-mdio"; 79 compatible = "fsl,gianfar-mdio";
79 reg = <24520 20>; 80 reg = <0x24520 0x20>;
80 81
81 phy0: ethernet-phy@0 { 82 phy0: ethernet-phy@0 {
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <5 1>; 84 interrupts = <5 1>;
84 reg = <0>; 85 reg = <0x0>;
85 device_type = "ethernet-phy"; 86 device_type = "ethernet-phy";
86 }; 87 };
87 phy1: ethernet-phy@1 { 88 phy1: ethernet-phy@1 {
88 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
89 interrupts = <5 1>; 90 interrupts = <5 1>;
90 reg = <1>; 91 reg = <0x1>;
91 device_type = "ethernet-phy"; 92 device_type = "ethernet-phy";
92 }; 93 };
93 phy2: ethernet-phy@2 { 94 phy2: ethernet-phy@2 {
94 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
95 interrupts = <7 1>; 96 interrupts = <7 1>;
96 reg = <2>; 97 reg = <0x2>;
97 device_type = "ethernet-phy"; 98 device_type = "ethernet-phy";
98 }; 99 };
99 phy3: ethernet-phy@3 { 100 phy3: ethernet-phy@3 {
100 interrupt-parent = <&mpic>; 101 interrupt-parent = <&mpic>;
101 interrupts = <7 1>; 102 interrupts = <7 1>;
102 reg = <3>; 103 reg = <0x3>;
103 device_type = "ethernet-phy"; 104 device_type = "ethernet-phy";
104 }; 105 };
105 }; 106 };
@@ -109,9 +110,9 @@
109 device_type = "network"; 110 device_type = "network";
110 model = "TSEC"; 111 model = "TSEC";
111 compatible = "gianfar"; 112 compatible = "gianfar";
112 reg = <24000 1000>; 113 reg = <0x24000 0x1000>;
113 local-mac-address = [ 00 00 00 00 00 00 ]; 114 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <1d 2 1e 2 22 2>; 115 interrupts = <29 2 30 2 34 2>;
115 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
116 phy-handle = <&phy0>; 117 phy-handle = <&phy0>;
117 }; 118 };
@@ -121,9 +122,9 @@
121 device_type = "network"; 122 device_type = "network";
122 model = "TSEC"; 123 model = "TSEC";
123 compatible = "gianfar"; 124 compatible = "gianfar";
124 reg = <25000 1000>; 125 reg = <0x25000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ]; 126 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <23 2 24 2 28 2>; 127 interrupts = <35 2 36 2 40 2>;
127 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
128 phy-handle = <&phy1>; 129 phy-handle = <&phy1>;
129 }; 130 };
@@ -132,7 +133,7 @@
132 interrupt-controller; 133 interrupt-controller;
133 #address-cells = <0>; 134 #address-cells = <0>;
134 #interrupt-cells = <2>; 135 #interrupt-cells = <2>;
135 reg = <40000 40000>; 136 reg = <0x40000 0x40000>;
136 device_type = "open-pic"; 137 device_type = "open-pic";
137 }; 138 };
138 139
@@ -140,17 +141,17 @@
140 #address-cells = <1>; 141 #address-cells = <1>;
141 #size-cells = <1>; 142 #size-cells = <1>;
142 compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; 143 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
143 reg = <919c0 30>; 144 reg = <0x919c0 0x30>;
144 ranges; 145 ranges;
145 146
146 muram@80000 { 147 muram@80000 {
147 #address-cells = <1>; 148 #address-cells = <1>;
148 #size-cells = <1>; 149 #size-cells = <1>;
149 ranges = <0 80000 10000>; 150 ranges = <0x0 0x80000 0x10000>;
150 151
151 data@0 { 152 data@0 {
152 compatible = "fsl,cpm-muram-data"; 153 compatible = "fsl,cpm-muram-data";
153 reg = <0 4000 9000 2000>; 154 reg = <0x0 0x4000 0x9000 0x2000>;
154 }; 155 };
155 }; 156 };
156 157
@@ -158,17 +159,17 @@
158 compatible = "fsl,mpc8560-brg", 159 compatible = "fsl,mpc8560-brg",
159 "fsl,cpm2-brg", 160 "fsl,cpm2-brg",
160 "fsl,cpm-brg"; 161 "fsl,cpm-brg";
161 reg = <919f0 10 915f0 10>; 162 reg = <0x919f0 0x10 0x915f0 0x10>;
162 clock-frequency = <d#165000000>; 163 clock-frequency = <165000000>;
163 }; 164 };
164 165
165 cpmpic: pic@90c00 { 166 cpmpic: pic@90c00 {
166 interrupt-controller; 167 interrupt-controller;
167 #address-cells = <0>; 168 #address-cells = <0>;
168 #interrupt-cells = <2>; 169 #interrupt-cells = <2>;
169 interrupts = <2e 2>; 170 interrupts = <46 2>;
170 interrupt-parent = <&mpic>; 171 interrupt-parent = <&mpic>;
171 reg = <90c00 80>; 172 reg = <0x90c00 0x80>;
172 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 173 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
173 }; 174 };
174 175
@@ -176,11 +177,11 @@
176 device_type = "serial"; 177 device_type = "serial";
177 compatible = "fsl,mpc8560-scc-uart", 178 compatible = "fsl,mpc8560-scc-uart",
178 "fsl,cpm2-scc-uart"; 179 "fsl,cpm2-scc-uart";
179 reg = <91a00 20 88000 100>; 180 reg = <0x91a00 0x20 0x88000 0x100>;
180 fsl,cpm-brg = <1>; 181 fsl,cpm-brg = <1>;
181 fsl,cpm-command = <00800000>; 182 fsl,cpm-command = <0x800000>;
182 current-speed = <1c200>; 183 current-speed = <115200>;
183 interrupts = <28 8>; 184 interrupts = <40 8>;
184 interrupt-parent = <&cpmpic>; 185 interrupt-parent = <&cpmpic>;
185 }; 186 };
186 187
@@ -188,11 +189,11 @@
188 device_type = "serial"; 189 device_type = "serial";
189 compatible = "fsl,mpc8560-scc-uart", 190 compatible = "fsl,mpc8560-scc-uart",
190 "fsl,cpm2-scc-uart"; 191 "fsl,cpm2-scc-uart";
191 reg = <91a20 20 88100 100>; 192 reg = <0x91a20 0x20 0x88100 0x100>;
192 fsl,cpm-brg = <2>; 193 fsl,cpm-brg = <2>;
193 fsl,cpm-command = <04a00000>; 194 fsl,cpm-command = <0x4a00000>;
194 current-speed = <1c200>; 195 current-speed = <115200>;
195 interrupts = <29 8>; 196 interrupts = <41 8>;
196 interrupt-parent = <&cpmpic>; 197 interrupt-parent = <&cpmpic>;
197 }; 198 };
198 199
@@ -200,10 +201,10 @@
200 device_type = "network"; 201 device_type = "network";
201 compatible = "fsl,mpc8560-fcc-enet", 202 compatible = "fsl,mpc8560-fcc-enet",
202 "fsl,cpm2-fcc-enet"; 203 "fsl,cpm2-fcc-enet";
203 reg = <91320 20 88500 100 913b0 1>; 204 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
204 local-mac-address = [ 00 00 00 00 00 00 ]; 205 local-mac-address = [ 00 00 00 00 00 00 ];
205 fsl,cpm-command = <16200300>; 206 fsl,cpm-command = <0x16200300>;
206 interrupts = <21 8>; 207 interrupts = <33 8>;
207 interrupt-parent = <&cpmpic>; 208 interrupt-parent = <&cpmpic>;
208 phy-handle = <&phy2>; 209 phy-handle = <&phy2>;
209 }; 210 };
@@ -212,10 +213,10 @@
212 device_type = "network"; 213 device_type = "network";
213 compatible = "fsl,mpc8560-fcc-enet", 214 compatible = "fsl,mpc8560-fcc-enet",
214 "fsl,cpm2-fcc-enet"; 215 "fsl,cpm2-fcc-enet";
215 reg = <91340 20 88600 100 913d0 1>; 216 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
216 local-mac-address = [ 00 00 00 00 00 00 ]; 217 local-mac-address = [ 00 00 00 00 00 00 ];
217 fsl,cpm-command = <1a400300>; 218 fsl,cpm-command = <0x1a400300>;
218 interrupts = <22 8>; 219 interrupts = <34 8>;
219 interrupt-parent = <&cpmpic>; 220 interrupt-parent = <&cpmpic>;
220 phy-handle = <&phy3>; 221 phy-handle = <&phy3>;
221 }; 222 };
@@ -229,87 +230,87 @@
229 #address-cells = <3>; 230 #address-cells = <3>;
230 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 231 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
231 device_type = "pci"; 232 device_type = "pci";
232 reg = <e0008000 1000>; 233 reg = <0xe0008000 0x1000>;
233 clock-frequency = <3f940aa>; 234 clock-frequency = <66666666>;
234 interrupt-map-mask = <f800 0 0 7>; 235 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
235 interrupt-map = < 236 interrupt-map = <
236 237
237 /* IDSEL 0x2 */ 238 /* IDSEL 0x2 */
238 1000 0 0 1 &mpic 1 1 239 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
239 1000 0 0 2 &mpic 2 1 240 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
240 1000 0 0 3 &mpic 3 1 241 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
241 1000 0 0 4 &mpic 4 1 242 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
242 243
243 /* IDSEL 0x3 */ 244 /* IDSEL 0x3 */
244 1800 0 0 1 &mpic 4 1 245 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
245 1800 0 0 2 &mpic 1 1 246 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
246 1800 0 0 3 &mpic 2 1 247 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
247 1800 0 0 4 &mpic 3 1 248 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0x4 */ 250 /* IDSEL 0x4 */
250 2000 0 0 1 &mpic 3 1 251 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
251 2000 0 0 2 &mpic 4 1 252 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
252 2000 0 0 3 &mpic 1 1 253 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
253 2000 0 0 4 &mpic 2 1 254 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
254 255
255 /* IDSEL 0x5 */ 256 /* IDSEL 0x5 */
256 2800 0 0 1 &mpic 2 1 257 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
257 2800 0 0 2 &mpic 3 1 258 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
258 2800 0 0 3 &mpic 4 1 259 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
259 2800 0 0 4 &mpic 1 1 260 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
260 261
261 /* IDSEL 12 */ 262 /* IDSEL 12 */
262 6000 0 0 1 &mpic 1 1 263 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
263 6000 0 0 2 &mpic 2 1 264 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
264 6000 0 0 3 &mpic 3 1 265 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
265 6000 0 0 4 &mpic 4 1 266 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
266 267
267 /* IDSEL 13 */ 268 /* IDSEL 13 */
268 6800 0 0 1 &mpic 4 1 269 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
269 6800 0 0 2 &mpic 1 1 270 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
270 6800 0 0 3 &mpic 2 1 271 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
271 6800 0 0 4 &mpic 3 1 272 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
272 273
273 /* IDSEL 14*/ 274 /* IDSEL 14*/
274 7000 0 0 1 &mpic 3 1 275 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
275 7000 0 0 2 &mpic 4 1 276 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
276 7000 0 0 3 &mpic 1 1 277 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
277 7000 0 0 4 &mpic 2 1 278 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
278 279
279 /* IDSEL 15 */ 280 /* IDSEL 15 */
280 7800 0 0 1 &mpic 2 1 281 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
281 7800 0 0 2 &mpic 3 1 282 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
282 7800 0 0 3 &mpic 4 1 283 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
283 7800 0 0 4 &mpic 1 1 284 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
284 285
285 /* IDSEL 18 */ 286 /* IDSEL 18 */
286 9000 0 0 1 &mpic 1 1 287 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
287 9000 0 0 2 &mpic 2 1 288 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
288 9000 0 0 3 &mpic 3 1 289 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
289 9000 0 0 4 &mpic 4 1 290 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
290 291
291 /* IDSEL 19 */ 292 /* IDSEL 19 */
292 9800 0 0 1 &mpic 4 1 293 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
293 9800 0 0 2 &mpic 1 1 294 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
294 9800 0 0 3 &mpic 2 1 295 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
295 9800 0 0 4 &mpic 3 1 296 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
296 297
297 /* IDSEL 20 */ 298 /* IDSEL 20 */
298 a000 0 0 1 &mpic 3 1 299 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
299 a000 0 0 2 &mpic 4 1 300 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
300 a000 0 0 3 &mpic 1 1 301 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
301 a000 0 0 4 &mpic 2 1 302 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
302 303
303 /* IDSEL 21 */ 304 /* IDSEL 21 */
304 a800 0 0 1 &mpic 2 1 305 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
305 a800 0 0 2 &mpic 3 1 306 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
306 a800 0 0 3 &mpic 4 1 307 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
307 a800 0 0 4 &mpic 1 1>; 308 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
308 309
309 interrupt-parent = <&mpic>; 310 interrupt-parent = <&mpic>;
310 interrupts = <18 2>; 311 interrupts = <24 2>;
311 bus-range = <0 0>; 312 bus-range = <0 0>;
312 ranges = <02000000 0 80000000 80000000 0 20000000 313 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
313 01000000 0 00000000 e2000000 0 01000000>; 314 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
314 }; 315 };
315}; 316};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index df4b5e89d7e4..3e6739fc0aa2 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8568E MDS Device Tree Source 2 * MPC8568E MDS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/* 14/*
14/memreserve/ 00000000 1000000; 15/memreserve/ 00000000 1000000;
@@ -37,11 +38,11 @@
37 38
38 PowerPC,8568@0 { 39 PowerPC,8568@0 {
39 device_type = "cpu"; 40 device_type = "cpu";
40 reg = <0>; 41 reg = <0x0>;
41 d-cache-line-size = <20>; // 32 bytes 42 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <20>; // 32 bytes 43 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <8000>; // L1, 32K 44 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <8000>; // L1, 32K 45 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; 46 timebase-frequency = <0>;
46 bus-frequency = <0>; 47 bus-frequency = <0>;
47 clock-frequency = <0>; 48 clock-frequency = <0>;
@@ -50,36 +51,36 @@
50 51
51 memory { 52 memory {
52 device_type = "memory"; 53 device_type = "memory";
53 reg = <00000000 10000000>; 54 reg = <0x0 0x10000000>;
54 }; 55 };
55 56
56 bcsr@f8000000 { 57 bcsr@f8000000 {
57 device_type = "board-control"; 58 device_type = "board-control";
58 reg = <f8000000 8000>; 59 reg = <0xf8000000 0x8000>;
59 }; 60 };
60 61
61 soc8568@e0000000 { 62 soc8568@e0000000 {
62 #address-cells = <1>; 63 #address-cells = <1>;
63 #size-cells = <1>; 64 #size-cells = <1>;
64 device_type = "soc"; 65 device_type = "soc";
65 ranges = <0 e0000000 00100000>; 66 ranges = <0x0 0xe0000000 0x100000>;
66 reg = <e0000000 00001000>; 67 reg = <0xe0000000 0x1000>;
67 bus-frequency = <0>; 68 bus-frequency = <0>;
68 69
69 memory-controller@2000 { 70 memory-controller@2000 {
70 compatible = "fsl,8568-memory-controller"; 71 compatible = "fsl,8568-memory-controller";
71 reg = <2000 1000>; 72 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>; 73 interrupt-parent = <&mpic>;
73 interrupts = <12 2>; 74 interrupts = <18 2>;
74 }; 75 };
75 76
76 l2-cache-controller@20000 { 77 l2-cache-controller@20000 {
77 compatible = "fsl,8568-l2-cache-controller"; 78 compatible = "fsl,8568-l2-cache-controller";
78 reg = <20000 1000>; 79 reg = <0x20000 0x1000>;
79 cache-line-size = <20>; // 32 bytes 80 cache-line-size = <32>; // 32 bytes
80 cache-size = <80000>; // L2, 512K 81 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 interrupts = <10 2>; 83 interrupts = <16 2>;
83 }; 84 };
84 85
85 i2c@3000 { 86 i2c@3000 {
@@ -87,14 +88,14 @@
87 #size-cells = <0>; 88 #size-cells = <0>;
88 cell-index = <0>; 89 cell-index = <0>;
89 compatible = "fsl-i2c"; 90 compatible = "fsl-i2c";
90 reg = <3000 100>; 91 reg = <0x3000 0x100>;
91 interrupts = <2b 2>; 92 interrupts = <43 2>;
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 dfsrr; 94 dfsrr;
94 95
95 rtc@68 { 96 rtc@68 {
96 compatible = "dallas,ds1374"; 97 compatible = "dallas,ds1374";
97 reg = <68>; 98 reg = <0x68>;
98 }; 99 };
99 }; 100 };
100 101
@@ -103,8 +104,8 @@
103 #size-cells = <0>; 104 #size-cells = <0>;
104 cell-index = <1>; 105 cell-index = <1>;
105 compatible = "fsl-i2c"; 106 compatible = "fsl-i2c";
106 reg = <3100 100>; 107 reg = <0x3100 0x100>;
107 interrupts = <2b 2>; 108 interrupts = <43 2>;
108 interrupt-parent = <&mpic>; 109 interrupt-parent = <&mpic>;
109 dfsrr; 110 dfsrr;
110 }; 111 };
@@ -113,30 +114,30 @@
113 #address-cells = <1>; 114 #address-cells = <1>;
114 #size-cells = <0>; 115 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio"; 116 compatible = "fsl,gianfar-mdio";
116 reg = <24520 20>; 117 reg = <0x24520 0x20>;
117 118
118 phy0: ethernet-phy@7 { 119 phy0: ethernet-phy@7 {
119 interrupt-parent = <&mpic>; 120 interrupt-parent = <&mpic>;
120 interrupts = <1 1>; 121 interrupts = <1 1>;
121 reg = <7>; 122 reg = <0x7>;
122 device_type = "ethernet-phy"; 123 device_type = "ethernet-phy";
123 }; 124 };
124 phy1: ethernet-phy@1 { 125 phy1: ethernet-phy@1 {
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 interrupts = <2 1>; 127 interrupts = <2 1>;
127 reg = <1>; 128 reg = <0x1>;
128 device_type = "ethernet-phy"; 129 device_type = "ethernet-phy";
129 }; 130 };
130 phy2: ethernet-phy@2 { 131 phy2: ethernet-phy@2 {
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 interrupts = <1 1>; 133 interrupts = <1 1>;
133 reg = <2>; 134 reg = <0x2>;
134 device_type = "ethernet-phy"; 135 device_type = "ethernet-phy";
135 }; 136 };
136 phy3: ethernet-phy@3 { 137 phy3: ethernet-phy@3 {
137 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
138 interrupts = <2 1>; 139 interrupts = <2 1>;
139 reg = <3>; 140 reg = <0x3>;
140 device_type = "ethernet-phy"; 141 device_type = "ethernet-phy";
141 }; 142 };
142 }; 143 };
@@ -146,9 +147,9 @@
146 device_type = "network"; 147 device_type = "network";
147 model = "eTSEC"; 148 model = "eTSEC";
148 compatible = "gianfar"; 149 compatible = "gianfar";
149 reg = <24000 1000>; 150 reg = <0x24000 0x1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ]; 151 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <1d 2 1e 2 22 2>; 152 interrupts = <29 2 30 2 34 2>;
152 interrupt-parent = <&mpic>; 153 interrupt-parent = <&mpic>;
153 phy-handle = <&phy2>; 154 phy-handle = <&phy2>;
154 }; 155 };
@@ -158,9 +159,9 @@
158 device_type = "network"; 159 device_type = "network";
159 model = "eTSEC"; 160 model = "eTSEC";
160 compatible = "gianfar"; 161 compatible = "gianfar";
161 reg = <25000 1000>; 162 reg = <0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ]; 163 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <23 2 24 2 28 2>; 164 interrupts = <35 2 36 2 40 2>;
164 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>;
165 phy-handle = <&phy3>; 166 phy-handle = <&phy3>;
166 }; 167 };
@@ -169,15 +170,15 @@
169 cell-index = <0>; 170 cell-index = <0>;
170 device_type = "serial"; 171 device_type = "serial";
171 compatible = "ns16550"; 172 compatible = "ns16550";
172 reg = <4500 100>; 173 reg = <0x4500 0x100>;
173 clock-frequency = <0>; 174 clock-frequency = <0>;
174 interrupts = <2a 2>; 175 interrupts = <42 2>;
175 interrupt-parent = <&mpic>; 176 interrupt-parent = <&mpic>;
176 }; 177 };
177 178
178 global-utilities@e0000 { //global utilities block 179 global-utilities@e0000 { //global utilities block
179 compatible = "fsl,mpc8548-guts"; 180 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>; 181 reg = <0xe0000 0x1000>;
181 fsl,has-rstcr; 182 fsl,has-rstcr;
182 }; 183 };
183 184
@@ -185,9 +186,9 @@
185 cell-index = <1>; 186 cell-index = <1>;
186 device_type = "serial"; 187 device_type = "serial";
187 compatible = "ns16550"; 188 compatible = "ns16550";
188 reg = <4600 100>; 189 reg = <0x4600 0x100>;
189 clock-frequency = <0>; 190 clock-frequency = <0>;
190 interrupts = <2a 2>; 191 interrupts = <42 2>;
191 interrupt-parent = <&mpic>; 192 interrupt-parent = <&mpic>;
192 }; 193 };
193 194
@@ -195,13 +196,13 @@
195 device_type = "crypto"; 196 device_type = "crypto";
196 model = "SEC2"; 197 model = "SEC2";
197 compatible = "talitos"; 198 compatible = "talitos";
198 reg = <30000 f000>; 199 reg = <0x30000 0xf000>;
199 interrupts = <2d 2>; 200 interrupts = <45 2>;
200 interrupt-parent = <&mpic>; 201 interrupt-parent = <&mpic>;
201 num-channels = <4>; 202 num-channels = <4>;
202 channel-fifo-len = <18>; 203 channel-fifo-len = <24>;
203 exec-units-mask = <000000fe>; 204 exec-units-mask = <0xfe>;
204 descriptor-types-mask = <012b0ebf>; 205 descriptor-types-mask = <0x12b0ebf>;
205 }; 206 };
206 207
207 mpic: pic@40000 { 208 mpic: pic@40000 {
@@ -209,73 +210,73 @@
209 interrupt-controller; 210 interrupt-controller;
210 #address-cells = <0>; 211 #address-cells = <0>;
211 #interrupt-cells = <2>; 212 #interrupt-cells = <2>;
212 reg = <40000 40000>; 213 reg = <0x40000 0x40000>;
213 compatible = "chrp,open-pic"; 214 compatible = "chrp,open-pic";
214 device_type = "open-pic"; 215 device_type = "open-pic";
215 big-endian; 216 big-endian;
216 }; 217 };
217 218
218 par_io@e0100 { 219 par_io@e0100 {
219 reg = <e0100 100>; 220 reg = <0xe0100 0x100>;
220 device_type = "par_io"; 221 device_type = "par_io";
221 num-ports = <7>; 222 num-ports = <7>;
222 223
223 pio1: ucc_pin@01 { 224 pio1: ucc_pin@01 {
224 pio-map = < 225 pio-map = <
225 /* port pin dir open_drain assignment has_irq */ 226 /* port pin dir open_drain assignment has_irq */
226 4 0a 1 0 2 0 /* TxD0 */ 227 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
227 4 09 1 0 2 0 /* TxD1 */ 228 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
228 4 08 1 0 2 0 /* TxD2 */ 229 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
229 4 07 1 0 2 0 /* TxD3 */ 230 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
230 4 17 1 0 2 0 /* TxD4 */ 231 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
231 4 16 1 0 2 0 /* TxD5 */ 232 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
232 4 15 1 0 2 0 /* TxD6 */ 233 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
233 4 14 1 0 2 0 /* TxD7 */ 234 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
234 4 0f 2 0 2 0 /* RxD0 */ 235 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
235 4 0e 2 0 2 0 /* RxD1 */ 236 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
236 4 0d 2 0 2 0 /* RxD2 */ 237 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
237 4 0c 2 0 2 0 /* RxD3 */ 238 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
238 4 1d 2 0 2 0 /* RxD4 */ 239 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
239 4 1c 2 0 2 0 /* RxD5 */ 240 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
240 4 1b 2 0 2 0 /* RxD6 */ 241 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
241 4 1a 2 0 2 0 /* RxD7 */ 242 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
242 4 0b 1 0 2 0 /* TX_EN */ 243 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
243 4 18 1 0 2 0 /* TX_ER */ 244 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
244 4 10 2 0 2 0 /* RX_DV */ 245 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
245 4 1e 2 0 2 0 /* RX_ER */ 246 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
246 4 11 2 0 2 0 /* RX_CLK */ 247 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
247 4 13 1 0 2 0 /* GTX_CLK */ 248 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
248 1 1f 2 0 3 0>; /* GTX125 */ 249 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
249 }; 250 };
250 251
251 pio2: ucc_pin@02 { 252 pio2: ucc_pin@02 {
252 pio-map = < 253 pio-map = <
253 /* port pin dir open_drain assignment has_irq */ 254 /* port pin dir open_drain assignment has_irq */
254 5 0a 1 0 2 0 /* TxD0 */ 255 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
255 5 09 1 0 2 0 /* TxD1 */ 256 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
256 5 08 1 0 2 0 /* TxD2 */ 257 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
257 5 07 1 0 2 0 /* TxD3 */ 258 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
258 5 17 1 0 2 0 /* TxD4 */ 259 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
259 5 16 1 0 2 0 /* TxD5 */ 260 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
260 5 15 1 0 2 0 /* TxD6 */ 261 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
261 5 14 1 0 2 0 /* TxD7 */ 262 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
262 5 0f 2 0 2 0 /* RxD0 */ 263 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
263 5 0e 2 0 2 0 /* RxD1 */ 264 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
264 5 0d 2 0 2 0 /* RxD2 */ 265 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
265 5 0c 2 0 2 0 /* RxD3 */ 266 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
266 5 1d 2 0 2 0 /* RxD4 */ 267 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
267 5 1c 2 0 2 0 /* RxD5 */ 268 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
268 5 1b 2 0 2 0 /* RxD6 */ 269 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
269 5 1a 2 0 2 0 /* RxD7 */ 270 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
270 5 0b 1 0 2 0 /* TX_EN */ 271 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
271 5 18 1 0 2 0 /* TX_ER */ 272 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
272 5 10 2 0 2 0 /* RX_DV */ 273 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
273 5 1e 2 0 2 0 /* RX_ER */ 274 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
274 5 11 2 0 2 0 /* RX_CLK */ 275 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
275 5 13 1 0 2 0 /* GTX_CLK */ 276 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
276 1 1f 2 0 3 0 /* GTX125 */ 277 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
277 4 06 3 0 2 0 /* MDIO */ 278 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
278 4 05 1 0 2 0>; /* MDC */ 279 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
279 }; 280 };
280 }; 281 };
281 }; 282 };
@@ -285,28 +286,28 @@
285 #size-cells = <1>; 286 #size-cells = <1>;
286 device_type = "qe"; 287 device_type = "qe";
287 compatible = "fsl,qe"; 288 compatible = "fsl,qe";
288 ranges = <0 e0080000 00040000>; 289 ranges = <0x0 0xe0080000 0x40000>;
289 reg = <e0080000 480>; 290 reg = <0xe0080000 0x480>;
290 brg-frequency = <0>; 291 brg-frequency = <0>;
291 bus-frequency = <179A7B00>; 292 bus-frequency = <396000000>;
292 293
293 muram@10000 { 294 muram@10000 {
294 #address-cells = <1>; 295 #address-cells = <1>;
295 #size-cells = <1>; 296 #size-cells = <1>;
296 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 297 compatible = "fsl,qe-muram", "fsl,cpm-muram";
297 ranges = <0 00010000 0000c000>; 298 ranges = <0x0 0x10000 0xc000>;
298 299
299 data-only@0 { 300 data-only@0 {
300 compatible = "fsl,qe-muram-data", 301 compatible = "fsl,qe-muram-data",
301 "fsl,cpm-muram-data"; 302 "fsl,cpm-muram-data";
302 reg = <0 c000>; 303 reg = <0x0 0xc000>;
303 }; 304 };
304 }; 305 };
305 306
306 spi@4c0 { 307 spi@4c0 {
307 cell-index = <0>; 308 cell-index = <0>;
308 compatible = "fsl,spi"; 309 compatible = "fsl,spi";
309 reg = <4c0 40>; 310 reg = <0x4c0 0x40>;
310 interrupts = <2>; 311 interrupts = <2>;
311 interrupt-parent = <&qeic>; 312 interrupt-parent = <&qeic>;
312 mode = "cpu"; 313 mode = "cpu";
@@ -315,7 +316,7 @@
315 spi@500 { 316 spi@500 {
316 cell-index = <1>; 317 cell-index = <1>;
317 compatible = "fsl,spi"; 318 compatible = "fsl,spi";
318 reg = <500 40>; 319 reg = <0x500 0x40>;
319 interrupts = <1>; 320 interrupts = <1>;
320 interrupt-parent = <&qeic>; 321 interrupt-parent = <&qeic>;
321 mode = "cpu"; 322 mode = "cpu";
@@ -325,8 +326,8 @@
325 device_type = "network"; 326 device_type = "network";
326 compatible = "ucc_geth"; 327 compatible = "ucc_geth";
327 cell-index = <1>; 328 cell-index = <1>;
328 reg = <2000 200>; 329 reg = <0x2000 0x200>;
329 interrupts = <20>; 330 interrupts = <32>;
330 interrupt-parent = <&qeic>; 331 interrupt-parent = <&qeic>;
331 local-mac-address = [ 00 00 00 00 00 00 ]; 332 local-mac-address = [ 00 00 00 00 00 00 ];
332 rx-clock-name = "none"; 333 rx-clock-name = "none";
@@ -340,8 +341,8 @@
340 device_type = "network"; 341 device_type = "network";
341 compatible = "ucc_geth"; 342 compatible = "ucc_geth";
342 cell-index = <2>; 343 cell-index = <2>;
343 reg = <3000 200>; 344 reg = <0x3000 0x200>;
344 interrupts = <21>; 345 interrupts = <33>;
345 interrupt-parent = <&qeic>; 346 interrupt-parent = <&qeic>;
346 local-mac-address = [ 00 00 00 00 00 00 ]; 347 local-mac-address = [ 00 00 00 00 00 00 ];
347 rx-clock-name = "none"; 348 rx-clock-name = "none";
@@ -354,7 +355,7 @@
354 mdio@2120 { 355 mdio@2120 {
355 #address-cells = <1>; 356 #address-cells = <1>;
356 #size-cells = <0>; 357 #size-cells = <0>;
357 reg = <2120 18>; 358 reg = <0x2120 0x18>;
358 compatible = "fsl,ucc-mdio"; 359 compatible = "fsl,ucc-mdio";
359 360
360 /* These are the same PHYs as on 361 /* These are the same PHYs as on
@@ -362,25 +363,25 @@
362 qe_phy0: ethernet-phy@07 { 363 qe_phy0: ethernet-phy@07 {
363 interrupt-parent = <&mpic>; 364 interrupt-parent = <&mpic>;
364 interrupts = <1 1>; 365 interrupts = <1 1>;
365 reg = <7>; 366 reg = <0x7>;
366 device_type = "ethernet-phy"; 367 device_type = "ethernet-phy";
367 }; 368 };
368 qe_phy1: ethernet-phy@01 { 369 qe_phy1: ethernet-phy@01 {
369 interrupt-parent = <&mpic>; 370 interrupt-parent = <&mpic>;
370 interrupts = <2 1>; 371 interrupts = <2 1>;
371 reg = <1>; 372 reg = <0x1>;
372 device_type = "ethernet-phy"; 373 device_type = "ethernet-phy";
373 }; 374 };
374 qe_phy2: ethernet-phy@02 { 375 qe_phy2: ethernet-phy@02 {
375 interrupt-parent = <&mpic>; 376 interrupt-parent = <&mpic>;
376 interrupts = <1 1>; 377 interrupts = <1 1>;
377 reg = <2>; 378 reg = <0x2>;
378 device_type = "ethernet-phy"; 379 device_type = "ethernet-phy";
379 }; 380 };
380 qe_phy3: ethernet-phy@03 { 381 qe_phy3: ethernet-phy@03 {
381 interrupt-parent = <&mpic>; 382 interrupt-parent = <&mpic>;
382 interrupts = <2 1>; 383 interrupts = <2 1>;
383 reg = <3>; 384 reg = <0x3>;
384 device_type = "ethernet-phy"; 385 device_type = "ethernet-phy";
385 }; 386 };
386 }; 387 };
@@ -390,9 +391,9 @@
390 compatible = "fsl,qe-ic"; 391 compatible = "fsl,qe-ic";
391 #address-cells = <0>; 392 #address-cells = <0>;
392 #interrupt-cells = <1>; 393 #interrupt-cells = <1>;
393 reg = <80 80>; 394 reg = <0x80 0x80>;
394 big-endian; 395 big-endian;
395 interrupts = <2e 2 2e 2>; //high:30 low:30 396 interrupts = <46 2 46 2>; //high:30 low:30
396 interrupt-parent = <&mpic>; 397 interrupt-parent = <&mpic>;
397 }; 398 };
398 399
@@ -400,30 +401,30 @@
400 401
401 pci0: pci@e0008000 { 402 pci0: pci@e0008000 {
402 cell-index = <0>; 403 cell-index = <0>;
403 interrupt-map-mask = <f800 0 0 7>; 404 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
404 interrupt-map = < 405 interrupt-map = <
405 /* IDSEL 0x12 AD18 */ 406 /* IDSEL 0x12 AD18 */
406 9000 0 0 1 &mpic 5 1 407 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
407 9000 0 0 2 &mpic 6 1 408 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
408 9000 0 0 3 &mpic 7 1 409 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
409 9000 0 0 4 &mpic 4 1 410 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
410 411
411 /* IDSEL 0x13 AD19 */ 412 /* IDSEL 0x13 AD19 */
412 9800 0 0 1 &mpic 6 1 413 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
413 9800 0 0 2 &mpic 7 1 414 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
414 9800 0 0 3 &mpic 4 1 415 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
415 9800 0 0 4 &mpic 5 1>; 416 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
416 417
417 interrupt-parent = <&mpic>; 418 interrupt-parent = <&mpic>;
418 interrupts = <18 2>; 419 interrupts = <24 2>;
419 bus-range = <0 ff>; 420 bus-range = <0 255>;
420 ranges = <02000000 0 80000000 80000000 0 20000000 421 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
421 01000000 0 00000000 e2000000 0 00800000>; 422 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
422 clock-frequency = <3f940aa>; 423 clock-frequency = <66666666>;
423 #interrupt-cells = <1>; 424 #interrupt-cells = <1>;
424 #size-cells = <2>; 425 #size-cells = <2>;
425 #address-cells = <3>; 426 #address-cells = <3>;
426 reg = <e0008000 1000>; 427 reg = <0xe0008000 0x1000>;
427 compatible = "fsl,mpc8540-pci"; 428 compatible = "fsl,mpc8540-pci";
428 device_type = "pci"; 429 device_type = "pci";
429 }; 430 };
@@ -431,39 +432,39 @@
431 /* PCI Express */ 432 /* PCI Express */
432 pci1: pcie@e000a000 { 433 pci1: pcie@e000a000 {
433 cell-index = <2>; 434 cell-index = <2>;
434 interrupt-map-mask = <f800 0 0 7>; 435 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
435 interrupt-map = < 436 interrupt-map = <
436 437
437 /* IDSEL 0x0 (PEX) */ 438 /* IDSEL 0x0 (PEX) */
438 00000 0 0 1 &mpic 0 1 439 00000 0x0 0x0 0x1 &mpic 0x0 0x1
439 00000 0 0 2 &mpic 1 1 440 00000 0x0 0x0 0x2 &mpic 0x1 0x1
440 00000 0 0 3 &mpic 2 1 441 00000 0x0 0x0 0x3 &mpic 0x2 0x1
441 00000 0 0 4 &mpic 3 1>; 442 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
442 443
443 interrupt-parent = <&mpic>; 444 interrupt-parent = <&mpic>;
444 interrupts = <1a 2>; 445 interrupts = <26 2>;
445 bus-range = <0 ff>; 446 bus-range = <0 255>;
446 ranges = <02000000 0 a0000000 a0000000 0 10000000 447 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
447 01000000 0 00000000 e2800000 0 00800000>; 448 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
448 clock-frequency = <1fca055>; 449 clock-frequency = <33333333>;
449 #interrupt-cells = <1>; 450 #interrupt-cells = <1>;
450 #size-cells = <2>; 451 #size-cells = <2>;
451 #address-cells = <3>; 452 #address-cells = <3>;
452 reg = <e000a000 1000>; 453 reg = <0xe000a000 0x1000>;
453 compatible = "fsl,mpc8548-pcie"; 454 compatible = "fsl,mpc8548-pcie";
454 device_type = "pci"; 455 device_type = "pci";
455 pcie@0 { 456 pcie@0 {
456 reg = <0 0 0 0 0>; 457 reg = <0x0 0x0 0x0 0x0 0x0>;
457 #size-cells = <2>; 458 #size-cells = <2>;
458 #address-cells = <3>; 459 #address-cells = <3>;
459 device_type = "pci"; 460 device_type = "pci";
460 ranges = <02000000 0 a0000000 461 ranges = <0x2000000 0x0 0xa0000000
461 02000000 0 a0000000 462 0x2000000 0x0 0xa0000000
462 0 10000000 463 0x0 0x10000000
463 464
464 01000000 0 00000000 465 0x1000000 0x0 0x0
465 01000000 0 00000000 466 0x1000000 0x0 0x0
466 0 00800000>; 467 0x0 0x800000>;
467 }; 468 };
468 }; 469 };
469}; 470};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index db37214aee37..66f27ab613a2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "fsl,MPC8572DS"; 14 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS"; 15 compatible = "fsl,MPC8572DS";
@@ -33,11 +34,11 @@
33 34
34 PowerPC,8572@0 { 35 PowerPC,8572@0 {
35 device_type = "cpu"; 36 device_type = "cpu";
36 reg = <0>; 37 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 42 timebase-frequency = <0>;
42 bus-frequency = <0>; 43 bus-frequency = <0>;
43 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -45,11 +46,11 @@
45 46
46 PowerPC,8572@1 { 47 PowerPC,8572@1 {
47 device_type = "cpu"; 48 device_type = "cpu";
48 reg = <1>; 49 reg = <0x1>;
49 d-cache-line-size = <20>; // 32 bytes 50 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <20>; // 32 bytes 51 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <8000>; // L1, 32K 52 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <8000>; // L1, 32K 53 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>; 54 timebase-frequency = <0>;
54 bus-frequency = <0>; 55 bus-frequency = <0>;
55 clock-frequency = <0>; 56 clock-frequency = <0>;
@@ -58,38 +59,38 @@
58 59
59 memory { 60 memory {
60 device_type = "memory"; 61 device_type = "memory";
61 reg = <00000000 00000000>; // Filled by U-Boot 62 reg = <0x0 0x0>; // Filled by U-Boot
62 }; 63 };
63 64
64 soc8572@ffe00000 { 65 soc8572@ffe00000 {
65 #address-cells = <1>; 66 #address-cells = <1>;
66 #size-cells = <1>; 67 #size-cells = <1>;
67 device_type = "soc"; 68 device_type = "soc";
68 ranges = <00000000 ffe00000 00100000>; 69 ranges = <0x0 0xffe00000 0x100000>;
69 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed 70 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
70 bus-frequency = <0>; // Filled out by uboot. 71 bus-frequency = <0>; // Filled out by uboot.
71 72
72 memory-controller@2000 { 73 memory-controller@2000 {
73 compatible = "fsl,mpc8572-memory-controller"; 74 compatible = "fsl,mpc8572-memory-controller";
74 reg = <2000 1000>; 75 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <12 2>; 77 interrupts = <18 2>;
77 }; 78 };
78 79
79 memory-controller@6000 { 80 memory-controller@6000 {
80 compatible = "fsl,mpc8572-memory-controller"; 81 compatible = "fsl,mpc8572-memory-controller";
81 reg = <6000 1000>; 82 reg = <0x6000 0x1000>;
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <12 2>; 84 interrupts = <18 2>;
84 }; 85 };
85 86
86 l2-cache-controller@20000 { 87 l2-cache-controller@20000 {
87 compatible = "fsl,mpc8572-l2-cache-controller"; 88 compatible = "fsl,mpc8572-l2-cache-controller";
88 reg = <20000 1000>; 89 reg = <0x20000 0x1000>;
89 cache-line-size = <20>; // 32 bytes 90 cache-line-size = <32>; // 32 bytes
90 cache-size = <80000>; // L2, 512K 91 cache-size = <0x80000>; // L2, 512K
91 interrupt-parent = <&mpic>; 92 interrupt-parent = <&mpic>;
92 interrupts = <10 2>; 93 interrupts = <16 2>;
93 }; 94 };
94 95
95 i2c@3000 { 96 i2c@3000 {
@@ -97,8 +98,8 @@
97 #size-cells = <0>; 98 #size-cells = <0>;
98 cell-index = <0>; 99 cell-index = <0>;
99 compatible = "fsl-i2c"; 100 compatible = "fsl-i2c";
100 reg = <3000 100>; 101 reg = <0x3000 0x100>;
101 interrupts = <2b 2>; 102 interrupts = <43 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 dfsrr; 104 dfsrr;
104 }; 105 };
@@ -108,8 +109,8 @@
108 #size-cells = <0>; 109 #size-cells = <0>;
109 cell-index = <1>; 110 cell-index = <1>;
110 compatible = "fsl-i2c"; 111 compatible = "fsl-i2c";
111 reg = <3100 100>; 112 reg = <0x3100 0x100>;
112 interrupts = <2b 2>; 113 interrupts = <43 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 dfsrr; 115 dfsrr;
115 }; 116 };
@@ -118,27 +119,27 @@
118 #address-cells = <1>; 119 #address-cells = <1>;
119 #size-cells = <0>; 120 #size-cells = <0>;
120 compatible = "fsl,gianfar-mdio"; 121 compatible = "fsl,gianfar-mdio";
121 reg = <24520 20>; 122 reg = <0x24520 0x20>;
122 123
123 phy0: ethernet-phy@0 { 124 phy0: ethernet-phy@0 {
124 interrupt-parent = <&mpic>; 125 interrupt-parent = <&mpic>;
125 interrupts = <a 1>; 126 interrupts = <10 1>;
126 reg = <0>; 127 reg = <0x0>;
127 }; 128 };
128 phy1: ethernet-phy@1 { 129 phy1: ethernet-phy@1 {
129 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>;
130 interrupts = <a 1>; 131 interrupts = <10 1>;
131 reg = <1>; 132 reg = <0x1>;
132 }; 133 };
133 phy2: ethernet-phy@2 { 134 phy2: ethernet-phy@2 {
134 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
135 interrupts = <a 1>; 136 interrupts = <10 1>;
136 reg = <2>; 137 reg = <0x2>;
137 }; 138 };
138 phy3: ethernet-phy@3 { 139 phy3: ethernet-phy@3 {
139 interrupt-parent = <&mpic>; 140 interrupt-parent = <&mpic>;
140 interrupts = <a 1>; 141 interrupts = <10 1>;
141 reg = <3>; 142 reg = <0x3>;
142 }; 143 };
143 }; 144 };
144 145
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <24000 1000>; 151 reg = <0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <1d 2 1e 2 22 2>; 153 interrupts = <29 2 30 2 34 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy0>; 155 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-id"; 156 phy-connection-type = "rgmii-id";
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <25000 1000>; 164 reg = <0x25000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <23 2 24 2 28 2>; 166 interrupts = <35 2 36 2 40 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy1>; 168 phy-handle = <&phy1>;
168 phy-connection-type = "rgmii-id"; 169 phy-connection-type = "rgmii-id";
@@ -173,9 +174,9 @@
173 device_type = "network"; 174 device_type = "network";
174 model = "eTSEC"; 175 model = "eTSEC";
175 compatible = "gianfar"; 176 compatible = "gianfar";
176 reg = <26000 1000>; 177 reg = <0x26000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ]; 178 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <1f 2 20 2 21 2>; 179 interrupts = <31 2 32 2 33 2>;
179 interrupt-parent = <&mpic>; 180 interrupt-parent = <&mpic>;
180 phy-handle = <&phy2>; 181 phy-handle = <&phy2>;
181 phy-connection-type = "rgmii-id"; 182 phy-connection-type = "rgmii-id";
@@ -186,9 +187,9 @@
186 device_type = "network"; 187 device_type = "network";
187 model = "eTSEC"; 188 model = "eTSEC";
188 compatible = "gianfar"; 189 compatible = "gianfar";
189 reg = <27000 1000>; 190 reg = <0x27000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <25 2 26 2 27 2>; 192 interrupts = <37 2 38 2 39 2>;
192 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
193 phy-handle = <&phy3>; 194 phy-handle = <&phy3>;
194 phy-connection-type = "rgmii-id"; 195 phy-connection-type = "rgmii-id";
@@ -198,9 +199,9 @@
198 cell-index = <0>; 199 cell-index = <0>;
199 device_type = "serial"; 200 device_type = "serial";
200 compatible = "ns16550"; 201 compatible = "ns16550";
201 reg = <4500 100>; 202 reg = <0x4500 0x100>;
202 clock-frequency = <0>; 203 clock-frequency = <0>;
203 interrupts = <2a 2>; 204 interrupts = <42 2>;
204 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
205 }; 206 };
206 207
@@ -208,15 +209,15 @@
208 cell-index = <1>; 209 cell-index = <1>;
209 device_type = "serial"; 210 device_type = "serial";
210 compatible = "ns16550"; 211 compatible = "ns16550";
211 reg = <4600 100>; 212 reg = <0x4600 0x100>;
212 clock-frequency = <0>; 213 clock-frequency = <0>;
213 interrupts = <2a 2>; 214 interrupts = <42 2>;
214 interrupt-parent = <&mpic>; 215 interrupt-parent = <&mpic>;
215 }; 216 };
216 217
217 global-utilities@e0000 { //global utilities block 218 global-utilities@e0000 { //global utilities block
218 compatible = "fsl,mpc8572-guts"; 219 compatible = "fsl,mpc8572-guts";
219 reg = <e0000 1000>; 220 reg = <0xe0000 0x1000>;
220 fsl,has-rstcr; 221 fsl,has-rstcr;
221 }; 222 };
222 223
@@ -225,7 +226,7 @@
225 interrupt-controller; 226 interrupt-controller;
226 #address-cells = <0>; 227 #address-cells = <0>;
227 #interrupt-cells = <2>; 228 #interrupt-cells = <2>;
228 reg = <40000 40000>; 229 reg = <0x40000 0x40000>;
229 compatible = "chrp,open-pic"; 230 compatible = "chrp,open-pic";
230 device_type = "open-pic"; 231 device_type = "open-pic";
231 big-endian; 232 big-endian;
@@ -239,167 +240,167 @@
239 #interrupt-cells = <1>; 240 #interrupt-cells = <1>;
240 #size-cells = <2>; 241 #size-cells = <2>;
241 #address-cells = <3>; 242 #address-cells = <3>;
242 reg = <ffe08000 1000>; 243 reg = <0xffe08000 0x1000>;
243 bus-range = <0 ff>; 244 bus-range = <0 255>;
244 ranges = <02000000 0 80000000 80000000 0 20000000 245 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
245 01000000 0 00000000 ffc00000 0 00010000>; 246 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
246 clock-frequency = <1fca055>; 247 clock-frequency = <33333333>;
247 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
248 interrupts = <18 2>; 249 interrupts = <24 2>;
249 interrupt-map-mask = <ff00 0 0 7>; 250 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
250 interrupt-map = < 251 interrupt-map = <
251 /* IDSEL 0x11 func 0 - PCI slot 1 */ 252 /* IDSEL 0x11 func 0 - PCI slot 1 */
252 8800 0 0 1 &mpic 2 1 253 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
253 8800 0 0 2 &mpic 3 1 254 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
254 8800 0 0 3 &mpic 4 1 255 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
255 8800 0 0 4 &mpic 1 1 256 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
256 257
257 /* IDSEL 0x11 func 1 - PCI slot 1 */ 258 /* IDSEL 0x11 func 1 - PCI slot 1 */
258 8900 0 0 1 &mpic 2 1 259 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
259 8900 0 0 2 &mpic 3 1 260 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
260 8900 0 0 3 &mpic 4 1 261 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
261 8900 0 0 4 &mpic 1 1 262 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
262 263
263 /* IDSEL 0x11 func 2 - PCI slot 1 */ 264 /* IDSEL 0x11 func 2 - PCI slot 1 */
264 8a00 0 0 1 &mpic 2 1 265 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
265 8a00 0 0 2 &mpic 3 1 266 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
266 8a00 0 0 3 &mpic 4 1 267 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
267 8a00 0 0 4 &mpic 1 1 268 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
268 269
269 /* IDSEL 0x11 func 3 - PCI slot 1 */ 270 /* IDSEL 0x11 func 3 - PCI slot 1 */
270 8b00 0 0 1 &mpic 2 1 271 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
271 8b00 0 0 2 &mpic 3 1 272 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
272 8b00 0 0 3 &mpic 4 1 273 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
273 8b00 0 0 4 &mpic 1 1 274 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
274 275
275 /* IDSEL 0x11 func 4 - PCI slot 1 */ 276 /* IDSEL 0x11 func 4 - PCI slot 1 */
276 8c00 0 0 1 &mpic 2 1 277 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
277 8c00 0 0 2 &mpic 3 1 278 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
278 8c00 0 0 3 &mpic 4 1 279 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
279 8c00 0 0 4 &mpic 1 1 280 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
280 281
281 /* IDSEL 0x11 func 5 - PCI slot 1 */ 282 /* IDSEL 0x11 func 5 - PCI slot 1 */
282 8d00 0 0 1 &mpic 2 1 283 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
283 8d00 0 0 2 &mpic 3 1 284 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
284 8d00 0 0 3 &mpic 4 1 285 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
285 8d00 0 0 4 &mpic 1 1 286 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
286 287
287 /* IDSEL 0x11 func 6 - PCI slot 1 */ 288 /* IDSEL 0x11 func 6 - PCI slot 1 */
288 8e00 0 0 1 &mpic 2 1 289 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
289 8e00 0 0 2 &mpic 3 1 290 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
290 8e00 0 0 3 &mpic 4 1 291 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
291 8e00 0 0 4 &mpic 1 1 292 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
292 293
293 /* IDSEL 0x11 func 7 - PCI slot 1 */ 294 /* IDSEL 0x11 func 7 - PCI slot 1 */
294 8f00 0 0 1 &mpic 2 1 295 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
295 8f00 0 0 2 &mpic 3 1 296 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
296 8f00 0 0 3 &mpic 4 1 297 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
297 8f00 0 0 4 &mpic 1 1 298 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
298 299
299 /* IDSEL 0x12 func 0 - PCI slot 2 */ 300 /* IDSEL 0x12 func 0 - PCI slot 2 */
300 9000 0 0 1 &mpic 3 1 301 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
301 9000 0 0 2 &mpic 4 1 302 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
302 9000 0 0 3 &mpic 1 1 303 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
303 9000 0 0 4 &mpic 2 1 304 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
304 305
305 /* IDSEL 0x12 func 1 - PCI slot 2 */ 306 /* IDSEL 0x12 func 1 - PCI slot 2 */
306 9100 0 0 1 &mpic 3 1 307 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
307 9100 0 0 2 &mpic 4 1 308 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
308 9100 0 0 3 &mpic 1 1 309 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
309 9100 0 0 4 &mpic 2 1 310 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
310 311
311 /* IDSEL 0x12 func 2 - PCI slot 2 */ 312 /* IDSEL 0x12 func 2 - PCI slot 2 */
312 9200 0 0 1 &mpic 3 1 313 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
313 9200 0 0 2 &mpic 4 1 314 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
314 9200 0 0 3 &mpic 1 1 315 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
315 9200 0 0 4 &mpic 2 1 316 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
316 317
317 /* IDSEL 0x12 func 3 - PCI slot 2 */ 318 /* IDSEL 0x12 func 3 - PCI slot 2 */
318 9300 0 0 1 &mpic 3 1 319 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
319 9300 0 0 2 &mpic 4 1 320 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
320 9300 0 0 3 &mpic 1 1 321 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
321 9300 0 0 4 &mpic 2 1 322 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
322 323
323 /* IDSEL 0x12 func 4 - PCI slot 2 */ 324 /* IDSEL 0x12 func 4 - PCI slot 2 */
324 9400 0 0 1 &mpic 3 1 325 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
325 9400 0 0 2 &mpic 4 1 326 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
326 9400 0 0 3 &mpic 1 1 327 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
327 9400 0 0 4 &mpic 2 1 328 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
328 329
329 /* IDSEL 0x12 func 5 - PCI slot 2 */ 330 /* IDSEL 0x12 func 5 - PCI slot 2 */
330 9500 0 0 1 &mpic 3 1 331 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
331 9500 0 0 2 &mpic 4 1 332 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
332 9500 0 0 3 &mpic 1 1 333 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
333 9500 0 0 4 &mpic 2 1 334 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
334 335
335 /* IDSEL 0x12 func 6 - PCI slot 2 */ 336 /* IDSEL 0x12 func 6 - PCI slot 2 */
336 9600 0 0 1 &mpic 3 1 337 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
337 9600 0 0 2 &mpic 4 1 338 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
338 9600 0 0 3 &mpic 1 1 339 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
339 9600 0 0 4 &mpic 2 1 340 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
340 341
341 /* IDSEL 0x12 func 7 - PCI slot 2 */ 342 /* IDSEL 0x12 func 7 - PCI slot 2 */
342 9700 0 0 1 &mpic 3 1 343 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
343 9700 0 0 2 &mpic 4 1 344 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
344 9700 0 0 3 &mpic 1 1 345 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
345 9700 0 0 4 &mpic 2 1 346 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
346 347
347 // IDSEL 0x1c USB 348 // IDSEL 0x1c USB
348 e000 0 0 1 &i8259 c 2 349 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
349 e100 0 0 2 &i8259 9 2 350 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
350 e200 0 0 3 &i8259 a 2 351 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
351 e300 0 0 4 &i8259 b 2 352 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
352 353
353 // IDSEL 0x1d Audio 354 // IDSEL 0x1d Audio
354 e800 0 0 1 &i8259 6 2 355 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
355 356
356 // IDSEL 0x1e Legacy 357 // IDSEL 0x1e Legacy
357 f000 0 0 1 &i8259 7 2 358 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
358 f100 0 0 1 &i8259 7 2 359 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
359 360
360 // IDSEL 0x1f IDE/SATA 361 // IDSEL 0x1f IDE/SATA
361 f800 0 0 1 &i8259 e 2 362 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
362 f900 0 0 1 &i8259 5 2 363 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
363 364
364 >; 365 >;
365 366
366 pcie@0 { 367 pcie@0 {
367 reg = <0 0 0 0 0>; 368 reg = <0x0 0x0 0x0 0x0 0x0>;
368 #size-cells = <2>; 369 #size-cells = <2>;
369 #address-cells = <3>; 370 #address-cells = <3>;
370 device_type = "pci"; 371 device_type = "pci";
371 ranges = <02000000 0 80000000 372 ranges = <0x2000000 0x0 0x80000000
372 02000000 0 80000000 373 0x2000000 0x0 0x80000000
373 0 20000000 374 0x0 0x20000000
374 375
375 01000000 0 00000000 376 0x1000000 0x0 0x0
376 01000000 0 00000000 377 0x1000000 0x0 0x0
377 0 00100000>; 378 0x0 0x100000>;
378 uli1575@0 { 379 uli1575@0 {
379 reg = <0 0 0 0 0>; 380 reg = <0x0 0x0 0x0 0x0 0x0>;
380 #size-cells = <2>; 381 #size-cells = <2>;
381 #address-cells = <3>; 382 #address-cells = <3>;
382 ranges = <02000000 0 80000000 383 ranges = <0x2000000 0x0 0x80000000
383 02000000 0 80000000 384 0x2000000 0x0 0x80000000
384 0 20000000 385 0x0 0x20000000
385 386
386 01000000 0 00000000 387 0x1000000 0x0 0x0
387 01000000 0 00000000 388 0x1000000 0x0 0x0
388 0 00100000>; 389 0x0 0x100000>;
389 isa@1e { 390 isa@1e {
390 device_type = "isa"; 391 device_type = "isa";
391 #interrupt-cells = <2>; 392 #interrupt-cells = <2>;
392 #size-cells = <1>; 393 #size-cells = <1>;
393 #address-cells = <2>; 394 #address-cells = <2>;
394 reg = <f000 0 0 0 0>; 395 reg = <0xf000 0x0 0x0 0x0 0x0>;
395 ranges = <1 0 01000000 0 0 396 ranges = <0x1 0x0 0x1000000 0x0 0x0
396 00001000>; 397 0x1000>;
397 interrupt-parent = <&i8259>; 398 interrupt-parent = <&i8259>;
398 399
399 i8259: interrupt-controller@20 { 400 i8259: interrupt-controller@20 {
400 reg = <1 20 2 401 reg = <0x1 0x20 0x2
401 1 a0 2 402 0x1 0xa0 0x2
402 1 4d0 2>; 403 0x1 0x4d0 0x2>;
403 interrupt-controller; 404 interrupt-controller;
404 device_type = "interrupt-controller"; 405 device_type = "interrupt-controller";
405 #address-cells = <0>; 406 #address-cells = <0>;
@@ -412,29 +413,29 @@
412 i8042@60 { 413 i8042@60 {
413 #size-cells = <0>; 414 #size-cells = <0>;
414 #address-cells = <1>; 415 #address-cells = <1>;
415 reg = <1 60 1 1 64 1>; 416 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
416 interrupts = <1 3 c 3>; 417 interrupts = <1 3 12 3>;
417 interrupt-parent = 418 interrupt-parent =
418 <&i8259>; 419 <&i8259>;
419 420
420 keyboard@0 { 421 keyboard@0 {
421 reg = <0>; 422 reg = <0x0>;
422 compatible = "pnpPNP,303"; 423 compatible = "pnpPNP,303";
423 }; 424 };
424 425
425 mouse@1 { 426 mouse@1 {
426 reg = <1>; 427 reg = <0x1>;
427 compatible = "pnpPNP,f03"; 428 compatible = "pnpPNP,f03";
428 }; 429 };
429 }; 430 };
430 431
431 rtc@70 { 432 rtc@70 {
432 compatible = "pnpPNP,b00"; 433 compatible = "pnpPNP,b00";
433 reg = <1 70 2>; 434 reg = <0x1 0x70 0x2>;
434 }; 435 };
435 436
436 gpio@400 { 437 gpio@400 {
437 reg = <1 400 80>; 438 reg = <0x1 0x400 0x80>;
438 }; 439 };
439 }; 440 };
440 }; 441 };
@@ -449,33 +450,33 @@
449 #interrupt-cells = <1>; 450 #interrupt-cells = <1>;
450 #size-cells = <2>; 451 #size-cells = <2>;
451 #address-cells = <3>; 452 #address-cells = <3>;
452 reg = <ffe09000 1000>; 453 reg = <0xffe09000 0x1000>;
453 bus-range = <0 ff>; 454 bus-range = <0 255>;
454 ranges = <02000000 0 a0000000 a0000000 0 20000000 455 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
455 01000000 0 00000000 ffc10000 0 00010000>; 456 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
456 clock-frequency = <1fca055>; 457 clock-frequency = <33333333>;
457 interrupt-parent = <&mpic>; 458 interrupt-parent = <&mpic>;
458 interrupts = <1a 2>; 459 interrupts = <26 2>;
459 interrupt-map-mask = <f800 0 0 7>; 460 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
460 interrupt-map = < 461 interrupt-map = <
461 /* IDSEL 0x0 */ 462 /* IDSEL 0x0 */
462 0000 0 0 1 &mpic 4 1 463 0000 0x0 0x0 0x1 &mpic 0x4 0x1
463 0000 0 0 2 &mpic 5 1 464 0000 0x0 0x0 0x2 &mpic 0x5 0x1
464 0000 0 0 3 &mpic 6 1 465 0000 0x0 0x0 0x3 &mpic 0x6 0x1
465 0000 0 0 4 &mpic 7 1 466 0000 0x0 0x0 0x4 &mpic 0x7 0x1
466 >; 467 >;
467 pcie@0 { 468 pcie@0 {
468 reg = <0 0 0 0 0>; 469 reg = <0x0 0x0 0x0 0x0 0x0>;
469 #size-cells = <2>; 470 #size-cells = <2>;
470 #address-cells = <3>; 471 #address-cells = <3>;
471 device_type = "pci"; 472 device_type = "pci";
472 ranges = <02000000 0 a0000000 473 ranges = <0x2000000 0x0 0xa0000000
473 02000000 0 a0000000 474 0x2000000 0x0 0xa0000000
474 0 20000000 475 0x0 0x20000000
475 476
476 01000000 0 00000000 477 0x1000000 0x0 0x0
477 01000000 0 00000000 478 0x1000000 0x0 0x0
478 0 00100000>; 479 0x0 0x100000>;
479 }; 480 };
480 }; 481 };
481 482
@@ -486,33 +487,33 @@
486 #interrupt-cells = <1>; 487 #interrupt-cells = <1>;
487 #size-cells = <2>; 488 #size-cells = <2>;
488 #address-cells = <3>; 489 #address-cells = <3>;
489 reg = <ffe0a000 1000>; 490 reg = <0xffe0a000 0x1000>;
490 bus-range = <0 ff>; 491 bus-range = <0 255>;
491 ranges = <02000000 0 c0000000 c0000000 0 20000000 492 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
492 01000000 0 00000000 ffc20000 0 00010000>; 493 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
493 clock-frequency = <1fca055>; 494 clock-frequency = <33333333>;
494 interrupt-parent = <&mpic>; 495 interrupt-parent = <&mpic>;
495 interrupts = <1b 2>; 496 interrupts = <27 2>;
496 interrupt-map-mask = <f800 0 0 7>; 497 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
497 interrupt-map = < 498 interrupt-map = <
498 /* IDSEL 0x0 */ 499 /* IDSEL 0x0 */
499 0000 0 0 1 &mpic 0 1 500 0000 0x0 0x0 0x1 &mpic 0x0 0x1
500 0000 0 0 2 &mpic 1 1 501 0000 0x0 0x0 0x2 &mpic 0x1 0x1
501 0000 0 0 3 &mpic 2 1 502 0000 0x0 0x0 0x3 &mpic 0x2 0x1
502 0000 0 0 4 &mpic 3 1 503 0000 0x0 0x0 0x4 &mpic 0x3 0x1
503 >; 504 >;
504 pcie@0 { 505 pcie@0 {
505 reg = <0 0 0 0 0>; 506 reg = <0x0 0x0 0x0 0x0 0x0>;
506 #size-cells = <2>; 507 #size-cells = <2>;
507 #address-cells = <3>; 508 #address-cells = <3>;
508 device_type = "pci"; 509 device_type = "pci";
509 ranges = <02000000 0 c0000000 510 ranges = <0x2000000 0x0 0xc0000000
510 02000000 0 c0000000 511 0x2000000 0x0 0xc0000000
511 0 20000000 512 0x0 0x20000000
512 513
513 01000000 0 00000000 514 0x1000000 0x0 0x0
514 01000000 0 00000000 515 0x1000000 0x0 0x0
515 0 00100000>; 516 0x0 0x100000>;
516 }; 517 };
517 }; 518 };
518}; 519};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 10:33:57 -0500