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authorPaul Mackerras <paulus@samba.org>2005-10-20 07:06:44 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-20 07:06:44 -0400
commitd85b525e6e1d0886eebd1d4c4f954d9d2f226a63 (patch)
treedd36c3369323d53aaa026530fe038d90b5626e16 /arch
parent374e99d450a0c44dc30041fa83eccfd0890330c7 (diff)
ppc64: Use the merged mpic.c
This means we now compile in arch/powerpc/sysdev for ARCH=ppc64. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/ppc64/Makefile1
-rw-r--r--arch/ppc64/kernel/Makefile3
-rw-r--r--arch/ppc64/kernel/mpic.c887
3 files changed, 2 insertions, 889 deletions
diff --git a/arch/ppc64/Makefile b/arch/ppc64/Makefile
index 4a9928ef3032..4d18bdb680f0 100644
--- a/arch/ppc64/Makefile
+++ b/arch/ppc64/Makefile
@@ -84,6 +84,7 @@ head-y := arch/ppc64/kernel/head.o
84libs-y += arch/ppc64/lib/ 84libs-y += arch/ppc64/lib/
85core-y += arch/ppc64/kernel/ arch/powerpc/kernel/ 85core-y += arch/ppc64/kernel/ arch/powerpc/kernel/
86core-y += arch/powerpc/mm/ 86core-y += arch/powerpc/mm/
87core-y += arch/powerpc/sysdev/
87core-y += arch/powerpc/platforms/ 88core-y += arch/powerpc/platforms/
88core-$(CONFIG_XMON) += arch/ppc64/xmon/ 89core-$(CONFIG_XMON) += arch/ppc64/xmon/
89drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/ 90drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/
diff --git a/arch/ppc64/kernel/Makefile b/arch/ppc64/kernel/Makefile
index 6cce419f4b09..6c02a79955c7 100644
--- a/arch/ppc64/kernel/Makefile
+++ b/arch/ppc64/kernel/Makefile
@@ -55,9 +55,8 @@ obj-$(CONFIG_HVCS) += hvcserver.o
55 55
56obj-$(CONFIG_IBMVIO) += vio.o 56obj-$(CONFIG_IBMVIO) += vio.o
57obj-$(CONFIG_XICS) += xics.o 57obj-$(CONFIG_XICS) += xics.o
58ifneq ($(CONFIG_PPC_MERGE),y)
59obj-$(CONFIG_MPIC) += mpic.o
60 58
59ifneq ($(CONFIG_PPC_MERGE),y)
61obj-$(CONFIG_PPC_PMAC) += pmac_setup.o pmac_feature.o pmac_pci.o \ 60obj-$(CONFIG_PPC_PMAC) += pmac_setup.o pmac_feature.o pmac_pci.o \
62 pmac_time.o pmac_nvram.o pmac_low_i2c.o \ 61 pmac_time.o pmac_nvram.o pmac_low_i2c.o \
63 udbg_scc.o 62 udbg_scc.o
diff --git a/arch/ppc64/kernel/mpic.c b/arch/ppc64/kernel/mpic.c
deleted file mode 100644
index ec22321342ad..000000000000
--- a/arch/ppc64/kernel/mpic.c
+++ /dev/null
@@ -1,887 +0,0 @@
1/*
2 * arch/ppc64/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15#undef DEBUG
16
17#include <linux/config.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/smp.h>
23#include <linux/interrupt.h>
24#include <linux/bootmem.h>
25#include <linux/spinlock.h>
26#include <linux/pci.h>
27
28#include <asm/ptrace.h>
29#include <asm/signal.h>
30#include <asm/io.h>
31#include <asm/pgtable.h>
32#include <asm/irq.h>
33#include <asm/machdep.h>
34#include <asm/mpic.h>
35
36#ifdef DEBUG
37#define DBG(fmt...) printk(fmt)
38#else
39#define DBG(fmt...)
40#endif
41
42static struct mpic *mpics;
43static struct mpic *mpic_primary;
44static DEFINE_SPINLOCK(mpic_lock);
45
46
47/*
48 * Register accessor functions
49 */
50
51
52static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
53 unsigned int reg)
54{
55 if (be)
56 return in_be32(base + (reg >> 2));
57 else
58 return in_le32(base + (reg >> 2));
59}
60
61static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
62 unsigned int reg, u32 value)
63{
64 if (be)
65 out_be32(base + (reg >> 2), value);
66 else
67 out_le32(base + (reg >> 2), value);
68}
69
70static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
71{
72 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
73 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
74
75 if (mpic->flags & MPIC_BROKEN_IPI)
76 be = !be;
77 return _mpic_read(be, mpic->gregs, offset);
78}
79
80static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
81{
82 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
83
84 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
85}
86
87static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
88{
89 unsigned int cpu = 0;
90
91 if (mpic->flags & MPIC_PRIMARY)
92 cpu = hard_smp_processor_id();
93
94 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg);
95}
96
97static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
98{
99 unsigned int cpu = 0;
100
101 if (mpic->flags & MPIC_PRIMARY)
102 cpu = hard_smp_processor_id();
103
104 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
105}
106
107static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
108{
109 unsigned int isu = src_no >> mpic->isu_shift;
110 unsigned int idx = src_no & mpic->isu_mask;
111
112 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
113 reg + (idx * MPIC_IRQ_STRIDE));
114}
115
116static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
117 unsigned int reg, u32 value)
118{
119 unsigned int isu = src_no >> mpic->isu_shift;
120 unsigned int idx = src_no & mpic->isu_mask;
121
122 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE), value);
124}
125
126#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
127#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
128#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
129#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
130#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
131#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
132#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
133#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
134
135
136/*
137 * Low level utility functions
138 */
139
140
141
142/* Check if we have one of those nice broken MPICs with a flipped endian on
143 * reads from IPI registers
144 */
145static void __init mpic_test_broken_ipi(struct mpic *mpic)
146{
147 u32 r;
148
149 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
150 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
151
152 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
153 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
154 mpic->flags |= MPIC_BROKEN_IPI;
155 }
156}
157
158#ifdef CONFIG_MPIC_BROKEN_U3
159
160/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
161 * to force the edge setting on the MPIC and do the ack workaround.
162 */
163static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no)
164{
165 if (source_no >= 128 || !mpic->fixups)
166 return 0;
167 return mpic->fixups[source_no].base != NULL;
168}
169
170static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
171{
172 struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
173 u32 tmp;
174
175 spin_lock(&mpic->fixup_lock);
176 writeb(0x11 + 2 * fixup->irq, fixup->base);
177 tmp = readl(fixup->base + 2);
178 writel(tmp | 0x80000000ul, fixup->base + 2);
179 /* config writes shouldn't be posted but let's be safe ... */
180 (void)readl(fixup->base + 2);
181 spin_unlock(&mpic->fixup_lock);
182}
183
184
185static void __init mpic_amd8111_read_irq(struct mpic *mpic, u8 __iomem *devbase)
186{
187 int i, irq;
188 u32 tmp;
189
190 printk(KERN_INFO "mpic: - Workarounds on AMD 8111 @ %p\n", devbase);
191
192 for (i=0; i < 24; i++) {
193 writeb(0x10 + 2*i, devbase + 0xf2);
194 tmp = readl(devbase + 0xf4);
195 if ((tmp & 0x1) || !(tmp & 0x20))
196 continue;
197 irq = (tmp >> 16) & 0xff;
198 mpic->fixups[irq].irq = i;
199 mpic->fixups[irq].base = devbase + 0xf2;
200 }
201}
202
203static void __init mpic_amd8131_read_irq(struct mpic *mpic, u8 __iomem *devbase)
204{
205 int i, irq;
206 u32 tmp;
207
208 printk(KERN_INFO "mpic: - Workarounds on AMD 8131 @ %p\n", devbase);
209
210 for (i=0; i < 4; i++) {
211 writeb(0x10 + 2*i, devbase + 0xba);
212 tmp = readl(devbase + 0xbc);
213 if ((tmp & 0x1) || !(tmp & 0x20))
214 continue;
215 irq = (tmp >> 16) & 0xff;
216 mpic->fixups[irq].irq = i;
217 mpic->fixups[irq].base = devbase + 0xba;
218 }
219}
220
221static void __init mpic_scan_ioapics(struct mpic *mpic)
222{
223 unsigned int devfn;
224 u8 __iomem *cfgspace;
225
226 printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n");
227
228 /* Allocate fixups array */
229 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
230 BUG_ON(mpic->fixups == NULL);
231 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
232
233 /* Init spinlock */
234 spin_lock_init(&mpic->fixup_lock);
235
236 /* Map u3 config space. We assume all IO-APICs are on the primary bus
237 * and slot will never be above "0xf" so we only need to map 32k
238 */
239 cfgspace = (unsigned char __iomem *)ioremap(0xf2000000, 0x8000);
240 BUG_ON(cfgspace == NULL);
241
242 /* Now we scan all slots. We do a very quick scan, we read the header type,
243 * vendor ID and device ID only, that's plenty enough
244 */
245 for (devfn = 0; devfn < PCI_DEVFN(0x10,0); devfn ++) {
246 u8 __iomem *devbase = cfgspace + (devfn << 8);
247 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
248 u32 l = readl(devbase + PCI_VENDOR_ID);
249 u16 vendor_id, device_id;
250 int multifunc = 0;
251
252 DBG("devfn %x, l: %x\n", devfn, l);
253
254 /* If no device, skip */
255 if (l == 0xffffffff || l == 0x00000000 ||
256 l == 0x0000ffff || l == 0xffff0000)
257 goto next;
258
259 /* Check if it's a multifunction device (only really used
260 * to function 0 though
261 */
262 multifunc = !!(hdr_type & 0x80);
263 vendor_id = l & 0xffff;
264 device_id = (l >> 16) & 0xffff;
265
266 /* If a known device, go to fixup setup code */
267 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7460)
268 mpic_amd8111_read_irq(mpic, devbase);
269 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7450)
270 mpic_amd8131_read_irq(mpic, devbase);
271 next:
272 /* next device, if function 0 */
273 if ((PCI_FUNC(devfn) == 0) && !multifunc)
274 devfn += 7;
275 }
276}
277
278#endif /* CONFIG_MPIC_BROKEN_U3 */
279
280
281/* Find an mpic associated with a given linux interrupt */
282static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
283{
284 struct mpic *mpic = mpics;
285
286 while(mpic) {
287 /* search IPIs first since they may override the main interrupts */
288 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
289 if (is_ipi)
290 *is_ipi = 1;
291 return mpic;
292 }
293 if (irq >= mpic->irq_offset &&
294 irq < (mpic->irq_offset + mpic->irq_count)) {
295 if (is_ipi)
296 *is_ipi = 0;
297 return mpic;
298 }
299 mpic = mpic -> next;
300 }
301 return NULL;
302}
303
304/* Convert a cpu mask from logical to physical cpu numbers. */
305static inline u32 mpic_physmask(u32 cpumask)
306{
307 int i;
308 u32 mask = 0;
309
310 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
311 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
312 return mask;
313}
314
315#ifdef CONFIG_SMP
316/* Get the mpic structure from the IPI number */
317static inline struct mpic * mpic_from_ipi(unsigned int ipi)
318{
319 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
320}
321#endif
322
323/* Get the mpic structure from the irq number */
324static inline struct mpic * mpic_from_irq(unsigned int irq)
325{
326 return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
327}
328
329/* Send an EOI */
330static inline void mpic_eoi(struct mpic *mpic)
331{
332 mpic_cpu_write(MPIC_CPU_EOI, 0);
333 (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
334}
335
336#ifdef CONFIG_SMP
337static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
338{
339 struct mpic *mpic = dev_id;
340
341 smp_message_recv(irq - mpic->ipi_offset, regs);
342 return IRQ_HANDLED;
343}
344#endif /* CONFIG_SMP */
345
346/*
347 * Linux descriptor level callbacks
348 */
349
350
351static void mpic_enable_irq(unsigned int irq)
352{
353 unsigned int loops = 100000;
354 struct mpic *mpic = mpic_from_irq(irq);
355 unsigned int src = irq - mpic->irq_offset;
356
357 DBG("%s: enable_irq: %d (src %d)\n", mpic->name, irq, src);
358
359 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
360 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & ~MPIC_VECPRI_MASK);
361
362 /* make sure mask gets to controller before we return to user */
363 do {
364 if (!loops--) {
365 printk(KERN_ERR "mpic_enable_irq timeout\n");
366 break;
367 }
368 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
369}
370
371static void mpic_disable_irq(unsigned int irq)
372{
373 unsigned int loops = 100000;
374 struct mpic *mpic = mpic_from_irq(irq);
375 unsigned int src = irq - mpic->irq_offset;
376
377 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
378
379 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
380 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | MPIC_VECPRI_MASK);
381
382 /* make sure mask gets to controller before we return to user */
383 do {
384 if (!loops--) {
385 printk(KERN_ERR "mpic_enable_irq timeout\n");
386 break;
387 }
388 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
389}
390
391static void mpic_end_irq(unsigned int irq)
392{
393 struct mpic *mpic = mpic_from_irq(irq);
394
395 DBG("%s: end_irq: %d\n", mpic->name, irq);
396
397 /* We always EOI on end_irq() even for edge interrupts since that
398 * should only lower the priority, the MPIC should have properly
399 * latched another edge interrupt coming in anyway
400 */
401
402#ifdef CONFIG_MPIC_BROKEN_U3
403 if (mpic->flags & MPIC_BROKEN_U3) {
404 unsigned int src = irq - mpic->irq_offset;
405 if (mpic_is_ht_interrupt(mpic, src))
406 mpic_apic_end_irq(mpic, src);
407 }
408#endif /* CONFIG_MPIC_BROKEN_U3 */
409
410 mpic_eoi(mpic);
411}
412
413#ifdef CONFIG_SMP
414
415static void mpic_enable_ipi(unsigned int irq)
416{
417 struct mpic *mpic = mpic_from_ipi(irq);
418 unsigned int src = irq - mpic->ipi_offset;
419
420 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
421 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
422}
423
424static void mpic_disable_ipi(unsigned int irq)
425{
426 /* NEVER disable an IPI... that's just plain wrong! */
427}
428
429static void mpic_end_ipi(unsigned int irq)
430{
431 struct mpic *mpic = mpic_from_ipi(irq);
432
433 /*
434 * IPIs are marked IRQ_PER_CPU. This has the side effect of
435 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
436 * applying to them. We EOI them late to avoid re-entering.
437 * We mark IPI's with SA_INTERRUPT as they must run with
438 * irqs disabled.
439 */
440 mpic_eoi(mpic);
441}
442
443#endif /* CONFIG_SMP */
444
445static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
446{
447 struct mpic *mpic = mpic_from_irq(irq);
448
449 cpumask_t tmp;
450
451 cpus_and(tmp, cpumask, cpu_online_map);
452
453 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
454 mpic_physmask(cpus_addr(tmp)[0]));
455}
456
457
458/*
459 * Exported functions
460 */
461
462
463struct mpic * __init mpic_alloc(unsigned long phys_addr,
464 unsigned int flags,
465 unsigned int isu_size,
466 unsigned int irq_offset,
467 unsigned int irq_count,
468 unsigned int ipi_offset,
469 unsigned char *senses,
470 unsigned int senses_count,
471 const char *name)
472{
473 struct mpic *mpic;
474 u32 reg;
475 const char *vers;
476 int i;
477
478 mpic = alloc_bootmem(sizeof(struct mpic));
479 if (mpic == NULL)
480 return NULL;
481
482 memset(mpic, 0, sizeof(struct mpic));
483 mpic->name = name;
484
485 mpic->hc_irq.typename = name;
486 mpic->hc_irq.enable = mpic_enable_irq;
487 mpic->hc_irq.disable = mpic_disable_irq;
488 mpic->hc_irq.end = mpic_end_irq;
489 if (flags & MPIC_PRIMARY)
490 mpic->hc_irq.set_affinity = mpic_set_affinity;
491#ifdef CONFIG_SMP
492 mpic->hc_ipi.typename = name;
493 mpic->hc_ipi.enable = mpic_enable_ipi;
494 mpic->hc_ipi.disable = mpic_disable_ipi;
495 mpic->hc_ipi.end = mpic_end_ipi;
496#endif /* CONFIG_SMP */
497
498 mpic->flags = flags;
499 mpic->isu_size = isu_size;
500 mpic->irq_offset = irq_offset;
501 mpic->irq_count = irq_count;
502 mpic->ipi_offset = ipi_offset;
503 mpic->num_sources = 0; /* so far */
504 mpic->senses = senses;
505 mpic->senses_count = senses_count;
506
507 /* Map the global registers */
508 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
509 mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2);
510 BUG_ON(mpic->gregs == NULL);
511
512 /* Reset */
513 if (flags & MPIC_WANTS_RESET) {
514 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
515 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
516 | MPIC_GREG_GCONF_RESET);
517 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
518 & MPIC_GREG_GCONF_RESET)
519 mb();
520 }
521
522 /* Read feature register, calculate num CPUs and, for non-ISU
523 * MPICs, num sources as well. On ISU MPICs, sources are counted
524 * as ISUs are added
525 */
526 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
527 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
528 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
529 if (isu_size == 0)
530 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
531 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
532
533 /* Map the per-CPU registers */
534 for (i = 0; i < mpic->num_cpus; i++) {
535 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
536 i * MPIC_CPU_STRIDE, 0x1000);
537 BUG_ON(mpic->cpuregs[i] == NULL);
538 }
539
540 /* Initialize main ISU if none provided */
541 if (mpic->isu_size == 0) {
542 mpic->isu_size = mpic->num_sources;
543 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
544 MPIC_IRQ_STRIDE * mpic->isu_size);
545 BUG_ON(mpic->isus[0] == NULL);
546 }
547 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
548 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
549
550 /* Display version */
551 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
552 case 1:
553 vers = "1.0";
554 break;
555 case 2:
556 vers = "1.2";
557 break;
558 case 3:
559 vers = "1.3";
560 break;
561 default:
562 vers = "<unknown>";
563 break;
564 }
565 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
566 name, vers, phys_addr, mpic->num_cpus);
567 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
568 mpic->isu_shift, mpic->isu_mask);
569
570 mpic->next = mpics;
571 mpics = mpic;
572
573 if (flags & MPIC_PRIMARY)
574 mpic_primary = mpic;
575
576 return mpic;
577}
578
579void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
580 unsigned long phys_addr)
581{
582 unsigned int isu_first = isu_num * mpic->isu_size;
583
584 BUG_ON(isu_num >= MPIC_MAX_ISU);
585
586 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
587 if ((isu_first + mpic->isu_size) > mpic->num_sources)
588 mpic->num_sources = isu_first + mpic->isu_size;
589}
590
591void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler,
592 void *data)
593{
594 struct mpic *mpic = mpic_find(irq, NULL);
595 unsigned long flags;
596
597 /* Synchronization here is a bit dodgy, so don't try to replace cascade
598 * interrupts on the fly too often ... but normally it's set up at boot.
599 */
600 spin_lock_irqsave(&mpic_lock, flags);
601 if (mpic->cascade)
602 mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset);
603 mpic->cascade = NULL;
604 wmb();
605 mpic->cascade_vec = irq - mpic->irq_offset;
606 mpic->cascade_data = data;
607 wmb();
608 mpic->cascade = handler;
609 mpic_enable_irq(irq);
610 spin_unlock_irqrestore(&mpic_lock, flags);
611}
612
613void __init mpic_init(struct mpic *mpic)
614{
615 int i;
616
617 BUG_ON(mpic->num_sources == 0);
618
619 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
620
621 /* Set current processor priority to max */
622 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
623
624 /* Initialize timers: just disable them all */
625 for (i = 0; i < 4; i++) {
626 mpic_write(mpic->tmregs,
627 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
628 mpic_write(mpic->tmregs,
629 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
630 MPIC_VECPRI_MASK |
631 (MPIC_VEC_TIMER_0 + i));
632 }
633
634 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
635 mpic_test_broken_ipi(mpic);
636 for (i = 0; i < 4; i++) {
637 mpic_ipi_write(i,
638 MPIC_VECPRI_MASK |
639 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
640 (MPIC_VEC_IPI_0 + i));
641#ifdef CONFIG_SMP
642 if (!(mpic->flags & MPIC_PRIMARY))
643 continue;
644 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
645 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
646
647#endif /* CONFIG_SMP */
648 }
649
650 /* Initialize interrupt sources */
651 if (mpic->irq_count == 0)
652 mpic->irq_count = mpic->num_sources;
653
654#ifdef CONFIG_MPIC_BROKEN_U3
655 /* Do the ioapic fixups on U3 broken mpic */
656 DBG("MPIC flags: %x\n", mpic->flags);
657 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
658 mpic_scan_ioapics(mpic);
659#endif /* CONFIG_MPIC_BROKEN_U3 */
660
661 for (i = 0; i < mpic->num_sources; i++) {
662 /* start with vector = source number, and masked */
663 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
664 int level = 0;
665
666 /* if it's an IPI, we skip it */
667 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
668 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
669 continue;
670
671 /* do senses munging */
672 if (mpic->senses && i < mpic->senses_count) {
673 if (mpic->senses[i] & IRQ_SENSE_LEVEL)
674 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
675 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
676 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
677 } else
678 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
679
680 /* remember if it was a level interrupts */
681 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
682
683 /* deal with broken U3 */
684 if (mpic->flags & MPIC_BROKEN_U3) {
685#ifdef CONFIG_MPIC_BROKEN_U3
686 if (mpic_is_ht_interrupt(mpic, i)) {
687 vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
688 MPIC_VECPRI_POLARITY_MASK);
689 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
690 }
691#else
692 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
693#endif
694 }
695
696 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
697 (level != 0));
698
699 /* init hw */
700 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
701 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
702 1 << get_hard_smp_processor_id(boot_cpuid));
703
704 /* init linux descriptors */
705 if (i < mpic->irq_count) {
706 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
707 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
708 }
709 }
710
711 /* Init spurrious vector */
712 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
713
714 /* Disable 8259 passthrough */
715 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
716 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
717 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
718
719 /* Set current processor priority to 0 */
720 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
721}
722
723
724
725void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
726{
727 int is_ipi;
728 struct mpic *mpic = mpic_find(irq, &is_ipi);
729 unsigned long flags;
730 u32 reg;
731
732 spin_lock_irqsave(&mpic_lock, flags);
733 if (is_ipi) {
734 reg = mpic_ipi_read(irq - mpic->ipi_offset) & MPIC_VECPRI_PRIORITY_MASK;
735 mpic_ipi_write(irq - mpic->ipi_offset,
736 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
737 } else {
738 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI)
739 & MPIC_VECPRI_PRIORITY_MASK;
740 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
741 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
742 }
743 spin_unlock_irqrestore(&mpic_lock, flags);
744}
745
746unsigned int mpic_irq_get_priority(unsigned int irq)
747{
748 int is_ipi;
749 struct mpic *mpic = mpic_find(irq, &is_ipi);
750 unsigned long flags;
751 u32 reg;
752
753 spin_lock_irqsave(&mpic_lock, flags);
754 if (is_ipi)
755 reg = mpic_ipi_read(irq - mpic->ipi_offset);
756 else
757 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
758 spin_unlock_irqrestore(&mpic_lock, flags);
759 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
760}
761
762void mpic_setup_this_cpu(void)
763{
764#ifdef CONFIG_SMP
765 struct mpic *mpic = mpic_primary;
766 unsigned long flags;
767 u32 msk = 1 << hard_smp_processor_id();
768 unsigned int i;
769
770 BUG_ON(mpic == NULL);
771
772 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
773
774 spin_lock_irqsave(&mpic_lock, flags);
775
776 /* let the mpic know we want intrs. default affinity is 0xffffffff
777 * until changed via /proc. That's how it's done on x86. If we want
778 * it differently, then we should make sure we also change the default
779 * values of irq_affinity in irq.c.
780 */
781 if (distribute_irqs) {
782 for (i = 0; i < mpic->num_sources ; i++)
783 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
784 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
785 }
786
787 /* Set current processor priority to 0 */
788 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
789
790 spin_unlock_irqrestore(&mpic_lock, flags);
791#endif /* CONFIG_SMP */
792}
793
794/*
795 * XXX: someone who knows mpic should check this.
796 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
797 * or can we reset the mpic in the new kernel?
798 */
799void mpic_teardown_this_cpu(int secondary)
800{
801 struct mpic *mpic = mpic_primary;
802 unsigned long flags;
803 u32 msk = 1 << hard_smp_processor_id();
804 unsigned int i;
805
806 BUG_ON(mpic == NULL);
807
808 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
809 spin_lock_irqsave(&mpic_lock, flags);
810
811 /* let the mpic know we don't want intrs. */
812 for (i = 0; i < mpic->num_sources ; i++)
813 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
814 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
815
816 /* Set current processor priority to max */
817 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
818
819 spin_unlock_irqrestore(&mpic_lock, flags);
820}
821
822
823void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
824{
825 struct mpic *mpic = mpic_primary;
826
827 BUG_ON(mpic == NULL);
828
829 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
830
831 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
832 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
833}
834
835int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
836{
837 u32 irq;
838
839 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
840 DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
841
842 if (mpic->cascade && irq == mpic->cascade_vec) {
843 DBG("%s: cascading ...\n", mpic->name);
844 irq = mpic->cascade(regs, mpic->cascade_data);
845 mpic_eoi(mpic);
846 return irq;
847 }
848 if (unlikely(irq == MPIC_VEC_SPURRIOUS))
849 return -1;
850 if (irq < MPIC_VEC_IPI_0)
851 return irq + mpic->irq_offset;
852 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
853 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
854}
855
856int mpic_get_irq(struct pt_regs *regs)
857{
858 struct mpic *mpic = mpic_primary;
859
860 BUG_ON(mpic == NULL);
861
862 return mpic_get_one_irq(mpic, regs);
863}
864
865
866#ifdef CONFIG_SMP
867void mpic_request_ipis(void)
868{
869 struct mpic *mpic = mpic_primary;
870
871 BUG_ON(mpic == NULL);
872
873 printk("requesting IPIs ... \n");
874
875 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
876 request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT,
877 "IPI0 (call function)", mpic);
878 request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT,
879 "IPI1 (reschedule)", mpic);
880 request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT,
881 "IPI2 (unused)", mpic);
882 request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT,
883 "IPI3 (debugger break)", mpic);
884
885 printk("IPIs requested... \n");
886}
887#endif /* CONFIG_SMP */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 12:11:41 -0500