sh: Move alias computation to shared cache init.

This migrates the alias computation and printing of probed cache
parameters from the SH-4 code to the shared cpu_cache_init().

This permits other platforms with aliases to make use of the same
probe logic without having to roll their own, and also produces
consistent output regardless of platform.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 51 insertions, 53 deletions

diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index df2eb87f1524..4ac844b1432f 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -44,61 +44,15 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
 static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
         (void (*)(unsigned long, unsigned long))0xdeadbeef;
 
-static void compute_alias(struct cache_info *c)
-{
-        c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
-        c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
-}
-
-static void __init emit_cache_params(void)
-{
-        printk("PVR=%08x CVR=%08x PRR=%08x\n",
-                ctrl_inl(CCN_PVR),
-                ctrl_inl(CCN_CVR),
-                ctrl_inl(CCN_PRR));
-        printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
-                boot_cpu_data.icache.ways,
-                boot_cpu_data.icache.sets,
-                boot_cpu_data.icache.way_incr);
-        printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
-                boot_cpu_data.icache.entry_mask,
-                boot_cpu_data.icache.alias_mask,
-                boot_cpu_data.icache.n_aliases);
-        printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
-                boot_cpu_data.dcache.ways,
-                boot_cpu_data.dcache.sets,
-                boot_cpu_data.dcache.way_incr);
-        printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
-                boot_cpu_data.dcache.entry_mask,
-                boot_cpu_data.dcache.alias_mask,
-                boot_cpu_data.dcache.n_aliases);
-
-        /*
-         * Emit Secondary Cache parameters if the CPU has a probed L2.
-         */
-        if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
-                printk("S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
-                        boot_cpu_data.scache.ways,
-                        boot_cpu_data.scache.sets,
-                        boot_cpu_data.scache.way_incr);
-                printk("S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
-                        boot_cpu_data.scache.entry_mask,
-                        boot_cpu_data.scache.alias_mask,
-                        boot_cpu_data.scache.n_aliases);
-        }
-
-        if (!__flush_dcache_segment_fn)
-                panic("unknown number of cache ways\n");
-}
-
 /*
  * SH-4 has virtually indexed and physically tagged cache.
  */
 void __init sh4_cache_init(void)
 {
-        compute_alias(&boot_cpu_data.icache);
-        compute_alias(&boot_cpu_data.dcache);
-        compute_alias(&boot_cpu_data.scache);
+        printk("PVR=%08x CVR=%08x PRR=%08x\n",
+                ctrl_inl(CCN_PVR),
+                ctrl_inl(CCN_CVR),
+                ctrl_inl(CCN_PRR));
 
         switch (boot_cpu_data.dcache.ways) {
         case 1:
@@ -111,11 +65,9 @@ void __init sh4_cache_init(void)
                 __flush_dcache_segment_fn = __flush_dcache_segment_4way;
                 break;
         default:
-                __flush_dcache_segment_fn = NULL;
+                panic("unknown number of cache ways\n");
                 break;
         }
-
-        emit_cache_params();
 }
 
 /*
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 659981ffae24..a31e5c46e7a6 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -128,8 +128,52 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
         }
 }
 
+static void compute_alias(struct cache_info *c)
+{
+        c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
+        c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
+}
+
+static void __init emit_cache_params(void)
+{
+        printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
+                boot_cpu_data.icache.ways,
+                boot_cpu_data.icache.sets,
+                boot_cpu_data.icache.way_incr);
+        printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
+                boot_cpu_data.icache.entry_mask,
+                boot_cpu_data.icache.alias_mask,
+                boot_cpu_data.icache.n_aliases);
+        printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
+                boot_cpu_data.dcache.ways,
+                boot_cpu_data.dcache.sets,
+                boot_cpu_data.dcache.way_incr);
+        printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
+                boot_cpu_data.dcache.entry_mask,
+                boot_cpu_data.dcache.alias_mask,
+                boot_cpu_data.dcache.n_aliases);
+
+        /*
+         * Emit Secondary Cache parameters if the CPU has a probed L2.
+         */
+        if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+                printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
+                        boot_cpu_data.scache.ways,
+                        boot_cpu_data.scache.sets,
+                        boot_cpu_data.scache.way_incr);
+                printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
+                        boot_cpu_data.scache.entry_mask,
+                        boot_cpu_data.scache.alias_mask,
+                        boot_cpu_data.scache.n_aliases);
+        }
+}
+
 void __init cpu_cache_init(void)
 {
+        compute_alias(&boot_cpu_data.icache);
+        compute_alias(&boot_cpu_data.dcache);
+        compute_alias(&boot_cpu_data.scache);
+
         if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
             (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
             (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
@@ -137,4 +181,6 @@ void __init cpu_cache_init(void)
 
                 sh4_cache_init();
         }
+
+        emit_cache_params();
 }