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authorSteven J. Hill <Steven.Hill@imgtec.com>2013-04-10 17:27:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-05-09 11:55:20 -0400
commitff86714fda0310ad153a2ba4836067f195e1f0b9 (patch)
tree62b59fd6a48dca9b07d29cfa42d5a0afd080d030 /arch
parent451b001b05551a2bf9ec4c2293f20e34a4520701 (diff)
MIPS: Move 'gic_present' to common location.
Move the global variable 'gic_present' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/gic.h2
-rw-r--r--arch/mips/kernel/irq-gic.c1
-rw-r--r--arch/mips/kernel/smp-mt.c3
-rw-r--r--arch/mips/mti-malta/malta-int.c1
-rw-r--r--arch/mips/mti-sead3/sead3-int.c1
5 files changed, 3 insertions, 5 deletions
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index bdc9786ab5a7..a05f97db0735 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -359,7 +359,7 @@ struct gic_shared_intr_map {
359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
360#define GIC_PIN_TO_VEC_OFFSET (1) 360#define GIC_PIN_TO_VEC_OFFSET (1)
361 361
362extern int gic_present; 362extern unsigned int gic_present;
363extern unsigned long _gic_base; 363extern unsigned long _gic_base;
364extern unsigned int gic_irq_base; 364extern unsigned int gic_irq_base;
365extern unsigned int gic_irq_flags[]; 365extern unsigned int gic_irq_flags[];
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 485e6a961b31..130aec6f0644 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -19,6 +19,7 @@
19#include <linux/hardirq.h> 19#include <linux/hardirq.h>
20#include <asm-generic/bitops/find.h> 20#include <asm-generic/bitops/find.h>
21 21
22unsigned int gic_present;
22unsigned long _gic_base; 23unsigned long _gic_base;
23unsigned int gic_irq_base; 24unsigned int gic_irq_base;
24unsigned int gic_irq_flags[GIC_NUM_INTRS]; 25unsigned int gic_irq_flags[GIC_NUM_INTRS];
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index bfede063d96a..3e5164c11cac 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -34,6 +34,7 @@
34#include <asm/mipsregs.h> 34#include <asm/mipsregs.h>
35#include <asm/mipsmtregs.h> 35#include <asm/mipsmtregs.h>
36#include <asm/mips_mt.h> 36#include <asm/mips_mt.h>
37#include <asm/gic.h>
37 38
38static void __init smvp_copy_vpe_config(void) 39static void __init smvp_copy_vpe_config(void)
39{ 40{
@@ -151,8 +152,6 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
151static void __cpuinit vsmp_init_secondary(void) 152static void __cpuinit vsmp_init_secondary(void)
152{ 153{
153#ifdef CONFIG_IRQ_GIC 154#ifdef CONFIG_IRQ_GIC
154 extern int gic_present;
155
156 /* This is Malta specific: IPI,performance and timer interrupts */ 155 /* This is Malta specific: IPI,performance and timer interrupts */
157 if (gic_present) 156 if (gic_present)
158 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | 157 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index e364af70e6cf..8e840c20629e 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -47,7 +47,6 @@
47#include <asm/setup.h> 47#include <asm/setup.h>
48 48
49int gcmp_present = -1; 49int gcmp_present = -1;
50int gic_present;
51static unsigned long _msc01_biu_base; 50static unsigned long _msc01_biu_base;
52static unsigned long _gcmp_base; 51static unsigned long _gcmp_base;
53static unsigned int ipi_map[NR_CPUS]; 52static unsigned int ipi_map[NR_CPUS];
diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
index e26e08274fc5..6a560ac03def 100644
--- a/arch/mips/mti-sead3/sead3-int.c
+++ b/arch/mips/mti-sead3/sead3-int.c
@@ -20,7 +20,6 @@
20#define SEAD_CONFIG_BASE 0x1b100110 20#define SEAD_CONFIG_BASE 0x1b100110
21#define SEAD_CONFIG_SIZE 4 21#define SEAD_CONFIG_SIZE 4
22 22
23int gic_present;
24static unsigned long sead3_config_reg; 23static unsigned long sead3_config_reg;
25 24
26/* 25/*