aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorDan Williams <dan.j.williams@intel.com>2011-03-11 17:56:58 -0500
committerDan Williams <dan.j.williams@intel.com>2011-03-11 17:56:58 -0500
commit6c11371dd17c5bd29e3a53cf5263be6ea67c51e4 (patch)
tree012aaba103ad8f685cd1b6bb882472b56818b446 /arch
parentf5539af572ffa35545f21f604fb747eae55c8042 (diff)
parent0b863b333f529c7ddd8bee58e6696a7254417a05 (diff)
Merge branch 'for_dan' of git://git.infradead.org/users/vkoul/slave-dma into dmaengine
* 'for_dan' of git://git.infradead.org/users/vkoul/slave-dma: drivers, pch_dma: Fix warning when CONFIG_PM=n. dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize dw_dmac: Setting Default Burst length for transfers as 16. dw_dmac: Allow src/dst msize & flow controller to be configured at runtime dw_dmac: Changing type of src_master and dest_master to u8. dw_dmac: Pass Channel Priority from platform_data dw_dmac: Pass Channel Allocation Order from platform_data dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finish dw_dmac: Change value of DWC_MAX_COUNT to 4095. dw_dmac: Adding support for 64 bit access width for memcpy xfers dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lock dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in dwc_complete_all dw_dmac: Replace module_init() with subsys_initcall() dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLK dmaengine: mxs-dma: add dma support for i.MX23/28 pch_dma: set the number of array correctly pch_dma: fix kernel error issue
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mxs/include/mach/dma.h26
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c9
2 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
new file mode 100644
index 000000000000..7f4aeeaba8df
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_MXS_DMA_H__
10#define __MACH_MXS_DMA_H__
11
12struct mxs_dma_data {
13 int chan_irq;
14};
15
16static inline int mxs_dma_is_apbh(struct dma_chan *chan)
17{
18 return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbh");
19}
20
21static inline int mxs_dma_is_apbx(struct dma_chan *chan)
22{
23 return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbx");
24}
25
26#endif /* __MACH_MXS_DMA_H__ */
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 2747cde8c9a7..b4aaebd8780c 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -2050,6 +2050,9 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2050 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2050 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2051 rx_dws->src_master = 0; 2051 rx_dws->src_master = 0;
2052 rx_dws->dst_master = 1; 2052 rx_dws->dst_master = 1;
2053 rx_dws->src_msize = DW_DMA_MSIZE_1;
2054 rx_dws->dst_msize = DW_DMA_MSIZE_1;
2055 rx_dws->fc = DW_DMA_FC_D_P2M;
2053 } 2056 }
2054 2057
2055 /* Check if DMA slave interface for playback should be configured. */ 2058 /* Check if DMA slave interface for playback should be configured. */
@@ -2060,6 +2063,9 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2060 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2063 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2061 rx_dws->src_master = 0; 2064 rx_dws->src_master = 0;
2062 rx_dws->dst_master = 1; 2065 rx_dws->dst_master = 1;
2066 tx_dws->src_msize = DW_DMA_MSIZE_1;
2067 tx_dws->dst_msize = DW_DMA_MSIZE_1;
2068 tx_dws->fc = DW_DMA_FC_D_M2P;
2063 } 2069 }
2064 2070
2065 if (platform_device_add_data(pdev, data, 2071 if (platform_device_add_data(pdev, data,
@@ -2134,6 +2140,9 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2134 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2140 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2135 dws->src_master = 0; 2141 dws->src_master = 0;
2136 dws->dst_master = 1; 2142 dws->dst_master = 1;
2143 dws->src_msize = DW_DMA_MSIZE_1;
2144 dws->dst_msize = DW_DMA_MSIZE_1;
2145 dws->fc = DW_DMA_FC_D_M2P;
2137 2146
2138 if (platform_device_add_data(pdev, data, 2147 if (platform_device_add_data(pdev, data,
2139 sizeof(struct atmel_abdac_pdata))) 2148 sizeof(struct atmel_abdac_pdata)))