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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-12 18:22:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-12 18:22:22 -0500
commitf40542532e96dda5506eb76badea322f2ae4731c (patch)
tree157b37de0c375aaebe73dc68762beb7ffe998e76 /arch
parentf01eb3640308c005d31b29d0a8bc2b7acb4e3f75 (diff)
parent0fd7dc7f6c88ba4a46ff472a30d175facc8b6292 (diff)
Merge branch 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6
* 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6: IXP4xx: GTWX5715 platform only has two PCI IRQ lines, not four. IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files. IXP4xx: move Gemtek GTWX5715 platform macros to the platform code. IXP4xx: Remove unused Motorola PrPMC1100 platform macros. IXP4xx: move FSG platform macros to the platform code. IXP4xx: move DSM G600 platform macros to the platform code. IXP4xx: move NAS100D platform macros to the platform code. IXP4xx: move NSLU2 platform macros to the platform code. IXP4xx: move Coyote platform macros to the platform code. IXP4xx: move AVILA platform macros to the platform code. IXP4xx: move IXDP425 platform macros to the platform code. IXP4xx: Extend PCI MMIO indirect address space to 1 GB. IXP4xx: Fix compilation failure with CONFIG_IXP4XX_INDIRECT_PCI. IXP4xx: Drop "__ixp4xx_" prefix from in/out/ioread/iowrite functions for clarity. IXP4xx: Rename indirect MMIO primitives from __ixp4xx_* to __indirect_*. IXP4xx: Ensure index is positive in irq_to_gpio() and npe_request(). ARM: fix insl() and outsl() endianness on IXP4xx architecture. IXP4xx: Fix normally-disabled debugging text in drivers/net/arm/ixp4xx_eth.c. IXP4xx: change the timer base frequency to 66.666000 MHz.
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig22
-rw-r--r--arch/arm/mach-ixp4xx/avila-pci.c42
-rw-r--r--arch/arm/mach-ixp4xx/avila-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c6
-rw-r--r--arch/arm/mach-ixp4xx/common.c2
-rw-r--r--arch/arm/mach-ixp4xx/coyote-pci.c22
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c9
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-pci.c46
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c17
-rw-r--r--arch/arm/mach-ixp4xx/fsg-pci.c31
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c8
-rw-r--r--arch/arm/mach-ixp4xx/goramo_mlr.c45
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-pci.c40
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c30
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/avila.h39
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/coyote.h33
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/dsmg600.h52
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/fsg.h50
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/gtwx5715.h116
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h307
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/irqs.h69
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixdp425.h39
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/nas100d.h52
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/npe.h2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/nslu2.h55
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/prpmc1100.h33
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/timex.h2
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-pci.c43
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c12
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_npe.c2
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-pci.c41
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c16
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-pci.c35
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c21
36 files changed, 453 insertions, 910 deletions
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 264f4d59f898..9e5070da17ae 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI
179 help 179 help
180 IXP4xx provides two methods of accessing PCI memory space: 180 IXP4xx provides two methods of accessing PCI memory space:
181 181
182 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). 182 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
183 To access PCI via this space, we simply ioremap() the BAR 183 To access PCI via this space, we simply ioremap() the BAR
184 into the kernel and we can use the standard read[bwl]/write[bwl] 184 into the kernel and we can use the standard read[bwl]/write[bwl]
185 macros. This is the preferred method due to speed but it 185 macros. This is the preferred method due to speed but it
186 limits the system to just 64MB of PCI memory. This can be 186 limits the system to just 64MB of PCI memory. This can be
187 problematic if using video cards and other memory-heavy devices. 187 problematic if using video cards and other memory-heavy devices.
188 188
189 2) If > 64MB of memory space is required, the IXP4xx can be 189 2) If > 64MB of memory space is required, the IXP4xx can be
190 configured to use indirect registers to access PCI This allows 190 configured to use indirect registers to access the whole PCI
191 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 191 memory space. This currently allows for up to 1 GB (0x10000000
192 The disadvantage of this is that every PCI access requires 192 to 0x4FFFFFFF) of memory on the bus. The disadvantage of this
193 three local register accesses plus a spinlock, but in some 193 is that every PCI access requires three local register accesses
194 cases the performance hit is acceptable. In addition, you cannot 194 plus a spinlock, but in some cases the performance hit is
195 mmap() PCI devices in this case due to the indirect nature 195 acceptable. In addition, you cannot mmap() PCI devices in this
196 of the PCI window. 196 case due to the indirect nature of the PCI window.
197 197
198 By default, the direct method is used. Choose this option if you 198 By default, the direct method is used. Choose this option if you
199 need to use the indirect method instead. If you don't know 199 need to use the indirect method instead. If you don't know
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 08d65dcdb5fe..845e1b500548 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -22,40 +22,45 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25
26#include <asm/mach/pci.h> 25#include <asm/mach/pci.h>
27#include <asm/irq.h> 26#include <asm/irq.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
29#include <asm/mach-types.h> 28#include <asm/mach-types.h>
30 29
30#define AVILA_MAX_DEV 4
31#define LOFT_MAX_DEV 6
32#define IRQ_LINES 4
33
34/* PCI controller GPIO to IRQ pin mappings */
35#define INTA 11
36#define INTB 10
37#define INTC 9
38#define INTD 8
39
31void __init avila_pci_preinit(void) 40void __init avila_pci_preinit(void)
32{ 41{
33 set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 42 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
34 set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 43 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
35 set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 44 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW); 45 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
37
38 ixp4xx_pci_preinit(); 46 ixp4xx_pci_preinit();
39} 47}
40 48
41static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 49static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
42{ 50{
43 static int pci_irq_table[AVILA_PCI_IRQ_LINES] = { 51 static int pci_irq_table[IRQ_LINES] = {
44 IRQ_AVILA_PCI_INTA, 52 IXP4XX_GPIO_IRQ(INTA),
45 IRQ_AVILA_PCI_INTB, 53 IXP4XX_GPIO_IRQ(INTB),
46 IRQ_AVILA_PCI_INTC, 54 IXP4XX_GPIO_IRQ(INTC),
47 IRQ_AVILA_PCI_INTD 55 IXP4XX_GPIO_IRQ(INTD)
48 }; 56 };
49 57
50 int irq = -1;
51
52 if (slot >= 1 && 58 if (slot >= 1 &&
53 slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) && 59 slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) &&
54 pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) { 60 pin >= 1 && pin <= IRQ_LINES)
55 irq = pci_irq_table[(slot + pin - 2) % 4]; 61 return pci_irq_table[(slot + pin - 2) % 4];
56 }
57 62
58 return irq; 63 return -1;
59} 64}
60 65
61struct hw_pci avila_pci __initdata = { 66struct hw_pci avila_pci __initdata = {
@@ -75,4 +80,3 @@ int __init avila_pci_init(void)
75} 80}
76 81
77subsys_initcall(avila_pci_init); 82subsys_initcall(avila_pci_init);
78
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 797995ce18b9..6e558a76457d 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -19,7 +19,6 @@
19#include <linux/serial_8250.h> 19#include <linux/serial_8250.h>
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/i2c-gpio.h> 21#include <linux/i2c-gpio.h>
22
23#include <asm/types.h> 22#include <asm/types.h>
24#include <asm/setup.h> 23#include <asm/setup.h>
25#include <asm/memory.h> 24#include <asm/memory.h>
@@ -29,6 +28,9 @@
29#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
30#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
31 30
31#define AVILA_SDA_PIN 7
32#define AVILA_SCL_PIN 6
33
32static struct flash_platform_data avila_flash_data = { 34static struct flash_platform_data avila_flash_data = {
33 .map_name = "cfi_probe", 35 .map_name = "cfi_probe",
34 .width = 2, 36 .width = 2,
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 70afcfe5b881..c4a01594c761 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -481,11 +481,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
481 481
482 res[1].name = "PCI Memory Space"; 482 res[1].name = "PCI Memory Space";
483 res[1].start = PCIBIOS_MIN_MEM; 483 res[1].start = PCIBIOS_MIN_MEM;
484#ifndef CONFIG_IXP4XX_INDIRECT_PCI 484 res[1].end = PCIBIOS_MAX_MEM;
485 res[1].end = 0x4bffffff;
486#else
487 res[1].end = 0x4fffffff;
488#endif
489 res[1].flags = IORESOURCE_MEM; 485 res[1].flags = IORESOURCE_MEM;
490 486
491 request_resource(&ioport_resource, &res[0]); 487 request_resource(&ioport_resource, &res[0]);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index cfd52fb341cb..3bbf40f6d964 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -117,7 +117,7 @@ int gpio_to_irq(int gpio)
117} 117}
118EXPORT_SYMBOL(gpio_to_irq); 118EXPORT_SYMBOL(gpio_to_irq);
119 119
120int irq_to_gpio(int irq) 120int irq_to_gpio(unsigned int irq)
121{ 121{
122 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; 122 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
123 123
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index efddf01ed17b..b978ea8bd6f0 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -18,27 +18,31 @@
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21
22#include <asm/mach-types.h> 21#include <asm/mach-types.h>
23#include <mach/hardware.h> 22#include <mach/hardware.h>
24#include <asm/irq.h> 23#include <asm/irq.h>
25
26#include <asm/mach/pci.h> 24#include <asm/mach/pci.h>
27 25
26#define SLOT0_DEVID 14
27#define SLOT1_DEVID 15
28
29/* PCI controller GPIO to IRQ pin mappings */
30#define SLOT0_INTA 6
31#define SLOT1_INTA 11
32
28void __init coyote_pci_preinit(void) 33void __init coyote_pci_preinit(void)
29{ 34{
30 set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); 35 set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
31 set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW); 36 set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
32
33 ixp4xx_pci_preinit(); 37 ixp4xx_pci_preinit();
34} 38}
35 39
36static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 40static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
37{ 41{
38 if (slot == COYOTE_PCI_SLOT0_DEVID) 42 if (slot == SLOT0_DEVID)
39 return IRQ_COYOTE_PCI_SLOT0; 43 return IXP4XX_GPIO_IRQ(SLOT0_INTA);
40 else if (slot == COYOTE_PCI_SLOT1_DEVID) 44 else if (slot == SLOT1_DEVID)
41 return IRQ_COYOTE_PCI_SLOT1; 45 return IXP4XX_GPIO_IRQ(SLOT1_INTA);
42 else return -1; 46 else return -1;
43} 47}
44 48
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index aab1954e2747..25bf5ad770ea 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -25,6 +25,15 @@
25#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/mach/flash.h> 26#include <asm/mach/flash.h>
27 27
28#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
29#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
30#define COYOTE_IDE_REGION_SIZE 0x1000
31
32#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
33#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
34#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
35#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
36
28static struct flash_platform_data coyote_flash_data = { 37static struct flash_platform_data coyote_flash_data = {
29 .map_name = "cfi_probe", 38 .map_name = "cfi_probe",
30 .width = 2, 39 .width = 2,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index 926d15f885fb..fa70fed462ba 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -19,39 +19,45 @@
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22
23#include <asm/mach/pci.h> 22#include <asm/mach/pci.h>
24#include <asm/mach-types.h> 23#include <asm/mach-types.h>
25 24
25#define MAX_DEV 4
26#define IRQ_LINES 3
27
28/* PCI controller GPIO to IRQ pin mappings */
29#define INTA 11
30#define INTB 10
31#define INTC 9
32#define INTD 8
33#define INTE 7
34#define INTF 6
35
26void __init dsmg600_pci_preinit(void) 36void __init dsmg600_pci_preinit(void)
27{ 37{
28 set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 38 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
29 set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 39 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
30 set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 40 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
31 set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); 41 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
32 set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); 42 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
33 set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); 43 set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
34
35 ixp4xx_pci_preinit(); 44 ixp4xx_pci_preinit();
36} 45}
37 46
38static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 47static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
39{ 48{
40 static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] = 49 static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
41 { 50 { IXP4XX_GPIO_IRQ(INTE), -1, -1 },
42 { IRQ_DSMG600_PCI_INTE, -1, -1 }, 51 { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
43 { IRQ_DSMG600_PCI_INTA, -1, -1 }, 52 { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
44 { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD }, 53 IXP4XX_GPIO_IRQ(INTD) },
45 { IRQ_DSMG600_PCI_INTF, -1, -1 }, 54 { IXP4XX_GPIO_IRQ(INTF), -1, -1 },
46 }; 55 };
47 56
48 int irq = -1; 57 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
49 58 return pci_irq_table[slot - 1][pin - 1];
50 if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV &&
51 pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES)
52 irq = pci_irq_table[slot-1][pin-1];
53 59
54 return irq; 60 return -1;
55} 61}
56 62
57struct hw_pci __initdata dsmg600_pci = { 63struct hw_pci __initdata dsmg600_pci = {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index a51bfa6978b6..7c1fa54a6145 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -33,6 +33,23 @@
33#include <asm/mach/time.h> 33#include <asm/mach/time.h>
34#include <asm/gpio.h> 34#include <asm/gpio.h>
35 35
36#define DSMG600_SDA_PIN 5
37#define DSMG600_SCL_PIN 4
38
39/* DSM-G600 Timer Setting */
40#define DSMG600_FREQ 66000000
41
42/* Buttons */
43#define DSMG600_PB_GPIO 15 /* power button */
44#define DSMG600_RB_GPIO 3 /* reset button */
45
46/* Power control */
47#define DSMG600_PO_GPIO 2 /* power off */
48
49/* LEDs */
50#define DSMG600_LED_PWR_GPIO 0
51#define DSMG600_LED_WLAN_GPIO 14
52
36static struct flash_platform_data dsmg600_flash_data = { 53static struct flash_platform_data dsmg600_flash_data = {
37 .map_name = "cfi_probe", 54 .map_name = "cfi_probe",
38 .width = 2, 55 .width = 2,
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index ca12a9ca0830..5a810c930624 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -19,33 +19,38 @@
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22
23#include <asm/mach/pci.h> 22#include <asm/mach/pci.h>
24#include <asm/mach-types.h> 23#include <asm/mach-types.h>
25 24
25#define MAX_DEV 3
26#define IRQ_LINES 3
27
28/* PCI controller GPIO to IRQ pin mappings */
29#define INTA 6
30#define INTB 7
31#define INTC 5
32
26void __init fsg_pci_preinit(void) 33void __init fsg_pci_preinit(void)
27{ 34{
28 set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 35 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
29 set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 36 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
30 set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 37 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
31
32 ixp4xx_pci_preinit(); 38 ixp4xx_pci_preinit();
33} 39}
34 40
35static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 41static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
36{ 42{
37 static int pci_irq_table[FSG_PCI_IRQ_LINES] = { 43 static int pci_irq_table[IRQ_LINES] = {
38 IRQ_FSG_PCI_INTC, 44 IXP4XX_GPIO_IRQ(INTC),
39 IRQ_FSG_PCI_INTB, 45 IXP4XX_GPIO_IRQ(INTB),
40 IRQ_FSG_PCI_INTA, 46 IXP4XX_GPIO_IRQ(INTA),
41 }; 47 };
42 48
43 int irq = -1; 49 int irq = -1;
44 slot = slot - 11; 50 slot -= 11;
45 51
46 if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && 52 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
47 pin >= 1 && pin <= FSG_PCI_IRQ_LINES) 53 irq = pci_irq_table[slot - 1];
48 irq = pci_irq_table[(slot - 1)];
49 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", 54 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
50 __func__, slot, pin, irq); 55 __func__, slot, pin, irq);
51 56
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 5add22fc9899..e7f4befba422 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -24,12 +24,18 @@
24#include <linux/i2c.h> 24#include <linux/i2c.h>
25#include <linux/i2c-gpio.h> 25#include <linux/i2c-gpio.h>
26#include <linux/io.h> 26#include <linux/io.h>
27
28#include <asm/mach-types.h> 27#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
30#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
31#include <asm/gpio.h> 30#include <asm/gpio.h>
32 31
32#define FSG_SDA_PIN 12
33#define FSG_SCL_PIN 13
34
35#define FSG_SB_GPIO 4 /* sync button */
36#define FSG_RB_GPIO 9 /* reset button */
37#define FSG_UB_GPIO 10 /* usb button */
38
33static struct flash_platform_data fsg_flash_data = { 39static struct flash_platform_data fsg_flash_data = {
34 .map_name = "cfi_probe", 40 .map_name = "cfi_probe",
35 .width = 2, 41 .width = 2,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index a733b8ff3cec..1c28048209c1 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -17,29 +17,28 @@
17#include <asm/mach/flash.h> 17#include <asm/mach/flash.h>
18#include <asm/mach/pci.h> 18#include <asm/mach/pci.h>
19 19
20#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n)
21#define gpio_irq(n) xgpio_irq(n)
22
23#define SLOT_ETHA 0x0B /* IDSEL = AD21 */ 20#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
24#define SLOT_ETHB 0x0C /* IDSEL = AD20 */ 21#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
25#define SLOT_MPCI 0x0D /* IDSEL = AD19 */ 22#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
26#define SLOT_NEC 0x0E /* IDSEL = AD18 */ 23#define SLOT_NEC 0x0E /* IDSEL = AD18 */
27 24
28#define IRQ_ETHA IRQ_IXP4XX_GPIO4
29#define IRQ_ETHB IRQ_IXP4XX_GPIO5
30#define IRQ_NEC IRQ_IXP4XX_GPIO3
31#define IRQ_MPCI IRQ_IXP4XX_GPIO12
32
33/* GPIO lines */ 25/* GPIO lines */
34#define GPIO_SCL 0 26#define GPIO_SCL 0
35#define GPIO_SDA 1 27#define GPIO_SDA 1
36#define GPIO_STR 2 28#define GPIO_STR 2
29#define GPIO_IRQ_NEC 3
30#define GPIO_IRQ_ETHA 4
31#define GPIO_IRQ_ETHB 5
37#define GPIO_HSS0_DCD_N 6 32#define GPIO_HSS0_DCD_N 6
38#define GPIO_HSS1_DCD_N 7 33#define GPIO_HSS1_DCD_N 7
34#define GPIO_UART0_DCD 8
35#define GPIO_UART1_DCD 9
39#define GPIO_HSS0_CTS_N 10 36#define GPIO_HSS0_CTS_N 10
40#define GPIO_HSS1_CTS_N 11 37#define GPIO_HSS1_CTS_N 11
38#define GPIO_IRQ_MPCI 12
41#define GPIO_HSS1_RTS_N 13 39#define GPIO_HSS1_RTS_N 13
42#define GPIO_HSS0_RTS_N 14 40#define GPIO_HSS0_RTS_N 14
41/* GPIO15 is not connected */
43 42
44/* Control outputs from 74HC4094 */ 43/* Control outputs from 74HC4094 */
45#define CONTROL_HSS0_CLK_INT 0 44#define CONTROL_HSS0_CLK_INT 0
@@ -152,7 +151,7 @@ static int hss_set_clock(int port, unsigned int clock_type)
152 151
153static irqreturn_t hss_dcd_irq(int irq, void *pdev) 152static irqreturn_t hss_dcd_irq(int irq, void *pdev)
154{ 153{
155 int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); 154 int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
156 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); 155 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
157 set_carrier_cb_tab[port](pdev, !i); 156 set_carrier_cb_tab[port](pdev, !i);
158 return IRQ_HANDLED; 157 return IRQ_HANDLED;
@@ -165,9 +164,9 @@ static int hss_open(int port, void *pdev,
165 int i, irq; 164 int i, irq;
166 165
167 if (!port) 166 if (!port)
168 irq = gpio_irq(GPIO_HSS0_DCD_N); 167 irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
169 else 168 else
170 irq = gpio_irq(GPIO_HSS1_DCD_N); 169 irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
171 170
172 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); 171 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
173 set_carrier_cb(pdev, !i); 172 set_carrier_cb(pdev, !i);
@@ -188,8 +187,8 @@ static int hss_open(int port, void *pdev,
188 187
189static void hss_close(int port, void *pdev) 188static void hss_close(int port, void *pdev)
190{ 189{
191 free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), 190 free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
192 pdev); 191 IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
193 set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ 192 set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
194 193
195 set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); 194 set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
@@ -421,8 +420,8 @@ static void __init gmlr_init(void)
421 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); 420 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
422 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); 421 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
423 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); 422 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
424 set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); 423 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
425 set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); 424 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
426 425
427 set_control(CONTROL_HSS0_DTR_N, 1); 426 set_control(CONTROL_HSS0_DTR_N, 1);
428 set_control(CONTROL_HSS1_DTR_N, 1); 427 set_control(CONTROL_HSS1_DTR_N, 1);
@@ -442,10 +441,10 @@ static void __init gmlr_init(void)
442#ifdef CONFIG_PCI 441#ifdef CONFIG_PCI
443static void __init gmlr_pci_preinit(void) 442static void __init gmlr_pci_preinit(void)
444{ 443{
445 set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); 444 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
446 set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); 445 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
447 set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); 446 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
448 set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); 447 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
449 ixp4xx_pci_preinit(); 448 ixp4xx_pci_preinit();
450} 449}
451 450
@@ -466,10 +465,10 @@ static void __init gmlr_pci_postinit(void)
466static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 465static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
467{ 466{
468 switch(slot) { 467 switch(slot) {
469 case SLOT_ETHA: return IRQ_ETHA; 468 case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
470 case SLOT_ETHB: return IRQ_ETHB; 469 case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
471 case SLOT_NEC: return IRQ_NEC; 470 case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
472 default: return IRQ_MPCI; 471 default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
473 } 472 }
474} 473}
475 474
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 7b8a2c323840..25d2c333c204 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -26,14 +26,16 @@
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/irq.h> 28#include <linux/irq.h>
29
30#include <asm/mach-types.h> 29#include <asm/mach-types.h>
31#include <mach/hardware.h> 30#include <mach/hardware.h>
32#include <mach/gtwx5715.h>
33#include <asm/mach/pci.h> 31#include <asm/mach/pci.h>
34 32
33#define SLOT0_DEVID 0
34#define SLOT1_DEVID 1
35#define INTA 10 /* slot 1 has INTA and INTB crossed */
36#define INTB 11
37
35/* 38/*
36 * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
37 * Slot 0 isn't actually populated with a card connector but 39 * Slot 0 isn't actually populated with a card connector but
38 * we initialize it anyway in case a future version has the 40 * we initialize it anyway in case a future version has the
39 * slot populated or someone with good soldering skills has 41 * slot populated or someone with good soldering skills has
@@ -41,32 +43,26 @@
41 */ 43 */
42void __init gtwx5715_pci_preinit(void) 44void __init gtwx5715_pci_preinit(void)
43{ 45{
44 set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); 46 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
45 set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); 47 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
46 set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
47 set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
48
49 ixp4xx_pci_preinit(); 48 ixp4xx_pci_preinit();
50} 49}
51 50
52 51
53static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 52static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
54{ 53{
55 int rc; 54 int rc = -1;
56 static int gtwx5715_irqmap
57 [GTWX5715_PCI_SLOT_COUNT]
58 [GTWX5715_PCI_INT_PIN_COUNT] = {
59 {GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ},
60 {GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ},
61};
62 55
63 if (slot >= GTWX5715_PCI_SLOT_COUNT || 56 if ((slot == SLOT0_DEVID && pin == 1) ||
64 pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1; 57 (slot == SLOT1_DEVID && pin == 2))
65 else 58 rc = IXP4XX_GPIO_IRQ(INTA);
66 rc = gtwx5715_irqmap[slot][pin-1]; 59 else if ((slot == SLOT0_DEVID && pin == 2) ||
60 (slot == SLOT1_DEVID && pin == 1))
61 rc = IXP4XX_GPIO_IRQ(INTB);
67 62
68 printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); 63 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
69 return(rc); 64 __func__, slot, pin, rc);
65 return rc;
70} 66}
71 67
72struct hw_pci gtwx5715_pci __initdata = { 68struct hw_pci gtwx5715_pci __initdata = {
@@ -81,9 +77,7 @@ struct hw_pci gtwx5715_pci __initdata = {
81int __init gtwx5715_pci_init(void) 77int __init gtwx5715_pci_init(void)
82{ 78{
83 if (machine_is_gtwx5715()) 79 if (machine_is_gtwx5715())
84 {
85 pci_common_init(&gtwx5715_pci); 80 pci_common_init(&gtwx5715_pci);
86 }
87 81
88 return 0; 82 return 0;
89} 83}
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 25c21d6665ec..0bc7185cb6f7 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -28,7 +28,6 @@
28#include <linux/tty.h> 28#include <linux/tty.h>
29#include <linux/serial_8250.h> 29#include <linux/serial_8250.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31
32#include <asm/types.h> 31#include <asm/types.h>
33#include <asm/setup.h> 32#include <asm/setup.h>
34#include <asm/memory.h> 33#include <asm/memory.h>
@@ -37,7 +36,34 @@
37#include <asm/mach-types.h> 36#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
39#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
40#include <mach/gtwx5715.h> 39
40/* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch
41 and operate as an SPI type interface. The details of the interface
42 are available on Kendin/Micrel's web site. */
43
44#define GTWX5715_KSSPI_SELECT 5
45#define GTWX5715_KSSPI_TXD 6
46#define GTWX5715_KSSPI_CLOCK 7
47#define GTWX5715_KSSPI_RXD 12
48
49/* The "reset" button is wired to GPIO 3.
50 The GPIO is brought "low" when the button is pushed. */
51
52#define GTWX5715_BUTTON_GPIO 3
53
54/* Board Label Front Label
55 LED1 Power
56 LED2 Wireless-G
57 LED3 not populated but could be
58 LED4 Internet
59 LED5 - LED8 Controlled by KS8995M Switch
60 LED9 DMZ */
61
62#define GTWX5715_LED1_GPIO 2
63#define GTWX5715_LED2_GPIO 9
64#define GTWX5715_LED3_GPIO 8
65#define GTWX5715_LED4_GPIO 1
66#define GTWX5715_LED9_GPIO 4
41 67
42/* 68/*
43 * Xscale UART registers are 32 bits wide with only the least 69 * Xscale UART registers are 32 bits wide with only the least
diff --git a/arch/arm/mach-ixp4xx/include/mach/avila.h b/arch/arm/mach-ixp4xx/include/mach/avila.h
deleted file mode 100644
index 1640cb61972b..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/avila.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/avila.h
3 *
4 * Gateworks Avila platform specific definitions
5 *
6 * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
7 *
8 * Based on ixdp425.h
9 * Author: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <mach/hardware.h>"
20#endif
21
22#define AVILA_SDA_PIN 7
23#define AVILA_SCL_PIN 6
24
25/*
26 * AVILA PCI IRQs
27 */
28#define AVILA_PCI_MAX_DEV 4
29#define LOFT_PCI_MAX_DEV 6
30#define AVILA_PCI_IRQ_LINES 4
31
32
33/* PCI controller GPIO to IRQ pin mappings */
34#define AVILA_PCI_INTA_PIN 11
35#define AVILA_PCI_INTB_PIN 10
36#define AVILA_PCI_INTC_PIN 9
37#define AVILA_PCI_INTD_PIN 8
38
39
diff --git a/arch/arm/mach-ixp4xx/include/mach/coyote.h b/arch/arm/mach-ixp4xx/include/mach/coyote.h
deleted file mode 100644
index 717ac6d16f55..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/coyote.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/coyote.h
3 *
4 * ADI Engineering platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19/* PCI controller GPIO to IRQ pin mappings */
20#define COYOTE_PCI_SLOT0_PIN 6
21#define COYOTE_PCI_SLOT1_PIN 11
22
23#define COYOTE_PCI_SLOT0_DEVID 14
24#define COYOTE_PCI_SLOT1_DEVID 15
25
26#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
27#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
28#define COYOTE_IDE_REGION_SIZE 0x1000
29
30#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
31#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
32#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
33
diff --git a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
deleted file mode 100644
index dc087a34a268..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * DSM-G600 platform specific definitions
3 *
4 * Copyright (C) 2006 Tower Technologies
5 * Author: Alessandro Zummo <a.zummo@towertech.it>
6 *
7 * based on ixdp425.h:
8 * Copyright 2004 (C) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19#define DSMG600_SDA_PIN 5
20#define DSMG600_SCL_PIN 4
21
22/*
23 * DSMG600 PCI IRQs
24 */
25#define DSMG600_PCI_MAX_DEV 4
26#define DSMG600_PCI_IRQ_LINES 3
27
28
29/* PCI controller GPIO to IRQ pin mappings */
30#define DSMG600_PCI_INTA_PIN 11
31#define DSMG600_PCI_INTB_PIN 10
32#define DSMG600_PCI_INTC_PIN 9
33#define DSMG600_PCI_INTD_PIN 8
34#define DSMG600_PCI_INTE_PIN 7
35#define DSMG600_PCI_INTF_PIN 6
36
37/* DSM-G600 Timer Setting */
38#define DSMG600_FREQ 66000000
39
40/* Buttons */
41
42#define DSMG600_PB_GPIO 15 /* power button */
43#define DSMG600_RB_GPIO 3 /* reset button */
44
45/* Power control */
46
47#define DSMG600_PO_GPIO 2 /* power off */
48
49/* LEDs */
50
51#define DSMG600_LED_PWR_GPIO 0
52#define DSMG600_LED_WLAN_GPIO 14
diff --git a/arch/arm/mach-ixp4xx/include/mach/fsg.h b/arch/arm/mach-ixp4xx/include/mach/fsg.h
deleted file mode 100644
index 1f02b7e22a13..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/fsg.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/fsg.h
3 *
4 * Freecom FSG-3 platform specific definitions
5 *
6 * Author: Rod Whitby <rod@whitby.id.au>
7 * Author: Tomasz Chmielewski <mangoo@wpkg.org>
8 * Maintainers: http://www.nslu2-linux.org
9 *
10 * Based on coyote.h by
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <mach/hardware.h>"
20#endif
21
22#define FSG_SDA_PIN 12
23#define FSG_SCL_PIN 13
24
25/*
26 * FSG PCI IRQs
27 */
28#define FSG_PCI_MAX_DEV 3
29#define FSG_PCI_IRQ_LINES 3
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define FSG_PCI_INTA_PIN 6
34#define FSG_PCI_INTB_PIN 7
35#define FSG_PCI_INTC_PIN 5
36
37/* Buttons */
38
39#define FSG_SB_GPIO 4 /* sync button */
40#define FSG_RB_GPIO 9 /* reset button */
41#define FSG_UB_GPIO 10 /* usb button */
42
43/* LEDs */
44
45#define FSG_LED_WLAN_BIT 0
46#define FSG_LED_WAN_BIT 1
47#define FSG_LED_SATA_BIT 2
48#define FSG_LED_USB_BIT 4
49#define FSG_LED_RING_BIT 5
50#define FSG_LED_SYNC_BIT 7
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
index cd5aec26c072..a5f87ded2f28 100644
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h
@@ -70,7 +70,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
70#include <asm-generic/gpio.h> /* cansleep wrappers */ 70#include <asm-generic/gpio.h> /* cansleep wrappers */
71 71
72extern int gpio_to_irq(int gpio); 72extern int gpio_to_irq(int gpio);
73extern int irq_to_gpio(int gpio); 73extern int irq_to_gpio(unsigned int irq);
74 74
75#endif 75#endif
76 76
diff --git a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
deleted file mode 100644
index 5d5e201cac7e..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
3 *
4 * Gemtek GTWX5715 Gateway (Linksys WRV54G)
5 *
6 * Copyright 2004 (c) George T. Joseph
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#ifndef __ASM_ARCH_HARDWARE_H__
24#error "Do not include this directly, instead #include <mach/hardware.h>"
25#endif
26#include "irqs.h"
27
28#define GTWX5715_GPIO0 0
29#define GTWX5715_GPIO1 1
30#define GTWX5715_GPIO2 2
31#define GTWX5715_GPIO3 3
32#define GTWX5715_GPIO4 4
33#define GTWX5715_GPIO5 5
34#define GTWX5715_GPIO6 6
35#define GTWX5715_GPIO7 7
36#define GTWX5715_GPIO8 8
37#define GTWX5715_GPIO9 9
38#define GTWX5715_GPIO10 10
39#define GTWX5715_GPIO11 11
40#define GTWX5715_GPIO12 12
41#define GTWX5715_GPIO13 13
42#define GTWX5715_GPIO14 14
43
44#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0
45#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1
46#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2
47#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3
48#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4
49#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5
50#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6
51#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7
52#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8
53#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9
54#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10
55#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11
56#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12
57#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
58#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
59
60/* PCI controller GPIO to IRQ pin mappings
61
62 INTA INTB
63SLOT 0 10 11
64SLOT 1 11 10
65
66*/
67
68#define GTWX5715_PCI_SLOT0_DEVID 0
69#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10
70#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11
71#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ
72#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ
73
74#define GTWX5715_PCI_SLOT1_DEVID 1
75#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11
76#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10
77#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ
78#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ
79
80#define GTWX5715_PCI_SLOT_COUNT 2
81#define GTWX5715_PCI_INT_PIN_COUNT 2
82
83/*
84 * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
85 * and operate as an SPI type interface. The details of the interface
86 * are available on Kendin/Micrel's web site.
87 */
88
89#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5
90#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6
91#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7
92#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12
93
94/*
95 * The "reset" button is wired to GPIO 3.
96 * The GPIO is brought "low" when the button is pushed.
97 */
98
99#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3
100#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ
101
102/*
103 * Board Label Front Label
104 * LED1 Power
105 * LED2 Wireless-G
106 * LED3 not populated but could be
107 * LED4 Internet
108 * LED5 - LED8 Controlled by KS8995M Switch
109 * LED9 DMZ
110 */
111
112#define GTWX5715_LED1_GPIO GTWX5715_GPIO2
113#define GTWX5715_LED2_GPIO GTWX5715_GPIO9
114#define GTWX5715_LED3_GPIO GTWX5715_GPIO8
115#define GTWX5715_LED4_GPIO GTWX5715_GPIO1
116#define GTWX5715_LED9_GPIO GTWX5715_GPIO4
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index f58a43a23966..f9d1c43e4a54 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -18,7 +18,13 @@
18#define __ASM_ARCH_HARDWARE_H__ 18#define __ASM_ARCH_HARDWARE_H__
19 19
20#define PCIBIOS_MIN_IO 0x00001000 20#define PCIBIOS_MIN_IO 0x00001000
21#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000) 21#ifdef CONFIG_IXP4XX_INDIRECT_PCI
22#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */
23#define PCIBIOS_MAX_MEM 0x4FFFFFFF
24#else
25#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */
26#define PCIBIOS_MAX_MEM 0x4BFFFFFF
27#endif
22 28
23/* 29/*
24 * We override the standard dma-mask routines for bouncing. 30 * We override the standard dma-mask routines for bouncing.
@@ -37,14 +43,4 @@
37/* Platform helper functions and definitions */ 43/* Platform helper functions and definitions */
38#include "platform.h" 44#include "platform.h"
39 45
40/* Platform specific details */
41#include "ixdp425.h"
42#include "avila.h"
43#include "coyote.h"
44#include "prpmc1100.h"
45#include "nslu2.h"
46#include "nas100d.h"
47#include "dsmg600.h"
48#include "fsg.h"
49
50#endif /* _ASM_ARCH_HARDWARE_H */ 46#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 8a947d42a6f1..6ea7e2fb2701 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
26/* 26/*
27 * IXP4xx provides two methods of accessing PCI memory space: 27 * IXP4xx provides two methods of accessing PCI memory space:
28 * 28 *
29 * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). 29 * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
30 * To access PCI via this space, we simply ioremap() the BAR 30 * To access PCI via this space, we simply ioremap() the BAR
31 * into the kernel and we can use the standard read[bwl]/write[bwl] 31 * into the kernel and we can use the standard read[bwl]/write[bwl]
32 * macros. This is the preffered method due to speed but it 32 * macros. This is the preffered method due to speed but it
33 * limits the system to just 64MB of PCI memory. This can be 33 * limits the system to just 64MB of PCI memory. This can be
34 * problamatic if using video cards and other memory-heavy 34 * problematic if using video cards and other memory-heavy targets.
35 * targets.
36 *
37 * 2) If > 64MB of memory space is required, the IXP4xx can be configured
38 * to use indirect registers to access PCI (as we do below for I/O
39 * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
40 * of memory on the bus. The disadvantage of this is that every
41 * PCI access requires three local register accesses plus a spinlock,
42 * but in some cases the performance hit is acceptable. In addition,
43 * you cannot mmap() PCI devices in this case.
44 * 35 *
36 * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
37 * registers to access the whole 4 GB of PCI memory space (as we do below
38 * for I/O transactions). This allows currently for up to 1 GB (0x10000000
39 * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
40 * every PCI access requires three local register accesses plus a spinlock,
41 * but in some cases the performance hit is acceptable. In addition, you
42 * cannot mmap() PCI devices in this case.
45 */ 43 */
46#ifndef CONFIG_IXP4XX_INDIRECT_PCI 44#ifndef CONFIG_IXP4XX_INDIRECT_PCI
47 45
@@ -55,48 +53,52 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
55 * access registers. If something outside of PCI is ioremap'd, we 53 * access registers. If something outside of PCI is ioremap'd, we
56 * fallback to the default. 54 * fallback to the default.
57 */ 55 */
58static inline void __iomem * 56
59__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) 57static inline int is_pci_memory(u32 addr)
58{
59 return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
60}
61
62static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
63 unsigned int mtype)
60{ 64{
61 if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) 65 if (!is_pci_memory(addr))
62 return __arm_ioremap(addr, size, mtype); 66 return __arm_ioremap(addr, size, mtype);
63 67
64 return (void __iomem *)addr; 68 return (void __iomem *)addr;
65} 69}
66 70
67static inline void 71static inline void __indirect_iounmap(void __iomem *addr)
68__ixp4xx_iounmap(void __iomem *addr)
69{ 72{
70 if ((__force u32)addr >= VMALLOC_START) 73 if (!is_pci_memory((__force u32)addr))
71 __iounmap(addr); 74 __iounmap(addr);
72} 75}
73 76
74#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) 77#define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f)
75#define __arch_iounmap(a) __ixp4xx_iounmap(a) 78#define __arch_iounmap(a) __indirect_iounmap(a)
76 79
77#define writeb(v, p) __ixp4xx_writeb(v, p) 80#define writeb(v, p) __indirect_writeb(v, p)
78#define writew(v, p) __ixp4xx_writew(v, p) 81#define writew(v, p) __indirect_writew(v, p)
79#define writel(v, p) __ixp4xx_writel(v, p) 82#define writel(v, p) __indirect_writel(v, p)
80 83
81#define writesb(p, v, l) __ixp4xx_writesb(p, v, l) 84#define writesb(p, v, l) __indirect_writesb(p, v, l)
82#define writesw(p, v, l) __ixp4xx_writesw(p, v, l) 85#define writesw(p, v, l) __indirect_writesw(p, v, l)
83#define writesl(p, v, l) __ixp4xx_writesl(p, v, l) 86#define writesl(p, v, l) __indirect_writesl(p, v, l)
84
85#define readb(p) __ixp4xx_readb(p)
86#define readw(p) __ixp4xx_readw(p)
87#define readl(p) __ixp4xx_readl(p)
88
89#define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
90#define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
91#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
92 87
93static inline void 88#define readb(p) __indirect_readb(p)
94__ixp4xx_writeb(u8 value, volatile void __iomem *p) 89#define readw(p) __indirect_readw(p)
90#define readl(p) __indirect_readl(p)
91
92#define readsb(p, v, l) __indirect_readsb(p, v, l)
93#define readsw(p, v, l) __indirect_readsw(p, v, l)
94#define readsl(p, v, l) __indirect_readsl(p, v, l)
95
96static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
95{ 97{
96 u32 addr = (u32)p; 98 u32 addr = (u32)p;
97 u32 n, byte_enables, data; 99 u32 n, byte_enables, data;
98 100
99 if (addr >= VMALLOC_START) { 101 if (!is_pci_memory(addr)) {
100 __raw_writeb(value, addr); 102 __raw_writeb(value, addr);
101 return; 103 return;
102 } 104 }
@@ -107,20 +109,19 @@ __ixp4xx_writeb(u8 value, volatile void __iomem *p)
107 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); 109 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
108} 110}
109 111
110static inline void 112static inline void __indirect_writesb(volatile void __iomem *bus_addr,
111__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) 113 const u8 *vaddr, int count)
112{ 114{
113 while (count--) 115 while (count--)
114 writeb(*vaddr++, bus_addr); 116 writeb(*vaddr++, bus_addr);
115} 117}
116 118
117static inline void 119static inline void __indirect_writew(u16 value, volatile void __iomem *p)
118__ixp4xx_writew(u16 value, volatile void __iomem *p)
119{ 120{
120 u32 addr = (u32)p; 121 u32 addr = (u32)p;
121 u32 n, byte_enables, data; 122 u32 n, byte_enables, data;
122 123
123 if (addr >= VMALLOC_START) { 124 if (!is_pci_memory(addr)) {
124 __raw_writew(value, addr); 125 __raw_writew(value, addr);
125 return; 126 return;
126 } 127 }
@@ -131,18 +132,18 @@ __ixp4xx_writew(u16 value, volatile void __iomem *p)
131 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); 132 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
132} 133}
133 134
134static inline void 135static inline void __indirect_writesw(volatile void __iomem *bus_addr,
135__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) 136 const u16 *vaddr, int count)
136{ 137{
137 while (count--) 138 while (count--)
138 writew(*vaddr++, bus_addr); 139 writew(*vaddr++, bus_addr);
139} 140}
140 141
141static inline void 142static inline void __indirect_writel(u32 value, volatile void __iomem *p)
142__ixp4xx_writel(u32 value, volatile void __iomem *p)
143{ 143{
144 u32 addr = (__force u32)p; 144 u32 addr = (__force u32)p;
145 if (addr >= VMALLOC_START) { 145
146 if (!is_pci_memory(addr)) {
146 __raw_writel(value, p); 147 __raw_writel(value, p);
147 return; 148 return;
148 } 149 }
@@ -150,20 +151,19 @@ __ixp4xx_writel(u32 value, volatile void __iomem *p)
150 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); 151 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
151} 152}
152 153
153static inline void 154static inline void __indirect_writesl(volatile void __iomem *bus_addr,
154__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) 155 const u32 *vaddr, int count)
155{ 156{
156 while (count--) 157 while (count--)
157 writel(*vaddr++, bus_addr); 158 writel(*vaddr++, bus_addr);
158} 159}
159 160
160static inline unsigned char 161static inline unsigned char __indirect_readb(const volatile void __iomem *p)
161__ixp4xx_readb(const volatile void __iomem *p)
162{ 162{
163 u32 addr = (u32)p; 163 u32 addr = (u32)p;
164 u32 n, byte_enables, data; 164 u32 n, byte_enables, data;
165 165
166 if (addr >= VMALLOC_START) 166 if (!is_pci_memory(addr))
167 return __raw_readb(addr); 167 return __raw_readb(addr);
168 168
169 n = addr % 4; 169 n = addr % 4;
@@ -174,20 +174,19 @@ __ixp4xx_readb(const volatile void __iomem *p)
174 return data >> (8*n); 174 return data >> (8*n);
175} 175}
176 176
177static inline void 177static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
178__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) 178 u8 *vaddr, u32 count)
179{ 179{
180 while (count--) 180 while (count--)
181 *vaddr++ = readb(bus_addr); 181 *vaddr++ = readb(bus_addr);
182} 182}
183 183
184static inline unsigned short 184static inline unsigned short __indirect_readw(const volatile void __iomem *p)
185__ixp4xx_readw(const volatile void __iomem *p)
186{ 185{
187 u32 addr = (u32)p; 186 u32 addr = (u32)p;
188 u32 n, byte_enables, data; 187 u32 n, byte_enables, data;
189 188
190 if (addr >= VMALLOC_START) 189 if (!is_pci_memory(addr))
191 return __raw_readw(addr); 190 return __raw_readw(addr);
192 191
193 n = addr % 4; 192 n = addr % 4;
@@ -198,20 +197,19 @@ __ixp4xx_readw(const volatile void __iomem *p)
198 return data>>(8*n); 197 return data>>(8*n);
199} 198}
200 199
201static inline void 200static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
202__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) 201 u16 *vaddr, u32 count)
203{ 202{
204 while (count--) 203 while (count--)
205 *vaddr++ = readw(bus_addr); 204 *vaddr++ = readw(bus_addr);
206} 205}
207 206
208static inline unsigned long 207static inline unsigned long __indirect_readl(const volatile void __iomem *p)
209__ixp4xx_readl(const volatile void __iomem *p)
210{ 208{
211 u32 addr = (__force u32)p; 209 u32 addr = (__force u32)p;
212 u32 data; 210 u32 data;
213 211
214 if (addr >= VMALLOC_START) 212 if (!is_pci_memory(addr))
215 return __raw_readl(p); 213 return __raw_readl(p);
216 214
217 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) 215 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
@@ -220,8 +218,8 @@ __ixp4xx_readl(const volatile void __iomem *p)
220 return data; 218 return data;
221} 219}
222 220
223static inline void 221static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
224__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) 222 u32 *vaddr, u32 count)
225{ 223{
226 while (count--) 224 while (count--)
227 *vaddr++ = readl(bus_addr); 225 *vaddr++ = readl(bus_addr);
@@ -235,7 +233,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
235#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) 233#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
236#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) 234#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
237 235
238#endif 236#endif /* CONFIG_IXP4XX_INDIRECT_PCI */
239 237
240#ifndef CONFIG_PCI 238#ifndef CONFIG_PCI
241 239
@@ -250,25 +248,8 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
250 * transaction. This means that we need to override the default 248 * transaction. This means that we need to override the default
251 * I/O functions. 249 * I/O functions.
252 */ 250 */
253#define outb(p, v) __ixp4xx_outb(p, v)
254#define outw(p, v) __ixp4xx_outw(p, v)
255#define outl(p, v) __ixp4xx_outl(p, v)
256
257#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
258#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
259#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
260 251
261#define inb(p) __ixp4xx_inb(p) 252static inline void outb(u8 value, u32 addr)
262#define inw(p) __ixp4xx_inw(p)
263#define inl(p) __ixp4xx_inl(p)
264
265#define insb(p, v, l) __ixp4xx_insb(p, v, l)
266#define insw(p, v, l) __ixp4xx_insw(p, v, l)
267#define insl(p, v, l) __ixp4xx_insl(p, v, l)
268
269
270static inline void
271__ixp4xx_outb(u8 value, u32 addr)
272{ 253{
273 u32 n, byte_enables, data; 254 u32 n, byte_enables, data;
274 n = addr % 4; 255 n = addr % 4;
@@ -277,15 +258,13 @@ __ixp4xx_outb(u8 value, u32 addr)
277 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); 258 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
278} 259}
279 260
280static inline void 261static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
281__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
282{ 262{
283 while (count--) 263 while (count--)
284 outb(*vaddr++, io_addr); 264 outb(*vaddr++, io_addr);
285} 265}
286 266
287static inline void 267static inline void outw(u16 value, u32 addr)
288__ixp4xx_outw(u16 value, u32 addr)
289{ 268{
290 u32 n, byte_enables, data; 269 u32 n, byte_enables, data;
291 n = addr % 4; 270 n = addr % 4;
@@ -294,28 +273,24 @@ __ixp4xx_outw(u16 value, u32 addr)
294 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); 273 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
295} 274}
296 275
297static inline void 276static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
298__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
299{ 277{
300 while (count--) 278 while (count--)
301 outw(cpu_to_le16(*vaddr++), io_addr); 279 outw(cpu_to_le16(*vaddr++), io_addr);
302} 280}
303 281
304static inline void 282static inline void outl(u32 value, u32 addr)
305__ixp4xx_outl(u32 value, u32 addr)
306{ 283{
307 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); 284 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
308} 285}
309 286
310static inline void 287static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
311__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
312{ 288{
313 while (count--) 289 while (count--)
314 outl(*vaddr++, io_addr); 290 outl(cpu_to_le32(*vaddr++), io_addr);
315} 291}
316 292
317static inline u8 293static inline u8 inb(u32 addr)
318__ixp4xx_inb(u32 addr)
319{ 294{
320 u32 n, byte_enables, data; 295 u32 n, byte_enables, data;
321 n = addr % 4; 296 n = addr % 4;
@@ -326,15 +301,13 @@ __ixp4xx_inb(u32 addr)
326 return data >> (8*n); 301 return data >> (8*n);
327} 302}
328 303
329static inline void 304static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
330__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
331{ 305{
332 while (count--) 306 while (count--)
333 *vaddr++ = inb(io_addr); 307 *vaddr++ = inb(io_addr);
334} 308}
335 309
336static inline u16 310static inline u16 inw(u32 addr)
337__ixp4xx_inw(u32 addr)
338{ 311{
339 u32 n, byte_enables, data; 312 u32 n, byte_enables, data;
340 n = addr % 4; 313 n = addr % 4;
@@ -345,15 +318,13 @@ __ixp4xx_inw(u32 addr)
345 return data>>(8*n); 318 return data>>(8*n);
346} 319}
347 320
348static inline void 321static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
349__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
350{ 322{
351 while (count--) 323 while (count--)
352 *vaddr++ = le16_to_cpu(inw(io_addr)); 324 *vaddr++ = le16_to_cpu(inw(io_addr));
353} 325}
354 326
355static inline u32 327static inline u32 inl(u32 addr)
356__ixp4xx_inl(u32 addr)
357{ 328{
358 u32 data; 329 u32 data;
359 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) 330 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
@@ -362,11 +333,10 @@ __ixp4xx_inl(u32 addr)
362 return data; 333 return data;
363} 334}
364 335
365static inline void 336static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
366__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
367{ 337{
368 while (count--) 338 while (count--)
369 *vaddr++ = inl(io_addr); 339 *vaddr++ = le32_to_cpu(inl(io_addr));
370} 340}
371 341
372#define PIO_OFFSET 0x10000UL 342#define PIO_OFFSET 0x10000UL
@@ -374,194 +344,183 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
374 344
375#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ 345#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
376 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) 346 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
377static inline unsigned int 347
378__ixp4xx_ioread8(const void __iomem *addr) 348#define ioread8(p) ioread8(p)
349static inline unsigned int ioread8(const void __iomem *addr)
379{ 350{
380 unsigned long port = (unsigned long __force)addr; 351 unsigned long port = (unsigned long __force)addr;
381 if (__is_io_address(port)) 352 if (__is_io_address(port))
382 return (unsigned int)__ixp4xx_inb(port & PIO_MASK); 353 return (unsigned int)inb(port & PIO_MASK);
383 else 354 else
384#ifndef CONFIG_IXP4XX_INDIRECT_PCI 355#ifndef CONFIG_IXP4XX_INDIRECT_PCI
385 return (unsigned int)__raw_readb(port); 356 return (unsigned int)__raw_readb(port);
386#else 357#else
387 return (unsigned int)__ixp4xx_readb(addr); 358 return (unsigned int)__indirect_readb(addr);
388#endif 359#endif
389} 360}
390 361
391static inline void 362#define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
392__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) 363static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
393{ 364{
394 unsigned long port = (unsigned long __force)addr; 365 unsigned long port = (unsigned long __force)addr;
395 if (__is_io_address(port)) 366 if (__is_io_address(port))
396 __ixp4xx_insb(port & PIO_MASK, vaddr, count); 367 insb(port & PIO_MASK, vaddr, count);
397 else 368 else
398#ifndef CONFIG_IXP4XX_INDIRECT_PCI 369#ifndef CONFIG_IXP4XX_INDIRECT_PCI
399 __raw_readsb(addr, vaddr, count); 370 __raw_readsb(addr, vaddr, count);
400#else 371#else
401 __ixp4xx_readsb(addr, vaddr, count); 372 __indirect_readsb(addr, vaddr, count);
402#endif 373#endif
403} 374}
404 375
405static inline unsigned int 376#define ioread16(p) ioread16(p)
406__ixp4xx_ioread16(const void __iomem *addr) 377static inline unsigned int ioread16(const void __iomem *addr)
407{ 378{
408 unsigned long port = (unsigned long __force)addr; 379 unsigned long port = (unsigned long __force)addr;
409 if (__is_io_address(port)) 380 if (__is_io_address(port))
410 return (unsigned int)__ixp4xx_inw(port & PIO_MASK); 381 return (unsigned int)inw(port & PIO_MASK);
411 else 382 else
412#ifndef CONFIG_IXP4XX_INDIRECT_PCI 383#ifndef CONFIG_IXP4XX_INDIRECT_PCI
413 return le16_to_cpu(__raw_readw((u32)port)); 384 return le16_to_cpu(__raw_readw((u32)port));
414#else 385#else
415 return (unsigned int)__ixp4xx_readw(addr); 386 return (unsigned int)__indirect_readw(addr);
416#endif 387#endif
417} 388}
418 389
419static inline void 390#define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
420__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) 391static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
392 u32 count)
421{ 393{
422 unsigned long port = (unsigned long __force)addr; 394 unsigned long port = (unsigned long __force)addr;
423 if (__is_io_address(port)) 395 if (__is_io_address(port))
424 __ixp4xx_insw(port & PIO_MASK, vaddr, count); 396 insw(port & PIO_MASK, vaddr, count);
425 else 397 else
426#ifndef CONFIG_IXP4XX_INDIRECT_PCI 398#ifndef CONFIG_IXP4XX_INDIRECT_PCI
427 __raw_readsw(addr, vaddr, count); 399 __raw_readsw(addr, vaddr, count);
428#else 400#else
429 __ixp4xx_readsw(addr, vaddr, count); 401 __indirect_readsw(addr, vaddr, count);
430#endif 402#endif
431} 403}
432 404
433static inline unsigned int 405#define ioread32(p) ioread32(p)
434__ixp4xx_ioread32(const void __iomem *addr) 406static inline unsigned int ioread32(const void __iomem *addr)
435{ 407{
436 unsigned long port = (unsigned long __force)addr; 408 unsigned long port = (unsigned long __force)addr;
437 if (__is_io_address(port)) 409 if (__is_io_address(port))
438 return (unsigned int)__ixp4xx_inl(port & PIO_MASK); 410 return (unsigned int)inl(port & PIO_MASK);
439 else { 411 else {
440#ifndef CONFIG_IXP4XX_INDIRECT_PCI 412#ifndef CONFIG_IXP4XX_INDIRECT_PCI
441 return le32_to_cpu((__force __le32)__raw_readl(addr)); 413 return le32_to_cpu((__force __le32)__raw_readl(addr));
442#else 414#else
443 return (unsigned int)__ixp4xx_readl(addr); 415 return (unsigned int)__indirect_readl(addr);
444#endif 416#endif
445 } 417 }
446} 418}
447 419
448static inline void 420#define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
449__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) 421static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
422 u32 count)
450{ 423{
451 unsigned long port = (unsigned long __force)addr; 424 unsigned long port = (unsigned long __force)addr;
452 if (__is_io_address(port)) 425 if (__is_io_address(port))
453 __ixp4xx_insl(port & PIO_MASK, vaddr, count); 426 insl(port & PIO_MASK, vaddr, count);
454 else 427 else
455#ifndef CONFIG_IXP4XX_INDIRECT_PCI 428#ifndef CONFIG_IXP4XX_INDIRECT_PCI
456 __raw_readsl(addr, vaddr, count); 429 __raw_readsl(addr, vaddr, count);
457#else 430#else
458 __ixp4xx_readsl(addr, vaddr, count); 431 __indirect_readsl(addr, vaddr, count);
459#endif 432#endif
460} 433}
461 434
462static inline void 435#define iowrite8(v, p) iowrite8(v, p)
463__ixp4xx_iowrite8(u8 value, void __iomem *addr) 436static inline void iowrite8(u8 value, void __iomem *addr)
464{ 437{
465 unsigned long port = (unsigned long __force)addr; 438 unsigned long port = (unsigned long __force)addr;
466 if (__is_io_address(port)) 439 if (__is_io_address(port))
467 __ixp4xx_outb(value, port & PIO_MASK); 440 outb(value, port & PIO_MASK);
468 else 441 else
469#ifndef CONFIG_IXP4XX_INDIRECT_PCI 442#ifndef CONFIG_IXP4XX_INDIRECT_PCI
470 __raw_writeb(value, port); 443 __raw_writeb(value, port);
471#else 444#else
472 __ixp4xx_writeb(value, addr); 445 __indirect_writeb(value, addr);
473#endif 446#endif
474} 447}
475 448
476static inline void 449#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
477__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) 450static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
451 u32 count)
478{ 452{
479 unsigned long port = (unsigned long __force)addr; 453 unsigned long port = (unsigned long __force)addr;
480 if (__is_io_address(port)) 454 if (__is_io_address(port))
481 __ixp4xx_outsb(port & PIO_MASK, vaddr, count); 455 outsb(port & PIO_MASK, vaddr, count);
482 else 456 else
483#ifndef CONFIG_IXP4XX_INDIRECT_PCI 457#ifndef CONFIG_IXP4XX_INDIRECT_PCI
484 __raw_writesb(addr, vaddr, count); 458 __raw_writesb(addr, vaddr, count);
485#else 459#else
486 __ixp4xx_writesb(addr, vaddr, count); 460 __indirect_writesb(addr, vaddr, count);
487#endif 461#endif
488} 462}
489 463
490static inline void 464#define iowrite16(v, p) iowrite16(v, p)
491__ixp4xx_iowrite16(u16 value, void __iomem *addr) 465static inline void iowrite16(u16 value, void __iomem *addr)
492{ 466{
493 unsigned long port = (unsigned long __force)addr; 467 unsigned long port = (unsigned long __force)addr;
494 if (__is_io_address(port)) 468 if (__is_io_address(port))
495 __ixp4xx_outw(value, port & PIO_MASK); 469 outw(value, port & PIO_MASK);
496 else 470 else
497#ifndef CONFIG_IXP4XX_INDIRECT_PCI 471#ifndef CONFIG_IXP4XX_INDIRECT_PCI
498 __raw_writew(cpu_to_le16(value), addr); 472 __raw_writew(cpu_to_le16(value), addr);
499#else 473#else
500 __ixp4xx_writew(value, addr); 474 __indirect_writew(value, addr);
501#endif 475#endif
502} 476}
503 477
504static inline void 478#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
505__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) 479static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
480 u32 count)
506{ 481{
507 unsigned long port = (unsigned long __force)addr; 482 unsigned long port = (unsigned long __force)addr;
508 if (__is_io_address(port)) 483 if (__is_io_address(port))
509 __ixp4xx_outsw(port & PIO_MASK, vaddr, count); 484 outsw(port & PIO_MASK, vaddr, count);
510 else 485 else
511#ifndef CONFIG_IXP4XX_INDIRECT_PCI 486#ifndef CONFIG_IXP4XX_INDIRECT_PCI
512 __raw_writesw(addr, vaddr, count); 487 __raw_writesw(addr, vaddr, count);
513#else 488#else
514 __ixp4xx_writesw(addr, vaddr, count); 489 __indirect_writesw(addr, vaddr, count);
515#endif 490#endif
516} 491}
517 492
518static inline void 493#define iowrite32(v, p) iowrite32(v, p)
519__ixp4xx_iowrite32(u32 value, void __iomem *addr) 494static inline void iowrite32(u32 value, void __iomem *addr)
520{ 495{
521 unsigned long port = (unsigned long __force)addr; 496 unsigned long port = (unsigned long __force)addr;
522 if (__is_io_address(port)) 497 if (__is_io_address(port))
523 __ixp4xx_outl(value, port & PIO_MASK); 498 outl(value, port & PIO_MASK);
524 else 499 else
525#ifndef CONFIG_IXP4XX_INDIRECT_PCI 500#ifndef CONFIG_IXP4XX_INDIRECT_PCI
526 __raw_writel((u32 __force)cpu_to_le32(value), addr); 501 __raw_writel((u32 __force)cpu_to_le32(value), addr);
527#else 502#else
528 __ixp4xx_writel(value, addr); 503 __indirect_writel(value, addr);
529#endif 504#endif
530} 505}
531 506
532static inline void 507#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
533__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) 508static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
509 u32 count)
534{ 510{
535 unsigned long port = (unsigned long __force)addr; 511 unsigned long port = (unsigned long __force)addr;
536 if (__is_io_address(port)) 512 if (__is_io_address(port))
537 __ixp4xx_outsl(port & PIO_MASK, vaddr, count); 513 outsl(port & PIO_MASK, vaddr, count);
538 else 514 else
539#ifndef CONFIG_IXP4XX_INDIRECT_PCI 515#ifndef CONFIG_IXP4XX_INDIRECT_PCI
540 __raw_writesl(addr, vaddr, count); 516 __raw_writesl(addr, vaddr, count);
541#else 517#else
542 __ixp4xx_writesl(addr, vaddr, count); 518 __indirect_writesl(addr, vaddr, count);
543#endif 519#endif
544} 520}
545 521
546#define ioread8(p) __ixp4xx_ioread8(p)
547#define ioread16(p) __ixp4xx_ioread16(p)
548#define ioread32(p) __ixp4xx_ioread32(p)
549
550#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
551#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
552#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
553
554#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
555#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
556#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
557
558#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
559#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
560#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
561
562#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) 522#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
563#define ioport_unmap(addr) 523#define ioport_unmap(addr)
564#endif // !CONFIG_PCI 524#endif /* CONFIG_PCI */
565
566#endif // __ASM_ARM_ARCH_IO_H
567 525
526#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h
index f4d74de1566a..7e6d4cce7c27 100644
--- a/arch/arm/mach-ixp4xx/include/mach/irqs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h
@@ -15,7 +15,6 @@
15#ifndef _ARCH_IXP4XX_IRQS_H_ 15#ifndef _ARCH_IXP4XX_IRQS_H_
16#define _ARCH_IXP4XX_IRQS_H_ 16#define _ARCH_IXP4XX_IRQS_H_
17 17
18
19#define IRQ_IXP4XX_NPEA 0 18#define IRQ_IXP4XX_NPEA 0
20#define IRQ_IXP4XX_NPEB 1 19#define IRQ_IXP4XX_NPEB 1
21#define IRQ_IXP4XX_NPEC 2 20#define IRQ_IXP4XX_NPEC 2
@@ -59,6 +58,9 @@
59#define IRQ_IXP4XX_MCU_ECC 61 58#define IRQ_IXP4XX_MCU_ECC 61
60#define IRQ_IXP4XX_EXP_PE 62 59#define IRQ_IXP4XX_EXP_PE 62
61 60
61#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n)
62#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n)
63
62/* 64/*
63 * Only first 32 sources are valid if running on IXP42x systems 65 * Only first 32 sources are valid if running on IXP42x systems
64 */ 66 */
@@ -70,69 +72,4 @@
70 72
71#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) 73#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
72 74
73/*
74 * IXDP425 board IRQs
75 */
76#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
77#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
78#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
79#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
80
81/*
82 * Gateworks Avila board IRQs
83 */
84#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11
85#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10
86#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9
87#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8
88
89
90/*
91 * PrPMC1100 Board IRQs
92 */
93#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
94#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
95#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
96#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
97
98/*
99 * ADI Coyote Board IRQs
100 */
101#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
102#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
103#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
104
105/*
106 * NSLU2 board IRQs
107 */
108#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11
109#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
110#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
111
112/*
113 * NAS100D board IRQs
114 */
115#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
116#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
117#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
118#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
119#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
120
121/*
122 * D-Link DSM-G600 RevA board IRQs
123 */
124#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11
125#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10
126#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9
127#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8
128#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
129#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
130
131/*
132 * Freecom FSG-3 Board IRQs
133 */
134#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
135#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
136#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
137
138#endif 75#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
deleted file mode 100644
index 2cafe65ebfee..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/ixdp425.h
3 *
4 * IXDP425 platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19#define IXDP425_SDA_PIN 7
20#define IXDP425_SCL_PIN 6
21
22/*
23 * IXDP425 PCI IRQs
24 */
25#define IXDP425_PCI_MAX_DEV 4
26#define IXDP425_PCI_IRQ_LINES 4
27
28
29/* PCI controller GPIO to IRQ pin mappings */
30#define IXDP425_PCI_INTA_PIN 11
31#define IXDP425_PCI_INTB_PIN 10
32#define IXDP425_PCI_INTC_PIN 9
33#define IXDP425_PCI_INTD_PIN 8
34
35/* NAND Flash pins */
36#define IXDP425_NAND_NCE_PIN 12
37
38#define IXDP425_NAND_CMD_BYTE 0x01
39#define IXDP425_NAND_ADDR_BYTE 0x02
diff --git a/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/arch/arm/mach-ixp4xx/include/mach/nas100d.h
deleted file mode 100644
index 3771d62a9748..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/nas100d.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/nas100d.h
3 *
4 * NAS100D platform specific definitions
5 *
6 * Copyright (c) 2005 Tower Technologies
7 *
8 * Author: Alessandro Zummo <a.zummo@towertech.it>
9 *
10 * based on ixdp425.h:
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <mach/hardware.h>"
20#endif
21
22#define NAS100D_SDA_PIN 5
23#define NAS100D_SCL_PIN 6
24
25/*
26 * NAS100D PCI IRQs
27 */
28#define NAS100D_PCI_MAX_DEV 3
29#define NAS100D_PCI_IRQ_LINES 3
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define NAS100D_PCI_INTA_PIN 11
34#define NAS100D_PCI_INTB_PIN 10
35#define NAS100D_PCI_INTC_PIN 9
36#define NAS100D_PCI_INTD_PIN 8
37#define NAS100D_PCI_INTE_PIN 7
38
39/* Buttons */
40
41#define NAS100D_PB_GPIO 14 /* power button */
42#define NAS100D_RB_GPIO 4 /* reset button */
43
44/* Power control */
45
46#define NAS100D_PO_GPIO 12 /* power off */
47
48/* LEDs */
49
50#define NAS100D_LED_WLAN_GPIO 0
51#define NAS100D_LED_DISK_GPIO 3
52#define NAS100D_LED_PWR_GPIO 15
diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h
index 37d0511689dc..e320db2457ae 100644
--- a/arch/arm/mach-ixp4xx/include/mach/npe.h
+++ b/arch/arm/mach-ixp4xx/include/mach/npe.h
@@ -33,7 +33,7 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what);
33int npe_recv_message(struct npe *npe, void *msg, const char *what); 33int npe_recv_message(struct npe *npe, void *msg, const char *what);
34int npe_send_recv_message(struct npe *npe, void *msg, const char *what); 34int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
35int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); 35int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
36struct npe *npe_request(int id); 36struct npe *npe_request(unsigned id);
37void npe_release(struct npe *npe); 37void npe_release(struct npe *npe);
38 38
39#endif /* __IXP4XX_NPE_H */ 39#endif /* __IXP4XX_NPE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/arch/arm/mach-ixp4xx/include/mach/nslu2.h
deleted file mode 100644
index 85d00adbfb92..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/nslu2.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/nslu2.h
3 *
4 * NSLU2 platform specific definitions
5 *
6 * Author: Mark Rakes <mrakes AT mac.com>
7 * Maintainers: http://www.nslu2-linux.org
8 *
9 * based on ixdp425.h:
10 * Copyright 2004 (c) MontaVista, Software, Inc.
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H__
18#error "Do not include this directly, instead #include <mach/hardware.h>"
19#endif
20
21#define NSLU2_SDA_PIN 7
22#define NSLU2_SCL_PIN 6
23
24/*
25 * NSLU2 PCI IRQs
26 */
27#define NSLU2_PCI_MAX_DEV 3
28#define NSLU2_PCI_IRQ_LINES 3
29
30
31/* PCI controller GPIO to IRQ pin mappings */
32#define NSLU2_PCI_INTA_PIN 11
33#define NSLU2_PCI_INTB_PIN 10
34#define NSLU2_PCI_INTC_PIN 9
35#define NSLU2_PCI_INTD_PIN 8
36
37/* NSLU2 Timer */
38#define NSLU2_FREQ 66000000
39
40/* Buttons */
41
42#define NSLU2_PB_GPIO 5 /* power button */
43#define NSLU2_PO_GPIO 8 /* power off */
44#define NSLU2_RB_GPIO 12 /* reset button */
45
46/* Buzzer */
47
48#define NSLU2_GPIO_BUZZ 4
49
50/* LEDs */
51
52#define NSLU2_LED_RED_GPIO 0
53#define NSLU2_LED_GRN_GPIO 1
54#define NSLU2_LED_DISK1_GPIO 3
55#define NSLU2_LED_DISK2_GPIO 2
diff --git a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
deleted file mode 100644
index 17274a2e3dec..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
3 *
4 * Motorolla PrPMC1100 platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
20#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
21
22#define PRPMC1100_PCI_MIN_DEVID 10
23#define PRPMC1100_PCI_MAX_DEVID 16
24#define PRPMC1100_PCI_IRQ_LINES 4
25
26
27/* PCI controller GPIO to IRQ pin mappings */
28#define PRPMC1100_PCI_INTA_PIN 11
29#define PRPMC1100_PCI_INTB_PIN 10
30#define PRPMC1100_PCI_INTC_PIN 9
31#define PRPMC1100_PCI_INTD_PIN 8
32
33
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index 89ce3ee84698..2c3f93c3eb79 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -10,6 +10,6 @@
10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the 10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
11 * timer register ignores the bottom 2 bits of the LATCH value. 11 * timer register ignores the bottom 2 bits of the LATCH value.
12 */ 12 */
13#define FREQ 66666666 13#define FREQ 66666000
14#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) 14#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
15 15
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 64c29aacaac9..1ba165a6edac 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-ixp4xx/ixdp425-pci.c 2 * arch/arm/mach-ixp4xx/ixdp425-pci.c
3 * 3 *
4 * IXDP425 board-level PCI initialization 4 * IXDP425 board-level PCI initialization
5 * 5 *
@@ -19,39 +19,43 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22
23#include <asm/mach/pci.h> 22#include <asm/mach/pci.h>
24#include <asm/irq.h> 23#include <asm/irq.h>
25#include <mach/hardware.h> 24#include <mach/hardware.h>
26#include <asm/mach-types.h> 25#include <asm/mach-types.h>
27 26
27#define MAX_DEV 4
28#define IRQ_LINES 4
29
30/* PCI controller GPIO to IRQ pin mappings */
31#define INTA 11
32#define INTB 10
33#define INTC 9
34#define INTD 8
35
36
28void __init ixdp425_pci_preinit(void) 37void __init ixdp425_pci_preinit(void)
29{ 38{
30 set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 39 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
31 set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 40 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
32 set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 41 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
33 set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW); 42 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
34
35 ixp4xx_pci_preinit(); 43 ixp4xx_pci_preinit();
36} 44}
37 45
38static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 46static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
39{ 47{
40 static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = { 48 static int pci_irq_table[IRQ_LINES] = {
41 IRQ_IXDP425_PCI_INTA, 49 IXP4XX_GPIO_IRQ(INTA),
42 IRQ_IXDP425_PCI_INTB, 50 IXP4XX_GPIO_IRQ(INTB),
43 IRQ_IXDP425_PCI_INTC, 51 IXP4XX_GPIO_IRQ(INTC),
44 IRQ_IXDP425_PCI_INTD 52 IXP4XX_GPIO_IRQ(INTD)
45 }; 53 };
46 54
47 int irq = -1; 55 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
48 56 return pci_irq_table[(slot + pin - 2) % 4];
49 if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV &&
50 pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) {
51 irq = pci_irq_table[(slot + pin - 2) % 4];
52 }
53 57
54 return irq; 58 return -1;
55} 59}
56 60
57struct hw_pci ixdp425_pci __initdata = { 61struct hw_pci ixdp425_pci __initdata = {
@@ -72,4 +76,3 @@ int __init ixdp425_pci_init(void)
72} 76}
73 77
74subsys_initcall(ixdp425_pci_init); 78subsys_initcall(ixdp425_pci_init);
75
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index f4a0c1bc1331..bbb768988845 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-ixp4xx/ixdp425-setup.c 2 * arch/arm/mach-ixp4xx/ixdp425-setup.c
3 * 3 *
4 * IXDP425/IXCDP1100 board-setup 4 * IXDP425/IXCDP1100 board-setup
5 * 5 *
6 * Copyright (C) 2003-2005 MontaVista Software, Inc. 6 * Copyright (C) 2003-2005 MontaVista Software, Inc.
7 * 7 *
@@ -21,7 +21,6 @@
21#include <linux/mtd/nand.h> 21#include <linux/mtd/nand.h>
22#include <linux/mtd/partitions.h> 22#include <linux/mtd/partitions.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24
25#include <asm/types.h> 24#include <asm/types.h>
26#include <asm/setup.h> 25#include <asm/setup.h>
27#include <asm/memory.h> 26#include <asm/memory.h>
@@ -31,6 +30,15 @@
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
33 32
33#define IXDP425_SDA_PIN 7
34#define IXDP425_SCL_PIN 6
35
36/* NAND Flash pins */
37#define IXDP425_NAND_NCE_PIN 12
38
39#define IXDP425_NAND_CMD_BYTE 0x01
40#define IXDP425_NAND_ADDR_BYTE 0x02
41
34static struct flash_platform_data ixdp425_flash_data = { 42static struct flash_platform_data ixdp425_flash_data = {
35 .map_name = "cfi_probe", 43 .map_name = "cfi_probe",
36 .width = 2, 44 .width = 2,
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index 47ac69c7ec78..e8bb25778166 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -665,7 +665,7 @@ err:
665} 665}
666 666
667 667
668struct npe *npe_request(int id) 668struct npe *npe_request(unsigned id)
669{ 669{
670 if (id < NPE_COUNT) 670 if (id < NPE_COUNT)
671 if (npe_tab[id].valid) 671 if (npe_tab[id].valid)
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index 1088426fdcee..d0cea34cf61e 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -18,37 +18,42 @@
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21
22#include <asm/mach/pci.h> 21#include <asm/mach/pci.h>
23#include <asm/mach-types.h> 22#include <asm/mach-types.h>
24 23
24#define MAX_DEV 3
25#define IRQ_LINES 3
26
27/* PCI controller GPIO to IRQ pin mappings */
28#define INTA 11
29#define INTB 10
30#define INTC 9
31#define INTD 8
32#define INTE 7
33
25void __init nas100d_pci_preinit(void) 34void __init nas100d_pci_preinit(void)
26{ 35{
27 set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 36 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
28 set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 37 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
29 set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 38 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
30 set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); 39 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
31 set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); 40 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
32
33 ixp4xx_pci_preinit(); 41 ixp4xx_pci_preinit();
34} 42}
35 43
36static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 44static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
37{ 45{
38 static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = 46 static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
39 { 47 { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
40 { IRQ_NAS100D_PCI_INTA, -1, -1 }, 48 { IXP4XX_GPIO_IRQ(INTB), -1, -1 },
41 { IRQ_NAS100D_PCI_INTB, -1, -1 }, 49 { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
42 { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, 50 IXP4XX_GPIO_IRQ(INTE) },
43 }; 51 };
44 52
45 int irq = -1; 53 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
46 54 return pci_irq_table[slot - 1][pin - 1];
47 if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV &&
48 pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES)
49 irq = pci_irq_table[slot-1][pin-1];
50 55
51 return irq; 56 return -1;
52} 57}
53 58
54struct hw_pci __initdata nas100d_pci = { 59struct hw_pci __initdata nas100d_pci = {
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 921c947b5b6b..e3ee880aa1e6 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -29,12 +29,26 @@
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/i2c-gpio.h> 30#include <linux/i2c-gpio.h>
31#include <linux/io.h> 31#include <linux/io.h>
32
33#include <asm/mach-types.h> 32#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
35#include <asm/mach/flash.h> 34#include <asm/mach/flash.h>
36#include <asm/gpio.h> 35#include <asm/gpio.h>
37 36
37#define NAS100D_SDA_PIN 5
38#define NAS100D_SCL_PIN 6
39
40/* Buttons */
41#define NAS100D_PB_GPIO 14 /* power button */
42#define NAS100D_RB_GPIO 4 /* reset button */
43
44/* Power control */
45#define NAS100D_PO_GPIO 12 /* power off */
46
47/* LEDs */
48#define NAS100D_LED_WLAN_GPIO 0
49#define NAS100D_LED_DISK_GPIO 3
50#define NAS100D_LED_PWR_GPIO 15
51
38static struct flash_platform_data nas100d_flash_data = { 52static struct flash_platform_data nas100d_flash_data = {
39 .map_name = "cfi_probe", 53 .map_name = "cfi_probe",
40 .width = 2, 54 .width = 2,
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 4429b8448b61..1eb5a90470bc 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -18,35 +18,38 @@
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21
22#include <asm/mach/pci.h> 21#include <asm/mach/pci.h>
23#include <asm/mach-types.h> 22#include <asm/mach-types.h>
24 23
24#define MAX_DEV 3
25#define IRQ_LINES 3
26
27/* PCI controller GPIO to IRQ pin mappings */
28#define INTA 11
29#define INTB 10
30#define INTC 9
31#define INTD 8
32
25void __init nslu2_pci_preinit(void) 33void __init nslu2_pci_preinit(void)
26{ 34{
27 set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 35 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
28 set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 36 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
29 set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 37 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
30
31 ixp4xx_pci_preinit(); 38 ixp4xx_pci_preinit();
32} 39}
33 40
34static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 41static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
35{ 42{
36 static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = { 43 static int pci_irq_table[IRQ_LINES] = {
37 IRQ_NSLU2_PCI_INTA, 44 IXP4XX_GPIO_IRQ(INTA),
38 IRQ_NSLU2_PCI_INTB, 45 IXP4XX_GPIO_IRQ(INTB),
39 IRQ_NSLU2_PCI_INTC, 46 IXP4XX_GPIO_IRQ(INTC),
40 }; 47 };
41 48
42 int irq = -1; 49 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
43 50 return pci_irq_table[(slot + pin - 2) % IRQ_LINES];
44 if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV &&
45 pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) {
46 irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES];
47 }
48 51
49 return irq; 52 return -1;
50} 53}
51 54
52struct hw_pci __initdata nslu2_pci = { 55struct hw_pci __initdata nslu2_pci = {
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index ff6a08d02cc4..c14e0034be4b 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -26,13 +26,32 @@
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/i2c-gpio.h> 27#include <linux/i2c-gpio.h>
28#include <linux/io.h> 28#include <linux/io.h>
29
30#include <asm/mach-types.h> 29#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
33#include <asm/mach/time.h> 32#include <asm/mach/time.h>
34#include <asm/gpio.h> 33#include <asm/gpio.h>
35 34
35#define NSLU2_SDA_PIN 7
36#define NSLU2_SCL_PIN 6
37
38/* NSLU2 Timer */
39#define NSLU2_FREQ 66000000
40
41/* Buttons */
42#define NSLU2_PB_GPIO 5 /* power button */
43#define NSLU2_PO_GPIO 8 /* power off */
44#define NSLU2_RB_GPIO 12 /* reset button */
45
46/* Buzzer */
47#define NSLU2_GPIO_BUZZ 4
48
49/* LEDs */
50#define NSLU2_LED_RED_GPIO 0
51#define NSLU2_LED_GRN_GPIO 1
52#define NSLU2_LED_DISK1_GPIO 3
53#define NSLU2_LED_DISK2_GPIO 2
54
36static struct flash_platform_data nslu2_flash_data = { 55static struct flash_platform_data nslu2_flash_data = {
37 .map_name = "cfi_probe", 56 .map_name = "cfi_probe",
38 .width = 2, 57 .width = 2,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 11:57:46 -0500