diff options
author | Bjorn Helgaas <bjorn.helgaas@hp.com> | 2006-10-12 18:20:59 -0400 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2006-10-17 17:53:52 -0400 |
commit | c12fb1885787dcc2e20c4b88149e1e607e1293b2 (patch) | |
tree | b607d2cf6e4915b5005a2c98a7efea0742103e28 /arch | |
parent | accaddb27a2d544e38e10ff2a2782b33bbbad913 (diff) |
[IA64] remove unused PAL_CALL_IC_OFF
Linux maps PAL instructions with an ITR, but uses a DTC for PAL data.
Section 11.10.2.1.3, "Making PAL Procedures Calls in Physical or Virtual
Mode," of the SDM (rev 2.2), says we must therefore make all PAL calls
with PSR.ic = 1 so that Linux can handle any TLB faults.
PAL_CALL_IC_OFF is currently unused, and as long as we use the ITR + DTC
strategy, we can't use it. So remove it. I also removed the code in
ia64_pal_call_static() that conditionally cleared PSR.ic.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/ia64/kernel/pal.S | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/ia64/kernel/pal.S b/arch/ia64/kernel/pal.S index ebaf1e685f5e..5f50e6bbc686 100644 --- a/arch/ia64/kernel/pal.S +++ b/arch/ia64/kernel/pal.S | |||
@@ -50,12 +50,10 @@ END(ia64_pal_default_handler) | |||
50 | * | 50 | * |
51 | * in0 Index of PAL service | 51 | * in0 Index of PAL service |
52 | * in1 - in3 Remaining PAL arguments | 52 | * in1 - in3 Remaining PAL arguments |
53 | * in4 1 ==> clear psr.ic, 0 ==> don't clear psr.ic | ||
54 | * | ||
55 | */ | 53 | */ |
56 | GLOBAL_ENTRY(ia64_pal_call_static) | 54 | GLOBAL_ENTRY(ia64_pal_call_static) |
57 | .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5) | 55 | .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4) |
58 | alloc loc1 = ar.pfs,5,5,0,0 | 56 | alloc loc1 = ar.pfs,4,5,0,0 |
59 | movl loc2 = pal_entry_point | 57 | movl loc2 = pal_entry_point |
60 | 1: { | 58 | 1: { |
61 | mov r28 = in0 | 59 | mov r28 = in0 |
@@ -64,7 +62,6 @@ GLOBAL_ENTRY(ia64_pal_call_static) | |||
64 | } | 62 | } |
65 | ;; | 63 | ;; |
66 | ld8 loc2 = [loc2] // loc2 <- entry point | 64 | ld8 loc2 = [loc2] // loc2 <- entry point |
67 | tbit.nz p6,p7 = in4, 0 | ||
68 | adds r8 = 1f-1b,r8 | 65 | adds r8 = 1f-1b,r8 |
69 | mov loc4=ar.rsc // save RSE configuration | 66 | mov loc4=ar.rsc // save RSE configuration |
70 | ;; | 67 | ;; |
@@ -74,13 +71,11 @@ GLOBAL_ENTRY(ia64_pal_call_static) | |||
74 | .body | 71 | .body |
75 | mov r30 = in2 | 72 | mov r30 = in2 |
76 | 73 | ||
77 | (p6) rsm psr.i | psr.ic | ||
78 | mov r31 = in3 | 74 | mov r31 = in3 |
79 | mov b7 = loc2 | 75 | mov b7 = loc2 |
80 | 76 | ||
81 | (p7) rsm psr.i | 77 | rsm psr.i |
82 | ;; | 78 | ;; |
83 | (p6) srlz.i | ||
84 | mov rp = r8 | 79 | mov rp = r8 |
85 | br.cond.sptk.many b7 | 80 | br.cond.sptk.many b7 |
86 | 1: mov psr.l = loc3 | 81 | 1: mov psr.l = loc3 |