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authorRalf Baechle <ralf@linux-mips.org>2006-04-02 08:16:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-04-18 22:14:19 -0400
commitb56bce9a25e8c117794fe74c1b9bf790de10d554 (patch)
treeb6996b9fe369fdfe6c2db9133f4289ac9ae8897d /arch
parent0428657d874edf228fcd5396bb0e095b806e954c (diff)
[MIPS] Jaguar: Fix build errors after the recent move of Marvell headers.
Some things were renamed because the PPC variant of the MV-643XX now uses the same header and the Jaguar code didn't catch up on that. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 91d9637143d7..1379c76845dc 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -381,24 +381,24 @@ void __init plat_setup(void)
381 * shut down ethernet ports, just to be sure our memory doesn't get 381 * shut down ethernet ports, just to be sure our memory doesn't get
382 * corrupted by random ethernet traffic. 382 * corrupted by random ethernet traffic.
383 */ 383 */
384 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); 384 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
385 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); 385 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
386 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); 386 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
387 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); 387 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
388 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); 388 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
389 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); 389 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
390 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); 390 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
391 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); 391 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
392 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); 392 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
393 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); 393 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
394 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); 394 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
395 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); 395 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
396 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), 396 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
397 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); 397 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
398 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), 398 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
399 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); 399 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
400 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2), 400 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
401 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); 401 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
402 402
403 /* Turn off the Bit-Error LED */ 403 /* Turn off the Bit-Error LED */
404 JAGUAR_FPGA_WRITE(0x80, CLR); 404 JAGUAR_FPGA_WRITE(0x80, CLR);