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authorElizabeth Oldham <beth@mips.com>2006-08-17 07:39:21 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-09-27 08:37:36 -0400
commita94d702049569401c65b579d0751ce282f962b41 (patch)
tree4272d85203da3648ef1f6feea02c24465e132057 /arch
parent6e74bae9a0c2fc59ffb0e25fec074b4ac0ac7048 (diff)
[MIPS] MT: Fix setting of XTC.
XTC can only be set if VPA is clear, which it may not be. There is also the possibility of a back to back c0 register access hazard to take care of. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/vpe.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 9ee0ec2cd067..51ddd2166898 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -768,10 +768,16 @@ int vpe_run(struct vpe * v)
768 */ 768 */
769 write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor); 769 write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor);
770 770
771 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
772
773 back_to_back_c0_hazard();
774
771 /* Set up the XTC bit in vpeconf0 to point at our tc */ 775 /* Set up the XTC bit in vpeconf0 to point at our tc */
772 write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) 776 write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
773 | (t->index << VPECONF0_XTC_SHIFT)); 777 | (t->index << VPECONF0_XTC_SHIFT));
774 778
779 back_to_back_c0_hazard();
780
775 /* enable this VPE */ 781 /* enable this VPE */
776 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); 782 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
777 783