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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-06-24 10:26:38 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-03 14:14:27 -0400
commit8986d2f50e1a9ba63f64ccbf59181886aa7898c3 (patch)
tree0fde3d8ff52cb4cac35348c2464939fc7b6fc9e9 /arch
parent7e3297dc280f88ec0c6619a895f3d449776f952e (diff)
[MIPS] cevt-txx9: Reset timer counter on initialization
The txx9_tmr_init() will not clear a timer counter register in a certain case. The counter register is cleared on 1->0 transition of TCE bit if CRE=1. So just clearing the TCE bit is not enough. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/cevt-txx9.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 795cb8fb0d74..b5fc4eb412d2 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
161 struct txx9_tmr_reg __iomem *tmrptr; 161 struct txx9_tmr_reg __iomem *tmrptr;
162 162
163 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 163 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
164 /* Start once to make CounterResetEnable effective */
165 __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
166 /* Stop and reset the counter */
164 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); 167 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
165 __raw_writel(0, &tmrptr->tisr); 168 __raw_writel(0, &tmrptr->tisr);
166 __raw_writel(0xffffffff, &tmrptr->cpra); 169 __raw_writel(0xffffffff, &tmrptr->cpra);