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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2008-04-30 15:25:55 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-05-12 11:46:54 -0400
commit7916c3548e53bffb0545a1d0dc7fde86d79add92 (patch)
tree6e0020f6f24865343938cb56ef537fd9eb0297df /arch
parentabd14cc00d940b8b5b4fc92be23f656b57c6ecfe (diff)
[MIPS] Pb1000 code style cleanup
Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - brace not on the same line with condition in the 'switch' statement; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - properly indent the 'switch' statement; - remove needless parentheses; - insert spaces between operator and its operands; - replace numeric literals/expressions with the matching macros; - remove useless #if dirctive from board_setup(); - remove unneeded numeric literal type casts; - remove space after the type cast's closing parenthesis; - replace spaces after the macro name with tabs in the #define directives, and sometimes insert spaces there; - remove excess new lines; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first/last line; - combine some comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/au1000/pb1000/Makefile8
-rw-r--r--arch/mips/au1000/pb1000/board_setup.c110
-rw-r--r--arch/mips/au1000/pb1000/init.c20
3 files changed, 70 insertions, 68 deletions
diff --git a/arch/mips/au1000/pb1000/Makefile b/arch/mips/au1000/pb1000/Makefile
index daa1a507e72f..99bbec0ca41b 100644
--- a/arch/mips/au1000/pb1000/Makefile
+++ b/arch/mips/au1000/pb1000/Makefile
@@ -1,8 +1,8 @@
1# 1#
2# Copyright 2000 MontaVista Software Inc. 2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. 3# Author: MontaVista Software, Inc. <source@mvista.com>
4# ppopov@mvista.com or source@mvista.com 4#
5# Makefile for the Alchemy Semiconductor Pb1000 board.
5# 6#
6# Makefile for the Alchemy Semiconductor PB1000 board.
7 7
8lib-y := init.o board_setup.o irqmap.o 8lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 33f15acc1b17..a06c653596cb 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright 2000 MontaVista Software Inc. 2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. 3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 * ppopov@mvista.com or source@mvista.com
5 * 4 *
6 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -40,106 +39,108 @@ void __init board_setup(void)
40 u32 sys_freqctrl, sys_clksrc; 39 u32 sys_freqctrl, sys_clksrc;
41 u32 prid = read_c0_prid(); 40 u32 prid = read_c0_prid();
42 41
43 // set AUX clock to 12MHz * 8 = 96 MHz 42 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
44 au_writel(8, SYS_AUXPLL); 43 au_writel(8, SYS_AUXPLL);
45 au_writel(0, SYS_PINSTATERD); 44 au_writel(0, SYS_PINSTATERD);
46 udelay(100); 45 udelay(100);
47 46
48#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 47#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
49 /* zero and disable FREQ2 */ 48 /* Zero and disable FREQ2 */
50 sys_freqctrl = au_readl(SYS_FREQCTRL0); 49 sys_freqctrl = au_readl(SYS_FREQCTRL0);
51 sys_freqctrl &= ~0xFFF00000; 50 sys_freqctrl &= ~0xFFF00000;
52 au_writel(sys_freqctrl, SYS_FREQCTRL0); 51 au_writel(sys_freqctrl, SYS_FREQCTRL0);
53 52
54 /* zero and disable USBH/USBD clocks */ 53 /* Zero and disable USBH/USBD clocks */
55 sys_clksrc = au_readl(SYS_CLKSRC); 54 sys_clksrc = au_readl(SYS_CLKSRC);
56 sys_clksrc &= ~0x00007FE0; 55 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
56 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
57 au_writel(sys_clksrc, SYS_CLKSRC); 57 au_writel(sys_clksrc, SYS_CLKSRC);
58 58
59 sys_freqctrl = au_readl(SYS_FREQCTRL0); 59 sys_freqctrl = au_readl(SYS_FREQCTRL0);
60 sys_freqctrl &= ~0xFFF00000; 60 sys_freqctrl &= ~0xFFF00000;
61 61
62 sys_clksrc = au_readl(SYS_CLKSRC); 62 sys_clksrc = au_readl(SYS_CLKSRC);
63 sys_clksrc &= ~0x00007FE0; 63 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
64 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
64 65
65 switch (prid & 0x000000FF) 66 switch (prid & 0x000000FF) {
66 {
67 case 0x00: /* DA */ 67 case 0x00: /* DA */
68 case 0x01: /* HA */ 68 case 0x01: /* HA */
69 case 0x02: /* HB */ 69 case 0x02: /* HB */
70 /* CPU core freq to 48MHz to slow it way down... */ 70 /* CPU core freq to 48 MHz to slow it way down... */
71 au_writel(4, SYS_CPUPLL); 71 au_writel(4, SYS_CPUPLL);
72 72
73 /* 73 /*
74 * Setup 48MHz FREQ2 from CPUPLL for USB Host 74 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
75 */ 75 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
76 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ 76 */
77 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); 77 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
78 au_writel(sys_freqctrl, SYS_FREQCTRL0); 78 au_writel(sys_freqctrl, SYS_FREQCTRL0);
79 79
80 /* CPU core freq to 384MHz */ 80 /* CPU core freq to 384 MHz */
81 au_writel(0x20, SYS_CPUPLL); 81 au_writel(0x20, SYS_CPUPLL);
82 82
83 printk("Au1000: 48MHz OHCI workaround enabled\n"); 83 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
84 break; 84 break;
85 85
86 default: /* HC and newer */ 86 default: /* HC and newer */
87 // FREQ2 = aux/2 = 48 MHz 87 /* FREQ2 = aux / 2 = 48 MHz */
88 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); 88 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
89 au_writel(sys_freqctrl, SYS_FREQCTRL0); 89 SYS_FC_FE2 | SYS_FC_FS2;
90 au_writel(sys_freqctrl, SYS_FREQCTRL0);
90 break; 91 break;
91 } 92 }
92 93
93 /* 94 /*
94 * Route 48MHz FREQ2 into USB Host and/or Device 95 * Route 48 MHz FREQ2 into USB Host and/or Device
95 */ 96 */
96#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 97 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
97 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
98#endif
99 au_writel(sys_clksrc, SYS_CLKSRC); 98 au_writel(sys_clksrc, SYS_CLKSRC);
100 99
101 // configure pins GPIO[14:9] as GPIO 100 /* Configure pins GPIO[14:9] as GPIO */
102 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); 101 pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
103 102
104 // 2nd USB port is USB host 103 /* 2nd USB port is USB host */
105 pin_func |= 0x8000; 104 pin_func |= SYS_PF_USB;
106 105
107 au_writel(pin_func, SYS_PINFUNC); 106 au_writel(pin_func, SYS_PINFUNC);
108 au_writel(0x2800, SYS_TRIOUTCLR); 107 au_writel(0x2800, SYS_TRIOUTCLR);
109 au_writel(0x0030, SYS_OUTPUTCLR); 108 au_writel(0x0030, SYS_OUTPUTCLR);
110#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 109#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
111 110
112 // make gpio 15 an input (for interrupt line) 111 /* Make GPIO 15 an input (for interrupt line) */
113 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100); 112 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
114 // we don't need I2S, so make it available for GPIO[31:29] 113 /* We don't need I2S, so make it available for GPIO[31:29] */
115 pin_func |= (1<<5); 114 pin_func |= SYS_PF_I2S;
116 au_writel(pin_func, SYS_PINFUNC); 115 au_writel(pin_func, SYS_PINFUNC);
117 116
118 au_writel(0x8000, SYS_TRIOUTCLR); 117 au_writel(0x8000, SYS_TRIOUTCLR);
119 118
120 static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00); 119 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
121 au_writel(static_cfg0, MEM_STCFG0); 120 au_writel(static_cfg0, MEM_STCFG0);
122 121
123 // configure RCE2* for LCD 122 /* configure RCE2* for LCD */
124 au_writel(0x00000004, MEM_STCFG2); 123 au_writel(0x00000004, MEM_STCFG2);
125 124
126 // MEM_STTIME2 125 /* MEM_STTIME2 */
127 au_writel(0x09000000, MEM_STTIME2); 126 au_writel(0x09000000, MEM_STTIME2);
128 127
129 // Set 32-bit base address decoding for RCE2* 128 /* Set 32-bit base address decoding for RCE2* */
130 au_writel(0x10003ff0, MEM_STADDR2); 129 au_writel(0x10003ff0, MEM_STADDR2);
131 130
132 // PCI CPLD setup 131 /*
133 // expand CE0 to cover PCI 132 * PCI CPLD setup
133 * Expand CE0 to cover PCI
134 */
134 au_writel(0x11803e40, MEM_STADDR1); 135 au_writel(0x11803e40, MEM_STADDR1);
135 136
136 // burst visibility on 137 /* Burst visibility on */
137 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); 138 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
138 139
139 au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing 140 au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
140 au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA 141 au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
141 142
142 /* setup the static bus controller */ 143 /* Setup the static bus controller */
143 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ 144 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
144 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ 145 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
145 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ 146 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
@@ -151,17 +152,20 @@ void __init board_setup(void)
151 au_sync_delay(1); 152 au_sync_delay(1);
152#endif 153#endif
153 154
154 /* Enable Au1000 BCLK switching - note: sed1356 must not use 155 /*
155 * its BCLK (Au1000 LCLK) for any timings */ 156 * Enable Au1000 BCLK switching - note: sed1356 must not use
156 switch (prid & 0x000000FF) 157 * its BCLK (Au1000 LCLK) for any timings
157 { 158 */
159 switch (prid & 0x000000FF) {
158 case 0x00: /* DA */ 160 case 0x00: /* DA */
159 case 0x01: /* HA */ 161 case 0x01: /* HA */
160 case 0x02: /* HB */ 162 case 0x02: /* HB */
161 break; 163 break;
162 default: /* HC and newer */ 164 default: /* HC and newer */
163 /* Enable sys bus clock divider when IDLE state or no bus 165 /*
164 activity. */ 166 * Enable sys bus clock divider when IDLE state or no bus
167 * activity.
168 */
165 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); 169 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
166 break; 170 break;
167 } 171 }
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index 549447df71d6..3837365d613d 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -1,10 +1,9 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * PB1000 board setup 3 * Pb1000 board setup
4 * 4 *
5 * Copyright 2001 MontaVista Software Inc. 5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 * ppopov@mvista.com or source@mvista.com
8 * 7 *
9 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -44,16 +43,15 @@ void __init prom_init(void)
44 unsigned char *memsize_str; 43 unsigned char *memsize_str;
45 unsigned long memsize; 44 unsigned long memsize;
46 45
47 prom_argc = (int) fw_arg0; 46 prom_argc = (int)fw_arg0;
48 prom_argv = (char **) fw_arg1; 47 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **) fw_arg2; 48 prom_envp = (char **)fw_arg2;
50 49
51 prom_init_cmdline(); 50 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize"); 51 memsize_str = prom_getenv("memsize");
53 if (!memsize_str) { 52 if (!memsize_str)
54 memsize = 0x04000000; 53 memsize = 0x04000000;
55 } else { 54 else
56 memsize = simple_strtol(memsize_str, NULL, 0); 55 memsize = strict_strtol(memsize_str, 0, NULL);
57 }
58 add_memory_region(0, memsize, BOOT_MEM_RAM); 56 add_memory_region(0, memsize, BOOT_MEM_RAM);
59} 57}