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author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-01-12 06:07:32 -0500 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-01-12 06:07:32 -0500 |
commit | 68b5e4891c2a7a86d8fe65c29c025d7a7f2b0e35 (patch) | |
tree | f0cba9126de680dc05087ce7d27abfe6569b16a0 /arch | |
parent | ae04d1401577bb63151480a053057de58b8e10bb (diff) |
[ARM] i.MX: remove LCDC controller register definitions from imx-regs.h
The LCDC controller register definitions are now part of the driver
itself, so remove them from imx-regs.h to avoid redefitions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-imx/include/mach/imx-regs.h | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h index fb9de2733879..490297fc0e38 100644 --- a/arch/arm/mach-imx/include/mach/imx-regs.h +++ b/arch/arm/mach-imx/include/mach/imx-regs.h | |||
@@ -373,110 +373,4 @@ | |||
373 | #define TSTAT_CAPT (1<<1) | 373 | #define TSTAT_CAPT (1<<1) |
374 | #define TSTAT_COMP (1<<0) | 374 | #define TSTAT_COMP (1<<0) |
375 | 375 | ||
376 | /* | ||
377 | * LCD Controller | ||
378 | */ | ||
379 | |||
380 | #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) | ||
381 | |||
382 | #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) | ||
383 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | ||
384 | #define SIZE_YMAX(y) ( (y) & 0x1ff ) | ||
385 | |||
386 | #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) | ||
387 | #define VPW_VPW(x) ( (x) & 0x3ff ) | ||
388 | |||
389 | #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) | ||
390 | #define CPOS_CC1 (1<<31) | ||
391 | #define CPOS_CC0 (1<<30) | ||
392 | #define CPOS_OP (1<<28) | ||
393 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | ||
394 | #define CPOS_CYP(y) ((y) & 0x1ff) | ||
395 | |||
396 | #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) | ||
397 | #define LCWHB_BK_EN (1<<31) | ||
398 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) | ||
399 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) | ||
400 | #define LCWHB_BD(x) ((x) & 0xff) | ||
401 | |||
402 | #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) | ||
403 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) | ||
404 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) | ||
405 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) | ||
406 | |||
407 | #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) | ||
408 | #define PCR_TFT (1<<31) | ||
409 | #define PCR_COLOR (1<<30) | ||
410 | #define PCR_PBSIZ_1 (0<<28) | ||
411 | #define PCR_PBSIZ_2 (1<<28) | ||
412 | #define PCR_PBSIZ_4 (2<<28) | ||
413 | #define PCR_PBSIZ_8 (3<<28) | ||
414 | #define PCR_BPIX_1 (0<<25) | ||
415 | #define PCR_BPIX_2 (1<<25) | ||
416 | #define PCR_BPIX_4 (2<<25) | ||
417 | #define PCR_BPIX_8 (3<<25) | ||
418 | #define PCR_BPIX_12 (4<<25) | ||
419 | #define PCR_BPIX_16 (4<<25) | ||
420 | #define PCR_PIXPOL (1<<24) | ||
421 | #define PCR_FLMPOL (1<<23) | ||
422 | #define PCR_LPPOL (1<<22) | ||
423 | #define PCR_CLKPOL (1<<21) | ||
424 | #define PCR_OEPOL (1<<20) | ||
425 | #define PCR_SCLKIDLE (1<<19) | ||
426 | #define PCR_END_SEL (1<<18) | ||
427 | #define PCR_END_BYTE_SWAP (1<<17) | ||
428 | #define PCR_REV_VS (1<<16) | ||
429 | #define PCR_ACD_SEL (1<<15) | ||
430 | #define PCR_ACD(x) (((x) & 0x7f) << 8) | ||
431 | #define PCR_SCLK_SEL (1<<7) | ||
432 | #define PCR_SHARP (1<<6) | ||
433 | #define PCR_PCD(x) ((x) & 0x3f) | ||
434 | |||
435 | #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) | ||
436 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) | ||
437 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) | ||
438 | #define HCR_H_WAIT_2(x) ((x) & 0xff) | ||
439 | |||
440 | #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) | ||
441 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) | ||
442 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) | ||
443 | #define VCR_V_WAIT_2(x) ((x) & 0xff) | ||
444 | |||
445 | #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) | ||
446 | #define POS_POS(x) ((x) & 1f) | ||
447 | |||
448 | #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) | ||
449 | #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) | ||
450 | #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) | ||
451 | #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) | ||
452 | #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) | ||
453 | #define LSCR1_GRAY1(x) (((x) & 0xf)) | ||
454 | |||
455 | #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) | ||
456 | #define PWMR_CLS(x) (((x) & 0x1ff) << 16) | ||
457 | #define PWMR_LDMSK (1<<15) | ||
458 | #define PWMR_SCR1 (1<<10) | ||
459 | #define PWMR_SCR0 (1<<9) | ||
460 | #define PWMR_CC_EN (1<<8) | ||
461 | #define PWMR_PW(x) ((x) & 0xff) | ||
462 | |||
463 | #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) | ||
464 | #define DMACR_BURST (1<<31) | ||
465 | #define DMACR_HM(x) (((x) & 0xf) << 16) | ||
466 | #define DMACR_TM(x) ((x) &0xf) | ||
467 | |||
468 | #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) | ||
469 | #define RMCR_LCDC_EN (1<<1) | ||
470 | #define RMCR_SELF_REF (1<<0) | ||
471 | |||
472 | #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) | ||
473 | #define LCDICR_INT_SYN (1<<2) | ||
474 | #define LCDICR_INT_CON (1) | ||
475 | |||
476 | #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) | ||
477 | #define LCDISR_UDR_ERR (1<<3) | ||
478 | #define LCDISR_ERR_RES (1<<2) | ||
479 | #define LCDISR_EOF (1<<1) | ||
480 | #define LCDISR_BOF (1<<0) | ||
481 | |||
482 | #endif // _IMX_REGS_H | 376 | #endif // _IMX_REGS_H |