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authorIngo Molnar <mingo@elte.hu>2008-07-10 10:21:38 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-10 12:55:45 -0400
commit26dd9fcfc2abc298e3c60597bbe6405826aabf91 (patch)
tree8c036c3d9c85cbf96c9befdd078d2e7adb2c297a /arch
parent0cecf92db84694cfed08329271e8ae6316e811eb (diff)
x86, VisWS: turn into generic arch, clean up
merge traps_visws.c and apic_visws.c into visws_quirks.c. (no code changed) Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/Makefile2
-rw-r--r--arch/x86/kernel/apic_visws.c295
-rw-r--r--arch/x86/kernel/traps_visws.c71
-rw-r--r--arch/x86/kernel/visws_quirks.c373
4 files changed, 372 insertions, 369 deletions
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 2ef0fbd3488f..f77dd6774bba 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -19,7 +19,7 @@ obj-y := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
19obj-y += traps_$(BITS).o irq_$(BITS).o 19obj-y += traps_$(BITS).o irq_$(BITS).o
20obj-y += time_$(BITS).o ioport.o ldt.o 20obj-y += time_$(BITS).o ioport.o ldt.o
21obj-y += setup.o i8259.o irqinit_$(BITS).o setup_percpu.o 21obj-y += setup.o i8259.o irqinit_$(BITS).o setup_percpu.o
22obj-$(CONFIG_X86_VISWS) += visws_quirks.o traps_visws.o apic_visws.o 22obj-$(CONFIG_X86_VISWS) += visws_quirks.o
23obj-$(CONFIG_X86_32) += probe_roms_32.o 23obj-$(CONFIG_X86_32) += probe_roms_32.o
24obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o 24obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o
25obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o 25obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o
diff --git a/arch/x86/kernel/apic_visws.c b/arch/x86/kernel/apic_visws.c
deleted file mode 100644
index 6c02c8d09932..000000000000
--- a/arch/x86/kernel/apic_visws.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
3 *
4 * SGI Visual Workstation interrupt controller
5 *
6 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
7 * which serves as the main interrupt controller in the system. Non-legacy
8 * hardware in the system uses this controller directly. Legacy devices
9 * are connected to the PIIX4 which in turn has its 8259(s) connected to
10 * a of the Cobalt APIC entry.
11 *
12 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
13 *
14 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
15 */
16
17#include <linux/kernel_stat.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20
21#include <asm/io.h>
22#include <asm/apic.h>
23#include <asm/i8259.h>
24#include <asm/irq_vectors.h>
25#include <asm/visws/cobalt.h>
26
27static DEFINE_SPINLOCK(cobalt_lock);
28
29/*
30 * Set the given Cobalt APIC Redirection Table entry to point
31 * to the given IDT vector/index.
32 */
33static inline void co_apic_set(int entry, int irq)
34{
35 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
36 co_apic_write(CO_APIC_HI(entry), 0);
37}
38
39/*
40 * Cobalt (IO)-APIC functions to handle PCI devices.
41 */
42static inline int co_apic_ide0_hack(void)
43{
44 extern char visws_board_type;
45 extern char visws_board_rev;
46
47 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
48 return 5;
49 return CO_APIC_IDE0;
50}
51
52static int is_co_apic(unsigned int irq)
53{
54 if (IS_CO_APIC(irq))
55 return CO_APIC(irq);
56
57 switch (irq) {
58 case 0: return CO_APIC_CPU;
59 case CO_IRQ_IDE0: return co_apic_ide0_hack();
60 case CO_IRQ_IDE1: return CO_APIC_IDE1;
61 default: return -1;
62 }
63}
64
65
66/*
67 * This is the SGI Cobalt (IO-)APIC:
68 */
69
70static void enable_cobalt_irq(unsigned int irq)
71{
72 co_apic_set(is_co_apic(irq), irq);
73}
74
75static void disable_cobalt_irq(unsigned int irq)
76{
77 int entry = is_co_apic(irq);
78
79 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
80 co_apic_read(CO_APIC_LO(entry));
81}
82
83/*
84 * "irq" really just serves to identify the device. Here is where we
85 * map this to the Cobalt APIC entry where it's physically wired.
86 * This is called via request_irq -> setup_irq -> irq_desc->startup()
87 */
88static unsigned int startup_cobalt_irq(unsigned int irq)
89{
90 unsigned long flags;
91
92 spin_lock_irqsave(&cobalt_lock, flags);
93 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
94 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
95 enable_cobalt_irq(irq);
96 spin_unlock_irqrestore(&cobalt_lock, flags);
97 return 0;
98}
99
100static void ack_cobalt_irq(unsigned int irq)
101{
102 unsigned long flags;
103
104 spin_lock_irqsave(&cobalt_lock, flags);
105 disable_cobalt_irq(irq);
106 apic_write(APIC_EOI, APIC_EIO_ACK);
107 spin_unlock_irqrestore(&cobalt_lock, flags);
108}
109
110static void end_cobalt_irq(unsigned int irq)
111{
112 unsigned long flags;
113
114 spin_lock_irqsave(&cobalt_lock, flags);
115 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
116 enable_cobalt_irq(irq);
117 spin_unlock_irqrestore(&cobalt_lock, flags);
118}
119
120static struct irq_chip cobalt_irq_type = {
121 .typename = "Cobalt-APIC",
122 .startup = startup_cobalt_irq,
123 .shutdown = disable_cobalt_irq,
124 .enable = enable_cobalt_irq,
125 .disable = disable_cobalt_irq,
126 .ack = ack_cobalt_irq,
127 .end = end_cobalt_irq,
128};
129
130
131/*
132 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
133 * -- not the manner expected by the code in i8259.c.
134 *
135 * there is a 'master' physical interrupt source that gets sent to
136 * the CPU. But in the chipset there are various 'virtual' interrupts
137 * waiting to be handled. We represent this to Linux through a 'master'
138 * interrupt controller type, and through a special virtual interrupt-
139 * controller. Device drivers only see the virtual interrupt sources.
140 */
141static unsigned int startup_piix4_master_irq(unsigned int irq)
142{
143 init_8259A(0);
144
145 return startup_cobalt_irq(irq);
146}
147
148static void end_piix4_master_irq(unsigned int irq)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&cobalt_lock, flags);
153 enable_cobalt_irq(irq);
154 spin_unlock_irqrestore(&cobalt_lock, flags);
155}
156
157static struct irq_chip piix4_master_irq_type = {
158 .typename = "PIIX4-master",
159 .startup = startup_piix4_master_irq,
160 .ack = ack_cobalt_irq,
161 .end = end_piix4_master_irq,
162};
163
164
165static struct irq_chip piix4_virtual_irq_type = {
166 .typename = "PIIX4-virtual",
167 .shutdown = disable_8259A_irq,
168 .enable = enable_8259A_irq,
169 .disable = disable_8259A_irq,
170};
171
172
173/*
174 * PIIX4-8259 master/virtual functions to handle interrupt requests
175 * from legacy devices: floppy, parallel, serial, rtc.
176 *
177 * None of these get Cobalt APIC entries, neither do they have IDT
178 * entries. These interrupts are purely virtual and distributed from
179 * the 'master' interrupt source: CO_IRQ_8259.
180 *
181 * When the 8259 interrupts its handler figures out which of these
182 * devices is interrupting and dispatches to its handler.
183 *
184 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
185 * enable_irq gets the right irq. This 'master' irq is never directly
186 * manipulated by any driver.
187 */
188static irqreturn_t piix4_master_intr(int irq, void *dev_id)
189{
190 int realirq;
191 irq_desc_t *desc;
192 unsigned long flags;
193
194 spin_lock_irqsave(&i8259A_lock, flags);
195
196 /* Find out what's interrupting in the PIIX4 master 8259 */
197 outb(0x0c, 0x20); /* OCW3 Poll command */
198 realirq = inb(0x20);
199
200 /*
201 * Bit 7 == 0 means invalid/spurious
202 */
203 if (unlikely(!(realirq & 0x80)))
204 goto out_unlock;
205
206 realirq &= 7;
207
208 if (unlikely(realirq == 2)) {
209 outb(0x0c, 0xa0);
210 realirq = inb(0xa0);
211
212 if (unlikely(!(realirq & 0x80)))
213 goto out_unlock;
214
215 realirq = (realirq & 7) + 8;
216 }
217
218 /* mask and ack interrupt */
219 cached_irq_mask |= 1 << realirq;
220 if (unlikely(realirq > 7)) {
221 inb(0xa1);
222 outb(cached_slave_mask, 0xa1);
223 outb(0x60 + (realirq & 7), 0xa0);
224 outb(0x60 + 2, 0x20);
225 } else {
226 inb(0x21);
227 outb(cached_master_mask, 0x21);
228 outb(0x60 + realirq, 0x20);
229 }
230
231 spin_unlock_irqrestore(&i8259A_lock, flags);
232
233 desc = irq_desc + realirq;
234
235 /*
236 * handle this 'virtual interrupt' as a Cobalt one now.
237 */
238 kstat_cpu(smp_processor_id()).irqs[realirq]++;
239
240 if (likely(desc->action != NULL))
241 handle_IRQ_event(realirq, desc->action);
242
243 if (!(desc->status & IRQ_DISABLED))
244 enable_8259A_irq(realirq);
245
246 return IRQ_HANDLED;
247
248out_unlock:
249 spin_unlock_irqrestore(&i8259A_lock, flags);
250 return IRQ_NONE;
251}
252
253static struct irqaction master_action = {
254 .handler = piix4_master_intr,
255 .name = "PIIX4-8259",
256};
257
258static struct irqaction cascade_action = {
259 .handler = no_action,
260 .name = "cascade",
261};
262
263
264void init_VISWS_APIC_irqs(void)
265{
266 int i;
267
268 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
269 irq_desc[i].status = IRQ_DISABLED;
270 irq_desc[i].action = 0;
271 irq_desc[i].depth = 1;
272
273 if (i == 0) {
274 irq_desc[i].chip = &cobalt_irq_type;
275 }
276 else if (i == CO_IRQ_IDE0) {
277 irq_desc[i].chip = &cobalt_irq_type;
278 }
279 else if (i == CO_IRQ_IDE1) {
280 irq_desc[i].chip = &cobalt_irq_type;
281 }
282 else if (i == CO_IRQ_8259) {
283 irq_desc[i].chip = &piix4_master_irq_type;
284 }
285 else if (i < CO_IRQ_APIC0) {
286 irq_desc[i].chip = &piix4_virtual_irq_type;
287 }
288 else if (IS_CO_APIC(i)) {
289 irq_desc[i].chip = &cobalt_irq_type;
290 }
291 }
292
293 setup_irq(CO_IRQ_8259, &master_action);
294 setup_irq(2, &cascade_action);
295}
diff --git a/arch/x86/kernel/traps_visws.c b/arch/x86/kernel/traps_visws.c
deleted file mode 100644
index e5e6492c2676..000000000000
--- a/arch/x86/kernel/traps_visws.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/* VISWS traps */
2
3#include <linux/sched.h>
4#include <linux/kernel.h>
5#include <linux/init.h>
6#include <linux/pci.h>
7#include <linux/pci_ids.h>
8
9#include <asm/io.h>
10#include <asm/apic.h>
11#include <asm/arch_hooks.h>
12#include <asm/visws/cobalt.h>
13#include <asm/visws/lithium.h>
14
15
16#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
17#define BCD (LI_INTB | LI_INTC | LI_INTD)
18#define ALLDEVS (A01234 | BCD)
19
20static __init void lithium_init(void)
21{
22 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
23 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
24
25 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
26 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
27 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
28/* panic("This machine is not SGI Visual Workstation 320/540"); */
29 }
30
31 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
32 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
33 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
34/* panic("This machine is not SGI Visual Workstation 320/540"); */
35 }
36
37 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
38 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
39}
40
41static __init void cobalt_init(void)
42{
43 /*
44 * On normal SMP PC this is used only with SMP, but we have to
45 * use it and set it up here to start the Cobalt clock
46 */
47 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
48 setup_local_APIC();
49 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
50 (unsigned int)apic_read(APIC_LVR),
51 (unsigned int)apic_read(APIC_ID));
52
53 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
54 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
55 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
56 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
57
58 /* Enable Cobalt APIC being careful to NOT change the ID! */
59 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
60
61 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
62 co_apic_read(CO_APIC_ID));
63}
64
65int __init visws_trap_init_quirk(void)
66{
67 lithium_init();
68 cobalt_init();
69
70 return 1;
71}
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c
index e19b91c47e90..5c715c24ab55 100644
--- a/arch/x86/kernel/visws_quirks.c
+++ b/arch/x86/kernel/visws_quirks.c
@@ -1,8 +1,22 @@
1/* 1/*
2 * Unmaintained SGI Visual Workstation support. 2 * SGI Visual Workstation support and quirks, unmaintained.
3 *
3 * Split out from setup.c by davej@suse.de 4 * Split out from setup.c by davej@suse.de
5 *
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
7 *
8 * SGI Visual Workstation interrupt controller
9 *
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
15 *
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
17 *
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
4 */ 19 */
5
6#include <linux/interrupt.h> 20#include <linux/interrupt.h>
7#include <linux/module.h> 21#include <linux/module.h>
8#include <linux/init.h> 22#include <linux/init.h>
@@ -25,6 +39,30 @@
25#include <linux/init.h> 39#include <linux/init.h>
26#include <linux/smp.h> 40#include <linux/smp.h>
27 41
42#include <linux/kernel_stat.h>
43#include <linux/interrupt.h>
44#include <linux/init.h>
45
46#include <asm/io.h>
47#include <asm/apic.h>
48#include <asm/i8259.h>
49#include <asm/irq_vectors.h>
50#include <asm/visws/cobalt.h>
51#include <asm/visws/lithium.h>
52#include <asm/visws/piix4.h>
53
54#include <linux/sched.h>
55#include <linux/kernel.h>
56#include <linux/init.h>
57#include <linux/pci.h>
58#include <linux/pci_ids.h>
59
60#include <asm/io.h>
61#include <asm/apic.h>
62#include <asm/arch_hooks.h>
63#include <asm/visws/cobalt.h>
64#include <asm/visws/lithium.h>
65
28char visws_board_type = -1; 66char visws_board_type = -1;
29char visws_board_rev = -1; 67char visws_board_rev = -1;
30 68
@@ -336,3 +374,334 @@ void __init visws_early_detect(void)
336 (visws_board_type == VISWS_540 ? "540" : 374 (visws_board_type == VISWS_540 ? "540" :
337 "unknown")), visws_board_rev); 375 "unknown")), visws_board_rev);
338} 376}
377
378#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
379#define BCD (LI_INTB | LI_INTC | LI_INTD)
380#define ALLDEVS (A01234 | BCD)
381
382static __init void lithium_init(void)
383{
384 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
385 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
386
387 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
388 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
389 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
390/* panic("This machine is not SGI Visual Workstation 320/540"); */
391 }
392
393 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
394 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
395 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
396/* panic("This machine is not SGI Visual Workstation 320/540"); */
397 }
398
399 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
400 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
401}
402
403static __init void cobalt_init(void)
404{
405 /*
406 * On normal SMP PC this is used only with SMP, but we have to
407 * use it and set it up here to start the Cobalt clock
408 */
409 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
410 setup_local_APIC();
411 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
412 (unsigned int)apic_read(APIC_LVR),
413 (unsigned int)apic_read(APIC_ID));
414
415 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
416 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
417 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
418 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
419
420 /* Enable Cobalt APIC being careful to NOT change the ID! */
421 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
422
423 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
424 co_apic_read(CO_APIC_ID));
425}
426
427int __init visws_trap_init_quirk(void)
428{
429 lithium_init();
430 cobalt_init();
431
432 return 1;
433}
434
435/*
436 * IRQ controller / APIC support:
437 */
438
439static DEFINE_SPINLOCK(cobalt_lock);
440
441/*
442 * Set the given Cobalt APIC Redirection Table entry to point
443 * to the given IDT vector/index.
444 */
445static inline void co_apic_set(int entry, int irq)
446{
447 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
448 co_apic_write(CO_APIC_HI(entry), 0);
449}
450
451/*
452 * Cobalt (IO)-APIC functions to handle PCI devices.
453 */
454static inline int co_apic_ide0_hack(void)
455{
456 extern char visws_board_type;
457 extern char visws_board_rev;
458
459 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
460 return 5;
461 return CO_APIC_IDE0;
462}
463
464static int is_co_apic(unsigned int irq)
465{
466 if (IS_CO_APIC(irq))
467 return CO_APIC(irq);
468
469 switch (irq) {
470 case 0: return CO_APIC_CPU;
471 case CO_IRQ_IDE0: return co_apic_ide0_hack();
472 case CO_IRQ_IDE1: return CO_APIC_IDE1;
473 default: return -1;
474 }
475}
476
477
478/*
479 * This is the SGI Cobalt (IO-)APIC:
480 */
481
482static void enable_cobalt_irq(unsigned int irq)
483{
484 co_apic_set(is_co_apic(irq), irq);
485}
486
487static void disable_cobalt_irq(unsigned int irq)
488{
489 int entry = is_co_apic(irq);
490
491 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
492 co_apic_read(CO_APIC_LO(entry));
493}
494
495/*
496 * "irq" really just serves to identify the device. Here is where we
497 * map this to the Cobalt APIC entry where it's physically wired.
498 * This is called via request_irq -> setup_irq -> irq_desc->startup()
499 */
500static unsigned int startup_cobalt_irq(unsigned int irq)
501{
502 unsigned long flags;
503
504 spin_lock_irqsave(&cobalt_lock, flags);
505 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
506 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
507 enable_cobalt_irq(irq);
508 spin_unlock_irqrestore(&cobalt_lock, flags);
509 return 0;
510}
511
512static void ack_cobalt_irq(unsigned int irq)
513{
514 unsigned long flags;
515
516 spin_lock_irqsave(&cobalt_lock, flags);
517 disable_cobalt_irq(irq);
518 apic_write(APIC_EOI, APIC_EIO_ACK);
519 spin_unlock_irqrestore(&cobalt_lock, flags);
520}
521
522static void end_cobalt_irq(unsigned int irq)
523{
524 unsigned long flags;
525
526 spin_lock_irqsave(&cobalt_lock, flags);
527 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
528 enable_cobalt_irq(irq);
529 spin_unlock_irqrestore(&cobalt_lock, flags);
530}
531
532static struct irq_chip cobalt_irq_type = {
533 .typename = "Cobalt-APIC",
534 .startup = startup_cobalt_irq,
535 .shutdown = disable_cobalt_irq,
536 .enable = enable_cobalt_irq,
537 .disable = disable_cobalt_irq,
538 .ack = ack_cobalt_irq,
539 .end = end_cobalt_irq,
540};
541
542
543/*
544 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
545 * -- not the manner expected by the code in i8259.c.
546 *
547 * there is a 'master' physical interrupt source that gets sent to
548 * the CPU. But in the chipset there are various 'virtual' interrupts
549 * waiting to be handled. We represent this to Linux through a 'master'
550 * interrupt controller type, and through a special virtual interrupt-
551 * controller. Device drivers only see the virtual interrupt sources.
552 */
553static unsigned int startup_piix4_master_irq(unsigned int irq)
554{
555 init_8259A(0);
556
557 return startup_cobalt_irq(irq);
558}
559
560static void end_piix4_master_irq(unsigned int irq)
561{
562 unsigned long flags;
563
564 spin_lock_irqsave(&cobalt_lock, flags);
565 enable_cobalt_irq(irq);
566 spin_unlock_irqrestore(&cobalt_lock, flags);
567}
568
569static struct irq_chip piix4_master_irq_type = {
570 .typename = "PIIX4-master",
571 .startup = startup_piix4_master_irq,
572 .ack = ack_cobalt_irq,
573 .end = end_piix4_master_irq,
574};
575
576
577static struct irq_chip piix4_virtual_irq_type = {
578 .typename = "PIIX4-virtual",
579 .shutdown = disable_8259A_irq,
580 .enable = enable_8259A_irq,
581 .disable = disable_8259A_irq,
582};
583
584
585/*
586 * PIIX4-8259 master/virtual functions to handle interrupt requests
587 * from legacy devices: floppy, parallel, serial, rtc.
588 *
589 * None of these get Cobalt APIC entries, neither do they have IDT
590 * entries. These interrupts are purely virtual and distributed from
591 * the 'master' interrupt source: CO_IRQ_8259.
592 *
593 * When the 8259 interrupts its handler figures out which of these
594 * devices is interrupting and dispatches to its handler.
595 *
596 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
597 * enable_irq gets the right irq. This 'master' irq is never directly
598 * manipulated by any driver.
599 */
600static irqreturn_t piix4_master_intr(int irq, void *dev_id)
601{
602 int realirq;
603 irq_desc_t *desc;
604 unsigned long flags;
605
606 spin_lock_irqsave(&i8259A_lock, flags);
607
608 /* Find out what's interrupting in the PIIX4 master 8259 */
609 outb(0x0c, 0x20); /* OCW3 Poll command */
610 realirq = inb(0x20);
611
612 /*
613 * Bit 7 == 0 means invalid/spurious
614 */
615 if (unlikely(!(realirq & 0x80)))
616 goto out_unlock;
617
618 realirq &= 7;
619
620 if (unlikely(realirq == 2)) {
621 outb(0x0c, 0xa0);
622 realirq = inb(0xa0);
623
624 if (unlikely(!(realirq & 0x80)))
625 goto out_unlock;
626
627 realirq = (realirq & 7) + 8;
628 }
629
630 /* mask and ack interrupt */
631 cached_irq_mask |= 1 << realirq;
632 if (unlikely(realirq > 7)) {
633 inb(0xa1);
634 outb(cached_slave_mask, 0xa1);
635 outb(0x60 + (realirq & 7), 0xa0);
636 outb(0x60 + 2, 0x20);
637 } else {
638 inb(0x21);
639 outb(cached_master_mask, 0x21);
640 outb(0x60 + realirq, 0x20);
641 }
642
643 spin_unlock_irqrestore(&i8259A_lock, flags);
644
645 desc = irq_desc + realirq;
646
647 /*
648 * handle this 'virtual interrupt' as a Cobalt one now.
649 */
650 kstat_cpu(smp_processor_id()).irqs[realirq]++;
651
652 if (likely(desc->action != NULL))
653 handle_IRQ_event(realirq, desc->action);
654
655 if (!(desc->status & IRQ_DISABLED))
656 enable_8259A_irq(realirq);
657
658 return IRQ_HANDLED;
659
660out_unlock:
661 spin_unlock_irqrestore(&i8259A_lock, flags);
662 return IRQ_NONE;
663}
664
665static struct irqaction master_action = {
666 .handler = piix4_master_intr,
667 .name = "PIIX4-8259",
668};
669
670static struct irqaction cascade_action = {
671 .handler = no_action,
672 .name = "cascade",
673};
674
675
676void init_VISWS_APIC_irqs(void)
677{
678 int i;
679
680 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
681 irq_desc[i].status = IRQ_DISABLED;
682 irq_desc[i].action = 0;
683 irq_desc[i].depth = 1;
684
685 if (i == 0) {
686 irq_desc[i].chip = &cobalt_irq_type;
687 }
688 else if (i == CO_IRQ_IDE0) {
689 irq_desc[i].chip = &cobalt_irq_type;
690 }
691 else if (i == CO_IRQ_IDE1) {
692 irq_desc[i].chip = &cobalt_irq_type;
693 }
694 else if (i == CO_IRQ_8259) {
695 irq_desc[i].chip = &piix4_master_irq_type;
696 }
697 else if (i < CO_IRQ_APIC0) {
698 irq_desc[i].chip = &piix4_virtual_irq_type;
699 }
700 else if (IS_CO_APIC(i)) {
701 irq_desc[i].chip = &cobalt_irq_type;
702 }
703 }
704
705 setup_irq(CO_IRQ_8259, &master_action);
706 setup_irq(2, &cascade_action);
707}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 09:18:15 -0500