diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-01-28 14:35:03 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 12:50:44 -0500 |
commit | 439764cc18beb20ef409991e75e29b460db71d33 (patch) | |
tree | 6ae4c648bfe34c3f511fef89282f10efe69ca48b /arch | |
parent | de07fedd79999668c4c112a2ba3eaf3d7434235c (diff) |
[ARM] OMAP2xxx clock: consolidate DELAYED_APP clock commits; fix barrier
Consolidate the commit code for DELAYED_APP clocks into a subroutine,
_omap2xxx_clk_commit(). Also convert the MPU barrier wmb() into an
OCP barrier, since with an MPU barrier, we have no guarantee that the
write actually reached the endpoint device.
linux-omap source commit is 0f5bdb736515801b296125d16937a21ff7b3cfdc.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 33 |
1 files changed, 24 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 0803c8c811f4..7f12230fef73 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -74,6 +74,28 @@ u8 cpu_mask; | |||
74 | * OMAP2/3 specific clock functions | 74 | * OMAP2/3 specific clock functions |
75 | *-------------------------------------------------------------------------*/ | 75 | *-------------------------------------------------------------------------*/ |
76 | 76 | ||
77 | /** | ||
78 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware | ||
79 | * @clk: struct clk * | ||
80 | * | ||
81 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | ||
82 | * don't take effect until the VALID_CONFIG bit is written, write the | ||
83 | * VALID_CONFIG bit and wait for the write to complete. No return value. | ||
84 | */ | ||
85 | static void _omap2xxx_clk_commit(struct clk *clk) | ||
86 | { | ||
87 | if (!cpu_is_omap24xx()) | ||
88 | return; | ||
89 | |||
90 | if (!(clk->flags & DELAYED_APP)) | ||
91 | return; | ||
92 | |||
93 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | ||
94 | OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
95 | /* OCP barrier */ | ||
96 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
97 | } | ||
98 | |||
77 | /* | 99 | /* |
78 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL | 100 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL |
79 | * @clk: DPLL struct clk to test | 101 | * @clk: DPLL struct clk to test |
@@ -685,11 +707,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | |||
685 | 707 | ||
686 | clk->rate = clk->parent->rate / new_div; | 708 | clk->rate = clk->parent->rate / new_div; |
687 | 709 | ||
688 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | 710 | _omap2xxx_clk_commit(clk); |
689 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, | ||
690 | OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
691 | wmb(); | ||
692 | } | ||
693 | 711 | ||
694 | return 0; | 712 | return 0; |
695 | } | 713 | } |
@@ -772,10 +790,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |||
772 | __raw_writel(v, clk->clksel_reg); | 790 | __raw_writel(v, clk->clksel_reg); |
773 | wmb(); | 791 | wmb(); |
774 | 792 | ||
775 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | 793 | _omap2xxx_clk_commit(clk); |
776 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); | ||
777 | wmb(); | ||
778 | } | ||
779 | 794 | ||
780 | if (clk->usecount > 0) | 795 | if (clk->usecount > 0) |
781 | _omap2_clk_enable(clk); | 796 | _omap2_clk_enable(clk); |