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authorPaul Gortmaker <paul.gortmaker@windriver.com>2009-09-21 10:30:08 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-11-05 08:16:54 -0500
commitcb5485a0b99b232c5c7c4c21e2346f8ab7ef555d (patch)
tree47ee7cb385a0c52c56d64c12cb09e48e723ee0ce /arch
parent38634e6769920929385f1ffc8820dc3e893cc630 (diff)
powerpc/85xx: sbc8548 - fixup of PCI-e related DTS fields
The PCI-e addressing was originally patterned of the MPC8548CDS which has PCI1, PCI2, and PCI-e. Since this board only has PCI1 and PCI-e, it makes more sense to be similar to the MPC8568MDS board. This does that by cutting the PCI/PCI-e I/O sizes from 16MB to 8MB and pulling the PCI-e I/O range back to 0xe280_0000 (the hole where PCI2 I/O would have been). This also fixes a typo where an extra zero made an 8MB range a 128MB range, removes the hole left by PCI2 from the aliases, and sets the clocks to match the oscillators that are actually on the board. With accompanying u-boot updates, PCI-e has been validated with both a sky2 card (1148:9e00) and an e1000 card (8086:108b). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts17
1 files changed, 8 insertions, 9 deletions
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 9eefe00ed253..94a332251710 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -26,8 +26,7 @@
26 serial0 = &serial0; 26 serial0 = &serial0;
27 serial1 = &serial1; 27 serial1 = &serial1;
28 pci0 = &pci0; 28 pci0 = &pci0;
29 /* pci1 doesn't have a corresponding physical connector */ 29 pci1 = &pci1;
30 pci2 = &pci2;
31 }; 30 };
32 31
33 cpus { 32 cpus {
@@ -381,7 +380,7 @@
381 bus-range = <0 0>; 380 bus-range = <0 0>;
382 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 381 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
383 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>; 382 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
384 clock-frequency = <66666666>; 383 clock-frequency = <66000000>;
385 #interrupt-cells = <1>; 384 #interrupt-cells = <1>;
386 #size-cells = <2>; 385 #size-cells = <2>;
387 #address-cells = <3>; 386 #address-cells = <3>;
@@ -390,7 +389,7 @@
390 device_type = "pci"; 389 device_type = "pci";
391 }; 390 };
392 391
393 pci2: pcie@e000a000 { 392 pci1: pcie@e000a000 {
394 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 393 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
395 interrupt-map = < 394 interrupt-map = <
396 395
@@ -403,9 +402,9 @@
403 interrupt-parent = <&mpic>; 402 interrupt-parent = <&mpic>;
404 interrupts = <0x1a 0x2>; 403 interrupts = <0x1a 0x2>;
405 bus-range = <0x0 0xff>; 404 bus-range = <0x0 0xff>;
406 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 405 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
407 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>; 406 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
408 clock-frequency = <33333333>; 407 clock-frequency = <33000000>;
409 #interrupt-cells = <1>; 408 #interrupt-cells = <1>;
410 #size-cells = <2>; 409 #size-cells = <2>;
411 #address-cells = <3>; 410 #address-cells = <3>;
@@ -419,11 +418,11 @@
419 device_type = "pci"; 418 device_type = "pci";
420 ranges = <0x02000000 0x0 0xa0000000 419 ranges = <0x02000000 0x0 0xa0000000
421 0x02000000 0x0 0xa0000000 420 0x02000000 0x0 0xa0000000
422 0x0 0x20000000 421 0x0 0x10000000
423 422
424 0x01000000 0x0 0x00000000 423 0x01000000 0x0 0x00000000
425 0x01000000 0x0 0x00000000 424 0x01000000 0x0 0x00000000
426 0x0 0x08000000>; 425 0x0 0x00800000>;
427 }; 426 };
428 }; 427 };
429}; 428};