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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-01-19 10:27:29 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 12:50:14 -0500
commit8ad8ff6548f1c0bcbeaa02f274b3927c5015a921 (patch)
treee089b88bc8da54f107acdd6ee395359b73dbd37c /arch
parentd7e8f1f9d655af2c7ea90738bf567aa6990159b3 (diff)
[ARM] omap: convert OMAP2 to use clkdev
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock24xx.c197
-rw-r--r--arch/arm/mach-omap2/clock24xx.h353
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h4
4 files changed, 218 insertions, 337 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 3a0a1b8aa0bb..36093ea878a3 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -31,6 +31,7 @@
31#include <mach/clock.h> 31#include <mach/clock.h>
32#include <mach/sram.h> 32#include <mach/sram.h>
33#include <asm/div64.h> 33#include <asm/div64.h>
34#include <asm/clkdev.h>
34 35
35#include "memory.h" 36#include "memory.h"
36#include "clock.h" 37#include "clock.h"
@@ -44,6 +45,177 @@ static const struct clkops clkops_fixed;
44 45
45#include "clock24xx.h" 46#include "clock24xx.h"
46 47
48struct omap_clk {
49 u32 cpu;
50 struct clk_lookup lk;
51};
52
53#define CLK(dev, con, ck, cp) \
54 { \
55 .cpu = cp, \
56 .lk = { \
57 .dev_id = dev, \
58 .con_id = con, \
59 .clk = ck, \
60 }, \
61 }
62
63#define CK_243X (1 << 0)
64#define CK_242X (1 << 1)
65
66static struct omap_clk omap24xx_clks[] = {
67 /* external root sources */
68 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
69 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
70 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
71 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
72 /* internal analog sources */
73 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
74 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
75 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
76 /* internal prcm root sources */
77 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
78 CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
79 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
80 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
81 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
82 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
83 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
84 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
85 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
86 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
87 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
88 /* mpu domain clocks */
89 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
90 /* dsp domain clocks */
91 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
92 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
93 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
94 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
95 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
96 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
97 /* GFX domain clocks */
98 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
99 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
100 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
101 /* Modem domain clocks */
102 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
103 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
104 /* DSS domain clocks */
105 CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X),
106 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X),
107 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X),
108 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X),
109 /* L3 domain clocks */
110 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
111 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
112 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
113 /* L4 domain clocks */
114 CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
115 /* virtual meta-group clock */
116 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
117 /* general l4 interface ck, multi-parent functional clk */
118 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
119 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
120 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
121 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
122 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
123 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
124 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
125 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
126 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
127 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
128 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
129 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
130 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
131 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
132 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
133 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
134 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
135 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
136 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
137 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
138 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
139 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
140 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
141 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
142 CLK("omap-mcbsp.1", "mcbsp_ick", &mcbsp1_ick, CK_243X | CK_242X),
143 CLK("omap-mcbsp.1", "mcbsp_fck", &mcbsp1_fck, CK_243X | CK_242X),
144 CLK("omap-mcbsp.2", "mcbsp_ick", &mcbsp2_ick, CK_243X | CK_242X),
145 CLK("omap-mcbsp.2", "mcbsp_fck", &mcbsp2_fck, CK_243X | CK_242X),
146 CLK("omap-mcbsp.3", "mcbsp_ick", &mcbsp3_ick, CK_243X),
147 CLK("omap-mcbsp.3", "mcbsp_fck", &mcbsp3_fck, CK_243X),
148 CLK("omap-mcbsp.4", "mcbsp_ick", &mcbsp4_ick, CK_243X),
149 CLK("omap-mcbsp.4", "mcbsp_fck", &mcbsp4_fck, CK_243X),
150 CLK("omap-mcbsp.5", "mcbsp_ick", &mcbsp5_ick, CK_243X),
151 CLK("omap-mcbsp.5", "mcbsp_fck", &mcbsp5_fck, CK_243X),
152 CLK("omap2_mcspi.1", "mcspi_ick", &mcspi1_ick, CK_243X | CK_242X),
153 CLK("omap2_mcspi.1", "mcspi_fck", &mcspi1_fck, CK_243X | CK_242X),
154 CLK("omap2_mcspi.2", "mcspi_ick", &mcspi2_ick, CK_243X | CK_242X),
155 CLK("omap2_mcspi.2", "mcspi_fck", &mcspi2_fck, CK_243X | CK_242X),
156 CLK("omap2_mcspi.3", "mcspi_ick", &mcspi3_ick, CK_243X),
157 CLK("omap2_mcspi.3", "mcspi_fck", &mcspi3_fck, CK_243X),
158 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
159 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
160 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
161 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
162 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
163 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
164 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
165 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
166 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X | CK_242X),
167 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X | CK_242X),
168 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
169 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
170 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
171 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
172 CLK(NULL, "cam_fck", &cam_fck, CK_243X | CK_242X),
173 CLK(NULL, "cam_ick", &cam_ick, CK_243X | CK_242X),
174 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
175 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
176 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
177 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
178 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
179 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
180 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
181 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
182 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
183 CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
184 CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
185 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
186 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
187 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X | CK_242X),
188 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X | CK_242X),
189 CLK("i2c_omap.1", "i2c_ick", &i2c1_ick, CK_243X | CK_242X),
190 CLK("i2c_omap.1", "i2c_fck", &i2c1_fck, CK_242X),
191 CLK("i2c_omap.1", "i2c_fck", &i2chs1_fck, CK_243X),
192 CLK("i2c_omap.2", "i2c_ick", &i2c2_ick, CK_243X | CK_242X),
193 CLK("i2c_omap.2", "i2c_fck", &i2c2_fck, CK_242X),
194 CLK("i2c_omap.2", "i2c_fck", &i2chs2_fck, CK_243X),
195 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
196 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
197 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
198 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
199 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
200 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
201 CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
202 CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
203 CLK(NULL, "rng_ick", &rng_ick, CK_243X | CK_242X),
204 CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
205 CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
206 CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
207 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
208 CLK("mmci-omap-hs.0", "mmchs_ick", &mmchs1_ick, CK_243X),
209 CLK("mmci-omap-hs.0", "mmchs_fck", &mmchs1_fck, CK_243X),
210 CLK("mmci-omap-hs.1", "mmchs_ick", &mmchs2_ick, CK_243X),
211 CLK("mmci-omap-hs.1", "mmchs_fck", &mmchs2_fck, CK_243X),
212 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
213 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
214 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
215 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
216 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
217};
218
47/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ 219/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
48#define EN_APLL_STOPPED 0 220#define EN_APLL_STOPPED 0
49#define EN_APLL_LOCKED 3 221#define EN_APLL_LOCKED 3
@@ -487,8 +659,8 @@ arch_initcall(omap2_clk_arch_init);
487int __init omap2_clk_init(void) 659int __init omap2_clk_init(void)
488{ 660{
489 struct prcm_config *prcm; 661 struct prcm_config *prcm;
490 struct clk **clkp; 662 struct omap_clk *c;
491 u32 clkrate; 663 u32 clkrate, cpu_mask;
492 664
493 if (cpu_is_omap242x()) 665 if (cpu_is_omap242x())
494 cpu_mask = RATE_IN_242X; 666 cpu_mask = RATE_IN_242X;
@@ -502,21 +674,18 @@ int __init omap2_clk_init(void)
502 omap2_sys_clk_recalc(&sys_ck); 674 omap2_sys_clk_recalc(&sys_ck);
503 propagate_rate(&sys_ck); 675 propagate_rate(&sys_ck);
504 676
505 for (clkp = onchip_24xx_clks; 677 cpu_mask = 0;
506 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); 678 if (cpu_is_omap2420())
507 clkp++) { 679 cpu_mask |= CK_242X;
680 if (cpu_is_omap2430())
681 cpu_mask |= CK_243X;
508 682
509 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { 683 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
510 clk_register(*clkp); 684 if (c->cpu & cpu_mask) {
511 continue; 685 clkdev_add(&c->lk);
686 clk_register(c->lk.clk);
512 } 687 }
513 688
514 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
515 clk_register(*clkp);
516 continue;
517 }
518 }
519
520 /* Check the MPU rate set by bootloader */ 689 /* Check the MPU rate set by bootloader */
521 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); 690 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
522 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 691 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index e07dcba4b3e9..b2442475fb47 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -621,8 +621,7 @@ static struct clk func_32k_ck = {
621 .name = "func_32k_ck", 621 .name = "func_32k_ck",
622 .ops = &clkops_null, 622 .ops = &clkops_null,
623 .rate = 32000, 623 .rate = 32000,
624 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 624 .flags = RATE_FIXED | RATE_PROPAGATES,
625 RATE_FIXED | RATE_PROPAGATES,
626 .clkdm_name = "wkup_clkdm", 625 .clkdm_name = "wkup_clkdm",
627}; 626};
628 627
@@ -630,8 +629,7 @@ static struct clk func_32k_ck = {
630static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 629static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
631 .name = "osc_ck", 630 .name = "osc_ck",
632 .ops = &clkops_oscck, 631 .ops = &clkops_oscck,
633 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 632 .flags = RATE_PROPAGATES,
634 RATE_PROPAGATES,
635 .clkdm_name = "wkup_clkdm", 633 .clkdm_name = "wkup_clkdm",
636 .recalc = &omap2_osc_clk_recalc, 634 .recalc = &omap2_osc_clk_recalc,
637}; 635};
@@ -641,8 +639,7 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
641 .name = "sys_ck", /* ~ ref_clk also */ 639 .name = "sys_ck", /* ~ ref_clk also */
642 .ops = &clkops_null, 640 .ops = &clkops_null,
643 .parent = &osc_ck, 641 .parent = &osc_ck,
644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 642 .flags = RATE_PROPAGATES,
645 RATE_PROPAGATES,
646 .clkdm_name = "wkup_clkdm", 643 .clkdm_name = "wkup_clkdm",
647 .recalc = &omap2_sys_clk_recalc, 644 .recalc = &omap2_sys_clk_recalc,
648}; 645};
@@ -651,8 +648,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
651 .name = "alt_ck", 648 .name = "alt_ck",
652 .ops = &clkops_null, 649 .ops = &clkops_null,
653 .rate = 54000000, 650 .rate = 54000000,
654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 651 .flags = RATE_FIXED | RATE_PROPAGATES,
655 RATE_FIXED | RATE_PROPAGATES,
656 .clkdm_name = "wkup_clkdm", 652 .clkdm_name = "wkup_clkdm",
657}; 653};
658 654
@@ -683,8 +679,7 @@ static struct clk dpll_ck = {
683 .ops = &clkops_null, 679 .ops = &clkops_null,
684 .parent = &sys_ck, /* Can be func_32k also */ 680 .parent = &sys_ck, /* Can be func_32k also */
685 .dpll_data = &dpll_dd, 681 .dpll_data = &dpll_dd,
686 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 682 .flags = RATE_PROPAGATES,
687 RATE_PROPAGATES,
688 .clkdm_name = "wkup_clkdm", 683 .clkdm_name = "wkup_clkdm",
689 .recalc = &omap2_dpllcore_recalc, 684 .recalc = &omap2_dpllcore_recalc,
690 .set_rate = &omap2_reprogram_dpllcore, 685 .set_rate = &omap2_reprogram_dpllcore,
@@ -695,8 +690,7 @@ static struct clk apll96_ck = {
695 .ops = &clkops_fixed, 690 .ops = &clkops_fixed,
696 .parent = &sys_ck, 691 .parent = &sys_ck,
697 .rate = 96000000, 692 .rate = 96000000,
698 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 693 .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
699 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
700 .clkdm_name = "wkup_clkdm", 694 .clkdm_name = "wkup_clkdm",
701 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 695 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
702 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 696 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
@@ -707,8 +701,7 @@ static struct clk apll54_ck = {
707 .ops = &clkops_fixed, 701 .ops = &clkops_fixed,
708 .parent = &sys_ck, 702 .parent = &sys_ck,
709 .rate = 54000000, 703 .rate = 54000000,
710 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 704 .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
711 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
712 .clkdm_name = "wkup_clkdm", 705 .clkdm_name = "wkup_clkdm",
713 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 706 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
714 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 707 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
@@ -740,8 +733,7 @@ static struct clk func_54m_ck = {
740 .name = "func_54m_ck", 733 .name = "func_54m_ck",
741 .ops = &clkops_null, 734 .ops = &clkops_null,
742 .parent = &apll54_ck, /* can also be alt_clk */ 735 .parent = &apll54_ck, /* can also be alt_clk */
743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 736 .flags = RATE_PROPAGATES,
744 RATE_PROPAGATES,
745 .clkdm_name = "wkup_clkdm", 737 .clkdm_name = "wkup_clkdm",
746 .init = &omap2_init_clksel_parent, 738 .init = &omap2_init_clksel_parent,
747 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 739 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -754,8 +746,7 @@ static struct clk core_ck = {
754 .name = "core_ck", 746 .name = "core_ck",
755 .ops = &clkops_null, 747 .ops = &clkops_null,
756 .parent = &dpll_ck, /* can also be 32k */ 748 .parent = &dpll_ck, /* can also be 32k */
757 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 749 .flags = RATE_PROPAGATES,
758 RATE_PROPAGATES,
759 .clkdm_name = "wkup_clkdm", 750 .clkdm_name = "wkup_clkdm",
760 .recalc = &followparent_recalc, 751 .recalc = &followparent_recalc,
761}; 752};
@@ -782,8 +773,7 @@ static struct clk func_96m_ck = {
782 .name = "func_96m_ck", 773 .name = "func_96m_ck",
783 .ops = &clkops_null, 774 .ops = &clkops_null,
784 .parent = &apll96_ck, 775 .parent = &apll96_ck,
785 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 776 .flags = RATE_PROPAGATES,
786 RATE_PROPAGATES,
787 .clkdm_name = "wkup_clkdm", 777 .clkdm_name = "wkup_clkdm",
788 .init = &omap2_init_clksel_parent, 778 .init = &omap2_init_clksel_parent,
789 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 779 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -816,8 +806,7 @@ static struct clk func_48m_ck = {
816 .name = "func_48m_ck", 806 .name = "func_48m_ck",
817 .ops = &clkops_null, 807 .ops = &clkops_null,
818 .parent = &apll96_ck, /* 96M or Alt */ 808 .parent = &apll96_ck, /* 96M or Alt */
819 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 809 .flags = RATE_PROPAGATES,
820 RATE_PROPAGATES,
821 .clkdm_name = "wkup_clkdm", 810 .clkdm_name = "wkup_clkdm",
822 .init = &omap2_init_clksel_parent, 811 .init = &omap2_init_clksel_parent,
823 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 812 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -833,8 +822,7 @@ static struct clk func_12m_ck = {
833 .ops = &clkops_null, 822 .ops = &clkops_null,
834 .parent = &func_48m_ck, 823 .parent = &func_48m_ck,
835 .fixed_div = 4, 824 .fixed_div = 4,
836 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 825 .flags = RATE_PROPAGATES,
837 RATE_PROPAGATES,
838 .clkdm_name = "wkup_clkdm", 826 .clkdm_name = "wkup_clkdm",
839 .recalc = &omap2_fixed_divisor_recalc, 827 .recalc = &omap2_fixed_divisor_recalc,
840}; 828};
@@ -844,7 +832,6 @@ static struct clk wdt1_osc_ck = {
844 .name = "ck_wdt1_osc", 832 .name = "ck_wdt1_osc",
845 .ops = &clkops_null, /* RMK: missing? */ 833 .ops = &clkops_null, /* RMK: missing? */
846 .parent = &osc_ck, 834 .parent = &osc_ck,
847 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
848 .recalc = &followparent_recalc, 835 .recalc = &followparent_recalc,
849}; 836};
850 837
@@ -888,8 +875,7 @@ static struct clk sys_clkout_src = {
888 .name = "sys_clkout_src", 875 .name = "sys_clkout_src",
889 .ops = &clkops_omap2_dflt, 876 .ops = &clkops_omap2_dflt,
890 .parent = &func_54m_ck, 877 .parent = &func_54m_ck,
891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 878 .flags = RATE_PROPAGATES,
892 RATE_PROPAGATES,
893 .clkdm_name = "wkup_clkdm", 879 .clkdm_name = "wkup_clkdm",
894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 880 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 881 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -920,7 +906,6 @@ static struct clk sys_clkout = {
920 .name = "sys_clkout", 906 .name = "sys_clkout",
921 .ops = &clkops_null, 907 .ops = &clkops_null,
922 .parent = &sys_clkout_src, 908 .parent = &sys_clkout_src,
923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
924 .clkdm_name = "wkup_clkdm", 909 .clkdm_name = "wkup_clkdm",
925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 910 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 911 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
@@ -935,7 +920,7 @@ static struct clk sys_clkout2_src = {
935 .name = "sys_clkout2_src", 920 .name = "sys_clkout2_src",
936 .ops = &clkops_omap2_dflt, 921 .ops = &clkops_omap2_dflt,
937 .parent = &func_54m_ck, 922 .parent = &func_54m_ck,
938 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, 923 .flags = RATE_PROPAGATES,
939 .clkdm_name = "wkup_clkdm", 924 .clkdm_name = "wkup_clkdm",
940 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 925 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
941 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 926 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -958,7 +943,6 @@ static struct clk sys_clkout2 = {
958 .name = "sys_clkout2", 943 .name = "sys_clkout2",
959 .ops = &clkops_null, 944 .ops = &clkops_null,
960 .parent = &sys_clkout2_src, 945 .parent = &sys_clkout2_src,
961 .flags = CLOCK_IN_OMAP242X,
962 .clkdm_name = "wkup_clkdm", 946 .clkdm_name = "wkup_clkdm",
963 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 947 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
964 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 948 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
@@ -972,7 +956,6 @@ static struct clk emul_ck = {
972 .name = "emul_ck", 956 .name = "emul_ck",
973 .ops = &clkops_omap2_dflt, 957 .ops = &clkops_omap2_dflt,
974 .parent = &func_54m_ck, 958 .parent = &func_54m_ck,
975 .flags = CLOCK_IN_OMAP242X,
976 .clkdm_name = "wkup_clkdm", 959 .clkdm_name = "wkup_clkdm",
977 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 960 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
978 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 961 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
@@ -1008,9 +991,7 @@ static struct clk mpu_ck = { /* Control cpu */
1008 .name = "mpu_ck", 991 .name = "mpu_ck",
1009 .ops = &clkops_null, 992 .ops = &clkops_null,
1010 .parent = &core_ck, 993 .parent = &core_ck,
1011 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 994 .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1012 DELAYED_APP |
1013 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1014 .clkdm_name = "mpu_clkdm", 995 .clkdm_name = "mpu_clkdm",
1015 .init = &omap2_init_clksel_parent, 996 .init = &omap2_init_clksel_parent,
1016 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 997 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1052,8 +1033,7 @@ static struct clk dsp_fck = {
1052 .name = "dsp_fck", 1033 .name = "dsp_fck",
1053 .ops = &clkops_omap2_dflt_wait, 1034 .ops = &clkops_omap2_dflt_wait,
1054 .parent = &core_ck, 1035 .parent = &core_ck,
1055 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1036 .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1056 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1057 .clkdm_name = "dsp_clkdm", 1037 .clkdm_name = "dsp_clkdm",
1058 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1038 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1059 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1039 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1083,8 +1063,7 @@ static struct clk dsp_irate_ick = {
1083 .name = "dsp_irate_ick", 1063 .name = "dsp_irate_ick",
1084 .ops = &clkops_null, 1064 .ops = &clkops_null,
1085 .parent = &dsp_fck, 1065 .parent = &dsp_fck,
1086 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1066 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1087 CONFIG_PARTICIPANT,
1088 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1067 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1089 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 1068 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1090 .clksel = dsp_irate_ick_clksel, 1069 .clksel = dsp_irate_ick_clksel,
@@ -1098,7 +1077,7 @@ static struct clk dsp_ick = {
1098 .name = "dsp_ick", /* apparently ipi and isp */ 1077 .name = "dsp_ick", /* apparently ipi and isp */
1099 .ops = &clkops_omap2_dflt_wait, 1078 .ops = &clkops_omap2_dflt_wait,
1100 .parent = &dsp_irate_ick, 1079 .parent = &dsp_irate_ick,
1101 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, 1080 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1102 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 1081 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1103 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ 1082 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1104}; 1083};
@@ -1108,7 +1087,7 @@ static struct clk iva2_1_ick = {
1108 .name = "iva2_1_ick", 1087 .name = "iva2_1_ick",
1109 .ops = &clkops_omap2_dflt_wait, 1088 .ops = &clkops_omap2_dflt_wait,
1110 .parent = &dsp_irate_ick, 1089 .parent = &dsp_irate_ick,
1111 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1090 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1112 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1091 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1113 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1092 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1114}; 1093};
@@ -1122,8 +1101,7 @@ static struct clk iva1_ifck = {
1122 .name = "iva1_ifck", 1101 .name = "iva1_ifck",
1123 .ops = &clkops_omap2_dflt_wait, 1102 .ops = &clkops_omap2_dflt_wait,
1124 .parent = &core_ck, 1103 .parent = &core_ck,
1125 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1104 .flags = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
1126 RATE_PROPAGATES | DELAYED_APP,
1127 .clkdm_name = "iva1_clkdm", 1105 .clkdm_name = "iva1_clkdm",
1128 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1106 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1129 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1107 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1140,7 +1118,6 @@ static struct clk iva1_mpu_int_ifck = {
1140 .name = "iva1_mpu_int_ifck", 1118 .name = "iva1_mpu_int_ifck",
1141 .ops = &clkops_omap2_dflt_wait, 1119 .ops = &clkops_omap2_dflt_wait,
1142 .parent = &iva1_ifck, 1120 .parent = &iva1_ifck,
1143 .flags = CLOCK_IN_OMAP242X,
1144 .clkdm_name = "iva1_clkdm", 1121 .clkdm_name = "iva1_clkdm",
1145 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1122 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1146 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1123 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
@@ -1187,9 +1164,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1187 .name = "core_l3_ck", 1164 .name = "core_l3_ck",
1188 .ops = &clkops_null, 1165 .ops = &clkops_null,
1189 .parent = &core_ck, 1166 .parent = &core_ck,
1190 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1167 .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1191 DELAYED_APP |
1192 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1193 .clkdm_name = "core_l3_clkdm", 1168 .clkdm_name = "core_l3_clkdm",
1194 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1169 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1195 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1170 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -1217,8 +1192,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
1217 .name = "usb_l4_ick", 1192 .name = "usb_l4_ick",
1218 .ops = &clkops_omap2_dflt_wait, 1193 .ops = &clkops_omap2_dflt_wait,
1219 .parent = &core_l3_ck, 1194 .parent = &core_l3_ck,
1220 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1195 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1221 DELAYED_APP | CONFIG_PARTICIPANT,
1222 .clkdm_name = "core_l4_clkdm", 1196 .clkdm_name = "core_l4_clkdm",
1223 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1224 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1198 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -1252,8 +1226,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
1252 .name = "l4_ck", 1226 .name = "l4_ck",
1253 .ops = &clkops_null, 1227 .ops = &clkops_null,
1254 .parent = &core_l3_ck, 1228 .parent = &core_l3_ck,
1255 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1229 .flags = DELAYED_APP | RATE_PROPAGATES,
1256 DELAYED_APP | RATE_PROPAGATES,
1257 .clkdm_name = "core_l4_clkdm", 1230 .clkdm_name = "core_l4_clkdm",
1258 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1231 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1259 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 1232 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
@@ -1291,8 +1264,7 @@ static struct clk ssi_ssr_sst_fck = {
1291 .name = "ssi_fck", 1264 .name = "ssi_fck",
1292 .ops = &clkops_omap2_dflt_wait, 1265 .ops = &clkops_omap2_dflt_wait,
1293 .parent = &core_ck, 1266 .parent = &core_ck,
1294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1267 .flags = DELAYED_APP,
1295 DELAYED_APP,
1296 .clkdm_name = "core_l3_clkdm", 1268 .clkdm_name = "core_l3_clkdm",
1297 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1298 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1270 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -1328,7 +1300,6 @@ static struct clk gfx_3d_fck = {
1328 .name = "gfx_3d_fck", 1300 .name = "gfx_3d_fck",
1329 .ops = &clkops_omap2_dflt_wait, 1301 .ops = &clkops_omap2_dflt_wait,
1330 .parent = &core_l3_ck, 1302 .parent = &core_l3_ck,
1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332 .clkdm_name = "gfx_clkdm", 1303 .clkdm_name = "gfx_clkdm",
1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1304 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1305 .enable_bit = OMAP24XX_EN_3D_SHIFT,
@@ -1344,7 +1315,6 @@ static struct clk gfx_2d_fck = {
1344 .name = "gfx_2d_fck", 1315 .name = "gfx_2d_fck",
1345 .ops = &clkops_omap2_dflt_wait, 1316 .ops = &clkops_omap2_dflt_wait,
1346 .parent = &core_l3_ck, 1317 .parent = &core_l3_ck,
1347 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1348 .clkdm_name = "gfx_clkdm", 1318 .clkdm_name = "gfx_clkdm",
1349 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1319 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1350 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1320 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -1360,7 +1330,6 @@ static struct clk gfx_ick = {
1360 .name = "gfx_ick", /* From l3 */ 1330 .name = "gfx_ick", /* From l3 */
1361 .ops = &clkops_omap2_dflt_wait, 1331 .ops = &clkops_omap2_dflt_wait,
1362 .parent = &core_l3_ck, 1332 .parent = &core_l3_ck,
1363 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1364 .clkdm_name = "gfx_clkdm", 1333 .clkdm_name = "gfx_clkdm",
1365 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1334 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1366 .enable_bit = OMAP_EN_GFX_SHIFT, 1335 .enable_bit = OMAP_EN_GFX_SHIFT,
@@ -1391,7 +1360,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1391 .name = "mdm_ick", 1360 .name = "mdm_ick",
1392 .ops = &clkops_omap2_dflt_wait, 1361 .ops = &clkops_omap2_dflt_wait,
1393 .parent = &core_ck, 1362 .parent = &core_ck,
1394 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1363 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1395 .clkdm_name = "mdm_clkdm", 1364 .clkdm_name = "mdm_clkdm",
1396 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1365 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1397 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1366 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -1407,7 +1376,6 @@ static struct clk mdm_osc_ck = {
1407 .name = "mdm_osc_ck", 1376 .name = "mdm_osc_ck",
1408 .ops = &clkops_omap2_dflt_wait, 1377 .ops = &clkops_omap2_dflt_wait,
1409 .parent = &osc_ck, 1378 .parent = &osc_ck,
1410 .flags = CLOCK_IN_OMAP243X,
1411 .clkdm_name = "mdm_clkdm", 1379 .clkdm_name = "mdm_clkdm",
1412 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1380 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1413 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1381 .enable_bit = OMAP2430_EN_OSC_SHIFT,
@@ -1453,7 +1421,6 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1453 .name = "dss_ick", 1421 .name = "dss_ick",
1454 .ops = &clkops_omap2_dflt, 1422 .ops = &clkops_omap2_dflt,
1455 .parent = &l4_ck, /* really both l3 and l4 */ 1423 .parent = &l4_ck, /* really both l3 and l4 */
1456 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1457 .clkdm_name = "dss_clkdm", 1424 .clkdm_name = "dss_clkdm",
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1425 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1459 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1426 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1464,8 +1431,7 @@ static struct clk dss1_fck = {
1464 .name = "dss1_fck", 1431 .name = "dss1_fck",
1465 .ops = &clkops_omap2_dflt, 1432 .ops = &clkops_omap2_dflt,
1466 .parent = &core_ck, /* Core or sys */ 1433 .parent = &core_ck, /* Core or sys */
1467 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1434 .flags = DELAYED_APP,
1468 DELAYED_APP,
1469 .clkdm_name = "dss_clkdm", 1435 .clkdm_name = "dss_clkdm",
1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1436 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1437 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1498,8 +1464,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1498 .name = "dss2_fck", 1464 .name = "dss2_fck",
1499 .ops = &clkops_omap2_dflt, 1465 .ops = &clkops_omap2_dflt,
1500 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1466 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1501 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1467 .flags = DELAYED_APP,
1502 DELAYED_APP,
1503 .clkdm_name = "dss_clkdm", 1468 .clkdm_name = "dss_clkdm",
1504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1469 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1505 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1470 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
@@ -1514,7 +1479,6 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
1514 .name = "dss_54m_fck", /* 54m tv clk */ 1479 .name = "dss_54m_fck", /* 54m tv clk */
1515 .ops = &clkops_omap2_dflt_wait, 1480 .ops = &clkops_omap2_dflt_wait,
1516 .parent = &func_54m_ck, 1481 .parent = &func_54m_ck,
1517 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1518 .clkdm_name = "dss_clkdm", 1482 .clkdm_name = "dss_clkdm",
1519 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1520 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1484 .enable_bit = OMAP24XX_EN_TV_SHIFT,
@@ -1543,7 +1507,6 @@ static struct clk gpt1_ick = {
1543 .name = "gpt1_ick", 1507 .name = "gpt1_ick",
1544 .ops = &clkops_omap2_dflt_wait, 1508 .ops = &clkops_omap2_dflt_wait,
1545 .parent = &l4_ck, 1509 .parent = &l4_ck,
1546 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547 .clkdm_name = "core_l4_clkdm", 1510 .clkdm_name = "core_l4_clkdm",
1548 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1511 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1549 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1512 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1554,7 +1517,6 @@ static struct clk gpt1_fck = {
1554 .name = "gpt1_fck", 1517 .name = "gpt1_fck",
1555 .ops = &clkops_omap2_dflt_wait, 1518 .ops = &clkops_omap2_dflt_wait,
1556 .parent = &func_32k_ck, 1519 .parent = &func_32k_ck,
1557 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558 .clkdm_name = "core_l4_clkdm", 1520 .clkdm_name = "core_l4_clkdm",
1559 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1521 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1560 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1522 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1571,7 +1533,6 @@ static struct clk gpt2_ick = {
1571 .name = "gpt2_ick", 1533 .name = "gpt2_ick",
1572 .ops = &clkops_omap2_dflt_wait, 1534 .ops = &clkops_omap2_dflt_wait,
1573 .parent = &l4_ck, 1535 .parent = &l4_ck,
1574 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1575 .clkdm_name = "core_l4_clkdm", 1536 .clkdm_name = "core_l4_clkdm",
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1537 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1577 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1538 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1582,7 +1543,6 @@ static struct clk gpt2_fck = {
1582 .name = "gpt2_fck", 1543 .name = "gpt2_fck",
1583 .ops = &clkops_omap2_dflt_wait, 1544 .ops = &clkops_omap2_dflt_wait,
1584 .parent = &func_32k_ck, 1545 .parent = &func_32k_ck,
1585 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1586 .clkdm_name = "core_l4_clkdm", 1546 .clkdm_name = "core_l4_clkdm",
1587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1548 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1597,7 +1557,6 @@ static struct clk gpt3_ick = {
1597 .name = "gpt3_ick", 1557 .name = "gpt3_ick",
1598 .ops = &clkops_omap2_dflt_wait, 1558 .ops = &clkops_omap2_dflt_wait,
1599 .parent = &l4_ck, 1559 .parent = &l4_ck,
1600 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1601 .clkdm_name = "core_l4_clkdm", 1560 .clkdm_name = "core_l4_clkdm",
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1562 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1608,7 +1567,6 @@ static struct clk gpt3_fck = {
1608 .name = "gpt3_fck", 1567 .name = "gpt3_fck",
1609 .ops = &clkops_omap2_dflt_wait, 1568 .ops = &clkops_omap2_dflt_wait,
1610 .parent = &func_32k_ck, 1569 .parent = &func_32k_ck,
1611 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1612 .clkdm_name = "core_l4_clkdm", 1570 .clkdm_name = "core_l4_clkdm",
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1614 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1572 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1623,7 +1581,6 @@ static struct clk gpt4_ick = {
1623 .name = "gpt4_ick", 1581 .name = "gpt4_ick",
1624 .ops = &clkops_omap2_dflt_wait, 1582 .ops = &clkops_omap2_dflt_wait,
1625 .parent = &l4_ck, 1583 .parent = &l4_ck,
1626 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1627 .clkdm_name = "core_l4_clkdm", 1584 .clkdm_name = "core_l4_clkdm",
1628 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1629 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1586 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1634,7 +1591,6 @@ static struct clk gpt4_fck = {
1634 .name = "gpt4_fck", 1591 .name = "gpt4_fck",
1635 .ops = &clkops_omap2_dflt_wait, 1592 .ops = &clkops_omap2_dflt_wait,
1636 .parent = &func_32k_ck, 1593 .parent = &func_32k_ck,
1637 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1638 .clkdm_name = "core_l4_clkdm", 1594 .clkdm_name = "core_l4_clkdm",
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1595 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1640 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1596 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1649,7 +1605,6 @@ static struct clk gpt5_ick = {
1649 .name = "gpt5_ick", 1605 .name = "gpt5_ick",
1650 .ops = &clkops_omap2_dflt_wait, 1606 .ops = &clkops_omap2_dflt_wait,
1651 .parent = &l4_ck, 1607 .parent = &l4_ck,
1652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653 .clkdm_name = "core_l4_clkdm", 1608 .clkdm_name = "core_l4_clkdm",
1654 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1655 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1610 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1660,7 +1615,6 @@ static struct clk gpt5_fck = {
1660 .name = "gpt5_fck", 1615 .name = "gpt5_fck",
1661 .ops = &clkops_omap2_dflt_wait, 1616 .ops = &clkops_omap2_dflt_wait,
1662 .parent = &func_32k_ck, 1617 .parent = &func_32k_ck,
1663 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1664 .clkdm_name = "core_l4_clkdm", 1618 .clkdm_name = "core_l4_clkdm",
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1620 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1675,7 +1629,6 @@ static struct clk gpt6_ick = {
1675 .name = "gpt6_ick", 1629 .name = "gpt6_ick",
1676 .ops = &clkops_omap2_dflt_wait, 1630 .ops = &clkops_omap2_dflt_wait,
1677 .parent = &l4_ck, 1631 .parent = &l4_ck,
1678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1679 .clkdm_name = "core_l4_clkdm", 1632 .clkdm_name = "core_l4_clkdm",
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1633 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1681 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1634 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1686,7 +1639,6 @@ static struct clk gpt6_fck = {
1686 .name = "gpt6_fck", 1639 .name = "gpt6_fck",
1687 .ops = &clkops_omap2_dflt_wait, 1640 .ops = &clkops_omap2_dflt_wait,
1688 .parent = &func_32k_ck, 1641 .parent = &func_32k_ck,
1689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1690 .clkdm_name = "core_l4_clkdm", 1642 .clkdm_name = "core_l4_clkdm",
1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1692 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1644 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1701,7 +1653,6 @@ static struct clk gpt7_ick = {
1701 .name = "gpt7_ick", 1653 .name = "gpt7_ick",
1702 .ops = &clkops_omap2_dflt_wait, 1654 .ops = &clkops_omap2_dflt_wait,
1703 .parent = &l4_ck, 1655 .parent = &l4_ck,
1704 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1706 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1657 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1707 .recalc = &followparent_recalc, 1658 .recalc = &followparent_recalc,
@@ -1711,7 +1662,6 @@ static struct clk gpt7_fck = {
1711 .name = "gpt7_fck", 1662 .name = "gpt7_fck",
1712 .ops = &clkops_omap2_dflt_wait, 1663 .ops = &clkops_omap2_dflt_wait,
1713 .parent = &func_32k_ck, 1664 .parent = &func_32k_ck,
1714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1715 .clkdm_name = "core_l4_clkdm", 1665 .clkdm_name = "core_l4_clkdm",
1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1666 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1717 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1667 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1726,7 +1676,6 @@ static struct clk gpt8_ick = {
1726 .name = "gpt8_ick", 1676 .name = "gpt8_ick",
1727 .ops = &clkops_omap2_dflt_wait, 1677 .ops = &clkops_omap2_dflt_wait,
1728 .parent = &l4_ck, 1678 .parent = &l4_ck,
1729 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1730 .clkdm_name = "core_l4_clkdm", 1679 .clkdm_name = "core_l4_clkdm",
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1681 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1737,7 +1686,6 @@ static struct clk gpt8_fck = {
1737 .name = "gpt8_fck", 1686 .name = "gpt8_fck",
1738 .ops = &clkops_omap2_dflt_wait, 1687 .ops = &clkops_omap2_dflt_wait,
1739 .parent = &func_32k_ck, 1688 .parent = &func_32k_ck,
1740 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741 .clkdm_name = "core_l4_clkdm", 1689 .clkdm_name = "core_l4_clkdm",
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1690 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1743 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1691 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1752,7 +1700,6 @@ static struct clk gpt9_ick = {
1752 .name = "gpt9_ick", 1700 .name = "gpt9_ick",
1753 .ops = &clkops_omap2_dflt_wait, 1701 .ops = &clkops_omap2_dflt_wait,
1754 .parent = &l4_ck, 1702 .parent = &l4_ck,
1755 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756 .clkdm_name = "core_l4_clkdm", 1703 .clkdm_name = "core_l4_clkdm",
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1704 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1705 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1763,7 +1710,6 @@ static struct clk gpt9_fck = {
1763 .name = "gpt9_fck", 1710 .name = "gpt9_fck",
1764 .ops = &clkops_omap2_dflt_wait, 1711 .ops = &clkops_omap2_dflt_wait,
1765 .parent = &func_32k_ck, 1712 .parent = &func_32k_ck,
1766 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1767 .clkdm_name = "core_l4_clkdm", 1713 .clkdm_name = "core_l4_clkdm",
1768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1769 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1715 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1778,7 +1724,6 @@ static struct clk gpt10_ick = {
1778 .name = "gpt10_ick", 1724 .name = "gpt10_ick",
1779 .ops = &clkops_omap2_dflt_wait, 1725 .ops = &clkops_omap2_dflt_wait,
1780 .parent = &l4_ck, 1726 .parent = &l4_ck,
1781 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1782 .clkdm_name = "core_l4_clkdm", 1727 .clkdm_name = "core_l4_clkdm",
1783 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1728 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1729 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1789,7 +1734,6 @@ static struct clk gpt10_fck = {
1789 .name = "gpt10_fck", 1734 .name = "gpt10_fck",
1790 .ops = &clkops_omap2_dflt_wait, 1735 .ops = &clkops_omap2_dflt_wait,
1791 .parent = &func_32k_ck, 1736 .parent = &func_32k_ck,
1792 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1793 .clkdm_name = "core_l4_clkdm", 1737 .clkdm_name = "core_l4_clkdm",
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1795 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1739 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1804,7 +1748,6 @@ static struct clk gpt11_ick = {
1804 .name = "gpt11_ick", 1748 .name = "gpt11_ick",
1805 .ops = &clkops_omap2_dflt_wait, 1749 .ops = &clkops_omap2_dflt_wait,
1806 .parent = &l4_ck, 1750 .parent = &l4_ck,
1807 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1808 .clkdm_name = "core_l4_clkdm", 1751 .clkdm_name = "core_l4_clkdm",
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1753 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1815,7 +1758,6 @@ static struct clk gpt11_fck = {
1815 .name = "gpt11_fck", 1758 .name = "gpt11_fck",
1816 .ops = &clkops_omap2_dflt_wait, 1759 .ops = &clkops_omap2_dflt_wait,
1817 .parent = &func_32k_ck, 1760 .parent = &func_32k_ck,
1818 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1819 .clkdm_name = "core_l4_clkdm", 1761 .clkdm_name = "core_l4_clkdm",
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1821 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1763 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1830,7 +1772,6 @@ static struct clk gpt12_ick = {
1830 .name = "gpt12_ick", 1772 .name = "gpt12_ick",
1831 .ops = &clkops_omap2_dflt_wait, 1773 .ops = &clkops_omap2_dflt_wait,
1832 .parent = &l4_ck, 1774 .parent = &l4_ck,
1833 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1834 .clkdm_name = "core_l4_clkdm", 1775 .clkdm_name = "core_l4_clkdm",
1835 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1836 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1777 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1841,7 +1782,6 @@ static struct clk gpt12_fck = {
1841 .name = "gpt12_fck", 1782 .name = "gpt12_fck",
1842 .ops = &clkops_omap2_dflt_wait, 1783 .ops = &clkops_omap2_dflt_wait,
1843 .parent = &func_32k_ck, 1784 .parent = &func_32k_ck,
1844 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1845 .clkdm_name = "core_l4_clkdm", 1785 .clkdm_name = "core_l4_clkdm",
1846 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1786 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1847 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1787 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1857,7 +1797,6 @@ static struct clk mcbsp1_ick = {
1857 .ops = &clkops_omap2_dflt_wait, 1797 .ops = &clkops_omap2_dflt_wait,
1858 .id = 1, 1798 .id = 1,
1859 .parent = &l4_ck, 1799 .parent = &l4_ck,
1860 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1861 .clkdm_name = "core_l4_clkdm", 1800 .clkdm_name = "core_l4_clkdm",
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1802 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1869,7 +1808,6 @@ static struct clk mcbsp1_fck = {
1869 .ops = &clkops_omap2_dflt_wait, 1808 .ops = &clkops_omap2_dflt_wait,
1870 .id = 1, 1809 .id = 1,
1871 .parent = &func_96m_ck, 1810 .parent = &func_96m_ck,
1872 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1873 .clkdm_name = "core_l4_clkdm", 1811 .clkdm_name = "core_l4_clkdm",
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1812 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1875 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1813 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1881,7 +1819,6 @@ static struct clk mcbsp2_ick = {
1881 .ops = &clkops_omap2_dflt_wait, 1819 .ops = &clkops_omap2_dflt_wait,
1882 .id = 2, 1820 .id = 2,
1883 .parent = &l4_ck, 1821 .parent = &l4_ck,
1884 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1885 .clkdm_name = "core_l4_clkdm", 1822 .clkdm_name = "core_l4_clkdm",
1886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1823 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1824 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1893,7 +1830,6 @@ static struct clk mcbsp2_fck = {
1893 .ops = &clkops_omap2_dflt_wait, 1830 .ops = &clkops_omap2_dflt_wait,
1894 .id = 2, 1831 .id = 2,
1895 .parent = &func_96m_ck, 1832 .parent = &func_96m_ck,
1896 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1897 .clkdm_name = "core_l4_clkdm", 1833 .clkdm_name = "core_l4_clkdm",
1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1899 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1835 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1905,7 +1841,6 @@ static struct clk mcbsp3_ick = {
1905 .ops = &clkops_omap2_dflt_wait, 1841 .ops = &clkops_omap2_dflt_wait,
1906 .id = 3, 1842 .id = 3,
1907 .parent = &l4_ck, 1843 .parent = &l4_ck,
1908 .flags = CLOCK_IN_OMAP243X,
1909 .clkdm_name = "core_l4_clkdm", 1844 .clkdm_name = "core_l4_clkdm",
1910 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1845 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1911 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1846 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1917,7 +1852,6 @@ static struct clk mcbsp3_fck = {
1917 .ops = &clkops_omap2_dflt_wait, 1852 .ops = &clkops_omap2_dflt_wait,
1918 .id = 3, 1853 .id = 3,
1919 .parent = &func_96m_ck, 1854 .parent = &func_96m_ck,
1920 .flags = CLOCK_IN_OMAP243X,
1921 .clkdm_name = "core_l4_clkdm", 1855 .clkdm_name = "core_l4_clkdm",
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1923 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1857 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1929,7 +1863,6 @@ static struct clk mcbsp4_ick = {
1929 .ops = &clkops_omap2_dflt_wait, 1863 .ops = &clkops_omap2_dflt_wait,
1930 .id = 4, 1864 .id = 4,
1931 .parent = &l4_ck, 1865 .parent = &l4_ck,
1932 .flags = CLOCK_IN_OMAP243X,
1933 .clkdm_name = "core_l4_clkdm", 1866 .clkdm_name = "core_l4_clkdm",
1934 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1935 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1868 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1941,7 +1874,6 @@ static struct clk mcbsp4_fck = {
1941 .ops = &clkops_omap2_dflt_wait, 1874 .ops = &clkops_omap2_dflt_wait,
1942 .id = 4, 1875 .id = 4,
1943 .parent = &func_96m_ck, 1876 .parent = &func_96m_ck,
1944 .flags = CLOCK_IN_OMAP243X,
1945 .clkdm_name = "core_l4_clkdm", 1877 .clkdm_name = "core_l4_clkdm",
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1878 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1947 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1879 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1953,7 +1885,6 @@ static struct clk mcbsp5_ick = {
1953 .ops = &clkops_omap2_dflt_wait, 1885 .ops = &clkops_omap2_dflt_wait,
1954 .id = 5, 1886 .id = 5,
1955 .parent = &l4_ck, 1887 .parent = &l4_ck,
1956 .flags = CLOCK_IN_OMAP243X,
1957 .clkdm_name = "core_l4_clkdm", 1888 .clkdm_name = "core_l4_clkdm",
1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1959 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1890 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1965,7 +1896,6 @@ static struct clk mcbsp5_fck = {
1965 .ops = &clkops_omap2_dflt_wait, 1896 .ops = &clkops_omap2_dflt_wait,
1966 .id = 5, 1897 .id = 5,
1967 .parent = &func_96m_ck, 1898 .parent = &func_96m_ck,
1968 .flags = CLOCK_IN_OMAP243X,
1969 .clkdm_name = "core_l4_clkdm", 1899 .clkdm_name = "core_l4_clkdm",
1970 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1900 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1971 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1901 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1978,7 +1908,6 @@ static struct clk mcspi1_ick = {
1978 .id = 1, 1908 .id = 1,
1979 .parent = &l4_ck, 1909 .parent = &l4_ck,
1980 .clkdm_name = "core_l4_clkdm", 1910 .clkdm_name = "core_l4_clkdm",
1981 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1912 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1984 .recalc = &followparent_recalc, 1913 .recalc = &followparent_recalc,
@@ -1989,7 +1918,6 @@ static struct clk mcspi1_fck = {
1989 .ops = &clkops_omap2_dflt_wait, 1918 .ops = &clkops_omap2_dflt_wait,
1990 .id = 1, 1919 .id = 1,
1991 .parent = &func_48m_ck, 1920 .parent = &func_48m_ck,
1992 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1993 .clkdm_name = "core_l4_clkdm", 1921 .clkdm_name = "core_l4_clkdm",
1994 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1995 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1923 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -2001,7 +1929,6 @@ static struct clk mcspi2_ick = {
2001 .ops = &clkops_omap2_dflt_wait, 1929 .ops = &clkops_omap2_dflt_wait,
2002 .id = 2, 1930 .id = 2,
2003 .parent = &l4_ck, 1931 .parent = &l4_ck,
2004 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2005 .clkdm_name = "core_l4_clkdm", 1932 .clkdm_name = "core_l4_clkdm",
2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1933 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1934 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -2013,7 +1940,6 @@ static struct clk mcspi2_fck = {
2013 .ops = &clkops_omap2_dflt_wait, 1940 .ops = &clkops_omap2_dflt_wait,
2014 .id = 2, 1941 .id = 2,
2015 .parent = &func_48m_ck, 1942 .parent = &func_48m_ck,
2016 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2017 .clkdm_name = "core_l4_clkdm", 1943 .clkdm_name = "core_l4_clkdm",
2018 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1944 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2019 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1945 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -2025,7 +1951,6 @@ static struct clk mcspi3_ick = {
2025 .ops = &clkops_omap2_dflt_wait, 1951 .ops = &clkops_omap2_dflt_wait,
2026 .id = 3, 1952 .id = 3,
2027 .parent = &l4_ck, 1953 .parent = &l4_ck,
2028 .flags = CLOCK_IN_OMAP243X,
2029 .clkdm_name = "core_l4_clkdm", 1954 .clkdm_name = "core_l4_clkdm",
2030 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1955 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2031 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1956 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -2037,7 +1962,6 @@ static struct clk mcspi3_fck = {
2037 .ops = &clkops_omap2_dflt_wait, 1962 .ops = &clkops_omap2_dflt_wait,
2038 .id = 3, 1963 .id = 3,
2039 .parent = &func_48m_ck, 1964 .parent = &func_48m_ck,
2040 .flags = CLOCK_IN_OMAP243X,
2041 .clkdm_name = "core_l4_clkdm", 1965 .clkdm_name = "core_l4_clkdm",
2042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1966 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2043 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1967 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -2048,7 +1972,6 @@ static struct clk uart1_ick = {
2048 .name = "uart1_ick", 1972 .name = "uart1_ick",
2049 .ops = &clkops_omap2_dflt_wait, 1973 .ops = &clkops_omap2_dflt_wait,
2050 .parent = &l4_ck, 1974 .parent = &l4_ck,
2051 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2052 .clkdm_name = "core_l4_clkdm", 1975 .clkdm_name = "core_l4_clkdm",
2053 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2054 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1977 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -2059,7 +1982,6 @@ static struct clk uart1_fck = {
2059 .name = "uart1_fck", 1982 .name = "uart1_fck",
2060 .ops = &clkops_omap2_dflt_wait, 1983 .ops = &clkops_omap2_dflt_wait,
2061 .parent = &func_48m_ck, 1984 .parent = &func_48m_ck,
2062 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2063 .clkdm_name = "core_l4_clkdm", 1985 .clkdm_name = "core_l4_clkdm",
2064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2065 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1987 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -2070,7 +1992,6 @@ static struct clk uart2_ick = {
2070 .name = "uart2_ick", 1992 .name = "uart2_ick",
2071 .ops = &clkops_omap2_dflt_wait, 1993 .ops = &clkops_omap2_dflt_wait,
2072 .parent = &l4_ck, 1994 .parent = &l4_ck,
2073 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2074 .clkdm_name = "core_l4_clkdm", 1995 .clkdm_name = "core_l4_clkdm",
2075 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2076 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 1997 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2081,7 +2002,6 @@ static struct clk uart2_fck = {
2081 .name = "uart2_fck", 2002 .name = "uart2_fck",
2082 .ops = &clkops_omap2_dflt_wait, 2003 .ops = &clkops_omap2_dflt_wait,
2083 .parent = &func_48m_ck, 2004 .parent = &func_48m_ck,
2084 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2085 .clkdm_name = "core_l4_clkdm", 2005 .clkdm_name = "core_l4_clkdm",
2086 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2087 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2007 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2092,7 +2012,6 @@ static struct clk uart3_ick = {
2092 .name = "uart3_ick", 2012 .name = "uart3_ick",
2093 .ops = &clkops_omap2_dflt_wait, 2013 .ops = &clkops_omap2_dflt_wait,
2094 .parent = &l4_ck, 2014 .parent = &l4_ck,
2095 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2096 .clkdm_name = "core_l4_clkdm", 2015 .clkdm_name = "core_l4_clkdm",
2097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2098 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2017 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2103,7 +2022,6 @@ static struct clk uart3_fck = {
2103 .name = "uart3_fck", 2022 .name = "uart3_fck",
2104 .ops = &clkops_omap2_dflt_wait, 2023 .ops = &clkops_omap2_dflt_wait,
2105 .parent = &func_48m_ck, 2024 .parent = &func_48m_ck,
2106 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2107 .clkdm_name = "core_l4_clkdm", 2025 .clkdm_name = "core_l4_clkdm",
2108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2109 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2027 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2114,7 +2032,6 @@ static struct clk gpios_ick = {
2114 .name = "gpios_ick", 2032 .name = "gpios_ick",
2115 .ops = &clkops_omap2_dflt_wait, 2033 .ops = &clkops_omap2_dflt_wait,
2116 .parent = &l4_ck, 2034 .parent = &l4_ck,
2117 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2118 .clkdm_name = "core_l4_clkdm", 2035 .clkdm_name = "core_l4_clkdm",
2119 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2036 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2120 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2037 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2125,7 +2042,6 @@ static struct clk gpios_fck = {
2125 .name = "gpios_fck", 2042 .name = "gpios_fck",
2126 .ops = &clkops_omap2_dflt_wait, 2043 .ops = &clkops_omap2_dflt_wait,
2127 .parent = &func_32k_ck, 2044 .parent = &func_32k_ck,
2128 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2129 .clkdm_name = "wkup_clkdm", 2045 .clkdm_name = "wkup_clkdm",
2130 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2046 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2131 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2047 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2136,7 +2052,6 @@ static struct clk mpu_wdt_ick = {
2136 .name = "mpu_wdt_ick", 2052 .name = "mpu_wdt_ick",
2137 .ops = &clkops_omap2_dflt_wait, 2053 .ops = &clkops_omap2_dflt_wait,
2138 .parent = &l4_ck, 2054 .parent = &l4_ck,
2139 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2140 .clkdm_name = "core_l4_clkdm", 2055 .clkdm_name = "core_l4_clkdm",
2141 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2056 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2142 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2057 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2147,7 +2062,6 @@ static struct clk mpu_wdt_fck = {
2147 .name = "mpu_wdt_fck", 2062 .name = "mpu_wdt_fck",
2148 .ops = &clkops_omap2_dflt_wait, 2063 .ops = &clkops_omap2_dflt_wait,
2149 .parent = &func_32k_ck, 2064 .parent = &func_32k_ck,
2150 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2151 .clkdm_name = "wkup_clkdm", 2065 .clkdm_name = "wkup_clkdm",
2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2066 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2153 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2067 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2158,8 +2072,7 @@ static struct clk sync_32k_ick = {
2158 .name = "sync_32k_ick", 2072 .name = "sync_32k_ick",
2159 .ops = &clkops_omap2_dflt_wait, 2073 .ops = &clkops_omap2_dflt_wait,
2160 .parent = &l4_ck, 2074 .parent = &l4_ck,
2161 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2075 .flags = ENABLE_ON_INIT,
2162 ENABLE_ON_INIT,
2163 .clkdm_name = "core_l4_clkdm", 2076 .clkdm_name = "core_l4_clkdm",
2164 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2077 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2165 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2078 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
@@ -2170,7 +2083,6 @@ static struct clk wdt1_ick = {
2170 .name = "wdt1_ick", 2083 .name = "wdt1_ick",
2171 .ops = &clkops_omap2_dflt_wait, 2084 .ops = &clkops_omap2_dflt_wait,
2172 .parent = &l4_ck, 2085 .parent = &l4_ck,
2173 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2174 .clkdm_name = "core_l4_clkdm", 2086 .clkdm_name = "core_l4_clkdm",
2175 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2087 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2176 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2088 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
@@ -2181,8 +2093,7 @@ static struct clk omapctrl_ick = {
2181 .name = "omapctrl_ick", 2093 .name = "omapctrl_ick",
2182 .ops = &clkops_omap2_dflt_wait, 2094 .ops = &clkops_omap2_dflt_wait,
2183 .parent = &l4_ck, 2095 .parent = &l4_ck,
2184 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2096 .flags = ENABLE_ON_INIT,
2185 ENABLE_ON_INIT,
2186 .clkdm_name = "core_l4_clkdm", 2097 .clkdm_name = "core_l4_clkdm",
2187 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2098 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2188 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2099 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
@@ -2193,7 +2104,6 @@ static struct clk icr_ick = {
2193 .name = "icr_ick", 2104 .name = "icr_ick",
2194 .ops = &clkops_omap2_dflt_wait, 2105 .ops = &clkops_omap2_dflt_wait,
2195 .parent = &l4_ck, 2106 .parent = &l4_ck,
2196 .flags = CLOCK_IN_OMAP243X,
2197 .clkdm_name = "core_l4_clkdm", 2107 .clkdm_name = "core_l4_clkdm",
2198 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2108 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2199 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2109 .enable_bit = OMAP2430_EN_ICR_SHIFT,
@@ -2204,7 +2114,6 @@ static struct clk cam_ick = {
2204 .name = "cam_ick", 2114 .name = "cam_ick",
2205 .ops = &clkops_omap2_dflt, 2115 .ops = &clkops_omap2_dflt,
2206 .parent = &l4_ck, 2116 .parent = &l4_ck,
2207 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2208 .clkdm_name = "core_l4_clkdm", 2117 .clkdm_name = "core_l4_clkdm",
2209 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2118 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2210 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2119 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2220,7 +2129,6 @@ static struct clk cam_fck = {
2220 .name = "cam_fck", 2129 .name = "cam_fck",
2221 .ops = &clkops_omap2_dflt, 2130 .ops = &clkops_omap2_dflt,
2222 .parent = &func_96m_ck, 2131 .parent = &func_96m_ck,
2223 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2224 .clkdm_name = "core_l3_clkdm", 2132 .clkdm_name = "core_l3_clkdm",
2225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2133 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2226 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2134 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2231,7 +2139,6 @@ static struct clk mailboxes_ick = {
2231 .name = "mailboxes_ick", 2139 .name = "mailboxes_ick",
2232 .ops = &clkops_omap2_dflt_wait, 2140 .ops = &clkops_omap2_dflt_wait,
2233 .parent = &l4_ck, 2141 .parent = &l4_ck,
2234 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2235 .clkdm_name = "core_l4_clkdm", 2142 .clkdm_name = "core_l4_clkdm",
2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2143 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2237 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2144 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
@@ -2242,7 +2149,6 @@ static struct clk wdt4_ick = {
2242 .name = "wdt4_ick", 2149 .name = "wdt4_ick",
2243 .ops = &clkops_omap2_dflt_wait, 2150 .ops = &clkops_omap2_dflt_wait,
2244 .parent = &l4_ck, 2151 .parent = &l4_ck,
2245 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2246 .clkdm_name = "core_l4_clkdm", 2152 .clkdm_name = "core_l4_clkdm",
2247 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2153 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2248 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2154 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2253,7 +2159,6 @@ static struct clk wdt4_fck = {
2253 .name = "wdt4_fck", 2159 .name = "wdt4_fck",
2254 .ops = &clkops_omap2_dflt_wait, 2160 .ops = &clkops_omap2_dflt_wait,
2255 .parent = &func_32k_ck, 2161 .parent = &func_32k_ck,
2256 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2257 .clkdm_name = "core_l4_clkdm", 2162 .clkdm_name = "core_l4_clkdm",
2258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2259 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2164 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2264,7 +2169,6 @@ static struct clk wdt3_ick = {
2264 .name = "wdt3_ick", 2169 .name = "wdt3_ick",
2265 .ops = &clkops_omap2_dflt_wait, 2170 .ops = &clkops_omap2_dflt_wait,
2266 .parent = &l4_ck, 2171 .parent = &l4_ck,
2267 .flags = CLOCK_IN_OMAP242X,
2268 .clkdm_name = "core_l4_clkdm", 2172 .clkdm_name = "core_l4_clkdm",
2269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2173 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2270 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2174 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2275,7 +2179,6 @@ static struct clk wdt3_fck = {
2275 .name = "wdt3_fck", 2179 .name = "wdt3_fck",
2276 .ops = &clkops_omap2_dflt_wait, 2180 .ops = &clkops_omap2_dflt_wait,
2277 .parent = &func_32k_ck, 2181 .parent = &func_32k_ck,
2278 .flags = CLOCK_IN_OMAP242X,
2279 .clkdm_name = "core_l4_clkdm", 2182 .clkdm_name = "core_l4_clkdm",
2280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2281 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2184 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2286,7 +2189,6 @@ static struct clk mspro_ick = {
2286 .name = "mspro_ick", 2189 .name = "mspro_ick",
2287 .ops = &clkops_omap2_dflt_wait, 2190 .ops = &clkops_omap2_dflt_wait,
2288 .parent = &l4_ck, 2191 .parent = &l4_ck,
2289 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2290 .clkdm_name = "core_l4_clkdm", 2192 .clkdm_name = "core_l4_clkdm",
2291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2193 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2292 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2194 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2297,7 +2199,6 @@ static struct clk mspro_fck = {
2297 .name = "mspro_fck", 2199 .name = "mspro_fck",
2298 .ops = &clkops_omap2_dflt_wait, 2200 .ops = &clkops_omap2_dflt_wait,
2299 .parent = &func_96m_ck, 2201 .parent = &func_96m_ck,
2300 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2301 .clkdm_name = "core_l4_clkdm", 2202 .clkdm_name = "core_l4_clkdm",
2302 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2203 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2303 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2204 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2308,7 +2209,6 @@ static struct clk mmc_ick = {
2308 .name = "mmc_ick", 2209 .name = "mmc_ick",
2309 .ops = &clkops_omap2_dflt_wait, 2210 .ops = &clkops_omap2_dflt_wait,
2310 .parent = &l4_ck, 2211 .parent = &l4_ck,
2311 .flags = CLOCK_IN_OMAP242X,
2312 .clkdm_name = "core_l4_clkdm", 2212 .clkdm_name = "core_l4_clkdm",
2313 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2213 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2314 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2214 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2319,7 +2219,6 @@ static struct clk mmc_fck = {
2319 .name = "mmc_fck", 2219 .name = "mmc_fck",
2320 .ops = &clkops_omap2_dflt_wait, 2220 .ops = &clkops_omap2_dflt_wait,
2321 .parent = &func_96m_ck, 2221 .parent = &func_96m_ck,
2322 .flags = CLOCK_IN_OMAP242X,
2323 .clkdm_name = "core_l4_clkdm", 2222 .clkdm_name = "core_l4_clkdm",
2324 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2223 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2325 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2224 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2330,7 +2229,6 @@ static struct clk fac_ick = {
2330 .name = "fac_ick", 2229 .name = "fac_ick",
2331 .ops = &clkops_omap2_dflt_wait, 2230 .ops = &clkops_omap2_dflt_wait,
2332 .parent = &l4_ck, 2231 .parent = &l4_ck,
2333 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2334 .clkdm_name = "core_l4_clkdm", 2232 .clkdm_name = "core_l4_clkdm",
2335 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2233 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2336 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2234 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2341,7 +2239,6 @@ static struct clk fac_fck = {
2341 .name = "fac_fck", 2239 .name = "fac_fck",
2342 .ops = &clkops_omap2_dflt_wait, 2240 .ops = &clkops_omap2_dflt_wait,
2343 .parent = &func_12m_ck, 2241 .parent = &func_12m_ck,
2344 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2345 .clkdm_name = "core_l4_clkdm", 2242 .clkdm_name = "core_l4_clkdm",
2346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2347 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2244 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2352,7 +2249,6 @@ static struct clk eac_ick = {
2352 .name = "eac_ick", 2249 .name = "eac_ick",
2353 .ops = &clkops_omap2_dflt_wait, 2250 .ops = &clkops_omap2_dflt_wait,
2354 .parent = &l4_ck, 2251 .parent = &l4_ck,
2355 .flags = CLOCK_IN_OMAP242X,
2356 .clkdm_name = "core_l4_clkdm", 2252 .clkdm_name = "core_l4_clkdm",
2357 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2358 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2254 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2363,7 +2259,6 @@ static struct clk eac_fck = {
2363 .name = "eac_fck", 2259 .name = "eac_fck",
2364 .ops = &clkops_omap2_dflt_wait, 2260 .ops = &clkops_omap2_dflt_wait,
2365 .parent = &func_96m_ck, 2261 .parent = &func_96m_ck,
2366 .flags = CLOCK_IN_OMAP242X,
2367 .clkdm_name = "core_l4_clkdm", 2262 .clkdm_name = "core_l4_clkdm",
2368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2263 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2369 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2264 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2374,7 +2269,6 @@ static struct clk hdq_ick = {
2374 .name = "hdq_ick", 2269 .name = "hdq_ick",
2375 .ops = &clkops_omap2_dflt_wait, 2270 .ops = &clkops_omap2_dflt_wait,
2376 .parent = &l4_ck, 2271 .parent = &l4_ck,
2377 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2378 .clkdm_name = "core_l4_clkdm", 2272 .clkdm_name = "core_l4_clkdm",
2379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2273 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2380 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2274 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2385,7 +2279,6 @@ static struct clk hdq_fck = {
2385 .name = "hdq_fck", 2279 .name = "hdq_fck",
2386 .ops = &clkops_omap2_dflt_wait, 2280 .ops = &clkops_omap2_dflt_wait,
2387 .parent = &func_12m_ck, 2281 .parent = &func_12m_ck,
2388 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2389 .clkdm_name = "core_l4_clkdm", 2282 .clkdm_name = "core_l4_clkdm",
2390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2391 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2284 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2397,7 +2290,6 @@ static struct clk i2c2_ick = {
2397 .ops = &clkops_omap2_dflt_wait, 2290 .ops = &clkops_omap2_dflt_wait,
2398 .id = 2, 2291 .id = 2,
2399 .parent = &l4_ck, 2292 .parent = &l4_ck,
2400 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2401 .clkdm_name = "core_l4_clkdm", 2293 .clkdm_name = "core_l4_clkdm",
2402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2294 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2403 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2295 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2409,7 +2301,6 @@ static struct clk i2c2_fck = {
2409 .ops = &clkops_omap2_dflt_wait, 2301 .ops = &clkops_omap2_dflt_wait,
2410 .id = 2, 2302 .id = 2,
2411 .parent = &func_12m_ck, 2303 .parent = &func_12m_ck,
2412 .flags = CLOCK_IN_OMAP242X,
2413 .clkdm_name = "core_l4_clkdm", 2304 .clkdm_name = "core_l4_clkdm",
2414 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2305 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2415 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2306 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2421,7 +2312,6 @@ static struct clk i2chs2_fck = {
2421 .ops = &clkops_omap2_dflt_wait, 2312 .ops = &clkops_omap2_dflt_wait,
2422 .id = 2, 2313 .id = 2,
2423 .parent = &func_96m_ck, 2314 .parent = &func_96m_ck,
2424 .flags = CLOCK_IN_OMAP243X,
2425 .clkdm_name = "core_l4_clkdm", 2315 .clkdm_name = "core_l4_clkdm",
2426 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2427 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2317 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
@@ -2433,7 +2323,6 @@ static struct clk i2c1_ick = {
2433 .ops = &clkops_omap2_dflt_wait, 2323 .ops = &clkops_omap2_dflt_wait,
2434 .id = 1, 2324 .id = 1,
2435 .parent = &l4_ck, 2325 .parent = &l4_ck,
2436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2437 .clkdm_name = "core_l4_clkdm", 2326 .clkdm_name = "core_l4_clkdm",
2438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2439 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2328 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2445,7 +2334,6 @@ static struct clk i2c1_fck = {
2445 .ops = &clkops_omap2_dflt_wait, 2334 .ops = &clkops_omap2_dflt_wait,
2446 .id = 1, 2335 .id = 1,
2447 .parent = &func_12m_ck, 2336 .parent = &func_12m_ck,
2448 .flags = CLOCK_IN_OMAP242X,
2449 .clkdm_name = "core_l4_clkdm", 2337 .clkdm_name = "core_l4_clkdm",
2450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2451 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2339 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2457,7 +2345,6 @@ static struct clk i2chs1_fck = {
2457 .ops = &clkops_omap2_dflt_wait, 2345 .ops = &clkops_omap2_dflt_wait,
2458 .id = 1, 2346 .id = 1,
2459 .parent = &func_96m_ck, 2347 .parent = &func_96m_ck,
2460 .flags = CLOCK_IN_OMAP243X,
2461 .clkdm_name = "core_l4_clkdm", 2348 .clkdm_name = "core_l4_clkdm",
2462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2463 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2350 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
@@ -2468,8 +2355,7 @@ static struct clk gpmc_fck = {
2468 .name = "gpmc_fck", 2355 .name = "gpmc_fck",
2469 .ops = &clkops_null, /* RMK: missing? */ 2356 .ops = &clkops_null, /* RMK: missing? */
2470 .parent = &core_l3_ck, 2357 .parent = &core_l3_ck,
2471 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2358 .flags = ENABLE_ON_INIT,
2472 ENABLE_ON_INIT,
2473 .clkdm_name = "core_l3_clkdm", 2359 .clkdm_name = "core_l3_clkdm",
2474 .recalc = &followparent_recalc, 2360 .recalc = &followparent_recalc,
2475}; 2361};
@@ -2478,7 +2364,6 @@ static struct clk sdma_fck = {
2478 .name = "sdma_fck", 2364 .name = "sdma_fck",
2479 .ops = &clkops_null, /* RMK: missing? */ 2365 .ops = &clkops_null, /* RMK: missing? */
2480 .parent = &core_l3_ck, 2366 .parent = &core_l3_ck,
2481 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2482 .clkdm_name = "core_l3_clkdm", 2367 .clkdm_name = "core_l3_clkdm",
2483 .recalc = &followparent_recalc, 2368 .recalc = &followparent_recalc,
2484}; 2369};
@@ -2487,7 +2372,6 @@ static struct clk sdma_ick = {
2487 .name = "sdma_ick", 2372 .name = "sdma_ick",
2488 .ops = &clkops_null, /* RMK: missing? */ 2373 .ops = &clkops_null, /* RMK: missing? */
2489 .parent = &l4_ck, 2374 .parent = &l4_ck,
2490 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2491 .clkdm_name = "core_l3_clkdm", 2375 .clkdm_name = "core_l3_clkdm",
2492 .recalc = &followparent_recalc, 2376 .recalc = &followparent_recalc,
2493}; 2377};
@@ -2496,7 +2380,6 @@ static struct clk vlynq_ick = {
2496 .name = "vlynq_ick", 2380 .name = "vlynq_ick",
2497 .ops = &clkops_omap2_dflt_wait, 2381 .ops = &clkops_omap2_dflt_wait,
2498 .parent = &core_l3_ck, 2382 .parent = &core_l3_ck,
2499 .flags = CLOCK_IN_OMAP242X,
2500 .clkdm_name = "core_l3_clkdm", 2383 .clkdm_name = "core_l3_clkdm",
2501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2384 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2502 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2385 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2532,7 +2415,7 @@ static struct clk vlynq_fck = {
2532 .name = "vlynq_fck", 2415 .name = "vlynq_fck",
2533 .ops = &clkops_omap2_dflt_wait, 2416 .ops = &clkops_omap2_dflt_wait,
2534 .parent = &func_96m_ck, 2417 .parent = &func_96m_ck,
2535 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2418 .flags = DELAYED_APP,
2536 .clkdm_name = "core_l3_clkdm", 2419 .clkdm_name = "core_l3_clkdm",
2537 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2538 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2421 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2549,7 +2432,7 @@ static struct clk sdrc_ick = {
2549 .name = "sdrc_ick", 2432 .name = "sdrc_ick",
2550 .ops = &clkops_omap2_dflt_wait, 2433 .ops = &clkops_omap2_dflt_wait,
2551 .parent = &l4_ck, 2434 .parent = &l4_ck,
2552 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2435 .flags = ENABLE_ON_INIT,
2553 .clkdm_name = "core_l4_clkdm", 2436 .clkdm_name = "core_l4_clkdm",
2554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2555 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2438 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
@@ -2560,7 +2443,6 @@ static struct clk des_ick = {
2560 .name = "des_ick", 2443 .name = "des_ick",
2561 .ops = &clkops_omap2_dflt_wait, 2444 .ops = &clkops_omap2_dflt_wait,
2562 .parent = &l4_ck, 2445 .parent = &l4_ck,
2563 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2564 .clkdm_name = "core_l4_clkdm", 2446 .clkdm_name = "core_l4_clkdm",
2565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2566 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2448 .enable_bit = OMAP24XX_EN_DES_SHIFT,
@@ -2571,7 +2453,6 @@ static struct clk sha_ick = {
2571 .name = "sha_ick", 2453 .name = "sha_ick",
2572 .ops = &clkops_omap2_dflt_wait, 2454 .ops = &clkops_omap2_dflt_wait,
2573 .parent = &l4_ck, 2455 .parent = &l4_ck,
2574 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2575 .clkdm_name = "core_l4_clkdm", 2456 .clkdm_name = "core_l4_clkdm",
2576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2457 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2577 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2458 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
@@ -2582,7 +2463,6 @@ static struct clk rng_ick = {
2582 .name = "rng_ick", 2463 .name = "rng_ick",
2583 .ops = &clkops_omap2_dflt_wait, 2464 .ops = &clkops_omap2_dflt_wait,
2584 .parent = &l4_ck, 2465 .parent = &l4_ck,
2585 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2586 .clkdm_name = "core_l4_clkdm", 2466 .clkdm_name = "core_l4_clkdm",
2587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2467 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2588 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2468 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
@@ -2593,7 +2473,6 @@ static struct clk aes_ick = {
2593 .name = "aes_ick", 2473 .name = "aes_ick",
2594 .ops = &clkops_omap2_dflt_wait, 2474 .ops = &clkops_omap2_dflt_wait,
2595 .parent = &l4_ck, 2475 .parent = &l4_ck,
2596 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2597 .clkdm_name = "core_l4_clkdm", 2476 .clkdm_name = "core_l4_clkdm",
2598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2477 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2599 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2478 .enable_bit = OMAP24XX_EN_AES_SHIFT,
@@ -2604,7 +2483,6 @@ static struct clk pka_ick = {
2604 .name = "pka_ick", 2483 .name = "pka_ick",
2605 .ops = &clkops_omap2_dflt_wait, 2484 .ops = &clkops_omap2_dflt_wait,
2606 .parent = &l4_ck, 2485 .parent = &l4_ck,
2607 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2608 .clkdm_name = "core_l4_clkdm", 2486 .clkdm_name = "core_l4_clkdm",
2609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2487 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2610 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2488 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
@@ -2615,7 +2493,6 @@ static struct clk usb_fck = {
2615 .name = "usb_fck", 2493 .name = "usb_fck",
2616 .ops = &clkops_omap2_dflt_wait, 2494 .ops = &clkops_omap2_dflt_wait,
2617 .parent = &func_48m_ck, 2495 .parent = &func_48m_ck,
2618 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2619 .clkdm_name = "core_l3_clkdm", 2496 .clkdm_name = "core_l3_clkdm",
2620 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2621 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2498 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -2626,7 +2503,6 @@ static struct clk usbhs_ick = {
2626 .name = "usbhs_ick", 2503 .name = "usbhs_ick",
2627 .ops = &clkops_omap2_dflt_wait, 2504 .ops = &clkops_omap2_dflt_wait,
2628 .parent = &core_l3_ck, 2505 .parent = &core_l3_ck,
2629 .flags = CLOCK_IN_OMAP243X,
2630 .clkdm_name = "core_l3_clkdm", 2506 .clkdm_name = "core_l3_clkdm",
2631 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2507 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2632 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2508 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
@@ -2637,7 +2513,6 @@ static struct clk mmchs1_ick = {
2637 .name = "mmchs_ick", 2513 .name = "mmchs_ick",
2638 .ops = &clkops_omap2_dflt_wait, 2514 .ops = &clkops_omap2_dflt_wait,
2639 .parent = &l4_ck, 2515 .parent = &l4_ck,
2640 .flags = CLOCK_IN_OMAP243X,
2641 .clkdm_name = "core_l4_clkdm", 2516 .clkdm_name = "core_l4_clkdm",
2642 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2517 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2643 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2518 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2648,7 +2523,6 @@ static struct clk mmchs1_fck = {
2648 .name = "mmchs_fck", 2523 .name = "mmchs_fck",
2649 .ops = &clkops_omap2_dflt_wait, 2524 .ops = &clkops_omap2_dflt_wait,
2650 .parent = &func_96m_ck, 2525 .parent = &func_96m_ck,
2651 .flags = CLOCK_IN_OMAP243X,
2652 .clkdm_name = "core_l3_clkdm", 2526 .clkdm_name = "core_l3_clkdm",
2653 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2654 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2528 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2660,7 +2534,6 @@ static struct clk mmchs2_ick = {
2660 .ops = &clkops_omap2_dflt_wait, 2534 .ops = &clkops_omap2_dflt_wait,
2661 .id = 1, 2535 .id = 1,
2662 .parent = &l4_ck, 2536 .parent = &l4_ck,
2663 .flags = CLOCK_IN_OMAP243X,
2664 .clkdm_name = "core_l4_clkdm", 2537 .clkdm_name = "core_l4_clkdm",
2665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2666 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2539 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2672,7 +2545,6 @@ static struct clk mmchs2_fck = {
2672 .ops = &clkops_omap2_dflt_wait, 2545 .ops = &clkops_omap2_dflt_wait,
2673 .id = 1, 2546 .id = 1,
2674 .parent = &func_96m_ck, 2547 .parent = &func_96m_ck,
2675 .flags = CLOCK_IN_OMAP243X,
2676 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2548 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2677 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2549 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2678 .recalc = &followparent_recalc, 2550 .recalc = &followparent_recalc,
@@ -2682,7 +2554,6 @@ static struct clk gpio5_ick = {
2682 .name = "gpio5_ick", 2554 .name = "gpio5_ick",
2683 .ops = &clkops_omap2_dflt_wait, 2555 .ops = &clkops_omap2_dflt_wait,
2684 .parent = &l4_ck, 2556 .parent = &l4_ck,
2685 .flags = CLOCK_IN_OMAP243X,
2686 .clkdm_name = "core_l4_clkdm", 2557 .clkdm_name = "core_l4_clkdm",
2687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2688 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2559 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2693,7 +2564,6 @@ static struct clk gpio5_fck = {
2693 .name = "gpio5_fck", 2564 .name = "gpio5_fck",
2694 .ops = &clkops_omap2_dflt_wait, 2565 .ops = &clkops_omap2_dflt_wait,
2695 .parent = &func_32k_ck, 2566 .parent = &func_32k_ck,
2696 .flags = CLOCK_IN_OMAP243X,
2697 .clkdm_name = "core_l4_clkdm", 2567 .clkdm_name = "core_l4_clkdm",
2698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2699 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2569 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2704,7 +2574,6 @@ static struct clk mdm_intc_ick = {
2704 .name = "mdm_intc_ick", 2574 .name = "mdm_intc_ick",
2705 .ops = &clkops_omap2_dflt_wait, 2575 .ops = &clkops_omap2_dflt_wait,
2706 .parent = &l4_ck, 2576 .parent = &l4_ck,
2707 .flags = CLOCK_IN_OMAP243X,
2708 .clkdm_name = "core_l4_clkdm", 2577 .clkdm_name = "core_l4_clkdm",
2709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2710 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2579 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
@@ -2715,7 +2584,6 @@ static struct clk mmchsdb1_fck = {
2715 .name = "mmchsdb_fck", 2584 .name = "mmchsdb_fck",
2716 .ops = &clkops_omap2_dflt_wait, 2585 .ops = &clkops_omap2_dflt_wait,
2717 .parent = &func_32k_ck, 2586 .parent = &func_32k_ck,
2718 .flags = CLOCK_IN_OMAP243X,
2719 .clkdm_name = "core_l4_clkdm", 2587 .clkdm_name = "core_l4_clkdm",
2720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2721 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2589 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
@@ -2727,7 +2595,6 @@ static struct clk mmchsdb2_fck = {
2727 .ops = &clkops_omap2_dflt_wait, 2595 .ops = &clkops_omap2_dflt_wait,
2728 .id = 1, 2596 .id = 1,
2729 .parent = &func_32k_ck, 2597 .parent = &func_32k_ck,
2730 .flags = CLOCK_IN_OMAP243X,
2731 .clkdm_name = "core_l4_clkdm", 2598 .clkdm_name = "core_l4_clkdm",
2732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2733 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2600 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
@@ -2751,166 +2618,12 @@ static struct clk mmchsdb2_fck = {
2751static struct clk virt_prcm_set = { 2618static struct clk virt_prcm_set = {
2752 .name = "virt_prcm_set", 2619 .name = "virt_prcm_set",
2753 .ops = &clkops_null, 2620 .ops = &clkops_null,
2754 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2621 .flags = DELAYED_APP,
2755 DELAYED_APP,
2756 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2622 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2757 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ 2623 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2758 .set_rate = &omap2_select_table_rate, 2624 .set_rate = &omap2_select_table_rate,
2759 .round_rate = &omap2_round_to_table_rate, 2625 .round_rate = &omap2_round_to_table_rate,
2760}; 2626};
2761 2627
2762static struct clk *onchip_24xx_clks[] __initdata = {
2763 /* external root sources */
2764 &func_32k_ck,
2765 &osc_ck,
2766 &sys_ck,
2767 &alt_ck,
2768 /* internal analog sources */
2769 &dpll_ck,
2770 &apll96_ck,
2771 &apll54_ck,
2772 /* internal prcm root sources */
2773 &func_54m_ck,
2774 &core_ck,
2775 &func_96m_ck,
2776 &func_48m_ck,
2777 &func_12m_ck,
2778 &wdt1_osc_ck,
2779 &sys_clkout_src,
2780 &sys_clkout,
2781 &sys_clkout2_src,
2782 &sys_clkout2,
2783 &emul_ck,
2784 /* mpu domain clocks */
2785 &mpu_ck,
2786 /* dsp domain clocks */
2787 &dsp_fck,
2788 &dsp_irate_ick,
2789 &dsp_ick, /* 242x */
2790 &iva2_1_ick, /* 243x */
2791 &iva1_ifck, /* 242x */
2792 &iva1_mpu_int_ifck, /* 242x */
2793 /* GFX domain clocks */
2794 &gfx_3d_fck,
2795 &gfx_2d_fck,
2796 &gfx_ick,
2797 /* Modem domain clocks */
2798 &mdm_ick,
2799 &mdm_osc_ck,
2800 /* DSS domain clocks */
2801 &dss_ick,
2802 &dss1_fck,
2803 &dss2_fck,
2804 &dss_54m_fck,
2805 /* L3 domain clocks */
2806 &core_l3_ck,
2807 &ssi_ssr_sst_fck,
2808 &usb_l4_ick,
2809 /* L4 domain clocks */
2810 &l4_ck, /* used as both core_l4 and wu_l4 */
2811 /* virtual meta-group clock */
2812 &virt_prcm_set,
2813 /* general l4 interface ck, multi-parent functional clk */
2814 &gpt1_ick,
2815 &gpt1_fck,
2816 &gpt2_ick,
2817 &gpt2_fck,
2818 &gpt3_ick,
2819 &gpt3_fck,
2820 &gpt4_ick,
2821 &gpt4_fck,
2822 &gpt5_ick,
2823 &gpt5_fck,
2824 &gpt6_ick,
2825 &gpt6_fck,
2826 &gpt7_ick,
2827 &gpt7_fck,
2828 &gpt8_ick,
2829 &gpt8_fck,
2830 &gpt9_ick,
2831 &gpt9_fck,
2832 &gpt10_ick,
2833 &gpt10_fck,
2834 &gpt11_ick,
2835 &gpt11_fck,
2836 &gpt12_ick,
2837 &gpt12_fck,
2838 &mcbsp1_ick,
2839 &mcbsp1_fck,
2840 &mcbsp2_ick,
2841 &mcbsp2_fck,
2842 &mcbsp3_ick,
2843 &mcbsp3_fck,
2844 &mcbsp4_ick,
2845 &mcbsp4_fck,
2846 &mcbsp5_ick,
2847 &mcbsp5_fck,
2848 &mcspi1_ick,
2849 &mcspi1_fck,
2850 &mcspi2_ick,
2851 &mcspi2_fck,
2852 &mcspi3_ick,
2853 &mcspi3_fck,
2854 &uart1_ick,
2855 &uart1_fck,
2856 &uart2_ick,
2857 &uart2_fck,
2858 &uart3_ick,
2859 &uart3_fck,
2860 &gpios_ick,
2861 &gpios_fck,
2862 &mpu_wdt_ick,
2863 &mpu_wdt_fck,
2864 &sync_32k_ick,
2865 &wdt1_ick,
2866 &omapctrl_ick,
2867 &icr_ick,
2868 &cam_fck,
2869 &cam_ick,
2870 &mailboxes_ick,
2871 &wdt4_ick,
2872 &wdt4_fck,
2873 &wdt3_ick,
2874 &wdt3_fck,
2875 &mspro_ick,
2876 &mspro_fck,
2877 &mmc_ick,
2878 &mmc_fck,
2879 &fac_ick,
2880 &fac_fck,
2881 &eac_ick,
2882 &eac_fck,
2883 &hdq_ick,
2884 &hdq_fck,
2885 &i2c1_ick,
2886 &i2c1_fck,
2887 &i2chs1_fck,
2888 &i2c2_ick,
2889 &i2c2_fck,
2890 &i2chs2_fck,
2891 &gpmc_fck,
2892 &sdma_fck,
2893 &sdma_ick,
2894 &vlynq_ick,
2895 &vlynq_fck,
2896 &sdrc_ick,
2897 &des_ick,
2898 &sha_ick,
2899 &rng_ick,
2900 &aes_ick,
2901 &pka_ick,
2902 &usb_fck,
2903 &usbhs_ick,
2904 &mmchs1_ick,
2905 &mmchs1_fck,
2906 &mmchs2_ick,
2907 &mmchs2_fck,
2908 &gpio5_ick,
2909 &gpio5_fck,
2910 &mdm_intc_ick,
2911 &mmchsdb1_fck,
2912 &mmchsdb2_fck,
2913};
2914
2915#endif 2628#endif
2916 2629
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index fc7b6831f3eb..90372131055b 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -16,6 +16,7 @@ config ARCH_OMAP1
16config ARCH_OMAP2 16config ARCH_OMAP2
17 bool "TI OMAP2" 17 bool "TI OMAP2"
18 select CPU_V6 18 select CPU_V6
19 select COMMON_CLKDEV
19 20
20config ARCH_OMAP3 21config ARCH_OMAP3
21 bool "TI OMAP3" 22 bool "TI OMAP3"
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 2af4bc24cfe9..214dc46d6ad1 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -136,9 +136,7 @@ extern const struct clkops clkops_null;
136#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ 136#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
137#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ 137#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
138#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ 138#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
139/* bits 13-24 are currently free */ 139/* bits 13-26 are currently free */
140#define CLOCK_IN_OMAP242X (1 << 25)
141#define CLOCK_IN_OMAP243X (1 << 26)
142#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ 140#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
143#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ 141#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
144#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ 142#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 03:21:50 -0500