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authorRajendra Nayak <rnayak@ti.com>2010-02-23 00:09:39 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 19:45:16 -0500
commit547760502665eacc1f9fd9f3782b8b7f27c56bd4 (patch)
treef87a3b03f5e9e51789815e5741e76a9c55933a7c /arch
parent30962d9d0c74f6b00a7dece200fa08392b62817d (diff)
OMAP4: clock: Rename leaf clock nodes to end with a _ick or _fck
All leaf clock nodes are renamed for OMAP4 to have a clk name which end with a _ick or a _fck. This is done so that the naming convention is same as that followed on older OMAPs. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c561
1 files changed, 297 insertions, 264 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 6deca1e01608..c0825cffdbbc 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * OMAP4 Clock data 2 * OMAP4 Clock data
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com) 8 * Rajendra Nayak (rnayak@ti.com)
@@ -1254,8 +1254,8 @@ static struct clk syc_clk_div_ck = {
1254 1254
1255/* Leaf clocks controlled by modules */ 1255/* Leaf clocks controlled by modules */
1256 1256
1257static struct clk aes1_ck = { 1257static struct clk aes1_fck = {
1258 .name = "aes1_ck", 1258 .name = "aes1_fck",
1259 .ops = &clkops_omap2_dflt, 1259 .ops = &clkops_omap2_dflt,
1260 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, 1260 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1264,8 +1264,8 @@ static struct clk aes1_ck = {
1264 .recalc = &followparent_recalc, 1264 .recalc = &followparent_recalc,
1265}; 1265};
1266 1266
1267static struct clk aes2_ck = { 1267static struct clk aes2_fck = {
1268 .name = "aes2_ck", 1268 .name = "aes2_fck",
1269 .ops = &clkops_omap2_dflt, 1269 .ops = &clkops_omap2_dflt,
1270 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, 1270 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1274,8 +1274,8 @@ static struct clk aes2_ck = {
1274 .recalc = &followparent_recalc, 1274 .recalc = &followparent_recalc,
1275}; 1275};
1276 1276
1277static struct clk aess_ck = { 1277static struct clk aess_fck = {
1278 .name = "aess_ck", 1278 .name = "aess_fck",
1279 .ops = &clkops_omap2_dflt, 1279 .ops = &clkops_omap2_dflt,
1280 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, 1280 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1281 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1281 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1284,8 +1284,8 @@ static struct clk aess_ck = {
1284 .recalc = &followparent_recalc, 1284 .recalc = &followparent_recalc,
1285}; 1285};
1286 1286
1287static struct clk cust_efuse_ck = { 1287static struct clk cust_efuse_fck = {
1288 .name = "cust_efuse_ck", 1288 .name = "cust_efuse_fck",
1289 .ops = &clkops_omap2_dflt, 1289 .ops = &clkops_omap2_dflt,
1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, 1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1294,8 +1294,8 @@ static struct clk cust_efuse_ck = {
1294 .recalc = &followparent_recalc, 1294 .recalc = &followparent_recalc,
1295}; 1295};
1296 1296
1297static struct clk des3des_ck = { 1297static struct clk des3des_fck = {
1298 .name = "des3des_ck", 1298 .name = "des3des_fck",
1299 .ops = &clkops_omap2_dflt, 1299 .ops = &clkops_omap2_dflt,
1300 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, 1300 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1301 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1301 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1329,9 +1329,9 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = {
1329 { .parent = NULL }, 1329 { .parent = NULL },
1330}; 1330};
1331 1331
1332/* Merged func_dmic_abe_gfclk into dmic_ck */ 1332/* Merged func_dmic_abe_gfclk into dmic */
1333static struct clk dmic_ck = { 1333static struct clk dmic_fck = {
1334 .name = "dmic_ck", 1334 .name = "dmic_fck",
1335 .parent = &dmic_sync_mux_ck, 1335 .parent = &dmic_sync_mux_ck,
1336 .clksel = func_dmic_abe_gfclk_sel, 1336 .clksel = func_dmic_abe_gfclk_sel,
1337 .init = &omap2_init_clksel_parent, 1337 .init = &omap2_init_clksel_parent,
@@ -1344,8 +1344,8 @@ static struct clk dmic_ck = {
1344 .clkdm_name = "abe_clkdm", 1344 .clkdm_name = "abe_clkdm",
1345}; 1345};
1346 1346
1347static struct clk dss_ck = { 1347static struct clk dss_fck = {
1348 .name = "dss_ck", 1348 .name = "dss_fck",
1349 .ops = &clkops_omap2_dflt, 1349 .ops = &clkops_omap2_dflt,
1350 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1350 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1351 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1351 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1354,8 +1354,8 @@ static struct clk dss_ck = {
1354 .recalc = &followparent_recalc, 1354 .recalc = &followparent_recalc,
1355}; 1355};
1356 1356
1357static struct clk ducati_ck = { 1357static struct clk ducati_ick = {
1358 .name = "ducati_ck", 1358 .name = "ducati_ick",
1359 .ops = &clkops_omap2_dflt, 1359 .ops = &clkops_omap2_dflt,
1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1364,8 +1364,8 @@ static struct clk ducati_ck = {
1364 .recalc = &followparent_recalc, 1364 .recalc = &followparent_recalc,
1365}; 1365};
1366 1366
1367static struct clk emif1_ck = { 1367static struct clk emif1_ick = {
1368 .name = "emif1_ck", 1368 .name = "emif1_ick",
1369 .ops = &clkops_omap2_dflt, 1369 .ops = &clkops_omap2_dflt,
1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, 1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1374,8 +1374,8 @@ static struct clk emif1_ck = {
1374 .recalc = &followparent_recalc, 1374 .recalc = &followparent_recalc,
1375}; 1375};
1376 1376
1377static struct clk emif2_ck = { 1377static struct clk emif2_ick = {
1378 .name = "emif2_ck", 1378 .name = "emif2_ick",
1379 .ops = &clkops_omap2_dflt, 1379 .ops = &clkops_omap2_dflt,
1380 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, 1380 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1381 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1381 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1389,9 +1389,9 @@ static const struct clksel fdif_fclk_div[] = {
1389 { .parent = NULL }, 1389 { .parent = NULL },
1390}; 1390};
1391 1391
1392/* Merged fdif_fclk into fdif_ck */ 1392/* Merged fdif_fclk into fdif */
1393static struct clk fdif_ck = { 1393static struct clk fdif_fck = {
1394 .name = "fdif_ck", 1394 .name = "fdif_fck",
1395 .parent = &dpll_per_m4_ck, 1395 .parent = &dpll_per_m4_ck,
1396 .clksel = fdif_fclk_div, 1396 .clksel = fdif_fclk_div,
1397 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, 1397 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
@@ -1428,9 +1428,9 @@ static const struct clksel sgx_clk_mux_sel[] = {
1428 { .parent = NULL }, 1428 { .parent = NULL },
1429}; 1429};
1430 1430
1431/* Merged sgx_clk_mux into gfx_ck */ 1431/* Merged sgx_clk_mux into gfx */
1432static struct clk gfx_ck = { 1432static struct clk gfx_fck = {
1433 .name = "gfx_ck", 1433 .name = "gfx_fck",
1434 .parent = &dpll_core_m7_ck, 1434 .parent = &dpll_core_m7_ck,
1435 .clksel = sgx_clk_mux_sel, 1435 .clksel = sgx_clk_mux_sel,
1436 .init = &omap2_init_clksel_parent, 1436 .init = &omap2_init_clksel_parent,
@@ -1443,8 +1443,8 @@ static struct clk gfx_ck = {
1443 .clkdm_name = "l3_gfx_clkdm", 1443 .clkdm_name = "l3_gfx_clkdm",
1444}; 1444};
1445 1445
1446static struct clk gpio1_ck = { 1446static struct clk gpio1_ick = {
1447 .name = "gpio1_ck", 1447 .name = "gpio1_ick",
1448 .ops = &clkops_omap2_dflt, 1448 .ops = &clkops_omap2_dflt,
1449 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 1449 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1450 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1450 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1453,8 +1453,8 @@ static struct clk gpio1_ck = {
1453 .recalc = &followparent_recalc, 1453 .recalc = &followparent_recalc,
1454}; 1454};
1455 1455
1456static struct clk gpio2_ck = { 1456static struct clk gpio2_ick = {
1457 .name = "gpio2_ck", 1457 .name = "gpio2_ick",
1458 .ops = &clkops_omap2_dflt, 1458 .ops = &clkops_omap2_dflt,
1459 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, 1459 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1460 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1460 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1463,8 +1463,8 @@ static struct clk gpio2_ck = {
1463 .recalc = &followparent_recalc, 1463 .recalc = &followparent_recalc,
1464}; 1464};
1465 1465
1466static struct clk gpio3_ck = { 1466static struct clk gpio3_ick = {
1467 .name = "gpio3_ck", 1467 .name = "gpio3_ick",
1468 .ops = &clkops_omap2_dflt, 1468 .ops = &clkops_omap2_dflt,
1469 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 1469 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1470 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1470 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1473,8 +1473,8 @@ static struct clk gpio3_ck = {
1473 .recalc = &followparent_recalc, 1473 .recalc = &followparent_recalc,
1474}; 1474};
1475 1475
1476static struct clk gpio4_ck = { 1476static struct clk gpio4_ick = {
1477 .name = "gpio4_ck", 1477 .name = "gpio4_ick",
1478 .ops = &clkops_omap2_dflt, 1478 .ops = &clkops_omap2_dflt,
1479 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, 1479 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1480 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1480 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1483,8 +1483,8 @@ static struct clk gpio4_ck = {
1483 .recalc = &followparent_recalc, 1483 .recalc = &followparent_recalc,
1484}; 1484};
1485 1485
1486static struct clk gpio5_ck = { 1486static struct clk gpio5_ick = {
1487 .name = "gpio5_ck", 1487 .name = "gpio5_ick",
1488 .ops = &clkops_omap2_dflt, 1488 .ops = &clkops_omap2_dflt,
1489 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, 1489 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1490 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1490 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1493,8 +1493,8 @@ static struct clk gpio5_ck = {
1493 .recalc = &followparent_recalc, 1493 .recalc = &followparent_recalc,
1494}; 1494};
1495 1495
1496static struct clk gpio6_ck = { 1496static struct clk gpio6_ick = {
1497 .name = "gpio6_ck", 1497 .name = "gpio6_ick",
1498 .ops = &clkops_omap2_dflt, 1498 .ops = &clkops_omap2_dflt,
1499 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, 1499 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1500 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1500 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1503,8 +1503,8 @@ static struct clk gpio6_ck = {
1503 .recalc = &followparent_recalc, 1503 .recalc = &followparent_recalc,
1504}; 1504};
1505 1505
1506static struct clk gpmc_ck = { 1506static struct clk gpmc_ick = {
1507 .name = "gpmc_ck", 1507 .name = "gpmc_ick",
1508 .ops = &clkops_omap2_dflt, 1508 .ops = &clkops_omap2_dflt,
1509 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, 1509 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1510 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1510 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1519,9 +1519,12 @@ static const struct clksel dmt1_clk_mux_sel[] = {
1519 { .parent = NULL }, 1519 { .parent = NULL },
1520}; 1520};
1521 1521
1522/* Merged dmt1_clk_mux into gptimer1_ck */ 1522/*
1523static struct clk gptimer1_ck = { 1523 * Merged dmt1_clk_mux into gptimer1
1524 .name = "gptimer1_ck", 1524 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
1525 */
1526static struct clk gpt1_fck = {
1527 .name = "gpt1_fck",
1525 .parent = &sys_clkin_ck, 1528 .parent = &sys_clkin_ck,
1526 .clksel = dmt1_clk_mux_sel, 1529 .clksel = dmt1_clk_mux_sel,
1527 .init = &omap2_init_clksel_parent, 1530 .init = &omap2_init_clksel_parent,
@@ -1534,9 +1537,12 @@ static struct clk gptimer1_ck = {
1534 .clkdm_name = "l4_wkup_clkdm", 1537 .clkdm_name = "l4_wkup_clkdm",
1535}; 1538};
1536 1539
1537/* Merged cm2_dm10_mux into gptimer10_ck */ 1540/*
1538static struct clk gptimer10_ck = { 1541 * Merged cm2_dm10_mux into gptimer10
1539 .name = "gptimer10_ck", 1542 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1543 */
1544static struct clk gpt10_fck = {
1545 .name = "gpt10_fck",
1540 .parent = &sys_clkin_ck, 1546 .parent = &sys_clkin_ck,
1541 .clksel = dmt1_clk_mux_sel, 1547 .clksel = dmt1_clk_mux_sel,
1542 .init = &omap2_init_clksel_parent, 1548 .init = &omap2_init_clksel_parent,
@@ -1549,9 +1555,12 @@ static struct clk gptimer10_ck = {
1549 .clkdm_name = "l4_per_clkdm", 1555 .clkdm_name = "l4_per_clkdm",
1550}; 1556};
1551 1557
1552/* Merged cm2_dm11_mux into gptimer11_ck */ 1558/*
1553static struct clk gptimer11_ck = { 1559 * Merged cm2_dm11_mux into gptimer11
1554 .name = "gptimer11_ck", 1560 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1561 */
1562static struct clk gpt11_fck = {
1563 .name = "gpt11_fck",
1555 .parent = &sys_clkin_ck, 1564 .parent = &sys_clkin_ck,
1556 .clksel = dmt1_clk_mux_sel, 1565 .clksel = dmt1_clk_mux_sel,
1557 .init = &omap2_init_clksel_parent, 1566 .init = &omap2_init_clksel_parent,
@@ -1564,9 +1573,12 @@ static struct clk gptimer11_ck = {
1564 .clkdm_name = "l4_per_clkdm", 1573 .clkdm_name = "l4_per_clkdm",
1565}; 1574};
1566 1575
1567/* Merged cm2_dm2_mux into gptimer2_ck */ 1576/*
1568static struct clk gptimer2_ck = { 1577 * Merged cm2_dm2_mux into gptimer2
1569 .name = "gptimer2_ck", 1578 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1579 */
1580static struct clk gpt2_fck = {
1581 .name = "gpt2_fck",
1570 .parent = &sys_clkin_ck, 1582 .parent = &sys_clkin_ck,
1571 .clksel = dmt1_clk_mux_sel, 1583 .clksel = dmt1_clk_mux_sel,
1572 .init = &omap2_init_clksel_parent, 1584 .init = &omap2_init_clksel_parent,
@@ -1579,9 +1591,12 @@ static struct clk gptimer2_ck = {
1579 .clkdm_name = "l4_per_clkdm", 1591 .clkdm_name = "l4_per_clkdm",
1580}; 1592};
1581 1593
1582/* Merged cm2_dm3_mux into gptimer3_ck */ 1594/*
1583static struct clk gptimer3_ck = { 1595 * Merged cm2_dm3_mux into gptimer3
1584 .name = "gptimer3_ck", 1596 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1597 */
1598static struct clk gpt3_fck = {
1599 .name = "gpt3_fck",
1585 .parent = &sys_clkin_ck, 1600 .parent = &sys_clkin_ck,
1586 .clksel = dmt1_clk_mux_sel, 1601 .clksel = dmt1_clk_mux_sel,
1587 .init = &omap2_init_clksel_parent, 1602 .init = &omap2_init_clksel_parent,
@@ -1594,9 +1609,12 @@ static struct clk gptimer3_ck = {
1594 .clkdm_name = "l4_per_clkdm", 1609 .clkdm_name = "l4_per_clkdm",
1595}; 1610};
1596 1611
1597/* Merged cm2_dm4_mux into gptimer4_ck */ 1612/*
1598static struct clk gptimer4_ck = { 1613 * Merged cm2_dm4_mux into gptimer4
1599 .name = "gptimer4_ck", 1614 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1615 */
1616static struct clk gpt4_fck = {
1617 .name = "gpt4_fck",
1600 .parent = &sys_clkin_ck, 1618 .parent = &sys_clkin_ck,
1601 .clksel = dmt1_clk_mux_sel, 1619 .clksel = dmt1_clk_mux_sel,
1602 .init = &omap2_init_clksel_parent, 1620 .init = &omap2_init_clksel_parent,
@@ -1615,9 +1633,12 @@ static const struct clksel timer5_sync_mux_sel[] = {
1615 { .parent = NULL }, 1633 { .parent = NULL },
1616}; 1634};
1617 1635
1618/* Merged timer5_sync_mux into gptimer5_ck */ 1636/*
1619static struct clk gptimer5_ck = { 1637 * Merged timer5_sync_mux into gptimer5
1620 .name = "gptimer5_ck", 1638 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
1639 */
1640static struct clk gpt5_fck = {
1641 .name = "gpt5_fck",
1621 .parent = &syc_clk_div_ck, 1642 .parent = &syc_clk_div_ck,
1622 .clksel = timer5_sync_mux_sel, 1643 .clksel = timer5_sync_mux_sel,
1623 .init = &omap2_init_clksel_parent, 1644 .init = &omap2_init_clksel_parent,
@@ -1630,9 +1651,12 @@ static struct clk gptimer5_ck = {
1630 .clkdm_name = "abe_clkdm", 1651 .clkdm_name = "abe_clkdm",
1631}; 1652};
1632 1653
1633/* Merged timer6_sync_mux into gptimer6_ck */ 1654/*
1634static struct clk gptimer6_ck = { 1655 * Merged timer6_sync_mux into gptimer6
1635 .name = "gptimer6_ck", 1656 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1657 */
1658static struct clk gpt6_fck = {
1659 .name = "gpt6_fck",
1636 .parent = &syc_clk_div_ck, 1660 .parent = &syc_clk_div_ck,
1637 .clksel = timer5_sync_mux_sel, 1661 .clksel = timer5_sync_mux_sel,
1638 .init = &omap2_init_clksel_parent, 1662 .init = &omap2_init_clksel_parent,
@@ -1645,9 +1669,12 @@ static struct clk gptimer6_ck = {
1645 .clkdm_name = "abe_clkdm", 1669 .clkdm_name = "abe_clkdm",
1646}; 1670};
1647 1671
1648/* Merged timer7_sync_mux into gptimer7_ck */ 1672/*
1649static struct clk gptimer7_ck = { 1673 * Merged timer7_sync_mux into gptimer7
1650 .name = "gptimer7_ck", 1674 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1675 */
1676static struct clk gpt7_fck = {
1677 .name = "gpt7_fck",
1651 .parent = &syc_clk_div_ck, 1678 .parent = &syc_clk_div_ck,
1652 .clksel = timer5_sync_mux_sel, 1679 .clksel = timer5_sync_mux_sel,
1653 .init = &omap2_init_clksel_parent, 1680 .init = &omap2_init_clksel_parent,
@@ -1660,9 +1687,12 @@ static struct clk gptimer7_ck = {
1660 .clkdm_name = "abe_clkdm", 1687 .clkdm_name = "abe_clkdm",
1661}; 1688};
1662 1689
1663/* Merged timer8_sync_mux into gptimer8_ck */ 1690/*
1664static struct clk gptimer8_ck = { 1691 * Merged timer8_sync_mux into gptimer8
1665 .name = "gptimer8_ck", 1692 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1693 */
1694static struct clk gpt8_fck = {
1695 .name = "gpt8_fck",
1666 .parent = &syc_clk_div_ck, 1696 .parent = &syc_clk_div_ck,
1667 .clksel = timer5_sync_mux_sel, 1697 .clksel = timer5_sync_mux_sel,
1668 .init = &omap2_init_clksel_parent, 1698 .init = &omap2_init_clksel_parent,
@@ -1675,9 +1705,12 @@ static struct clk gptimer8_ck = {
1675 .clkdm_name = "abe_clkdm", 1705 .clkdm_name = "abe_clkdm",
1676}; 1706};
1677 1707
1678/* Merged cm2_dm9_mux into gptimer9_ck */ 1708/*
1679static struct clk gptimer9_ck = { 1709 * Merged cm2_dm9_mux into gptimer9
1680 .name = "gptimer9_ck", 1710 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1711 */
1712static struct clk gpt9_fck = {
1713 .name = "gpt9_fck",
1681 .parent = &sys_clkin_ck, 1714 .parent = &sys_clkin_ck,
1682 .clksel = dmt1_clk_mux_sel, 1715 .clksel = dmt1_clk_mux_sel,
1683 .init = &omap2_init_clksel_parent, 1716 .init = &omap2_init_clksel_parent,
@@ -1690,8 +1723,8 @@ static struct clk gptimer9_ck = {
1690 .clkdm_name = "l4_per_clkdm", 1723 .clkdm_name = "l4_per_clkdm",
1691}; 1724};
1692 1725
1693static struct clk hdq1w_ck = { 1726static struct clk hdq1w_fck = {
1694 .name = "hdq1w_ck", 1727 .name = "hdq1w_fck",
1695 .ops = &clkops_omap2_dflt, 1728 .ops = &clkops_omap2_dflt,
1696 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, 1729 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1697 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1730 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1700,9 +1733,9 @@ static struct clk hdq1w_ck = {
1700 .recalc = &followparent_recalc, 1733 .recalc = &followparent_recalc,
1701}; 1734};
1702 1735
1703/* Merged hsi_fclk into hsi_ck */ 1736/* Merged hsi_fclk into hsi */
1704static struct clk hsi_ck = { 1737static struct clk hsi_ick = {
1705 .name = "hsi_ck", 1738 .name = "hsi_ick",
1706 .parent = &dpll_per_m2x2_ck, 1739 .parent = &dpll_per_m2x2_ck,
1707 .clksel = per_sgx_fclk_div, 1740 .clksel = per_sgx_fclk_div,
1708 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1741 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
@@ -1716,8 +1749,8 @@ static struct clk hsi_ck = {
1716 .clkdm_name = "l3_init_clkdm", 1749 .clkdm_name = "l3_init_clkdm",
1717}; 1750};
1718 1751
1719static struct clk i2c1_ck = { 1752static struct clk i2c1_fck = {
1720 .name = "i2c1_ck", 1753 .name = "i2c1_fck",
1721 .ops = &clkops_omap2_dflt, 1754 .ops = &clkops_omap2_dflt,
1722 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, 1755 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1723 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1756 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1726,8 +1759,8 @@ static struct clk i2c1_ck = {
1726 .recalc = &followparent_recalc, 1759 .recalc = &followparent_recalc,
1727}; 1760};
1728 1761
1729static struct clk i2c2_ck = { 1762static struct clk i2c2_fck = {
1730 .name = "i2c2_ck", 1763 .name = "i2c2_fck",
1731 .ops = &clkops_omap2_dflt, 1764 .ops = &clkops_omap2_dflt,
1732 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, 1765 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1733 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1766 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1736,8 +1769,8 @@ static struct clk i2c2_ck = {
1736 .recalc = &followparent_recalc, 1769 .recalc = &followparent_recalc,
1737}; 1770};
1738 1771
1739static struct clk i2c3_ck = { 1772static struct clk i2c3_fck = {
1740 .name = "i2c3_ck", 1773 .name = "i2c3_fck",
1741 .ops = &clkops_omap2_dflt, 1774 .ops = &clkops_omap2_dflt,
1742 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, 1775 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1743 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1776 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1746,8 +1779,8 @@ static struct clk i2c3_ck = {
1746 .recalc = &followparent_recalc, 1779 .recalc = &followparent_recalc,
1747}; 1780};
1748 1781
1749static struct clk i2c4_ck = { 1782static struct clk i2c4_fck = {
1750 .name = "i2c4_ck", 1783 .name = "i2c4_fck",
1751 .ops = &clkops_omap2_dflt, 1784 .ops = &clkops_omap2_dflt,
1752 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, 1785 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1753 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1786 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1756,8 +1789,8 @@ static struct clk i2c4_ck = {
1756 .recalc = &followparent_recalc, 1789 .recalc = &followparent_recalc,
1757}; 1790};
1758 1791
1759static struct clk iss_ck = { 1792static struct clk iss_fck = {
1760 .name = "iss_ck", 1793 .name = "iss_fck",
1761 .ops = &clkops_omap2_dflt, 1794 .ops = &clkops_omap2_dflt,
1762 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, 1795 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1763 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1796 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1766,8 +1799,8 @@ static struct clk iss_ck = {
1766 .recalc = &followparent_recalc, 1799 .recalc = &followparent_recalc,
1767}; 1800};
1768 1801
1769static struct clk ivahd_ck = { 1802static struct clk ivahd_ick = {
1770 .name = "ivahd_ck", 1803 .name = "ivahd_ick",
1771 .ops = &clkops_omap2_dflt, 1804 .ops = &clkops_omap2_dflt,
1772 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1805 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1773 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1806 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1776,8 +1809,8 @@ static struct clk ivahd_ck = {
1776 .recalc = &followparent_recalc, 1809 .recalc = &followparent_recalc,
1777}; 1810};
1778 1811
1779static struct clk keyboard_ck = { 1812static struct clk keyboard_fck = {
1780 .name = "keyboard_ck", 1813 .name = "keyboard_fck",
1781 .ops = &clkops_omap2_dflt, 1814 .ops = &clkops_omap2_dflt,
1782 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 1815 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1783 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1816 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1786,8 +1819,8 @@ static struct clk keyboard_ck = {
1786 .recalc = &followparent_recalc, 1819 .recalc = &followparent_recalc,
1787}; 1820};
1788 1821
1789static struct clk l3_instr_interconnect_ck = { 1822static struct clk l3_instr_interconnect_ick = {
1790 .name = "l3_instr_interconnect_ck", 1823 .name = "l3_instr_interconnect_ick",
1791 .ops = &clkops_omap2_dflt, 1824 .ops = &clkops_omap2_dflt,
1792 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1825 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1793 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1826 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1796,8 +1829,8 @@ static struct clk l3_instr_interconnect_ck = {
1796 .recalc = &followparent_recalc, 1829 .recalc = &followparent_recalc,
1797}; 1830};
1798 1831
1799static struct clk l3_interconnect_3_ck = { 1832static struct clk l3_interconnect_3_ick = {
1800 .name = "l3_interconnect_3_ck", 1833 .name = "l3_interconnect_3_ick",
1801 .ops = &clkops_omap2_dflt, 1834 .ops = &clkops_omap2_dflt,
1802 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1835 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1803 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1836 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1824,9 +1857,9 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1824 { .parent = NULL }, 1857 { .parent = NULL },
1825}; 1858};
1826 1859
1827/* Merged func_mcasp_abe_gfclk into mcasp_ck */ 1860/* Merged func_mcasp_abe_gfclk into mcasp */
1828static struct clk mcasp_ck = { 1861static struct clk mcasp_fck = {
1829 .name = "mcasp_ck", 1862 .name = "mcasp_fck",
1830 .parent = &mcasp_sync_mux_ck, 1863 .parent = &mcasp_sync_mux_ck,
1831 .clksel = func_mcasp_abe_gfclk_sel, 1864 .clksel = func_mcasp_abe_gfclk_sel,
1832 .init = &omap2_init_clksel_parent, 1865 .init = &omap2_init_clksel_parent,
@@ -1857,9 +1890,9 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
1857 { .parent = NULL }, 1890 { .parent = NULL },
1858}; 1891};
1859 1892
1860/* Merged func_mcbsp1_gfclk into mcbsp1_ck */ 1893/* Merged func_mcbsp1_gfclk into mcbsp1 */
1861static struct clk mcbsp1_ck = { 1894static struct clk mcbsp1_fck = {
1862 .name = "mcbsp1_ck", 1895 .name = "mcbsp1_fck",
1863 .parent = &mcbsp1_sync_mux_ck, 1896 .parent = &mcbsp1_sync_mux_ck,
1864 .clksel = func_mcbsp1_gfclk_sel, 1897 .clksel = func_mcbsp1_gfclk_sel,
1865 .init = &omap2_init_clksel_parent, 1898 .init = &omap2_init_clksel_parent,
@@ -1890,9 +1923,9 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
1890 { .parent = NULL }, 1923 { .parent = NULL },
1891}; 1924};
1892 1925
1893/* Merged func_mcbsp2_gfclk into mcbsp2_ck */ 1926/* Merged func_mcbsp2_gfclk into mcbsp2 */
1894static struct clk mcbsp2_ck = { 1927static struct clk mcbsp2_fck = {
1895 .name = "mcbsp2_ck", 1928 .name = "mcbsp2_fck",
1896 .parent = &mcbsp2_sync_mux_ck, 1929 .parent = &mcbsp2_sync_mux_ck,
1897 .clksel = func_mcbsp2_gfclk_sel, 1930 .clksel = func_mcbsp2_gfclk_sel,
1898 .init = &omap2_init_clksel_parent, 1931 .init = &omap2_init_clksel_parent,
@@ -1923,9 +1956,9 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
1923 { .parent = NULL }, 1956 { .parent = NULL },
1924}; 1957};
1925 1958
1926/* Merged func_mcbsp3_gfclk into mcbsp3_ck */ 1959/* Merged func_mcbsp3_gfclk into mcbsp3 */
1927static struct clk mcbsp3_ck = { 1960static struct clk mcbsp3_fck = {
1928 .name = "mcbsp3_ck", 1961 .name = "mcbsp3_fck",
1929 .parent = &mcbsp3_sync_mux_ck, 1962 .parent = &mcbsp3_sync_mux_ck,
1930 .clksel = func_mcbsp3_gfclk_sel, 1963 .clksel = func_mcbsp3_gfclk_sel,
1931 .init = &omap2_init_clksel_parent, 1964 .init = &omap2_init_clksel_parent,
@@ -1955,9 +1988,9 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = {
1955 { .parent = NULL }, 1988 { .parent = NULL },
1956}; 1989};
1957 1990
1958/* Merged per_mcbsp4_gfclk into mcbsp4_ck */ 1991/* Merged per_mcbsp4_gfclk into mcbsp4 */
1959static struct clk mcbsp4_ck = { 1992static struct clk mcbsp4_fck = {
1960 .name = "mcbsp4_ck", 1993 .name = "mcbsp4_fck",
1961 .parent = &mcbsp4_sync_mux_ck, 1994 .parent = &mcbsp4_sync_mux_ck,
1962 .clksel = per_mcbsp4_gfclk_sel, 1995 .clksel = per_mcbsp4_gfclk_sel,
1963 .init = &omap2_init_clksel_parent, 1996 .init = &omap2_init_clksel_parent,
@@ -1970,8 +2003,8 @@ static struct clk mcbsp4_ck = {
1970 .clkdm_name = "l4_per_clkdm", 2003 .clkdm_name = "l4_per_clkdm",
1971}; 2004};
1972 2005
1973static struct clk mcspi1_ck = { 2006static struct clk mcspi1_fck = {
1974 .name = "mcspi1_ck", 2007 .name = "mcspi1_fck",
1975 .ops = &clkops_omap2_dflt, 2008 .ops = &clkops_omap2_dflt,
1976 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, 2009 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1977 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2010 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1980,8 +2013,8 @@ static struct clk mcspi1_ck = {
1980 .recalc = &followparent_recalc, 2013 .recalc = &followparent_recalc,
1981}; 2014};
1982 2015
1983static struct clk mcspi2_ck = { 2016static struct clk mcspi2_fck = {
1984 .name = "mcspi2_ck", 2017 .name = "mcspi2_fck",
1985 .ops = &clkops_omap2_dflt, 2018 .ops = &clkops_omap2_dflt,
1986 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, 2019 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1987 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2020 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1990,8 +2023,8 @@ static struct clk mcspi2_ck = {
1990 .recalc = &followparent_recalc, 2023 .recalc = &followparent_recalc,
1991}; 2024};
1992 2025
1993static struct clk mcspi3_ck = { 2026static struct clk mcspi3_fck = {
1994 .name = "mcspi3_ck", 2027 .name = "mcspi3_fck",
1995 .ops = &clkops_omap2_dflt, 2028 .ops = &clkops_omap2_dflt,
1996 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, 2029 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1997 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2030 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2000,8 +2033,8 @@ static struct clk mcspi3_ck = {
2000 .recalc = &followparent_recalc, 2033 .recalc = &followparent_recalc,
2001}; 2034};
2002 2035
2003static struct clk mcspi4_ck = { 2036static struct clk mcspi4_fck = {
2004 .name = "mcspi4_ck", 2037 .name = "mcspi4_fck",
2005 .ops = &clkops_omap2_dflt, 2038 .ops = &clkops_omap2_dflt,
2006 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, 2039 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2007 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2040 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2010,9 +2043,9 @@ static struct clk mcspi4_ck = {
2010 .recalc = &followparent_recalc, 2043 .recalc = &followparent_recalc,
2011}; 2044};
2012 2045
2013/* Merged hsmmc1_fclk into mmc1_ck */ 2046/* Merged hsmmc1_fclk into mmc1 */
2014static struct clk mmc1_ck = { 2047static struct clk mmc1_fck = {
2015 .name = "mmc1_ck", 2048 .name = "mmc1_fck",
2016 .parent = &func_64m_fclk, 2049 .parent = &func_64m_fclk,
2017 .clksel = hsmmc6_fclk_sel, 2050 .clksel = hsmmc6_fclk_sel,
2018 .init = &omap2_init_clksel_parent, 2051 .init = &omap2_init_clksel_parent,
@@ -2025,9 +2058,9 @@ static struct clk mmc1_ck = {
2025 .clkdm_name = "l3_init_clkdm", 2058 .clkdm_name = "l3_init_clkdm",
2026}; 2059};
2027 2060
2028/* Merged hsmmc2_fclk into mmc2_ck */ 2061/* Merged hsmmc2_fclk into mmc2 */
2029static struct clk mmc2_ck = { 2062static struct clk mmc2_fck = {
2030 .name = "mmc2_ck", 2063 .name = "mmc2_fck",
2031 .parent = &func_64m_fclk, 2064 .parent = &func_64m_fclk,
2032 .clksel = hsmmc6_fclk_sel, 2065 .clksel = hsmmc6_fclk_sel,
2033 .init = &omap2_init_clksel_parent, 2066 .init = &omap2_init_clksel_parent,
@@ -2040,8 +2073,8 @@ static struct clk mmc2_ck = {
2040 .clkdm_name = "l3_init_clkdm", 2073 .clkdm_name = "l3_init_clkdm",
2041}; 2074};
2042 2075
2043static struct clk mmc3_ck = { 2076static struct clk mmc3_fck = {
2044 .name = "mmc3_ck", 2077 .name = "mmc3_fck",
2045 .ops = &clkops_omap2_dflt, 2078 .ops = &clkops_omap2_dflt,
2046 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, 2079 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2047 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2080 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2050,8 +2083,8 @@ static struct clk mmc3_ck = {
2050 .recalc = &followparent_recalc, 2083 .recalc = &followparent_recalc,
2051}; 2084};
2052 2085
2053static struct clk mmc4_ck = { 2086static struct clk mmc4_fck = {
2054 .name = "mmc4_ck", 2087 .name = "mmc4_fck",
2055 .ops = &clkops_omap2_dflt, 2088 .ops = &clkops_omap2_dflt,
2056 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, 2089 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2057 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2090 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2060,8 +2093,8 @@ static struct clk mmc4_ck = {
2060 .recalc = &followparent_recalc, 2093 .recalc = &followparent_recalc,
2061}; 2094};
2062 2095
2063static struct clk mmc5_ck = { 2096static struct clk mmc5_fck = {
2064 .name = "mmc5_ck", 2097 .name = "mmc5_fck",
2065 .ops = &clkops_omap2_dflt, 2098 .ops = &clkops_omap2_dflt,
2066 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, 2099 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2067 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2100 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2070,8 +2103,8 @@ static struct clk mmc5_ck = {
2070 .recalc = &followparent_recalc, 2103 .recalc = &followparent_recalc,
2071}; 2104};
2072 2105
2073static struct clk ocp_wp1_ck = { 2106static struct clk ocp_wp1_ick = {
2074 .name = "ocp_wp1_ck", 2107 .name = "ocp_wp1_ick",
2075 .ops = &clkops_omap2_dflt, 2108 .ops = &clkops_omap2_dflt,
2076 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2109 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2077 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2110 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2080,8 +2113,8 @@ static struct clk ocp_wp1_ck = {
2080 .recalc = &followparent_recalc, 2113 .recalc = &followparent_recalc,
2081}; 2114};
2082 2115
2083static struct clk pdm_ck = { 2116static struct clk pdm_fck = {
2084 .name = "pdm_ck", 2117 .name = "pdm_fck",
2085 .ops = &clkops_omap2_dflt, 2118 .ops = &clkops_omap2_dflt,
2086 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 2119 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2087 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2120 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2090,8 +2123,8 @@ static struct clk pdm_ck = {
2090 .recalc = &followparent_recalc, 2123 .recalc = &followparent_recalc,
2091}; 2124};
2092 2125
2093static struct clk pkaeip29_ck = { 2126static struct clk pkaeip29_fck = {
2094 .name = "pkaeip29_ck", 2127 .name = "pkaeip29_fck",
2095 .ops = &clkops_omap2_dflt, 2128 .ops = &clkops_omap2_dflt,
2096 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, 2129 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2097 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2130 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2100,8 +2133,8 @@ static struct clk pkaeip29_ck = {
2100 .recalc = &followparent_recalc, 2133 .recalc = &followparent_recalc,
2101}; 2134};
2102 2135
2103static struct clk rng_ck = { 2136static struct clk rng_ick = {
2104 .name = "rng_ck", 2137 .name = "rng_ick",
2105 .ops = &clkops_omap2_dflt, 2138 .ops = &clkops_omap2_dflt,
2106 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, 2139 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2107 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2140 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2110,8 +2143,8 @@ static struct clk rng_ck = {
2110 .recalc = &followparent_recalc, 2143 .recalc = &followparent_recalc,
2111}; 2144};
2112 2145
2113static struct clk sha2md51_ck = { 2146static struct clk sha2md51_fck = {
2114 .name = "sha2md51_ck", 2147 .name = "sha2md51_fck",
2115 .ops = &clkops_omap2_dflt, 2148 .ops = &clkops_omap2_dflt,
2116 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 2149 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2117 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2150 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2120,8 +2153,8 @@ static struct clk sha2md51_ck = {
2120 .recalc = &followparent_recalc, 2153 .recalc = &followparent_recalc,
2121}; 2154};
2122 2155
2123static struct clk sl2_ck = { 2156static struct clk sl2_ick = {
2124 .name = "sl2_ck", 2157 .name = "sl2_ick",
2125 .ops = &clkops_omap2_dflt, 2158 .ops = &clkops_omap2_dflt,
2126 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 2159 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2127 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2160 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2130,8 +2163,8 @@ static struct clk sl2_ck = {
2130 .recalc = &followparent_recalc, 2163 .recalc = &followparent_recalc,
2131}; 2164};
2132 2165
2133static struct clk slimbus1_ck = { 2166static struct clk slimbus1_fck = {
2134 .name = "slimbus1_ck", 2167 .name = "slimbus1_fck",
2135 .ops = &clkops_omap2_dflt, 2168 .ops = &clkops_omap2_dflt,
2136 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 2169 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2137 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2170 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2140,8 +2173,8 @@ static struct clk slimbus1_ck = {
2140 .recalc = &followparent_recalc, 2173 .recalc = &followparent_recalc,
2141}; 2174};
2142 2175
2143static struct clk slimbus2_ck = { 2176static struct clk slimbus2_fck = {
2144 .name = "slimbus2_ck", 2177 .name = "slimbus2_fck",
2145 .ops = &clkops_omap2_dflt, 2178 .ops = &clkops_omap2_dflt,
2146 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 2179 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2147 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2180 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2150,8 +2183,8 @@ static struct clk slimbus2_ck = {
2150 .recalc = &followparent_recalc, 2183 .recalc = &followparent_recalc,
2151}; 2184};
2152 2185
2153static struct clk sr_core_ck = { 2186static struct clk sr_core_fck = {
2154 .name = "sr_core_ck", 2187 .name = "sr_core_fck",
2155 .ops = &clkops_omap2_dflt, 2188 .ops = &clkops_omap2_dflt,
2156 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 2189 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2157 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2190 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2160,8 +2193,8 @@ static struct clk sr_core_ck = {
2160 .recalc = &followparent_recalc, 2193 .recalc = &followparent_recalc,
2161}; 2194};
2162 2195
2163static struct clk sr_iva_ck = { 2196static struct clk sr_iva_fck = {
2164 .name = "sr_iva_ck", 2197 .name = "sr_iva_fck",
2165 .ops = &clkops_omap2_dflt, 2198 .ops = &clkops_omap2_dflt,
2166 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 2199 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2167 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2200 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2170,8 +2203,8 @@ static struct clk sr_iva_ck = {
2170 .recalc = &followparent_recalc, 2203 .recalc = &followparent_recalc,
2171}; 2204};
2172 2205
2173static struct clk sr_mpu_ck = { 2206static struct clk sr_mpu_fck = {
2174 .name = "sr_mpu_ck", 2207 .name = "sr_mpu_fck",
2175 .ops = &clkops_omap2_dflt, 2208 .ops = &clkops_omap2_dflt,
2176 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 2209 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2177 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2210 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2180,8 +2213,8 @@ static struct clk sr_mpu_ck = {
2180 .recalc = &followparent_recalc, 2213 .recalc = &followparent_recalc,
2181}; 2214};
2182 2215
2183static struct clk tesla_ck = { 2216static struct clk tesla_ick = {
2184 .name = "tesla_ck", 2217 .name = "tesla_ick",
2185 .ops = &clkops_omap2_dflt, 2218 .ops = &clkops_omap2_dflt,
2186 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 2219 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
2187 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2220 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2190,8 +2223,8 @@ static struct clk tesla_ck = {
2190 .recalc = &followparent_recalc, 2223 .recalc = &followparent_recalc,
2191}; 2224};
2192 2225
2193static struct clk uart1_ck = { 2226static struct clk uart1_fck = {
2194 .name = "uart1_ck", 2227 .name = "uart1_fck",
2195 .ops = &clkops_omap2_dflt, 2228 .ops = &clkops_omap2_dflt,
2196 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, 2229 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2197 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2230 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2200,8 +2233,8 @@ static struct clk uart1_ck = {
2200 .recalc = &followparent_recalc, 2233 .recalc = &followparent_recalc,
2201}; 2234};
2202 2235
2203static struct clk uart2_ck = { 2236static struct clk uart2_fck = {
2204 .name = "uart2_ck", 2237 .name = "uart2_fck",
2205 .ops = &clkops_omap2_dflt, 2238 .ops = &clkops_omap2_dflt,
2206 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, 2239 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2207 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2240 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2210,8 +2243,8 @@ static struct clk uart2_ck = {
2210 .recalc = &followparent_recalc, 2243 .recalc = &followparent_recalc,
2211}; 2244};
2212 2245
2213static struct clk uart3_ck = { 2246static struct clk uart3_fck = {
2214 .name = "uart3_ck", 2247 .name = "uart3_fck",
2215 .ops = &clkops_omap2_dflt, 2248 .ops = &clkops_omap2_dflt,
2216 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, 2249 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2217 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2250 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2220,8 +2253,8 @@ static struct clk uart3_ck = {
2220 .recalc = &followparent_recalc, 2253 .recalc = &followparent_recalc,
2221}; 2254};
2222 2255
2223static struct clk uart4_ck = { 2256static struct clk uart4_fck = {
2224 .name = "uart4_ck", 2257 .name = "uart4_fck",
2225 .ops = &clkops_omap2_dflt, 2258 .ops = &clkops_omap2_dflt,
2226 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, 2259 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2227 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2260 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2230,8 +2263,8 @@ static struct clk uart4_ck = {
2230 .recalc = &followparent_recalc, 2263 .recalc = &followparent_recalc,
2231}; 2264};
2232 2265
2233static struct clk unipro1_ck = { 2266static struct clk unipro1_fck = {
2234 .name = "unipro1_ck", 2267 .name = "unipro1_fck",
2235 .ops = &clkops_omap2_dflt, 2268 .ops = &clkops_omap2_dflt,
2236 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, 2269 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
2237 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2270 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2240,8 +2273,8 @@ static struct clk unipro1_ck = {
2240 .recalc = &followparent_recalc, 2273 .recalc = &followparent_recalc,
2241}; 2274};
2242 2275
2243static struct clk usb_host_ck = { 2276static struct clk usb_host_fck = {
2244 .name = "usb_host_ck", 2277 .name = "usb_host_fck",
2245 .ops = &clkops_omap2_dflt, 2278 .ops = &clkops_omap2_dflt,
2246 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2279 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2247 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2280 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2250,8 +2283,8 @@ static struct clk usb_host_ck = {
2250 .recalc = &followparent_recalc, 2283 .recalc = &followparent_recalc,
2251}; 2284};
2252 2285
2253static struct clk usb_host_fs_ck = { 2286static struct clk usb_host_fs_fck = {
2254 .name = "usb_host_fs_ck", 2287 .name = "usb_host_fs_fck",
2255 .ops = &clkops_omap2_dflt, 2288 .ops = &clkops_omap2_dflt,
2256 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, 2289 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2257 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2290 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2260,8 +2293,8 @@ static struct clk usb_host_fs_ck = {
2260 .recalc = &followparent_recalc, 2293 .recalc = &followparent_recalc,
2261}; 2294};
2262 2295
2263static struct clk usb_otg_ck = { 2296static struct clk usb_otg_ick = {
2264 .name = "usb_otg_ck", 2297 .name = "usb_otg_ick",
2265 .ops = &clkops_omap2_dflt, 2298 .ops = &clkops_omap2_dflt,
2266 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2299 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2267 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2300 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2270,8 +2303,8 @@ static struct clk usb_otg_ck = {
2270 .recalc = &followparent_recalc, 2303 .recalc = &followparent_recalc,
2271}; 2304};
2272 2305
2273static struct clk usb_tll_ck = { 2306static struct clk usb_tll_ick = {
2274 .name = "usb_tll_ck", 2307 .name = "usb_tll_ick",
2275 .ops = &clkops_omap2_dflt, 2308 .ops = &clkops_omap2_dflt,
2276 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2309 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2277 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2310 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2280,8 +2313,8 @@ static struct clk usb_tll_ck = {
2280 .recalc = &followparent_recalc, 2313 .recalc = &followparent_recalc,
2281}; 2314};
2282 2315
2283static struct clk usbphyocp2scp_ck = { 2316static struct clk usbphyocp2scp_ick = {
2284 .name = "usbphyocp2scp_ck", 2317 .name = "usbphyocp2scp_ick",
2285 .ops = &clkops_omap2_dflt, 2318 .ops = &clkops_omap2_dflt,
2286 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, 2319 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2287 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2320 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2290,8 +2323,8 @@ static struct clk usbphyocp2scp_ck = {
2290 .recalc = &followparent_recalc, 2323 .recalc = &followparent_recalc,
2291}; 2324};
2292 2325
2293static struct clk usim_ck = { 2326static struct clk usim_fck = {
2294 .name = "usim_ck", 2327 .name = "usim_fck",
2295 .ops = &clkops_omap2_dflt, 2328 .ops = &clkops_omap2_dflt,
2296 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2329 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2297 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2330 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2300,8 +2333,8 @@ static struct clk usim_ck = {
2300 .recalc = &followparent_recalc, 2333 .recalc = &followparent_recalc,
2301}; 2334};
2302 2335
2303static struct clk wdt2_ck = { 2336static struct clk wdt2_fck = {
2304 .name = "wdt2_ck", 2337 .name = "wdt2_fck",
2305 .ops = &clkops_omap2_dflt, 2338 .ops = &clkops_omap2_dflt,
2306 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 2339 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2307 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2340 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2310,8 +2343,8 @@ static struct clk wdt2_ck = {
2310 .recalc = &followparent_recalc, 2343 .recalc = &followparent_recalc,
2311}; 2344};
2312 2345
2313static struct clk wdt3_ck = { 2346static struct clk wdt3_fck = {
2314 .name = "wdt3_ck", 2347 .name = "wdt3_fck",
2315 .ops = &clkops_omap2_dflt, 2348 .ops = &clkops_omap2_dflt,
2316 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 2349 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2317 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2350 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2519,93 +2552,93 @@ static struct omap_clk omap44xx_clks[] = {
2519 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 2552 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
2520 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 2553 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
2521 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 2554 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
2522 CLK(NULL, "aes1_ck", &aes1_ck, CK_443X), 2555 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2523 CLK(NULL, "aes2_ck", &aes2_ck, CK_443X), 2556 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2524 CLK(NULL, "aess_ck", &aess_ck, CK_443X), 2557 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2525 CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X), 2558 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X),
2526 CLK(NULL, "des3des_ck", &des3des_ck, CK_443X), 2559 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2527 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 2560 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2528 CLK(NULL, "dmic_ck", &dmic_ck, CK_443X), 2561 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2529 CLK(NULL, "dss_ck", &dss_ck, CK_443X), 2562 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2530 CLK(NULL, "ducati_ck", &ducati_ck, CK_443X), 2563 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X),
2531 CLK(NULL, "emif1_ck", &emif1_ck, CK_443X), 2564 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X),
2532 CLK(NULL, "emif2_ck", &emif2_ck, CK_443X), 2565 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X),
2533 CLK(NULL, "fdif_ck", &fdif_ck, CK_443X), 2566 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2534 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), 2567 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
2535 CLK(NULL, "gfx_ck", &gfx_ck, CK_443X), 2568 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X),
2536 CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X), 2569 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2537 CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X), 2570 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2538 CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X), 2571 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2539 CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X), 2572 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2540 CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X), 2573 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2541 CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X), 2574 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2542 CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X), 2575 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2543 CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X), 2576 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X),
2544 CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X), 2577 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2545 CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X), 2578 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2546 CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X), 2579 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2547 CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X), 2580 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2548 CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X), 2581 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2549 CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X), 2582 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2550 CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X), 2583 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2551 CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X), 2584 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2552 CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X), 2585 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2553 CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X), 2586 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2554 CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X), 2587 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2555 CLK(NULL, "hsi_ck", &hsi_ck, CK_443X), 2588 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X),
2556 CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X), 2589 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2557 CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X), 2590 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2558 CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X), 2591 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2559 CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X), 2592 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2560 CLK(NULL, "iss_ck", &iss_ck, CK_443X), 2593 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2561 CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X), 2594 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X),
2562 CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X), 2595 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X),
2563 CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X), 2596 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X),
2564 CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X), 2597 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X),
2565 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 2598 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2566 CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X), 2599 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2567 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 2600 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
2568 CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X), 2601 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
2569 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 2602 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
2570 CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X), 2603 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
2571 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 2604 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
2572 CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X), 2605 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2573 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 2606 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2574 CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X), 2607 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
2575 CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X), 2608 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2576 CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X), 2609 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2577 CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X), 2610 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
2578 CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X), 2611 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
2579 CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X), 2612 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
2580 CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X), 2613 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
2581 CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X), 2614 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2582 CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X), 2615 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2583 CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X), 2616 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2584 CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X), 2617 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X),
2585 CLK(NULL, "pdm_ck", &pdm_ck, CK_443X), 2618 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X),
2586 CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X), 2619 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X),
2587 CLK("omap_rng", "ick", &rng_ck, CK_443X), 2620 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2588 CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X), 2621 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X),
2589 CLK(NULL, "sl2_ck", &sl2_ck, CK_443X), 2622 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X),
2590 CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X), 2623 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2591 CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X), 2624 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2592 CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X), 2625 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X),
2593 CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X), 2626 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X),
2594 CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X), 2627 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X),
2595 CLK(NULL, "tesla_ck", &tesla_ck, CK_443X), 2628 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X),
2596 CLK(NULL, "uart1_ck", &uart1_ck, CK_443X), 2629 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2597 CLK(NULL, "uart2_ck", &uart2_ck, CK_443X), 2630 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2598 CLK(NULL, "uart3_ck", &uart3_ck, CK_443X), 2631 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2599 CLK(NULL, "uart4_ck", &uart4_ck, CK_443X), 2632 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2600 CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X), 2633 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2601 CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X), 2634 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2602 CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X), 2635 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2603 CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X), 2636 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X),
2604 CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X), 2637 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X),
2605 CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X), 2638 CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X),
2606 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 2639 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2607 CLK("omap_wdt", "fck", &wdt2_ck, CK_443X), 2640 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X),
2608 CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X), 2641 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X),
2609 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), 2642 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2610 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 2643 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2611 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 2644 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 12:30:38 -0400