diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-02 13:34:25 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-02 13:34:25 -0500 |
| commit | 5057bfaff82e12f01a2ffd58f55535cbd7c5c3a2 (patch) | |
| tree | 0397253173308317480ed82f0b75af46cd3f6cb1 /arch | |
| parent | 6c0ad5dfd3d5ad6def89b485ee52834547da239b (diff) | |
| parent | d702d12167a2c05a346f49aac7a311d597762495 (diff) | |
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (214 commits)
omap2: Initialize Menelaus and MMC for N8X0
AM3517 EVM: correct typo - tca6416 mispelt as tca6516
AM3517 EVM: Enable I2C support
AM35x: Enable OMAP_MUX in defconfig
AM35x: Add missing GPIO mux config for EHCI port
Zoom3: Defconfig update
omap: i2c: Fix muxing for command line enabled bus
OMAP4: clock: Remove clock hacks from timer-gp.c
OMAP4: clock: Add dummy clock nodes for interface clocks
OMAP4: clock: Rename leaf clock nodes to end with a _ick or _fck
OMAP2+ clock: revise omap2_clk_{disable,enable}()
OMAP2/3 clock: combine OMAP2 & 3 boot-time MPU rate change code
OMAP clockdomain: if no autodeps exist, don't try to add or remove them
OMAP hwmod: add hwmod class support
OMAP hwmod: convert header files with static allocations into C files
OMAP hwmod: convert hwmod to use hardware clock names rather than clkdev dev+con
OMAP clock: add omap_clk_get_by_name() for use by OMAP hwmod core code
OMAP3: clock: add capability to change rate of dpll4_m5_ck_3630
OMAP4 clock: drop the ALWAYS_ENABLED clock flag
OMAP clock: drop RATE_FIXED clock flag
...
Diffstat (limited to 'arch')
185 files changed, 18904 insertions, 7755 deletions
diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig index abe9966781ce..66a10b50d938 100644 --- a/arch/arm/configs/am3517_evm_defconfig +++ b/arch/arm/configs/am3517_evm_defconfig | |||
| @@ -201,7 +201,7 @@ CONFIG_ARCH_OMAP3=y | |||
| 201 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | 201 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set |
| 202 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | 202 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set |
| 203 | CONFIG_OMAP_RESET_CLOCKS=y | 203 | CONFIG_OMAP_RESET_CLOCKS=y |
| 204 | # CONFIG_OMAP_MUX is not set | 204 | CONFIG_OMAP_MUX=y |
| 205 | # CONFIG_OMAP_MCBSP is not set | 205 | # CONFIG_OMAP_MCBSP is not set |
| 206 | # CONFIG_OMAP_MBOX_FWK is not set | 206 | # CONFIG_OMAP_MBOX_FWK is not set |
| 207 | # CONFIG_OMAP_MPU_TIMER is not set | 207 | # CONFIG_OMAP_MPU_TIMER is not set |
| @@ -590,7 +590,46 @@ CONFIG_HW_RANDOM=y | |||
| 590 | # CONFIG_R3964 is not set | 590 | # CONFIG_R3964 is not set |
| 591 | # CONFIG_RAW_DRIVER is not set | 591 | # CONFIG_RAW_DRIVER is not set |
| 592 | # CONFIG_TCG_TPM is not set | 592 | # CONFIG_TCG_TPM is not set |
| 593 | # CONFIG_I2C is not set | 593 | CONFIG_I2C=y |
| 594 | CONFIG_I2C_BOARDINFO=y | ||
| 595 | CONFIG_I2C_COMPAT=y | ||
| 596 | CONFIG_I2C_CHARDEV=y | ||
| 597 | CONFIG_I2C_HELPER_AUTO=y | ||
| 598 | |||
| 599 | # | ||
| 600 | # I2C Hardware Bus support | ||
| 601 | # | ||
| 602 | |||
| 603 | # | ||
| 604 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 605 | # | ||
| 606 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 607 | # CONFIG_I2C_GPIO is not set | ||
| 608 | # CONFIG_I2C_OCORES is not set | ||
| 609 | CONFIG_I2C_OMAP=y | ||
| 610 | # CONFIG_I2C_SIMTEC is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # External I2C/SMBus adapter drivers | ||
| 614 | # | ||
| 615 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 616 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 617 | # CONFIG_I2C_TINY_USB is not set | ||
| 618 | |||
| 619 | # | ||
| 620 | # Other I2C/SMBus bus drivers | ||
| 621 | # | ||
| 622 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 623 | # CONFIG_I2C_STUB is not set | ||
| 624 | |||
| 625 | # | ||
| 626 | # Miscellaneous I2C Chip support | ||
| 627 | # | ||
| 628 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 629 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 630 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 631 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 632 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 594 | # CONFIG_SPI is not set | 633 | # CONFIG_SPI is not set |
| 595 | 634 | ||
| 596 | # | 635 | # |
diff --git a/arch/arm/configs/devkit8000_defconfig b/arch/arm/configs/devkit8000_defconfig new file mode 100644 index 000000000000..61a817e8cf81 --- /dev/null +++ b/arch/arm/configs/devkit8000_defconfig | |||
| @@ -0,0 +1,1889 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.33-rc6 | ||
| 4 | # Thu Feb 4 15:42:56 2010 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_GENERIC_HARDIRQS=y | ||
| 12 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 14 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 16 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 17 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 19 | CONFIG_ARCH_HAS_CPUFREQ=y | ||
| 20 | CONFIG_GENERIC_HWEIGHT=y | ||
| 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 23 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 24 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 25 | CONFIG_CONSTRUCTORS=y | ||
| 26 | |||
| 27 | # | ||
| 28 | # General setup | ||
| 29 | # | ||
| 30 | CONFIG_EXPERIMENTAL=y | ||
| 31 | CONFIG_BROKEN_ON_SMP=y | ||
| 32 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 33 | CONFIG_LOCALVERSION="" | ||
| 34 | CONFIG_LOCALVERSION_AUTO=y | ||
| 35 | CONFIG_HAVE_KERNEL_GZIP=y | ||
| 36 | CONFIG_HAVE_KERNEL_LZO=y | ||
| 37 | CONFIG_KERNEL_GZIP=y | ||
| 38 | # CONFIG_KERNEL_BZIP2 is not set | ||
| 39 | # CONFIG_KERNEL_LZMA is not set | ||
| 40 | # CONFIG_KERNEL_LZO is not set | ||
| 41 | CONFIG_SWAP=y | ||
| 42 | CONFIG_SYSVIPC=y | ||
| 43 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 44 | # CONFIG_POSIX_MQUEUE is not set | ||
| 45 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 46 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
| 47 | # CONFIG_TASKSTATS is not set | ||
| 48 | # CONFIG_AUDIT is not set | ||
| 49 | |||
| 50 | # | ||
| 51 | # RCU Subsystem | ||
| 52 | # | ||
| 53 | CONFIG_TREE_RCU=y | ||
| 54 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
| 55 | # CONFIG_TINY_RCU is not set | ||
| 56 | # CONFIG_RCU_TRACE is not set | ||
| 57 | CONFIG_RCU_FANOUT=32 | ||
| 58 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 59 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 60 | CONFIG_IKCONFIG=y | ||
| 61 | CONFIG_IKCONFIG_PROC=y | ||
| 62 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 63 | CONFIG_GROUP_SCHED=y | ||
| 64 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 65 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 66 | CONFIG_USER_SCHED=y | ||
| 67 | # CONFIG_CGROUP_SCHED is not set | ||
| 68 | # CONFIG_CGROUPS is not set | ||
| 69 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 70 | # CONFIG_RELAY is not set | ||
| 71 | # CONFIG_NAMESPACES is not set | ||
| 72 | CONFIG_BLK_DEV_INITRD=y | ||
| 73 | CONFIG_INITRAMFS_SOURCE="" | ||
| 74 | CONFIG_RD_GZIP=y | ||
| 75 | CONFIG_RD_BZIP2=y | ||
| 76 | CONFIG_RD_LZMA=y | ||
| 77 | # CONFIG_RD_LZO is not set | ||
| 78 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 79 | CONFIG_SYSCTL=y | ||
| 80 | CONFIG_ANON_INODES=y | ||
| 81 | CONFIG_EMBEDDED=y | ||
| 82 | CONFIG_UID16=y | ||
| 83 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 84 | CONFIG_KALLSYMS=y | ||
| 85 | # CONFIG_KALLSYMS_ALL is not set | ||
| 86 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 87 | CONFIG_HOTPLUG=y | ||
| 88 | CONFIG_PRINTK=y | ||
| 89 | CONFIG_BUG=y | ||
| 90 | CONFIG_ELF_CORE=y | ||
| 91 | CONFIG_BASE_FULL=y | ||
| 92 | CONFIG_FUTEX=y | ||
| 93 | CONFIG_EPOLL=y | ||
| 94 | CONFIG_SIGNALFD=y | ||
| 95 | CONFIG_TIMERFD=y | ||
| 96 | CONFIG_EVENTFD=y | ||
| 97 | CONFIG_SHMEM=y | ||
| 98 | CONFIG_AIO=y | ||
| 99 | |||
| 100 | # | ||
| 101 | # Kernel Performance Events And Counters | ||
| 102 | # | ||
| 103 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 104 | CONFIG_COMPAT_BRK=y | ||
| 105 | CONFIG_SLAB=y | ||
| 106 | # CONFIG_SLUB is not set | ||
| 107 | # CONFIG_SLOB is not set | ||
| 108 | # CONFIG_PROFILING is not set | ||
| 109 | CONFIG_HAVE_OPROFILE=y | ||
| 110 | # CONFIG_KPROBES is not set | ||
| 111 | CONFIG_HAVE_KPROBES=y | ||
| 112 | CONFIG_HAVE_KRETPROBES=y | ||
| 113 | CONFIG_HAVE_CLK=y | ||
| 114 | |||
| 115 | # | ||
| 116 | # GCOV-based kernel profiling | ||
| 117 | # | ||
| 118 | # CONFIG_SLOW_WORK is not set | ||
| 119 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 120 | CONFIG_SLABINFO=y | ||
| 121 | CONFIG_RT_MUTEXES=y | ||
| 122 | CONFIG_BASE_SMALL=0 | ||
| 123 | CONFIG_MODULES=y | ||
| 124 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 125 | CONFIG_MODULE_UNLOAD=y | ||
| 126 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 127 | CONFIG_MODVERSIONS=y | ||
| 128 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 129 | CONFIG_BLOCK=y | ||
| 130 | CONFIG_LBDAF=y | ||
| 131 | # CONFIG_BLK_DEV_BSG is not set | ||
| 132 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 133 | |||
| 134 | # | ||
| 135 | # IO Schedulers | ||
| 136 | # | ||
| 137 | CONFIG_IOSCHED_NOOP=y | ||
| 138 | CONFIG_IOSCHED_DEADLINE=y | ||
| 139 | CONFIG_IOSCHED_CFQ=y | ||
| 140 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 141 | CONFIG_DEFAULT_CFQ=y | ||
| 142 | # CONFIG_DEFAULT_NOOP is not set | ||
| 143 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 144 | # CONFIG_INLINE_SPIN_TRYLOCK is not set | ||
| 145 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
| 146 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
| 147 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
| 148 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
| 149 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
| 150 | CONFIG_INLINE_SPIN_UNLOCK=y | ||
| 151 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
| 152 | CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | ||
| 153 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
| 154 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
| 155 | # CONFIG_INLINE_READ_LOCK is not set | ||
| 156 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
| 157 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
| 158 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
| 159 | CONFIG_INLINE_READ_UNLOCK=y | ||
| 160 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
| 161 | CONFIG_INLINE_READ_UNLOCK_IRQ=y | ||
| 162 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
| 163 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
| 164 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
| 165 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
| 166 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
| 167 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
| 168 | CONFIG_INLINE_WRITE_UNLOCK=y | ||
| 169 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
| 170 | CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | ||
| 171 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
| 172 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
| 173 | # CONFIG_FREEZER is not set | ||
| 174 | |||
| 175 | # | ||
| 176 | # System Type | ||
| 177 | # | ||
| 178 | CONFIG_MMU=y | ||
| 179 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 180 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 181 | # CONFIG_ARCH_REALVIEW is not set | ||
| 182 | # CONFIG_ARCH_VERSATILE is not set | ||
| 183 | # CONFIG_ARCH_AT91 is not set | ||
| 184 | # CONFIG_ARCH_CLPS711X is not set | ||
| 185 | # CONFIG_ARCH_GEMINI is not set | ||
| 186 | # CONFIG_ARCH_EBSA110 is not set | ||
| 187 | # CONFIG_ARCH_EP93XX is not set | ||
| 188 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 189 | # CONFIG_ARCH_MXC is not set | ||
| 190 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 191 | # CONFIG_ARCH_NETX is not set | ||
| 192 | # CONFIG_ARCH_H720X is not set | ||
| 193 | # CONFIG_ARCH_NOMADIK is not set | ||
| 194 | # CONFIG_ARCH_IOP13XX is not set | ||
| 195 | # CONFIG_ARCH_IOP32X is not set | ||
| 196 | # CONFIG_ARCH_IOP33X is not set | ||
| 197 | # CONFIG_ARCH_IXP23XX is not set | ||
| 198 | # CONFIG_ARCH_IXP2000 is not set | ||
| 199 | # CONFIG_ARCH_IXP4XX is not set | ||
| 200 | # CONFIG_ARCH_L7200 is not set | ||
| 201 | # CONFIG_ARCH_DOVE is not set | ||
| 202 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 203 | # CONFIG_ARCH_LOKI is not set | ||
| 204 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 205 | # CONFIG_ARCH_ORION5X is not set | ||
| 206 | # CONFIG_ARCH_MMP is not set | ||
| 207 | # CONFIG_ARCH_KS8695 is not set | ||
| 208 | # CONFIG_ARCH_NS9XXX is not set | ||
| 209 | # CONFIG_ARCH_W90X900 is not set | ||
| 210 | # CONFIG_ARCH_PNX4008 is not set | ||
| 211 | # CONFIG_ARCH_PXA is not set | ||
| 212 | # CONFIG_ARCH_MSM is not set | ||
| 213 | # CONFIG_ARCH_RPC is not set | ||
| 214 | # CONFIG_ARCH_SA1100 is not set | ||
| 215 | # CONFIG_ARCH_S3C2410 is not set | ||
| 216 | # CONFIG_ARCH_S3C64XX is not set | ||
| 217 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 218 | # CONFIG_ARCH_SHARK is not set | ||
| 219 | # CONFIG_ARCH_LH7A40X is not set | ||
| 220 | # CONFIG_ARCH_U300 is not set | ||
| 221 | # CONFIG_ARCH_DAVINCI is not set | ||
| 222 | CONFIG_ARCH_OMAP=y | ||
| 223 | # CONFIG_ARCH_BCMRING is not set | ||
| 224 | # CONFIG_ARCH_U8500 is not set | ||
| 225 | |||
| 226 | # | ||
| 227 | # TI OMAP Implementations | ||
| 228 | # | ||
| 229 | CONFIG_ARCH_OMAP_OTG=y | ||
| 230 | # CONFIG_ARCH_OMAP1 is not set | ||
| 231 | CONFIG_ARCH_OMAP2PLUS=y | ||
| 232 | # CONFIG_ARCH_OMAP2 is not set | ||
| 233 | CONFIG_ARCH_OMAP3=y | ||
| 234 | # CONFIG_ARCH_OMAP4 is not set | ||
| 235 | |||
| 236 | # | ||
| 237 | # OMAP Feature Selections | ||
| 238 | # | ||
| 239 | # CONFIG_OMAP_RESET_CLOCKS is not set | ||
| 240 | # CONFIG_OMAP_MUX is not set | ||
| 241 | CONFIG_OMAP_MCBSP=y | ||
| 242 | # CONFIG_OMAP_MBOX_FWK is not set | ||
| 243 | # CONFIG_OMAP_MPU_TIMER is not set | ||
| 244 | CONFIG_OMAP_32K_TIMER=y | ||
| 245 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
| 246 | CONFIG_OMAP_DM_TIMER=y | ||
| 247 | # CONFIG_OMAP_PM_NONE is not set | ||
| 248 | CONFIG_OMAP_PM_NOOP=y | ||
| 249 | CONFIG_ARCH_OMAP3430=y | ||
| 250 | |||
| 251 | # | ||
| 252 | # OMAP Board Type | ||
| 253 | # | ||
| 254 | # CONFIG_MACH_OMAP3_BEAGLE is not set | ||
| 255 | CONFIG_MACH_DEVKIT8000=y | ||
| 256 | # CONFIG_MACH_OMAP_LDP is not set | ||
| 257 | # CONFIG_MACH_OVERO is not set | ||
| 258 | # CONFIG_MACH_OMAP3EVM is not set | ||
| 259 | # CONFIG_MACH_OMAP3517EVM is not set | ||
| 260 | # CONFIG_MACH_OMAP3_PANDORA is not set | ||
| 261 | # CONFIG_MACH_OMAP3_TOUCHBOOK is not set | ||
| 262 | # CONFIG_MACH_OMAP_3430SDP is not set | ||
| 263 | # CONFIG_MACH_NOKIA_RX51 is not set | ||
| 264 | # CONFIG_MACH_OMAP_ZOOM2 is not set | ||
| 265 | # CONFIG_MACH_OMAP_ZOOM3 is not set | ||
| 266 | # CONFIG_MACH_CM_T35 is not set | ||
| 267 | # CONFIG_MACH_IGEP0020 is not set | ||
| 268 | # CONFIG_MACH_OMAP_3630SDP is not set | ||
| 269 | # CONFIG_OMAP3_EMU is not set | ||
| 270 | # CONFIG_OMAP3_SDRC_AC_TIMING is not set | ||
| 271 | |||
| 272 | # | ||
| 273 | # Processor Type | ||
| 274 | # | ||
| 275 | CONFIG_CPU_32v6K=y | ||
| 276 | CONFIG_CPU_V7=y | ||
| 277 | CONFIG_CPU_32v7=y | ||
| 278 | CONFIG_CPU_ABRT_EV7=y | ||
| 279 | CONFIG_CPU_PABRT_V7=y | ||
| 280 | CONFIG_CPU_CACHE_V7=y | ||
| 281 | CONFIG_CPU_CACHE_VIPT=y | ||
| 282 | CONFIG_CPU_COPY_V6=y | ||
| 283 | CONFIG_CPU_TLB_V7=y | ||
| 284 | CONFIG_CPU_HAS_ASID=y | ||
| 285 | CONFIG_CPU_CP15=y | ||
| 286 | CONFIG_CPU_CP15_MMU=y | ||
| 287 | |||
| 288 | # | ||
| 289 | # Processor Features | ||
| 290 | # | ||
| 291 | CONFIG_ARM_THUMB=y | ||
| 292 | # CONFIG_ARM_THUMBEE is not set | ||
| 293 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 294 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 295 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 296 | CONFIG_HAS_TLS_REG=y | ||
| 297 | CONFIG_ARM_L1_CACHE_SHIFT=6 | ||
| 298 | # CONFIG_ARM_ERRATA_430973 is not set | ||
| 299 | # CONFIG_ARM_ERRATA_458693 is not set | ||
| 300 | # CONFIG_ARM_ERRATA_460075 is not set | ||
| 301 | CONFIG_COMMON_CLKDEV=y | ||
| 302 | |||
| 303 | # | ||
| 304 | # Bus support | ||
| 305 | # | ||
| 306 | # CONFIG_PCI_SYSCALL is not set | ||
| 307 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 308 | # CONFIG_PCCARD is not set | ||
| 309 | |||
| 310 | # | ||
| 311 | # Kernel Features | ||
| 312 | # | ||
| 313 | CONFIG_TICK_ONESHOT=y | ||
| 314 | CONFIG_NO_HZ=y | ||
| 315 | CONFIG_HIGH_RES_TIMERS=y | ||
| 316 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 317 | CONFIG_VMSPLIT_3G=y | ||
| 318 | # CONFIG_VMSPLIT_2G is not set | ||
| 319 | # CONFIG_VMSPLIT_1G is not set | ||
| 320 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 321 | CONFIG_PREEMPT_NONE=y | ||
| 322 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 323 | # CONFIG_PREEMPT is not set | ||
| 324 | CONFIG_HZ=128 | ||
| 325 | # CONFIG_THUMB2_KERNEL is not set | ||
| 326 | CONFIG_AEABI=y | ||
| 327 | CONFIG_OABI_COMPAT=y | ||
| 328 | CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y | ||
| 329 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 330 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 331 | # CONFIG_HIGHMEM is not set | ||
| 332 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 333 | CONFIG_FLATMEM_MANUAL=y | ||
| 334 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 335 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 336 | CONFIG_FLATMEM=y | ||
| 337 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 338 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 339 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 340 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 341 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 342 | CONFIG_VIRT_TO_BUS=y | ||
| 343 | # CONFIG_KSM is not set | ||
| 344 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 345 | # CONFIG_LEDS is not set | ||
| 346 | CONFIG_ALIGNMENT_TRAP=y | ||
| 347 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 348 | |||
| 349 | # | ||
| 350 | # Boot options | ||
| 351 | # | ||
| 352 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 353 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 354 | CONFIG_CMDLINE="console=ttyS2,115200n8 root=/dev/nfs nfsroot=192.168.1.1:home/nfsroot/current,home/nfsroot/current ip=dhcp rw noinitrd root delay=3" | ||
| 355 | # CONFIG_XIP_KERNEL is not set | ||
| 356 | # CONFIG_KEXEC is not set | ||
| 357 | |||
| 358 | # | ||
| 359 | # CPU Power Management | ||
| 360 | # | ||
| 361 | # CONFIG_CPU_FREQ is not set | ||
| 362 | # CONFIG_CPU_IDLE is not set | ||
| 363 | |||
| 364 | # | ||
| 365 | # Floating point emulation | ||
| 366 | # | ||
| 367 | |||
| 368 | # | ||
| 369 | # At least one emulation must be selected | ||
| 370 | # | ||
| 371 | CONFIG_FPE_NWFPE=y | ||
| 372 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 373 | # CONFIG_FPE_FASTFPE is not set | ||
| 374 | CONFIG_VFP=y | ||
| 375 | CONFIG_VFPv3=y | ||
| 376 | CONFIG_NEON=y | ||
| 377 | |||
| 378 | # | ||
| 379 | # Userspace binary formats | ||
| 380 | # | ||
| 381 | CONFIG_BINFMT_ELF=y | ||
| 382 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 383 | CONFIG_HAVE_AOUT=y | ||
| 384 | # CONFIG_BINFMT_AOUT is not set | ||
| 385 | # CONFIG_BINFMT_MISC is not set | ||
| 386 | |||
| 387 | # | ||
| 388 | # Power management options | ||
| 389 | # | ||
| 390 | # CONFIG_PM is not set | ||
| 391 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 392 | CONFIG_NET=y | ||
| 393 | |||
| 394 | # | ||
| 395 | # Networking options | ||
| 396 | # | ||
| 397 | CONFIG_PACKET=y | ||
| 398 | # CONFIG_PACKET_MMAP is not set | ||
| 399 | CONFIG_UNIX=y | ||
| 400 | CONFIG_XFRM=y | ||
| 401 | # CONFIG_XFRM_USER is not set | ||
| 402 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 403 | # CONFIG_XFRM_MIGRATE is not set | ||
| 404 | # CONFIG_XFRM_STATISTICS is not set | ||
| 405 | CONFIG_NET_KEY=y | ||
| 406 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 407 | CONFIG_INET=y | ||
| 408 | CONFIG_IP_MULTICAST=y | ||
| 409 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 410 | CONFIG_IP_FIB_HASH=y | ||
| 411 | CONFIG_IP_PNP=y | ||
| 412 | CONFIG_IP_PNP_DHCP=y | ||
| 413 | CONFIG_IP_PNP_BOOTP=y | ||
| 414 | CONFIG_IP_PNP_RARP=y | ||
| 415 | # CONFIG_NET_IPIP is not set | ||
| 416 | # CONFIG_NET_IPGRE is not set | ||
| 417 | # CONFIG_IP_MROUTE is not set | ||
| 418 | # CONFIG_ARPD is not set | ||
| 419 | # CONFIG_SYN_COOKIES is not set | ||
| 420 | # CONFIG_INET_AH is not set | ||
| 421 | # CONFIG_INET_ESP is not set | ||
| 422 | # CONFIG_INET_IPCOMP is not set | ||
| 423 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 424 | # CONFIG_INET_TUNNEL is not set | ||
| 425 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 426 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 427 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 428 | # CONFIG_INET_LRO is not set | ||
| 429 | CONFIG_INET_DIAG=y | ||
| 430 | CONFIG_INET_TCP_DIAG=y | ||
| 431 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 432 | CONFIG_TCP_CONG_CUBIC=y | ||
| 433 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 434 | # CONFIG_TCP_MD5SIG is not set | ||
| 435 | # CONFIG_IPV6 is not set | ||
| 436 | # CONFIG_NETWORK_SECMARK is not set | ||
| 437 | # CONFIG_NETFILTER is not set | ||
| 438 | # CONFIG_IP_DCCP is not set | ||
| 439 | # CONFIG_IP_SCTP is not set | ||
| 440 | # CONFIG_RDS is not set | ||
| 441 | # CONFIG_TIPC is not set | ||
| 442 | # CONFIG_ATM is not set | ||
| 443 | # CONFIG_BRIDGE is not set | ||
| 444 | # CONFIG_NET_DSA is not set | ||
| 445 | # CONFIG_VLAN_8021Q is not set | ||
| 446 | # CONFIG_DECNET is not set | ||
| 447 | # CONFIG_LLC2 is not set | ||
| 448 | # CONFIG_IPX is not set | ||
| 449 | # CONFIG_ATALK is not set | ||
| 450 | # CONFIG_X25 is not set | ||
| 451 | # CONFIG_LAPB is not set | ||
| 452 | # CONFIG_ECONET is not set | ||
| 453 | # CONFIG_WAN_ROUTER is not set | ||
| 454 | # CONFIG_PHONET is not set | ||
| 455 | # CONFIG_IEEE802154 is not set | ||
| 456 | # CONFIG_NET_SCHED is not set | ||
| 457 | # CONFIG_DCB is not set | ||
| 458 | |||
| 459 | # | ||
| 460 | # Network testing | ||
| 461 | # | ||
| 462 | # CONFIG_NET_PKTGEN is not set | ||
| 463 | # CONFIG_HAMRADIO is not set | ||
| 464 | # CONFIG_CAN is not set | ||
| 465 | CONFIG_IRDA=y | ||
| 466 | |||
| 467 | # | ||
| 468 | # IrDA protocols | ||
| 469 | # | ||
| 470 | # CONFIG_IRLAN is not set | ||
| 471 | # CONFIG_IRCOMM is not set | ||
| 472 | # CONFIG_IRDA_ULTRA is not set | ||
| 473 | |||
| 474 | # | ||
| 475 | # IrDA options | ||
| 476 | # | ||
| 477 | # CONFIG_IRDA_CACHE_LAST_LSAP is not set | ||
| 478 | # CONFIG_IRDA_FAST_RR is not set | ||
| 479 | # CONFIG_IRDA_DEBUG is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Infrared-port device drivers | ||
| 483 | # | ||
| 484 | |||
| 485 | # | ||
| 486 | # SIR device drivers | ||
| 487 | # | ||
| 488 | # CONFIG_IRTTY_SIR is not set | ||
| 489 | |||
| 490 | # | ||
| 491 | # Dongle support | ||
| 492 | # | ||
| 493 | # CONFIG_KINGSUN_DONGLE is not set | ||
| 494 | # CONFIG_KSDAZZLE_DONGLE is not set | ||
| 495 | # CONFIG_KS959_DONGLE is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # FIR device drivers | ||
| 499 | # | ||
| 500 | # CONFIG_USB_IRDA is not set | ||
| 501 | # CONFIG_SIGMATEL_FIR is not set | ||
| 502 | # CONFIG_MCS_FIR is not set | ||
| 503 | CONFIG_BT=y | ||
| 504 | # CONFIG_BT_L2CAP is not set | ||
| 505 | # CONFIG_BT_SCO is not set | ||
| 506 | |||
| 507 | # | ||
| 508 | # Bluetooth device drivers | ||
| 509 | # | ||
| 510 | # CONFIG_BT_HCIBTUSB is not set | ||
| 511 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 512 | # CONFIG_BT_HCIUART is not set | ||
| 513 | # CONFIG_BT_HCIBCM203X is not set | ||
| 514 | # CONFIG_BT_HCIBPA10X is not set | ||
| 515 | # CONFIG_BT_HCIBFUSB is not set | ||
| 516 | # CONFIG_BT_HCIVHCI is not set | ||
| 517 | # CONFIG_BT_MRVL is not set | ||
| 518 | # CONFIG_AF_RXRPC is not set | ||
| 519 | CONFIG_WIRELESS=y | ||
| 520 | # CONFIG_CFG80211 is not set | ||
| 521 | # CONFIG_LIB80211 is not set | ||
| 522 | |||
| 523 | # | ||
| 524 | # CFG80211 needs to be enabled for MAC80211 | ||
| 525 | # | ||
| 526 | # CONFIG_WIMAX is not set | ||
| 527 | # CONFIG_RFKILL is not set | ||
| 528 | # CONFIG_NET_9P is not set | ||
| 529 | |||
| 530 | # | ||
| 531 | # Device Drivers | ||
| 532 | # | ||
| 533 | |||
| 534 | # | ||
| 535 | # Generic Driver Options | ||
| 536 | # | ||
| 537 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 538 | # CONFIG_DEVTMPFS is not set | ||
| 539 | CONFIG_STANDALONE=y | ||
| 540 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 541 | # CONFIG_FW_LOADER is not set | ||
| 542 | # CONFIG_DEBUG_DRIVER is not set | ||
| 543 | # CONFIG_DEBUG_DEVRES is not set | ||
| 544 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 545 | # CONFIG_CONNECTOR is not set | ||
| 546 | CONFIG_MTD=y | ||
| 547 | # CONFIG_MTD_DEBUG is not set | ||
| 548 | # CONFIG_MTD_TESTS is not set | ||
| 549 | # CONFIG_MTD_CONCAT is not set | ||
| 550 | CONFIG_MTD_PARTITIONS=y | ||
| 551 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 552 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 553 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 554 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 555 | |||
| 556 | # | ||
| 557 | # User Modules And Translation Layers | ||
| 558 | # | ||
| 559 | CONFIG_MTD_CHAR=y | ||
| 560 | CONFIG_MTD_BLKDEVS=y | ||
| 561 | CONFIG_MTD_BLOCK=y | ||
| 562 | # CONFIG_FTL is not set | ||
| 563 | # CONFIG_NFTL is not set | ||
| 564 | # CONFIG_INFTL is not set | ||
| 565 | # CONFIG_RFD_FTL is not set | ||
| 566 | # CONFIG_SSFDC is not set | ||
| 567 | # CONFIG_MTD_OOPS is not set | ||
| 568 | |||
| 569 | # | ||
| 570 | # RAM/ROM/Flash chip drivers | ||
| 571 | # | ||
| 572 | # CONFIG_MTD_CFI is not set | ||
| 573 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 574 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 575 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 576 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 577 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 578 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 579 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 580 | CONFIG_MTD_CFI_I1=y | ||
| 581 | CONFIG_MTD_CFI_I2=y | ||
| 582 | # CONFIG_MTD_CFI_I4 is not set | ||
| 583 | # CONFIG_MTD_CFI_I8 is not set | ||
| 584 | CONFIG_MTD_RAM=y | ||
| 585 | CONFIG_MTD_ROM=y | ||
| 586 | # CONFIG_MTD_ABSENT is not set | ||
| 587 | |||
| 588 | # | ||
| 589 | # Mapping drivers for chip access | ||
| 590 | # | ||
| 591 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 592 | # CONFIG_MTD_PHYSMAP is not set | ||
| 593 | # CONFIG_MTD_PLATRAM is not set | ||
| 594 | |||
| 595 | # | ||
| 596 | # Self-contained MTD device drivers | ||
| 597 | # | ||
| 598 | # CONFIG_MTD_DATAFLASH is not set | ||
| 599 | # CONFIG_MTD_M25P80 is not set | ||
| 600 | # CONFIG_MTD_SST25L is not set | ||
| 601 | # CONFIG_MTD_SLRAM is not set | ||
| 602 | # CONFIG_MTD_PHRAM is not set | ||
| 603 | # CONFIG_MTD_MTDRAM is not set | ||
| 604 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 605 | |||
| 606 | # | ||
| 607 | # Disk-On-Chip Device Drivers | ||
| 608 | # | ||
| 609 | # CONFIG_MTD_DOC2000 is not set | ||
| 610 | # CONFIG_MTD_DOC2001 is not set | ||
| 611 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 612 | CONFIG_MTD_NAND=y | ||
| 613 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 614 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 615 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 616 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 617 | CONFIG_MTD_NAND_OMAP2=y | ||
| 618 | CONFIG_MTD_NAND_OMAP_PREFETCH=y | ||
| 619 | # CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set | ||
| 620 | CONFIG_MTD_NAND_IDS=y | ||
| 621 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 622 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 623 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 624 | # CONFIG_MTD_ALAUDA is not set | ||
| 625 | # CONFIG_MTD_ONENAND is not set | ||
| 626 | |||
| 627 | # | ||
| 628 | # LPDDR flash memory drivers | ||
| 629 | # | ||
| 630 | # CONFIG_MTD_LPDDR is not set | ||
| 631 | |||
| 632 | # | ||
| 633 | # UBI - Unsorted block images | ||
| 634 | # | ||
| 635 | CONFIG_MTD_UBI=y | ||
| 636 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 637 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 638 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
| 639 | |||
| 640 | # | ||
| 641 | # UBI debugging options | ||
| 642 | # | ||
| 643 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 644 | # CONFIG_PARPORT is not set | ||
| 645 | CONFIG_BLK_DEV=y | ||
| 646 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 647 | CONFIG_BLK_DEV_LOOP=y | ||
| 648 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 649 | |||
| 650 | # | ||
| 651 | # DRBD disabled because PROC_FS, INET or CONNECTOR not selected | ||
| 652 | # | ||
| 653 | # CONFIG_BLK_DEV_NBD is not set | ||
| 654 | # CONFIG_BLK_DEV_UB is not set | ||
| 655 | CONFIG_BLK_DEV_RAM=y | ||
| 656 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 657 | CONFIG_BLK_DEV_RAM_SIZE=40960 | ||
| 658 | # CONFIG_BLK_DEV_XIP is not set | ||
| 659 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 660 | # CONFIG_ATA_OVER_ETH is not set | ||
| 661 | # CONFIG_MG_DISK is not set | ||
| 662 | # CONFIG_MISC_DEVICES is not set | ||
| 663 | CONFIG_HAVE_IDE=y | ||
| 664 | # CONFIG_IDE is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # SCSI device support | ||
| 668 | # | ||
| 669 | # CONFIG_RAID_ATTRS is not set | ||
| 670 | CONFIG_SCSI=y | ||
| 671 | CONFIG_SCSI_DMA=y | ||
| 672 | # CONFIG_SCSI_TGT is not set | ||
| 673 | # CONFIG_SCSI_NETLINK is not set | ||
| 674 | CONFIG_SCSI_PROC_FS=y | ||
| 675 | |||
| 676 | # | ||
| 677 | # SCSI support type (disk, tape, CD-ROM) | ||
| 678 | # | ||
| 679 | CONFIG_BLK_DEV_SD=y | ||
| 680 | # CONFIG_CHR_DEV_ST is not set | ||
| 681 | # CONFIG_CHR_DEV_OSST is not set | ||
| 682 | # CONFIG_BLK_DEV_SR is not set | ||
| 683 | # CONFIG_CHR_DEV_SG is not set | ||
| 684 | # CONFIG_CHR_DEV_SCH is not set | ||
| 685 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 686 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 687 | # CONFIG_SCSI_LOGGING is not set | ||
| 688 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 689 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 690 | |||
| 691 | # | ||
| 692 | # SCSI Transports | ||
| 693 | # | ||
| 694 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 695 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 696 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 697 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 698 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 699 | CONFIG_SCSI_LOWLEVEL=y | ||
| 700 | # CONFIG_ISCSI_TCP is not set | ||
| 701 | # CONFIG_LIBFC is not set | ||
| 702 | # CONFIG_LIBFCOE is not set | ||
| 703 | # CONFIG_SCSI_DEBUG is not set | ||
| 704 | # CONFIG_SCSI_DH is not set | ||
| 705 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 706 | # CONFIG_ATA is not set | ||
| 707 | # CONFIG_MD is not set | ||
| 708 | CONFIG_NETDEVICES=y | ||
| 709 | # CONFIG_DUMMY is not set | ||
| 710 | # CONFIG_BONDING is not set | ||
| 711 | # CONFIG_MACVLAN is not set | ||
| 712 | # CONFIG_EQUALIZER is not set | ||
| 713 | # CONFIG_TUN is not set | ||
| 714 | # CONFIG_VETH is not set | ||
| 715 | # CONFIG_PHYLIB is not set | ||
| 716 | CONFIG_NET_ETHERNET=y | ||
| 717 | CONFIG_MII=y | ||
| 718 | # CONFIG_AX88796 is not set | ||
| 719 | # CONFIG_SMC91X is not set | ||
| 720 | CONFIG_DM9000=y | ||
| 721 | CONFIG_DM9000_DEBUGLEVEL=4 | ||
| 722 | CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y | ||
| 723 | # CONFIG_ENC28J60 is not set | ||
| 724 | # CONFIG_ETHOC is not set | ||
| 725 | # CONFIG_SMC911X is not set | ||
| 726 | # CONFIG_SMSC911X is not set | ||
| 727 | # CONFIG_DNET is not set | ||
| 728 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 729 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 730 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 731 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 732 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 733 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 734 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 735 | # CONFIG_B44 is not set | ||
| 736 | # CONFIG_KS8842 is not set | ||
| 737 | # CONFIG_KS8851 is not set | ||
| 738 | # CONFIG_KS8851_MLL is not set | ||
| 739 | # CONFIG_NETDEV_1000 is not set | ||
| 740 | # CONFIG_NETDEV_10000 is not set | ||
| 741 | # CONFIG_WLAN is not set | ||
| 742 | |||
| 743 | # | ||
| 744 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 745 | # | ||
| 746 | |||
| 747 | # | ||
| 748 | # USB Network Adapters | ||
| 749 | # | ||
| 750 | # CONFIG_USB_CATC is not set | ||
| 751 | # CONFIG_USB_KAWETH is not set | ||
| 752 | # CONFIG_USB_PEGASUS is not set | ||
| 753 | # CONFIG_USB_RTL8150 is not set | ||
| 754 | # CONFIG_USB_USBNET is not set | ||
| 755 | # CONFIG_WAN is not set | ||
| 756 | # CONFIG_PPP is not set | ||
| 757 | # CONFIG_SLIP is not set | ||
| 758 | # CONFIG_NETCONSOLE is not set | ||
| 759 | # CONFIG_NETPOLL is not set | ||
| 760 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 761 | # CONFIG_ISDN is not set | ||
| 762 | # CONFIG_PHONE is not set | ||
| 763 | |||
| 764 | # | ||
| 765 | # Input device support | ||
| 766 | # | ||
| 767 | CONFIG_INPUT=y | ||
| 768 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 769 | # CONFIG_INPUT_POLLDEV is not set | ||
| 770 | # CONFIG_INPUT_SPARSEKMAP is not set | ||
| 771 | |||
| 772 | # | ||
| 773 | # Userland interfaces | ||
| 774 | # | ||
| 775 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 776 | # CONFIG_INPUT_JOYDEV is not set | ||
| 777 | CONFIG_INPUT_EVDEV=y | ||
| 778 | # CONFIG_INPUT_EVBUG is not set | ||
| 779 | |||
| 780 | # | ||
| 781 | # Input Device Drivers | ||
| 782 | # | ||
| 783 | CONFIG_INPUT_KEYBOARD=y | ||
| 784 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 785 | CONFIG_KEYBOARD_ATKBD=y | ||
| 786 | # CONFIG_QT2160 is not set | ||
| 787 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 788 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 789 | CONFIG_KEYBOARD_MATRIX=y | ||
| 790 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 791 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 792 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 793 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
| 794 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 795 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 796 | CONFIG_KEYBOARD_TWL4030=y | ||
| 797 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 798 | # CONFIG_INPUT_MOUSE is not set | ||
| 799 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 800 | # CONFIG_INPUT_TABLET is not set | ||
| 801 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 802 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 803 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 804 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 805 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 806 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 807 | # CONFIG_TOUCHSCREEN_DYNAPRO is not set | ||
| 808 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
| 809 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 810 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 811 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 812 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 813 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
| 814 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 815 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 816 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 817 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 818 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 819 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 820 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 821 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 822 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 823 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 824 | # CONFIG_INPUT_MISC is not set | ||
| 825 | |||
| 826 | # | ||
| 827 | # Hardware I/O ports | ||
| 828 | # | ||
| 829 | CONFIG_SERIO=y | ||
| 830 | CONFIG_SERIO_SERPORT=y | ||
| 831 | CONFIG_SERIO_LIBPS2=y | ||
| 832 | CONFIG_SERIO_RAW=y | ||
| 833 | # CONFIG_SERIO_ALTERA_PS2 is not set | ||
| 834 | # CONFIG_GAMEPORT is not set | ||
| 835 | |||
| 836 | # | ||
| 837 | # Character devices | ||
| 838 | # | ||
| 839 | CONFIG_VT=y | ||
| 840 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 841 | CONFIG_VT_CONSOLE=y | ||
| 842 | CONFIG_HW_CONSOLE=y | ||
| 843 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 844 | CONFIG_DEVKMEM=y | ||
| 845 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 846 | |||
| 847 | # | ||
| 848 | # Serial drivers | ||
| 849 | # | ||
| 850 | CONFIG_SERIAL_8250=y | ||
| 851 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 852 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 853 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 854 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 855 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 856 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 857 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 858 | CONFIG_SERIAL_8250_RSA=y | ||
| 859 | |||
| 860 | # | ||
| 861 | # Non-8250 serial port support | ||
| 862 | # | ||
| 863 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 864 | CONFIG_SERIAL_CORE=y | ||
| 865 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 866 | CONFIG_UNIX98_PTYS=y | ||
| 867 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 868 | # CONFIG_LEGACY_PTYS is not set | ||
| 869 | # CONFIG_IPMI_HANDLER is not set | ||
| 870 | CONFIG_HW_RANDOM=y | ||
| 871 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
| 872 | # CONFIG_R3964 is not set | ||
| 873 | CONFIG_RAW_DRIVER=y | ||
| 874 | CONFIG_MAX_RAW_DEVS=256 | ||
| 875 | # CONFIG_TCG_TPM is not set | ||
| 876 | CONFIG_I2C=y | ||
| 877 | CONFIG_I2C_BOARDINFO=y | ||
| 878 | CONFIG_I2C_COMPAT=y | ||
| 879 | CONFIG_I2C_CHARDEV=y | ||
| 880 | CONFIG_I2C_HELPER_AUTO=y | ||
| 881 | |||
| 882 | # | ||
| 883 | # I2C Hardware Bus support | ||
| 884 | # | ||
| 885 | |||
| 886 | # | ||
| 887 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 888 | # | ||
| 889 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 890 | # CONFIG_I2C_GPIO is not set | ||
| 891 | # CONFIG_I2C_OCORES is not set | ||
| 892 | CONFIG_I2C_OMAP=y | ||
| 893 | # CONFIG_I2C_SIMTEC is not set | ||
| 894 | |||
| 895 | # | ||
| 896 | # External I2C/SMBus adapter drivers | ||
| 897 | # | ||
| 898 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 899 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 900 | # CONFIG_I2C_TINY_USB is not set | ||
| 901 | |||
| 902 | # | ||
| 903 | # Other I2C/SMBus bus drivers | ||
| 904 | # | ||
| 905 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 906 | # CONFIG_I2C_STUB is not set | ||
| 907 | |||
| 908 | # | ||
| 909 | # Miscellaneous I2C Chip support | ||
| 910 | # | ||
| 911 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 912 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 913 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 914 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 915 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 916 | CONFIG_SPI=y | ||
| 917 | # CONFIG_SPI_DEBUG is not set | ||
| 918 | CONFIG_SPI_MASTER=y | ||
| 919 | |||
| 920 | # | ||
| 921 | # SPI Master Controller Drivers | ||
| 922 | # | ||
| 923 | # CONFIG_SPI_BITBANG is not set | ||
| 924 | # CONFIG_SPI_GPIO is not set | ||
| 925 | CONFIG_SPI_OMAP24XX=y | ||
| 926 | # CONFIG_SPI_XILINX is not set | ||
| 927 | # CONFIG_SPI_DESIGNWARE is not set | ||
| 928 | |||
| 929 | # | ||
| 930 | # SPI Protocol Masters | ||
| 931 | # | ||
| 932 | # CONFIG_SPI_SPIDEV is not set | ||
| 933 | # CONFIG_SPI_TLE62X0 is not set | ||
| 934 | |||
| 935 | # | ||
| 936 | # PPS support | ||
| 937 | # | ||
| 938 | # CONFIG_PPS is not set | ||
| 939 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 940 | CONFIG_GPIOLIB=y | ||
| 941 | # CONFIG_DEBUG_GPIO is not set | ||
| 942 | # CONFIG_GPIO_SYSFS is not set | ||
| 943 | |||
| 944 | # | ||
| 945 | # Memory mapped GPIO expanders: | ||
| 946 | # | ||
| 947 | |||
| 948 | # | ||
| 949 | # I2C GPIO expanders: | ||
| 950 | # | ||
| 951 | # CONFIG_GPIO_MAX732X is not set | ||
| 952 | # CONFIG_GPIO_PCA953X is not set | ||
| 953 | # CONFIG_GPIO_PCF857X is not set | ||
| 954 | CONFIG_GPIO_TWL4030=y | ||
| 955 | # CONFIG_GPIO_ADP5588 is not set | ||
| 956 | |||
| 957 | # | ||
| 958 | # PCI GPIO expanders: | ||
| 959 | # | ||
| 960 | |||
| 961 | # | ||
| 962 | # SPI GPIO expanders: | ||
| 963 | # | ||
| 964 | # CONFIG_GPIO_MAX7301 is not set | ||
| 965 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 966 | # CONFIG_GPIO_MC33880 is not set | ||
| 967 | |||
| 968 | # | ||
| 969 | # AC97 GPIO expanders: | ||
| 970 | # | ||
| 971 | # CONFIG_W1 is not set | ||
| 972 | # CONFIG_POWER_SUPPLY is not set | ||
| 973 | # CONFIG_HWMON is not set | ||
| 974 | # CONFIG_THERMAL is not set | ||
| 975 | # CONFIG_WATCHDOG is not set | ||
| 976 | CONFIG_SSB_POSSIBLE=y | ||
| 977 | |||
| 978 | # | ||
| 979 | # Sonics Silicon Backplane | ||
| 980 | # | ||
| 981 | # CONFIG_SSB is not set | ||
| 982 | |||
| 983 | # | ||
| 984 | # Multifunction device drivers | ||
| 985 | # | ||
| 986 | CONFIG_MFD_CORE=y | ||
| 987 | # CONFIG_MFD_SM501 is not set | ||
| 988 | # CONFIG_MFD_ASIC3 is not set | ||
| 989 | # CONFIG_HTC_EGPIO is not set | ||
| 990 | # CONFIG_HTC_PASIC3 is not set | ||
| 991 | # CONFIG_TPS65010 is not set | ||
| 992 | CONFIG_TWL4030_CORE=y | ||
| 993 | CONFIG_TWL4030_POWER=y | ||
| 994 | CONFIG_TWL4030_CODEC=y | ||
| 995 | # CONFIG_MFD_TMIO is not set | ||
| 996 | # CONFIG_MFD_T7L66XB is not set | ||
| 997 | # CONFIG_MFD_TC6387XB is not set | ||
| 998 | # CONFIG_MFD_TC6393XB is not set | ||
| 999 | # CONFIG_PMIC_DA903X is not set | ||
| 1000 | # CONFIG_PMIC_ADP5520 is not set | ||
| 1001 | # CONFIG_MFD_WM8400 is not set | ||
| 1002 | # CONFIG_MFD_WM831X is not set | ||
| 1003 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1004 | # CONFIG_MFD_PCF50633 is not set | ||
| 1005 | # CONFIG_MFD_MC13783 is not set | ||
| 1006 | # CONFIG_AB3100_CORE is not set | ||
| 1007 | # CONFIG_EZX_PCAP is not set | ||
| 1008 | # CONFIG_MFD_88PM8607 is not set | ||
| 1009 | # CONFIG_AB4500_CORE is not set | ||
| 1010 | CONFIG_REGULATOR=y | ||
| 1011 | # CONFIG_REGULATOR_DEBUG is not set | ||
| 1012 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 1013 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 1014 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | ||
| 1015 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1016 | # CONFIG_REGULATOR_MAX1586 is not set | ||
| 1017 | # CONFIG_REGULATOR_MAX8660 is not set | ||
| 1018 | CONFIG_REGULATOR_TWL4030=y | ||
| 1019 | # CONFIG_REGULATOR_LP3971 is not set | ||
| 1020 | # CONFIG_REGULATOR_TPS65023 is not set | ||
| 1021 | # CONFIG_REGULATOR_TPS6507X is not set | ||
| 1022 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 1023 | |||
| 1024 | # | ||
| 1025 | # Graphics support | ||
| 1026 | # | ||
| 1027 | # CONFIG_VGASTATE is not set | ||
| 1028 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1029 | CONFIG_FB=y | ||
| 1030 | # CONFIG_FIRMWARE_EDID is not set | ||
| 1031 | # CONFIG_FB_DDC is not set | ||
| 1032 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1033 | CONFIG_FB_CFB_FILLRECT=y | ||
| 1034 | CONFIG_FB_CFB_COPYAREA=y | ||
| 1035 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 1036 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 1037 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 1038 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 1039 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 1040 | CONFIG_FB_FOREIGN_ENDIAN=y | ||
| 1041 | CONFIG_FB_BOTH_ENDIAN=y | ||
| 1042 | # CONFIG_FB_BIG_ENDIAN is not set | ||
| 1043 | # CONFIG_FB_LITTLE_ENDIAN is not set | ||
| 1044 | # CONFIG_FB_SYS_FOPS is not set | ||
| 1045 | # CONFIG_FB_SVGALIB is not set | ||
| 1046 | # CONFIG_FB_MACMODES is not set | ||
| 1047 | # CONFIG_FB_BACKLIGHT is not set | ||
| 1048 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 1049 | # CONFIG_FB_TILEBLITTING is not set | ||
| 1050 | |||
| 1051 | # | ||
| 1052 | # Frame buffer hardware drivers | ||
| 1053 | # | ||
| 1054 | # CONFIG_FB_S1D13XXX is not set | ||
| 1055 | # CONFIG_FB_TMIO is not set | ||
| 1056 | # CONFIG_FB_VIRTUAL is not set | ||
| 1057 | # CONFIG_FB_METRONOME is not set | ||
| 1058 | # CONFIG_FB_MB862XX is not set | ||
| 1059 | # CONFIG_FB_BROADSHEET is not set | ||
| 1060 | CONFIG_FB_OMAP_BOOTLOADER_INIT=y | ||
| 1061 | CONFIG_OMAP2_VRAM=y | ||
| 1062 | CONFIG_OMAP2_VRFB=y | ||
| 1063 | CONFIG_OMAP2_DSS=y | ||
| 1064 | CONFIG_OMAP2_VRAM_SIZE=0 | ||
| 1065 | CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y | ||
| 1066 | # CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set | ||
| 1067 | # CONFIG_OMAP2_DSS_RFBI is not set | ||
| 1068 | CONFIG_OMAP2_DSS_VENC=y | ||
| 1069 | # CONFIG_OMAP2_DSS_SDI is not set | ||
| 1070 | # CONFIG_OMAP2_DSS_DSI is not set | ||
| 1071 | # CONFIG_OMAP2_DSS_FAKE_VSYNC is not set | ||
| 1072 | CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 | ||
| 1073 | CONFIG_FB_OMAP2=y | ||
| 1074 | CONFIG_FB_OMAP2_DEBUG_SUPPORT=y | ||
| 1075 | # CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set | ||
| 1076 | CONFIG_FB_OMAP2_NUM_FBS=3 | ||
| 1077 | |||
| 1078 | # | ||
| 1079 | # OMAP2/3 Display Device Drivers | ||
| 1080 | # | ||
| 1081 | CONFIG_PANEL_GENERIC=y | ||
| 1082 | # CONFIG_PANEL_SHARP_LS037V7DW01 is not set | ||
| 1083 | CONFIG_PANEL_INNOLUX_AT070TN83=y | ||
| 1084 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 1085 | |||
| 1086 | # | ||
| 1087 | # Display device support | ||
| 1088 | # | ||
| 1089 | CONFIG_DISPLAY_SUPPORT=y | ||
| 1090 | |||
| 1091 | # | ||
| 1092 | # Display hardware drivers | ||
| 1093 | # | ||
| 1094 | |||
| 1095 | # | ||
| 1096 | # Console display driver support | ||
| 1097 | # | ||
| 1098 | # CONFIG_VGA_CONSOLE is not set | ||
| 1099 | CONFIG_DUMMY_CONSOLE=y | ||
| 1100 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 1101 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 1102 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 1103 | # CONFIG_FONTS is not set | ||
| 1104 | CONFIG_FONT_8x8=y | ||
| 1105 | CONFIG_FONT_8x16=y | ||
| 1106 | CONFIG_LOGO=y | ||
| 1107 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 1108 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 1109 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 1110 | CONFIG_SOUND=y | ||
| 1111 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 1112 | CONFIG_SND=y | ||
| 1113 | CONFIG_SND_TIMER=y | ||
| 1114 | CONFIG_SND_PCM=y | ||
| 1115 | CONFIG_SND_JACK=y | ||
| 1116 | # CONFIG_SND_SEQUENCER is not set | ||
| 1117 | # CONFIG_SND_MIXER_OSS is not set | ||
| 1118 | # CONFIG_SND_PCM_OSS is not set | ||
| 1119 | # CONFIG_SND_HRTIMER is not set | ||
| 1120 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1121 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1122 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1123 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1124 | # CONFIG_SND_DEBUG is not set | ||
| 1125 | # CONFIG_SND_RAWMIDI_SEQ is not set | ||
| 1126 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
| 1127 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
| 1128 | # CONFIG_SND_SBAWE_SEQ is not set | ||
| 1129 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 1130 | CONFIG_SND_DRIVERS=y | ||
| 1131 | # CONFIG_SND_DUMMY is not set | ||
| 1132 | # CONFIG_SND_MTPAV is not set | ||
| 1133 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1134 | # CONFIG_SND_MPU401 is not set | ||
| 1135 | CONFIG_SND_ARM=y | ||
| 1136 | CONFIG_SND_SPI=y | ||
| 1137 | CONFIG_SND_USB=y | ||
| 1138 | # CONFIG_SND_USB_AUDIO is not set | ||
| 1139 | # CONFIG_SND_USB_CAIAQ is not set | ||
| 1140 | CONFIG_SND_SOC=y | ||
| 1141 | CONFIG_SND_OMAP_SOC=y | ||
| 1142 | CONFIG_SND_OMAP_SOC_MCBSP=y | ||
| 1143 | CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y | ||
| 1144 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1145 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1146 | CONFIG_SND_SOC_TWL4030=y | ||
| 1147 | # CONFIG_SOUND_PRIME is not set | ||
| 1148 | CONFIG_HID_SUPPORT=y | ||
| 1149 | CONFIG_HID=y | ||
| 1150 | CONFIG_HIDRAW=y | ||
| 1151 | |||
| 1152 | # | ||
| 1153 | # USB Input Devices | ||
| 1154 | # | ||
| 1155 | CONFIG_USB_HID=y | ||
| 1156 | # CONFIG_HID_PID is not set | ||
| 1157 | CONFIG_USB_HIDDEV=y | ||
| 1158 | |||
| 1159 | # | ||
| 1160 | # Special HID drivers | ||
| 1161 | # | ||
| 1162 | CONFIG_HID_A4TECH=y | ||
| 1163 | CONFIG_HID_APPLE=y | ||
| 1164 | CONFIG_HID_BELKIN=y | ||
| 1165 | CONFIG_HID_CHERRY=y | ||
| 1166 | CONFIG_HID_CHICONY=y | ||
| 1167 | CONFIG_HID_CYPRESS=y | ||
| 1168 | # CONFIG_HID_DRAGONRISE is not set | ||
| 1169 | CONFIG_HID_EZKEY=y | ||
| 1170 | # CONFIG_HID_KYE is not set | ||
| 1171 | CONFIG_HID_GYRATION=y | ||
| 1172 | # CONFIG_HID_TWINHAN is not set | ||
| 1173 | # CONFIG_HID_KENSINGTON is not set | ||
| 1174 | CONFIG_HID_LOGITECH=y | ||
| 1175 | # CONFIG_LOGITECH_FF is not set | ||
| 1176 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1177 | CONFIG_HID_MICROSOFT=y | ||
| 1178 | CONFIG_HID_MONTEREY=y | ||
| 1179 | # CONFIG_HID_NTRIG is not set | ||
| 1180 | CONFIG_HID_PANTHERLORD=y | ||
| 1181 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1182 | CONFIG_HID_PETALYNX=y | ||
| 1183 | CONFIG_HID_SAMSUNG=y | ||
| 1184 | CONFIG_HID_SONY=y | ||
| 1185 | CONFIG_HID_SUNPLUS=y | ||
| 1186 | # CONFIG_HID_GREENASIA is not set | ||
| 1187 | # CONFIG_HID_SMARTJOYPLUS is not set | ||
| 1188 | # CONFIG_HID_TOPSEED is not set | ||
| 1189 | # CONFIG_HID_THRUSTMASTER is not set | ||
| 1190 | # CONFIG_HID_ZEROPLUS is not set | ||
| 1191 | CONFIG_USB_SUPPORT=y | ||
| 1192 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1193 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1194 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 1195 | CONFIG_USB=y | ||
| 1196 | # CONFIG_USB_DEBUG is not set | ||
| 1197 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 1198 | |||
| 1199 | # | ||
| 1200 | # Miscellaneous USB options | ||
| 1201 | # | ||
| 1202 | # CONFIG_USB_DEVICEFS is not set | ||
| 1203 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 1204 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1205 | # CONFIG_USB_OTG is not set | ||
| 1206 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1207 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1208 | CONFIG_USB_MON=y | ||
| 1209 | # CONFIG_USB_WUSB is not set | ||
| 1210 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1211 | |||
| 1212 | # | ||
| 1213 | # USB Host Controller Drivers | ||
| 1214 | # | ||
| 1215 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1216 | CONFIG_USB_EHCI_HCD=y | ||
| 1217 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 1218 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | ||
| 1219 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1220 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1221 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 1222 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1223 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1224 | # CONFIG_USB_SL811_HCD is not set | ||
| 1225 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1226 | # CONFIG_USB_HWA_HCD is not set | ||
| 1227 | CONFIG_USB_MUSB_HDRC=y | ||
| 1228 | CONFIG_USB_MUSB_SOC=y | ||
| 1229 | |||
| 1230 | # | ||
| 1231 | # OMAP 343x high speed USB support | ||
| 1232 | # | ||
| 1233 | CONFIG_USB_MUSB_HOST=y | ||
| 1234 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 1235 | # CONFIG_USB_MUSB_OTG is not set | ||
| 1236 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1237 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 1238 | # CONFIG_MUSB_PIO_ONLY is not set | ||
| 1239 | CONFIG_USB_INVENTRA_DMA=y | ||
| 1240 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1241 | # CONFIG_USB_MUSB_DEBUG is not set | ||
| 1242 | |||
| 1243 | # | ||
| 1244 | # USB Device Class drivers | ||
| 1245 | # | ||
| 1246 | # CONFIG_USB_ACM is not set | ||
| 1247 | # CONFIG_USB_PRINTER is not set | ||
| 1248 | # CONFIG_USB_WDM is not set | ||
| 1249 | # CONFIG_USB_TMC is not set | ||
| 1250 | |||
| 1251 | # | ||
| 1252 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 1253 | # | ||
| 1254 | |||
| 1255 | # | ||
| 1256 | # also be needed; see USB_STORAGE Help for more info | ||
| 1257 | # | ||
| 1258 | CONFIG_USB_STORAGE=m | ||
| 1259 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1260 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1261 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1262 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1263 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1264 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1265 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1266 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1267 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1268 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1269 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1270 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1271 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1272 | |||
| 1273 | # | ||
| 1274 | # USB Imaging devices | ||
| 1275 | # | ||
| 1276 | # CONFIG_USB_MDC800 is not set | ||
| 1277 | # CONFIG_USB_MICROTEK is not set | ||
| 1278 | |||
| 1279 | # | ||
| 1280 | # USB port drivers | ||
| 1281 | # | ||
| 1282 | # CONFIG_USB_SERIAL is not set | ||
| 1283 | |||
| 1284 | # | ||
| 1285 | # USB Miscellaneous drivers | ||
| 1286 | # | ||
| 1287 | # CONFIG_USB_EMI62 is not set | ||
| 1288 | # CONFIG_USB_EMI26 is not set | ||
| 1289 | # CONFIG_USB_ADUTUX is not set | ||
| 1290 | # CONFIG_USB_SEVSEG is not set | ||
| 1291 | # CONFIG_USB_RIO500 is not set | ||
| 1292 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1293 | # CONFIG_USB_LCD is not set | ||
| 1294 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1295 | # CONFIG_USB_LED is not set | ||
| 1296 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1297 | # CONFIG_USB_CYTHERM is not set | ||
| 1298 | # CONFIG_USB_IDMOUSE is not set | ||
| 1299 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1300 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1301 | # CONFIG_USB_SISUSBVGA is not set | ||
| 1302 | # CONFIG_USB_LD is not set | ||
| 1303 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1304 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1305 | # CONFIG_USB_TEST is not set | ||
| 1306 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1307 | # CONFIG_USB_VST is not set | ||
| 1308 | CONFIG_USB_GADGET=y | ||
| 1309 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1310 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 1311 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1312 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1313 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1314 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1315 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1316 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1317 | CONFIG_USB_GADGET_OMAP=y | ||
| 1318 | CONFIG_USB_OMAP=y | ||
| 1319 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1320 | # CONFIG_USB_GADGET_R8A66597 is not set | ||
| 1321 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1322 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
| 1323 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1324 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1325 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1326 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1327 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1328 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1329 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1330 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1331 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 1332 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1333 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 1334 | # CONFIG_USB_ZERO is not set | ||
| 1335 | CONFIG_USB_AUDIO=m | ||
| 1336 | CONFIG_USB_ETH=m | ||
| 1337 | CONFIG_USB_ETH_RNDIS=y | ||
| 1338 | CONFIG_USB_ETH_EEM=y | ||
| 1339 | CONFIG_USB_GADGETFS=m | ||
| 1340 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1341 | # CONFIG_USB_MASS_STORAGE is not set | ||
| 1342 | CONFIG_USB_G_SERIAL=m | ||
| 1343 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1344 | CONFIG_USB_G_PRINTER=m | ||
| 1345 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1346 | # CONFIG_USB_G_MULTI is not set | ||
| 1347 | |||
| 1348 | # | ||
| 1349 | # OTG and related infrastructure | ||
| 1350 | # | ||
| 1351 | CONFIG_USB_OTG_UTILS=y | ||
| 1352 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1353 | # CONFIG_ISP1301_OMAP is not set | ||
| 1354 | # CONFIG_USB_ULPI is not set | ||
| 1355 | CONFIG_TWL4030_USB=y | ||
| 1356 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1357 | CONFIG_MMC=y | ||
| 1358 | # CONFIG_MMC_DEBUG is not set | ||
| 1359 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1360 | |||
| 1361 | # | ||
| 1362 | # MMC/SD/SDIO Card Drivers | ||
| 1363 | # | ||
| 1364 | CONFIG_MMC_BLOCK=y | ||
| 1365 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1366 | # CONFIG_SDIO_UART is not set | ||
| 1367 | # CONFIG_MMC_TEST is not set | ||
| 1368 | |||
| 1369 | # | ||
| 1370 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1371 | # | ||
| 1372 | CONFIG_MMC_SDHCI=y | ||
| 1373 | CONFIG_MMC_SDHCI_PLTFM=m | ||
| 1374 | # CONFIG_MMC_OMAP is not set | ||
| 1375 | CONFIG_MMC_OMAP_HS=y | ||
| 1376 | # CONFIG_MMC_AT91 is not set | ||
| 1377 | # CONFIG_MMC_ATMELMCI is not set | ||
| 1378 | CONFIG_MMC_SPI=m | ||
| 1379 | # CONFIG_MEMSTICK is not set | ||
| 1380 | CONFIG_NEW_LEDS=y | ||
| 1381 | CONFIG_LEDS_CLASS=y | ||
| 1382 | |||
| 1383 | # | ||
| 1384 | # LED drivers | ||
| 1385 | # | ||
| 1386 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1387 | CONFIG_LEDS_GPIO=y | ||
| 1388 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1389 | # CONFIG_LEDS_LP3944 is not set | ||
| 1390 | # CONFIG_LEDS_PCA955X is not set | ||
| 1391 | # CONFIG_LEDS_DAC124S085 is not set | ||
| 1392 | # CONFIG_LEDS_REGULATOR is not set | ||
| 1393 | # CONFIG_LEDS_BD2802 is not set | ||
| 1394 | # CONFIG_LEDS_LT3593 is not set | ||
| 1395 | |||
| 1396 | # | ||
| 1397 | # LED Triggers | ||
| 1398 | # | ||
| 1399 | CONFIG_LEDS_TRIGGERS=y | ||
| 1400 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1401 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1402 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1403 | # CONFIG_LEDS_TRIGGER_GPIO is not set | ||
| 1404 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1405 | |||
| 1406 | # | ||
| 1407 | # iptables trigger is under Netfilter config (LED target) | ||
| 1408 | # | ||
| 1409 | # CONFIG_ACCESSIBILITY is not set | ||
| 1410 | CONFIG_RTC_LIB=y | ||
| 1411 | CONFIG_RTC_CLASS=y | ||
| 1412 | CONFIG_RTC_HCTOSYS=y | ||
| 1413 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1414 | # CONFIG_RTC_DEBUG is not set | ||
| 1415 | |||
| 1416 | # | ||
| 1417 | # RTC interfaces | ||
| 1418 | # | ||
| 1419 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1420 | CONFIG_RTC_INTF_PROC=y | ||
| 1421 | CONFIG_RTC_INTF_DEV=y | ||
| 1422 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1423 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1424 | |||
| 1425 | # | ||
| 1426 | # I2C RTC drivers | ||
| 1427 | # | ||
| 1428 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1429 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1430 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1431 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1432 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1433 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1434 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1435 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1436 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1437 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1438 | # CONFIG_RTC_DRV_BQ32K is not set | ||
| 1439 | CONFIG_RTC_DRV_TWL4030=y | ||
| 1440 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1441 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1442 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1443 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1444 | |||
| 1445 | # | ||
| 1446 | # SPI RTC drivers | ||
| 1447 | # | ||
| 1448 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1449 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1450 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1451 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1452 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1453 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1454 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1455 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1456 | |||
| 1457 | # | ||
| 1458 | # Platform RTC drivers | ||
| 1459 | # | ||
| 1460 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1461 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1462 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1463 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1464 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1465 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1466 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1467 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1468 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1469 | # CONFIG_RTC_DRV_MSM6242 is not set | ||
| 1470 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1471 | # CONFIG_RTC_DRV_RP5C01 is not set | ||
| 1472 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1473 | |||
| 1474 | # | ||
| 1475 | # on-CPU RTC drivers | ||
| 1476 | # | ||
| 1477 | # CONFIG_DMADEVICES is not set | ||
| 1478 | # CONFIG_AUXDISPLAY is not set | ||
| 1479 | # CONFIG_UIO is not set | ||
| 1480 | |||
| 1481 | # | ||
| 1482 | # TI VLYNQ | ||
| 1483 | # | ||
| 1484 | # CONFIG_STAGING is not set | ||
| 1485 | |||
| 1486 | # | ||
| 1487 | # CBUS support | ||
| 1488 | # | ||
| 1489 | # CONFIG_CBUS is not set | ||
| 1490 | |||
| 1491 | # | ||
| 1492 | # File systems | ||
| 1493 | # | ||
| 1494 | CONFIG_EXT2_FS=y | ||
| 1495 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1496 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1497 | CONFIG_EXT3_FS=y | ||
| 1498 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1499 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1500 | # CONFIG_EXT4_FS is not set | ||
| 1501 | CONFIG_JBD=y | ||
| 1502 | # CONFIG_REISERFS_FS is not set | ||
| 1503 | # CONFIG_JFS_FS is not set | ||
| 1504 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1505 | # CONFIG_XFS_FS is not set | ||
| 1506 | # CONFIG_GFS2_FS is not set | ||
| 1507 | # CONFIG_OCFS2_FS is not set | ||
| 1508 | # CONFIG_BTRFS_FS is not set | ||
| 1509 | # CONFIG_NILFS2_FS is not set | ||
| 1510 | CONFIG_FILE_LOCKING=y | ||
| 1511 | CONFIG_FSNOTIFY=y | ||
| 1512 | CONFIG_DNOTIFY=y | ||
| 1513 | CONFIG_INOTIFY=y | ||
| 1514 | CONFIG_INOTIFY_USER=y | ||
| 1515 | CONFIG_QUOTA=y | ||
| 1516 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
| 1517 | CONFIG_PRINT_QUOTA_WARNING=y | ||
| 1518 | CONFIG_QUOTA_TREE=y | ||
| 1519 | # CONFIG_QFMT_V1 is not set | ||
| 1520 | CONFIG_QFMT_V2=y | ||
| 1521 | CONFIG_QUOTACTL=y | ||
| 1522 | # CONFIG_AUTOFS_FS is not set | ||
| 1523 | # CONFIG_AUTOFS4_FS is not set | ||
| 1524 | # CONFIG_FUSE_FS is not set | ||
| 1525 | |||
| 1526 | # | ||
| 1527 | # Caches | ||
| 1528 | # | ||
| 1529 | # CONFIG_FSCACHE is not set | ||
| 1530 | |||
| 1531 | # | ||
| 1532 | # CD-ROM/DVD Filesystems | ||
| 1533 | # | ||
| 1534 | # CONFIG_ISO9660_FS is not set | ||
| 1535 | # CONFIG_UDF_FS is not set | ||
| 1536 | |||
| 1537 | # | ||
| 1538 | # DOS/FAT/NT Filesystems | ||
| 1539 | # | ||
| 1540 | CONFIG_FAT_FS=y | ||
| 1541 | CONFIG_MSDOS_FS=y | ||
| 1542 | CONFIG_VFAT_FS=y | ||
| 1543 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1544 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1545 | # CONFIG_NTFS_FS is not set | ||
| 1546 | |||
| 1547 | # | ||
| 1548 | # Pseudo filesystems | ||
| 1549 | # | ||
| 1550 | CONFIG_PROC_FS=y | ||
| 1551 | CONFIG_PROC_SYSCTL=y | ||
| 1552 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1553 | CONFIG_SYSFS=y | ||
| 1554 | CONFIG_TMPFS=y | ||
| 1555 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1556 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1557 | # CONFIG_CONFIGFS_FS is not set | ||
| 1558 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1559 | # CONFIG_ADFS_FS is not set | ||
| 1560 | # CONFIG_AFFS_FS is not set | ||
| 1561 | # CONFIG_HFS_FS is not set | ||
| 1562 | # CONFIG_HFSPLUS_FS is not set | ||
| 1563 | # CONFIG_BEFS_FS is not set | ||
| 1564 | # CONFIG_BFS_FS is not set | ||
| 1565 | # CONFIG_EFS_FS is not set | ||
| 1566 | CONFIG_JFFS2_FS=y | ||
| 1567 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1568 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1569 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1570 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 1571 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1572 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1573 | CONFIG_JFFS2_ZLIB=y | ||
| 1574 | # CONFIG_JFFS2_LZO is not set | ||
| 1575 | CONFIG_JFFS2_RTIME=y | ||
| 1576 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1577 | CONFIG_UBIFS_FS=y | ||
| 1578 | # CONFIG_UBIFS_FS_XATTR is not set | ||
| 1579 | # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | ||
| 1580 | CONFIG_UBIFS_FS_LZO=y | ||
| 1581 | CONFIG_UBIFS_FS_ZLIB=y | ||
| 1582 | # CONFIG_UBIFS_FS_DEBUG is not set | ||
| 1583 | CONFIG_CRAMFS=y | ||
| 1584 | # CONFIG_SQUASHFS is not set | ||
| 1585 | # CONFIG_VXFS_FS is not set | ||
| 1586 | # CONFIG_MINIX_FS is not set | ||
| 1587 | # CONFIG_OMFS_FS is not set | ||
| 1588 | # CONFIG_HPFS_FS is not set | ||
| 1589 | # CONFIG_QNX4FS_FS is not set | ||
| 1590 | # CONFIG_ROMFS_FS is not set | ||
| 1591 | # CONFIG_SYSV_FS is not set | ||
| 1592 | # CONFIG_UFS_FS is not set | ||
| 1593 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1594 | CONFIG_NFS_FS=y | ||
| 1595 | CONFIG_NFS_V3=y | ||
| 1596 | # CONFIG_NFS_V3_ACL is not set | ||
| 1597 | CONFIG_NFS_V4=y | ||
| 1598 | # CONFIG_NFS_V4_1 is not set | ||
| 1599 | CONFIG_ROOT_NFS=y | ||
| 1600 | # CONFIG_NFSD is not set | ||
| 1601 | CONFIG_LOCKD=y | ||
| 1602 | CONFIG_LOCKD_V4=y | ||
| 1603 | CONFIG_NFS_COMMON=y | ||
| 1604 | CONFIG_SUNRPC=y | ||
| 1605 | CONFIG_SUNRPC_GSS=y | ||
| 1606 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 1607 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1608 | # CONFIG_SMB_FS is not set | ||
| 1609 | # CONFIG_CIFS is not set | ||
| 1610 | # CONFIG_NCP_FS is not set | ||
| 1611 | # CONFIG_CODA_FS is not set | ||
| 1612 | # CONFIG_AFS_FS is not set | ||
| 1613 | |||
| 1614 | # | ||
| 1615 | # Partition Types | ||
| 1616 | # | ||
| 1617 | CONFIG_PARTITION_ADVANCED=y | ||
| 1618 | # CONFIG_ACORN_PARTITION is not set | ||
| 1619 | # CONFIG_OSF_PARTITION is not set | ||
| 1620 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1621 | # CONFIG_ATARI_PARTITION is not set | ||
| 1622 | # CONFIG_MAC_PARTITION is not set | ||
| 1623 | CONFIG_MSDOS_PARTITION=y | ||
| 1624 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1625 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1626 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1627 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1628 | # CONFIG_LDM_PARTITION is not set | ||
| 1629 | # CONFIG_SGI_PARTITION is not set | ||
| 1630 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1631 | # CONFIG_SUN_PARTITION is not set | ||
| 1632 | # CONFIG_KARMA_PARTITION is not set | ||
| 1633 | # CONFIG_EFI_PARTITION is not set | ||
| 1634 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1635 | CONFIG_NLS=y | ||
| 1636 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1637 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1638 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1639 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1640 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1641 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1642 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1643 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1644 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1645 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1646 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1647 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1648 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1649 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1650 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1651 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1652 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1653 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1654 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1655 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1656 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1657 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1658 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1659 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1660 | # CONFIG_NLS_ASCII is not set | ||
| 1661 | CONFIG_NLS_ISO8859_1=y | ||
| 1662 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1663 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1664 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1665 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1666 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1667 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1668 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1669 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1670 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1671 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1672 | # CONFIG_NLS_KOI8_R is not set | ||
| 1673 | # CONFIG_NLS_KOI8_U is not set | ||
| 1674 | # CONFIG_NLS_UTF8 is not set | ||
| 1675 | # CONFIG_DLM is not set | ||
| 1676 | |||
| 1677 | # | ||
| 1678 | # Kernel hacking | ||
| 1679 | # | ||
| 1680 | CONFIG_PRINTK_TIME=y | ||
| 1681 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1682 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1683 | CONFIG_FRAME_WARN=1024 | ||
| 1684 | CONFIG_MAGIC_SYSRQ=y | ||
| 1685 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1686 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1687 | # CONFIG_DEBUG_FS is not set | ||
| 1688 | # CONFIG_HEADERS_CHECK is not set | ||
| 1689 | CONFIG_DEBUG_KERNEL=y | ||
| 1690 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1691 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1692 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1693 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1694 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1695 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y | ||
| 1696 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 | ||
| 1697 | CONFIG_SCHED_DEBUG=y | ||
| 1698 | # CONFIG_SCHEDSTATS is not set | ||
| 1699 | # CONFIG_TIMER_STATS is not set | ||
| 1700 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1701 | # CONFIG_DEBUG_SLAB is not set | ||
| 1702 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1703 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1704 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1705 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1706 | CONFIG_DEBUG_MUTEXES=y | ||
| 1707 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1708 | # CONFIG_PROVE_LOCKING is not set | ||
| 1709 | # CONFIG_LOCK_STAT is not set | ||
| 1710 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1711 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1712 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1713 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1714 | # CONFIG_DEBUG_INFO is not set | ||
| 1715 | # CONFIG_DEBUG_VM is not set | ||
| 1716 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1717 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1718 | # CONFIG_DEBUG_LIST is not set | ||
| 1719 | # CONFIG_DEBUG_SG is not set | ||
| 1720 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1721 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 1722 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1723 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1724 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1725 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1726 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1727 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 1728 | # CONFIG_FAULT_INJECTION is not set | ||
| 1729 | # CONFIG_LATENCYTOP is not set | ||
| 1730 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1731 | # CONFIG_PAGE_POISONING is not set | ||
| 1732 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1733 | CONFIG_TRACING_SUPPORT=y | ||
| 1734 | CONFIG_FTRACE=y | ||
| 1735 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1736 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1737 | # CONFIG_SCHED_TRACER is not set | ||
| 1738 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
| 1739 | # CONFIG_BOOT_TRACER is not set | ||
| 1740 | CONFIG_BRANCH_PROFILE_NONE=y | ||
| 1741 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 1742 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 1743 | # CONFIG_STACK_TRACER is not set | ||
| 1744 | # CONFIG_KMEMTRACE is not set | ||
| 1745 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1746 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1747 | # CONFIG_SAMPLES is not set | ||
| 1748 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1749 | # CONFIG_KGDB is not set | ||
| 1750 | CONFIG_ARM_UNWIND=y | ||
| 1751 | CONFIG_DEBUG_USER=y | ||
| 1752 | CONFIG_DEBUG_ERRORS=y | ||
| 1753 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1754 | # CONFIG_DEBUG_LL is not set | ||
| 1755 | # CONFIG_OC_ETM is not set | ||
| 1756 | |||
| 1757 | # | ||
| 1758 | # Security options | ||
| 1759 | # | ||
| 1760 | # CONFIG_KEYS is not set | ||
| 1761 | # CONFIG_SECURITY is not set | ||
| 1762 | # CONFIG_SECURITYFS is not set | ||
| 1763 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set | ||
| 1764 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
| 1765 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
| 1766 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
| 1767 | CONFIG_DEFAULT_SECURITY="" | ||
| 1768 | CONFIG_CRYPTO=y | ||
| 1769 | |||
| 1770 | # | ||
| 1771 | # Crypto core or helper | ||
| 1772 | # | ||
| 1773 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1774 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1775 | CONFIG_CRYPTO_AEAD2=y | ||
| 1776 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1777 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1778 | CONFIG_CRYPTO_HASH=y | ||
| 1779 | CONFIG_CRYPTO_HASH2=y | ||
| 1780 | CONFIG_CRYPTO_RNG2=y | ||
| 1781 | CONFIG_CRYPTO_PCOMP=y | ||
| 1782 | CONFIG_CRYPTO_MANAGER=y | ||
| 1783 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1784 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1785 | # CONFIG_CRYPTO_NULL is not set | ||
| 1786 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 1787 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1788 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1789 | # CONFIG_CRYPTO_TEST is not set | ||
| 1790 | |||
| 1791 | # | ||
| 1792 | # Authenticated Encryption with Associated Data | ||
| 1793 | # | ||
| 1794 | # CONFIG_CRYPTO_CCM is not set | ||
| 1795 | # CONFIG_CRYPTO_GCM is not set | ||
| 1796 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1797 | |||
| 1798 | # | ||
| 1799 | # Block modes | ||
| 1800 | # | ||
| 1801 | CONFIG_CRYPTO_CBC=y | ||
| 1802 | # CONFIG_CRYPTO_CTR is not set | ||
| 1803 | # CONFIG_CRYPTO_CTS is not set | ||
| 1804 | CONFIG_CRYPTO_ECB=m | ||
| 1805 | # CONFIG_CRYPTO_LRW is not set | ||
| 1806 | CONFIG_CRYPTO_PCBC=m | ||
| 1807 | # CONFIG_CRYPTO_XTS is not set | ||
| 1808 | |||
| 1809 | # | ||
| 1810 | # Hash modes | ||
| 1811 | # | ||
| 1812 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1813 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1814 | # CONFIG_CRYPTO_VMAC is not set | ||
| 1815 | |||
| 1816 | # | ||
| 1817 | # Digest | ||
| 1818 | # | ||
| 1819 | CONFIG_CRYPTO_CRC32C=y | ||
| 1820 | # CONFIG_CRYPTO_GHASH is not set | ||
| 1821 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1822 | CONFIG_CRYPTO_MD5=y | ||
| 1823 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1824 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1825 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1826 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1827 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1828 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1829 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1830 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1831 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1832 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1833 | |||
| 1834 | # | ||
| 1835 | # Ciphers | ||
| 1836 | # | ||
| 1837 | # CONFIG_CRYPTO_AES is not set | ||
| 1838 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1839 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1840 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1841 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1842 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1843 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1844 | CONFIG_CRYPTO_DES=y | ||
| 1845 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1846 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1847 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1848 | # CONFIG_CRYPTO_SEED is not set | ||
| 1849 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1850 | # CONFIG_CRYPTO_TEA is not set | ||
| 1851 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1852 | |||
| 1853 | # | ||
| 1854 | # Compression | ||
| 1855 | # | ||
| 1856 | CONFIG_CRYPTO_DEFLATE=y | ||
| 1857 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1858 | CONFIG_CRYPTO_LZO=y | ||
| 1859 | |||
| 1860 | # | ||
| 1861 | # Random Number Generation | ||
| 1862 | # | ||
| 1863 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1864 | CONFIG_CRYPTO_HW=y | ||
| 1865 | # CONFIG_BINARY_PRINTF is not set | ||
| 1866 | |||
| 1867 | # | ||
| 1868 | # Library routines | ||
| 1869 | # | ||
| 1870 | CONFIG_BITREVERSE=y | ||
| 1871 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1872 | CONFIG_CRC_CCITT=y | ||
| 1873 | CONFIG_CRC16=y | ||
| 1874 | CONFIG_CRC_T10DIF=m | ||
| 1875 | CONFIG_CRC_ITU_T=m | ||
| 1876 | CONFIG_CRC32=y | ||
| 1877 | CONFIG_CRC7=m | ||
| 1878 | CONFIG_LIBCRC32C=y | ||
| 1879 | CONFIG_ZLIB_INFLATE=y | ||
| 1880 | CONFIG_ZLIB_DEFLATE=y | ||
| 1881 | CONFIG_LZO_COMPRESS=y | ||
| 1882 | CONFIG_LZO_DECOMPRESS=y | ||
| 1883 | CONFIG_DECOMPRESS_GZIP=y | ||
| 1884 | CONFIG_DECOMPRESS_BZIP2=y | ||
| 1885 | CONFIG_DECOMPRESS_LZMA=y | ||
| 1886 | CONFIG_HAS_IOMEM=y | ||
| 1887 | CONFIG_HAS_IOPORT=y | ||
| 1888 | CONFIG_HAS_DMA=y | ||
| 1889 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/igep0020_defconfig b/arch/arm/configs/igep0020_defconfig index a192248c6dd6..e7940a9c5ccc 100644 --- a/arch/arm/configs/igep0020_defconfig +++ b/arch/arm/configs/igep0020_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.32-rc6 | 3 | # Linux kernel version: 2.6.33-rc3 |
| 4 | # Fri Nov 13 12:01:17 2009 | 4 | # Thu Jan 7 16:14:55 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -46,6 +46,7 @@ CONFIG_BSD_PROCESS_ACCT=y | |||
| 46 | # | 46 | # |
| 47 | CONFIG_TREE_RCU=y | 47 | CONFIG_TREE_RCU=y |
| 48 | # CONFIG_TREE_PREEMPT_RCU is not set | 48 | # CONFIG_TREE_PREEMPT_RCU is not set |
| 49 | # CONFIG_TINY_RCU is not set | ||
| 49 | # CONFIG_RCU_TRACE is not set | 50 | # CONFIG_RCU_TRACE is not set |
| 50 | CONFIG_RCU_FANOUT=32 | 51 | CONFIG_RCU_FANOUT=32 |
| 51 | # CONFIG_RCU_FANOUT_EXACT is not set | 52 | # CONFIG_RCU_FANOUT_EXACT is not set |
| @@ -126,14 +127,41 @@ CONFIG_LBDAF=y | |||
| 126 | # IO Schedulers | 127 | # IO Schedulers |
| 127 | # | 128 | # |
| 128 | CONFIG_IOSCHED_NOOP=y | 129 | CONFIG_IOSCHED_NOOP=y |
| 129 | CONFIG_IOSCHED_AS=y | ||
| 130 | CONFIG_IOSCHED_DEADLINE=y | 130 | CONFIG_IOSCHED_DEADLINE=y |
| 131 | CONFIG_IOSCHED_CFQ=y | 131 | CONFIG_IOSCHED_CFQ=y |
| 132 | CONFIG_DEFAULT_AS=y | ||
| 133 | # CONFIG_DEFAULT_DEADLINE is not set | 132 | # CONFIG_DEFAULT_DEADLINE is not set |
| 134 | # CONFIG_DEFAULT_CFQ is not set | 133 | CONFIG_DEFAULT_CFQ=y |
| 135 | # CONFIG_DEFAULT_NOOP is not set | 134 | # CONFIG_DEFAULT_NOOP is not set |
| 136 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 135 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 136 | # CONFIG_INLINE_SPIN_TRYLOCK is not set | ||
| 137 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
| 138 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
| 139 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
| 140 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
| 141 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
| 142 | CONFIG_INLINE_SPIN_UNLOCK=y | ||
| 143 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
| 144 | CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | ||
| 145 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
| 146 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
| 147 | # CONFIG_INLINE_READ_LOCK is not set | ||
| 148 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
| 149 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
| 150 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
| 151 | CONFIG_INLINE_READ_UNLOCK=y | ||
| 152 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
| 153 | CONFIG_INLINE_READ_UNLOCK_IRQ=y | ||
| 154 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
| 155 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
| 156 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
| 157 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
| 158 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
| 159 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
| 160 | CONFIG_INLINE_WRITE_UNLOCK=y | ||
| 161 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
| 162 | CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | ||
| 163 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
| 164 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
| 137 | # CONFIG_FREEZER is not set | 165 | # CONFIG_FREEZER is not set |
| 138 | 166 | ||
| 139 | # | 167 | # |
| @@ -162,6 +190,7 @@ CONFIG_MMU=y | |||
| 162 | # CONFIG_ARCH_IXP2000 is not set | 190 | # CONFIG_ARCH_IXP2000 is not set |
| 163 | # CONFIG_ARCH_IXP4XX is not set | 191 | # CONFIG_ARCH_IXP4XX is not set |
| 164 | # CONFIG_ARCH_L7200 is not set | 192 | # CONFIG_ARCH_L7200 is not set |
| 193 | # CONFIG_ARCH_DOVE is not set | ||
| 165 | # CONFIG_ARCH_KIRKWOOD is not set | 194 | # CONFIG_ARCH_KIRKWOOD is not set |
| 166 | # CONFIG_ARCH_LOKI is not set | 195 | # CONFIG_ARCH_LOKI is not set |
| 167 | # CONFIG_ARCH_MV78XX0 is not set | 196 | # CONFIG_ARCH_MV78XX0 is not set |
| @@ -184,6 +213,7 @@ CONFIG_MMU=y | |||
| 184 | # CONFIG_ARCH_DAVINCI is not set | 213 | # CONFIG_ARCH_DAVINCI is not set |
| 185 | CONFIG_ARCH_OMAP=y | 214 | CONFIG_ARCH_OMAP=y |
| 186 | # CONFIG_ARCH_BCMRING is not set | 215 | # CONFIG_ARCH_BCMRING is not set |
| 216 | # CONFIG_ARCH_U8500 is not set | ||
| 187 | 217 | ||
| 188 | # | 218 | # |
| 189 | # TI OMAP Implementations | 219 | # TI OMAP Implementations |
| @@ -197,12 +227,8 @@ CONFIG_ARCH_OMAP3=y | |||
| 197 | # | 227 | # |
| 198 | # OMAP Feature Selections | 228 | # OMAP Feature Selections |
| 199 | # | 229 | # |
| 200 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | 230 | CONFIG_OMAP_RESET_CLOCKS=y |
| 201 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | 231 | # CONFIG_OMAP_MUX is not set |
| 202 | # CONFIG_OMAP_RESET_CLOCKS is not set | ||
| 203 | CONFIG_OMAP_MUX=y | ||
| 204 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 205 | CONFIG_OMAP_MUX_WARNINGS=y | ||
| 206 | CONFIG_OMAP_MCBSP=y | 232 | CONFIG_OMAP_MCBSP=y |
| 207 | # CONFIG_OMAP_MBOX_FWK is not set | 233 | # CONFIG_OMAP_MBOX_FWK is not set |
| 208 | # CONFIG_OMAP_MPU_TIMER is not set | 234 | # CONFIG_OMAP_MPU_TIMER is not set |
| @@ -217,6 +243,7 @@ CONFIG_OMAP_LL_DEBUG_UART3=y | |||
| 217 | CONFIG_OMAP_PM_NOOP=y | 243 | CONFIG_OMAP_PM_NOOP=y |
| 218 | CONFIG_ARCH_OMAP34XX=y | 244 | CONFIG_ARCH_OMAP34XX=y |
| 219 | CONFIG_ARCH_OMAP3430=y | 245 | CONFIG_ARCH_OMAP3430=y |
| 246 | CONFIG_OMAP_PACKAGE_CBB=y | ||
| 220 | 247 | ||
| 221 | # | 248 | # |
| 222 | # OMAP Board Type | 249 | # OMAP Board Type |
| @@ -227,13 +254,16 @@ CONFIG_ARCH_OMAP3430=y | |||
| 227 | # CONFIG_MACH_OMAP3EVM is not set | 254 | # CONFIG_MACH_OMAP3EVM is not set |
| 228 | # CONFIG_MACH_OMAP3517EVM is not set | 255 | # CONFIG_MACH_OMAP3517EVM is not set |
| 229 | # CONFIG_MACH_OMAP3_PANDORA is not set | 256 | # CONFIG_MACH_OMAP3_PANDORA is not set |
| 257 | # CONFIG_MACH_OMAP3_TOUCHBOOK is not set | ||
| 230 | # CONFIG_MACH_OMAP_3430SDP is not set | 258 | # CONFIG_MACH_OMAP_3430SDP is not set |
| 231 | # CONFIG_MACH_NOKIA_RX51 is not set | 259 | # CONFIG_MACH_NOKIA_RX51 is not set |
| 232 | # CONFIG_MACH_OMAP_ZOOM2 is not set | 260 | # CONFIG_MACH_OMAP_ZOOM2 is not set |
| 233 | # CONFIG_MACH_CM_T35 is not set | ||
| 234 | # CONFIG_MACH_OMAP_ZOOM3 is not set | 261 | # CONFIG_MACH_OMAP_ZOOM3 is not set |
| 235 | # CONFIG_MACH_OMAP_3630SDP is not set | 262 | # CONFIG_MACH_CM_T35 is not set |
| 236 | CONFIG_MACH_IGEP0020=y | 263 | CONFIG_MACH_IGEP0020=y |
| 264 | # CONFIG_MACH_OMAP_3630SDP is not set | ||
| 265 | # CONFIG_OMAP3_EMU is not set | ||
| 266 | # CONFIG_OMAP3_SDRC_AC_TIMING is not set | ||
| 237 | 267 | ||
| 238 | # | 268 | # |
| 239 | # Processor Type | 269 | # Processor Type |
| @@ -305,8 +335,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 305 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 335 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 306 | CONFIG_ZONE_DMA_FLAG=0 | 336 | CONFIG_ZONE_DMA_FLAG=0 |
| 307 | CONFIG_VIRT_TO_BUS=y | 337 | CONFIG_VIRT_TO_BUS=y |
| 308 | CONFIG_HAVE_MLOCK=y | ||
| 309 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 310 | # CONFIG_KSM is not set | 338 | # CONFIG_KSM is not set |
| 311 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | 339 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 |
| 312 | # CONFIG_LEDS is not set | 340 | # CONFIG_LEDS is not set |
| @@ -440,35 +468,35 @@ CONFIG_BT_HIDP=m | |||
| 440 | # | 468 | # |
| 441 | # Bluetooth device drivers | 469 | # Bluetooth device drivers |
| 442 | # | 470 | # |
| 443 | CONFIG_BT_HCIBTUSB=m | 471 | # CONFIG_BT_HCIBTUSB is not set |
| 444 | # CONFIG_BT_HCIBTSDIO is not set | 472 | # CONFIG_BT_HCIBTSDIO is not set |
| 445 | CONFIG_BT_HCIUART=m | 473 | CONFIG_BT_HCIUART=m |
| 446 | CONFIG_BT_HCIUART_H4=y | 474 | CONFIG_BT_HCIUART_H4=y |
| 447 | CONFIG_BT_HCIUART_BCSP=y | 475 | CONFIG_BT_HCIUART_BCSP=y |
| 448 | CONFIG_BT_HCIUART_LL=y | 476 | CONFIG_BT_HCIUART_LL=y |
| 449 | CONFIG_BT_HCIBCM203X=m | 477 | # CONFIG_BT_HCIBCM203X is not set |
| 450 | CONFIG_BT_HCIBPA10X=m | 478 | # CONFIG_BT_HCIBPA10X is not set |
| 451 | CONFIG_BT_HCIBFUSB=m | 479 | # CONFIG_BT_HCIBFUSB is not set |
| 452 | CONFIG_BT_HCIVHCI=m | 480 | CONFIG_BT_HCIVHCI=m |
| 453 | CONFIG_BT_MRVL=m | 481 | CONFIG_BT_MRVL=m |
| 454 | CONFIG_BT_MRVL_SDIO=m | 482 | CONFIG_BT_MRVL_SDIO=m |
| 455 | # CONFIG_AF_RXRPC is not set | 483 | # CONFIG_AF_RXRPC is not set |
| 456 | CONFIG_WIRELESS=y | 484 | CONFIG_WIRELESS=y |
| 457 | CONFIG_CFG80211=m | 485 | CONFIG_WIRELESS_EXT=y |
| 486 | CONFIG_WEXT_CORE=y | ||
| 487 | CONFIG_WEXT_PROC=y | ||
| 488 | CONFIG_WEXT_SPY=y | ||
| 489 | CONFIG_CFG80211=y | ||
| 458 | # CONFIG_NL80211_TESTMODE is not set | 490 | # CONFIG_NL80211_TESTMODE is not set |
| 459 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set | 491 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set |
| 460 | # CONFIG_CFG80211_REG_DEBUG is not set | 492 | # CONFIG_CFG80211_REG_DEBUG is not set |
| 461 | CONFIG_CFG80211_DEFAULT_PS=y | 493 | CONFIG_CFG80211_DEFAULT_PS=y |
| 462 | CONFIG_CFG80211_DEFAULT_PS_VALUE=1 | ||
| 463 | # CONFIG_WIRELESS_OLD_REGULATORY is not set | 494 | # CONFIG_WIRELESS_OLD_REGULATORY is not set |
| 464 | CONFIG_WIRELESS_EXT=y | 495 | CONFIG_CFG80211_WEXT=y |
| 465 | CONFIG_WIRELESS_EXT_SYSFS=y | 496 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 466 | CONFIG_LIB80211=m | 497 | CONFIG_LIB80211=y |
| 467 | CONFIG_LIB80211_CRYPT_WEP=m | ||
| 468 | CONFIG_LIB80211_CRYPT_CCMP=m | ||
| 469 | CONFIG_LIB80211_CRYPT_TKIP=m | ||
| 470 | # CONFIG_LIB80211_DEBUG is not set | 498 | # CONFIG_LIB80211_DEBUG is not set |
| 471 | CONFIG_MAC80211=m | 499 | CONFIG_MAC80211=y |
| 472 | # CONFIG_MAC80211_RC_PID is not set | 500 | # CONFIG_MAC80211_RC_PID is not set |
| 473 | CONFIG_MAC80211_RC_MINSTREL=y | 501 | CONFIG_MAC80211_RC_MINSTREL=y |
| 474 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | 502 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set |
| @@ -500,12 +528,95 @@ CONFIG_EXTRA_FIRMWARE="" | |||
| 500 | # CONFIG_SYS_HYPERVISOR is not set | 528 | # CONFIG_SYS_HYPERVISOR is not set |
| 501 | CONFIG_CONNECTOR=y | 529 | CONFIG_CONNECTOR=y |
| 502 | CONFIG_PROC_EVENTS=y | 530 | CONFIG_PROC_EVENTS=y |
| 503 | # CONFIG_MTD is not set | 531 | CONFIG_MTD=y |
| 532 | # CONFIG_MTD_DEBUG is not set | ||
| 533 | # CONFIG_MTD_TESTS is not set | ||
| 534 | # CONFIG_MTD_CONCAT is not set | ||
| 535 | CONFIG_MTD_PARTITIONS=y | ||
| 536 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 537 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 538 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 539 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 540 | |||
| 541 | # | ||
| 542 | # User Modules And Translation Layers | ||
| 543 | # | ||
| 544 | CONFIG_MTD_CHAR=y | ||
| 545 | CONFIG_MTD_BLKDEVS=y | ||
| 546 | CONFIG_MTD_BLOCK=y | ||
| 547 | # CONFIG_FTL is not set | ||
| 548 | # CONFIG_NFTL is not set | ||
| 549 | # CONFIG_INFTL is not set | ||
| 550 | # CONFIG_RFD_FTL is not set | ||
| 551 | # CONFIG_SSFDC is not set | ||
| 552 | # CONFIG_MTD_OOPS is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # RAM/ROM/Flash chip drivers | ||
| 556 | # | ||
| 557 | # CONFIG_MTD_CFI is not set | ||
| 558 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 559 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 560 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 561 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 562 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 563 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 564 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 565 | CONFIG_MTD_CFI_I1=y | ||
| 566 | CONFIG_MTD_CFI_I2=y | ||
| 567 | # CONFIG_MTD_CFI_I4 is not set | ||
| 568 | # CONFIG_MTD_CFI_I8 is not set | ||
| 569 | # CONFIG_MTD_RAM is not set | ||
| 570 | # CONFIG_MTD_ROM is not set | ||
| 571 | # CONFIG_MTD_ABSENT is not set | ||
| 572 | |||
| 573 | # | ||
| 574 | # Mapping drivers for chip access | ||
| 575 | # | ||
| 576 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 577 | # CONFIG_MTD_PLATRAM is not set | ||
| 578 | |||
| 579 | # | ||
| 580 | # Self-contained MTD device drivers | ||
| 581 | # | ||
| 582 | # CONFIG_MTD_DATAFLASH is not set | ||
| 583 | # CONFIG_MTD_M25P80 is not set | ||
| 584 | # CONFIG_MTD_SST25L is not set | ||
| 585 | # CONFIG_MTD_SLRAM is not set | ||
| 586 | # CONFIG_MTD_PHRAM is not set | ||
| 587 | # CONFIG_MTD_MTDRAM is not set | ||
| 588 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 589 | |||
| 590 | # | ||
| 591 | # Disk-On-Chip Device Drivers | ||
| 592 | # | ||
| 593 | # CONFIG_MTD_DOC2000 is not set | ||
| 594 | # CONFIG_MTD_DOC2001 is not set | ||
| 595 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 596 | # CONFIG_MTD_NAND is not set | ||
| 597 | CONFIG_MTD_ONENAND=y | ||
| 598 | # CONFIG_MTD_ONENAND_VERIFY_WRITE is not set | ||
| 599 | # CONFIG_MTD_ONENAND_GENERIC is not set | ||
| 600 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 601 | # CONFIG_MTD_ONENAND_OTP is not set | ||
| 602 | CONFIG_MTD_ONENAND_2X_PROGRAM=y | ||
| 603 | # CONFIG_MTD_ONENAND_SIM is not set | ||
| 604 | |||
| 605 | # | ||
| 606 | # LPDDR flash memory drivers | ||
| 607 | # | ||
| 608 | # CONFIG_MTD_LPDDR is not set | ||
| 609 | |||
| 610 | # | ||
| 611 | # UBI - Unsorted block images | ||
| 612 | # | ||
| 613 | # CONFIG_MTD_UBI is not set | ||
| 504 | # CONFIG_PARPORT is not set | 614 | # CONFIG_PARPORT is not set |
| 505 | CONFIG_BLK_DEV=y | 615 | CONFIG_BLK_DEV=y |
| 506 | # CONFIG_BLK_DEV_COW_COMMON is not set | 616 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 507 | CONFIG_BLK_DEV_LOOP=y | 617 | CONFIG_BLK_DEV_LOOP=y |
| 508 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 618 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| 619 | # CONFIG_BLK_DEV_DRBD is not set | ||
| 509 | # CONFIG_BLK_DEV_NBD is not set | 620 | # CONFIG_BLK_DEV_NBD is not set |
| 510 | # CONFIG_BLK_DEV_UB is not set | 621 | # CONFIG_BLK_DEV_UB is not set |
| 511 | CONFIG_BLK_DEV_RAM=y | 622 | CONFIG_BLK_DEV_RAM=y |
| @@ -516,7 +627,6 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 | |||
| 516 | # CONFIG_ATA_OVER_ETH is not set | 627 | # CONFIG_ATA_OVER_ETH is not set |
| 517 | # CONFIG_MG_DISK is not set | 628 | # CONFIG_MG_DISK is not set |
| 518 | # CONFIG_MISC_DEVICES is not set | 629 | # CONFIG_MISC_DEVICES is not set |
| 519 | CONFIG_EEPROM_93CX6=m | ||
| 520 | CONFIG_HAVE_IDE=y | 630 | CONFIG_HAVE_IDE=y |
| 521 | # CONFIG_IDE is not set | 631 | # CONFIG_IDE is not set |
| 522 | 632 | ||
| @@ -613,56 +723,26 @@ CONFIG_SMSC911X=y | |||
| 613 | # CONFIG_NETDEV_1000 is not set | 723 | # CONFIG_NETDEV_1000 is not set |
| 614 | # CONFIG_NETDEV_10000 is not set | 724 | # CONFIG_NETDEV_10000 is not set |
| 615 | CONFIG_WLAN=y | 725 | CONFIG_WLAN=y |
| 616 | # CONFIG_WLAN_PRE80211 is not set | ||
| 617 | CONFIG_WLAN_80211=y | ||
| 618 | CONFIG_LIBERTAS=m | ||
| 619 | CONFIG_LIBERTAS_USB=m | ||
| 620 | CONFIG_LIBERTAS_SDIO=m | ||
| 621 | # CONFIG_LIBERTAS_SPI is not set | ||
| 622 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 623 | # CONFIG_LIBERTAS_THINFIRM is not set | 726 | # CONFIG_LIBERTAS_THINFIRM is not set |
| 624 | CONFIG_AT76C50X_USB=m | 727 | # CONFIG_AT76C50X_USB is not set |
| 625 | CONFIG_USB_ZD1201=m | 728 | # CONFIG_USB_ZD1201 is not set |
| 626 | CONFIG_USB_NET_RNDIS_WLAN=m | 729 | # CONFIG_USB_NET_RNDIS_WLAN is not set |
| 627 | CONFIG_RTL8187=m | 730 | # CONFIG_RTL8187 is not set |
| 628 | # CONFIG_MAC80211_HWSIM is not set | 731 | # CONFIG_MAC80211_HWSIM is not set |
| 629 | CONFIG_P54_COMMON=m | 732 | # CONFIG_ATH_COMMON is not set |
| 630 | CONFIG_P54_USB=m | 733 | # CONFIG_B43 is not set |
| 631 | CONFIG_P54_SPI=m | 734 | # CONFIG_B43LEGACY is not set |
| 632 | CONFIG_ATH_COMMON=m | 735 | # CONFIG_HOSTAP is not set |
| 633 | CONFIG_AR9170_USB=m | ||
| 634 | CONFIG_HOSTAP=m | ||
| 635 | CONFIG_HOSTAP_FIRMWARE=y | ||
| 636 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
| 637 | CONFIG_B43=m | ||
| 638 | # CONFIG_B43_SDIO is not set | ||
| 639 | # CONFIG_B43_PHY_LP is not set | ||
| 640 | CONFIG_B43_HWRNG=y | ||
| 641 | # CONFIG_B43_DEBUG is not set | ||
| 642 | CONFIG_B43LEGACY=m | ||
| 643 | CONFIG_B43LEGACY_HWRNG=y | ||
| 644 | # CONFIG_B43LEGACY_DEBUG is not set | ||
| 645 | CONFIG_B43LEGACY_DMA=y | ||
| 646 | CONFIG_B43LEGACY_PIO=y | ||
| 647 | CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y | ||
| 648 | # CONFIG_B43LEGACY_DMA_MODE is not set | ||
| 649 | # CONFIG_B43LEGACY_PIO_MODE is not set | ||
| 650 | CONFIG_ZD1211RW=m | ||
| 651 | # CONFIG_ZD1211RW_DEBUG is not set | ||
| 652 | CONFIG_RT2X00=m | ||
| 653 | CONFIG_RT2500USB=m | ||
| 654 | CONFIG_RT73USB=m | ||
| 655 | CONFIG_RT2800USB=m | ||
| 656 | CONFIG_RT2X00_LIB_USB=m | ||
| 657 | CONFIG_RT2X00_LIB=m | ||
| 658 | CONFIG_RT2X00_LIB_HT=y | ||
| 659 | CONFIG_RT2X00_LIB_FIRMWARE=y | ||
| 660 | CONFIG_RT2X00_LIB_CRYPTO=y | ||
| 661 | # CONFIG_RT2X00_DEBUG is not set | ||
| 662 | CONFIG_WL12XX=m | ||
| 663 | # CONFIG_WL1251 is not set | ||
| 664 | # CONFIG_WL1271 is not set | ||
| 665 | # CONFIG_IWM is not set | 736 | # CONFIG_IWM is not set |
| 737 | CONFIG_LIBERTAS=y | ||
| 738 | # CONFIG_LIBERTAS_USB is not set | ||
| 739 | CONFIG_LIBERTAS_SDIO=y | ||
| 740 | # CONFIG_LIBERTAS_SPI is not set | ||
| 741 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 742 | # CONFIG_P54_COMMON is not set | ||
| 743 | # CONFIG_RT2X00 is not set | ||
| 744 | # CONFIG_WL12XX is not set | ||
| 745 | # CONFIG_ZD1211RW is not set | ||
| 666 | 746 | ||
| 667 | # | 747 | # |
| 668 | # Enable WiMAX (Networking options) to see the WiMAX drivers | 748 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| @@ -672,29 +752,10 @@ CONFIG_WL12XX=m | |||
| 672 | # USB Network Adapters | 752 | # USB Network Adapters |
| 673 | # | 753 | # |
| 674 | # CONFIG_USB_CATC is not set | 754 | # CONFIG_USB_CATC is not set |
| 675 | CONFIG_USB_KAWETH=m | 755 | # CONFIG_USB_KAWETH is not set |
| 676 | CONFIG_USB_PEGASUS=m | 756 | # CONFIG_USB_PEGASUS is not set |
| 677 | # CONFIG_USB_RTL8150 is not set | 757 | # CONFIG_USB_RTL8150 is not set |
| 678 | CONFIG_USB_USBNET=m | 758 | # CONFIG_USB_USBNET is not set |
| 679 | CONFIG_USB_NET_AX8817X=m | ||
| 680 | CONFIG_USB_NET_CDCETHER=m | ||
| 681 | CONFIG_USB_NET_CDC_EEM=m | ||
| 682 | CONFIG_USB_NET_DM9601=m | ||
| 683 | CONFIG_USB_NET_SMSC95XX=m | ||
| 684 | CONFIG_USB_NET_GL620A=m | ||
| 685 | CONFIG_USB_NET_NET1080=m | ||
| 686 | CONFIG_USB_NET_PLUSB=m | ||
| 687 | CONFIG_USB_NET_MCS7830=m | ||
| 688 | CONFIG_USB_NET_RNDIS_HOST=m | ||
| 689 | CONFIG_USB_NET_CDC_SUBSET=m | ||
| 690 | # CONFIG_USB_ALI_M5632 is not set | ||
| 691 | # CONFIG_USB_AN2720 is not set | ||
| 692 | CONFIG_USB_BELKIN=y | ||
| 693 | CONFIG_USB_ARMLINUX=y | ||
| 694 | # CONFIG_USB_EPSON2888 is not set | ||
| 695 | # CONFIG_USB_KC2190 is not set | ||
| 696 | CONFIG_USB_NET_ZAURUS=m | ||
| 697 | # CONFIG_USB_NET_INT51X1 is not set | ||
| 698 | # CONFIG_WAN is not set | 759 | # CONFIG_WAN is not set |
| 699 | # CONFIG_PPP is not set | 760 | # CONFIG_PPP is not set |
| 700 | # CONFIG_SLIP is not set | 761 | # CONFIG_SLIP is not set |
| @@ -710,6 +771,7 @@ CONFIG_USB_NET_ZAURUS=m | |||
| 710 | CONFIG_INPUT=y | 771 | CONFIG_INPUT=y |
| 711 | # CONFIG_INPUT_FF_MEMLESS is not set | 772 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 712 | # CONFIG_INPUT_POLLDEV is not set | 773 | # CONFIG_INPUT_POLLDEV is not set |
| 774 | # CONFIG_INPUT_SPARSEKMAP is not set | ||
| 713 | 775 | ||
| 714 | # | 776 | # |
| 715 | # Userland interfaces | 777 | # Userland interfaces |
| @@ -809,7 +871,6 @@ CONFIG_I2C_OMAP=y | |||
| 809 | # | 871 | # |
| 810 | # Miscellaneous I2C Chip support | 872 | # Miscellaneous I2C Chip support |
| 811 | # | 873 | # |
| 812 | # CONFIG_DS1682 is not set | ||
| 813 | # CONFIG_SENSORS_TSL2550 is not set | 874 | # CONFIG_SENSORS_TSL2550 is not set |
| 814 | # CONFIG_I2C_DEBUG_CORE is not set | 875 | # CONFIG_I2C_DEBUG_CORE is not set |
| 815 | # CONFIG_I2C_DEBUG_ALGO is not set | 876 | # CONFIG_I2C_DEBUG_ALGO is not set |
| @@ -825,6 +886,8 @@ CONFIG_SPI_MASTER=y | |||
| 825 | # CONFIG_SPI_BITBANG is not set | 886 | # CONFIG_SPI_BITBANG is not set |
| 826 | # CONFIG_SPI_GPIO is not set | 887 | # CONFIG_SPI_GPIO is not set |
| 827 | CONFIG_SPI_OMAP24XX=y | 888 | CONFIG_SPI_OMAP24XX=y |
| 889 | # CONFIG_SPI_XILINX is not set | ||
| 890 | # CONFIG_SPI_DESIGNWARE is not set | ||
| 828 | 891 | ||
| 829 | # | 892 | # |
| 830 | # SPI Protocol Masters | 893 | # SPI Protocol Masters |
| @@ -892,7 +955,7 @@ CONFIG_SSB_SDIOHOST_POSSIBLE=y | |||
| 892 | # | 955 | # |
| 893 | # Multifunction device drivers | 956 | # Multifunction device drivers |
| 894 | # | 957 | # |
| 895 | # CONFIG_MFD_CORE is not set | 958 | CONFIG_MFD_CORE=y |
| 896 | # CONFIG_MFD_SM501 is not set | 959 | # CONFIG_MFD_SM501 is not set |
| 897 | # CONFIG_MFD_ASIC3 is not set | 960 | # CONFIG_MFD_ASIC3 is not set |
| 898 | # CONFIG_HTC_EGPIO is not set | 961 | # CONFIG_HTC_EGPIO is not set |
| @@ -900,11 +963,13 @@ CONFIG_SSB_SDIOHOST_POSSIBLE=y | |||
| 900 | # CONFIG_TPS65010 is not set | 963 | # CONFIG_TPS65010 is not set |
| 901 | CONFIG_TWL4030_CORE=y | 964 | CONFIG_TWL4030_CORE=y |
| 902 | # CONFIG_TWL4030_POWER is not set | 965 | # CONFIG_TWL4030_POWER is not set |
| 966 | CONFIG_TWL4030_CODEC=y | ||
| 903 | # CONFIG_MFD_TMIO is not set | 967 | # CONFIG_MFD_TMIO is not set |
| 904 | # CONFIG_MFD_T7L66XB is not set | 968 | # CONFIG_MFD_T7L66XB is not set |
| 905 | # CONFIG_MFD_TC6387XB is not set | 969 | # CONFIG_MFD_TC6387XB is not set |
| 906 | # CONFIG_MFD_TC6393XB is not set | 970 | # CONFIG_MFD_TC6393XB is not set |
| 907 | # CONFIG_PMIC_DA903X is not set | 971 | # CONFIG_PMIC_DA903X is not set |
| 972 | # CONFIG_PMIC_ADP5520 is not set | ||
| 908 | # CONFIG_MFD_WM8400 is not set | 973 | # CONFIG_MFD_WM8400 is not set |
| 909 | # CONFIG_MFD_WM831X is not set | 974 | # CONFIG_MFD_WM831X is not set |
| 910 | # CONFIG_MFD_WM8350_I2C is not set | 975 | # CONFIG_MFD_WM8350_I2C is not set |
| @@ -912,6 +977,8 @@ CONFIG_TWL4030_CORE=y | |||
| 912 | # CONFIG_MFD_MC13783 is not set | 977 | # CONFIG_MFD_MC13783 is not set |
| 913 | # CONFIG_AB3100_CORE is not set | 978 | # CONFIG_AB3100_CORE is not set |
| 914 | # CONFIG_EZX_PCAP is not set | 979 | # CONFIG_EZX_PCAP is not set |
| 980 | # CONFIG_MFD_88PM8607 is not set | ||
| 981 | # CONFIG_AB4500_CORE is not set | ||
| 915 | CONFIG_REGULATOR=y | 982 | CONFIG_REGULATOR=y |
| 916 | # CONFIG_REGULATOR_DEBUG is not set | 983 | # CONFIG_REGULATOR_DEBUG is not set |
| 917 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | 984 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set |
| @@ -919,6 +986,7 @@ CONFIG_REGULATOR=y | |||
| 919 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | 986 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set |
| 920 | # CONFIG_REGULATOR_BQ24022 is not set | 987 | # CONFIG_REGULATOR_BQ24022 is not set |
| 921 | # CONFIG_REGULATOR_MAX1586 is not set | 988 | # CONFIG_REGULATOR_MAX1586 is not set |
| 989 | # CONFIG_REGULATOR_MAX8660 is not set | ||
| 922 | CONFIG_REGULATOR_TWL4030=y | 990 | CONFIG_REGULATOR_TWL4030=y |
| 923 | # CONFIG_REGULATOR_LP3971 is not set | 991 | # CONFIG_REGULATOR_LP3971 is not set |
| 924 | # CONFIG_REGULATOR_TPS65023 is not set | 992 | # CONFIG_REGULATOR_TPS65023 is not set |
| @@ -930,65 +998,129 @@ CONFIG_REGULATOR_TWL4030=y | |||
| 930 | # | 998 | # |
| 931 | # CONFIG_VGASTATE is not set | 999 | # CONFIG_VGASTATE is not set |
| 932 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | 1000 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set |
| 933 | # CONFIG_FB is not set | 1001 | CONFIG_FB=y |
| 1002 | # CONFIG_FIRMWARE_EDID is not set | ||
| 1003 | # CONFIG_FB_DDC is not set | ||
| 1004 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1005 | CONFIG_FB_CFB_FILLRECT=y | ||
| 1006 | CONFIG_FB_CFB_COPYAREA=y | ||
| 1007 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 1008 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 1009 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 1010 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 1011 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 1012 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 1013 | # CONFIG_FB_SYS_FOPS is not set | ||
| 1014 | # CONFIG_FB_SVGALIB is not set | ||
| 1015 | # CONFIG_FB_MACMODES is not set | ||
| 1016 | # CONFIG_FB_BACKLIGHT is not set | ||
| 1017 | CONFIG_FB_MODE_HELPERS=y | ||
| 1018 | # CONFIG_FB_TILEBLITTING is not set | ||
| 1019 | |||
| 1020 | # | ||
| 1021 | # Frame buffer hardware drivers | ||
| 1022 | # | ||
| 1023 | # CONFIG_FB_UVESA is not set | ||
| 1024 | # CONFIG_FB_S1D13XXX is not set | ||
| 1025 | # CONFIG_FB_TMIO is not set | ||
| 1026 | # CONFIG_FB_VIRTUAL is not set | ||
| 1027 | # CONFIG_FB_METRONOME is not set | ||
| 1028 | # CONFIG_FB_MB862XX is not set | ||
| 1029 | # CONFIG_FB_BROADSHEET is not set | ||
| 1030 | # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set | ||
| 1031 | CONFIG_OMAP2_VRAM=y | ||
| 1032 | CONFIG_OMAP2_VRFB=y | ||
| 1033 | CONFIG_OMAP2_DSS=y | ||
| 1034 | CONFIG_OMAP2_VRAM_SIZE=14 | ||
| 1035 | # CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set | ||
| 1036 | # CONFIG_OMAP2_DSS_RFBI is not set | ||
| 1037 | # CONFIG_OMAP2_DSS_VENC is not set | ||
| 1038 | # CONFIG_OMAP2_DSS_SDI is not set | ||
| 1039 | CONFIG_OMAP2_DSS_DSI=y | ||
| 1040 | CONFIG_OMAP2_DSS_USE_DSI_PLL=y | ||
| 1041 | # CONFIG_OMAP2_DSS_FAKE_VSYNC is not set | ||
| 1042 | CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 | ||
| 1043 | CONFIG_FB_OMAP2=y | ||
| 1044 | # CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set | ||
| 1045 | # CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set | ||
| 1046 | CONFIG_FB_OMAP2_NUM_FBS=3 | ||
| 1047 | |||
| 1048 | # | ||
| 1049 | # OMAP2/3 Display Device Drivers | ||
| 1050 | # | ||
| 1051 | CONFIG_PANEL_GENERIC=y | ||
| 1052 | # CONFIG_PANEL_SHARP_LS037V7DW01 is not set | ||
| 1053 | # CONFIG_PANEL_TAAL is not set | ||
| 934 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 1054 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 935 | 1055 | ||
| 936 | # | 1056 | # |
| 937 | # Display device support | 1057 | # Display device support |
| 938 | # | 1058 | # |
| 939 | # CONFIG_DISPLAY_SUPPORT is not set | 1059 | CONFIG_DISPLAY_SUPPORT=y |
| 1060 | |||
| 1061 | # | ||
| 1062 | # Display hardware drivers | ||
| 1063 | # | ||
| 940 | 1064 | ||
| 941 | # | 1065 | # |
| 942 | # Console display driver support | 1066 | # Console display driver support |
| 943 | # | 1067 | # |
| 944 | # CONFIG_VGA_CONSOLE is not set | 1068 | # CONFIG_VGA_CONSOLE is not set |
| 945 | CONFIG_DUMMY_CONSOLE=y | 1069 | CONFIG_DUMMY_CONSOLE=y |
| 946 | # CONFIG_SOUND is not set | 1070 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 947 | CONFIG_HID_SUPPORT=y | 1071 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set |
| 948 | CONFIG_HID=y | 1072 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set |
| 949 | # CONFIG_HIDRAW is not set | 1073 | # CONFIG_FONTS is not set |
| 950 | 1074 | CONFIG_FONT_8x8=y | |
| 951 | # | 1075 | CONFIG_FONT_8x16=y |
| 952 | # USB Input Devices | 1076 | CONFIG_LOGO=y |
| 953 | # | 1077 | # CONFIG_LOGO_LINUX_MONO is not set |
| 954 | CONFIG_USB_HID=y | 1078 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 955 | # CONFIG_HID_PID is not set | 1079 | CONFIG_LOGO_LINUX_CLUT224=y |
| 956 | # CONFIG_USB_HIDDEV is not set | 1080 | CONFIG_SOUND=y |
| 957 | 1081 | # CONFIG_SOUND_OSS_CORE is not set | |
| 958 | # | 1082 | CONFIG_SND=y |
| 959 | # Special HID drivers | 1083 | CONFIG_SND_TIMER=y |
| 960 | # | 1084 | CONFIG_SND_PCM=y |
| 961 | # CONFIG_HID_A4TECH is not set | 1085 | CONFIG_SND_JACK=y |
| 962 | # CONFIG_HID_APPLE is not set | 1086 | # CONFIG_SND_SEQUENCER is not set |
| 963 | # CONFIG_HID_BELKIN is not set | 1087 | # CONFIG_SND_MIXER_OSS is not set |
| 964 | # CONFIG_HID_CHERRY is not set | 1088 | # CONFIG_SND_PCM_OSS is not set |
| 965 | # CONFIG_HID_CHICONY is not set | 1089 | # CONFIG_SND_HRTIMER is not set |
| 966 | # CONFIG_HID_CYPRESS is not set | 1090 | # CONFIG_SND_DYNAMIC_MINORS is not set |
| 967 | # CONFIG_HID_DRAGONRISE is not set | 1091 | # CONFIG_SND_SUPPORT_OLD_API is not set |
| 968 | # CONFIG_HID_EZKEY is not set | 1092 | # CONFIG_SND_VERBOSE_PROCFS is not set |
| 969 | # CONFIG_HID_KYE is not set | 1093 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 970 | # CONFIG_HID_GYRATION is not set | 1094 | # CONFIG_SND_DEBUG is not set |
| 971 | # CONFIG_HID_TWINHAN is not set | 1095 | # CONFIG_SND_RAWMIDI_SEQ is not set |
| 972 | # CONFIG_HID_KENSINGTON is not set | 1096 | # CONFIG_SND_OPL3_LIB_SEQ is not set |
| 973 | # CONFIG_HID_LOGITECH is not set | 1097 | # CONFIG_SND_OPL4_LIB_SEQ is not set |
| 974 | # CONFIG_HID_MICROSOFT is not set | 1098 | # CONFIG_SND_SBAWE_SEQ is not set |
| 975 | # CONFIG_HID_MONTEREY is not set | 1099 | # CONFIG_SND_EMU10K1_SEQ is not set |
| 976 | # CONFIG_HID_NTRIG is not set | 1100 | CONFIG_SND_DRIVERS=y |
| 977 | # CONFIG_HID_PANTHERLORD is not set | 1101 | # CONFIG_SND_DUMMY is not set |
| 978 | # CONFIG_HID_PETALYNX is not set | 1102 | # CONFIG_SND_MTPAV is not set |
| 979 | # CONFIG_HID_SAMSUNG is not set | 1103 | # CONFIG_SND_SERIAL_U16550 is not set |
| 980 | # CONFIG_HID_SONY is not set | 1104 | # CONFIG_SND_MPU401 is not set |
| 981 | # CONFIG_HID_SUNPLUS is not set | 1105 | CONFIG_SND_ARM=y |
| 982 | # CONFIG_HID_GREENASIA is not set | 1106 | CONFIG_SND_SPI=y |
| 983 | # CONFIG_HID_SMARTJOYPLUS is not set | 1107 | CONFIG_SND_USB=y |
| 984 | # CONFIG_HID_TOPSEED is not set | 1108 | # CONFIG_SND_USB_AUDIO is not set |
| 985 | # CONFIG_HID_THRUSTMASTER is not set | 1109 | # CONFIG_SND_USB_CAIAQ is not set |
| 986 | # CONFIG_HID_WACOM is not set | 1110 | CONFIG_SND_SOC=y |
| 987 | # CONFIG_HID_ZEROPLUS is not set | 1111 | CONFIG_SND_OMAP_SOC=y |
| 1112 | CONFIG_SND_OMAP_SOC_MCBSP=y | ||
| 1113 | CONFIG_SND_OMAP_SOC_IGEP0020=y | ||
| 1114 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1115 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1116 | CONFIG_SND_SOC_TWL4030=y | ||
| 1117 | # CONFIG_SOUND_PRIME is not set | ||
| 1118 | # CONFIG_HID_SUPPORT is not set | ||
| 1119 | CONFIG_HID=m | ||
| 988 | CONFIG_USB_SUPPORT=y | 1120 | CONFIG_USB_SUPPORT=y |
| 989 | CONFIG_USB_ARCH_HAS_HCD=y | 1121 | CONFIG_USB_ARCH_HAS_HCD=y |
| 990 | CONFIG_USB_ARCH_HAS_OHCI=y | 1122 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 991 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1123 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 992 | CONFIG_USB=y | 1124 | CONFIG_USB=y |
| 993 | # CONFIG_USB_DEBUG is not set | 1125 | # CONFIG_USB_DEBUG is not set |
| 994 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 1126 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| @@ -997,12 +1129,12 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | |||
| 997 | # Miscellaneous USB options | 1129 | # Miscellaneous USB options |
| 998 | # | 1130 | # |
| 999 | # CONFIG_USB_DEVICEFS is not set | 1131 | # CONFIG_USB_DEVICEFS is not set |
| 1000 | # CONFIG_USB_DEVICE_CLASS is not set | 1132 | CONFIG_USB_DEVICE_CLASS=y |
| 1001 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1133 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1002 | # CONFIG_USB_OTG is not set | 1134 | # CONFIG_USB_OTG is not set |
| 1003 | # CONFIG_USB_OTG_WHITELIST is not set | 1135 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1004 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | 1136 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set |
| 1005 | CONFIG_USB_MON=m | 1137 | # CONFIG_USB_MON is not set |
| 1006 | # CONFIG_USB_WUSB is not set | 1138 | # CONFIG_USB_WUSB is not set |
| 1007 | # CONFIG_USB_WUSB_CBAF is not set | 1139 | # CONFIG_USB_WUSB_CBAF is not set |
| 1008 | 1140 | ||
| @@ -1010,29 +1142,21 @@ CONFIG_USB_MON=m | |||
| 1010 | # USB Host Controller Drivers | 1142 | # USB Host Controller Drivers |
| 1011 | # | 1143 | # |
| 1012 | # CONFIG_USB_C67X00_HCD is not set | 1144 | # CONFIG_USB_C67X00_HCD is not set |
| 1145 | CONFIG_USB_EHCI_HCD=y | ||
| 1146 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 1147 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | ||
| 1013 | # CONFIG_USB_OXU210HP_HCD is not set | 1148 | # CONFIG_USB_OXU210HP_HCD is not set |
| 1014 | # CONFIG_USB_ISP116X_HCD is not set | 1149 | # CONFIG_USB_ISP116X_HCD is not set |
| 1015 | # CONFIG_USB_ISP1760_HCD is not set | 1150 | # CONFIG_USB_ISP1760_HCD is not set |
| 1016 | # CONFIG_USB_ISP1362_HCD is not set | 1151 | # CONFIG_USB_ISP1362_HCD is not set |
| 1017 | # CONFIG_USB_OHCI_HCD is not set | 1152 | CONFIG_USB_OHCI_HCD=y |
| 1153 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 1154 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 1155 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 1018 | # CONFIG_USB_SL811_HCD is not set | 1156 | # CONFIG_USB_SL811_HCD is not set |
| 1019 | # CONFIG_USB_R8A66597_HCD is not set | 1157 | # CONFIG_USB_R8A66597_HCD is not set |
| 1020 | # CONFIG_USB_HWA_HCD is not set | 1158 | # CONFIG_USB_HWA_HCD is not set |
| 1021 | CONFIG_USB_MUSB_HDRC=y | 1159 | # CONFIG_USB_MUSB_HDRC is not set |
| 1022 | CONFIG_USB_MUSB_SOC=y | ||
| 1023 | |||
| 1024 | # | ||
| 1025 | # OMAP 343x high speed USB support | ||
| 1026 | # | ||
| 1027 | CONFIG_USB_MUSB_HOST=y | ||
| 1028 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 1029 | # CONFIG_USB_MUSB_OTG is not set | ||
| 1030 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1031 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 1032 | # CONFIG_MUSB_PIO_ONLY is not set | ||
| 1033 | CONFIG_USB_INVENTRA_DMA=y | ||
| 1034 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1035 | # CONFIG_USB_MUSB_DEBUG is not set | ||
| 1036 | 1160 | ||
| 1037 | # | 1161 | # |
| 1038 | # USB Device Class drivers | 1162 | # USB Device Class drivers |
| @@ -1049,19 +1173,7 @@ CONFIG_USB_INVENTRA_DMA=y | |||
| 1049 | # | 1173 | # |
| 1050 | # also be needed; see USB_STORAGE Help for more info | 1174 | # also be needed; see USB_STORAGE Help for more info |
| 1051 | # | 1175 | # |
| 1052 | CONFIG_USB_STORAGE=m | 1176 | # CONFIG_USB_STORAGE is not set |
| 1053 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1054 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1055 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1056 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1057 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1058 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1059 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1060 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1061 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1062 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1063 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1064 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1065 | # CONFIG_USB_LIBUSUAL is not set | 1177 | # CONFIG_USB_LIBUSUAL is not set |
| 1066 | 1178 | ||
| 1067 | # | 1179 | # |
| @@ -1099,41 +1211,7 @@ CONFIG_USB_STORAGE=m | |||
| 1099 | # CONFIG_USB_TEST is not set | 1211 | # CONFIG_USB_TEST is not set |
| 1100 | # CONFIG_USB_ISIGHTFW is not set | 1212 | # CONFIG_USB_ISIGHTFW is not set |
| 1101 | # CONFIG_USB_VST is not set | 1213 | # CONFIG_USB_VST is not set |
| 1102 | CONFIG_USB_GADGET=y | 1214 | # CONFIG_USB_GADGET is not set |
| 1103 | CONFIG_USB_GADGET_DEBUG=y | ||
| 1104 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 1105 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1106 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1107 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1108 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1109 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1110 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1111 | CONFIG_USB_GADGET_OMAP=y | ||
| 1112 | CONFIG_USB_OMAP=y | ||
| 1113 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1114 | # CONFIG_USB_GADGET_R8A66597 is not set | ||
| 1115 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1116 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
| 1117 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1118 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1119 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1120 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1121 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1122 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1123 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1124 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1125 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 1126 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1127 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 1128 | CONFIG_USB_ZERO=m | ||
| 1129 | # CONFIG_USB_AUDIO is not set | ||
| 1130 | # CONFIG_USB_ETH is not set | ||
| 1131 | # CONFIG_USB_GADGETFS is not set | ||
| 1132 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1133 | # CONFIG_USB_G_SERIAL is not set | ||
| 1134 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1135 | # CONFIG_USB_G_PRINTER is not set | ||
| 1136 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1137 | 1215 | ||
| 1138 | # | 1216 | # |
| 1139 | # OTG and related infrastructure | 1217 | # OTG and related infrastructure |
| @@ -1141,10 +1219,11 @@ CONFIG_USB_ZERO=m | |||
| 1141 | CONFIG_USB_OTG_UTILS=y | 1219 | CONFIG_USB_OTG_UTILS=y |
| 1142 | # CONFIG_USB_GPIO_VBUS is not set | 1220 | # CONFIG_USB_GPIO_VBUS is not set |
| 1143 | # CONFIG_ISP1301_OMAP is not set | 1221 | # CONFIG_ISP1301_OMAP is not set |
| 1144 | CONFIG_TWL4030_USB=y | 1222 | # CONFIG_USB_ULPI is not set |
| 1223 | # CONFIG_TWL4030_USB is not set | ||
| 1145 | # CONFIG_NOP_USB_XCEIV is not set | 1224 | # CONFIG_NOP_USB_XCEIV is not set |
| 1146 | CONFIG_MMC=y | 1225 | CONFIG_MMC=y |
| 1147 | # CONFIG_MMC_DEBUG is not set | 1226 | CONFIG_MMC_DEBUG=y |
| 1148 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1227 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1149 | 1228 | ||
| 1150 | # | 1229 | # |
| @@ -1158,7 +1237,8 @@ CONFIG_MMC_BLOCK_BOUNCE=y | |||
| 1158 | # | 1237 | # |
| 1159 | # MMC/SD/SDIO Host Controller Drivers | 1238 | # MMC/SD/SDIO Host Controller Drivers |
| 1160 | # | 1239 | # |
| 1161 | # CONFIG_MMC_SDHCI is not set | 1240 | CONFIG_MMC_SDHCI=y |
| 1241 | # CONFIG_MMC_SDHCI_PLTFM is not set | ||
| 1162 | # CONFIG_MMC_OMAP is not set | 1242 | # CONFIG_MMC_OMAP is not set |
| 1163 | CONFIG_MMC_OMAP_HS=y | 1243 | CONFIG_MMC_OMAP_HS=y |
| 1164 | # CONFIG_MMC_AT91 is not set | 1244 | # CONFIG_MMC_AT91 is not set |
| @@ -1179,6 +1259,11 @@ CONFIG_RTC_LIB=y | |||
| 1179 | # CONFIG_STAGING is not set | 1259 | # CONFIG_STAGING is not set |
| 1180 | 1260 | ||
| 1181 | # | 1261 | # |
| 1262 | # CBUS support | ||
| 1263 | # | ||
| 1264 | # CONFIG_CBUS is not set | ||
| 1265 | |||
| 1266 | # | ||
| 1182 | # File systems | 1267 | # File systems |
| 1183 | # | 1268 | # |
| 1184 | CONFIG_EXT2_FS=y | 1269 | CONFIG_EXT2_FS=y |
| @@ -1253,6 +1338,7 @@ CONFIG_MISC_FILESYSTEMS=y | |||
| 1253 | # CONFIG_BEFS_FS is not set | 1338 | # CONFIG_BEFS_FS is not set |
| 1254 | # CONFIG_BFS_FS is not set | 1339 | # CONFIG_BFS_FS is not set |
| 1255 | # CONFIG_EFS_FS is not set | 1340 | # CONFIG_EFS_FS is not set |
| 1341 | # CONFIG_JFFS2_FS is not set | ||
| 1256 | # CONFIG_CRAMFS is not set | 1342 | # CONFIG_CRAMFS is not set |
| 1257 | # CONFIG_SQUASHFS is not set | 1343 | # CONFIG_SQUASHFS is not set |
| 1258 | # CONFIG_VXFS_FS is not set | 1344 | # CONFIG_VXFS_FS is not set |
| @@ -1401,6 +1487,7 @@ CONFIG_DEBUG_INFO=y | |||
| 1401 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | 1487 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set |
| 1402 | # CONFIG_FAULT_INJECTION is not set | 1488 | # CONFIG_FAULT_INJECTION is not set |
| 1403 | # CONFIG_LATENCYTOP is not set | 1489 | # CONFIG_LATENCYTOP is not set |
| 1490 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1404 | # CONFIG_PAGE_POISONING is not set | 1491 | # CONFIG_PAGE_POISONING is not set |
| 1405 | CONFIG_HAVE_FUNCTION_TRACER=y | 1492 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1406 | CONFIG_TRACING_SUPPORT=y | 1493 | CONFIG_TRACING_SUPPORT=y |
| @@ -1425,7 +1512,9 @@ CONFIG_ARM_UNWIND=y | |||
| 1425 | # CONFIG_DEBUG_ERRORS is not set | 1512 | # CONFIG_DEBUG_ERRORS is not set |
| 1426 | # CONFIG_DEBUG_STACK_USAGE is not set | 1513 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1427 | CONFIG_DEBUG_LL=y | 1514 | CONFIG_DEBUG_LL=y |
| 1515 | # CONFIG_EARLY_PRINTK is not set | ||
| 1428 | # CONFIG_DEBUG_ICEDCC is not set | 1516 | # CONFIG_DEBUG_ICEDCC is not set |
| 1517 | # CONFIG_OC_ETM is not set | ||
| 1429 | 1518 | ||
| 1430 | # | 1519 | # |
| 1431 | # Security options | 1520 | # Security options |
| @@ -1433,7 +1522,11 @@ CONFIG_DEBUG_LL=y | |||
| 1433 | # CONFIG_KEYS is not set | 1522 | # CONFIG_KEYS is not set |
| 1434 | # CONFIG_SECURITY is not set | 1523 | # CONFIG_SECURITY is not set |
| 1435 | # CONFIG_SECURITYFS is not set | 1524 | # CONFIG_SECURITYFS is not set |
| 1436 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1525 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set |
| 1526 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
| 1527 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
| 1528 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
| 1529 | CONFIG_DEFAULT_SECURITY="" | ||
| 1437 | CONFIG_CRYPTO=y | 1530 | CONFIG_CRYPTO=y |
| 1438 | 1531 | ||
| 1439 | # | 1532 | # |
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig index 367be98a6aef..714835e5ebec 100644 --- a/arch/arm/configs/omap3_defconfig +++ b/arch/arm/configs/omap3_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.32-rc8 | 3 | # Linux kernel version: 2.6.33-rc5 |
| 4 | # Tue Dec 1 14:04:02 2009 | 4 | # Tue Jan 26 11:05:31 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -20,6 +20,8 @@ CONFIG_ARCH_HAS_CPUFREQ=y | |||
| 20 | CONFIG_GENERIC_HWEIGHT=y | 20 | CONFIG_GENERIC_HWEIGHT=y |
| 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 23 | CONFIG_OPROFILE_ARMV6=y | ||
| 24 | CONFIG_OPROFILE_ARM11_CORE=y | ||
| 23 | CONFIG_OPROFILE_ARMV7=y | 25 | CONFIG_OPROFILE_ARMV7=y |
| 24 | CONFIG_VECTORS_BASE=0xffff0000 | 26 | CONFIG_VECTORS_BASE=0xffff0000 |
| 25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| @@ -33,6 +35,12 @@ CONFIG_BROKEN_ON_SMP=y | |||
| 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 34 | CONFIG_LOCALVERSION="" | 36 | CONFIG_LOCALVERSION="" |
| 35 | CONFIG_LOCALVERSION_AUTO=y | 37 | CONFIG_LOCALVERSION_AUTO=y |
| 38 | CONFIG_HAVE_KERNEL_GZIP=y | ||
| 39 | CONFIG_HAVE_KERNEL_LZO=y | ||
| 40 | CONFIG_KERNEL_GZIP=y | ||
| 41 | # CONFIG_KERNEL_BZIP2 is not set | ||
| 42 | # CONFIG_KERNEL_LZMA is not set | ||
| 43 | # CONFIG_KERNEL_LZO is not set | ||
| 36 | CONFIG_SWAP=y | 44 | CONFIG_SWAP=y |
| 37 | CONFIG_SYSVIPC=y | 45 | CONFIG_SYSVIPC=y |
| 38 | CONFIG_SYSVIPC_SYSCTL=y | 46 | CONFIG_SYSVIPC_SYSCTL=y |
| @@ -48,6 +56,7 @@ CONFIG_BSD_PROCESS_ACCT=y | |||
| 48 | # | 56 | # |
| 49 | CONFIG_TREE_RCU=y | 57 | CONFIG_TREE_RCU=y |
| 50 | # CONFIG_TREE_PREEMPT_RCU is not set | 58 | # CONFIG_TREE_PREEMPT_RCU is not set |
| 59 | # CONFIG_TINY_RCU is not set | ||
| 51 | # CONFIG_RCU_TRACE is not set | 60 | # CONFIG_RCU_TRACE is not set |
| 52 | CONFIG_RCU_FANOUT=32 | 61 | CONFIG_RCU_FANOUT=32 |
| 53 | # CONFIG_RCU_FANOUT_EXACT is not set | 62 | # CONFIG_RCU_FANOUT_EXACT is not set |
| @@ -69,6 +78,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 69 | CONFIG_RD_GZIP=y | 78 | CONFIG_RD_GZIP=y |
| 70 | # CONFIG_RD_BZIP2 is not set | 79 | # CONFIG_RD_BZIP2 is not set |
| 71 | # CONFIG_RD_LZMA is not set | 80 | # CONFIG_RD_LZMA is not set |
| 81 | # CONFIG_RD_LZO is not set | ||
| 72 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 82 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 73 | CONFIG_SYSCTL=y | 83 | CONFIG_SYSCTL=y |
| 74 | CONFIG_ANON_INODES=y | 84 | CONFIG_ANON_INODES=y |
| @@ -133,14 +143,41 @@ CONFIG_LBDAF=y | |||
| 133 | # IO Schedulers | 143 | # IO Schedulers |
| 134 | # | 144 | # |
| 135 | CONFIG_IOSCHED_NOOP=y | 145 | CONFIG_IOSCHED_NOOP=y |
| 136 | CONFIG_IOSCHED_AS=y | ||
| 137 | CONFIG_IOSCHED_DEADLINE=y | 146 | CONFIG_IOSCHED_DEADLINE=y |
| 138 | CONFIG_IOSCHED_CFQ=y | 147 | CONFIG_IOSCHED_CFQ=y |
| 139 | # CONFIG_DEFAULT_AS is not set | ||
| 140 | # CONFIG_DEFAULT_DEADLINE is not set | 148 | # CONFIG_DEFAULT_DEADLINE is not set |
| 141 | CONFIG_DEFAULT_CFQ=y | 149 | CONFIG_DEFAULT_CFQ=y |
| 142 | # CONFIG_DEFAULT_NOOP is not set | 150 | # CONFIG_DEFAULT_NOOP is not set |
| 143 | CONFIG_DEFAULT_IOSCHED="cfq" | 151 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 152 | # CONFIG_INLINE_SPIN_TRYLOCK is not set | ||
| 153 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
| 154 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
| 155 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
| 156 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
| 157 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
| 158 | # CONFIG_INLINE_SPIN_UNLOCK is not set | ||
| 159 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
| 160 | # CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set | ||
| 161 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
| 162 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
| 163 | # CONFIG_INLINE_READ_LOCK is not set | ||
| 164 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
| 165 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
| 166 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
| 167 | # CONFIG_INLINE_READ_UNLOCK is not set | ||
| 168 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
| 169 | # CONFIG_INLINE_READ_UNLOCK_IRQ is not set | ||
| 170 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
| 171 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
| 172 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
| 173 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
| 174 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
| 175 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
| 176 | # CONFIG_INLINE_WRITE_UNLOCK is not set | ||
| 177 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
| 178 | # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set | ||
| 179 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
| 180 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
| 144 | CONFIG_FREEZER=y | 181 | CONFIG_FREEZER=y |
| 145 | 182 | ||
| 146 | # | 183 | # |
| @@ -169,6 +206,7 @@ CONFIG_MMU=y | |||
| 169 | # CONFIG_ARCH_IXP2000 is not set | 206 | # CONFIG_ARCH_IXP2000 is not set |
| 170 | # CONFIG_ARCH_IXP4XX is not set | 207 | # CONFIG_ARCH_IXP4XX is not set |
| 171 | # CONFIG_ARCH_L7200 is not set | 208 | # CONFIG_ARCH_L7200 is not set |
| 209 | # CONFIG_ARCH_DOVE is not set | ||
| 172 | # CONFIG_ARCH_KIRKWOOD is not set | 210 | # CONFIG_ARCH_KIRKWOOD is not set |
| 173 | # CONFIG_ARCH_LOKI is not set | 211 | # CONFIG_ARCH_LOKI is not set |
| 174 | # CONFIG_ARCH_MV78XX0 is not set | 212 | # CONFIG_ARCH_MV78XX0 is not set |
| @@ -191,21 +229,23 @@ CONFIG_MMU=y | |||
| 191 | # CONFIG_ARCH_DAVINCI is not set | 229 | # CONFIG_ARCH_DAVINCI is not set |
| 192 | CONFIG_ARCH_OMAP=y | 230 | CONFIG_ARCH_OMAP=y |
| 193 | # CONFIG_ARCH_BCMRING is not set | 231 | # CONFIG_ARCH_BCMRING is not set |
| 232 | # CONFIG_ARCH_U8500 is not set | ||
| 194 | 233 | ||
| 195 | # | 234 | # |
| 196 | # TI OMAP Implementations | 235 | # TI OMAP Implementations |
| 197 | # | 236 | # |
| 198 | CONFIG_ARCH_OMAP_OTG=y | 237 | CONFIG_ARCH_OMAP_OTG=y |
| 199 | # CONFIG_ARCH_OMAP1 is not set | 238 | # CONFIG_ARCH_OMAP1 is not set |
| 200 | # CONFIG_ARCH_OMAP2 is not set | 239 | CONFIG_ARCH_OMAP2PLUS=y |
| 240 | CONFIG_ARCH_OMAP2=y | ||
| 201 | CONFIG_ARCH_OMAP3=y | 241 | CONFIG_ARCH_OMAP3=y |
| 202 | # CONFIG_ARCH_OMAP4 is not set | 242 | CONFIG_ARCH_OMAP4=y |
| 203 | 243 | ||
| 204 | # | 244 | # |
| 205 | # OMAP Feature Selections | 245 | # OMAP Feature Selections |
| 206 | # | 246 | # |
| 207 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | 247 | CONFIG_OMAP_DEBUG_DEVICES=y |
| 208 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | 248 | CONFIG_OMAP_DEBUG_LEDS=y |
| 209 | CONFIG_OMAP_RESET_CLOCKS=y | 249 | CONFIG_OMAP_RESET_CLOCKS=y |
| 210 | CONFIG_OMAP_MUX=y | 250 | CONFIG_OMAP_MUX=y |
| 211 | CONFIG_OMAP_MUX_DEBUG=y | 251 | CONFIG_OMAP_MUX_DEBUG=y |
| @@ -216,43 +256,66 @@ CONFIG_OMAP_MCBSP=y | |||
| 216 | CONFIG_OMAP_32K_TIMER=y | 256 | CONFIG_OMAP_32K_TIMER=y |
| 217 | CONFIG_OMAP_32K_TIMER_HZ=128 | 257 | CONFIG_OMAP_32K_TIMER_HZ=128 |
| 218 | CONFIG_OMAP_DM_TIMER=y | 258 | CONFIG_OMAP_DM_TIMER=y |
| 219 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
| 220 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
| 221 | # CONFIG_OMAP_LL_DEBUG_UART3 is not set | ||
| 222 | CONFIG_OMAP_LL_DEBUG_NONE=y | ||
| 223 | # CONFIG_OMAP_PM_NONE is not set | 259 | # CONFIG_OMAP_PM_NONE is not set |
| 224 | CONFIG_OMAP_PM_NOOP=y | 260 | CONFIG_OMAP_PM_NOOP=y |
| 225 | CONFIG_ARCH_OMAP34XX=y | 261 | CONFIG_MACH_OMAP_GENERIC=y |
| 262 | |||
| 263 | # | ||
| 264 | # OMAP Core Type | ||
| 265 | # | ||
| 266 | CONFIG_ARCH_OMAP2420=y | ||
| 267 | # CONFIG_ARCH_OMAP2430 is not set | ||
| 226 | CONFIG_ARCH_OMAP3430=y | 268 | CONFIG_ARCH_OMAP3430=y |
| 269 | CONFIG_OMAP_PACKAGE_CBB=y | ||
| 270 | CONFIG_OMAP_PACKAGE_CUS=y | ||
| 271 | CONFIG_OMAP_PACKAGE_CBP=y | ||
| 227 | 272 | ||
| 228 | # | 273 | # |
| 229 | # OMAP Board Type | 274 | # OMAP Board Type |
| 230 | # | 275 | # |
| 276 | CONFIG_MACH_OMAP2_TUSB6010=y | ||
| 277 | CONFIG_MACH_OMAP_H4=y | ||
| 278 | CONFIG_MACH_OMAP_APOLLON=y | ||
| 279 | # CONFIG_MACH_OMAP_2430SDP is not set | ||
| 231 | CONFIG_MACH_OMAP3_BEAGLE=y | 280 | CONFIG_MACH_OMAP3_BEAGLE=y |
| 232 | CONFIG_MACH_OMAP_LDP=y | 281 | CONFIG_MACH_OMAP_LDP=y |
| 233 | CONFIG_MACH_OVERO=y | 282 | CONFIG_MACH_OVERO=y |
| 234 | CONFIG_MACH_OMAP3EVM=y | 283 | CONFIG_MACH_OMAP3EVM=y |
| 235 | CONFIG_MACH_OMAP3517EVM=y | 284 | CONFIG_MACH_OMAP3517EVM=y |
| 236 | CONFIG_MACH_OMAP3_PANDORA=y | 285 | CONFIG_MACH_OMAP3_PANDORA=y |
| 286 | CONFIG_MACH_OMAP3_TOUCHBOOK=y | ||
| 237 | CONFIG_MACH_OMAP_3430SDP=y | 287 | CONFIG_MACH_OMAP_3430SDP=y |
| 288 | CONFIG_MACH_NOKIA_N800=y | ||
| 289 | CONFIG_MACH_NOKIA_N810=y | ||
| 290 | CONFIG_MACH_NOKIA_N810_WIMAX=y | ||
| 291 | CONFIG_MACH_NOKIA_N8X0=y | ||
| 238 | CONFIG_MACH_NOKIA_RX51=y | 292 | CONFIG_MACH_NOKIA_RX51=y |
| 239 | CONFIG_MACH_OMAP_ZOOM2=y | 293 | CONFIG_MACH_OMAP_ZOOM2=y |
| 240 | CONFIG_MACH_OMAP_ZOOM3=y | 294 | CONFIG_MACH_OMAP_ZOOM3=y |
| 241 | CONFIG_MACH_CM_T35=y | 295 | CONFIG_MACH_CM_T35=y |
| 242 | CONFIG_MACH_IGEP0020=y | 296 | CONFIG_MACH_IGEP0020=y |
| 243 | CONFIG_MACH_OMAP_3630SDP=y | 297 | CONFIG_MACH_OMAP_3630SDP=y |
| 298 | CONFIG_MACH_OMAP_4430SDP=y | ||
| 299 | # CONFIG_OMAP3_EMU is not set | ||
| 300 | # CONFIG_OMAP3_SDRC_AC_TIMING is not set | ||
| 244 | 301 | ||
| 245 | # | 302 | # |
| 246 | # Processor Type | 303 | # Processor Type |
| 247 | # | 304 | # |
| 248 | CONFIG_CPU_32v6K=y | 305 | CONFIG_CPU_V6=y |
| 306 | # CONFIG_CPU_32v6K is not set | ||
| 249 | CONFIG_CPU_V7=y | 307 | CONFIG_CPU_V7=y |
| 308 | CONFIG_CPU_32v6=y | ||
| 250 | CONFIG_CPU_32v7=y | 309 | CONFIG_CPU_32v7=y |
| 310 | CONFIG_CPU_ABRT_EV6=y | ||
| 251 | CONFIG_CPU_ABRT_EV7=y | 311 | CONFIG_CPU_ABRT_EV7=y |
| 312 | CONFIG_CPU_PABRT_V6=y | ||
| 252 | CONFIG_CPU_PABRT_V7=y | 313 | CONFIG_CPU_PABRT_V7=y |
| 314 | CONFIG_CPU_CACHE_V6=y | ||
| 253 | CONFIG_CPU_CACHE_V7=y | 315 | CONFIG_CPU_CACHE_V7=y |
| 254 | CONFIG_CPU_CACHE_VIPT=y | 316 | CONFIG_CPU_CACHE_VIPT=y |
| 255 | CONFIG_CPU_COPY_V6=y | 317 | CONFIG_CPU_COPY_V6=y |
| 318 | CONFIG_CPU_TLB_V6=y | ||
| 256 | CONFIG_CPU_TLB_V7=y | 319 | CONFIG_CPU_TLB_V7=y |
| 257 | CONFIG_CPU_HAS_ASID=y | 320 | CONFIG_CPU_HAS_ASID=y |
| 258 | CONFIG_CPU_CP15=y | 321 | CONFIG_CPU_CP15=y |
| @@ -268,9 +331,11 @@ CONFIG_ARM_THUMBEE=y | |||
| 268 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 331 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 269 | CONFIG_HAS_TLS_REG=y | 332 | CONFIG_HAS_TLS_REG=y |
| 270 | CONFIG_ARM_L1_CACHE_SHIFT=6 | 333 | CONFIG_ARM_L1_CACHE_SHIFT=6 |
| 334 | # CONFIG_ARM_ERRATA_411920 is not set | ||
| 271 | # CONFIG_ARM_ERRATA_430973 is not set | 335 | # CONFIG_ARM_ERRATA_430973 is not set |
| 272 | # CONFIG_ARM_ERRATA_458693 is not set | 336 | # CONFIG_ARM_ERRATA_458693 is not set |
| 273 | # CONFIG_ARM_ERRATA_460075 is not set | 337 | # CONFIG_ARM_ERRATA_460075 is not set |
| 338 | CONFIG_ARM_GIC=y | ||
| 274 | CONFIG_COMMON_CLKDEV=y | 339 | CONFIG_COMMON_CLKDEV=y |
| 275 | 340 | ||
| 276 | # | 341 | # |
| @@ -287,6 +352,7 @@ CONFIG_TICK_ONESHOT=y | |||
| 287 | CONFIG_NO_HZ=y | 352 | CONFIG_NO_HZ=y |
| 288 | CONFIG_HIGH_RES_TIMERS=y | 353 | CONFIG_HIGH_RES_TIMERS=y |
| 289 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 354 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 355 | # CONFIG_SMP is not set | ||
| 290 | CONFIG_VMSPLIT_3G=y | 356 | CONFIG_VMSPLIT_3G=y |
| 291 | # CONFIG_VMSPLIT_2G is not set | 357 | # CONFIG_VMSPLIT_2G is not set |
| 292 | # CONFIG_VMSPLIT_1G is not set | 358 | # CONFIG_VMSPLIT_1G is not set |
| @@ -298,6 +364,7 @@ CONFIG_HZ=128 | |||
| 298 | # CONFIG_THUMB2_KERNEL is not set | 364 | # CONFIG_THUMB2_KERNEL is not set |
| 299 | CONFIG_AEABI=y | 365 | CONFIG_AEABI=y |
| 300 | CONFIG_OABI_COMPAT=y | 366 | CONFIG_OABI_COMPAT=y |
| 367 | CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y | ||
| 301 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | 368 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
| 302 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | 369 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set |
| 303 | # CONFIG_HIGHMEM is not set | 370 | # CONFIG_HIGHMEM is not set |
| @@ -308,12 +375,10 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 308 | CONFIG_FLATMEM=y | 375 | CONFIG_FLATMEM=y |
| 309 | CONFIG_FLAT_NODE_MEM_MAP=y | 376 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 310 | CONFIG_PAGEFLAGS_EXTENDED=y | 377 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 311 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 378 | CONFIG_SPLIT_PTLOCK_CPUS=999999 |
| 312 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 379 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 313 | CONFIG_ZONE_DMA_FLAG=0 | 380 | CONFIG_ZONE_DMA_FLAG=0 |
| 314 | CONFIG_VIRT_TO_BUS=y | 381 | CONFIG_VIRT_TO_BUS=y |
| 315 | CONFIG_HAVE_MLOCK=y | ||
| 316 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 317 | # CONFIG_KSM is not set | 382 | # CONFIG_KSM is not set |
| 318 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | 383 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 |
| 319 | CONFIG_LEDS=y | 384 | CONFIG_LEDS=y |
| @@ -509,15 +574,18 @@ CONFIG_BT_HCIBPA10X=y | |||
| 509 | # CONFIG_BT_MRVL is not set | 574 | # CONFIG_BT_MRVL is not set |
| 510 | # CONFIG_AF_RXRPC is not set | 575 | # CONFIG_AF_RXRPC is not set |
| 511 | CONFIG_WIRELESS=y | 576 | CONFIG_WIRELESS=y |
| 577 | CONFIG_WIRELESS_EXT=y | ||
| 578 | CONFIG_WEXT_CORE=y | ||
| 579 | CONFIG_WEXT_PROC=y | ||
| 580 | CONFIG_WEXT_SPY=y | ||
| 512 | CONFIG_CFG80211=y | 581 | CONFIG_CFG80211=y |
| 513 | # CONFIG_NL80211_TESTMODE is not set | 582 | # CONFIG_NL80211_TESTMODE is not set |
| 514 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set | 583 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set |
| 515 | # CONFIG_CFG80211_REG_DEBUG is not set | 584 | # CONFIG_CFG80211_REG_DEBUG is not set |
| 516 | CONFIG_CFG80211_DEFAULT_PS=y | 585 | CONFIG_CFG80211_DEFAULT_PS=y |
| 517 | CONFIG_CFG80211_DEFAULT_PS_VALUE=1 | ||
| 518 | # CONFIG_CFG80211_DEBUGFS is not set | 586 | # CONFIG_CFG80211_DEBUGFS is not set |
| 519 | CONFIG_WIRELESS_OLD_REGULATORY=y | 587 | CONFIG_WIRELESS_OLD_REGULATORY=y |
| 520 | CONFIG_WIRELESS_EXT=y | 588 | CONFIG_CFG80211_WEXT=y |
| 521 | CONFIG_WIRELESS_EXT_SYSFS=y | 589 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 522 | CONFIG_LIB80211=y | 590 | CONFIG_LIB80211=y |
| 523 | # CONFIG_LIB80211_DEBUG is not set | 591 | # CONFIG_LIB80211_DEBUG is not set |
| @@ -671,6 +739,7 @@ CONFIG_BLK_DEV=y | |||
| 671 | # CONFIG_BLK_DEV_COW_COMMON is not set | 739 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 672 | CONFIG_BLK_DEV_LOOP=y | 740 | CONFIG_BLK_DEV_LOOP=y |
| 673 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 741 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| 742 | # CONFIG_BLK_DEV_DRBD is not set | ||
| 674 | # CONFIG_BLK_DEV_NBD is not set | 743 | # CONFIG_BLK_DEV_NBD is not set |
| 675 | # CONFIG_BLK_DEV_UB is not set | 744 | # CONFIG_BLK_DEV_UB is not set |
| 676 | CONFIG_BLK_DEV_RAM=y | 745 | CONFIG_BLK_DEV_RAM=y |
| @@ -681,9 +750,12 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 | |||
| 681 | # CONFIG_ATA_OVER_ETH is not set | 750 | # CONFIG_ATA_OVER_ETH is not set |
| 682 | # CONFIG_MG_DISK is not set | 751 | # CONFIG_MG_DISK is not set |
| 683 | CONFIG_MISC_DEVICES=y | 752 | CONFIG_MISC_DEVICES=y |
| 753 | # CONFIG_AD525X_DPOT is not set | ||
| 684 | # CONFIG_ICS932S401 is not set | 754 | # CONFIG_ICS932S401 is not set |
| 685 | # CONFIG_ENCLOSURE_SERVICES is not set | 755 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 686 | # CONFIG_ISL29003 is not set | 756 | # CONFIG_ISL29003 is not set |
| 757 | # CONFIG_DS1682 is not set | ||
| 758 | # CONFIG_TI_DAC7512 is not set | ||
| 687 | # CONFIG_C2PORT is not set | 759 | # CONFIG_C2PORT is not set |
| 688 | 760 | ||
| 689 | # | 761 | # |
| @@ -694,6 +766,7 @@ CONFIG_MISC_DEVICES=y | |||
| 694 | CONFIG_EEPROM_LEGACY=y | 766 | CONFIG_EEPROM_LEGACY=y |
| 695 | # CONFIG_EEPROM_MAX6875 is not set | 767 | # CONFIG_EEPROM_MAX6875 is not set |
| 696 | # CONFIG_EEPROM_93CX6 is not set | 768 | # CONFIG_EEPROM_93CX6 is not set |
| 769 | # CONFIG_IWMC3200TOP is not set | ||
| 697 | CONFIG_HAVE_IDE=y | 770 | CONFIG_HAVE_IDE=y |
| 698 | # CONFIG_IDE is not set | 771 | # CONFIG_IDE is not set |
| 699 | 772 | ||
| @@ -792,28 +865,26 @@ CONFIG_SMSC911X=y | |||
| 792 | CONFIG_NETDEV_1000=y | 865 | CONFIG_NETDEV_1000=y |
| 793 | CONFIG_NETDEV_10000=y | 866 | CONFIG_NETDEV_10000=y |
| 794 | CONFIG_WLAN=y | 867 | CONFIG_WLAN=y |
| 795 | # CONFIG_WLAN_PRE80211 is not set | ||
| 796 | CONFIG_WLAN_80211=y | ||
| 797 | CONFIG_LIBERTAS=y | ||
| 798 | CONFIG_LIBERTAS_USB=y | ||
| 799 | CONFIG_LIBERTAS_SDIO=y | ||
| 800 | # CONFIG_LIBERTAS_SPI is not set | ||
| 801 | CONFIG_LIBERTAS_DEBUG=y | ||
| 802 | # CONFIG_LIBERTAS_THINFIRM is not set | 868 | # CONFIG_LIBERTAS_THINFIRM is not set |
| 803 | # CONFIG_AT76C50X_USB is not set | 869 | # CONFIG_AT76C50X_USB is not set |
| 804 | # CONFIG_USB_ZD1201 is not set | 870 | # CONFIG_USB_ZD1201 is not set |
| 805 | # CONFIG_USB_NET_RNDIS_WLAN is not set | 871 | # CONFIG_USB_NET_RNDIS_WLAN is not set |
| 806 | # CONFIG_RTL8187 is not set | 872 | # CONFIG_RTL8187 is not set |
| 807 | # CONFIG_MAC80211_HWSIM is not set | 873 | # CONFIG_MAC80211_HWSIM is not set |
| 808 | # CONFIG_P54_COMMON is not set | ||
| 809 | # CONFIG_ATH_COMMON is not set | 874 | # CONFIG_ATH_COMMON is not set |
| 810 | # CONFIG_HOSTAP is not set | ||
| 811 | # CONFIG_B43 is not set | 875 | # CONFIG_B43 is not set |
| 812 | # CONFIG_B43LEGACY is not set | 876 | # CONFIG_B43LEGACY is not set |
| 813 | # CONFIG_ZD1211RW is not set | 877 | # CONFIG_HOSTAP is not set |
| 878 | # CONFIG_IWM is not set | ||
| 879 | CONFIG_LIBERTAS=y | ||
| 880 | CONFIG_LIBERTAS_USB=y | ||
| 881 | CONFIG_LIBERTAS_SDIO=y | ||
| 882 | # CONFIG_LIBERTAS_SPI is not set | ||
| 883 | CONFIG_LIBERTAS_DEBUG=y | ||
| 884 | # CONFIG_P54_COMMON is not set | ||
| 814 | # CONFIG_RT2X00 is not set | 885 | # CONFIG_RT2X00 is not set |
| 815 | # CONFIG_WL12XX is not set | 886 | # CONFIG_WL12XX is not set |
| 816 | # CONFIG_IWM is not set | 887 | # CONFIG_ZD1211RW is not set |
| 817 | 888 | ||
| 818 | # | 889 | # |
| 819 | # Enable WiMAX (Networking options) to see the WiMAX drivers | 890 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| @@ -861,6 +932,7 @@ CONFIG_USB_NET_ZAURUS=y | |||
| 861 | CONFIG_INPUT=y | 932 | CONFIG_INPUT=y |
| 862 | # CONFIG_INPUT_FF_MEMLESS is not set | 933 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 863 | # CONFIG_INPUT_POLLDEV is not set | 934 | # CONFIG_INPUT_POLLDEV is not set |
| 935 | # CONFIG_INPUT_SPARSEKMAP is not set | ||
| 864 | 936 | ||
| 865 | # | 937 | # |
| 866 | # Userland interfaces | 938 | # Userland interfaces |
| @@ -889,6 +961,7 @@ CONFIG_KEYBOARD_GPIO=y | |||
| 889 | # CONFIG_KEYBOARD_OPENCORES is not set | 961 | # CONFIG_KEYBOARD_OPENCORES is not set |
| 890 | # CONFIG_KEYBOARD_STOWAWAY is not set | 962 | # CONFIG_KEYBOARD_STOWAWAY is not set |
| 891 | # CONFIG_KEYBOARD_SUNKBD is not set | 963 | # CONFIG_KEYBOARD_SUNKBD is not set |
| 964 | # CONFIG_KEYBOARD_OMAP is not set | ||
| 892 | CONFIG_KEYBOARD_TWL4030=y | 965 | CONFIG_KEYBOARD_TWL4030=y |
| 893 | # CONFIG_KEYBOARD_XTKBD is not set | 966 | # CONFIG_KEYBOARD_XTKBD is not set |
| 894 | CONFIG_INPUT_MOUSE=y | 967 | CONFIG_INPUT_MOUSE=y |
| @@ -914,6 +987,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y | |||
| 914 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 987 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 915 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | 988 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set |
| 916 | # CONFIG_TOUCHSCREEN_AD7879 is not set | 989 | # CONFIG_TOUCHSCREEN_AD7879 is not set |
| 990 | # CONFIG_TOUCHSCREEN_DYNAPRO is not set | ||
| 917 | # CONFIG_TOUCHSCREEN_EETI is not set | 991 | # CONFIG_TOUCHSCREEN_EETI is not set |
| 918 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 992 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 919 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 993 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| @@ -948,6 +1022,7 @@ CONFIG_SERIO=y | |||
| 948 | CONFIG_SERIO_SERPORT=y | 1022 | CONFIG_SERIO_SERPORT=y |
| 949 | CONFIG_SERIO_LIBPS2=y | 1023 | CONFIG_SERIO_LIBPS2=y |
| 950 | # CONFIG_SERIO_RAW is not set | 1024 | # CONFIG_SERIO_RAW is not set |
| 1025 | # CONFIG_SERIO_ALTERA_PS2 is not set | ||
| 951 | # CONFIG_GAMEPORT is not set | 1026 | # CONFIG_GAMEPORT is not set |
| 952 | 1027 | ||
| 953 | # | 1028 | # |
| @@ -986,6 +1061,7 @@ CONFIG_UNIX98_PTYS=y | |||
| 986 | # CONFIG_IPMI_HANDLER is not set | 1061 | # CONFIG_IPMI_HANDLER is not set |
| 987 | CONFIG_HW_RANDOM=y | 1062 | CONFIG_HW_RANDOM=y |
| 988 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | 1063 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set |
| 1064 | CONFIG_HW_RANDOM_OMAP=y | ||
| 989 | # CONFIG_R3964 is not set | 1065 | # CONFIG_R3964 is not set |
| 990 | # CONFIG_RAW_DRIVER is not set | 1066 | # CONFIG_RAW_DRIVER is not set |
| 991 | # CONFIG_TCG_TPM is not set | 1067 | # CONFIG_TCG_TPM is not set |
| @@ -1024,7 +1100,6 @@ CONFIG_I2C_OMAP=y | |||
| 1024 | # | 1100 | # |
| 1025 | # Miscellaneous I2C Chip support | 1101 | # Miscellaneous I2C Chip support |
| 1026 | # | 1102 | # |
| 1027 | # CONFIG_DS1682 is not set | ||
| 1028 | # CONFIG_SENSORS_TSL2550 is not set | 1103 | # CONFIG_SENSORS_TSL2550 is not set |
| 1029 | # CONFIG_I2C_DEBUG_CORE is not set | 1104 | # CONFIG_I2C_DEBUG_CORE is not set |
| 1030 | # CONFIG_I2C_DEBUG_ALGO is not set | 1105 | # CONFIG_I2C_DEBUG_ALGO is not set |
| @@ -1040,6 +1115,8 @@ CONFIG_SPI_MASTER=y | |||
| 1040 | # CONFIG_SPI_BITBANG is not set | 1115 | # CONFIG_SPI_BITBANG is not set |
| 1041 | # CONFIG_SPI_GPIO is not set | 1116 | # CONFIG_SPI_GPIO is not set |
| 1042 | CONFIG_SPI_OMAP24XX=y | 1117 | CONFIG_SPI_OMAP24XX=y |
| 1118 | # CONFIG_SPI_XILINX is not set | ||
| 1119 | # CONFIG_SPI_DESIGNWARE is not set | ||
| 1043 | 1120 | ||
| 1044 | # | 1121 | # |
| 1045 | # SPI Protocol Masters | 1122 | # SPI Protocol Masters |
| @@ -1067,6 +1144,7 @@ CONFIG_GPIO_SYSFS=y | |||
| 1067 | # CONFIG_GPIO_PCA953X is not set | 1144 | # CONFIG_GPIO_PCA953X is not set |
| 1068 | # CONFIG_GPIO_PCF857X is not set | 1145 | # CONFIG_GPIO_PCF857X is not set |
| 1069 | CONFIG_GPIO_TWL4030=y | 1146 | CONFIG_GPIO_TWL4030=y |
| 1147 | # CONFIG_GPIO_ADP5588 is not set | ||
| 1070 | 1148 | ||
| 1071 | # | 1149 | # |
| 1072 | # PCI GPIO expanders: | 1150 | # PCI GPIO expanders: |
| @@ -1141,6 +1219,7 @@ CONFIG_HWMON=y | |||
| 1141 | # CONFIG_SENSORS_IT87 is not set | 1219 | # CONFIG_SENSORS_IT87 is not set |
| 1142 | # CONFIG_SENSORS_LM63 is not set | 1220 | # CONFIG_SENSORS_LM63 is not set |
| 1143 | # CONFIG_SENSORS_LM70 is not set | 1221 | # CONFIG_SENSORS_LM70 is not set |
| 1222 | # CONFIG_SENSORS_LM73 is not set | ||
| 1144 | # CONFIG_SENSORS_LM75 is not set | 1223 | # CONFIG_SENSORS_LM75 is not set |
| 1145 | # CONFIG_SENSORS_LM77 is not set | 1224 | # CONFIG_SENSORS_LM77 is not set |
| 1146 | # CONFIG_SENSORS_LM78 is not set | 1225 | # CONFIG_SENSORS_LM78 is not set |
| @@ -1166,6 +1245,7 @@ CONFIG_HWMON=y | |||
| 1166 | # CONFIG_SENSORS_SMSC47M192 is not set | 1245 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 1167 | # CONFIG_SENSORS_SMSC47B397 is not set | 1246 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 1168 | # CONFIG_SENSORS_ADS7828 is not set | 1247 | # CONFIG_SENSORS_ADS7828 is not set |
| 1248 | # CONFIG_SENSORS_AMC6821 is not set | ||
| 1169 | # CONFIG_SENSORS_THMC50 is not set | 1249 | # CONFIG_SENSORS_THMC50 is not set |
| 1170 | # CONFIG_SENSORS_TMP401 is not set | 1250 | # CONFIG_SENSORS_TMP401 is not set |
| 1171 | # CONFIG_SENSORS_TMP421 is not set | 1251 | # CONFIG_SENSORS_TMP421 is not set |
| @@ -1179,6 +1259,7 @@ CONFIG_HWMON=y | |||
| 1179 | # CONFIG_SENSORS_W83627HF is not set | 1259 | # CONFIG_SENSORS_W83627HF is not set |
| 1180 | # CONFIG_SENSORS_W83627EHF is not set | 1260 | # CONFIG_SENSORS_W83627EHF is not set |
| 1181 | # CONFIG_SENSORS_LIS3_SPI is not set | 1261 | # CONFIG_SENSORS_LIS3_SPI is not set |
| 1262 | # CONFIG_SENSORS_LIS3_I2C is not set | ||
| 1182 | # CONFIG_THERMAL is not set | 1263 | # CONFIG_THERMAL is not set |
| 1183 | CONFIG_WATCHDOG=y | 1264 | CONFIG_WATCHDOG=y |
| 1184 | CONFIG_WATCHDOG_NOWAYOUT=y | 1265 | CONFIG_WATCHDOG_NOWAYOUT=y |
| @@ -1204,20 +1285,22 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1204 | # | 1285 | # |
| 1205 | # Multifunction device drivers | 1286 | # Multifunction device drivers |
| 1206 | # | 1287 | # |
| 1207 | # CONFIG_MFD_CORE is not set | 1288 | CONFIG_MFD_CORE=y |
| 1208 | # CONFIG_MFD_SM501 is not set | 1289 | # CONFIG_MFD_SM501 is not set |
| 1209 | # CONFIG_MFD_ASIC3 is not set | 1290 | # CONFIG_MFD_ASIC3 is not set |
| 1210 | # CONFIG_HTC_EGPIO is not set | 1291 | # CONFIG_HTC_EGPIO is not set |
| 1211 | # CONFIG_HTC_PASIC3 is not set | 1292 | # CONFIG_HTC_PASIC3 is not set |
| 1212 | # CONFIG_TPS65010 is not set | 1293 | # CONFIG_TPS65010 is not set |
| 1294 | # CONFIG_MENELAUS is not set | ||
| 1213 | CONFIG_TWL4030_CORE=y | 1295 | CONFIG_TWL4030_CORE=y |
| 1214 | # CONFIG_TWL4030_POWER is not set | 1296 | # CONFIG_TWL4030_POWER is not set |
| 1215 | # CONFIG_TWL4030_CODEC is not set | 1297 | CONFIG_TWL4030_CODEC=y |
| 1216 | # CONFIG_MFD_TMIO is not set | 1298 | # CONFIG_MFD_TMIO is not set |
| 1217 | # CONFIG_MFD_T7L66XB is not set | 1299 | # CONFIG_MFD_T7L66XB is not set |
| 1218 | # CONFIG_MFD_TC6387XB is not set | 1300 | # CONFIG_MFD_TC6387XB is not set |
| 1219 | # CONFIG_MFD_TC6393XB is not set | 1301 | # CONFIG_MFD_TC6393XB is not set |
| 1220 | # CONFIG_PMIC_DA903X is not set | 1302 | # CONFIG_PMIC_DA903X is not set |
| 1303 | # CONFIG_PMIC_ADP5520 is not set | ||
| 1221 | # CONFIG_MFD_WM8400 is not set | 1304 | # CONFIG_MFD_WM8400 is not set |
| 1222 | # CONFIG_MFD_WM831X is not set | 1305 | # CONFIG_MFD_WM831X is not set |
| 1223 | # CONFIG_MFD_WM8350_I2C is not set | 1306 | # CONFIG_MFD_WM8350_I2C is not set |
| @@ -1225,6 +1308,8 @@ CONFIG_TWL4030_CORE=y | |||
| 1225 | # CONFIG_MFD_MC13783 is not set | 1308 | # CONFIG_MFD_MC13783 is not set |
| 1226 | # CONFIG_AB3100_CORE is not set | 1309 | # CONFIG_AB3100_CORE is not set |
| 1227 | # CONFIG_EZX_PCAP is not set | 1310 | # CONFIG_EZX_PCAP is not set |
| 1311 | # CONFIG_MFD_88PM8607 is not set | ||
| 1312 | # CONFIG_AB4500_CORE is not set | ||
| 1228 | CONFIG_REGULATOR=y | 1313 | CONFIG_REGULATOR=y |
| 1229 | # CONFIG_REGULATOR_DEBUG is not set | 1314 | # CONFIG_REGULATOR_DEBUG is not set |
| 1230 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 1315 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| @@ -1232,6 +1317,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y | |||
| 1232 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | 1317 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set |
| 1233 | # CONFIG_REGULATOR_BQ24022 is not set | 1318 | # CONFIG_REGULATOR_BQ24022 is not set |
| 1234 | # CONFIG_REGULATOR_MAX1586 is not set | 1319 | # CONFIG_REGULATOR_MAX1586 is not set |
| 1320 | # CONFIG_REGULATOR_MAX8660 is not set | ||
| 1235 | CONFIG_REGULATOR_TWL4030=y | 1321 | CONFIG_REGULATOR_TWL4030=y |
| 1236 | # CONFIG_REGULATOR_LP3971 is not set | 1322 | # CONFIG_REGULATOR_LP3971 is not set |
| 1237 | # CONFIG_REGULATOR_TPS65023 is not set | 1323 | # CONFIG_REGULATOR_TPS65023 is not set |
| @@ -1267,6 +1353,7 @@ CONFIG_FB_TILEBLITTING=y | |||
| 1267 | # | 1353 | # |
| 1268 | # CONFIG_FB_UVESA is not set | 1354 | # CONFIG_FB_UVESA is not set |
| 1269 | # CONFIG_FB_S1D13XXX is not set | 1355 | # CONFIG_FB_S1D13XXX is not set |
| 1356 | # CONFIG_FB_TMIO is not set | ||
| 1270 | # CONFIG_FB_VIRTUAL is not set | 1357 | # CONFIG_FB_VIRTUAL is not set |
| 1271 | # CONFIG_FB_METRONOME is not set | 1358 | # CONFIG_FB_METRONOME is not set |
| 1272 | # CONFIG_FB_MB862XX is not set | 1359 | # CONFIG_FB_MB862XX is not set |
| @@ -1281,6 +1368,7 @@ CONFIG_FB_OMAP_079M3R=y | |||
| 1281 | # CONFIG_FB_OMAP_LCD_MIPID is not set | 1368 | # CONFIG_FB_OMAP_LCD_MIPID is not set |
| 1282 | # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set | 1369 | # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set |
| 1283 | CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 | 1370 | CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 |
| 1371 | # CONFIG_OMAP2_DSS is not set | ||
| 1284 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 1372 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 1285 | CONFIG_LCD_CLASS_DEVICE=y | 1373 | CONFIG_LCD_CLASS_DEVICE=y |
| 1286 | # CONFIG_LCD_LMS283GF05 is not set | 1374 | # CONFIG_LCD_LMS283GF05 is not set |
| @@ -1364,12 +1452,15 @@ CONFIG_SND_USB_AUDIO=y | |||
| 1364 | CONFIG_SND_SOC=y | 1452 | CONFIG_SND_SOC=y |
| 1365 | CONFIG_SND_OMAP_SOC=y | 1453 | CONFIG_SND_OMAP_SOC=y |
| 1366 | CONFIG_SND_OMAP_SOC_MCBSP=y | 1454 | CONFIG_SND_OMAP_SOC_MCBSP=y |
| 1455 | # CONFIG_SND_OMAP_SOC_N810 is not set | ||
| 1367 | # CONFIG_SND_OMAP_SOC_OVERO is not set | 1456 | # CONFIG_SND_OMAP_SOC_OVERO is not set |
| 1368 | # CONFIG_SND_OMAP_SOC_OMAP3EVM is not set | 1457 | # CONFIG_SND_OMAP_SOC_OMAP3EVM is not set |
| 1458 | # CONFIG_SND_OMAP_SOC_AM3517EVM is not set | ||
| 1369 | # CONFIG_SND_OMAP_SOC_SDP3430 is not set | 1459 | # CONFIG_SND_OMAP_SOC_SDP3430 is not set |
| 1370 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y | 1460 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y |
| 1371 | # CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE is not set | 1461 | # CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE is not set |
| 1372 | # CONFIG_SND_OMAP_SOC_ZOOM2 is not set | 1462 | # CONFIG_SND_OMAP_SOC_ZOOM2 is not set |
| 1463 | # CONFIG_SND_OMAP_SOC_IGEP0020 is not set | ||
| 1373 | CONFIG_SND_SOC_I2C_AND_SPI=y | 1464 | CONFIG_SND_SOC_I2C_AND_SPI=y |
| 1374 | # CONFIG_SND_SOC_ALL_CODECS is not set | 1465 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 1375 | CONFIG_SND_SOC_TWL4030=y | 1466 | CONFIG_SND_SOC_TWL4030=y |
| @@ -1418,7 +1509,7 @@ CONFIG_USB_HID=y | |||
| 1418 | CONFIG_USB_SUPPORT=y | 1509 | CONFIG_USB_SUPPORT=y |
| 1419 | CONFIG_USB_ARCH_HAS_HCD=y | 1510 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1420 | CONFIG_USB_ARCH_HAS_OHCI=y | 1511 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 1421 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1512 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 1422 | CONFIG_USB=y | 1513 | CONFIG_USB=y |
| 1423 | CONFIG_USB_DEBUG=y | 1514 | CONFIG_USB_DEBUG=y |
| 1424 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 1515 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| @@ -1441,6 +1532,7 @@ CONFIG_USB_MON=y | |||
| 1441 | # USB Host Controller Drivers | 1532 | # USB Host Controller Drivers |
| 1442 | # | 1533 | # |
| 1443 | # CONFIG_USB_C67X00_HCD is not set | 1534 | # CONFIG_USB_C67X00_HCD is not set |
| 1535 | # CONFIG_USB_EHCI_HCD is not set | ||
| 1444 | # CONFIG_USB_OXU210HP_HCD is not set | 1536 | # CONFIG_USB_OXU210HP_HCD is not set |
| 1445 | # CONFIG_USB_ISP116X_HCD is not set | 1537 | # CONFIG_USB_ISP116X_HCD is not set |
| 1446 | # CONFIG_USB_ISP1760_HCD is not set | 1538 | # CONFIG_USB_ISP1760_HCD is not set |
| @@ -1556,16 +1648,18 @@ CONFIG_USB_GADGET_SELECTED=y | |||
| 1556 | # CONFIG_USB_GADGET_LANGWELL is not set | 1648 | # CONFIG_USB_GADGET_LANGWELL is not set |
| 1557 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 1649 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| 1558 | CONFIG_USB_GADGET_DUALSPEED=y | 1650 | CONFIG_USB_GADGET_DUALSPEED=y |
| 1559 | CONFIG_USB_ZERO=y | 1651 | CONFIG_USB_ZERO=m |
| 1560 | # CONFIG_USB_ZERO_HNPTEST is not set | 1652 | # CONFIG_USB_ZERO_HNPTEST is not set |
| 1561 | # CONFIG_USB_AUDIO is not set | 1653 | # CONFIG_USB_AUDIO is not set |
| 1562 | # CONFIG_USB_ETH is not set | 1654 | # CONFIG_USB_ETH is not set |
| 1563 | # CONFIG_USB_GADGETFS is not set | 1655 | # CONFIG_USB_GADGETFS is not set |
| 1564 | # CONFIG_USB_FILE_STORAGE is not set | 1656 | # CONFIG_USB_FILE_STORAGE is not set |
| 1657 | # CONFIG_USB_MASS_STORAGE is not set | ||
| 1565 | # CONFIG_USB_G_SERIAL is not set | 1658 | # CONFIG_USB_G_SERIAL is not set |
| 1566 | # CONFIG_USB_MIDI_GADGET is not set | 1659 | # CONFIG_USB_MIDI_GADGET is not set |
| 1567 | # CONFIG_USB_G_PRINTER is not set | 1660 | # CONFIG_USB_G_PRINTER is not set |
| 1568 | # CONFIG_USB_CDC_COMPOSITE is not set | 1661 | # CONFIG_USB_CDC_COMPOSITE is not set |
| 1662 | # CONFIG_USB_G_MULTI is not set | ||
| 1569 | 1663 | ||
| 1570 | # | 1664 | # |
| 1571 | # OTG and related infrastructure | 1665 | # OTG and related infrastructure |
| @@ -1573,6 +1667,7 @@ CONFIG_USB_ZERO=y | |||
| 1573 | CONFIG_USB_OTG_UTILS=y | 1667 | CONFIG_USB_OTG_UTILS=y |
| 1574 | # CONFIG_USB_GPIO_VBUS is not set | 1668 | # CONFIG_USB_GPIO_VBUS is not set |
| 1575 | # CONFIG_ISP1301_OMAP is not set | 1669 | # CONFIG_ISP1301_OMAP is not set |
| 1670 | # CONFIG_USB_ULPI is not set | ||
| 1576 | CONFIG_TWL4030_USB=y | 1671 | CONFIG_TWL4030_USB=y |
| 1577 | CONFIG_NOP_USB_XCEIV=y | 1672 | CONFIG_NOP_USB_XCEIV=y |
| 1578 | CONFIG_MMC=y | 1673 | CONFIG_MMC=y |
| @@ -1609,7 +1704,9 @@ CONFIG_LEDS_GPIO_PLATFORM=y | |||
| 1609 | # CONFIG_LEDS_LP3944 is not set | 1704 | # CONFIG_LEDS_LP3944 is not set |
| 1610 | # CONFIG_LEDS_PCA955X is not set | 1705 | # CONFIG_LEDS_PCA955X is not set |
| 1611 | # CONFIG_LEDS_DAC124S085 is not set | 1706 | # CONFIG_LEDS_DAC124S085 is not set |
| 1707 | # CONFIG_LEDS_REGULATOR is not set | ||
| 1612 | # CONFIG_LEDS_BD2802 is not set | 1708 | # CONFIG_LEDS_BD2802 is not set |
| 1709 | # CONFIG_LEDS_LT3593 is not set | ||
| 1613 | 1710 | ||
| 1614 | # | 1711 | # |
| 1615 | # LED Triggers | 1712 | # LED Triggers |
| @@ -1653,6 +1750,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1653 | # CONFIG_RTC_DRV_PCF8563 is not set | 1750 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1654 | # CONFIG_RTC_DRV_PCF8583 is not set | 1751 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1655 | # CONFIG_RTC_DRV_M41T80 is not set | 1752 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1753 | # CONFIG_RTC_DRV_BQ32K is not set | ||
| 1656 | CONFIG_RTC_DRV_TWL4030=y | 1754 | CONFIG_RTC_DRV_TWL4030=y |
| 1657 | # CONFIG_RTC_DRV_S35390A is not set | 1755 | # CONFIG_RTC_DRV_S35390A is not set |
| 1658 | # CONFIG_RTC_DRV_FM3130 is not set | 1756 | # CONFIG_RTC_DRV_FM3130 is not set |
| @@ -1683,7 +1781,9 @@ CONFIG_RTC_DRV_TWL4030=y | |||
| 1683 | # CONFIG_RTC_DRV_M48T86 is not set | 1781 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1684 | # CONFIG_RTC_DRV_M48T35 is not set | 1782 | # CONFIG_RTC_DRV_M48T35 is not set |
| 1685 | # CONFIG_RTC_DRV_M48T59 is not set | 1783 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1784 | # CONFIG_RTC_DRV_MSM6242 is not set | ||
| 1686 | # CONFIG_RTC_DRV_BQ4802 is not set | 1785 | # CONFIG_RTC_DRV_BQ4802 is not set |
| 1786 | # CONFIG_RTC_DRV_RP5C01 is not set | ||
| 1687 | # CONFIG_RTC_DRV_V3020 is not set | 1787 | # CONFIG_RTC_DRV_V3020 is not set |
| 1688 | 1788 | ||
| 1689 | # | 1789 | # |
| @@ -1951,6 +2051,7 @@ CONFIG_DEBUG_INFO=y | |||
| 1951 | # CONFIG_LKDTM is not set | 2051 | # CONFIG_LKDTM is not set |
| 1952 | # CONFIG_FAULT_INJECTION is not set | 2052 | # CONFIG_FAULT_INJECTION is not set |
| 1953 | # CONFIG_LATENCYTOP is not set | 2053 | # CONFIG_LATENCYTOP is not set |
| 2054 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1954 | # CONFIG_PAGE_POISONING is not set | 2055 | # CONFIG_PAGE_POISONING is not set |
| 1955 | CONFIG_NOP_TRACER=y | 2056 | CONFIG_NOP_TRACER=y |
| 1956 | CONFIG_HAVE_FUNCTION_TRACER=y | 2057 | CONFIG_HAVE_FUNCTION_TRACER=y |
| @@ -1983,7 +2084,9 @@ CONFIG_ARM_UNWIND=y | |||
| 1983 | # CONFIG_DEBUG_ERRORS is not set | 2084 | # CONFIG_DEBUG_ERRORS is not set |
| 1984 | # CONFIG_DEBUG_STACK_USAGE is not set | 2085 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1985 | CONFIG_DEBUG_LL=y | 2086 | CONFIG_DEBUG_LL=y |
| 2087 | # CONFIG_EARLY_PRINTK is not set | ||
| 1986 | # CONFIG_DEBUG_ICEDCC is not set | 2088 | # CONFIG_DEBUG_ICEDCC is not set |
| 2089 | # CONFIG_OC_ETM is not set | ||
| 1987 | 2090 | ||
| 1988 | # | 2091 | # |
| 1989 | # Security options | 2092 | # Security options |
| @@ -1993,9 +2096,12 @@ CONFIG_SECURITY=y | |||
| 1993 | # CONFIG_SECURITYFS is not set | 2096 | # CONFIG_SECURITYFS is not set |
| 1994 | # CONFIG_SECURITY_NETWORK is not set | 2097 | # CONFIG_SECURITY_NETWORK is not set |
| 1995 | # CONFIG_SECURITY_PATH is not set | 2098 | # CONFIG_SECURITY_PATH is not set |
| 1996 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1997 | # CONFIG_SECURITY_ROOTPLUG is not set | ||
| 1998 | # CONFIG_SECURITY_TOMOYO is not set | 2099 | # CONFIG_SECURITY_TOMOYO is not set |
| 2100 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set | ||
| 2101 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
| 2102 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
| 2103 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
| 2104 | CONFIG_DEFAULT_SECURITY="" | ||
| 1999 | CONFIG_CRYPTO=y | 2105 | CONFIG_CRYPTO=y |
| 2000 | 2106 | ||
| 2001 | # | 2107 | # |
diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig index 86cc4bea616b..e2ad859fbec6 100644 --- a/arch/arm/configs/omap3_evm_defconfig +++ b/arch/arm/configs/omap3_evm_defconfig | |||
| @@ -187,6 +187,8 @@ CONFIG_ARCH_OMAP3=y | |||
| 187 | # | 187 | # |
| 188 | # OMAP Feature Selections | 188 | # OMAP Feature Selections |
| 189 | # | 189 | # |
| 190 | CONFIG_OMAP_SMARTREFLEX=y | ||
| 191 | # CONFIG_OMAP_SMARTREFLEX_TESTING is not set | ||
| 190 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | 192 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set |
| 191 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | 193 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set |
| 192 | CONFIG_OMAP_RESET_CLOCKS=y | 194 | CONFIG_OMAP_RESET_CLOCKS=y |
| @@ -333,7 +335,7 @@ CONFIG_BINFMT_MISC=y | |||
| 333 | # Power management options | 335 | # Power management options |
| 334 | # | 336 | # |
| 335 | CONFIG_PM=y | 337 | CONFIG_PM=y |
| 336 | # CONFIG_PM_DEBUG is not set | 338 | CONFIG_PM_DEBUG=y |
| 337 | CONFIG_PM_SLEEP=y | 339 | CONFIG_PM_SLEEP=y |
| 338 | CONFIG_SUSPEND=y | 340 | CONFIG_SUSPEND=y |
| 339 | CONFIG_SUSPEND_FREEZER=y | 341 | CONFIG_SUSPEND_FREEZER=y |
| @@ -1339,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y | |||
| 1339 | CONFIG_FRAME_WARN=1024 | 1341 | CONFIG_FRAME_WARN=1024 |
| 1340 | CONFIG_MAGIC_SYSRQ=y | 1342 | CONFIG_MAGIC_SYSRQ=y |
| 1341 | # CONFIG_UNUSED_SYMBOLS is not set | 1343 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1342 | # CONFIG_DEBUG_FS is not set | 1344 | CONFIG_DEBUG_FS=y |
| 1343 | # CONFIG_HEADERS_CHECK is not set | 1345 | # CONFIG_HEADERS_CHECK is not set |
| 1344 | CONFIG_DEBUG_KERNEL=y | 1346 | CONFIG_DEBUG_KERNEL=y |
| 1345 | # CONFIG_DEBUG_SHIRQ is not set | 1347 | # CONFIG_DEBUG_SHIRQ is not set |
diff --git a/arch/arm/configs/omap3_pandora_defconfig b/arch/arm/configs/omap3_pandora_defconfig index f74eb9a1d191..5d08e0b0361d 100644 --- a/arch/arm/configs/omap3_pandora_defconfig +++ b/arch/arm/configs/omap3_pandora_defconfig | |||
| @@ -1,15 +1,14 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28-rc7 | 3 | # Linux kernel version: 2.6.33-rc6 |
| 4 | # Fri Dec 5 11:54:09 2008 | 4 | # Sat Feb 6 20:25:41 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_GENERIC_TIME=y | 9 | CONFIG_GENERIC_TIME=y |
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | 10 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 11 | CONFIG_MMU=y | 11 | CONFIG_HAVE_PROC_CPU=y |
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | 12 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 13 | CONFIG_STACKTRACE_SUPPORT=y |
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y |
| @@ -18,13 +17,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | 20 | CONFIG_ARCH_HAS_CPUFREQ=y |
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | 21 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 22 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 23 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 26 | CONFIG_CONSTRUCTORS=y | ||
| 28 | 27 | ||
| 29 | # | 28 | # |
| 30 | # General setup | 29 | # General setup |
| @@ -32,8 +31,15 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | |||
| 32 | CONFIG_EXPERIMENTAL=y | 31 | CONFIG_EXPERIMENTAL=y |
| 33 | CONFIG_BROKEN_ON_SMP=y | 32 | CONFIG_BROKEN_ON_SMP=y |
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 34 | CONFIG_CROSS_COMPILE="" | ||
| 35 | CONFIG_LOCALVERSION="" | 35 | CONFIG_LOCALVERSION="" |
| 36 | CONFIG_LOCALVERSION_AUTO=y | 36 | CONFIG_LOCALVERSION_AUTO=y |
| 37 | CONFIG_HAVE_KERNEL_GZIP=y | ||
| 38 | CONFIG_HAVE_KERNEL_LZO=y | ||
| 39 | CONFIG_KERNEL_GZIP=y | ||
| 40 | # CONFIG_KERNEL_BZIP2 is not set | ||
| 41 | # CONFIG_KERNEL_LZMA is not set | ||
| 42 | # CONFIG_KERNEL_LZO is not set | ||
| 37 | CONFIG_SWAP=y | 43 | CONFIG_SWAP=y |
| 38 | CONFIG_SYSVIPC=y | 44 | CONFIG_SYSVIPC=y |
| 39 | CONFIG_SYSVIPC_SYSCTL=y | 45 | CONFIG_SYSVIPC_SYSCTL=y |
| @@ -42,24 +48,33 @@ CONFIG_BSD_PROCESS_ACCT=y | |||
| 42 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | 48 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set |
| 43 | # CONFIG_TASKSTATS is not set | 49 | # CONFIG_TASKSTATS is not set |
| 44 | # CONFIG_AUDIT is not set | 50 | # CONFIG_AUDIT is not set |
| 51 | |||
| 52 | # | ||
| 53 | # RCU Subsystem | ||
| 54 | # | ||
| 55 | CONFIG_TREE_RCU=y | ||
| 56 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
| 57 | # CONFIG_TINY_RCU is not set | ||
| 58 | # CONFIG_RCU_TRACE is not set | ||
| 59 | CONFIG_RCU_FANOUT=32 | ||
| 60 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 61 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 45 | CONFIG_IKCONFIG=y | 62 | CONFIG_IKCONFIG=y |
| 46 | CONFIG_IKCONFIG_PROC=y | 63 | CONFIG_IKCONFIG_PROC=y |
| 47 | CONFIG_LOG_BUF_SHIFT=14 | 64 | CONFIG_LOG_BUF_SHIFT=14 |
| 48 | # CONFIG_CGROUPS is not set | 65 | # CONFIG_CGROUPS is not set |
| 49 | CONFIG_GROUP_SCHED=y | 66 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 50 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 51 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 52 | CONFIG_USER_SCHED=y | ||
| 53 | # CONFIG_CGROUP_SCHED is not set | ||
| 54 | # CONFIG_SYSFS_DEPRECATED=y is not set | ||
| 55 | # CONFIG_SYSFS_DEPRECATED_V2=y is not set | ||
| 56 | |||
| 57 | # CONFIG_RELAY is not set | 67 | # CONFIG_RELAY is not set |
| 58 | # CONFIG_NAMESPACES is not set | 68 | # CONFIG_NAMESPACES is not set |
| 59 | CONFIG_BLK_DEV_INITRD=y | 69 | CONFIG_BLK_DEV_INITRD=y |
| 60 | CONFIG_INITRAMFS_SOURCE="" | 70 | CONFIG_INITRAMFS_SOURCE="" |
| 71 | CONFIG_RD_GZIP=y | ||
| 72 | # CONFIG_RD_BZIP2 is not set | ||
| 73 | # CONFIG_RD_LZMA is not set | ||
| 74 | # CONFIG_RD_LZO is not set | ||
| 61 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 75 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 62 | CONFIG_SYSCTL=y | 76 | CONFIG_SYSCTL=y |
| 77 | CONFIG_ANON_INODES=y | ||
| 63 | CONFIG_EMBEDDED=y | 78 | CONFIG_EMBEDDED=y |
| 64 | CONFIG_UID16=y | 79 | CONFIG_UID16=y |
| 65 | # CONFIG_SYSCTL_SYSCALL is not set | 80 | # CONFIG_SYSCTL_SYSCALL is not set |
| @@ -70,31 +85,41 @@ CONFIG_HOTPLUG=y | |||
| 70 | CONFIG_PRINTK=y | 85 | CONFIG_PRINTK=y |
| 71 | CONFIG_BUG=y | 86 | CONFIG_BUG=y |
| 72 | CONFIG_ELF_CORE=y | 87 | CONFIG_ELF_CORE=y |
| 73 | CONFIG_COMPAT_BRK=y | ||
| 74 | CONFIG_BASE_FULL=y | 88 | CONFIG_BASE_FULL=y |
| 75 | CONFIG_FUTEX=y | 89 | CONFIG_FUTEX=y |
| 76 | CONFIG_ANON_INODES=y | ||
| 77 | CONFIG_EPOLL=y | 90 | CONFIG_EPOLL=y |
| 78 | CONFIG_SIGNALFD=y | 91 | CONFIG_SIGNALFD=y |
| 79 | CONFIG_TIMERFD=y | 92 | CONFIG_TIMERFD=y |
| 80 | CONFIG_EVENTFD=y | 93 | CONFIG_EVENTFD=y |
| 81 | CONFIG_SHMEM=y | 94 | CONFIG_SHMEM=y |
| 82 | CONFIG_AIO=y | 95 | CONFIG_AIO=y |
| 96 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 97 | CONFIG_PERF_USE_VMALLOC=y | ||
| 98 | |||
| 99 | # | ||
| 100 | # Kernel Performance Events And Counters | ||
| 101 | # | ||
| 102 | # CONFIG_PERF_EVENTS is not set | ||
| 103 | # CONFIG_PERF_COUNTERS is not set | ||
| 83 | CONFIG_VM_EVENT_COUNTERS=y | 104 | CONFIG_VM_EVENT_COUNTERS=y |
| 105 | CONFIG_COMPAT_BRK=y | ||
| 84 | CONFIG_SLAB=y | 106 | CONFIG_SLAB=y |
| 85 | # CONFIG_SLUB is not set | 107 | # CONFIG_SLUB is not set |
| 86 | # CONFIG_SLOB is not set | 108 | # CONFIG_SLOB is not set |
| 87 | # CONFIG_PROFILING is not set | 109 | # CONFIG_PROFILING is not set |
| 88 | # CONFIG_MARKERS is not set | ||
| 89 | CONFIG_HAVE_OPROFILE=y | 110 | CONFIG_HAVE_OPROFILE=y |
| 90 | # CONFIG_KPROBES is not set | 111 | # CONFIG_KPROBES is not set |
| 91 | CONFIG_HAVE_KPROBES=y | 112 | CONFIG_HAVE_KPROBES=y |
| 92 | CONFIG_HAVE_KRETPROBES=y | 113 | CONFIG_HAVE_KRETPROBES=y |
| 93 | CONFIG_HAVE_CLK=y | 114 | CONFIG_HAVE_CLK=y |
| 115 | |||
| 116 | # | ||
| 117 | # GCOV-based kernel profiling | ||
| 118 | # | ||
| 119 | CONFIG_SLOW_WORK=y | ||
| 94 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 120 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 95 | CONFIG_SLABINFO=y | 121 | CONFIG_SLABINFO=y |
| 96 | CONFIG_RT_MUTEXES=y | 122 | CONFIG_RT_MUTEXES=y |
| 97 | # CONFIG_TINY_SHMEM is not set | ||
| 98 | CONFIG_BASE_SMALL=0 | 123 | CONFIG_BASE_SMALL=0 |
| 99 | CONFIG_MODULES=y | 124 | CONFIG_MODULES=y |
| 100 | # CONFIG_MODULE_FORCE_LOAD is not set | 125 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -102,11 +127,8 @@ CONFIG_MODULE_UNLOAD=y | |||
| 102 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 127 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 103 | CONFIG_MODVERSIONS=y | 128 | CONFIG_MODVERSIONS=y |
| 104 | CONFIG_MODULE_SRCVERSION_ALL=y | 129 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 105 | CONFIG_KMOD=y | ||
| 106 | CONFIG_BLOCK=y | 130 | CONFIG_BLOCK=y |
| 107 | # CONFIG_LBD is not set | 131 | CONFIG_LBDAF=y |
| 108 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 109 | # CONFIG_LSF is not set | ||
| 110 | # CONFIG_BLK_DEV_BSG is not set | 132 | # CONFIG_BLK_DEV_BSG is not set |
| 111 | # CONFIG_BLK_DEV_INTEGRITY is not set | 133 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 112 | 134 | ||
| @@ -114,33 +136,62 @@ CONFIG_BLOCK=y | |||
| 114 | # IO Schedulers | 136 | # IO Schedulers |
| 115 | # | 137 | # |
| 116 | CONFIG_IOSCHED_NOOP=y | 138 | CONFIG_IOSCHED_NOOP=y |
| 117 | CONFIG_IOSCHED_AS=y | ||
| 118 | CONFIG_IOSCHED_DEADLINE=y | 139 | CONFIG_IOSCHED_DEADLINE=y |
| 119 | CONFIG_IOSCHED_CFQ=y | 140 | CONFIG_IOSCHED_CFQ=y |
| 120 | CONFIG_DEFAULT_AS=y | ||
| 121 | # CONFIG_DEFAULT_DEADLINE is not set | 141 | # CONFIG_DEFAULT_DEADLINE is not set |
| 122 | # CONFIG_DEFAULT_CFQ is not set | 142 | CONFIG_DEFAULT_CFQ=y |
| 123 | # CONFIG_DEFAULT_NOOP is not set | 143 | # CONFIG_DEFAULT_NOOP is not set |
| 124 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 144 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 125 | CONFIG_CLASSIC_RCU=y | 145 | # CONFIG_INLINE_SPIN_TRYLOCK is not set |
| 146 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
| 147 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
| 148 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
| 149 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
| 150 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
| 151 | CONFIG_INLINE_SPIN_UNLOCK=y | ||
| 152 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
| 153 | CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | ||
| 154 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
| 155 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
| 156 | # CONFIG_INLINE_READ_LOCK is not set | ||
| 157 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
| 158 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
| 159 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
| 160 | CONFIG_INLINE_READ_UNLOCK=y | ||
| 161 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
| 162 | CONFIG_INLINE_READ_UNLOCK_IRQ=y | ||
| 163 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
| 164 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
| 165 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
| 166 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
| 167 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
| 168 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
| 169 | CONFIG_INLINE_WRITE_UNLOCK=y | ||
| 170 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
| 171 | CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | ||
| 172 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
| 173 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
| 126 | # CONFIG_FREEZER is not set | 174 | # CONFIG_FREEZER is not set |
| 127 | 175 | ||
| 128 | # | 176 | # |
| 129 | # System Type | 177 | # System Type |
| 130 | # | 178 | # |
| 179 | CONFIG_MMU=y | ||
| 131 | # CONFIG_ARCH_AAEC2000 is not set | 180 | # CONFIG_ARCH_AAEC2000 is not set |
| 132 | # CONFIG_ARCH_INTEGRATOR is not set | 181 | # CONFIG_ARCH_INTEGRATOR is not set |
| 133 | # CONFIG_ARCH_REALVIEW is not set | 182 | # CONFIG_ARCH_REALVIEW is not set |
| 134 | # CONFIG_ARCH_VERSATILE is not set | 183 | # CONFIG_ARCH_VERSATILE is not set |
| 135 | # CONFIG_ARCH_AT91 is not set | 184 | # CONFIG_ARCH_AT91 is not set |
| 136 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 137 | # CONFIG_ARCH_CLPS711X is not set | 185 | # CONFIG_ARCH_CLPS711X is not set |
| 186 | # CONFIG_ARCH_GEMINI is not set | ||
| 138 | # CONFIG_ARCH_EBSA110 is not set | 187 | # CONFIG_ARCH_EBSA110 is not set |
| 139 | # CONFIG_ARCH_EP93XX is not set | 188 | # CONFIG_ARCH_EP93XX is not set |
| 140 | # CONFIG_ARCH_FOOTBRIDGE is not set | 189 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 190 | # CONFIG_ARCH_MXC is not set | ||
| 191 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 141 | # CONFIG_ARCH_NETX is not set | 192 | # CONFIG_ARCH_NETX is not set |
| 142 | # CONFIG_ARCH_H720X is not set | 193 | # CONFIG_ARCH_H720X is not set |
| 143 | # CONFIG_ARCH_IMX is not set | 194 | # CONFIG_ARCH_NOMADIK is not set |
| 144 | # CONFIG_ARCH_IOP13XX is not set | 195 | # CONFIG_ARCH_IOP13XX is not set |
| 145 | # CONFIG_ARCH_IOP32X is not set | 196 | # CONFIG_ARCH_IOP32X is not set |
| 146 | # CONFIG_ARCH_IOP33X is not set | 197 | # CONFIG_ARCH_IOP33X is not set |
| @@ -148,49 +199,58 @@ CONFIG_CLASSIC_RCU=y | |||
| 148 | # CONFIG_ARCH_IXP2000 is not set | 199 | # CONFIG_ARCH_IXP2000 is not set |
| 149 | # CONFIG_ARCH_IXP4XX is not set | 200 | # CONFIG_ARCH_IXP4XX is not set |
| 150 | # CONFIG_ARCH_L7200 is not set | 201 | # CONFIG_ARCH_L7200 is not set |
| 202 | # CONFIG_ARCH_DOVE is not set | ||
| 151 | # CONFIG_ARCH_KIRKWOOD is not set | 203 | # CONFIG_ARCH_KIRKWOOD is not set |
| 152 | # CONFIG_ARCH_KS8695 is not set | ||
| 153 | # CONFIG_ARCH_NS9XXX is not set | ||
| 154 | # CONFIG_ARCH_LOKI is not set | 204 | # CONFIG_ARCH_LOKI is not set |
| 155 | # CONFIG_ARCH_MV78XX0 is not set | 205 | # CONFIG_ARCH_MV78XX0 is not set |
| 156 | # CONFIG_ARCH_MXC is not set | ||
| 157 | # CONFIG_ARCH_ORION5X is not set | 206 | # CONFIG_ARCH_ORION5X is not set |
| 207 | # CONFIG_ARCH_MMP is not set | ||
| 208 | # CONFIG_ARCH_KS8695 is not set | ||
| 209 | # CONFIG_ARCH_NS9XXX is not set | ||
| 210 | # CONFIG_ARCH_W90X900 is not set | ||
| 211 | # CONFIG_ARCH_NUC93X is not set | ||
| 158 | # CONFIG_ARCH_PNX4008 is not set | 212 | # CONFIG_ARCH_PNX4008 is not set |
| 159 | # CONFIG_ARCH_PXA is not set | 213 | # CONFIG_ARCH_PXA is not set |
| 214 | # CONFIG_ARCH_MSM is not set | ||
| 160 | # CONFIG_ARCH_RPC is not set | 215 | # CONFIG_ARCH_RPC is not set |
| 161 | # CONFIG_ARCH_SA1100 is not set | 216 | # CONFIG_ARCH_SA1100 is not set |
| 162 | # CONFIG_ARCH_S3C2410 is not set | 217 | # CONFIG_ARCH_S3C2410 is not set |
| 218 | # CONFIG_ARCH_S3C64XX is not set | ||
| 219 | # CONFIG_ARCH_S5P6440 is not set | ||
| 220 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 163 | # CONFIG_ARCH_SHARK is not set | 221 | # CONFIG_ARCH_SHARK is not set |
| 164 | # CONFIG_ARCH_LH7A40X is not set | 222 | # CONFIG_ARCH_LH7A40X is not set |
| 223 | # CONFIG_ARCH_U300 is not set | ||
| 165 | # CONFIG_ARCH_DAVINCI is not set | 224 | # CONFIG_ARCH_DAVINCI is not set |
| 166 | CONFIG_ARCH_OMAP=y | 225 | CONFIG_ARCH_OMAP=y |
| 167 | # CONFIG_ARCH_MSM is not set | 226 | # CONFIG_ARCH_BCMRING is not set |
| 227 | # CONFIG_ARCH_U8500 is not set | ||
| 168 | 228 | ||
| 169 | # | 229 | # |
| 170 | # TI OMAP Implementations | 230 | # TI OMAP Implementations |
| 171 | # | 231 | # |
| 172 | CONFIG_ARCH_OMAP_OTG=y | 232 | CONFIG_ARCH_OMAP_OTG=y |
| 173 | # CONFIG_ARCH_OMAP1 is not set | 233 | # CONFIG_ARCH_OMAP1 is not set |
| 234 | CONFIG_ARCH_OMAP2PLUS=y | ||
| 174 | # CONFIG_ARCH_OMAP2 is not set | 235 | # CONFIG_ARCH_OMAP2 is not set |
| 175 | CONFIG_ARCH_OMAP3=y | 236 | CONFIG_ARCH_OMAP3=y |
| 237 | # CONFIG_ARCH_OMAP4 is not set | ||
| 176 | 238 | ||
| 177 | # | 239 | # |
| 178 | # OMAP Feature Selections | 240 | # OMAP Feature Selections |
| 179 | # | 241 | # |
| 180 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
| 181 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
| 182 | # CONFIG_OMAP_RESET_CLOCKS is not set | 242 | # CONFIG_OMAP_RESET_CLOCKS is not set |
| 183 | # CONFIG_OMAP_MUX is not set | 243 | # CONFIG_OMAP_MUX is not set |
| 184 | CONFIG_OMAP_MCBSP=y | 244 | CONFIG_OMAP_MCBSP=y |
| 245 | # CONFIG_OMAP_MBOX_FWK is not set | ||
| 185 | # CONFIG_OMAP_MPU_TIMER is not set | 246 | # CONFIG_OMAP_MPU_TIMER is not set |
| 186 | CONFIG_OMAP_32K_TIMER=y | 247 | CONFIG_OMAP_32K_TIMER=y |
| 187 | CONFIG_OMAP_32K_TIMER_HZ=128 | 248 | CONFIG_OMAP_32K_TIMER_HZ=128 |
| 188 | CONFIG_OMAP_DM_TIMER=y | 249 | CONFIG_OMAP_DM_TIMER=y |
| 189 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | 250 | # CONFIG_OMAP_PM_NONE is not set |
| 190 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | 251 | CONFIG_OMAP_PM_NOOP=y |
| 191 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
| 192 | CONFIG_ARCH_OMAP34XX=y | ||
| 193 | CONFIG_ARCH_OMAP3430=y | 252 | CONFIG_ARCH_OMAP3430=y |
| 253 | CONFIG_OMAP_PACKAGE_CBB=y | ||
| 194 | 254 | ||
| 195 | # | 255 | # |
| 196 | # OMAP Board Type | 256 | # OMAP Board Type |
| @@ -198,15 +258,19 @@ CONFIG_ARCH_OMAP3430=y | |||
| 198 | # CONFIG_MACH_OMAP3_BEAGLE is not set | 258 | # CONFIG_MACH_OMAP3_BEAGLE is not set |
| 199 | # CONFIG_MACH_OMAP_LDP is not set | 259 | # CONFIG_MACH_OMAP_LDP is not set |
| 200 | # CONFIG_MACH_OVERO is not set | 260 | # CONFIG_MACH_OVERO is not set |
| 261 | # CONFIG_MACH_OMAP3EVM is not set | ||
| 262 | # CONFIG_MACH_OMAP3517EVM is not set | ||
| 201 | CONFIG_MACH_OMAP3_PANDORA=y | 263 | CONFIG_MACH_OMAP3_PANDORA=y |
| 202 | 264 | # CONFIG_MACH_OMAP3_TOUCHBOOK is not set | |
| 203 | # | 265 | # CONFIG_MACH_OMAP_3430SDP is not set |
| 204 | # Boot options | 266 | # CONFIG_MACH_NOKIA_RX51 is not set |
| 205 | # | 267 | # CONFIG_MACH_OMAP_ZOOM2 is not set |
| 206 | 268 | # CONFIG_MACH_OMAP_ZOOM3 is not set | |
| 207 | # | 269 | # CONFIG_MACH_CM_T35 is not set |
| 208 | # Power management | 270 | # CONFIG_MACH_IGEP0020 is not set |
| 209 | # | 271 | # CONFIG_MACH_OMAP_3630SDP is not set |
| 272 | # CONFIG_OMAP3_EMU is not set | ||
| 273 | # CONFIG_OMAP3_SDRC_AC_TIMING is not set | ||
| 210 | 274 | ||
| 211 | # | 275 | # |
| 212 | # Processor Type | 276 | # Processor Type |
| @@ -215,7 +279,7 @@ CONFIG_CPU_32v6K=y | |||
| 215 | CONFIG_CPU_V7=y | 279 | CONFIG_CPU_V7=y |
| 216 | CONFIG_CPU_32v7=y | 280 | CONFIG_CPU_32v7=y |
| 217 | CONFIG_CPU_ABRT_EV7=y | 281 | CONFIG_CPU_ABRT_EV7=y |
| 218 | CONFIG_CPU_PABRT_IFAR=y | 282 | CONFIG_CPU_PABRT_V7=y |
| 219 | CONFIG_CPU_CACHE_V7=y | 283 | CONFIG_CPU_CACHE_V7=y |
| 220 | CONFIG_CPU_CACHE_VIPT=y | 284 | CONFIG_CPU_CACHE_VIPT=y |
| 221 | CONFIG_CPU_COPY_V6=y | 285 | CONFIG_CPU_COPY_V6=y |
| @@ -233,7 +297,12 @@ CONFIG_ARM_THUMBEE=y | |||
| 233 | # CONFIG_CPU_DCACHE_DISABLE is not set | 297 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 234 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 298 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 235 | CONFIG_HAS_TLS_REG=y | 299 | CONFIG_HAS_TLS_REG=y |
| 236 | # CONFIG_OUTER_CACHE is not set | 300 | CONFIG_ARM_L1_CACHE_SHIFT=6 |
| 301 | CONFIG_CPU_HAS_PMU=y | ||
| 302 | # CONFIG_ARM_ERRATA_430973 is not set | ||
| 303 | # CONFIG_ARM_ERRATA_458693 is not set | ||
| 304 | # CONFIG_ARM_ERRATA_460075 is not set | ||
| 305 | CONFIG_COMMON_CLKDEV=y | ||
| 237 | 306 | ||
| 238 | # | 307 | # |
| 239 | # Bus support | 308 | # Bus support |
| @@ -253,13 +322,16 @@ CONFIG_VMSPLIT_3G=y | |||
| 253 | # CONFIG_VMSPLIT_2G is not set | 322 | # CONFIG_VMSPLIT_2G is not set |
| 254 | # CONFIG_VMSPLIT_1G is not set | 323 | # CONFIG_VMSPLIT_1G is not set |
| 255 | CONFIG_PAGE_OFFSET=0xC0000000 | 324 | CONFIG_PAGE_OFFSET=0xC0000000 |
| 325 | # CONFIG_PREEMPT_NONE is not set | ||
| 326 | CONFIG_PREEMPT_VOLUNTARY=y | ||
| 256 | # CONFIG_PREEMPT is not set | 327 | # CONFIG_PREEMPT is not set |
| 257 | CONFIG_HZ=128 | 328 | CONFIG_HZ=128 |
| 329 | # CONFIG_THUMB2_KERNEL is not set | ||
| 258 | CONFIG_AEABI=y | 330 | CONFIG_AEABI=y |
| 259 | CONFIG_OABI_COMPAT=y | 331 | CONFIG_OABI_COMPAT=y |
| 260 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 261 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | 332 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
| 262 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | 333 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set |
| 334 | # CONFIG_HIGHMEM is not set | ||
| 263 | CONFIG_SELECT_MEMORY_MODEL=y | 335 | CONFIG_SELECT_MEMORY_MODEL=y |
| 264 | CONFIG_FLATMEM_MANUAL=y | 336 | CONFIG_FLATMEM_MANUAL=y |
| 265 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 337 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| @@ -268,13 +340,14 @@ CONFIG_FLATMEM=y | |||
| 268 | CONFIG_FLAT_NODE_MEM_MAP=y | 340 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 269 | CONFIG_PAGEFLAGS_EXTENDED=y | 341 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 270 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 342 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 271 | # CONFIG_RESOURCES_64BIT is not set | ||
| 272 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 343 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 273 | CONFIG_ZONE_DMA_FLAG=0 | 344 | CONFIG_ZONE_DMA_FLAG=0 |
| 274 | CONFIG_VIRT_TO_BUS=y | 345 | CONFIG_VIRT_TO_BUS=y |
| 275 | CONFIG_UNEVICTABLE_LRU=y | 346 | # CONFIG_KSM is not set |
| 347 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 276 | # CONFIG_LEDS is not set | 348 | # CONFIG_LEDS is not set |
| 277 | CONFIG_ALIGNMENT_TRAP=y | 349 | CONFIG_ALIGNMENT_TRAP=y |
| 350 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 278 | 351 | ||
| 279 | # | 352 | # |
| 280 | # Boot options | 353 | # Boot options |
| @@ -366,6 +439,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 366 | # CONFIG_NETFILTER is not set | 439 | # CONFIG_NETFILTER is not set |
| 367 | # CONFIG_IP_DCCP is not set | 440 | # CONFIG_IP_DCCP is not set |
| 368 | # CONFIG_IP_SCTP is not set | 441 | # CONFIG_IP_SCTP is not set |
| 442 | # CONFIG_RDS is not set | ||
| 369 | # CONFIG_TIPC is not set | 443 | # CONFIG_TIPC is not set |
| 370 | # CONFIG_ATM is not set | 444 | # CONFIG_ATM is not set |
| 371 | # CONFIG_BRIDGE is not set | 445 | # CONFIG_BRIDGE is not set |
| @@ -379,7 +453,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 379 | # CONFIG_LAPB is not set | 453 | # CONFIG_LAPB is not set |
| 380 | # CONFIG_ECONET is not set | 454 | # CONFIG_ECONET is not set |
| 381 | # CONFIG_WAN_ROUTER is not set | 455 | # CONFIG_WAN_ROUTER is not set |
| 456 | # CONFIG_PHONET is not set | ||
| 457 | # CONFIG_IEEE802154 is not set | ||
| 382 | # CONFIG_NET_SCHED is not set | 458 | # CONFIG_NET_SCHED is not set |
| 459 | # CONFIG_DCB is not set | ||
| 383 | 460 | ||
| 384 | # | 461 | # |
| 385 | # Network testing | 462 | # Network testing |
| @@ -390,8 +467,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 390 | # CONFIG_IRDA is not set | 467 | # CONFIG_IRDA is not set |
| 391 | # CONFIG_BT is not set | 468 | # CONFIG_BT is not set |
| 392 | # CONFIG_AF_RXRPC is not set | 469 | # CONFIG_AF_RXRPC is not set |
| 393 | # CONFIG_PHONET is not set | 470 | CONFIG_WIRELESS=y |
| 394 | # CONFIG_WIRELESS is not set | 471 | # CONFIG_CFG80211 is not set |
| 472 | # CONFIG_LIB80211 is not set | ||
| 473 | |||
| 474 | # | ||
| 475 | # CFG80211 needs to be enabled for MAC80211 | ||
| 476 | # | ||
| 477 | # CONFIG_WIMAX is not set | ||
| 395 | # CONFIG_RFKILL is not set | 478 | # CONFIG_RFKILL is not set |
| 396 | # CONFIG_NET_9P is not set | 479 | # CONFIG_NET_9P is not set |
| 397 | 480 | ||
| @@ -403,6 +486,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 403 | # Generic Driver Options | 486 | # Generic Driver Options |
| 404 | # | 487 | # |
| 405 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 488 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 489 | CONFIG_DEVTMPFS=y | ||
| 490 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 406 | CONFIG_STANDALONE=y | 491 | CONFIG_STANDALONE=y |
| 407 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 492 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 408 | # CONFIG_FW_LOADER is not set | 493 | # CONFIG_FW_LOADER is not set |
| @@ -412,6 +497,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y | |||
| 412 | # CONFIG_CONNECTOR is not set | 497 | # CONFIG_CONNECTOR is not set |
| 413 | CONFIG_MTD=y | 498 | CONFIG_MTD=y |
| 414 | # CONFIG_MTD_DEBUG is not set | 499 | # CONFIG_MTD_DEBUG is not set |
| 500 | # CONFIG_MTD_TESTS is not set | ||
| 415 | # CONFIG_MTD_CONCAT is not set | 501 | # CONFIG_MTD_CONCAT is not set |
| 416 | CONFIG_MTD_PARTITIONS=y | 502 | CONFIG_MTD_PARTITIONS=y |
| 417 | # CONFIG_MTD_REDBOOT_PARTS is not set | 503 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| @@ -462,6 +548,7 @@ CONFIG_MTD_CFI_I2=y | |||
| 462 | # | 548 | # |
| 463 | # CONFIG_MTD_DATAFLASH is not set | 549 | # CONFIG_MTD_DATAFLASH is not set |
| 464 | # CONFIG_MTD_M25P80 is not set | 550 | # CONFIG_MTD_M25P80 is not set |
| 551 | # CONFIG_MTD_SST25L is not set | ||
| 465 | # CONFIG_MTD_SLRAM is not set | 552 | # CONFIG_MTD_SLRAM is not set |
| 466 | # CONFIG_MTD_PHRAM is not set | 553 | # CONFIG_MTD_PHRAM is not set |
| 467 | # CONFIG_MTD_MTDRAM is not set | 554 | # CONFIG_MTD_MTDRAM is not set |
| @@ -478,6 +565,9 @@ CONFIG_MTD_NAND=y | |||
| 478 | # CONFIG_MTD_NAND_ECC_SMC is not set | 565 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 479 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | 566 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set |
| 480 | # CONFIG_MTD_NAND_GPIO is not set | 567 | # CONFIG_MTD_NAND_GPIO is not set |
| 568 | CONFIG_MTD_NAND_OMAP2=y | ||
| 569 | CONFIG_MTD_NAND_OMAP_PREFETCH=y | ||
| 570 | # CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set | ||
| 481 | CONFIG_MTD_NAND_IDS=y | 571 | CONFIG_MTD_NAND_IDS=y |
| 482 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 572 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 483 | # CONFIG_MTD_NAND_NANDSIM is not set | 573 | # CONFIG_MTD_NAND_NANDSIM is not set |
| @@ -486,6 +576,11 @@ CONFIG_MTD_NAND_IDS=y | |||
| 486 | # CONFIG_MTD_ONENAND is not set | 576 | # CONFIG_MTD_ONENAND is not set |
| 487 | 577 | ||
| 488 | # | 578 | # |
| 579 | # LPDDR flash memory drivers | ||
| 580 | # | ||
| 581 | # CONFIG_MTD_LPDDR is not set | ||
| 582 | |||
| 583 | # | ||
| 489 | # UBI - Unsorted block images | 584 | # UBI - Unsorted block images |
| 490 | # | 585 | # |
| 491 | # CONFIG_MTD_UBI is not set | 586 | # CONFIG_MTD_UBI is not set |
| @@ -494,6 +589,10 @@ CONFIG_BLK_DEV=y | |||
| 494 | # CONFIG_BLK_DEV_COW_COMMON is not set | 589 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 495 | CONFIG_BLK_DEV_LOOP=y | 590 | CONFIG_BLK_DEV_LOOP=y |
| 496 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 591 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| 592 | |||
| 593 | # | ||
| 594 | # DRBD disabled because PROC_FS, INET or CONNECTOR not selected | ||
| 595 | # | ||
| 497 | # CONFIG_BLK_DEV_NBD is not set | 596 | # CONFIG_BLK_DEV_NBD is not set |
| 498 | # CONFIG_BLK_DEV_UB is not set | 597 | # CONFIG_BLK_DEV_UB is not set |
| 499 | CONFIG_BLK_DEV_RAM=y | 598 | CONFIG_BLK_DEV_RAM=y |
| @@ -502,7 +601,25 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 | |||
| 502 | # CONFIG_BLK_DEV_XIP is not set | 601 | # CONFIG_BLK_DEV_XIP is not set |
| 503 | # CONFIG_CDROM_PKTCDVD is not set | 602 | # CONFIG_CDROM_PKTCDVD is not set |
| 504 | # CONFIG_ATA_OVER_ETH is not set | 603 | # CONFIG_ATA_OVER_ETH is not set |
| 505 | # CONFIG_MISC_DEVICES is not set | 604 | # CONFIG_MG_DISK is not set |
| 605 | CONFIG_MISC_DEVICES=y | ||
| 606 | # CONFIG_AD525X_DPOT is not set | ||
| 607 | # CONFIG_ICS932S401 is not set | ||
| 608 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 609 | # CONFIG_ISL29003 is not set | ||
| 610 | # CONFIG_DS1682 is not set | ||
| 611 | # CONFIG_TI_DAC7512 is not set | ||
| 612 | # CONFIG_C2PORT is not set | ||
| 613 | |||
| 614 | # | ||
| 615 | # EEPROM support | ||
| 616 | # | ||
| 617 | # CONFIG_EEPROM_AT24 is not set | ||
| 618 | # CONFIG_EEPROM_AT25 is not set | ||
| 619 | # CONFIG_EEPROM_LEGACY is not set | ||
| 620 | # CONFIG_EEPROM_MAX6875 is not set | ||
| 621 | # CONFIG_EEPROM_93CX6 is not set | ||
| 622 | # CONFIG_IWMC3200TOP is not set | ||
| 506 | CONFIG_HAVE_IDE=y | 623 | CONFIG_HAVE_IDE=y |
| 507 | # CONFIG_IDE is not set | 624 | # CONFIG_IDE is not set |
| 508 | 625 | ||
| @@ -525,10 +642,6 @@ CONFIG_BLK_DEV_SD=y | |||
| 525 | # CONFIG_BLK_DEV_SR is not set | 642 | # CONFIG_BLK_DEV_SR is not set |
| 526 | # CONFIG_CHR_DEV_SG is not set | 643 | # CONFIG_CHR_DEV_SG is not set |
| 527 | # CONFIG_CHR_DEV_SCH is not set | 644 | # CONFIG_CHR_DEV_SCH is not set |
| 528 | |||
| 529 | # | ||
| 530 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 531 | # | ||
| 532 | # CONFIG_SCSI_MULTI_LUN is not set | 645 | # CONFIG_SCSI_MULTI_LUN is not set |
| 533 | # CONFIG_SCSI_CONSTANTS is not set | 646 | # CONFIG_SCSI_CONSTANTS is not set |
| 534 | # CONFIG_SCSI_LOGGING is not set | 647 | # CONFIG_SCSI_LOGGING is not set |
| @@ -545,8 +658,11 @@ CONFIG_SCSI_WAIT_SCAN=m | |||
| 545 | # CONFIG_SCSI_SRP_ATTRS is not set | 658 | # CONFIG_SCSI_SRP_ATTRS is not set |
| 546 | CONFIG_SCSI_LOWLEVEL=y | 659 | CONFIG_SCSI_LOWLEVEL=y |
| 547 | # CONFIG_ISCSI_TCP is not set | 660 | # CONFIG_ISCSI_TCP is not set |
| 661 | # CONFIG_LIBFC is not set | ||
| 662 | # CONFIG_LIBFCOE is not set | ||
| 548 | # CONFIG_SCSI_DEBUG is not set | 663 | # CONFIG_SCSI_DEBUG is not set |
| 549 | # CONFIG_SCSI_DH is not set | 664 | # CONFIG_SCSI_DH is not set |
| 665 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 550 | # CONFIG_ATA is not set | 666 | # CONFIG_ATA is not set |
| 551 | # CONFIG_MD is not set | 667 | # CONFIG_MD is not set |
| 552 | CONFIG_NETDEVICES=y | 668 | CONFIG_NETDEVICES=y |
| @@ -559,13 +675,13 @@ CONFIG_NETDEVICES=y | |||
| 559 | # CONFIG_NET_ETHERNET is not set | 675 | # CONFIG_NET_ETHERNET is not set |
| 560 | # CONFIG_NETDEV_1000 is not set | 676 | # CONFIG_NETDEV_1000 is not set |
| 561 | # CONFIG_NETDEV_10000 is not set | 677 | # CONFIG_NETDEV_10000 is not set |
| 678 | CONFIG_WLAN=y | ||
| 679 | # CONFIG_USB_ZD1201 is not set | ||
| 680 | # CONFIG_HOSTAP is not set | ||
| 562 | 681 | ||
| 563 | # | 682 | # |
| 564 | # Wireless LAN | 683 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| 565 | # | 684 | # |
| 566 | # CONFIG_WLAN_PRE80211 is not set | ||
| 567 | # CONFIG_WLAN_80211 is not set | ||
| 568 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 569 | 685 | ||
| 570 | # | 686 | # |
| 571 | # USB Network Adapters | 687 | # USB Network Adapters |
| @@ -582,6 +698,7 @@ CONFIG_NETDEVICES=y | |||
| 582 | # CONFIG_NETPOLL is not set | 698 | # CONFIG_NETPOLL is not set |
| 583 | # CONFIG_NET_POLL_CONTROLLER is not set | 699 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 584 | # CONFIG_ISDN is not set | 700 | # CONFIG_ISDN is not set |
| 701 | # CONFIG_PHONE is not set | ||
| 585 | 702 | ||
| 586 | # | 703 | # |
| 587 | # Input device support | 704 | # Input device support |
| @@ -589,6 +706,7 @@ CONFIG_NETDEVICES=y | |||
| 589 | CONFIG_INPUT=y | 706 | CONFIG_INPUT=y |
| 590 | # CONFIG_INPUT_FF_MEMLESS is not set | 707 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 591 | # CONFIG_INPUT_POLLDEV is not set | 708 | # CONFIG_INPUT_POLLDEV is not set |
| 709 | # CONFIG_INPUT_SPARSEKMAP is not set | ||
| 592 | 710 | ||
| 593 | # | 711 | # |
| 594 | # Userland interfaces | 712 | # Userland interfaces |
| @@ -605,13 +723,20 @@ CONFIG_INPUT_EVDEV=y | |||
| 605 | # Input Device Drivers | 723 | # Input Device Drivers |
| 606 | # | 724 | # |
| 607 | CONFIG_INPUT_KEYBOARD=y | 725 | CONFIG_INPUT_KEYBOARD=y |
| 726 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 608 | # CONFIG_KEYBOARD_ATKBD is not set | 727 | # CONFIG_KEYBOARD_ATKBD is not set |
| 609 | # CONFIG_KEYBOARD_SUNKBD is not set | 728 | # CONFIG_QT2160 is not set |
| 610 | # CONFIG_KEYBOARD_LKKBD is not set | 729 | # CONFIG_KEYBOARD_LKKBD is not set |
| 611 | # CONFIG_KEYBOARD_XTKBD is not set | 730 | CONFIG_KEYBOARD_GPIO=y |
| 731 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 732 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 733 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 612 | # CONFIG_KEYBOARD_NEWTON is not set | 734 | # CONFIG_KEYBOARD_NEWTON is not set |
| 735 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
| 613 | # CONFIG_KEYBOARD_STOWAWAY is not set | 736 | # CONFIG_KEYBOARD_STOWAWAY is not set |
| 614 | CONFIG_KEYBOARD_GPIO=y | 737 | # CONFIG_KEYBOARD_SUNKBD is not set |
| 738 | CONFIG_KEYBOARD_TWL4030=y | ||
| 739 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 615 | CONFIG_INPUT_MOUSE=y | 740 | CONFIG_INPUT_MOUSE=y |
| 616 | # CONFIG_MOUSE_PS2 is not set | 741 | # CONFIG_MOUSE_PS2 is not set |
| 617 | # CONFIG_MOUSE_SERIAL is not set | 742 | # CONFIG_MOUSE_SERIAL is not set |
| @@ -619,13 +744,22 @@ CONFIG_INPUT_MOUSE=y | |||
| 619 | # CONFIG_MOUSE_BCM5974 is not set | 744 | # CONFIG_MOUSE_BCM5974 is not set |
| 620 | # CONFIG_MOUSE_VSXXXAA is not set | 745 | # CONFIG_MOUSE_VSXXXAA is not set |
| 621 | # CONFIG_MOUSE_GPIO is not set | 746 | # CONFIG_MOUSE_GPIO is not set |
| 747 | # CONFIG_MOUSE_SYNAPTICS_I2C is not set | ||
| 622 | # CONFIG_INPUT_JOYSTICK is not set | 748 | # CONFIG_INPUT_JOYSTICK is not set |
| 623 | # CONFIG_INPUT_TABLET is not set | 749 | # CONFIG_INPUT_TABLET is not set |
| 624 | CONFIG_INPUT_TOUCHSCREEN=y | 750 | CONFIG_INPUT_TOUCHSCREEN=y |
| 625 | CONFIG_TOUCHSCREEN_ADS7846=y | 751 | CONFIG_TOUCHSCREEN_ADS7846=y |
| 752 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 753 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 754 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 755 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 756 | # CONFIG_TOUCHSCREEN_DYNAPRO is not set | ||
| 757 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
| 626 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 758 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 627 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 759 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 628 | # CONFIG_TOUCHSCREEN_ELO is not set | 760 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 761 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 762 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
| 629 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 763 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 630 | # CONFIG_TOUCHSCREEN_INEXIO is not set | 764 | # CONFIG_TOUCHSCREEN_INEXIO is not set |
| 631 | # CONFIG_TOUCHSCREEN_MK712 is not set | 765 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| @@ -634,8 +768,18 @@ CONFIG_TOUCHSCREEN_ADS7846=y | |||
| 634 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 768 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 635 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 769 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 636 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | 770 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set |
| 771 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 772 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 637 | CONFIG_INPUT_MISC=y | 773 | CONFIG_INPUT_MISC=y |
| 774 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 775 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 776 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 777 | # CONFIG_INPUT_POWERMATE is not set | ||
| 778 | # CONFIG_INPUT_YEALINK is not set | ||
| 779 | # CONFIG_INPUT_CM109 is not set | ||
| 638 | CONFIG_INPUT_TWL4030_PWRBUTTON=y | 780 | CONFIG_INPUT_TWL4030_PWRBUTTON=y |
| 781 | # CONFIG_INPUT_UINPUT is not set | ||
| 782 | # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set | ||
| 639 | 783 | ||
| 640 | # | 784 | # |
| 641 | # Hardware I/O ports | 785 | # Hardware I/O ports |
| @@ -670,18 +814,21 @@ CONFIG_SERIAL_8250_RSA=y | |||
| 670 | # | 814 | # |
| 671 | # Non-8250 serial port support | 815 | # Non-8250 serial port support |
| 672 | # | 816 | # |
| 817 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 673 | CONFIG_SERIAL_CORE=y | 818 | CONFIG_SERIAL_CORE=y |
| 674 | CONFIG_SERIAL_CORE_CONSOLE=y | 819 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 675 | CONFIG_UNIX98_PTYS=y | 820 | CONFIG_UNIX98_PTYS=y |
| 821 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 676 | # CONFIG_LEGACY_PTYS is not set | 822 | # CONFIG_LEGACY_PTYS is not set |
| 677 | # CONFIG_IPMI_HANDLER is not set | 823 | # CONFIG_IPMI_HANDLER is not set |
| 678 | CONFIG_HW_RANDOM=y | 824 | CONFIG_HW_RANDOM=y |
| 679 | # CONFIG_NVRAM is not set | 825 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set |
| 680 | # CONFIG_R3964 is not set | 826 | # CONFIG_R3964 is not set |
| 681 | # CONFIG_RAW_DRIVER is not set | 827 | # CONFIG_RAW_DRIVER is not set |
| 682 | # CONFIG_TCG_TPM is not set | 828 | # CONFIG_TCG_TPM is not set |
| 683 | CONFIG_I2C=y | 829 | CONFIG_I2C=y |
| 684 | CONFIG_I2C_BOARDINFO=y | 830 | CONFIG_I2C_BOARDINFO=y |
| 831 | CONFIG_I2C_COMPAT=y | ||
| 685 | CONFIG_I2C_CHARDEV=y | 832 | CONFIG_I2C_CHARDEV=y |
| 686 | CONFIG_I2C_HELPER_AUTO=y | 833 | CONFIG_I2C_HELPER_AUTO=y |
| 687 | 834 | ||
| @@ -692,10 +839,12 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 692 | # | 839 | # |
| 693 | # I2C system bus drivers (mostly embedded / system-on-chip) | 840 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 694 | # | 841 | # |
| 842 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 695 | # CONFIG_I2C_GPIO is not set | 843 | # CONFIG_I2C_GPIO is not set |
| 696 | # CONFIG_I2C_OCORES is not set | 844 | # CONFIG_I2C_OCORES is not set |
| 697 | CONFIG_I2C_OMAP=y | 845 | CONFIG_I2C_OMAP=y |
| 698 | # CONFIG_I2C_SIMTEC is not set | 846 | # CONFIG_I2C_SIMTEC is not set |
| 847 | # CONFIG_I2C_XILINX is not set | ||
| 699 | 848 | ||
| 700 | # | 849 | # |
| 701 | # External I2C/SMBus adapter drivers | 850 | # External I2C/SMBus adapter drivers |
| @@ -709,21 +858,6 @@ CONFIG_I2C_OMAP=y | |||
| 709 | # | 858 | # |
| 710 | # CONFIG_I2C_PCA_PLATFORM is not set | 859 | # CONFIG_I2C_PCA_PLATFORM is not set |
| 711 | # CONFIG_I2C_STUB is not set | 860 | # CONFIG_I2C_STUB is not set |
| 712 | |||
| 713 | # | ||
| 714 | # Miscellaneous I2C Chip support | ||
| 715 | # | ||
| 716 | # CONFIG_DS1682 is not set | ||
| 717 | # CONFIG_EEPROM_AT24 is not set | ||
| 718 | # CONFIG_EEPROM_LEGACY is not set | ||
| 719 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 720 | # CONFIG_PCF8575 is not set | ||
| 721 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 722 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 723 | # CONFIG_ISP1301_OMAP is not set | ||
| 724 | # CONFIG_TPS65010 is not set | ||
| 725 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 726 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 727 | # CONFIG_I2C_DEBUG_CORE is not set | 861 | # CONFIG_I2C_DEBUG_CORE is not set |
| 728 | # CONFIG_I2C_DEBUG_ALGO is not set | 862 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 729 | # CONFIG_I2C_DEBUG_BUS is not set | 863 | # CONFIG_I2C_DEBUG_BUS is not set |
| @@ -736,14 +870,21 @@ CONFIG_SPI_MASTER=y | |||
| 736 | # SPI Master Controller Drivers | 870 | # SPI Master Controller Drivers |
| 737 | # | 871 | # |
| 738 | # CONFIG_SPI_BITBANG is not set | 872 | # CONFIG_SPI_BITBANG is not set |
| 873 | # CONFIG_SPI_GPIO is not set | ||
| 739 | CONFIG_SPI_OMAP24XX=y | 874 | CONFIG_SPI_OMAP24XX=y |
| 875 | # CONFIG_SPI_XILINX is not set | ||
| 876 | # CONFIG_SPI_DESIGNWARE is not set | ||
| 740 | 877 | ||
| 741 | # | 878 | # |
| 742 | # SPI Protocol Masters | 879 | # SPI Protocol Masters |
| 743 | # | 880 | # |
| 744 | # CONFIG_EEPROM_AT25 is not set | ||
| 745 | # CONFIG_SPI_SPIDEV is not set | 881 | # CONFIG_SPI_SPIDEV is not set |
| 746 | # CONFIG_SPI_TLE62X0 is not set | 882 | # CONFIG_SPI_TLE62X0 is not set |
| 883 | |||
| 884 | # | ||
| 885 | # PPS support | ||
| 886 | # | ||
| 887 | # CONFIG_PPS is not set | ||
| 747 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 888 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 748 | CONFIG_GPIOLIB=y | 889 | CONFIG_GPIOLIB=y |
| 749 | # CONFIG_DEBUG_GPIO is not set | 890 | # CONFIG_DEBUG_GPIO is not set |
| @@ -760,6 +901,7 @@ CONFIG_GPIOLIB=y | |||
| 760 | # CONFIG_GPIO_PCA953X is not set | 901 | # CONFIG_GPIO_PCA953X is not set |
| 761 | # CONFIG_GPIO_PCF857X is not set | 902 | # CONFIG_GPIO_PCF857X is not set |
| 762 | CONFIG_GPIO_TWL4030=y | 903 | CONFIG_GPIO_TWL4030=y |
| 904 | # CONFIG_GPIO_ADP5588 is not set | ||
| 763 | 905 | ||
| 764 | # | 906 | # |
| 765 | # PCI GPIO expanders: | 907 | # PCI GPIO expanders: |
| @@ -770,11 +912,16 @@ CONFIG_GPIO_TWL4030=y | |||
| 770 | # | 912 | # |
| 771 | # CONFIG_GPIO_MAX7301 is not set | 913 | # CONFIG_GPIO_MAX7301 is not set |
| 772 | # CONFIG_GPIO_MCP23S08 is not set | 914 | # CONFIG_GPIO_MCP23S08 is not set |
| 915 | # CONFIG_GPIO_MC33880 is not set | ||
| 916 | |||
| 917 | # | ||
| 918 | # AC97 GPIO expanders: | ||
| 919 | # | ||
| 773 | # CONFIG_W1 is not set | 920 | # CONFIG_W1 is not set |
| 774 | # CONFIG_POWER_SUPPLY is not set | 921 | # CONFIG_POWER_SUPPLY is not set |
| 775 | # CONFIG_HWMON is not set | 922 | # CONFIG_HWMON is not set |
| 923 | # CONFIG_ALS is not set | ||
| 776 | # CONFIG_THERMAL is not set | 924 | # CONFIG_THERMAL is not set |
| 777 | # CONFIG_THERMAL_HWMON is not set | ||
| 778 | # CONFIG_WATCHDOG is not set | 925 | # CONFIG_WATCHDOG is not set |
| 779 | CONFIG_SSB_POSSIBLE=y | 926 | CONFIG_SSB_POSSIBLE=y |
| 780 | 927 | ||
| @@ -786,44 +933,111 @@ CONFIG_SSB_POSSIBLE=y | |||
| 786 | # | 933 | # |
| 787 | # Multifunction device drivers | 934 | # Multifunction device drivers |
| 788 | # | 935 | # |
| 789 | # CONFIG_MFD_CORE is not set | 936 | CONFIG_MFD_CORE=y |
| 937 | # CONFIG_MFD_88PM860X is not set | ||
| 790 | # CONFIG_MFD_SM501 is not set | 938 | # CONFIG_MFD_SM501 is not set |
| 791 | # CONFIG_MFD_ASIC3 is not set | 939 | # CONFIG_MFD_ASIC3 is not set |
| 792 | # CONFIG_HTC_EGPIO is not set | 940 | # CONFIG_HTC_EGPIO is not set |
| 793 | # CONFIG_HTC_PASIC3 is not set | 941 | # CONFIG_HTC_PASIC3 is not set |
| 942 | # CONFIG_HTC_I2CPLD is not set | ||
| 943 | # CONFIG_TPS65010 is not set | ||
| 794 | CONFIG_TWL4030_CORE=y | 944 | CONFIG_TWL4030_CORE=y |
| 945 | CONFIG_TWL4030_POWER=y | ||
| 946 | CONFIG_TWL4030_CODEC=y | ||
| 795 | # CONFIG_MFD_TMIO is not set | 947 | # CONFIG_MFD_TMIO is not set |
| 796 | # CONFIG_MFD_T7L66XB is not set | 948 | # CONFIG_MFD_T7L66XB is not set |
| 797 | # CONFIG_MFD_TC6387XB is not set | 949 | # CONFIG_MFD_TC6387XB is not set |
| 798 | # CONFIG_MFD_TC6393XB is not set | 950 | # CONFIG_MFD_TC6393XB is not set |
| 799 | # CONFIG_PMIC_DA903X is not set | 951 | # CONFIG_PMIC_DA903X is not set |
| 952 | # CONFIG_PMIC_ADP5520 is not set | ||
| 953 | # CONFIG_MFD_MAX8925 is not set | ||
| 800 | # CONFIG_MFD_WM8400 is not set | 954 | # CONFIG_MFD_WM8400 is not set |
| 955 | # CONFIG_MFD_WM831X is not set | ||
| 801 | # CONFIG_MFD_WM8350_I2C is not set | 956 | # CONFIG_MFD_WM8350_I2C is not set |
| 802 | 957 | # CONFIG_MFD_WM8994 is not set | |
| 803 | # | 958 | # CONFIG_MFD_PCF50633 is not set |
| 804 | # Multimedia devices | 959 | # CONFIG_MFD_MC13783 is not set |
| 805 | # | 960 | # CONFIG_AB3100_CORE is not set |
| 806 | 961 | # CONFIG_EZX_PCAP is not set | |
| 807 | # | 962 | # CONFIG_AB4500_CORE is not set |
| 808 | # Multimedia core support | 963 | CONFIG_REGULATOR=y |
| 809 | # | 964 | CONFIG_REGULATOR_DEBUG=y |
| 810 | # CONFIG_VIDEO_DEV is not set | 965 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set |
| 811 | # CONFIG_DVB_CORE is not set | 966 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set |
| 812 | # CONFIG_VIDEO_MEDIA is not set | 967 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set |
| 813 | 968 | # CONFIG_REGULATOR_BQ24022 is not set | |
| 814 | # | 969 | # CONFIG_REGULATOR_MAX1586 is not set |
| 815 | # Multimedia drivers | 970 | # CONFIG_REGULATOR_MAX8649 is not set |
| 816 | # | 971 | # CONFIG_REGULATOR_MAX8660 is not set |
| 817 | CONFIG_DAB=y | 972 | CONFIG_REGULATOR_TWL4030=y |
| 818 | # CONFIG_USB_DABUSB is not set | 973 | # CONFIG_REGULATOR_LP3971 is not set |
| 974 | # CONFIG_REGULATOR_TPS65023 is not set | ||
| 975 | # CONFIG_REGULATOR_TPS6507X is not set | ||
| 976 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 819 | 977 | ||
| 820 | # | 978 | # |
| 821 | # Graphics support | 979 | # Graphics support |
| 822 | # | 980 | # |
| 823 | # CONFIG_VGASTATE is not set | 981 | # CONFIG_VGASTATE is not set |
| 824 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | 982 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 825 | # CONFIG_FB is not set | 983 | CONFIG_FB=y |
| 826 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 984 | # CONFIG_FIRMWARE_EDID is not set |
| 985 | # CONFIG_FB_DDC is not set | ||
| 986 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 987 | CONFIG_FB_CFB_FILLRECT=y | ||
| 988 | CONFIG_FB_CFB_COPYAREA=y | ||
| 989 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 990 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 991 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 992 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 993 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 994 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 995 | # CONFIG_FB_SYS_FOPS is not set | ||
| 996 | # CONFIG_FB_SVGALIB is not set | ||
| 997 | # CONFIG_FB_MACMODES is not set | ||
| 998 | # CONFIG_FB_BACKLIGHT is not set | ||
| 999 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 1000 | # CONFIG_FB_TILEBLITTING is not set | ||
| 1001 | |||
| 1002 | # | ||
| 1003 | # Frame buffer hardware drivers | ||
| 1004 | # | ||
| 1005 | # CONFIG_FB_S1D13XXX is not set | ||
| 1006 | # CONFIG_FB_TMIO is not set | ||
| 1007 | # CONFIG_FB_VIRTUAL is not set | ||
| 1008 | # CONFIG_FB_METRONOME is not set | ||
| 1009 | # CONFIG_FB_MB862XX is not set | ||
| 1010 | # CONFIG_FB_BROADSHEET is not set | ||
| 1011 | # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set | ||
| 1012 | CONFIG_OMAP2_VRAM=y | ||
| 1013 | CONFIG_OMAP2_VRFB=y | ||
| 1014 | CONFIG_OMAP2_DSS=y | ||
| 1015 | CONFIG_OMAP2_VRAM_SIZE=0 | ||
| 1016 | CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y | ||
| 1017 | # CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set | ||
| 1018 | # CONFIG_OMAP2_DSS_RFBI is not set | ||
| 1019 | CONFIG_OMAP2_DSS_VENC=y | ||
| 1020 | # CONFIG_OMAP2_DSS_SDI is not set | ||
| 1021 | # CONFIG_OMAP2_DSS_DSI is not set | ||
| 1022 | # CONFIG_OMAP2_DSS_FAKE_VSYNC is not set | ||
| 1023 | CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 | ||
| 1024 | CONFIG_FB_OMAP2=y | ||
| 1025 | CONFIG_FB_OMAP2_DEBUG_SUPPORT=y | ||
| 1026 | # CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set | ||
| 1027 | CONFIG_FB_OMAP2_NUM_FBS=3 | ||
| 1028 | |||
| 1029 | # | ||
| 1030 | # OMAP2/3 Display Device Drivers | ||
| 1031 | # | ||
| 1032 | # CONFIG_PANEL_GENERIC is not set | ||
| 1033 | # CONFIG_PANEL_SHARP_LS037V7DW01 is not set | ||
| 1034 | # CONFIG_PANEL_SHARP_LQ043T1DG01 is not set | ||
| 1035 | # CONFIG_PANEL_TOPPOLY_TDO35S is not set | ||
| 1036 | CONFIG_PANEL_TPO_TD043MTEA1=y | ||
| 1037 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1038 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 1039 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 1040 | CONFIG_BACKLIGHT_GENERIC=y | ||
| 827 | 1041 | ||
| 828 | # | 1042 | # |
| 829 | # Display device support | 1043 | # Display device support |
| @@ -835,6 +1049,16 @@ CONFIG_DAB=y | |||
| 835 | # | 1049 | # |
| 836 | # CONFIG_VGA_CONSOLE is not set | 1050 | # CONFIG_VGA_CONSOLE is not set |
| 837 | CONFIG_DUMMY_CONSOLE=y | 1051 | CONFIG_DUMMY_CONSOLE=y |
| 1052 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 1053 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 1054 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 1055 | # CONFIG_FONTS is not set | ||
| 1056 | CONFIG_FONT_8x8=y | ||
| 1057 | CONFIG_FONT_8x16=y | ||
| 1058 | CONFIG_LOGO=y | ||
| 1059 | CONFIG_LOGO_LINUX_MONO=y | ||
| 1060 | CONFIG_LOGO_LINUX_VGA16=y | ||
| 1061 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 838 | CONFIG_SOUND=y | 1062 | CONFIG_SOUND=y |
| 839 | CONFIG_SOUND_OSS_CORE=y | 1063 | CONFIG_SOUND_OSS_CORE=y |
| 840 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y | 1064 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y |
| @@ -842,25 +1066,43 @@ CONFIG_SND=y | |||
| 842 | CONFIG_SND_TIMER=y | 1066 | CONFIG_SND_TIMER=y |
| 843 | CONFIG_SND_PCM=y | 1067 | CONFIG_SND_PCM=y |
| 844 | CONFIG_SND_JACK=y | 1068 | CONFIG_SND_JACK=y |
| 1069 | # CONFIG_SND_SEQUENCER is not set | ||
| 845 | CONFIG_SND_OSSEMUL=y | 1070 | CONFIG_SND_OSSEMUL=y |
| 846 | CONFIG_SND_MIXER_OSS=y | 1071 | CONFIG_SND_MIXER_OSS=y |
| 847 | CONFIG_SND_PCM_OSS=y | 1072 | CONFIG_SND_PCM_OSS=y |
| 848 | CONFIG_SND_PCM_OSS_PLUGINS=y | 1073 | CONFIG_SND_PCM_OSS_PLUGINS=y |
| 1074 | # CONFIG_SND_HRTIMER is not set | ||
| 1075 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 849 | CONFIG_SND_SUPPORT_OLD_API=y | 1076 | CONFIG_SND_SUPPORT_OLD_API=y |
| 850 | CONFIG_SND_VERBOSE_PROCFS=y | 1077 | CONFIG_SND_VERBOSE_PROCFS=y |
| 851 | CONFIG_SND_VERBOSE_PRINTK=y | 1078 | CONFIG_SND_VERBOSE_PRINTK=y |
| 1079 | # CONFIG_SND_DEBUG is not set | ||
| 1080 | # CONFIG_SND_RAWMIDI_SEQ is not set | ||
| 1081 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
| 1082 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
| 1083 | # CONFIG_SND_SBAWE_SEQ is not set | ||
| 1084 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 852 | CONFIG_SND_DRIVERS=y | 1085 | CONFIG_SND_DRIVERS=y |
| 1086 | # CONFIG_SND_DUMMY is not set | ||
| 1087 | # CONFIG_SND_MTPAV is not set | ||
| 1088 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1089 | # CONFIG_SND_MPU401 is not set | ||
| 1090 | CONFIG_SND_ARM=y | ||
| 1091 | CONFIG_SND_SPI=y | ||
| 853 | CONFIG_SND_USB=y | 1092 | CONFIG_SND_USB=y |
| 1093 | # CONFIG_SND_USB_AUDIO is not set | ||
| 1094 | # CONFIG_SND_USB_UA101 is not set | ||
| 1095 | # CONFIG_SND_USB_CAIAQ is not set | ||
| 854 | CONFIG_SND_SOC=y | 1096 | CONFIG_SND_SOC=y |
| 855 | CONFIG_SND_OMAP_SOC=y | 1097 | CONFIG_SND_OMAP_SOC=y |
| 856 | CONFIG_SND_OMAP_SOC_MCBSP=y | 1098 | CONFIG_SND_OMAP_SOC_MCBSP=y |
| 857 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y | 1099 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y |
| 858 | CONFIG_SND_SOC_I2C_AND_SPI=y | 1100 | CONFIG_SND_SOC_I2C_AND_SPI=y |
| 1101 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 859 | CONFIG_SND_SOC_TWL4030=y | 1102 | CONFIG_SND_SOC_TWL4030=y |
| 860 | 1103 | # CONFIG_SOUND_PRIME is not set | |
| 861 | CONFIG_HID_SUPPORT=y | 1104 | CONFIG_HID_SUPPORT=y |
| 862 | CONFIG_HID=y | 1105 | CONFIG_HID=y |
| 863 | # CONFIG_HID_DEBUG is not set | ||
| 864 | # CONFIG_HIDRAW is not set | 1106 | # CONFIG_HIDRAW is not set |
| 865 | 1107 | ||
| 866 | # | 1108 | # |
| @@ -873,31 +1115,40 @@ CONFIG_USB_HID=y | |||
| 873 | # | 1115 | # |
| 874 | # Special HID drivers | 1116 | # Special HID drivers |
| 875 | # | 1117 | # |
| 876 | # CONFIG_HID_COMPAT is not set | 1118 | # CONFIG_HID_3M_PCT is not set |
| 877 | # CONFIG_HID_A4TECH is not set | 1119 | # CONFIG_HID_A4TECH is not set |
| 878 | # CONFIG_HID_APPLE is not set | 1120 | # CONFIG_HID_APPLE is not set |
| 879 | # CONFIG_HID_BELKIN is not set | 1121 | # CONFIG_HID_BELKIN is not set |
| 880 | # CONFIG_HID_BRIGHT is not set | ||
| 881 | # CONFIG_HID_CHERRY is not set | 1122 | # CONFIG_HID_CHERRY is not set |
| 882 | # CONFIG_HID_CHICONY is not set | 1123 | # CONFIG_HID_CHICONY is not set |
| 883 | # CONFIG_HID_CYPRESS is not set | 1124 | # CONFIG_HID_CYPRESS is not set |
| 884 | # CONFIG_HID_DELL is not set | 1125 | # CONFIG_HID_DRAGONRISE is not set |
| 885 | # CONFIG_HID_EZKEY is not set | 1126 | # CONFIG_HID_EZKEY is not set |
| 1127 | # CONFIG_HID_KYE is not set | ||
| 886 | # CONFIG_HID_GYRATION is not set | 1128 | # CONFIG_HID_GYRATION is not set |
| 1129 | # CONFIG_HID_TWINHAN is not set | ||
| 1130 | # CONFIG_HID_KENSINGTON is not set | ||
| 887 | # CONFIG_HID_LOGITECH is not set | 1131 | # CONFIG_HID_LOGITECH is not set |
| 888 | # CONFIG_HID_MICROSOFT is not set | 1132 | # CONFIG_HID_MICROSOFT is not set |
| 889 | # CONFIG_HID_MONTEREY is not set | 1133 | # CONFIG_HID_MONTEREY is not set |
| 1134 | # CONFIG_HID_NTRIG is not set | ||
| 1135 | # CONFIG_HID_ORTEK is not set | ||
| 890 | # CONFIG_HID_PANTHERLORD is not set | 1136 | # CONFIG_HID_PANTHERLORD is not set |
| 891 | # CONFIG_HID_PETALYNX is not set | 1137 | # CONFIG_HID_PETALYNX is not set |
| 1138 | # CONFIG_HID_QUANTA is not set | ||
| 892 | # CONFIG_HID_SAMSUNG is not set | 1139 | # CONFIG_HID_SAMSUNG is not set |
| 893 | # CONFIG_HID_SONY is not set | 1140 | # CONFIG_HID_SONY is not set |
| 1141 | # CONFIG_HID_STANTUM is not set | ||
| 894 | # CONFIG_HID_SUNPLUS is not set | 1142 | # CONFIG_HID_SUNPLUS is not set |
| 895 | # CONFIG_THRUSTMASTER_FF is not set | 1143 | # CONFIG_HID_GREENASIA is not set |
| 896 | # CONFIG_ZEROPLUS_FF is not set | 1144 | # CONFIG_HID_SMARTJOYPLUS is not set |
| 1145 | # CONFIG_HID_TOPSEED is not set | ||
| 1146 | # CONFIG_HID_THRUSTMASTER is not set | ||
| 1147 | # CONFIG_HID_ZEROPLUS is not set | ||
| 897 | CONFIG_USB_SUPPORT=y | 1148 | CONFIG_USB_SUPPORT=y |
| 898 | CONFIG_USB_ARCH_HAS_HCD=y | 1149 | CONFIG_USB_ARCH_HAS_HCD=y |
| 899 | CONFIG_USB_ARCH_HAS_OHCI=y | 1150 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 900 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1151 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 901 | CONFIG_USB=y | 1152 | CONFIG_USB=y |
| 902 | # CONFIG_USB_DEBUG is not set | 1153 | # CONFIG_USB_DEBUG is not set |
| 903 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | 1154 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set |
| @@ -911,7 +1162,7 @@ CONFIG_USB_DEVICE_CLASS=y | |||
| 911 | # CONFIG_USB_OTG is not set | 1162 | # CONFIG_USB_OTG is not set |
| 912 | # CONFIG_USB_OTG_WHITELIST is not set | 1163 | # CONFIG_USB_OTG_WHITELIST is not set |
| 913 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | 1164 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set |
| 914 | CONFIG_USB_MON=y | 1165 | # CONFIG_USB_MON is not set |
| 915 | # CONFIG_USB_WUSB is not set | 1166 | # CONFIG_USB_WUSB is not set |
| 916 | # CONFIG_USB_WUSB_CBAF is not set | 1167 | # CONFIG_USB_WUSB_CBAF is not set |
| 917 | 1168 | ||
| @@ -919,7 +1170,13 @@ CONFIG_USB_MON=y | |||
| 919 | # USB Host Controller Drivers | 1170 | # USB Host Controller Drivers |
| 920 | # | 1171 | # |
| 921 | # CONFIG_USB_C67X00_HCD is not set | 1172 | # CONFIG_USB_C67X00_HCD is not set |
| 1173 | CONFIG_USB_EHCI_HCD=y | ||
| 1174 | # CONFIG_USB_EHCI_ROOT_HUB_TT is not set | ||
| 1175 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | ||
| 1176 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 922 | # CONFIG_USB_ISP116X_HCD is not set | 1177 | # CONFIG_USB_ISP116X_HCD is not set |
| 1178 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 1179 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 923 | # CONFIG_USB_OHCI_HCD is not set | 1180 | # CONFIG_USB_OHCI_HCD is not set |
| 924 | # CONFIG_USB_SL811_HCD is not set | 1181 | # CONFIG_USB_SL811_HCD is not set |
| 925 | # CONFIG_USB_R8A66597_HCD is not set | 1182 | # CONFIG_USB_R8A66597_HCD is not set |
| @@ -930,11 +1187,10 @@ CONFIG_USB_MUSB_SOC=y | |||
| 930 | # | 1187 | # |
| 931 | # OMAP 343x high speed USB support | 1188 | # OMAP 343x high speed USB support |
| 932 | # | 1189 | # |
| 933 | CONFIG_USB_MUSB_HOST=y | 1190 | # CONFIG_USB_MUSB_HOST is not set |
| 934 | # CONFIG_USB_MUSB_PERIPHERAL is not set | 1191 | CONFIG_USB_MUSB_PERIPHERAL=y |
| 935 | # CONFIG_USB_MUSB_OTG is not set | 1192 | # CONFIG_USB_MUSB_OTG is not set |
| 936 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | 1193 | CONFIG_USB_GADGET_MUSB_HDRC=y |
| 937 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 938 | # CONFIG_MUSB_PIO_ONLY is not set | 1194 | # CONFIG_MUSB_PIO_ONLY is not set |
| 939 | CONFIG_USB_INVENTRA_DMA=y | 1195 | CONFIG_USB_INVENTRA_DMA=y |
| 940 | # CONFIG_USB_TI_CPPI_DMA is not set | 1196 | # CONFIG_USB_TI_CPPI_DMA is not set |
| @@ -949,11 +1205,11 @@ CONFIG_USB_INVENTRA_DMA=y | |||
| 949 | # CONFIG_USB_TMC is not set | 1205 | # CONFIG_USB_TMC is not set |
| 950 | 1206 | ||
| 951 | # | 1207 | # |
| 952 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | 1208 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may |
| 953 | # | 1209 | # |
| 954 | 1210 | ||
| 955 | # | 1211 | # |
| 956 | # see USB_STORAGE Help for more information | 1212 | # also be needed; see USB_STORAGE Help for more info |
| 957 | # | 1213 | # |
| 958 | # CONFIG_USB_STORAGE is not set | 1214 | # CONFIG_USB_STORAGE is not set |
| 959 | # CONFIG_USB_LIBUSUAL is not set | 1215 | # CONFIG_USB_LIBUSUAL is not set |
| @@ -979,14 +1235,13 @@ CONFIG_USB_INVENTRA_DMA=y | |||
| 979 | # CONFIG_USB_RIO500 is not set | 1235 | # CONFIG_USB_RIO500 is not set |
| 980 | # CONFIG_USB_LEGOTOWER is not set | 1236 | # CONFIG_USB_LEGOTOWER is not set |
| 981 | # CONFIG_USB_LCD is not set | 1237 | # CONFIG_USB_LCD is not set |
| 982 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 983 | # CONFIG_USB_LED is not set | 1238 | # CONFIG_USB_LED is not set |
| 984 | # CONFIG_USB_CYPRESS_CY7C63 is not set | 1239 | # CONFIG_USB_CYPRESS_CY7C63 is not set |
| 985 | # CONFIG_USB_CYTHERM is not set | 1240 | # CONFIG_USB_CYTHERM is not set |
| 986 | # CONFIG_USB_PHIDGET is not set | ||
| 987 | # CONFIG_USB_IDMOUSE is not set | 1241 | # CONFIG_USB_IDMOUSE is not set |
| 988 | # CONFIG_USB_FTDI_ELAN is not set | 1242 | # CONFIG_USB_FTDI_ELAN is not set |
| 989 | # CONFIG_USB_APPLEDISPLAY is not set | 1243 | # CONFIG_USB_APPLEDISPLAY is not set |
| 1244 | # CONFIG_USB_SISUSBVGA is not set | ||
| 990 | # CONFIG_USB_LD is not set | 1245 | # CONFIG_USB_LD is not set |
| 991 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1246 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 992 | # CONFIG_USB_IOWARRIOR is not set | 1247 | # CONFIG_USB_IOWARRIOR is not set |
| @@ -1002,27 +1257,46 @@ CONFIG_USB_GADGET_SELECTED=y | |||
| 1002 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | 1257 | # CONFIG_USB_GADGET_ATMEL_USBA is not set |
| 1003 | # CONFIG_USB_GADGET_FSL_USB2 is not set | 1258 | # CONFIG_USB_GADGET_FSL_USB2 is not set |
| 1004 | # CONFIG_USB_GADGET_LH7A40X is not set | 1259 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 1005 | CONFIG_USB_GADGET_OMAP=y | 1260 | # CONFIG_USB_GADGET_OMAP is not set |
| 1006 | CONFIG_USB_OMAP=y | ||
| 1007 | # CONFIG_USB_GADGET_PXA25X is not set | 1261 | # CONFIG_USB_GADGET_PXA25X is not set |
| 1262 | # CONFIG_USB_GADGET_R8A66597 is not set | ||
| 1008 | # CONFIG_USB_GADGET_PXA27X is not set | 1263 | # CONFIG_USB_GADGET_PXA27X is not set |
| 1264 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
| 1265 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1009 | # CONFIG_USB_GADGET_S3C2410 is not set | 1266 | # CONFIG_USB_GADGET_S3C2410 is not set |
| 1010 | # CONFIG_USB_GADGET_M66592 is not set | 1267 | # CONFIG_USB_GADGET_M66592 is not set |
| 1011 | # CONFIG_USB_GADGET_AMD5536UDC is not set | 1268 | # CONFIG_USB_GADGET_AMD5536UDC is not set |
| 1012 | # CONFIG_USB_GADGET_FSL_QE is not set | 1269 | # CONFIG_USB_GADGET_FSL_QE is not set |
| 1270 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1013 | # CONFIG_USB_GADGET_NET2280 is not set | 1271 | # CONFIG_USB_GADGET_NET2280 is not set |
| 1014 | # CONFIG_USB_GADGET_GOKU is not set | 1272 | # CONFIG_USB_GADGET_GOKU is not set |
| 1273 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 1015 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 1274 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| 1016 | # CONFIG_USB_GADGET_DUALSPEED is not set | 1275 | CONFIG_USB_GADGET_DUALSPEED=y |
| 1017 | # CONFIG_USB_ZERO is not set | 1276 | # CONFIG_USB_ZERO is not set |
| 1277 | # CONFIG_USB_AUDIO is not set | ||
| 1018 | CONFIG_USB_ETH=y | 1278 | CONFIG_USB_ETH=y |
| 1019 | CONFIG_USB_ETH_RNDIS=y | 1279 | CONFIG_USB_ETH_RNDIS=y |
| 1280 | # CONFIG_USB_ETH_EEM is not set | ||
| 1020 | # CONFIG_USB_GADGETFS is not set | 1281 | # CONFIG_USB_GADGETFS is not set |
| 1021 | # CONFIG_USB_FILE_STORAGE is not set | 1282 | # CONFIG_USB_FILE_STORAGE is not set |
| 1283 | # CONFIG_USB_MASS_STORAGE is not set | ||
| 1022 | # CONFIG_USB_G_SERIAL is not set | 1284 | # CONFIG_USB_G_SERIAL is not set |
| 1023 | # CONFIG_USB_MIDI_GADGET is not set | 1285 | # CONFIG_USB_MIDI_GADGET is not set |
| 1024 | # CONFIG_USB_G_PRINTER is not set | 1286 | # CONFIG_USB_G_PRINTER is not set |
| 1025 | # CONFIG_USB_CDC_COMPOSITE is not set | 1287 | # CONFIG_USB_CDC_COMPOSITE is not set |
| 1288 | # CONFIG_USB_G_NOKIA is not set | ||
| 1289 | # CONFIG_USB_G_MULTI is not set | ||
| 1290 | |||
| 1291 | # | ||
| 1292 | # OTG and related infrastructure | ||
| 1293 | # | ||
| 1294 | CONFIG_USB_OTG_UTILS=y | ||
| 1295 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1296 | # CONFIG_ISP1301_OMAP is not set | ||
| 1297 | # CONFIG_USB_ULPI is not set | ||
| 1298 | CONFIG_TWL4030_USB=y | ||
| 1299 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1026 | CONFIG_MMC=y | 1300 | CONFIG_MMC=y |
| 1027 | # CONFIG_MMC_DEBUG is not set | 1301 | # CONFIG_MMC_DEBUG is not set |
| 1028 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1302 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| @@ -1040,16 +1314,41 @@ CONFIG_MMC_BLOCK_BOUNCE=y | |||
| 1040 | # | 1314 | # |
| 1041 | # CONFIG_MMC_SDHCI is not set | 1315 | # CONFIG_MMC_SDHCI is not set |
| 1042 | # CONFIG_MMC_OMAP is not set | 1316 | # CONFIG_MMC_OMAP is not set |
| 1317 | CONFIG_MMC_OMAP_HS=y | ||
| 1318 | # CONFIG_MMC_AT91 is not set | ||
| 1319 | # CONFIG_MMC_ATMELMCI is not set | ||
| 1043 | # CONFIG_MMC_SPI is not set | 1320 | # CONFIG_MMC_SPI is not set |
| 1044 | # CONFIG_MEMSTICK is not set | 1321 | # CONFIG_MEMSTICK is not set |
| 1045 | # CONFIG_ACCESSIBILITY is not set | ||
| 1046 | CONFIG_NEW_LEDS=y | 1322 | CONFIG_NEW_LEDS=y |
| 1047 | CONFIG_LEDS_CLASS=y | 1323 | CONFIG_LEDS_CLASS=y |
| 1324 | |||
| 1325 | # | ||
| 1326 | # LED drivers | ||
| 1327 | # | ||
| 1328 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1048 | CONFIG_LEDS_GPIO=y | 1329 | CONFIG_LEDS_GPIO=y |
| 1049 | CONFIG_LEDS_GPIO_PLATFORM=y | 1330 | CONFIG_LEDS_GPIO_PLATFORM=y |
| 1331 | # CONFIG_LEDS_LP3944 is not set | ||
| 1332 | # CONFIG_LEDS_PCA955X is not set | ||
| 1333 | # CONFIG_LEDS_DAC124S085 is not set | ||
| 1334 | # CONFIG_LEDS_REGULATOR is not set | ||
| 1335 | # CONFIG_LEDS_BD2802 is not set | ||
| 1336 | # CONFIG_LEDS_LT3593 is not set | ||
| 1337 | |||
| 1338 | # | ||
| 1339 | # LED Triggers | ||
| 1340 | # | ||
| 1050 | CONFIG_LEDS_TRIGGERS=y | 1341 | CONFIG_LEDS_TRIGGERS=y |
| 1342 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1343 | # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | ||
| 1344 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1345 | # CONFIG_LEDS_TRIGGER_GPIO is not set | ||
| 1051 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 1346 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 1052 | 1347 | ||
| 1348 | # | ||
| 1349 | # iptables trigger is under Netfilter config (LED target) | ||
| 1350 | # | ||
| 1351 | # CONFIG_ACCESSIBILITY is not set | ||
| 1053 | CONFIG_RTC_LIB=y | 1352 | CONFIG_RTC_LIB=y |
| 1054 | CONFIG_RTC_CLASS=y | 1353 | CONFIG_RTC_CLASS=y |
| 1055 | CONFIG_RTC_HCTOSYS=y | 1354 | CONFIG_RTC_HCTOSYS=y |
| @@ -1078,10 +1377,12 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1078 | # CONFIG_RTC_DRV_PCF8563 is not set | 1377 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1079 | # CONFIG_RTC_DRV_PCF8583 is not set | 1378 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1080 | # CONFIG_RTC_DRV_M41T80 is not set | 1379 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1380 | # CONFIG_RTC_DRV_BQ32K is not set | ||
| 1081 | CONFIG_RTC_DRV_TWL4030=y | 1381 | CONFIG_RTC_DRV_TWL4030=y |
| 1082 | # CONFIG_RTC_DRV_S35390A is not set | 1382 | # CONFIG_RTC_DRV_S35390A is not set |
| 1083 | # CONFIG_RTC_DRV_FM3130 is not set | 1383 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1084 | # CONFIG_RTC_DRV_RX8581 is not set | 1384 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1385 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1085 | 1386 | ||
| 1086 | # | 1387 | # |
| 1087 | # SPI RTC drivers | 1388 | # SPI RTC drivers |
| @@ -1093,6 +1394,7 @@ CONFIG_RTC_DRV_TWL4030=y | |||
| 1093 | # CONFIG_RTC_DRV_R9701 is not set | 1394 | # CONFIG_RTC_DRV_R9701 is not set |
| 1094 | # CONFIG_RTC_DRV_RS5C348 is not set | 1395 | # CONFIG_RTC_DRV_RS5C348 is not set |
| 1095 | # CONFIG_RTC_DRV_DS3234 is not set | 1396 | # CONFIG_RTC_DRV_DS3234 is not set |
| 1397 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1096 | 1398 | ||
| 1097 | # | 1399 | # |
| 1098 | # Platform RTC drivers | 1400 | # Platform RTC drivers |
| @@ -1106,18 +1408,22 @@ CONFIG_RTC_DRV_TWL4030=y | |||
| 1106 | # CONFIG_RTC_DRV_M48T86 is not set | 1408 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1107 | # CONFIG_RTC_DRV_M48T35 is not set | 1409 | # CONFIG_RTC_DRV_M48T35 is not set |
| 1108 | # CONFIG_RTC_DRV_M48T59 is not set | 1410 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1411 | # CONFIG_RTC_DRV_MSM6242 is not set | ||
| 1109 | # CONFIG_RTC_DRV_BQ4802 is not set | 1412 | # CONFIG_RTC_DRV_BQ4802 is not set |
| 1413 | # CONFIG_RTC_DRV_RP5C01 is not set | ||
| 1110 | # CONFIG_RTC_DRV_V3020 is not set | 1414 | # CONFIG_RTC_DRV_V3020 is not set |
| 1111 | 1415 | ||
| 1112 | # | 1416 | # |
| 1113 | # on-CPU RTC drivers | 1417 | # on-CPU RTC drivers |
| 1114 | # | 1418 | # |
| 1115 | # CONFIG_DMADEVICES is not set | 1419 | # CONFIG_DMADEVICES is not set |
| 1420 | # CONFIG_AUXDISPLAY is not set | ||
| 1116 | # CONFIG_UIO is not set | 1421 | # CONFIG_UIO is not set |
| 1117 | 1422 | ||
| 1118 | CONFIG_REGULATOR=y | 1423 | # |
| 1119 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 1424 | # TI VLYNQ |
| 1120 | CONFIG_REGULATOR_TWL4030=y | 1425 | # |
| 1426 | # CONFIG_STAGING is not set | ||
| 1121 | 1427 | ||
| 1122 | # | 1428 | # |
| 1123 | # File systems | 1429 | # File systems |
| @@ -1126,21 +1432,27 @@ CONFIG_EXT2_FS=y | |||
| 1126 | # CONFIG_EXT2_FS_XATTR is not set | 1432 | # CONFIG_EXT2_FS_XATTR is not set |
| 1127 | # CONFIG_EXT2_FS_XIP is not set | 1433 | # CONFIG_EXT2_FS_XIP is not set |
| 1128 | CONFIG_EXT3_FS=y | 1434 | CONFIG_EXT3_FS=y |
| 1435 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1129 | # CONFIG_EXT3_FS_XATTR is not set | 1436 | # CONFIG_EXT3_FS_XATTR is not set |
| 1130 | # CONFIG_EXT4_FS is not set | 1437 | # CONFIG_EXT4_FS is not set |
| 1131 | CONFIG_JBD=y | 1438 | CONFIG_JBD=y |
| 1132 | # CONFIG_REISERFS_FS is not set | 1439 | # CONFIG_REISERFS_FS is not set |
| 1133 | # CONFIG_JFS_FS is not set | 1440 | # CONFIG_JFS_FS is not set |
| 1134 | # CONFIG_FS_POSIX_ACL is not set | 1441 | # CONFIG_FS_POSIX_ACL is not set |
| 1135 | CONFIG_FILE_LOCKING=y | ||
| 1136 | # CONFIG_XFS_FS is not set | 1442 | # CONFIG_XFS_FS is not set |
| 1443 | # CONFIG_GFS2_FS is not set | ||
| 1137 | # CONFIG_OCFS2_FS is not set | 1444 | # CONFIG_OCFS2_FS is not set |
| 1445 | # CONFIG_BTRFS_FS is not set | ||
| 1446 | # CONFIG_NILFS2_FS is not set | ||
| 1447 | CONFIG_FILE_LOCKING=y | ||
| 1448 | CONFIG_FSNOTIFY=y | ||
| 1138 | CONFIG_DNOTIFY=y | 1449 | CONFIG_DNOTIFY=y |
| 1139 | CONFIG_INOTIFY=y | ||
| 1140 | CONFIG_INOTIFY_USER=y | 1450 | CONFIG_INOTIFY_USER=y |
| 1451 | CONFIG_FANOTIFY=y | ||
| 1141 | CONFIG_QUOTA=y | 1452 | CONFIG_QUOTA=y |
| 1142 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | 1453 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set |
| 1143 | CONFIG_PRINT_QUOTA_WARNING=y | 1454 | CONFIG_PRINT_QUOTA_WARNING=y |
| 1455 | CONFIG_QUOTA_TREE=y | ||
| 1144 | # CONFIG_QFMT_V1 is not set | 1456 | # CONFIG_QFMT_V1 is not set |
| 1145 | CONFIG_QFMT_V2=y | 1457 | CONFIG_QFMT_V2=y |
| 1146 | CONFIG_QUOTACTL=y | 1458 | CONFIG_QUOTACTL=y |
| @@ -1149,6 +1461,11 @@ CONFIG_QUOTACTL=y | |||
| 1149 | # CONFIG_FUSE_FS is not set | 1461 | # CONFIG_FUSE_FS is not set |
| 1150 | 1462 | ||
| 1151 | # | 1463 | # |
| 1464 | # Caches | ||
| 1465 | # | ||
| 1466 | # CONFIG_FSCACHE is not set | ||
| 1467 | |||
| 1468 | # | ||
| 1152 | # CD-ROM/DVD Filesystems | 1469 | # CD-ROM/DVD Filesystems |
| 1153 | # | 1470 | # |
| 1154 | # CONFIG_ISO9660_FS is not set | 1471 | # CONFIG_ISO9660_FS is not set |
| @@ -1175,10 +1492,7 @@ CONFIG_TMPFS=y | |||
| 1175 | # CONFIG_TMPFS_POSIX_ACL is not set | 1492 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1176 | # CONFIG_HUGETLB_PAGE is not set | 1493 | # CONFIG_HUGETLB_PAGE is not set |
| 1177 | # CONFIG_CONFIGFS_FS is not set | 1494 | # CONFIG_CONFIGFS_FS is not set |
| 1178 | 1495 | CONFIG_MISC_FILESYSTEMS=y | |
| 1179 | # | ||
| 1180 | # Miscellaneous filesystems | ||
| 1181 | # | ||
| 1182 | # CONFIG_ADFS_FS is not set | 1496 | # CONFIG_ADFS_FS is not set |
| 1183 | # CONFIG_AFFS_FS is not set | 1497 | # CONFIG_AFFS_FS is not set |
| 1184 | # CONFIG_HFS_FS is not set | 1498 | # CONFIG_HFS_FS is not set |
| @@ -1187,7 +1501,9 @@ CONFIG_TMPFS=y | |||
| 1187 | # CONFIG_BFS_FS is not set | 1501 | # CONFIG_BFS_FS is not set |
| 1188 | # CONFIG_EFS_FS is not set | 1502 | # CONFIG_EFS_FS is not set |
| 1189 | # CONFIG_JFFS2_FS is not set | 1503 | # CONFIG_JFFS2_FS is not set |
| 1504 | # CONFIG_LOGFS is not set | ||
| 1190 | # CONFIG_CRAMFS is not set | 1505 | # CONFIG_CRAMFS is not set |
| 1506 | # CONFIG_SQUASHFS is not set | ||
| 1191 | # CONFIG_VXFS_FS is not set | 1507 | # CONFIG_VXFS_FS is not set |
| 1192 | # CONFIG_MINIX_FS is not set | 1508 | # CONFIG_MINIX_FS is not set |
| 1193 | # CONFIG_OMFS_FS is not set | 1509 | # CONFIG_OMFS_FS is not set |
| @@ -1196,7 +1512,20 @@ CONFIG_TMPFS=y | |||
| 1196 | # CONFIG_ROMFS_FS is not set | 1512 | # CONFIG_ROMFS_FS is not set |
| 1197 | # CONFIG_SYSV_FS is not set | 1513 | # CONFIG_SYSV_FS is not set |
| 1198 | # CONFIG_UFS_FS is not set | 1514 | # CONFIG_UFS_FS is not set |
| 1199 | # CONFIG_NETWORK_FILESYSTEMS is not set | 1515 | CONFIG_NETWORK_FILESYSTEMS=y |
| 1516 | # CONFIG_NFS_FS is not set | ||
| 1517 | # CONFIG_NFSD is not set | ||
| 1518 | # CONFIG_SMB_FS is not set | ||
| 1519 | # CONFIG_CEPH_FS is not set | ||
| 1520 | CONFIG_CIFS=y | ||
| 1521 | # CONFIG_CIFS_STATS is not set | ||
| 1522 | # CONFIG_CIFS_WEAK_PW_HASH is not set | ||
| 1523 | # CONFIG_CIFS_XATTR is not set | ||
| 1524 | # CONFIG_CIFS_DEBUG2 is not set | ||
| 1525 | # CONFIG_CIFS_EXPERIMENTAL is not set | ||
| 1526 | # CONFIG_NCP_FS is not set | ||
| 1527 | # CONFIG_CODA_FS is not set | ||
| 1528 | # CONFIG_AFS_FS is not set | ||
| 1200 | 1529 | ||
| 1201 | # | 1530 | # |
| 1202 | # Partition Types | 1531 | # Partition Types |
| @@ -1269,6 +1598,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y | |||
| 1269 | CONFIG_ENABLE_MUST_CHECK=y | 1598 | CONFIG_ENABLE_MUST_CHECK=y |
| 1270 | CONFIG_FRAME_WARN=1024 | 1599 | CONFIG_FRAME_WARN=1024 |
| 1271 | CONFIG_MAGIC_SYSRQ=y | 1600 | CONFIG_MAGIC_SYSRQ=y |
| 1601 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1272 | # CONFIG_UNUSED_SYMBOLS is not set | 1602 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1273 | # CONFIG_DEBUG_FS is not set | 1603 | # CONFIG_DEBUG_FS is not set |
| 1274 | # CONFIG_HEADERS_CHECK is not set | 1604 | # CONFIG_HEADERS_CHECK is not set |
| @@ -1277,11 +1607,15 @@ CONFIG_DEBUG_KERNEL=y | |||
| 1277 | CONFIG_DETECT_SOFTLOCKUP=y | 1607 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1278 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1608 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1279 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1609 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| 1610 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1611 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1612 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1280 | CONFIG_SCHED_DEBUG=y | 1613 | CONFIG_SCHED_DEBUG=y |
| 1281 | # CONFIG_SCHEDSTATS is not set | 1614 | # CONFIG_SCHEDSTATS is not set |
| 1282 | # CONFIG_TIMER_STATS is not set | 1615 | # CONFIG_TIMER_STATS is not set |
| 1283 | # CONFIG_DEBUG_OBJECTS is not set | 1616 | # CONFIG_DEBUG_OBJECTS is not set |
| 1284 | # CONFIG_DEBUG_SLAB is not set | 1617 | # CONFIG_DEBUG_SLAB is not set |
| 1618 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1285 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1619 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1286 | # CONFIG_RT_MUTEX_TESTER is not set | 1620 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1287 | # CONFIG_DEBUG_SPINLOCK is not set | 1621 | # CONFIG_DEBUG_SPINLOCK is not set |
| @@ -1299,33 +1633,42 @@ CONFIG_DEBUG_INFO=y | |||
| 1299 | # CONFIG_DEBUG_MEMORY_INIT is not set | 1633 | # CONFIG_DEBUG_MEMORY_INIT is not set |
| 1300 | # CONFIG_DEBUG_LIST is not set | 1634 | # CONFIG_DEBUG_LIST is not set |
| 1301 | # CONFIG_DEBUG_SG is not set | 1635 | # CONFIG_DEBUG_SG is not set |
| 1302 | CONFIG_FRAME_POINTER=y | 1636 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 1637 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 1303 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1638 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1304 | # CONFIG_RCU_TORTURE_TEST is not set | 1639 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1305 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 1640 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 1306 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1641 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1307 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1642 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1643 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 1308 | # CONFIG_FAULT_INJECTION is not set | 1644 | # CONFIG_FAULT_INJECTION is not set |
| 1309 | # CONFIG_LATENCYTOP is not set | 1645 | # CONFIG_LATENCYTOP is not set |
| 1646 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1647 | # CONFIG_PAGE_POISONING is not set | ||
| 1310 | CONFIG_HAVE_FUNCTION_TRACER=y | 1648 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1311 | 1649 | CONFIG_TRACING_SUPPORT=y | |
| 1312 | # | 1650 | CONFIG_FTRACE=y |
| 1313 | # Tracers | ||
| 1314 | # | ||
| 1315 | # CONFIG_FUNCTION_TRACER is not set | 1651 | # CONFIG_FUNCTION_TRACER is not set |
| 1316 | # CONFIG_IRQSOFF_TRACER is not set | 1652 | # CONFIG_IRQSOFF_TRACER is not set |
| 1317 | # CONFIG_SCHED_TRACER is not set | 1653 | # CONFIG_SCHED_TRACER is not set |
| 1318 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1654 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set |
| 1319 | # CONFIG_BOOT_TRACER is not set | 1655 | # CONFIG_BOOT_TRACER is not set |
| 1656 | CONFIG_BRANCH_PROFILE_NONE=y | ||
| 1657 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 1658 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 1320 | # CONFIG_STACK_TRACER is not set | 1659 | # CONFIG_STACK_TRACER is not set |
| 1321 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 1660 | # CONFIG_KMEMTRACE is not set |
| 1661 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1662 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1322 | # CONFIG_SAMPLES is not set | 1663 | # CONFIG_SAMPLES is not set |
| 1323 | CONFIG_HAVE_ARCH_KGDB=y | 1664 | CONFIG_HAVE_ARCH_KGDB=y |
| 1324 | # CONFIG_KGDB is not set | 1665 | # CONFIG_KGDB is not set |
| 1666 | CONFIG_ARM_UNWIND=y | ||
| 1325 | # CONFIG_DEBUG_USER is not set | 1667 | # CONFIG_DEBUG_USER is not set |
| 1326 | # CONFIG_DEBUG_ERRORS is not set | 1668 | # CONFIG_DEBUG_ERRORS is not set |
| 1327 | # CONFIG_DEBUG_STACK_USAGE is not set | 1669 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1328 | # CONFIG_DEBUG_LL is not set | 1670 | # CONFIG_DEBUG_LL is not set |
| 1671 | # CONFIG_OC_ETM is not set | ||
| 1329 | 1672 | ||
| 1330 | # | 1673 | # |
| 1331 | # Security options | 1674 | # Security options |
| @@ -1333,19 +1676,22 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1333 | # CONFIG_KEYS is not set | 1676 | # CONFIG_KEYS is not set |
| 1334 | # CONFIG_SECURITY is not set | 1677 | # CONFIG_SECURITY is not set |
| 1335 | # CONFIG_SECURITYFS is not set | 1678 | # CONFIG_SECURITYFS is not set |
| 1336 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1679 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set |
| 1680 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
| 1681 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
| 1682 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
| 1683 | CONFIG_DEFAULT_SECURITY="" | ||
| 1337 | CONFIG_CRYPTO=y | 1684 | CONFIG_CRYPTO=y |
| 1338 | 1685 | ||
| 1339 | # | 1686 | # |
| 1340 | # Crypto core or helper | 1687 | # Crypto core or helper |
| 1341 | # | 1688 | # |
| 1342 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1343 | CONFIG_CRYPTO_ALGAPI=y | 1689 | CONFIG_CRYPTO_ALGAPI=y |
| 1344 | CONFIG_CRYPTO_AEAD=y | 1690 | CONFIG_CRYPTO_ALGAPI2=y |
| 1345 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1346 | CONFIG_CRYPTO_HASH=y | 1691 | CONFIG_CRYPTO_HASH=y |
| 1347 | CONFIG_CRYPTO_RNG=y | 1692 | CONFIG_CRYPTO_HASH2=y |
| 1348 | CONFIG_CRYPTO_MANAGER=y | 1693 | # CONFIG_CRYPTO_MANAGER is not set |
| 1694 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 1349 | # CONFIG_CRYPTO_GF128MUL is not set | 1695 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1350 | # CONFIG_CRYPTO_NULL is not set | 1696 | # CONFIG_CRYPTO_NULL is not set |
| 1351 | # CONFIG_CRYPTO_CRYPTD is not set | 1697 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -1362,12 +1708,12 @@ CONFIG_CRYPTO_MANAGER=y | |||
| 1362 | # | 1708 | # |
| 1363 | # Block modes | 1709 | # Block modes |
| 1364 | # | 1710 | # |
| 1365 | CONFIG_CRYPTO_CBC=y | 1711 | # CONFIG_CRYPTO_CBC is not set |
| 1366 | # CONFIG_CRYPTO_CTR is not set | 1712 | # CONFIG_CRYPTO_CTR is not set |
| 1367 | # CONFIG_CRYPTO_CTS is not set | 1713 | # CONFIG_CRYPTO_CTS is not set |
| 1368 | CONFIG_CRYPTO_ECB=m | 1714 | # CONFIG_CRYPTO_ECB is not set |
| 1369 | # CONFIG_CRYPTO_LRW is not set | 1715 | # CONFIG_CRYPTO_LRW is not set |
| 1370 | CONFIG_CRYPTO_PCBC=m | 1716 | # CONFIG_CRYPTO_PCBC is not set |
| 1371 | # CONFIG_CRYPTO_XTS is not set | 1717 | # CONFIG_CRYPTO_XTS is not set |
| 1372 | 1718 | ||
| 1373 | # | 1719 | # |
| @@ -1375,13 +1721,15 @@ CONFIG_CRYPTO_PCBC=m | |||
| 1375 | # | 1721 | # |
| 1376 | # CONFIG_CRYPTO_HMAC is not set | 1722 | # CONFIG_CRYPTO_HMAC is not set |
| 1377 | # CONFIG_CRYPTO_XCBC is not set | 1723 | # CONFIG_CRYPTO_XCBC is not set |
| 1724 | # CONFIG_CRYPTO_VMAC is not set | ||
| 1378 | 1725 | ||
| 1379 | # | 1726 | # |
| 1380 | # Digest | 1727 | # Digest |
| 1381 | # | 1728 | # |
| 1382 | # CONFIG_CRYPTO_CRC32C is not set | 1729 | CONFIG_CRYPTO_CRC32C=y |
| 1730 | # CONFIG_CRYPTO_GHASH is not set | ||
| 1383 | # CONFIG_CRYPTO_MD4 is not set | 1731 | # CONFIG_CRYPTO_MD4 is not set |
| 1384 | CONFIG_CRYPTO_MD5=y | 1732 | # CONFIG_CRYPTO_MD5 is not set |
| 1385 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1733 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| 1386 | # CONFIG_CRYPTO_RMD128 is not set | 1734 | # CONFIG_CRYPTO_RMD128 is not set |
| 1387 | # CONFIG_CRYPTO_RMD160 is not set | 1735 | # CONFIG_CRYPTO_RMD160 is not set |
| @@ -1403,7 +1751,7 @@ CONFIG_CRYPTO_MD5=y | |||
| 1403 | # CONFIG_CRYPTO_CAMELLIA is not set | 1751 | # CONFIG_CRYPTO_CAMELLIA is not set |
| 1404 | # CONFIG_CRYPTO_CAST5 is not set | 1752 | # CONFIG_CRYPTO_CAST5 is not set |
| 1405 | # CONFIG_CRYPTO_CAST6 is not set | 1753 | # CONFIG_CRYPTO_CAST6 is not set |
| 1406 | CONFIG_CRYPTO_DES=y | 1754 | # CONFIG_CRYPTO_DES is not set |
| 1407 | # CONFIG_CRYPTO_FCRYPT is not set | 1755 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1408 | # CONFIG_CRYPTO_KHAZAD is not set | 1756 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1409 | # CONFIG_CRYPTO_SALSA20 is not set | 1757 | # CONFIG_CRYPTO_SALSA20 is not set |
| @@ -1416,33 +1764,33 @@ CONFIG_CRYPTO_DES=y | |||
| 1416 | # Compression | 1764 | # Compression |
| 1417 | # | 1765 | # |
| 1418 | # CONFIG_CRYPTO_DEFLATE is not set | 1766 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1767 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1419 | # CONFIG_CRYPTO_LZO is not set | 1768 | # CONFIG_CRYPTO_LZO is not set |
| 1420 | 1769 | ||
| 1421 | # | 1770 | # |
| 1422 | # Random Number Generation | 1771 | # Random Number Generation |
| 1423 | # | 1772 | # |
| 1424 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 1773 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 1425 | CONFIG_CRYPTO_HW=y | 1774 | # CONFIG_CRYPTO_HW is not set |
| 1775 | # CONFIG_BINARY_PRINTF is not set | ||
| 1426 | 1776 | ||
| 1427 | # | 1777 | # |
| 1428 | # Library routines | 1778 | # Library routines |
| 1429 | # | 1779 | # |
| 1430 | CONFIG_BITREVERSE=y | 1780 | CONFIG_BITREVERSE=y |
| 1781 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1431 | CONFIG_CRC_CCITT=y | 1782 | CONFIG_CRC_CCITT=y |
| 1432 | # CONFIG_CRC16 is not set | 1783 | # CONFIG_CRC16 is not set |
| 1433 | # CONFIG_CRC_T10DIF is not set | 1784 | # CONFIG_CRC_T10DIF is not set |
| 1434 | # CONFIG_CRC_ITU_T is not set | 1785 | # CONFIG_CRC_ITU_T is not set |
| 1435 | CONFIG_CRC32=y | 1786 | CONFIG_CRC32=y |
| 1436 | # CONFIG_CRC7 is not set | 1787 | # CONFIG_CRC7 is not set |
| 1437 | CONFIG_LIBCRC32C=y | 1788 | # CONFIG_LIBCRC32C is not set |
| 1438 | CONFIG_PLIST=y | 1789 | CONFIG_ZLIB_INFLATE=y |
| 1790 | CONFIG_DECOMPRESS_GZIP=y | ||
| 1439 | CONFIG_HAS_IOMEM=y | 1791 | CONFIG_HAS_IOMEM=y |
| 1440 | CONFIG_HAS_IOPORT=y | 1792 | CONFIG_HAS_IOPORT=y |
| 1441 | CONFIG_HAS_DMA=y | 1793 | CONFIG_HAS_DMA=y |
| 1442 | 1794 | CONFIG_NLATTR=y | |
| 1443 | # added by hand for now | 1795 | # CONFIG_SHM_SIGNAL is not set |
| 1444 | CONFIG_KEYBOARD_TWL4030=y | 1796 | # CONFIG_IOQ is not set |
| 1445 | CONFIG_USB_OTG_UTILS=y | ||
| 1446 | CONFIG_TWL4030_USB=y | ||
| 1447 | CONFIG_MMC_OMAP_HS=y | ||
| 1448 | |||
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index c48d7b893869..a96bca290cd1 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig | |||
| @@ -199,7 +199,7 @@ CONFIG_ARCH_OMAP4=y | |||
| 199 | # | 199 | # |
| 200 | # CONFIG_OMAP_RESET_CLOCKS is not set | 200 | # CONFIG_OMAP_RESET_CLOCKS is not set |
| 201 | # CONFIG_OMAP_MUX is not set | 201 | # CONFIG_OMAP_MUX is not set |
| 202 | # CONFIG_OMAP_MCBSP is not set | 202 | CONFIG_OMAP_MCBSP=y |
| 203 | # CONFIG_OMAP_MBOX_FWK is not set | 203 | # CONFIG_OMAP_MBOX_FWK is not set |
| 204 | # CONFIG_OMAP_MPU_TIMER is not set | 204 | # CONFIG_OMAP_MPU_TIMER is not set |
| 205 | CONFIG_OMAP_32K_TIMER=y | 205 | CONFIG_OMAP_32K_TIMER=y |
| @@ -307,7 +307,7 @@ CONFIG_ALIGNMENT_TRAP=y | |||
| 307 | # | 307 | # |
| 308 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 308 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 309 | CONFIG_ZBOOT_ROM_BSS=0x0 | 309 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 310 | CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480" | 310 | CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" |
| 311 | # CONFIG_XIP_KERNEL is not set | 311 | # CONFIG_XIP_KERNEL is not set |
| 312 | # CONFIG_KEXEC is not set | 312 | # CONFIG_KEXEC is not set |
| 313 | 313 | ||
| @@ -491,7 +491,8 @@ CONFIG_GPIOLIB=y | |||
| 491 | # CONFIG_POWER_SUPPLY is not set | 491 | # CONFIG_POWER_SUPPLY is not set |
| 492 | # CONFIG_HWMON is not set | 492 | # CONFIG_HWMON is not set |
| 493 | # CONFIG_THERMAL is not set | 493 | # CONFIG_THERMAL is not set |
| 494 | # CONFIG_WATCHDOG is not set | 494 | CONFIG_WATCHDOG=y |
| 495 | CONFIG_OMAP_WATCHDOG=y | ||
| 495 | CONFIG_SSB_POSSIBLE=y | 496 | CONFIG_SSB_POSSIBLE=y |
| 496 | 497 | ||
| 497 | # | 498 | # |
diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig index a3e3c8274c9b..ff8ac3dcc31d 100644 --- a/arch/arm/configs/omap_zoom3_defconfig +++ b/arch/arm/configs/omap_zoom3_defconfig | |||
| @@ -1136,7 +1136,7 @@ CONFIG_TWL4030_USB=y | |||
| 1136 | # CONFIG_NOP_USB_XCEIV is not set | 1136 | # CONFIG_NOP_USB_XCEIV is not set |
| 1137 | CONFIG_MMC=y | 1137 | CONFIG_MMC=y |
| 1138 | # CONFIG_MMC_DEBUG is not set | 1138 | # CONFIG_MMC_DEBUG is not set |
| 1139 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1139 | CONFIG_MMC_UNSAFE_RESUME=y |
| 1140 | 1140 | ||
| 1141 | # | 1141 | # |
| 1142 | # MMC/SD/SDIO Card Drivers | 1142 | # MMC/SD/SDIO Card Drivers |
| @@ -1186,7 +1186,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1186 | # CONFIG_RTC_DRV_PCF8563 is not set | 1186 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1187 | # CONFIG_RTC_DRV_PCF8583 is not set | 1187 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1188 | # CONFIG_RTC_DRV_M41T80 is not set | 1188 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1189 | # CONFIG_RTC_DRV_TWL4030 is not set | 1189 | CONFIG_RTC_DRV_TWL4030=y |
| 1190 | # CONFIG_RTC_DRV_S35390A is not set | 1190 | # CONFIG_RTC_DRV_S35390A is not set |
| 1191 | # CONFIG_RTC_DRV_FM3130 is not set | 1191 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1192 | # CONFIG_RTC_DRV_RX8581 is not set | 1192 | # CONFIG_RTC_DRV_RX8581 is not set |
| @@ -1416,7 +1416,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1416 | CONFIG_MAGIC_SYSRQ=y | 1416 | CONFIG_MAGIC_SYSRQ=y |
| 1417 | # CONFIG_STRIP_ASM_SYMS is not set | 1417 | # CONFIG_STRIP_ASM_SYMS is not set |
| 1418 | # CONFIG_UNUSED_SYMBOLS is not set | 1418 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1419 | # CONFIG_DEBUG_FS is not set | 1419 | CONFIG_DEBUG_FS=y |
| 1420 | # CONFIG_HEADERS_CHECK is not set | 1420 | # CONFIG_HEADERS_CHECK is not set |
| 1421 | CONFIG_DEBUG_KERNEL=y | 1421 | CONFIG_DEBUG_KERNEL=y |
| 1422 | # CONFIG_DEBUG_SHIRQ is not set | 1422 | # CONFIG_DEBUG_SHIRQ is not set |
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig index b6eeebb31761..426ae948aefe 100644 --- a/arch/arm/configs/rx51_defconfig +++ b/arch/arm/configs/rx51_defconfig | |||
| @@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y | |||
| 1354 | # CONFIG_USB_GPIO_VBUS is not set | 1354 | # CONFIG_USB_GPIO_VBUS is not set |
| 1355 | # CONFIG_ISP1301_OMAP is not set | 1355 | # CONFIG_ISP1301_OMAP is not set |
| 1356 | CONFIG_TWL4030_USB=y | 1356 | CONFIG_TWL4030_USB=y |
| 1357 | CONFIG_MMC=y | 1357 | CONFIG_MMC=m |
| 1358 | # CONFIG_MMC_DEBUG is not set | 1358 | # CONFIG_MMC_DEBUG is not set |
| 1359 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1359 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1360 | 1360 | ||
| @@ -1362,7 +1362,7 @@ CONFIG_MMC=y | |||
| 1362 | # MMC/SD/SDIO Card Drivers | 1362 | # MMC/SD/SDIO Card Drivers |
| 1363 | # | 1363 | # |
| 1364 | CONFIG_MMC_BLOCK=m | 1364 | CONFIG_MMC_BLOCK=m |
| 1365 | CONFIG_MMC_BLOCK_BOUNCE=y | 1365 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 1366 | # CONFIG_SDIO_UART is not set | 1366 | # CONFIG_SDIO_UART is not set |
| 1367 | # CONFIG_MMC_TEST is not set | 1367 | # CONFIG_MMC_TEST is not set |
| 1368 | 1368 | ||
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 9ce17f13d3f1..b6a537c875b8 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o | 6 | obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o |
| 7 | obj-y += clock.o clock_data.o opp_data.o | 7 | obj-y += clock.o clock_data.o opp_data.o |
| 8 | 8 | ||
| 9 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 9 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 7e70c3c08da6..096f2ed102cb 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
| @@ -18,18 +18,19 @@ | |||
| 18 | #include <linux/mtd/mtd.h> | 18 | #include <linux/mtd/mtd.h> |
| 19 | #include <linux/mtd/nand.h> | 19 | #include <linux/mtd/nand.h> |
| 20 | #include <linux/mtd/partitions.h> | 20 | #include <linux/mtd/partitions.h> |
| 21 | #include <linux/mtd/physmap.h> | ||
| 21 | #include <linux/input.h> | 22 | #include <linux/input.h> |
| 22 | #include <linux/smc91x.h> | 23 | #include <linux/smc91x.h> |
| 23 | 24 | ||
| 24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 25 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 26 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/flash.h> | ||
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | 29 | ||
| 30 | #include <plat/tc.h> | 30 | #include <plat/tc.h> |
| 31 | #include <mach/gpio.h> | 31 | #include <mach/gpio.h> |
| 32 | #include <plat/mux.h> | 32 | #include <plat/mux.h> |
| 33 | #include <plat/flash.h> | ||
| 33 | #include <plat/fpga.h> | 34 | #include <plat/fpga.h> |
| 34 | #include <plat/keypad.h> | 35 | #include <plat/keypad.h> |
| 35 | #include <plat/common.h> | 36 | #include <plat/common.h> |
| @@ -150,9 +151,9 @@ static struct mtd_partition nor_partitions[] = { | |||
| 150 | }, | 151 | }, |
| 151 | }; | 152 | }; |
| 152 | 153 | ||
| 153 | static struct flash_platform_data nor_data = { | 154 | static struct physmap_flash_data nor_data = { |
| 154 | .map_name = "cfi_probe", | ||
| 155 | .width = 2, | 155 | .width = 2, |
| 156 | .set_vpp = omap1_set_vpp, | ||
| 156 | .parts = nor_partitions, | 157 | .parts = nor_partitions, |
| 157 | .nr_parts = ARRAY_SIZE(nor_partitions), | 158 | .nr_parts = ARRAY_SIZE(nor_partitions), |
| 158 | }; | 159 | }; |
| @@ -164,7 +165,7 @@ static struct resource nor_resource = { | |||
| 164 | }; | 165 | }; |
| 165 | 166 | ||
| 166 | static struct platform_device nor_device = { | 167 | static struct platform_device nor_device = { |
| 167 | .name = "omapflash", | 168 | .name = "physmap-flash", |
| 168 | .id = 0, | 169 | .id = 0, |
| 169 | .dev = { | 170 | .dev = { |
| 170 | .platform_data = &nor_data, | 171 | .platform_data = &nor_data, |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index fa7cecea19f9..d1100e4f65ac 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/mtd/mtd.h> | 26 | #include <linux/mtd/mtd.h> |
| 27 | #include <linux/mtd/nand.h> | 27 | #include <linux/mtd/nand.h> |
| 28 | #include <linux/mtd/partitions.h> | 28 | #include <linux/mtd/partitions.h> |
| 29 | #include <linux/mtd/physmap.h> | ||
| 29 | #include <linux/input.h> | 30 | #include <linux/input.h> |
| 30 | #include <linux/i2c/tps65010.h> | 31 | #include <linux/i2c/tps65010.h> |
| 31 | #include <linux/smc91x.h> | 32 | #include <linux/smc91x.h> |
| @@ -35,7 +36,6 @@ | |||
| 35 | 36 | ||
| 36 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
| 37 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| 38 | #include <asm/mach/flash.h> | ||
| 39 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| 40 | 40 | ||
| 41 | #include <plat/mux.h> | 41 | #include <plat/mux.h> |
| @@ -45,6 +45,7 @@ | |||
| 45 | #include <plat/usb.h> | 45 | #include <plat/usb.h> |
| 46 | #include <plat/keypad.h> | 46 | #include <plat/keypad.h> |
| 47 | #include <plat/common.h> | 47 | #include <plat/common.h> |
| 48 | #include <plat/flash.h> | ||
| 48 | 49 | ||
| 49 | #include "board-h2.h" | 50 | #include "board-h2.h" |
| 50 | 51 | ||
| @@ -121,9 +122,9 @@ static struct mtd_partition h2_nor_partitions[] = { | |||
| 121 | } | 122 | } |
| 122 | }; | 123 | }; |
| 123 | 124 | ||
| 124 | static struct flash_platform_data h2_nor_data = { | 125 | static struct physmap_flash_data h2_nor_data = { |
| 125 | .map_name = "cfi_probe", | ||
| 126 | .width = 2, | 126 | .width = 2, |
| 127 | .set_vpp = omap1_set_vpp, | ||
| 127 | .parts = h2_nor_partitions, | 128 | .parts = h2_nor_partitions, |
| 128 | .nr_parts = ARRAY_SIZE(h2_nor_partitions), | 129 | .nr_parts = ARRAY_SIZE(h2_nor_partitions), |
| 129 | }; | 130 | }; |
| @@ -134,7 +135,7 @@ static struct resource h2_nor_resource = { | |||
| 134 | }; | 135 | }; |
| 135 | 136 | ||
| 136 | static struct platform_device h2_nor_device = { | 137 | static struct platform_device h2_nor_device = { |
| 137 | .name = "omapflash", | 138 | .name = "physmap-flash", |
| 138 | .id = 0, | 139 | .id = 0, |
| 139 | .dev = { | 140 | .dev = { |
| 140 | .platform_data = &h2_nor_data, | 141 | .platform_data = &h2_nor_data, |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 6a7f9c391cf1..a53ab8297d25 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/mtd/mtd.h> | 25 | #include <linux/mtd/mtd.h> |
| 26 | #include <linux/mtd/nand.h> | 26 | #include <linux/mtd/nand.h> |
| 27 | #include <linux/mtd/partitions.h> | 27 | #include <linux/mtd/partitions.h> |
| 28 | #include <linux/mtd/physmap.h> | ||
| 28 | #include <linux/input.h> | 29 | #include <linux/input.h> |
| 29 | #include <linux/spi/spi.h> | 30 | #include <linux/spi/spi.h> |
| 30 | #include <linux/i2c/tps65010.h> | 31 | #include <linux/i2c/tps65010.h> |
| @@ -37,7 +38,6 @@ | |||
| 37 | 38 | ||
| 38 | #include <asm/mach-types.h> | 39 | #include <asm/mach-types.h> |
| 39 | #include <asm/mach/arch.h> | 40 | #include <asm/mach/arch.h> |
| 40 | #include <asm/mach/flash.h> | ||
| 41 | #include <asm/mach/map.h> | 41 | #include <asm/mach/map.h> |
| 42 | 42 | ||
| 43 | #include <mach/irqs.h> | 43 | #include <mach/irqs.h> |
| @@ -47,6 +47,7 @@ | |||
| 47 | #include <plat/keypad.h> | 47 | #include <plat/keypad.h> |
| 48 | #include <plat/dma.h> | 48 | #include <plat/dma.h> |
| 49 | #include <plat/common.h> | 49 | #include <plat/common.h> |
| 50 | #include <plat/flash.h> | ||
| 50 | 51 | ||
| 51 | #include "board-h3.h" | 52 | #include "board-h3.h" |
| 52 | 53 | ||
| @@ -126,9 +127,9 @@ static struct mtd_partition nor_partitions[] = { | |||
| 126 | } | 127 | } |
| 127 | }; | 128 | }; |
| 128 | 129 | ||
| 129 | static struct flash_platform_data nor_data = { | 130 | static struct physmap_flash_data nor_data = { |
| 130 | .map_name = "cfi_probe", | ||
| 131 | .width = 2, | 131 | .width = 2, |
| 132 | .set_vpp = omap1_set_vpp, | ||
| 132 | .parts = nor_partitions, | 133 | .parts = nor_partitions, |
| 133 | .nr_parts = ARRAY_SIZE(nor_partitions), | 134 | .nr_parts = ARRAY_SIZE(nor_partitions), |
| 134 | }; | 135 | }; |
| @@ -139,7 +140,7 @@ static struct resource nor_resource = { | |||
| 139 | }; | 140 | }; |
| 140 | 141 | ||
| 141 | static struct platform_device nor_device = { | 142 | static struct platform_device nor_device = { |
| 142 | .name = "omapflash", | 143 | .name = "physmap-flash", |
| 143 | .id = 0, | 144 | .id = 0, |
| 144 | .dev = { | 145 | .dev = { |
| 145 | .platform_data = &nor_data, | 146 | .platform_data = &nor_data, |
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 2133b006f6a3..5d12fd35681b 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
| @@ -22,16 +22,17 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/mtd/mtd.h> | 23 | #include <linux/mtd/mtd.h> |
| 24 | #include <linux/mtd/partitions.h> | 24 | #include <linux/mtd/partitions.h> |
| 25 | #include <linux/mtd/physmap.h> | ||
| 25 | #include <linux/input.h> | 26 | #include <linux/input.h> |
| 26 | #include <linux/smc91x.h> | 27 | #include <linux/smc91x.h> |
| 27 | 28 | ||
| 28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 29 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/flash.h> | ||
| 32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
| 33 | 33 | ||
| 34 | #include <plat/mux.h> | 34 | #include <plat/mux.h> |
| 35 | #include <plat/flash.h> | ||
| 35 | #include <plat/fpga.h> | 36 | #include <plat/fpga.h> |
| 36 | #include <mach/gpio.h> | 37 | #include <mach/gpio.h> |
| 37 | #include <plat/tc.h> | 38 | #include <plat/tc.h> |
| @@ -94,9 +95,9 @@ static struct mtd_partition innovator_partitions[] = { | |||
| 94 | } | 95 | } |
| 95 | }; | 96 | }; |
| 96 | 97 | ||
| 97 | static struct flash_platform_data innovator_flash_data = { | 98 | static struct physmap_flash_data innovator_flash_data = { |
| 98 | .map_name = "cfi_probe", | ||
| 99 | .width = 2, | 99 | .width = 2, |
| 100 | .set_vpp = omap1_set_vpp, | ||
| 100 | .parts = innovator_partitions, | 101 | .parts = innovator_partitions, |
| 101 | .nr_parts = ARRAY_SIZE(innovator_partitions), | 102 | .nr_parts = ARRAY_SIZE(innovator_partitions), |
| 102 | }; | 103 | }; |
| @@ -108,7 +109,7 @@ static struct resource innovator_flash_resource = { | |||
| 108 | }; | 109 | }; |
| 109 | 110 | ||
| 110 | static struct platform_device innovator_flash_device = { | 111 | static struct platform_device innovator_flash_device = { |
| 111 | .name = "omapflash", | 112 | .name = "physmap-flash", |
| 112 | .id = 0, | 113 | .id = 0, |
| 113 | .dev = { | 114 | .dev = { |
| 114 | .platform_data = &innovator_flash_data, | 115 | .platform_data = &innovator_flash_data, |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index ccea4f448e9a..80d862001def 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | 37 | ||
| 38 | #include <linux/mtd/mtd.h> | 38 | #include <linux/mtd/mtd.h> |
| 39 | #include <linux/mtd/partitions.h> | 39 | #include <linux/mtd/partitions.h> |
| 40 | #include <linux/mtd/physmap.h> | ||
| 40 | 41 | ||
| 41 | #include <linux/i2c/tps65010.h> | 42 | #include <linux/i2c/tps65010.h> |
| 42 | 43 | ||
| @@ -46,8 +47,8 @@ | |||
| 46 | #include <asm/mach-types.h> | 47 | #include <asm/mach-types.h> |
| 47 | #include <asm/mach/arch.h> | 48 | #include <asm/mach/arch.h> |
| 48 | #include <asm/mach/map.h> | 49 | #include <asm/mach/map.h> |
| 49 | #include <asm/mach/flash.h> | ||
| 50 | 50 | ||
| 51 | #include <plat/flash.h> | ||
| 51 | #include <plat/usb.h> | 52 | #include <plat/usb.h> |
| 52 | #include <plat/mux.h> | 53 | #include <plat/mux.h> |
| 53 | #include <plat/tc.h> | 54 | #include <plat/tc.h> |
| @@ -94,9 +95,9 @@ static struct mtd_partition osk_partitions[] = { | |||
| 94 | } | 95 | } |
| 95 | }; | 96 | }; |
| 96 | 97 | ||
| 97 | static struct flash_platform_data osk_flash_data = { | 98 | static struct physmap_flash_data osk_flash_data = { |
| 98 | .map_name = "cfi_probe", | ||
| 99 | .width = 2, | 99 | .width = 2, |
| 100 | .set_vpp = omap1_set_vpp, | ||
| 100 | .parts = osk_partitions, | 101 | .parts = osk_partitions, |
| 101 | .nr_parts = ARRAY_SIZE(osk_partitions), | 102 | .nr_parts = ARRAY_SIZE(osk_partitions), |
| 102 | }; | 103 | }; |
| @@ -107,7 +108,7 @@ static struct resource osk_flash_resource = { | |||
| 107 | }; | 108 | }; |
| 108 | 109 | ||
| 109 | static struct platform_device osk5912_flash_device = { | 110 | static struct platform_device osk5912_flash_device = { |
| 110 | .name = "omapflash", | 111 | .name = "physmap-flash", |
| 111 | .id = 0, | 112 | .id = 0, |
| 112 | .dev = { | 113 | .dev = { |
| 113 | .platform_data = &osk_flash_data, | 114 | .platform_data = &osk_flash_data, |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 9fe887262bdf..569b4c9085cd 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/mtd/mtd.h> | 24 | #include <linux/mtd/mtd.h> |
| 25 | #include <linux/mtd/partitions.h> | 25 | #include <linux/mtd/partitions.h> |
| 26 | #include <linux/mtd/physmap.h> | ||
| 26 | #include <linux/spi/spi.h> | 27 | #include <linux/spi/spi.h> |
| 27 | #include <linux/interrupt.h> | 28 | #include <linux/interrupt.h> |
| 28 | #include <linux/apm-emulation.h> | 29 | #include <linux/apm-emulation.h> |
| @@ -31,9 +32,9 @@ | |||
| 31 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 34 | #include <asm/mach/flash.h> | ||
| 35 | 35 | ||
| 36 | #include <mach/gpio.h> | 36 | #include <mach/gpio.h> |
| 37 | #include <plat/flash.h> | ||
| 37 | #include <plat/mux.h> | 38 | #include <plat/mux.h> |
| 38 | #include <plat/usb.h> | 39 | #include <plat/usb.h> |
| 39 | #include <plat/tc.h> | 40 | #include <plat/tc.h> |
| @@ -126,9 +127,9 @@ static struct mtd_partition palmte_rom_partitions[] = { | |||
| 126 | }, | 127 | }, |
| 127 | }; | 128 | }; |
| 128 | 129 | ||
| 129 | static struct flash_platform_data palmte_rom_data = { | 130 | static struct physmap_flash_data palmte_rom_data = { |
| 130 | .map_name = "map_rom", | ||
| 131 | .width = 2, | 131 | .width = 2, |
| 132 | .set_vpp = omap1_set_vpp, | ||
| 132 | .parts = palmte_rom_partitions, | 133 | .parts = palmte_rom_partitions, |
| 133 | .nr_parts = ARRAY_SIZE(palmte_rom_partitions), | 134 | .nr_parts = ARRAY_SIZE(palmte_rom_partitions), |
| 134 | }; | 135 | }; |
| @@ -140,7 +141,7 @@ static struct resource palmte_rom_resource = { | |||
| 140 | }; | 141 | }; |
| 141 | 142 | ||
| 142 | static struct platform_device palmte_rom_device = { | 143 | static struct platform_device palmte_rom_device = { |
| 143 | .name = "omapflash", | 144 | .name = "physmap-flash", |
| 144 | .id = -1, | 145 | .id = -1, |
| 145 | .dev = { | 146 | .dev = { |
| 146 | .platform_data = &palmte_rom_data, | 147 | .platform_data = &palmte_rom_data, |
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index af068e3e0fe7..6ad49a2cc1a0 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -21,16 +21,17 @@ | |||
| 21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/mtd/mtd.h> | 22 | #include <linux/mtd/mtd.h> |
| 23 | #include <linux/mtd/partitions.h> | 23 | #include <linux/mtd/partitions.h> |
| 24 | #include <linux/mtd/physmap.h> | ||
| 24 | #include <linux/leds.h> | 25 | #include <linux/leds.h> |
| 25 | 26 | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 30 | #include <asm/mach/flash.h> | ||
| 31 | 31 | ||
| 32 | #include <plat/led.h> | 32 | #include <plat/led.h> |
| 33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
| 34 | #include <plat/flash.h> | ||
| 34 | #include <plat/mux.h> | 35 | #include <plat/mux.h> |
| 35 | #include <plat/usb.h> | 36 | #include <plat/usb.h> |
| 36 | #include <plat/dma.h> | 37 | #include <plat/dma.h> |
| @@ -104,9 +105,9 @@ static struct mtd_partition palmtt_partitions[] = { | |||
| 104 | } | 105 | } |
| 105 | }; | 106 | }; |
| 106 | 107 | ||
| 107 | static struct flash_platform_data palmtt_flash_data = { | 108 | static struct physmap_flash_data palmtt_flash_data = { |
| 108 | .map_name = "cfi_probe", | ||
| 109 | .width = 2, | 109 | .width = 2, |
| 110 | .set_vpp = omap1_set_vpp, | ||
| 110 | .parts = palmtt_partitions, | 111 | .parts = palmtt_partitions, |
| 111 | .nr_parts = ARRAY_SIZE(palmtt_partitions), | 112 | .nr_parts = ARRAY_SIZE(palmtt_partitions), |
| 112 | }; | 113 | }; |
| @@ -118,7 +119,7 @@ static struct resource palmtt_flash_resource = { | |||
| 118 | }; | 119 | }; |
| 119 | 120 | ||
| 120 | static struct platform_device palmtt_flash_device = { | 121 | static struct platform_device palmtt_flash_device = { |
| 121 | .name = "omapflash", | 122 | .name = "physmap-flash", |
| 122 | .id = 0, | 123 | .id = 0, |
| 123 | .dev = { | 124 | .dev = { |
| 124 | .platform_data = &palmtt_flash_data, | 125 | .platform_data = &palmtt_flash_data, |
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index c7a3b6f36500..6641de9257ef 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -25,14 +25,15 @@ | |||
| 25 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/mtd/mtd.h> | 26 | #include <linux/mtd/mtd.h> |
| 27 | #include <linux/mtd/partitions.h> | 27 | #include <linux/mtd/partitions.h> |
| 28 | #include <linux/mtd/physmap.h> | ||
| 28 | 29 | ||
| 29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 32 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 33 | #include <asm/mach/flash.h> | ||
| 34 | 34 | ||
| 35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
| 36 | #include <plat/flash.h> | ||
| 36 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
| 37 | #include <plat/usb.h> | 38 | #include <plat/usb.h> |
| 38 | #include <plat/dma.h> | 39 | #include <plat/dma.h> |
| @@ -126,10 +127,9 @@ static struct mtd_partition palmz71_rom_partitions[] = { | |||
| 126 | }, | 127 | }, |
| 127 | }; | 128 | }; |
| 128 | 129 | ||
| 129 | static struct flash_platform_data palmz71_rom_data = { | 130 | static struct physmap_flash_data palmz71_rom_data = { |
| 130 | .map_name = "map_rom", | ||
| 131 | .name = "onboardrom", | ||
| 132 | .width = 2, | 131 | .width = 2, |
| 132 | .set_vpp = omap1_set_vpp, | ||
| 133 | .parts = palmz71_rom_partitions, | 133 | .parts = palmz71_rom_partitions, |
| 134 | .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), | 134 | .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), |
| 135 | }; | 135 | }; |
| @@ -141,7 +141,7 @@ static struct resource palmz71_rom_resource = { | |||
| 141 | }; | 141 | }; |
| 142 | 142 | ||
| 143 | static struct platform_device palmz71_rom_device = { | 143 | static struct platform_device palmz71_rom_device = { |
| 144 | .name = "omapflash", | 144 | .name = "physmap-flash", |
| 145 | .id = -1, | 145 | .id = -1, |
| 146 | .dev = { | 146 | .dev = { |
| 147 | .platform_data = &palmz71_rom_data, | 147 | .platform_data = &palmz71_rom_data, |
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 1387a4f15da9..e854d5741c88 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c | |||
| @@ -18,19 +18,20 @@ | |||
| 18 | #include <linux/mtd/mtd.h> | 18 | #include <linux/mtd/mtd.h> |
| 19 | #include <linux/mtd/nand.h> | 19 | #include <linux/mtd/nand.h> |
| 20 | #include <linux/mtd/partitions.h> | 20 | #include <linux/mtd/partitions.h> |
| 21 | #include <linux/mtd/physmap.h> | ||
| 21 | #include <linux/input.h> | 22 | #include <linux/input.h> |
| 22 | #include <linux/smc91x.h> | 23 | #include <linux/smc91x.h> |
| 23 | 24 | ||
| 24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 25 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 26 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/flash.h> | ||
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | 29 | ||
| 30 | #include <plat/tc.h> | 30 | #include <plat/tc.h> |
| 31 | #include <mach/gpio.h> | 31 | #include <mach/gpio.h> |
| 32 | #include <plat/mux.h> | 32 | #include <plat/mux.h> |
| 33 | #include <plat/fpga.h> | 33 | #include <plat/fpga.h> |
| 34 | #include <plat/flash.h> | ||
| 34 | #include <plat/keypad.h> | 35 | #include <plat/keypad.h> |
| 35 | #include <plat/common.h> | 36 | #include <plat/common.h> |
| 36 | #include <plat/board.h> | 37 | #include <plat/board.h> |
| @@ -117,9 +118,9 @@ static struct mtd_partition nor_partitions[] = { | |||
| 117 | }, | 118 | }, |
| 118 | }; | 119 | }; |
| 119 | 120 | ||
| 120 | static struct flash_platform_data nor_data = { | 121 | static struct physmap_flash_data nor_data = { |
| 121 | .map_name = "cfi_probe", | ||
| 122 | .width = 2, | 122 | .width = 2, |
| 123 | .set_vpp = omap1_set_vpp, | ||
| 123 | .parts = nor_partitions, | 124 | .parts = nor_partitions, |
| 124 | .nr_parts = ARRAY_SIZE(nor_partitions), | 125 | .nr_parts = ARRAY_SIZE(nor_partitions), |
| 125 | }; | 126 | }; |
| @@ -131,7 +132,7 @@ static struct resource nor_resource = { | |||
| 131 | }; | 132 | }; |
| 132 | 133 | ||
| 133 | static struct platform_device nor_device = { | 134 | static struct platform_device nor_device = { |
| 134 | .name = "omapflash", | 135 | .name = "physmap-flash", |
| 135 | .id = 0, | 136 | .id = 0, |
| 136 | .dev = { | 137 | .dev = { |
| 137 | .platform_data = &nor_data, | 138 | .platform_data = &nor_data, |
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 7a97fac83d8d..2fb1e5f8e2ec 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/notifier.h> | 22 | #include <linux/notifier.h> |
| 23 | #include <linux/mtd/mtd.h> | 23 | #include <linux/mtd/mtd.h> |
| 24 | #include <linux/mtd/partitions.h> | 24 | #include <linux/mtd/partitions.h> |
| 25 | #include <linux/mtd/physmap.h> | ||
| 25 | #include <linux/types.h> | 26 | #include <linux/types.h> |
| 26 | #include <linux/i2c.h> | 27 | #include <linux/i2c.h> |
| 27 | #include <linux/errno.h> | 28 | #include <linux/errno.h> |
| @@ -29,10 +30,10 @@ | |||
| 29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 32 | #include <asm/mach/flash.h> | ||
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | 34 | ||
| 35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
| 36 | #include <plat/flash.h> | ||
| 36 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
| 37 | #include <plat/dma.h> | 38 | #include <plat/dma.h> |
| 38 | #include <plat/irda.h> | 39 | #include <plat/irda.h> |
| @@ -287,9 +288,9 @@ static struct mtd_partition sx1_partitions[] = { | |||
| 287 | } | 288 | } |
| 288 | }; | 289 | }; |
| 289 | 290 | ||
| 290 | static struct flash_platform_data sx1_flash_data = { | 291 | static struct physmap_flash_data sx1_flash_data = { |
| 291 | .map_name = "cfi_probe", | ||
| 292 | .width = 2, | 292 | .width = 2, |
| 293 | .set_vpp = omap1_set_vpp, | ||
| 293 | .parts = sx1_partitions, | 294 | .parts = sx1_partitions, |
| 294 | .nr_parts = ARRAY_SIZE(sx1_partitions), | 295 | .nr_parts = ARRAY_SIZE(sx1_partitions), |
| 295 | }; | 296 | }; |
| @@ -310,7 +311,7 @@ static struct resource sx1_old_flash_resource[] = { | |||
| 310 | }; | 311 | }; |
| 311 | 312 | ||
| 312 | static struct platform_device sx1_flash_device = { | 313 | static struct platform_device sx1_flash_device = { |
| 313 | .name = "omapflash", | 314 | .name = "physmap-flash", |
| 314 | .id = 0, | 315 | .id = 0, |
| 315 | .dev = { | 316 | .dev = { |
| 316 | .platform_data = &sx1_flash_data, | 317 | .platform_data = &sx1_flash_data, |
| @@ -327,7 +328,7 @@ static struct resource sx1_new_flash_resource = { | |||
| 327 | }; | 328 | }; |
| 328 | 329 | ||
| 329 | static struct platform_device sx1_flash_device = { | 330 | static struct platform_device sx1_flash_device = { |
| 330 | .name = "omapflash", | 331 | .name = "physmap-flash", |
| 331 | .id = 0, | 332 | .id = 0, |
| 332 | .dev = { | 333 | .dev = { |
| 333 | .platform_data = &sx1_flash_data, | 334 | .platform_data = &sx1_flash_data, |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 169183537997..87b9436fe7c0 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <linux/irq.h> | 18 | #include <linux/irq.h> |
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/mtd/physmap.h> | ||
| 21 | #include <linux/notifier.h> | 22 | #include <linux/notifier.h> |
| 22 | #include <linux/reboot.h> | 23 | #include <linux/reboot.h> |
| 23 | #include <linux/serial_8250.h> | 24 | #include <linux/serial_8250.h> |
| @@ -27,11 +28,11 @@ | |||
| 27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 28 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 29 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 30 | #include <asm/mach/flash.h> | ||
| 31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| 32 | 32 | ||
| 33 | #include <plat/common.h> | 33 | #include <plat/common.h> |
| 34 | #include <mach/gpio.h> | 34 | #include <mach/gpio.h> |
| 35 | #include <plat/flash.h> | ||
| 35 | #include <plat/mux.h> | 36 | #include <plat/mux.h> |
| 36 | #include <plat/tc.h> | 37 | #include <plat/tc.h> |
| 37 | #include <plat/usb.h> | 38 | #include <plat/usb.h> |
| @@ -86,9 +87,9 @@ static int __init ext_uart_init(void) | |||
| 86 | } | 87 | } |
| 87 | arch_initcall(ext_uart_init); | 88 | arch_initcall(ext_uart_init); |
| 88 | 89 | ||
| 89 | static struct flash_platform_data voiceblue_flash_data = { | 90 | static struct physmap_flash_data voiceblue_flash_data = { |
| 90 | .map_name = "cfi_probe", | ||
| 91 | .width = 2, | 91 | .width = 2, |
| 92 | .set_vpp = omap1_set_vpp, | ||
| 92 | }; | 93 | }; |
| 93 | 94 | ||
| 94 | static struct resource voiceblue_flash_resource = { | 95 | static struct resource voiceblue_flash_resource = { |
| @@ -98,7 +99,7 @@ static struct resource voiceblue_flash_resource = { | |||
| 98 | }; | 99 | }; |
| 99 | 100 | ||
| 100 | static struct platform_device voiceblue_flash_device = { | 101 | static struct platform_device voiceblue_flash_device = { |
| 101 | .name = "omapflash", | 102 | .name = "physmap-flash", |
| 102 | .id = 0, | 103 | .id = 0, |
| 103 | .dev = { | 104 | .dev = { |
| 104 | .platform_data = &voiceblue_flash_data, | 105 | .platform_data = &voiceblue_flash_data, |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 04f1d29cba2c..e0aec1007a0d 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap1/clock.c | 2 | * linux/arch/arm/mach-omap1/clock.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation |
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 6 | * | 6 | * |
| 7 | * Modified to use omap shared clock framework by | 7 | * Modified to use omap shared clock framework by |
| @@ -38,26 +38,6 @@ struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | |||
| 38 | * Omap1 specific clock functions | 38 | * Omap1 specific clock functions |
| 39 | *-------------------------------------------------------------------------*/ | 39 | *-------------------------------------------------------------------------*/ |
| 40 | 40 | ||
| 41 | static int clk_omap1_dummy_enable(struct clk *clk) | ||
| 42 | { | ||
| 43 | return 0; | ||
| 44 | } | ||
| 45 | |||
| 46 | static void clk_omap1_dummy_disable(struct clk *clk) | ||
| 47 | { | ||
| 48 | } | ||
| 49 | |||
| 50 | const struct clkops clkops_dummy = { | ||
| 51 | .enable = clk_omap1_dummy_enable, | ||
| 52 | .disable = clk_omap1_dummy_disable, | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* XXX can be replaced with a fixed_divisor_recalc */ | ||
| 56 | unsigned long omap1_watchdog_recalc(struct clk *clk) | ||
| 57 | { | ||
| 58 | return clk->parent->rate / 14; | ||
| 59 | } | ||
| 60 | |||
| 61 | unsigned long omap1_uart_recalc(struct clk *clk) | 41 | unsigned long omap1_uart_recalc(struct clk *clk) |
| 62 | { | 42 | { |
| 63 | unsigned int val = __raw_readl(clk->enable_reg); | 43 | unsigned int val = __raw_readl(clk->enable_reg); |
| @@ -577,9 +557,6 @@ const struct clkops clkops_uart = { | |||
| 577 | 557 | ||
| 578 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 558 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
| 579 | { | 559 | { |
| 580 | if (clk->flags & RATE_FIXED) | ||
| 581 | return clk->rate; | ||
| 582 | |||
| 583 | if (clk->round_rate != NULL) | 560 | if (clk->round_rate != NULL) |
| 584 | return clk->round_rate(clk, rate); | 561 | return clk->round_rate(clk, rate); |
| 585 | 562 | ||
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 65e7b5b85d83..aa8558adbf1c 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap1/clock_data.c | 2 | * linux/arch/arm/mach-omap1/clock_data.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation |
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
| 7 | * | 7 | * |
| @@ -27,13 +27,6 @@ | |||
| 27 | * Omap1 clocks | 27 | * Omap1 clocks |
| 28 | *-------------------------------------------------------------------------*/ | 28 | *-------------------------------------------------------------------------*/ |
| 29 | 29 | ||
| 30 | /* XXX is this necessary? */ | ||
| 31 | static struct clk dummy_ck = { | ||
| 32 | .name = "dummy", | ||
| 33 | .ops = &clkops_dummy, | ||
| 34 | .flags = RATE_FIXED, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct clk ck_ref = { | 30 | static struct clk ck_ref = { |
| 38 | .name = "ck_ref", | 31 | .name = "ck_ref", |
| 39 | .ops = &clkops_null, | 32 | .ops = &clkops_null, |
| @@ -149,7 +142,8 @@ static struct arm_idlect1_clk armwdt_ck = { | |||
| 149 | .flags = CLOCK_IDLE_CONTROL, | 142 | .flags = CLOCK_IDLE_CONTROL, |
| 150 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | 143 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 151 | .enable_bit = EN_WDTCK, | 144 | .enable_bit = EN_WDTCK, |
| 152 | .recalc = &omap1_watchdog_recalc, | 145 | .fixed_div = 14, |
| 146 | .recalc = &omap_fixed_divisor_recalc, | ||
| 153 | }, | 147 | }, |
| 154 | .idlect_shift = 0, | 148 | .idlect_shift = 0, |
| 155 | }; | 149 | }; |
| @@ -388,8 +382,7 @@ static struct uart_clk uart1_16xx = { | |||
| 388 | /* Direct from ULPD, no real parent */ | 382 | /* Direct from ULPD, no real parent */ |
| 389 | .parent = &armper_ck.clk, | 383 | .parent = &armper_ck.clk, |
| 390 | .rate = 48000000, | 384 | .rate = 48000000, |
| 391 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | 385 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 392 | CLOCK_NO_IDLE_PARENT, | ||
| 393 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 386 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 394 | .enable_bit = 29, | 387 | .enable_bit = 29, |
| 395 | }, | 388 | }, |
| @@ -429,8 +422,7 @@ static struct uart_clk uart3_16xx = { | |||
| 429 | /* Direct from ULPD, no real parent */ | 422 | /* Direct from ULPD, no real parent */ |
| 430 | .parent = &armper_ck.clk, | 423 | .parent = &armper_ck.clk, |
| 431 | .rate = 48000000, | 424 | .rate = 48000000, |
| 432 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | 425 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 433 | CLOCK_NO_IDLE_PARENT, | ||
| 434 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 426 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 435 | .enable_bit = 31, | 427 | .enable_bit = 31, |
| 436 | }, | 428 | }, |
| @@ -442,7 +434,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |||
| 442 | .ops = &clkops_generic, | 434 | .ops = &clkops_generic, |
| 443 | /* Direct from ULPD, no parent */ | 435 | /* Direct from ULPD, no parent */ |
| 444 | .rate = 6000000, | 436 | .rate = 6000000, |
| 445 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 437 | .flags = ENABLE_REG_32BIT, |
| 446 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | 438 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
| 447 | .enable_bit = USB_MCLK_EN_BIT, | 439 | .enable_bit = USB_MCLK_EN_BIT, |
| 448 | }; | 440 | }; |
| @@ -452,7 +444,7 @@ static struct clk usb_hhc_ck1510 = { | |||
| 452 | .ops = &clkops_generic, | 444 | .ops = &clkops_generic, |
| 453 | /* Direct from ULPD, no parent */ | 445 | /* Direct from ULPD, no parent */ |
| 454 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | 446 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
| 455 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 447 | .flags = ENABLE_REG_32BIT, |
| 456 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 448 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 457 | .enable_bit = USB_HOST_HHC_UHOST_EN, | 449 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
| 458 | }; | 450 | }; |
| @@ -463,7 +455,7 @@ static struct clk usb_hhc_ck16xx = { | |||
| 463 | /* Direct from ULPD, no parent */ | 455 | /* Direct from ULPD, no parent */ |
| 464 | .rate = 48000000, | 456 | .rate = 48000000, |
| 465 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | 457 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
| 466 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 458 | .flags = ENABLE_REG_32BIT, |
| 467 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | 459 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
| 468 | .enable_bit = 8 /* UHOST_EN */, | 460 | .enable_bit = 8 /* UHOST_EN */, |
| 469 | }; | 461 | }; |
| @@ -473,7 +465,6 @@ static struct clk usb_dc_ck = { | |||
| 473 | .ops = &clkops_generic, | 465 | .ops = &clkops_generic, |
| 474 | /* Direct from ULPD, no parent */ | 466 | /* Direct from ULPD, no parent */ |
| 475 | .rate = 48000000, | 467 | .rate = 48000000, |
| 476 | .flags = RATE_FIXED, | ||
| 477 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 468 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 478 | .enable_bit = 4, | 469 | .enable_bit = 4, |
| 479 | }; | 470 | }; |
| @@ -483,7 +474,6 @@ static struct clk usb_dc_ck7xx = { | |||
| 483 | .ops = &clkops_generic, | 474 | .ops = &clkops_generic, |
| 484 | /* Direct from ULPD, no parent */ | 475 | /* Direct from ULPD, no parent */ |
| 485 | .rate = 48000000, | 476 | .rate = 48000000, |
| 486 | .flags = RATE_FIXED, | ||
| 487 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 477 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 488 | .enable_bit = 8, | 478 | .enable_bit = 8, |
| 489 | }; | 479 | }; |
| @@ -493,7 +483,6 @@ static struct clk mclk_1510 = { | |||
| 493 | .ops = &clkops_generic, | 483 | .ops = &clkops_generic, |
| 494 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 484 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 495 | .rate = 12000000, | 485 | .rate = 12000000, |
| 496 | .flags = RATE_FIXED, | ||
| 497 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 486 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 498 | .enable_bit = 6, | 487 | .enable_bit = 6, |
| 499 | }; | 488 | }; |
| @@ -514,7 +503,6 @@ static struct clk bclk_1510 = { | |||
| 514 | .ops = &clkops_generic, | 503 | .ops = &clkops_generic, |
| 515 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 504 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 516 | .rate = 12000000, | 505 | .rate = 12000000, |
| 517 | .flags = RATE_FIXED, | ||
| 518 | }; | 506 | }; |
| 519 | 507 | ||
| 520 | static struct clk bclk_16xx = { | 508 | static struct clk bclk_16xx = { |
| @@ -529,36 +517,34 @@ static struct clk bclk_16xx = { | |||
| 529 | }; | 517 | }; |
| 530 | 518 | ||
| 531 | static struct clk mmc1_ck = { | 519 | static struct clk mmc1_ck = { |
| 532 | .name = "mmc_ck", | 520 | .name = "mmc1_ck", |
| 533 | .ops = &clkops_generic, | 521 | .ops = &clkops_generic, |
| 534 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 522 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 535 | .parent = &armper_ck.clk, | 523 | .parent = &armper_ck.clk, |
| 536 | .rate = 48000000, | 524 | .rate = 48000000, |
| 537 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 525 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 538 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 526 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 539 | .enable_bit = 23, | 527 | .enable_bit = 23, |
| 540 | }; | 528 | }; |
| 541 | 529 | ||
| 542 | static struct clk mmc2_ck = { | 530 | static struct clk mmc2_ck = { |
| 543 | .name = "mmc_ck", | 531 | .name = "mmc2_ck", |
| 544 | .id = 1, | ||
| 545 | .ops = &clkops_generic, | 532 | .ops = &clkops_generic, |
| 546 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 533 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 547 | .parent = &armper_ck.clk, | 534 | .parent = &armper_ck.clk, |
| 548 | .rate = 48000000, | 535 | .rate = 48000000, |
| 549 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 536 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 550 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 537 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 551 | .enable_bit = 20, | 538 | .enable_bit = 20, |
| 552 | }; | 539 | }; |
| 553 | 540 | ||
| 554 | static struct clk mmc3_ck = { | 541 | static struct clk mmc3_ck = { |
| 555 | .name = "mmc_ck", | 542 | .name = "mmc3_ck", |
| 556 | .id = 2, | ||
| 557 | .ops = &clkops_generic, | 543 | .ops = &clkops_generic, |
| 558 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 544 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 559 | .parent = &armper_ck.clk, | 545 | .parent = &armper_ck.clk, |
| 560 | .rate = 48000000, | 546 | .rate = 48000000, |
| 561 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 547 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 562 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 548 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 563 | .enable_bit = 12, | 549 | .enable_bit = 12, |
| 564 | }; | 550 | }; |
| @@ -576,7 +562,6 @@ static struct clk virtual_ck_mpu = { | |||
| 576 | remains active during MPU idle whenever this is enabled */ | 562 | remains active during MPU idle whenever this is enabled */ |
| 577 | static struct clk i2c_fck = { | 563 | static struct clk i2c_fck = { |
| 578 | .name = "i2c_fck", | 564 | .name = "i2c_fck", |
| 579 | .id = 1, | ||
| 580 | .ops = &clkops_null, | 565 | .ops = &clkops_null, |
| 581 | .flags = CLOCK_NO_IDLE_PARENT, | 566 | .flags = CLOCK_NO_IDLE_PARENT, |
| 582 | .parent = &armxor_ck.clk, | 567 | .parent = &armxor_ck.clk, |
| @@ -585,7 +570,6 @@ static struct clk i2c_fck = { | |||
| 585 | 570 | ||
| 586 | static struct clk i2c_ick = { | 571 | static struct clk i2c_ick = { |
| 587 | .name = "i2c_ick", | 572 | .name = "i2c_ick", |
| 588 | .id = 1, | ||
| 589 | .ops = &clkops_null, | 573 | .ops = &clkops_null, |
| 590 | .flags = CLOCK_NO_IDLE_PARENT, | 574 | .flags = CLOCK_NO_IDLE_PARENT, |
| 591 | .parent = &armper_ck.clk, | 575 | .parent = &armper_ck.clk, |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index a2d07aa75c9e..379100c17639 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
| @@ -73,7 +73,7 @@ static inline void omap_init_rtc(void) {} | |||
| 73 | # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 | 73 | # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 |
| 74 | #endif | 74 | #endif |
| 75 | 75 | ||
| 76 | #define OMAP1_MBOX_BASE OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE) | 76 | #define OMAP1_MBOX_BASE OMAP16XX_MAILBOX_BASE |
| 77 | 77 | ||
| 78 | static struct resource mbox_resources[] = { | 78 | static struct resource mbox_resources[] = { |
| 79 | { | 79 | { |
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c new file mode 100644 index 000000000000..0b07a78eeaa7 --- /dev/null +++ b/arch/arm/mach-omap1/flash.c | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* | ||
| 2 | * Flash support for OMAP1 | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/mtd/mtd.h> | ||
| 10 | #include <linux/mtd/map.h> | ||
| 11 | |||
| 12 | #include <plat/io.h> | ||
| 13 | #include <plat/tc.h> | ||
| 14 | |||
| 15 | void omap1_set_vpp(struct map_info *map, int enable) | ||
| 16 | { | ||
| 17 | static int count; | ||
| 18 | u32 l; | ||
| 19 | |||
| 20 | if (enable) { | ||
| 21 | if (count++ == 0) { | ||
| 22 | l = omap_readl(EMIFS_CONFIG); | ||
| 23 | l |= OMAP_EMIFS_CONFIG_WP; | ||
| 24 | omap_writel(l, EMIFS_CONFIG); | ||
| 25 | } | ||
| 26 | } else { | ||
| 27 | if (count && (--count == 0)) { | ||
| 28 | l = omap_readl(EMIFS_CONFIG); | ||
| 29 | l &= ~OMAP_EMIFS_CONFIG_WP; | ||
| 30 | omap_writel(l, EMIFS_CONFIG); | ||
| 31 | } | ||
| 32 | } | ||
| 33 | } | ||
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index 1bf4735e27a6..5446c9912641 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c | |||
| @@ -23,9 +23,7 @@ | |||
| 23 | #include <plat/mux.h> | 23 | #include <plat/mux.h> |
| 24 | #include <plat/cpu.h> | 24 | #include <plat/cpu.h> |
| 25 | 25 | ||
| 26 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | 26 | void __init omap1_i2c_mux_pins(int bus_id) |
| 27 | struct i2c_board_info const *info, | ||
| 28 | unsigned len) | ||
| 29 | { | 27 | { |
| 30 | if (cpu_is_omap7xx()) { | 28 | if (cpu_is_omap7xx()) { |
| 31 | omap_cfg_reg(I2C_7XX_SDA); | 29 | omap_cfg_reg(I2C_7XX_SDA); |
| @@ -34,6 +32,4 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 34 | omap_cfg_reg(I2C_SDA); | 32 | omap_cfg_reg(I2C_SDA); |
| 35 | omap_cfg_reg(I2C_SCL); | 33 | omap_cfg_reg(I2C_SCL); |
| 36 | } | 34 | } |
| 37 | |||
| 38 | return omap_plat_register_i2c_bus(bus_id, clkrate, info, len); | ||
| 39 | } | 35 | } |
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index 8c74cab2fa8b..b6d9584544b4 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S | |||
| @@ -11,18 +11,80 @@ | |||
| 11 | * | 11 | * |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/serial_reg.h> | ||
| 15 | |||
| 16 | #include <plat/serial.h> | ||
| 17 | |||
| 18 | .pushsection .data | ||
| 19 | omap_uart_phys: .word 0x0 | ||
| 20 | omap_uart_virt: .word 0x0 | ||
| 21 | .popsection | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Note that this code won't work if the bootloader passes | ||
| 25 | * a wrong machine ID number in r1. To debug, just hardcode | ||
| 26 | * the desired UART phys and virt addresses temporarily into | ||
| 27 | * the omap_uart_phys and omap_uart_virt above. | ||
| 28 | */ | ||
| 14 | .macro addruart, rx, tmp | 29 | .macro addruart, rx, tmp |
| 30 | |||
| 31 | /* Use omap_uart_phys/virt if already configured */ | ||
| 32 | 9: mrc p15, 0, \rx, c1, c0 | ||
| 33 | tst \rx, #1 @ MMU enabled? | ||
| 34 | ldreq \rx, =omap_uart_phys @ physical base address | ||
| 35 | ldrne \rx, =omap_uart_virt @ virtual base | ||
| 36 | ldr \rx, [\rx, #0] | ||
| 37 | cmp \rx, #0 @ is port configured? | ||
| 38 | bne 99f @ already configured | ||
| 39 | |||
| 40 | /* Check 7XX UART1 scratchpad register for uart to use */ | ||
| 41 | mrc p15, 0, \rx, c1, c0 | ||
| 42 | tst \rx, #1 @ MMU enabled? | ||
| 43 | moveq \rx, #0xff000000 @ physical base address | ||
| 44 | movne \rx, #0xfe000000 @ virtual base | ||
| 45 | orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 | ||
| 46 | ldrb \rx, [\rx, #(UART_SCR << OMAP7XX_PORT_SHIFT)] | ||
| 47 | cmp \rx, #0 @ anything in 7XX scratchpad? | ||
| 48 | bne 10f @ found 7XX uart | ||
| 49 | |||
| 50 | /* Check 15xx/16xx UART1 scratchpad register for uart to use */ | ||
| 15 | mrc p15, 0, \rx, c1, c0 | 51 | mrc p15, 0, \rx, c1, c0 |
| 16 | tst \rx, #1 @ MMU enabled? | 52 | tst \rx, #1 @ MMU enabled? |
| 17 | moveq \rx, #0xff000000 @ physical base address | 53 | moveq \rx, #0xff000000 @ physical base address |
| 18 | movne \rx, #0xfe000000 @ virtual base | 54 | movne \rx, #0xfe000000 @ virtual base |
| 19 | orr \rx, \rx, #0x00fb0000 | 55 | orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 |
| 20 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | 56 | ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] |
| 21 | orr \rx, \rx, #0x00009000 @ UART 3 | 57 | |
| 22 | #endif | 58 | /* Select the UART to use based on the UART1 scratchpad value */ |
| 23 | #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) | 59 | 10: cmp \rx, #0 @ no port configured? |
| 24 | orr \rx, \rx, #0x00000800 @ UART 2 & 3 | 60 | beq 11f @ if none, try to use UART1 |
| 25 | #endif | 61 | cmp \rx, #OMAP1UART1 |
| 62 | beq 11f @ configure OMAP1UART1 | ||
| 63 | cmp \rx, #OMAP1UART2 | ||
| 64 | beq 12f @ configure OMAP1UART2 | ||
| 65 | cmp \rx, #OMAP1UART3 | ||
| 66 | beq 13f @ configure OMAP2UART3 | ||
| 67 | |||
| 68 | /* Configure the UART offset from the phys/virt base */ | ||
| 69 | 11: mov \rx, #0x00fb0000 @ OMAP1UART1 | ||
| 70 | b 98f | ||
| 71 | 12: mov \rx, #0x00fb0000 @ OMAP1UART1 | ||
| 72 | orr \rx, \rx, #0x00000800 @ OMAP1UART2 | ||
| 73 | b 98f | ||
| 74 | 13: mov \rx, #0x00fb0000 @ OMAP1UART1 | ||
| 75 | orr \rx, \rx, #0x00000800 @ OMAP1UART2 | ||
| 76 | orr \rx, \rx, #0x00009000 @ OMAP1UART3 | ||
| 77 | |||
| 78 | /* Store both phys and virt address for the uart */ | ||
| 79 | 98: add \rx, \rx, #0xff000000 @ phys base | ||
| 80 | ldr \tmp, =omap_uart_phys | ||
| 81 | str \rx, [\tmp, #0] | ||
| 82 | sub \rx, \rx, #0xff000000 @ phys base | ||
| 83 | add \rx, \rx, #0xfe000000 @ virt base | ||
| 84 | ldr \tmp, =omap_uart_virt | ||
| 85 | str \rx, [\tmp, #0] | ||
| 86 | b 9b | ||
| 87 | 99: | ||
| 26 | .endm | 88 | .endm |
| 27 | 89 | ||
| 28 | .macro senduart,rd,rx | 90 | .macro senduart,rd,rx |
| @@ -30,13 +92,13 @@ | |||
| 30 | .endm | 92 | .endm |
| 31 | 93 | ||
| 32 | .macro busyuart,rd,rx | 94 | .macro busyuart,rd,rx |
| 33 | 1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends | 95 | 1001: ldrb \rd, [\rx, #(UART_LSR << OMAP_PORT_SHIFT)] |
| 34 | and \rd, \rd, #0x60 | 96 | and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
| 35 | teq \rd, #0x60 | 97 | teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
| 36 | beq 1002f | 98 | beq 1002f |
| 37 | ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only | 99 | ldrb \rd, [\rx, #(UART_LSR << OMAP7XX_PORT_SHIFT)] |
| 38 | and \rd, \rd, #0x60 | 100 | and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
| 39 | teq \rd, #0x60 | 101 | teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
| 40 | bne 1001b | 102 | bne 1001b |
| 41 | 1002: | 103 | 1002: |
| 42 | .endm | 104 | .endm |
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index caf889aaa248..4f5b3da3d559 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c | |||
| @@ -146,7 +146,6 @@ EXPORT_SYMBOL(mbox_dsp_info); | |||
| 146 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) | 146 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) |
| 147 | { | 147 | { |
| 148 | struct resource *res; | 148 | struct resource *res; |
| 149 | int ret = 0; | ||
| 150 | 149 | ||
| 151 | if (pdev->num_resources != 2) { | 150 | if (pdev->num_resources != 2) { |
| 152 | dev_err(&pdev->dev, "invalid number of resources: %d\n", | 151 | dev_err(&pdev->dev, "invalid number of resources: %d\n", |
| @@ -160,12 +159,18 @@ static int __devinit omap1_mbox_probe(struct platform_device *pdev) | |||
| 160 | dev_err(&pdev->dev, "invalid mem resource\n"); | 159 | dev_err(&pdev->dev, "invalid mem resource\n"); |
| 161 | return -ENODEV; | 160 | return -ENODEV; |
| 162 | } | 161 | } |
| 163 | mbox_base = res->start; | 162 | |
| 163 | mbox_base = ioremap(res->start, resource_size(res)); | ||
| 164 | if (!mbox_base) { | ||
| 165 | dev_err(&pdev->dev, "ioremap failed\n"); | ||
| 166 | return -ENODEV; | ||
| 167 | } | ||
| 164 | 168 | ||
| 165 | /* DSP IRQ */ | 169 | /* DSP IRQ */ |
| 166 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 170 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 167 | if (unlikely(!res)) { | 171 | if (unlikely(!res)) { |
| 168 | dev_err(&pdev->dev, "invalid irq resource\n"); | 172 | dev_err(&pdev->dev, "invalid irq resource\n"); |
| 173 | iounmap(mbox_base); | ||
| 169 | return -ENODEV; | 174 | return -ENODEV; |
| 170 | } | 175 | } |
| 171 | mbox_dsp_info.irq = res->start; | 176 | mbox_dsp_info.irq = res->start; |
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 6bddce104ee9..f9a5cf750b59 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
| @@ -99,9 +99,11 @@ static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { | |||
| 99 | }, | 99 | }, |
| 100 | }; | 100 | }; |
| 101 | #define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) | 101 | #define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) |
| 102 | #define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) | ||
| 102 | #else | 103 | #else |
| 103 | #define omap7xx_mcbsp_pdata NULL | 104 | #define omap7xx_mcbsp_pdata NULL |
| 104 | #define OMAP7XX_MCBSP_PDATA_SZ 0 | 105 | #define OMAP7XX_MCBSP_PDATA_SZ 0 |
| 106 | #define OMAP7XX_MCBSP_REG_NUM 0 | ||
| 105 | #endif | 107 | #endif |
| 106 | 108 | ||
| 107 | #ifdef CONFIG_ARCH_OMAP15XX | 109 | #ifdef CONFIG_ARCH_OMAP15XX |
| @@ -132,9 +134,11 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { | |||
| 132 | }, | 134 | }, |
| 133 | }; | 135 | }; |
| 134 | #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) | 136 | #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) |
| 137 | #define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) | ||
| 135 | #else | 138 | #else |
| 136 | #define omap15xx_mcbsp_pdata NULL | 139 | #define omap15xx_mcbsp_pdata NULL |
| 137 | #define OMAP15XX_MCBSP_PDATA_SZ 0 | 140 | #define OMAP15XX_MCBSP_PDATA_SZ 0 |
| 141 | #define OMAP15XX_MCBSP_REG_NUM 0 | ||
| 138 | #endif | 142 | #endif |
| 139 | 143 | ||
| 140 | #ifdef CONFIG_ARCH_OMAP16XX | 144 | #ifdef CONFIG_ARCH_OMAP16XX |
| @@ -165,19 +169,25 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
| 165 | }, | 169 | }, |
| 166 | }; | 170 | }; |
| 167 | #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) | 171 | #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) |
| 172 | #define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) | ||
| 168 | #else | 173 | #else |
| 169 | #define omap16xx_mcbsp_pdata NULL | 174 | #define omap16xx_mcbsp_pdata NULL |
| 170 | #define OMAP16XX_MCBSP_PDATA_SZ 0 | 175 | #define OMAP16XX_MCBSP_PDATA_SZ 0 |
| 176 | #define OMAP16XX_MCBSP_REG_NUM 0 | ||
| 171 | #endif | 177 | #endif |
| 172 | 178 | ||
| 173 | int __init omap1_mcbsp_init(void) | 179 | int __init omap1_mcbsp_init(void) |
| 174 | { | 180 | { |
| 175 | if (cpu_is_omap7xx()) | 181 | if (cpu_is_omap7xx()) { |
| 176 | omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; | 182 | omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; |
| 177 | if (cpu_is_omap15xx()) | 183 | omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); |
| 184 | } else if (cpu_is_omap15xx()) { | ||
| 178 | omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; | 185 | omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; |
| 179 | if (cpu_is_omap16xx()) | 186 | omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); |
| 187 | } else if (cpu_is_omap16xx()) { | ||
| 180 | omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; | 188 | omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; |
| 189 | omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16); | ||
| 190 | } | ||
| 181 | 191 | ||
| 182 | mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), | 192 | mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), |
| 183 | GFP_KERNEL); | 193 | GFP_KERNEL); |
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 6e5207c81cf4..349de90194e3 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
| @@ -64,7 +64,7 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p) | |||
| 64 | 64 | ||
| 65 | static struct plat_serial8250_port serial_platform_data[] = { | 65 | static struct plat_serial8250_port serial_platform_data[] = { |
| 66 | { | 66 | { |
| 67 | .mapbase = OMAP_UART1_BASE, | 67 | .mapbase = OMAP1_UART1_BASE, |
| 68 | .irq = INT_UART1, | 68 | .irq = INT_UART1, |
| 69 | .flags = UPF_BOOT_AUTOCONF, | 69 | .flags = UPF_BOOT_AUTOCONF, |
| 70 | .iotype = UPIO_MEM, | 70 | .iotype = UPIO_MEM, |
| @@ -72,7 +72,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 72 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 72 | .uartclk = OMAP16XX_BASE_BAUD * 16, |
| 73 | }, | 73 | }, |
| 74 | { | 74 | { |
| 75 | .mapbase = OMAP_UART2_BASE, | 75 | .mapbase = OMAP1_UART2_BASE, |
| 76 | .irq = INT_UART2, | 76 | .irq = INT_UART2, |
| 77 | .flags = UPF_BOOT_AUTOCONF, | 77 | .flags = UPF_BOOT_AUTOCONF, |
| 78 | .iotype = UPIO_MEM, | 78 | .iotype = UPIO_MEM, |
| @@ -80,7 +80,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 80 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 80 | .uartclk = OMAP16XX_BASE_BAUD * 16, |
| 81 | }, | 81 | }, |
| 82 | { | 82 | { |
| 83 | .mapbase = OMAP_UART3_BASE, | 83 | .mapbase = OMAP1_UART3_BASE, |
| 84 | .irq = INT_UART3, | 84 | .irq = INT_UART3, |
| 85 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
| 86 | .iotype = UPIO_MEM, | 86 | .iotype = UPIO_MEM, |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 606bf04f51b6..a8a3d1e23e26 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -1,28 +1,19 @@ | |||
| 1 | comment "OMAP Core Type" | 1 | comment "OMAP Core Type" |
| 2 | depends on ARCH_OMAP2 | 2 | depends on ARCH_OMAP2 |
| 3 | 3 | ||
| 4 | config ARCH_OMAP24XX | ||
| 5 | bool "OMAP24xx Based System" | ||
| 6 | depends on ARCH_OMAP2 | ||
| 7 | |||
| 8 | config ARCH_OMAP2420 | 4 | config ARCH_OMAP2420 |
| 9 | bool "OMAP2420 support" | 5 | bool "OMAP2420 support" |
| 10 | depends on ARCH_OMAP24XX | 6 | depends on ARCH_OMAP2 |
| 11 | select OMAP_DM_TIMER | 7 | select OMAP_DM_TIMER |
| 12 | select ARCH_OMAP_OTG | 8 | select ARCH_OMAP_OTG |
| 13 | 9 | ||
| 14 | config ARCH_OMAP2430 | 10 | config ARCH_OMAP2430 |
| 15 | bool "OMAP2430 support" | 11 | bool "OMAP2430 support" |
| 16 | depends on ARCH_OMAP24XX | 12 | depends on ARCH_OMAP2 |
| 17 | |||
| 18 | config ARCH_OMAP34XX | ||
| 19 | bool "OMAP34xx Based System" | ||
| 20 | depends on ARCH_OMAP3 | ||
| 21 | select USB_ARCH_HAS_EHCI | ||
| 22 | 13 | ||
| 23 | config ARCH_OMAP3430 | 14 | config ARCH_OMAP3430 |
| 24 | bool "OMAP3430 support" | 15 | bool "OMAP3430 support" |
| 25 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 16 | depends on ARCH_OMAP3 |
| 26 | select ARCH_OMAP_OTG | 17 | select ARCH_OMAP_OTG |
| 27 | 18 | ||
| 28 | config OMAP_PACKAGE_CBC | 19 | config OMAP_PACKAGE_CBC |
| @@ -38,11 +29,11 @@ config OMAP_PACKAGE_CBP | |||
| 38 | bool | 29 | bool |
| 39 | 30 | ||
| 40 | comment "OMAP Board Type" | 31 | comment "OMAP Board Type" |
| 41 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 | 32 | depends on ARCH_OMAP2PLUS |
| 42 | 33 | ||
| 43 | config MACH_OMAP_GENERIC | 34 | config MACH_OMAP_GENERIC |
| 44 | bool "Generic OMAP board" | 35 | bool "Generic OMAP board" |
| 45 | depends on ARCH_OMAP2 && ARCH_OMAP24XX | 36 | depends on ARCH_OMAP2 |
| 46 | 37 | ||
| 47 | config MACH_OMAP2_TUSB6010 | 38 | config MACH_OMAP2_TUSB6010 |
| 48 | bool | 39 | bool |
| @@ -51,55 +42,59 @@ config MACH_OMAP2_TUSB6010 | |||
| 51 | 42 | ||
| 52 | config MACH_OMAP_H4 | 43 | config MACH_OMAP_H4 |
| 53 | bool "OMAP 2420 H4 board" | 44 | bool "OMAP 2420 H4 board" |
| 54 | depends on ARCH_OMAP2 && ARCH_OMAP24XX | 45 | depends on ARCH_OMAP2 |
| 55 | select OMAP_DEBUG_DEVICES | 46 | select OMAP_DEBUG_DEVICES |
| 56 | 47 | ||
| 57 | config MACH_OMAP_APOLLON | 48 | config MACH_OMAP_APOLLON |
| 58 | bool "OMAP 2420 Apollon board" | 49 | bool "OMAP 2420 Apollon board" |
| 59 | depends on ARCH_OMAP2 && ARCH_OMAP24XX | 50 | depends on ARCH_OMAP2 |
| 60 | 51 | ||
| 61 | config MACH_OMAP_2430SDP | 52 | config MACH_OMAP_2430SDP |
| 62 | bool "OMAP 2430 SDP board" | 53 | bool "OMAP 2430 SDP board" |
| 63 | depends on ARCH_OMAP2 && ARCH_OMAP24XX | 54 | depends on ARCH_OMAP2 |
| 64 | 55 | ||
| 65 | config MACH_OMAP3_BEAGLE | 56 | config MACH_OMAP3_BEAGLE |
| 66 | bool "OMAP3 BEAGLE board" | 57 | bool "OMAP3 BEAGLE board" |
| 67 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 58 | depends on ARCH_OMAP3 |
| 68 | select OMAP_PACKAGE_CBB | 59 | select OMAP_PACKAGE_CBB |
| 69 | 60 | ||
| 61 | config MACH_DEVKIT8000 | ||
| 62 | bool "DEVKIT8000 board" | ||
| 63 | depends on ARCH_OMAP3 | ||
| 64 | |||
| 70 | config MACH_OMAP_LDP | 65 | config MACH_OMAP_LDP |
| 71 | bool "OMAP3 LDP board" | 66 | bool "OMAP3 LDP board" |
| 72 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 67 | depends on ARCH_OMAP3 |
| 73 | select OMAP_PACKAGE_CBB | 68 | select OMAP_PACKAGE_CBB |
| 74 | 69 | ||
| 75 | config MACH_OVERO | 70 | config MACH_OVERO |
| 76 | bool "Gumstix Overo board" | 71 | bool "Gumstix Overo board" |
| 77 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 72 | depends on ARCH_OMAP3 |
| 78 | select OMAP_PACKAGE_CBB | 73 | select OMAP_PACKAGE_CBB |
| 79 | 74 | ||
| 80 | config MACH_OMAP3EVM | 75 | config MACH_OMAP3EVM |
| 81 | bool "OMAP 3530 EVM board" | 76 | bool "OMAP 3530 EVM board" |
| 82 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 77 | depends on ARCH_OMAP3 |
| 83 | select OMAP_PACKAGE_CBB | 78 | select OMAP_PACKAGE_CBB |
| 84 | 79 | ||
| 85 | config MACH_OMAP3517EVM | 80 | config MACH_OMAP3517EVM |
| 86 | bool "OMAP3517/ AM3517 EVM board" | 81 | bool "OMAP3517/ AM3517 EVM board" |
| 87 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 82 | depends on ARCH_OMAP3 |
| 88 | select OMAP_PACKAGE_CBB | 83 | select OMAP_PACKAGE_CBB |
| 89 | 84 | ||
| 90 | config MACH_OMAP3_PANDORA | 85 | config MACH_OMAP3_PANDORA |
| 91 | bool "OMAP3 Pandora" | 86 | bool "OMAP3 Pandora" |
| 92 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 87 | depends on ARCH_OMAP3 |
| 93 | select OMAP_PACKAGE_CBB | 88 | select OMAP_PACKAGE_CBB |
| 94 | 89 | ||
| 95 | config MACH_OMAP3_TOUCHBOOK | 90 | config MACH_OMAP3_TOUCHBOOK |
| 96 | bool "OMAP3 Touch Book" | 91 | bool "OMAP3 Touch Book" |
| 97 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 92 | depends on ARCH_OMAP3 |
| 98 | select BACKLIGHT_CLASS_DEVICE | 93 | select BACKLIGHT_CLASS_DEVICE |
| 99 | 94 | ||
| 100 | config MACH_OMAP_3430SDP | 95 | config MACH_OMAP_3430SDP |
| 101 | bool "OMAP 3430 SDP board" | 96 | bool "OMAP 3430 SDP board" |
| 102 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 97 | depends on ARCH_OMAP3 |
| 103 | select OMAP_PACKAGE_CBB | 98 | select OMAP_PACKAGE_CBB |
| 104 | 99 | ||
| 105 | config MACH_NOKIA_N800 | 100 | config MACH_NOKIA_N800 |
| @@ -120,33 +115,33 @@ config MACH_NOKIA_N8X0 | |||
| 120 | 115 | ||
| 121 | config MACH_NOKIA_RX51 | 116 | config MACH_NOKIA_RX51 |
| 122 | bool "Nokia RX-51 board" | 117 | bool "Nokia RX-51 board" |
| 123 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 118 | depends on ARCH_OMAP3 |
| 124 | select OMAP_PACKAGE_CBB | 119 | select OMAP_PACKAGE_CBB |
| 125 | 120 | ||
| 126 | config MACH_OMAP_ZOOM2 | 121 | config MACH_OMAP_ZOOM2 |
| 127 | bool "OMAP3 Zoom2 board" | 122 | bool "OMAP3 Zoom2 board" |
| 128 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 123 | depends on ARCH_OMAP3 |
| 129 | select OMAP_PACKAGE_CBB | 124 | select OMAP_PACKAGE_CBB |
| 130 | 125 | ||
| 131 | config MACH_OMAP_ZOOM3 | 126 | config MACH_OMAP_ZOOM3 |
| 132 | bool "OMAP3630 Zoom3 board" | 127 | bool "OMAP3630 Zoom3 board" |
| 133 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 128 | depends on ARCH_OMAP3 |
| 134 | select OMAP_PACKAGE_CBP | 129 | select OMAP_PACKAGE_CBP |
| 135 | 130 | ||
| 136 | config MACH_CM_T35 | 131 | config MACH_CM_T35 |
| 137 | bool "CompuLab CM-T35 module" | 132 | bool "CompuLab CM-T35 module" |
| 138 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 133 | depends on ARCH_OMAP3 |
| 139 | select OMAP_PACKAGE_CUS | 134 | select OMAP_PACKAGE_CUS |
| 140 | select OMAP_MUX | 135 | select OMAP_MUX |
| 141 | 136 | ||
| 142 | config MACH_IGEP0020 | 137 | config MACH_IGEP0020 |
| 143 | bool "IGEP0020" | 138 | bool "IGEP v2 board" |
| 144 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 139 | depends on ARCH_OMAP3 |
| 145 | select OMAP_PACKAGE_CBB | 140 | select OMAP_PACKAGE_CBB |
| 146 | 141 | ||
| 147 | config MACH_OMAP_3630SDP | 142 | config MACH_OMAP_3630SDP |
| 148 | bool "OMAP3630 SDP board" | 143 | bool "OMAP3630 SDP board" |
| 149 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 144 | depends on ARCH_OMAP3 |
| 150 | select OMAP_PACKAGE_CBP | 145 | select OMAP_PACKAGE_CBP |
| 151 | 146 | ||
| 152 | config MACH_OMAP_4430SDP | 147 | config MACH_OMAP_4430SDP |
| @@ -162,7 +157,7 @@ config OMAP3_EMU | |||
| 162 | 157 | ||
| 163 | config OMAP3_SDRC_AC_TIMING | 158 | config OMAP3_SDRC_AC_TIMING |
| 164 | bool "Enable SDRC AC timing register changes" | 159 | bool "Enable SDRC AC timing register changes" |
| 165 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | 160 | depends on ARCH_OMAP3 |
| 166 | default n | 161 | default n |
| 167 | help | 162 | help |
| 168 | If you know that none of your system initiators will attempt to | 163 | If you know that none of your system initiators will attempt to |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b32678b848bc..2069fb33baaa 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -5,15 +5,17 @@ | |||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o | 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o |
| 7 | 7 | ||
| 8 | omap-2-3-common = irq.o sdrc.o omap_hwmod.o | 8 | omap-2-3-common = irq.o sdrc.o |
| 9 | omap-3-4-common = dpll.o | 9 | hwmod-common = omap_hwmod.o \ |
| 10 | omap_hwmod_common_data.o | ||
| 10 | prcm-common = prcm.o powerdomain.o | 11 | prcm-common = prcm.o powerdomain.o |
| 11 | clock-common = clock.o clock_common_data.o clockdomain.o | 12 | clock-common = clock.o clock_common_data.o \ |
| 13 | clockdomain.o clkt_dpll.o \ | ||
| 14 | clkt_clksel.o | ||
| 12 | 15 | ||
| 13 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) | 16 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) |
| 14 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ | 17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) |
| 15 | $(omap-3-4-common) | 18 | obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) |
| 16 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o | ||
| 17 | 19 | ||
| 18 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 20 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
| 19 | 21 | ||
| @@ -26,6 +28,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o | |||
| 26 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o | 28 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o |
| 27 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o | 29 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o |
| 28 | 30 | ||
| 31 | AFLAGS_sram242x.o :=-Wa,-march=armv6 | ||
| 32 | AFLAGS_sram243x.o :=-Wa,-march=armv6 | ||
| 33 | AFLAGS_sram34xx.o :=-Wa,-march=armv7-a | ||
| 34 | |||
| 29 | # Pin multiplexing | 35 | # Pin multiplexing |
| 30 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o | 36 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o |
| 31 | 37 | ||
| @@ -36,9 +42,13 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | |||
| 36 | # Power Management | 42 | # Power Management |
| 37 | ifeq ($(CONFIG_PM),y) | 43 | ifeq ($(CONFIG_PM),y) |
| 38 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | 44 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o |
| 39 | obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o | 45 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o |
| 40 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o | 46 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o |
| 41 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 47 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
| 48 | |||
| 49 | AFLAGS_sleep24xx.o :=-Wa,-march=armv6 | ||
| 50 | AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a | ||
| 51 | |||
| 42 | endif | 52 | endif |
| 43 | 53 | ||
| 44 | # PRCM | 54 | # PRCM |
| @@ -47,14 +57,31 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o | |||
| 47 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o | 57 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o |
| 48 | 58 | ||
| 49 | # Clock framework | 59 | # Clock framework |
| 50 | obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o | 60 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ |
| 61 | clkt2xxx_sys.o \ | ||
| 62 | clkt2xxx_dpllcore.o \ | ||
| 63 | clkt2xxx_virt_prcm_set.o \ | ||
| 64 | clkt2xxx_apll.o clkt2xxx_osc.o | ||
| 65 | obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o | ||
| 66 | obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o | ||
| 67 | obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ | ||
| 68 | clock34xx.o clkt34xx_dpll3m2.o \ | ||
| 69 | clock3517.o clock36xx.o \ | ||
| 70 | dpll3xxx.o clock3xxx_data.o | ||
| 71 | obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ | ||
| 72 | dpll3xxx.o | ||
| 73 | |||
| 74 | # OMAP2 clock rate set data (old "OPP" data) | ||
| 51 | obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o | 75 | obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o |
| 52 | obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o | ||
| 53 | obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o | 76 | obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o |
| 54 | obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o | 77 | |
| 78 | # hwmod data | ||
| 79 | obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o | ||
| 80 | obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o | ||
| 81 | obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o | ||
| 55 | 82 | ||
| 56 | # EMU peripherals | 83 | # EMU peripherals |
| 57 | obj-$(CONFIG_OMAP3_EMU) += emu.o | 84 | obj-$(CONFIG_OMAP3_EMU) += emu.o |
| 58 | 85 | ||
| 59 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o | 86 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o |
| 60 | mailbox_mach-objs := mailbox.o | 87 | mailbox_mach-objs := mailbox.o |
| @@ -71,45 +98,48 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) | |||
| 71 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o | 98 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o |
| 72 | obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o | 99 | obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o |
| 73 | obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \ | 100 | obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \ |
| 74 | mmc-twl4030.o | 101 | hsmmc.o |
| 75 | obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o | 102 | obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o |
| 76 | obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ | 103 | obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ |
| 77 | mmc-twl4030.o | 104 | hsmmc.o |
| 105 | obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ | ||
| 106 | hsmmc.o | ||
| 78 | obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ | 107 | obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ |
| 79 | mmc-twl4030.o | 108 | hsmmc.o |
| 80 | obj-$(CONFIG_MACH_OVERO) += board-overo.o \ | 109 | obj-$(CONFIG_MACH_OVERO) += board-overo.o \ |
| 81 | mmc-twl4030.o | 110 | hsmmc.o |
| 82 | obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ | 111 | obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ |
| 83 | mmc-twl4030.o | 112 | hsmmc.o |
| 84 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ | 113 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ |
| 85 | mmc-twl4030.o | 114 | hsmmc.o |
| 86 | obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ | 115 | obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ |
| 87 | mmc-twl4030.o | 116 | hsmmc.o \ |
| 117 | board-sdp-flash.o | ||
| 88 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o | 118 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o |
| 89 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ | 119 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ |
| 90 | board-rx51-sdram.o \ | 120 | board-rx51-sdram.o \ |
| 91 | board-rx51-peripherals.o \ | 121 | board-rx51-peripherals.o \ |
| 92 | mmc-twl4030.o | 122 | hsmmc.o |
| 93 | obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ | 123 | obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ |
| 94 | board-zoom-peripherals.o \ | 124 | board-zoom-peripherals.o \ |
| 95 | mmc-twl4030.o \ | 125 | hsmmc.o \ |
| 96 | board-zoom-debugboard.o | 126 | board-zoom-debugboard.o |
| 97 | obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ | 127 | obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ |
| 98 | board-zoom-peripherals.o \ | 128 | board-zoom-peripherals.o \ |
| 99 | mmc-twl4030.o \ | 129 | hsmmc.o \ |
| 100 | board-zoom-debugboard.o | 130 | board-zoom-debugboard.o |
| 101 | obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ | 131 | obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ |
| 102 | board-zoom-peripherals.o \ | 132 | board-zoom-peripherals.o \ |
| 103 | mmc-twl4030.o | 133 | hsmmc.o |
| 104 | obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ | 134 | obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ |
| 105 | mmc-twl4030.o | 135 | hsmmc.o |
| 106 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ | 136 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ |
| 107 | mmc-twl4030.o | 137 | hsmmc.o |
| 108 | obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ | 138 | obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ |
| 109 | mmc-twl4030.o | 139 | hsmmc.o |
| 110 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o | 140 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o |
| 111 | 141 | ||
| 112 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 142 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
| 113 | 143 | ||
| 114 | # Platform specific device init code | 144 | # Platform specific device init code |
| 115 | obj-y += usb-musb.o | 145 | obj-y += usb-musb.o |
| @@ -119,5 +149,8 @@ obj-y += usb-ehci.o | |||
| 119 | onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o | 149 | onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o |
| 120 | obj-y += $(onenand-m) $(onenand-y) | 150 | obj-y += $(onenand-m) $(onenand-y) |
| 121 | 151 | ||
| 152 | nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o | ||
| 153 | obj-y += $(nand-m) $(nand-y) | ||
| 154 | |||
| 122 | smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o | 155 | smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o |
| 123 | obj-y += $(smc91x-m) $(smc91x-y) | 156 | obj-y += $(smc91x-m) $(smc91x-y) |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index e508904fb67e..01d113ff9fcf 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/mtd/mtd.h> | 19 | #include <linux/mtd/mtd.h> |
| 20 | #include <linux/mtd/partitions.h> | 20 | #include <linux/mtd/partitions.h> |
| 21 | #include <linux/mtd/physmap.h> | ||
| 21 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 22 | #include <linux/i2c/twl.h> | 23 | #include <linux/i2c/twl.h> |
| 23 | #include <linux/err.h> | 24 | #include <linux/err.h> |
| @@ -28,7 +29,6 @@ | |||
| 28 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 29 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 30 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| 31 | #include <asm/mach/flash.h> | ||
| 32 | 32 | ||
| 33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
| 34 | #include <plat/mux.h> | 34 | #include <plat/mux.h> |
| @@ -38,7 +38,7 @@ | |||
| 38 | #include <plat/usb.h> | 38 | #include <plat/usb.h> |
| 39 | #include <plat/gpmc-smc91x.h> | 39 | #include <plat/gpmc-smc91x.h> |
| 40 | 40 | ||
| 41 | #include "mmc-twl4030.h" | 41 | #include "hsmmc.h" |
| 42 | 42 | ||
| 43 | #define SDP2430_CS0_BASE 0x04000000 | 43 | #define SDP2430_CS0_BASE 0x04000000 |
| 44 | #define SECONDARY_LCD_GPIO 147 | 44 | #define SECONDARY_LCD_GPIO 147 |
| @@ -74,8 +74,7 @@ static struct mtd_partition sdp2430_partitions[] = { | |||
| 74 | } | 74 | } |
| 75 | }; | 75 | }; |
| 76 | 76 | ||
| 77 | static struct flash_platform_data sdp2430_flash_data = { | 77 | static struct physmap_flash_data sdp2430_flash_data = { |
| 78 | .map_name = "cfi_probe", | ||
| 79 | .width = 2, | 78 | .width = 2, |
| 80 | .parts = sdp2430_partitions, | 79 | .parts = sdp2430_partitions, |
| 81 | .nr_parts = ARRAY_SIZE(sdp2430_partitions), | 80 | .nr_parts = ARRAY_SIZE(sdp2430_partitions), |
| @@ -88,7 +87,7 @@ static struct resource sdp2430_flash_resource = { | |||
| 88 | }; | 87 | }; |
| 89 | 88 | ||
| 90 | static struct platform_device sdp2430_flash_device = { | 89 | static struct platform_device sdp2430_flash_device = { |
| 91 | .name = "omapflash", | 90 | .name = "physmap-flash", |
| 92 | .id = 0, | 91 | .id = 0, |
| 93 | .dev = { | 92 | .dev = { |
| 94 | .platform_data = &sdp2430_flash_data, | 93 | .platform_data = &sdp2430_flash_data, |
| @@ -183,7 +182,7 @@ static int __init omap2430_i2c_init(void) | |||
| 183 | return 0; | 182 | return 0; |
| 184 | } | 183 | } |
| 185 | 184 | ||
| 186 | static struct twl4030_hsmmc_info mmc[] __initdata = { | 185 | static struct omap2_hsmmc_info mmc[] __initdata = { |
| 187 | { | 186 | { |
| 188 | .mmc = 1, | 187 | .mmc = 1, |
| 189 | .wires = 4, | 188 | .wires = 4, |
| @@ -194,6 +193,12 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { | |||
| 194 | {} /* Terminator */ | 193 | {} /* Terminator */ |
| 195 | }; | 194 | }; |
| 196 | 195 | ||
| 196 | static struct omap_musb_board_data musb_board_data = { | ||
| 197 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 198 | .mode = MUSB_OTG, | ||
| 199 | .power = 100, | ||
| 200 | }; | ||
| 201 | |||
| 197 | static void __init omap_2430sdp_init(void) | 202 | static void __init omap_2430sdp_init(void) |
| 198 | { | 203 | { |
| 199 | int ret; | 204 | int ret; |
| @@ -202,8 +207,8 @@ static void __init omap_2430sdp_init(void) | |||
| 202 | 207 | ||
| 203 | platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); | 208 | platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); |
| 204 | omap_serial_init(); | 209 | omap_serial_init(); |
| 205 | twl4030_mmc_init(mmc); | 210 | omap2_hsmmc_init(mmc); |
| 206 | usb_musb_init(); | 211 | usb_musb_init(&musb_board_data); |
| 207 | board_smc91x_init(); | 212 | board_smc91x_init(); |
| 208 | 213 | ||
| 209 | /* Turn off secondary LCD backlight */ | 214 | /* Turn off secondary LCD backlight */ |
| @@ -215,7 +220,7 @@ static void __init omap_2430sdp_init(void) | |||
| 215 | static void __init omap_2430sdp_map_io(void) | 220 | static void __init omap_2430sdp_map_io(void) |
| 216 | { | 221 | { |
| 217 | omap2_set_globals_243x(); | 222 | omap2_set_globals_243x(); |
| 218 | omap2_map_common_io(); | 223 | omap243x_map_common_io(); |
| 219 | } | 224 | } |
| 220 | 225 | ||
| 221 | MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") | 226 | MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index c90b0d0b1927..f312b1513753 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -41,9 +41,12 @@ | |||
| 41 | #include <plat/control.h> | 41 | #include <plat/control.h> |
| 42 | #include <plat/gpmc-smc91x.h> | 42 | #include <plat/gpmc-smc91x.h> |
| 43 | 43 | ||
| 44 | #include <mach/board-sdp.h> | ||
| 45 | |||
| 44 | #include "mux.h" | 46 | #include "mux.h" |
| 45 | #include "sdram-qimonda-hyb18m512160af-6.h" | 47 | #include "sdram-qimonda-hyb18m512160af-6.h" |
| 46 | #include "mmc-twl4030.h" | 48 | #include "hsmmc.h" |
| 49 | #include "pm.h" | ||
| 47 | 50 | ||
| 48 | #define CONFIG_DISABLE_HFCLK 1 | 51 | #define CONFIG_DISABLE_HFCLK 1 |
| 49 | 52 | ||
| @@ -55,6 +58,24 @@ | |||
| 55 | 58 | ||
| 56 | #define TWL4030_MSECURE_GPIO 22 | 59 | #define TWL4030_MSECURE_GPIO 22 |
| 57 | 60 | ||
| 61 | /* FIXME: These values need to be updated based on more profiling on 3430sdp*/ | ||
| 62 | static struct cpuidle_params omap3_cpuidle_params_table[] = { | ||
| 63 | /* C1 */ | ||
| 64 | {1, 2, 2, 5}, | ||
| 65 | /* C2 */ | ||
| 66 | {1, 10, 10, 30}, | ||
| 67 | /* C3 */ | ||
| 68 | {1, 50, 50, 300}, | ||
| 69 | /* C4 */ | ||
| 70 | {1, 1500, 1800, 4000}, | ||
| 71 | /* C5 */ | ||
| 72 | {1, 2500, 7500, 12000}, | ||
| 73 | /* C6 */ | ||
| 74 | {1, 3000, 8500, 15000}, | ||
| 75 | /* C7 */ | ||
| 76 | {1, 10000, 30000, 300000}, | ||
| 77 | }; | ||
| 78 | |||
| 58 | static int board_keymap[] = { | 79 | static int board_keymap[] = { |
| 59 | KEY(0, 0, KEY_LEFT), | 80 | KEY(0, 0, KEY_LEFT), |
| 60 | KEY(0, 1, KEY_RIGHT), | 81 | KEY(0, 1, KEY_RIGHT), |
| @@ -305,6 +326,7 @@ static void __init omap_3430sdp_init_irq(void) | |||
| 305 | { | 326 | { |
| 306 | omap_board_config = sdp3430_config; | 327 | omap_board_config = sdp3430_config; |
| 307 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); | 328 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); |
| 329 | omap3_pm_init_cpuidle(omap3_cpuidle_params_table); | ||
| 308 | omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); | 330 | omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); |
| 309 | omap_init_irq(); | 331 | omap_init_irq(); |
| 310 | omap_gpio_init(); | 332 | omap_gpio_init(); |
| @@ -326,7 +348,7 @@ static struct twl4030_bci_platform_data sdp3430_bci_data = { | |||
| 326 | .tblsize = ARRAY_SIZE(sdp3430_batt_table), | 348 | .tblsize = ARRAY_SIZE(sdp3430_batt_table), |
| 327 | }; | 349 | }; |
| 328 | 350 | ||
| 329 | static struct twl4030_hsmmc_info mmc[] = { | 351 | static struct omap2_hsmmc_info mmc[] = { |
| 330 | { | 352 | { |
| 331 | .mmc = 1, | 353 | .mmc = 1, |
| 332 | /* 8 bits (default) requires S6.3 == ON, | 354 | /* 8 bits (default) requires S6.3 == ON, |
| @@ -363,7 +385,7 @@ static int sdp3430_twl_gpio_setup(struct device *dev, | |||
| 363 | */ | 385 | */ |
| 364 | mmc[0].gpio_cd = gpio + 0; | 386 | mmc[0].gpio_cd = gpio + 0; |
| 365 | mmc[1].gpio_cd = gpio + 1; | 387 | mmc[1].gpio_cd = gpio + 1; |
| 366 | twl4030_mmc_init(mmc); | 388 | omap2_hsmmc_init(mmc); |
| 367 | 389 | ||
| 368 | /* link regulators to MMC adapters ... we "know" the | 390 | /* link regulators to MMC adapters ... we "know" the |
| 369 | * regulators will be set up only *after* we return. | 391 | * regulators will be set up only *after* we return. |
| @@ -650,6 +672,120 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 650 | #define board_mux NULL | 672 | #define board_mux NULL |
| 651 | #endif | 673 | #endif |
| 652 | 674 | ||
| 675 | static struct mtd_partition sdp_nor_partitions[] = { | ||
| 676 | /* bootloader (U-Boot, etc) in first sector */ | ||
| 677 | { | ||
| 678 | .name = "Bootloader-NOR", | ||
| 679 | .offset = 0, | ||
| 680 | .size = SZ_256K, | ||
| 681 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 682 | }, | ||
| 683 | /* bootloader params in the next sector */ | ||
| 684 | { | ||
| 685 | .name = "Params-NOR", | ||
| 686 | .offset = MTDPART_OFS_APPEND, | ||
| 687 | .size = SZ_256K, | ||
| 688 | .mask_flags = 0, | ||
| 689 | }, | ||
| 690 | /* kernel */ | ||
| 691 | { | ||
| 692 | .name = "Kernel-NOR", | ||
| 693 | .offset = MTDPART_OFS_APPEND, | ||
| 694 | .size = SZ_2M, | ||
| 695 | .mask_flags = 0 | ||
| 696 | }, | ||
| 697 | /* file system */ | ||
| 698 | { | ||
| 699 | .name = "Filesystem-NOR", | ||
| 700 | .offset = MTDPART_OFS_APPEND, | ||
| 701 | .size = MTDPART_SIZ_FULL, | ||
| 702 | .mask_flags = 0 | ||
| 703 | } | ||
| 704 | }; | ||
| 705 | |||
| 706 | static struct mtd_partition sdp_onenand_partitions[] = { | ||
| 707 | { | ||
| 708 | .name = "X-Loader-OneNAND", | ||
| 709 | .offset = 0, | ||
| 710 | .size = 4 * (64 * 2048), | ||
| 711 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 712 | }, | ||
| 713 | { | ||
| 714 | .name = "U-Boot-OneNAND", | ||
| 715 | .offset = MTDPART_OFS_APPEND, | ||
| 716 | .size = 2 * (64 * 2048), | ||
| 717 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 718 | }, | ||
| 719 | { | ||
| 720 | .name = "U-Boot Environment-OneNAND", | ||
| 721 | .offset = MTDPART_OFS_APPEND, | ||
| 722 | .size = 1 * (64 * 2048), | ||
| 723 | }, | ||
| 724 | { | ||
| 725 | .name = "Kernel-OneNAND", | ||
| 726 | .offset = MTDPART_OFS_APPEND, | ||
| 727 | .size = 16 * (64 * 2048), | ||
| 728 | }, | ||
| 729 | { | ||
| 730 | .name = "File System-OneNAND", | ||
| 731 | .offset = MTDPART_OFS_APPEND, | ||
| 732 | .size = MTDPART_SIZ_FULL, | ||
| 733 | }, | ||
| 734 | }; | ||
| 735 | |||
| 736 | static struct mtd_partition sdp_nand_partitions[] = { | ||
| 737 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 738 | { | ||
| 739 | .name = "X-Loader-NAND", | ||
| 740 | .offset = 0, | ||
| 741 | .size = 4 * (64 * 2048), | ||
| 742 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 743 | }, | ||
| 744 | { | ||
| 745 | .name = "U-Boot-NAND", | ||
| 746 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 747 | .size = 10 * (64 * 2048), | ||
| 748 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 749 | }, | ||
| 750 | { | ||
| 751 | .name = "Boot Env-NAND", | ||
| 752 | |||
| 753 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | ||
| 754 | .size = 6 * (64 * 2048), | ||
| 755 | }, | ||
| 756 | { | ||
| 757 | .name = "Kernel-NAND", | ||
| 758 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | ||
| 759 | .size = 40 * (64 * 2048), | ||
| 760 | }, | ||
| 761 | { | ||
| 762 | .name = "File System - NAND", | ||
| 763 | .size = MTDPART_SIZ_FULL, | ||
| 764 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ | ||
| 765 | }, | ||
| 766 | }; | ||
| 767 | |||
| 768 | static struct flash_partitions sdp_flash_partitions[] = { | ||
| 769 | { | ||
| 770 | .parts = sdp_nor_partitions, | ||
| 771 | .nr_parts = ARRAY_SIZE(sdp_nor_partitions), | ||
| 772 | }, | ||
| 773 | { | ||
| 774 | .parts = sdp_onenand_partitions, | ||
| 775 | .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), | ||
| 776 | }, | ||
| 777 | { | ||
| 778 | .parts = sdp_nand_partitions, | ||
| 779 | .nr_parts = ARRAY_SIZE(sdp_nand_partitions), | ||
| 780 | }, | ||
| 781 | }; | ||
| 782 | |||
| 783 | static struct omap_musb_board_data musb_board_data = { | ||
| 784 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 785 | .mode = MUSB_OTG, | ||
| 786 | .power = 100, | ||
| 787 | }; | ||
| 788 | |||
| 653 | static void __init omap_3430sdp_init(void) | 789 | static void __init omap_3430sdp_init(void) |
| 654 | { | 790 | { |
| 655 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 791 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| @@ -664,8 +800,9 @@ static void __init omap_3430sdp_init(void) | |||
| 664 | ARRAY_SIZE(sdp3430_spi_board_info)); | 800 | ARRAY_SIZE(sdp3430_spi_board_info)); |
| 665 | ads7846_dev_init(); | 801 | ads7846_dev_init(); |
| 666 | omap_serial_init(); | 802 | omap_serial_init(); |
| 667 | usb_musb_init(); | 803 | usb_musb_init(&musb_board_data); |
| 668 | board_smc91x_init(); | 804 | board_smc91x_init(); |
| 805 | sdp_flash_init(sdp_flash_partitions); | ||
| 669 | sdp3430_display_init(); | 806 | sdp3430_display_init(); |
| 670 | enable_board_wakeup_source(); | 807 | enable_board_wakeup_source(); |
| 671 | usb_ehci_init(&ehci_pdata); | 808 | usb_ehci_init(&ehci_pdata); |
| @@ -674,7 +811,7 @@ static void __init omap_3430sdp_init(void) | |||
| 674 | static void __init omap_3430sdp_map_io(void) | 811 | static void __init omap_3430sdp_map_io(void) |
| 675 | { | 812 | { |
| 676 | omap2_set_globals_343x(); | 813 | omap2_set_globals_343x(); |
| 677 | omap2_map_common_io(); | 814 | omap34xx_map_common_io(); |
| 678 | } | 815 | } |
| 679 | 816 | ||
| 680 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") | 817 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") |
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 739059632811..4386d2b4a785 100755 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c | |||
| @@ -68,8 +68,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 68 | 68 | ||
| 69 | static void __init omap_sdp_map_io(void) | 69 | static void __init omap_sdp_map_io(void) |
| 70 | { | 70 | { |
| 71 | omap2_set_globals_343x(); | 71 | omap2_set_globals_36xx(); |
| 72 | omap2_map_common_io(); | 72 | omap34xx_map_common_io(); |
| 73 | } | 73 | } |
| 74 | 74 | ||
| 75 | static struct omap_board_config_kernel sdp_config[] __initdata = { | 75 | static struct omap_board_config_kernel sdp_config[] __initdata = { |
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 8ba8fb5b2514..180ac112e527 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | #include <linux/usb/otg.h> | ||
| 20 | 21 | ||
| 21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 22 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| @@ -27,6 +28,7 @@ | |||
| 27 | #include <plat/common.h> | 28 | #include <plat/common.h> |
| 28 | #include <plat/control.h> | 29 | #include <plat/control.h> |
| 29 | #include <plat/timer-gp.h> | 30 | #include <plat/timer-gp.h> |
| 31 | #include <plat/usb.h> | ||
| 30 | #include <asm/hardware/gic.h> | 32 | #include <asm/hardware/gic.h> |
| 31 | #include <asm/hardware/cache-l2x0.h> | 33 | #include <asm/hardware/cache-l2x0.h> |
| 32 | 34 | ||
| @@ -39,10 +41,6 @@ static struct platform_device *sdp4430_devices[] __initdata = { | |||
| 39 | &sdp4430_lcd_device, | 41 | &sdp4430_lcd_device, |
| 40 | }; | 42 | }; |
| 41 | 43 | ||
| 42 | static struct omap_uart_config sdp4430_uart_config __initdata = { | ||
| 43 | .enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), | ||
| 44 | }; | ||
| 45 | |||
| 46 | static struct omap_lcd_config sdp4430_lcd_config __initdata = { | 44 | static struct omap_lcd_config sdp4430_lcd_config __initdata = { |
| 47 | .ctrl_name = "internal", | 45 | .ctrl_name = "internal", |
| 48 | }; | 46 | }; |
| @@ -131,17 +129,27 @@ static void __init omap_4430sdp_init_irq(void) | |||
| 131 | omap_gpio_init(); | 129 | omap_gpio_init(); |
| 132 | } | 130 | } |
| 133 | 131 | ||
| 132 | static struct omap_musb_board_data musb_board_data = { | ||
| 133 | .interface_type = MUSB_INTERFACE_UTMI, | ||
| 134 | .mode = MUSB_PERIPHERAL, | ||
| 135 | .power = 100, | ||
| 136 | }; | ||
| 134 | 137 | ||
| 135 | static void __init omap_4430sdp_init(void) | 138 | static void __init omap_4430sdp_init(void) |
| 136 | { | 139 | { |
| 137 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); | 140 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); |
| 138 | omap_serial_init(); | 141 | omap_serial_init(); |
| 142 | /* OMAP4 SDP uses internal transceiver so register nop transceiver */ | ||
| 143 | usb_nop_xceiv_register(); | ||
| 144 | /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ | ||
| 145 | if (!cpu_is_omap44xx()) | ||
| 146 | usb_musb_init(&musb_board_data); | ||
| 139 | } | 147 | } |
| 140 | 148 | ||
| 141 | static void __init omap_4430sdp_map_io(void) | 149 | static void __init omap_4430sdp_map_io(void) |
| 142 | { | 150 | { |
| 143 | omap2_set_globals_443x(); | 151 | omap2_set_globals_443x(); |
| 144 | omap2_map_common_io(); | 152 | omap44xx_map_common_io(); |
| 145 | } | 153 | } |
| 146 | 154 | ||
| 147 | MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") | 155 | MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") |
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index b4e6eca0e8a9..70c18614773c 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
| @@ -20,8 +20,10 @@ | |||
| 20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 23 | #include <linux/i2c/pca953x.h> | ||
| 23 | 24 | ||
| 24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <mach/am35xx.h> | ||
| 25 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 26 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| @@ -29,9 +31,228 @@ | |||
| 29 | #include <plat/board.h> | 31 | #include <plat/board.h> |
| 30 | #include <plat/common.h> | 32 | #include <plat/common.h> |
| 31 | #include <plat/usb.h> | 33 | #include <plat/usb.h> |
| 34 | #include <plat/display.h> | ||
| 32 | 35 | ||
| 33 | #include "mux.h" | 36 | #include "mux.h" |
| 34 | 37 | ||
| 38 | #define LCD_PANEL_PWR 176 | ||
| 39 | #define LCD_PANEL_BKLIGHT_PWR 182 | ||
| 40 | #define LCD_PANEL_PWM 181 | ||
| 41 | |||
| 42 | static struct i2c_board_info __initdata am3517evm_i2c_boardinfo[] = { | ||
| 43 | { | ||
| 44 | I2C_BOARD_INFO("s35390a", 0x30), | ||
| 45 | .type = "s35390a", | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* | ||
| 50 | * RTC - S35390A | ||
| 51 | */ | ||
| 52 | #define GPIO_RTCS35390A_IRQ 55 | ||
| 53 | |||
| 54 | static void __init am3517_evm_rtc_init(void) | ||
| 55 | { | ||
| 56 | int r; | ||
| 57 | |||
| 58 | omap_mux_init_gpio(GPIO_RTCS35390A_IRQ, OMAP_PIN_INPUT_PULLUP); | ||
| 59 | r = gpio_request(GPIO_RTCS35390A_IRQ, "rtcs35390a-irq"); | ||
| 60 | if (r < 0) { | ||
| 61 | printk(KERN_WARNING "failed to request GPIO#%d\n", | ||
| 62 | GPIO_RTCS35390A_IRQ); | ||
| 63 | return; | ||
| 64 | } | ||
| 65 | r = gpio_direction_input(GPIO_RTCS35390A_IRQ); | ||
| 66 | if (r < 0) { | ||
| 67 | printk(KERN_WARNING "GPIO#%d cannot be configured as input\n", | ||
| 68 | GPIO_RTCS35390A_IRQ); | ||
| 69 | gpio_free(GPIO_RTCS35390A_IRQ); | ||
| 70 | return; | ||
| 71 | } | ||
| 72 | am3517evm_i2c_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ); | ||
| 73 | } | ||
| 74 | |||
| 75 | /* | ||
| 76 | * I2C GPIO Expander - TCA6416 | ||
| 77 | */ | ||
| 78 | |||
| 79 | /* Mounted on Base-Board */ | ||
| 80 | static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = { | ||
| 81 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 82 | }; | ||
| 83 | static struct i2c_board_info __initdata am3517evm_tca6416_info_0[] = { | ||
| 84 | { | ||
| 85 | I2C_BOARD_INFO("tca6416", 0x21), | ||
| 86 | .platform_data = &am3517evm_gpio_expander_info_0, | ||
| 87 | }, | ||
| 88 | }; | ||
| 89 | |||
| 90 | /* Mounted on UI Card */ | ||
| 91 | static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_1 = { | ||
| 92 | .gpio_base = OMAP_MAX_GPIO_LINES + 16, | ||
| 93 | }; | ||
| 94 | static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_2 = { | ||
| 95 | .gpio_base = OMAP_MAX_GPIO_LINES + 32, | ||
| 96 | }; | ||
| 97 | static struct i2c_board_info __initdata am3517evm_ui_tca6416_info[] = { | ||
| 98 | { | ||
| 99 | I2C_BOARD_INFO("tca6416", 0x20), | ||
| 100 | .platform_data = &am3517evm_ui_gpio_expander_info_1, | ||
| 101 | }, | ||
| 102 | { | ||
| 103 | I2C_BOARD_INFO("tca6416", 0x21), | ||
| 104 | .platform_data = &am3517evm_ui_gpio_expander_info_2, | ||
| 105 | }, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static int __init am3517_evm_i2c_init(void) | ||
| 109 | { | ||
| 110 | omap_register_i2c_bus(1, 400, NULL, 0); | ||
| 111 | omap_register_i2c_bus(2, 400, am3517evm_tca6416_info_0, | ||
| 112 | ARRAY_SIZE(am3517evm_tca6416_info_0)); | ||
| 113 | omap_register_i2c_bus(3, 400, am3517evm_ui_tca6416_info, | ||
| 114 | ARRAY_SIZE(am3517evm_ui_tca6416_info)); | ||
| 115 | |||
| 116 | return 0; | ||
| 117 | } | ||
| 118 | |||
| 119 | static int lcd_enabled; | ||
| 120 | static int dvi_enabled; | ||
| 121 | |||
| 122 | static void __init am3517_evm_display_init(void) | ||
| 123 | { | ||
| 124 | int r; | ||
| 125 | |||
| 126 | omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP); | ||
| 127 | omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN); | ||
| 128 | omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN); | ||
| 129 | /* | ||
| 130 | * Enable GPIO 182 = LCD Backlight Power | ||
| 131 | */ | ||
| 132 | r = gpio_request(LCD_PANEL_BKLIGHT_PWR, "lcd_backlight_pwr"); | ||
| 133 | if (r) { | ||
| 134 | printk(KERN_ERR "failed to get lcd_backlight_pwr\n"); | ||
| 135 | return; | ||
| 136 | } | ||
| 137 | gpio_direction_output(LCD_PANEL_BKLIGHT_PWR, 1); | ||
| 138 | /* | ||
| 139 | * Enable GPIO 181 = LCD Panel PWM | ||
| 140 | */ | ||
| 141 | r = gpio_request(LCD_PANEL_PWM, "lcd_pwm"); | ||
| 142 | if (r) { | ||
| 143 | printk(KERN_ERR "failed to get lcd_pwm\n"); | ||
| 144 | goto err_1; | ||
| 145 | } | ||
| 146 | gpio_direction_output(LCD_PANEL_PWM, 1); | ||
| 147 | /* | ||
| 148 | * Enable GPIO 176 = LCD Panel Power enable pin | ||
| 149 | */ | ||
| 150 | r = gpio_request(LCD_PANEL_PWR, "lcd_panel_pwr"); | ||
| 151 | if (r) { | ||
| 152 | printk(KERN_ERR "failed to get lcd_panel_pwr\n"); | ||
| 153 | goto err_2; | ||
| 154 | } | ||
| 155 | gpio_direction_output(LCD_PANEL_PWR, 1); | ||
| 156 | |||
| 157 | printk(KERN_INFO "Display initialized successfully\n"); | ||
| 158 | return; | ||
| 159 | |||
| 160 | err_2: | ||
| 161 | gpio_free(LCD_PANEL_PWM); | ||
| 162 | err_1: | ||
| 163 | gpio_free(LCD_PANEL_BKLIGHT_PWR); | ||
| 164 | } | ||
| 165 | |||
| 166 | static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 167 | { | ||
| 168 | if (dvi_enabled) { | ||
| 169 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | ||
| 170 | return -EINVAL; | ||
| 171 | } | ||
| 172 | gpio_set_value(LCD_PANEL_PWR, 1); | ||
| 173 | lcd_enabled = 1; | ||
| 174 | |||
| 175 | return 0; | ||
| 176 | } | ||
| 177 | |||
| 178 | static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 179 | { | ||
| 180 | gpio_set_value(LCD_PANEL_PWR, 0); | ||
| 181 | lcd_enabled = 0; | ||
| 182 | } | ||
| 183 | |||
| 184 | static struct omap_dss_device am3517_evm_lcd_device = { | ||
| 185 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 186 | .name = "lcd", | ||
| 187 | .driver_name = "sharp_lq_panel", | ||
| 188 | .phy.dpi.data_lines = 16, | ||
| 189 | .platform_enable = am3517_evm_panel_enable_lcd, | ||
| 190 | .platform_disable = am3517_evm_panel_disable_lcd, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev) | ||
| 194 | { | ||
| 195 | return 0; | ||
| 196 | } | ||
| 197 | |||
| 198 | static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 199 | { | ||
| 200 | } | ||
| 201 | |||
| 202 | static struct omap_dss_device am3517_evm_tv_device = { | ||
| 203 | .type = OMAP_DISPLAY_TYPE_VENC, | ||
| 204 | .name = "tv", | ||
| 205 | .driver_name = "venc", | ||
| 206 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | ||
| 207 | .platform_enable = am3517_evm_panel_enable_tv, | ||
| 208 | .platform_disable = am3517_evm_panel_disable_tv, | ||
| 209 | }; | ||
| 210 | |||
| 211 | static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev) | ||
| 212 | { | ||
| 213 | if (lcd_enabled) { | ||
| 214 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | ||
| 215 | return -EINVAL; | ||
| 216 | } | ||
| 217 | dvi_enabled = 1; | ||
| 218 | |||
| 219 | return 0; | ||
| 220 | } | ||
| 221 | |||
| 222 | static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev) | ||
| 223 | { | ||
| 224 | dvi_enabled = 0; | ||
| 225 | } | ||
| 226 | |||
| 227 | static struct omap_dss_device am3517_evm_dvi_device = { | ||
| 228 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 229 | .name = "dvi", | ||
| 230 | .driver_name = "generic_panel", | ||
| 231 | .phy.dpi.data_lines = 24, | ||
| 232 | .platform_enable = am3517_evm_panel_enable_dvi, | ||
| 233 | .platform_disable = am3517_evm_panel_disable_dvi, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct omap_dss_device *am3517_evm_dss_devices[] = { | ||
| 237 | &am3517_evm_lcd_device, | ||
| 238 | &am3517_evm_tv_device, | ||
| 239 | &am3517_evm_dvi_device, | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct omap_dss_board_info am3517_evm_dss_data = { | ||
| 243 | .num_devices = ARRAY_SIZE(am3517_evm_dss_devices), | ||
| 244 | .devices = am3517_evm_dss_devices, | ||
| 245 | .default_device = &am3517_evm_lcd_device, | ||
| 246 | }; | ||
| 247 | |||
| 248 | struct platform_device am3517_evm_dss_device = { | ||
| 249 | .name = "omapdss", | ||
| 250 | .id = -1, | ||
| 251 | .dev = { | ||
| 252 | .platform_data = &am3517_evm_dss_data, | ||
| 253 | }, | ||
| 254 | }; | ||
| 255 | |||
| 35 | /* | 256 | /* |
| 36 | * Board initialization | 257 | * Board initialization |
| 37 | */ | 258 | */ |
| @@ -39,6 +260,7 @@ static struct omap_board_config_kernel am3517_evm_config[] __initdata = { | |||
| 39 | }; | 260 | }; |
| 40 | 261 | ||
| 41 | static struct platform_device *am3517_evm_devices[] __initdata = { | 262 | static struct platform_device *am3517_evm_devices[] __initdata = { |
| 263 | &am3517_evm_dss_device, | ||
| 42 | }; | 264 | }; |
| 43 | 265 | ||
| 44 | static void __init am3517_evm_init_irq(void) | 266 | static void __init am3517_evm_init_irq(void) |
| @@ -72,18 +294,31 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 72 | 294 | ||
| 73 | static void __init am3517_evm_init(void) | 295 | static void __init am3517_evm_init(void) |
| 74 | { | 296 | { |
| 297 | am3517_evm_i2c_init(); | ||
| 298 | |||
| 75 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 299 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 76 | platform_add_devices(am3517_evm_devices, | 300 | platform_add_devices(am3517_evm_devices, |
| 77 | ARRAY_SIZE(am3517_evm_devices)); | 301 | ARRAY_SIZE(am3517_evm_devices)); |
| 78 | 302 | ||
| 79 | omap_serial_init(); | 303 | omap_serial_init(); |
| 304 | |||
| 305 | /* Configure GPIO for EHCI port */ | ||
| 306 | omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); | ||
| 80 | usb_ehci_init(&ehci_pdata); | 307 | usb_ehci_init(&ehci_pdata); |
| 308 | /* DSS */ | ||
| 309 | am3517_evm_display_init(); | ||
| 310 | |||
| 311 | /* RTC - S35390A */ | ||
| 312 | am3517_evm_rtc_init(); | ||
| 313 | |||
| 314 | i2c_register_board_info(1, am3517evm_i2c_boardinfo, | ||
| 315 | ARRAY_SIZE(am3517evm_i2c_boardinfo)); | ||
| 81 | } | 316 | } |
| 82 | 317 | ||
| 83 | static void __init am3517_evm_map_io(void) | 318 | static void __init am3517_evm_map_io(void) |
| 84 | { | 319 | { |
| 85 | omap2_set_globals_343x(); | 320 | omap2_set_globals_343x(); |
| 86 | omap2_map_common_io(); | 321 | omap34xx_map_common_io(); |
| 87 | } | 322 | } |
| 88 | 323 | ||
| 89 | MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") | 324 | MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index fbbd68d69cc8..aa69fb999748 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -337,7 +337,7 @@ static void __init omap_apollon_init(void) | |||
| 337 | static void __init omap_apollon_map_io(void) | 337 | static void __init omap_apollon_map_io(void) |
| 338 | { | 338 | { |
| 339 | omap2_set_globals_242x(); | 339 | omap2_set_globals_242x(); |
| 340 | omap2_map_common_io(); | 340 | omap242x_map_common_io(); |
| 341 | } | 341 | } |
| 342 | 342 | ||
| 343 | MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") | 343 | MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") |
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 2626a9f8a73a..afa77caaff4d 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
| @@ -32,6 +32,9 @@ | |||
| 32 | #include <linux/i2c/twl.h> | 32 | #include <linux/i2c/twl.h> |
| 33 | #include <linux/regulator/machine.h> | 33 | #include <linux/regulator/machine.h> |
| 34 | 34 | ||
| 35 | #include <linux/spi/spi.h> | ||
| 36 | #include <linux/spi/tdo24m.h> | ||
| 37 | |||
| 35 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
| 36 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| 37 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
| @@ -41,12 +44,13 @@ | |||
| 41 | #include <plat/nand.h> | 44 | #include <plat/nand.h> |
| 42 | #include <plat/gpmc.h> | 45 | #include <plat/gpmc.h> |
| 43 | #include <plat/usb.h> | 46 | #include <plat/usb.h> |
| 47 | #include <plat/display.h> | ||
| 44 | 48 | ||
| 45 | #include <mach/hardware.h> | 49 | #include <mach/hardware.h> |
| 46 | 50 | ||
| 47 | #include "mux.h" | 51 | #include "mux.h" |
| 48 | #include "sdram-micron-mt46h32m32lf-6.h" | 52 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 49 | #include "mmc-twl4030.h" | 53 | #include "hsmmc.h" |
| 50 | 54 | ||
| 51 | #define CM_T35_GPIO_PENDOWN 57 | 55 | #define CM_T35_GPIO_PENDOWN 57 |
| 52 | 56 | ||
| @@ -248,7 +252,6 @@ static inline void cm_t35_init_nand(void) {} | |||
| 248 | 252 | ||
| 249 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ | 253 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ |
| 250 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | 254 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) |
| 251 | #include <linux/spi/spi.h> | ||
| 252 | #include <linux/spi/ads7846.h> | 255 | #include <linux/spi/ads7846.h> |
| 253 | 256 | ||
| 254 | #include <plat/mcspi.h> | 257 | #include <plat/mcspi.h> |
| @@ -304,6 +307,193 @@ static void __init cm_t35_init_ads7846(void) | |||
| 304 | static inline void cm_t35_init_ads7846(void) {} | 307 | static inline void cm_t35_init_ads7846(void) {} |
| 305 | #endif | 308 | #endif |
| 306 | 309 | ||
| 310 | #define CM_T35_LCD_EN_GPIO 157 | ||
| 311 | #define CM_T35_LCD_BL_GPIO 58 | ||
| 312 | #define CM_T35_DVI_EN_GPIO 54 | ||
| 313 | |||
| 314 | static int lcd_bl_gpio; | ||
| 315 | static int lcd_en_gpio; | ||
| 316 | static int dvi_en_gpio; | ||
| 317 | |||
| 318 | static int lcd_enabled; | ||
| 319 | static int dvi_enabled; | ||
| 320 | |||
| 321 | static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 322 | { | ||
| 323 | if (dvi_enabled) { | ||
| 324 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | ||
| 325 | return -EINVAL; | ||
| 326 | } | ||
| 327 | |||
| 328 | gpio_set_value(lcd_en_gpio, 1); | ||
| 329 | gpio_set_value(lcd_bl_gpio, 1); | ||
| 330 | |||
| 331 | lcd_enabled = 1; | ||
| 332 | |||
| 333 | return 0; | ||
| 334 | } | ||
| 335 | |||
| 336 | static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 337 | { | ||
| 338 | lcd_enabled = 0; | ||
| 339 | |||
| 340 | gpio_set_value(lcd_bl_gpio, 0); | ||
| 341 | gpio_set_value(lcd_en_gpio, 0); | ||
| 342 | } | ||
| 343 | |||
| 344 | static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) | ||
| 345 | { | ||
| 346 | if (lcd_enabled) { | ||
| 347 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | ||
| 348 | return -EINVAL; | ||
| 349 | } | ||
| 350 | |||
| 351 | gpio_set_value(dvi_en_gpio, 0); | ||
| 352 | dvi_enabled = 1; | ||
| 353 | |||
| 354 | return 0; | ||
| 355 | } | ||
| 356 | |||
| 357 | static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) | ||
| 358 | { | ||
| 359 | gpio_set_value(dvi_en_gpio, 1); | ||
| 360 | dvi_enabled = 0; | ||
| 361 | } | ||
| 362 | |||
| 363 | static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) | ||
| 364 | { | ||
| 365 | return 0; | ||
| 366 | } | ||
| 367 | |||
| 368 | static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 369 | { | ||
| 370 | } | ||
| 371 | |||
| 372 | static struct omap_dss_device cm_t35_lcd_device = { | ||
| 373 | .name = "lcd", | ||
| 374 | .driver_name = "toppoly_tdo35s_panel", | ||
| 375 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 376 | .phy.dpi.data_lines = 18, | ||
| 377 | .platform_enable = cm_t35_panel_enable_lcd, | ||
| 378 | .platform_disable = cm_t35_panel_disable_lcd, | ||
| 379 | }; | ||
| 380 | |||
| 381 | static struct omap_dss_device cm_t35_dvi_device = { | ||
| 382 | .name = "dvi", | ||
| 383 | .driver_name = "generic_panel", | ||
| 384 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 385 | .phy.dpi.data_lines = 24, | ||
| 386 | .platform_enable = cm_t35_panel_enable_dvi, | ||
| 387 | .platform_disable = cm_t35_panel_disable_dvi, | ||
| 388 | }; | ||
| 389 | |||
| 390 | static struct omap_dss_device cm_t35_tv_device = { | ||
| 391 | .name = "tv", | ||
| 392 | .driver_name = "venc", | ||
| 393 | .type = OMAP_DISPLAY_TYPE_VENC, | ||
| 394 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | ||
| 395 | .platform_enable = cm_t35_panel_enable_tv, | ||
| 396 | .platform_disable = cm_t35_panel_disable_tv, | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct omap_dss_device *cm_t35_dss_devices[] = { | ||
| 400 | &cm_t35_lcd_device, | ||
| 401 | &cm_t35_dvi_device, | ||
| 402 | &cm_t35_tv_device, | ||
| 403 | }; | ||
| 404 | |||
| 405 | static struct omap_dss_board_info cm_t35_dss_data = { | ||
| 406 | .num_devices = ARRAY_SIZE(cm_t35_dss_devices), | ||
| 407 | .devices = cm_t35_dss_devices, | ||
| 408 | .default_device = &cm_t35_dvi_device, | ||
| 409 | }; | ||
| 410 | |||
| 411 | static struct platform_device cm_t35_dss_device = { | ||
| 412 | .name = "omapdss", | ||
| 413 | .id = -1, | ||
| 414 | .dev = { | ||
| 415 | .platform_data = &cm_t35_dss_data, | ||
| 416 | }, | ||
| 417 | }; | ||
| 418 | |||
| 419 | static struct omap2_mcspi_device_config tdo24m_mcspi_config = { | ||
| 420 | .turbo_mode = 0, | ||
| 421 | .single_channel = 1, /* 0: slave, 1: master */ | ||
| 422 | }; | ||
| 423 | |||
| 424 | static struct tdo24m_platform_data tdo24m_config = { | ||
| 425 | .model = TDO35S, | ||
| 426 | }; | ||
| 427 | |||
| 428 | static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { | ||
| 429 | { | ||
| 430 | .modalias = "tdo24m", | ||
| 431 | .bus_num = 4, | ||
| 432 | .chip_select = 0, | ||
| 433 | .max_speed_hz = 1000000, | ||
| 434 | .controller_data = &tdo24m_mcspi_config, | ||
| 435 | .platform_data = &tdo24m_config, | ||
| 436 | }, | ||
| 437 | }; | ||
| 438 | |||
| 439 | static void __init cm_t35_init_display(void) | ||
| 440 | { | ||
| 441 | int err; | ||
| 442 | |||
| 443 | lcd_en_gpio = CM_T35_LCD_EN_GPIO; | ||
| 444 | lcd_bl_gpio = CM_T35_LCD_BL_GPIO; | ||
| 445 | dvi_en_gpio = CM_T35_DVI_EN_GPIO; | ||
| 446 | |||
| 447 | spi_register_board_info(cm_t35_lcd_spi_board_info, | ||
| 448 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); | ||
| 449 | |||
| 450 | err = gpio_request(lcd_en_gpio, "LCD RST"); | ||
| 451 | if (err) { | ||
| 452 | pr_err("CM-T35: failed to get LCD reset GPIO\n"); | ||
| 453 | goto out; | ||
| 454 | } | ||
| 455 | |||
| 456 | err = gpio_request(lcd_bl_gpio, "LCD BL"); | ||
| 457 | if (err) { | ||
| 458 | pr_err("CM-T35: failed to get LCD backlight control GPIO\n"); | ||
| 459 | goto err_lcd_bl; | ||
| 460 | } | ||
| 461 | |||
| 462 | err = gpio_request(dvi_en_gpio, "DVI EN"); | ||
| 463 | if (err) { | ||
| 464 | pr_err("CM-T35: failed to get DVI reset GPIO\n"); | ||
| 465 | goto err_dvi_en; | ||
| 466 | } | ||
| 467 | |||
| 468 | gpio_export(lcd_en_gpio, 0); | ||
| 469 | gpio_export(lcd_bl_gpio, 0); | ||
| 470 | gpio_export(dvi_en_gpio, 0); | ||
| 471 | gpio_direction_output(lcd_en_gpio, 0); | ||
| 472 | gpio_direction_output(lcd_bl_gpio, 0); | ||
| 473 | gpio_direction_output(dvi_en_gpio, 1); | ||
| 474 | |||
| 475 | msleep(50); | ||
| 476 | gpio_set_value(lcd_en_gpio, 1); | ||
| 477 | |||
| 478 | err = platform_device_register(&cm_t35_dss_device); | ||
| 479 | if (err) { | ||
| 480 | pr_err("CM-T35: failed to register DSS device\n"); | ||
| 481 | goto err_dev_reg; | ||
| 482 | } | ||
| 483 | |||
| 484 | return; | ||
| 485 | |||
| 486 | err_dev_reg: | ||
| 487 | gpio_free(dvi_en_gpio); | ||
| 488 | err_dvi_en: | ||
| 489 | gpio_free(lcd_bl_gpio); | ||
| 490 | err_lcd_bl: | ||
| 491 | gpio_free(lcd_en_gpio); | ||
| 492 | out: | ||
| 493 | |||
| 494 | return; | ||
| 495 | } | ||
| 496 | |||
| 307 | static struct regulator_consumer_supply cm_t35_vmmc1_supply = { | 497 | static struct regulator_consumer_supply cm_t35_vmmc1_supply = { |
| 308 | .supply = "vmmc", | 498 | .supply = "vmmc", |
| 309 | }; | 499 | }; |
| @@ -312,6 +502,16 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = { | |||
| 312 | .supply = "vmmc_aux", | 502 | .supply = "vmmc_aux", |
| 313 | }; | 503 | }; |
| 314 | 504 | ||
| 505 | static struct regulator_consumer_supply cm_t35_vdac_supply = { | ||
| 506 | .supply = "vdda_dac", | ||
| 507 | .dev = &cm_t35_dss_device.dev, | ||
| 508 | }; | ||
| 509 | |||
| 510 | static struct regulator_consumer_supply cm_t35_vdvi_supply = { | ||
| 511 | .supply = "vdvi", | ||
| 512 | .dev = &cm_t35_dss_device.dev, | ||
| 513 | }; | ||
| 514 | |||
| 315 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ | 515 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
| 316 | static struct regulator_init_data cm_t35_vmmc1 = { | 516 | static struct regulator_init_data cm_t35_vmmc1 = { |
| 317 | .constraints = { | 517 | .constraints = { |
| @@ -342,6 +542,35 @@ static struct regulator_init_data cm_t35_vsim = { | |||
| 342 | .consumer_supplies = &cm_t35_vsim_supply, | 542 | .consumer_supplies = &cm_t35_vsim_supply, |
| 343 | }; | 543 | }; |
| 344 | 544 | ||
| 545 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ | ||
| 546 | static struct regulator_init_data cm_t35_vdac = { | ||
| 547 | .constraints = { | ||
| 548 | .min_uV = 1800000, | ||
| 549 | .max_uV = 1800000, | ||
| 550 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 551 | | REGULATOR_MODE_STANDBY, | ||
| 552 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 553 | | REGULATOR_CHANGE_STATUS, | ||
| 554 | }, | ||
| 555 | .num_consumer_supplies = 1, | ||
| 556 | .consumer_supplies = &cm_t35_vdac_supply, | ||
| 557 | }; | ||
| 558 | |||
| 559 | /* VPLL2 for digital video outputs */ | ||
| 560 | static struct regulator_init_data cm_t35_vpll2 = { | ||
| 561 | .constraints = { | ||
| 562 | .name = "VDVI", | ||
| 563 | .min_uV = 1800000, | ||
| 564 | .max_uV = 1800000, | ||
| 565 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 566 | | REGULATOR_MODE_STANDBY, | ||
| 567 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 568 | | REGULATOR_CHANGE_STATUS, | ||
| 569 | }, | ||
| 570 | .num_consumer_supplies = 1, | ||
| 571 | .consumer_supplies = &cm_t35_vdvi_supply, | ||
| 572 | }; | ||
| 573 | |||
| 345 | static struct twl4030_usb_data cm_t35_usb_data = { | 574 | static struct twl4030_usb_data cm_t35_usb_data = { |
| 346 | .usb_mode = T2_USB_MODE_ULPI, | 575 | .usb_mode = T2_USB_MODE_ULPI, |
| 347 | }; | 576 | }; |
| @@ -364,7 +593,7 @@ static struct twl4030_keypad_data cm_t35_kp_data = { | |||
| 364 | .rep = 1, | 593 | .rep = 1, |
| 365 | }; | 594 | }; |
| 366 | 595 | ||
| 367 | static struct twl4030_hsmmc_info mmc[] = { | 596 | static struct omap2_hsmmc_info mmc[] = { |
| 368 | { | 597 | { |
| 369 | .mmc = 1, | 598 | .mmc = 1, |
| 370 | .wires = 4, | 599 | .wires = 4, |
| @@ -413,7 +642,7 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, | |||
| 413 | 642 | ||
| 414 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 643 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 415 | mmc[0].gpio_cd = gpio + 0; | 644 | mmc[0].gpio_cd = gpio + 0; |
| 416 | twl4030_mmc_init(mmc); | 645 | omap2_hsmmc_init(mmc); |
| 417 | 646 | ||
| 418 | /* link regulators to MMC adapters */ | 647 | /* link regulators to MMC adapters */ |
| 419 | cm_t35_vmmc1_supply.dev = mmc[0].dev; | 648 | cm_t35_vmmc1_supply.dev = mmc[0].dev; |
| @@ -445,6 +674,8 @@ static struct twl4030_platform_data cm_t35_twldata = { | |||
| 445 | .gpio = &cm_t35_gpio_data, | 674 | .gpio = &cm_t35_gpio_data, |
| 446 | .vmmc1 = &cm_t35_vmmc1, | 675 | .vmmc1 = &cm_t35_vmmc1, |
| 447 | .vsim = &cm_t35_vsim, | 676 | .vsim = &cm_t35_vsim, |
| 677 | .vdac = &cm_t35_vdac, | ||
| 678 | .vpll2 = &cm_t35_vpll2, | ||
| 448 | }; | 679 | }; |
| 449 | 680 | ||
| 450 | static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = { | 681 | static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = { |
| @@ -479,7 +710,7 @@ static void __init cm_t35_init_irq(void) | |||
| 479 | static void __init cm_t35_map_io(void) | 710 | static void __init cm_t35_map_io(void) |
| 480 | { | 711 | { |
| 481 | omap2_set_globals_343x(); | 712 | omap2_set_globals_343x(); |
| 482 | omap2_map_common_io(); | 713 | omap34xx_map_common_io(); |
| 483 | } | 714 | } |
| 484 | 715 | ||
| 485 | static struct omap_board_mux board_mux[] __initdata = { | 716 | static struct omap_board_mux board_mux[] __initdata = { |
| @@ -568,6 +799,11 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 568 | OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | 799 | OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), |
| 569 | OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | 800 | OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), |
| 570 | 801 | ||
| 802 | /* display controls */ | ||
| 803 | OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 804 | OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 805 | OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 806 | |||
| 571 | /* TPS IRQ */ | 807 | /* TPS IRQ */ |
| 572 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ | 808 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ |
| 573 | OMAP_PIN_INPUT_PULLUP), | 809 | OMAP_PIN_INPUT_PULLUP), |
| @@ -575,6 +811,12 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 575 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 811 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 576 | }; | 812 | }; |
| 577 | 813 | ||
| 814 | static struct omap_musb_board_data musb_board_data = { | ||
| 815 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 816 | .mode = MUSB_OTG, | ||
| 817 | .power = 100, | ||
| 818 | }; | ||
| 819 | |||
| 578 | static void __init cm_t35_init(void) | 820 | static void __init cm_t35_init(void) |
| 579 | { | 821 | { |
| 580 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); | 822 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
| @@ -584,8 +826,9 @@ static void __init cm_t35_init(void) | |||
| 584 | cm_t35_init_ads7846(); | 826 | cm_t35_init_ads7846(); |
| 585 | cm_t35_init_ethernet(); | 827 | cm_t35_init_ethernet(); |
| 586 | cm_t35_init_led(); | 828 | cm_t35_init_led(); |
| 829 | cm_t35_init_display(); | ||
| 587 | 830 | ||
| 588 | usb_musb_init(); | 831 | usb_musb_init(&musb_board_data); |
| 589 | } | 832 | } |
| 590 | 833 | ||
| 591 | MACHINE_START(CM_T35, "Compulab CM-T35") | 834 | MACHINE_START(CM_T35, "Compulab CM-T35") |
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c new file mode 100644 index 000000000000..371019054b49 --- /dev/null +++ b/arch/arm/mach-omap2/board-devkit8000.c | |||
| @@ -0,0 +1,697 @@ | |||
| 1 | /* | ||
| 2 | * board-devkit8000.c - TimLL Devkit8000 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Kim Botherway | ||
| 5 | * Copyright (C) 2010 Thomas Weber | ||
| 6 | * | ||
| 7 | * Modified from mach-omap2/board-omap3beagle.c | ||
| 8 | * | ||
| 9 | * Initial code: Syed Mohammed Khasim | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <linux/delay.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/leds.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/input.h> | ||
| 26 | #include <linux/gpio_keys.h> | ||
| 27 | |||
| 28 | #include <linux/mtd/mtd.h> | ||
| 29 | #include <linux/mtd/partitions.h> | ||
| 30 | #include <linux/mtd/nand.h> | ||
| 31 | |||
| 32 | #include <linux/regulator/machine.h> | ||
| 33 | #include <linux/i2c/twl.h> | ||
| 34 | |||
| 35 | #include <mach/hardware.h> | ||
| 36 | #include <asm/mach-types.h> | ||
| 37 | #include <asm/mach/arch.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/flash.h> | ||
| 40 | |||
| 41 | #include <plat/board.h> | ||
| 42 | #include <plat/common.h> | ||
| 43 | #include <plat/gpmc.h> | ||
| 44 | #include <plat/nand.h> | ||
| 45 | #include <plat/usb.h> | ||
| 46 | #include <plat/timer-gp.h> | ||
| 47 | #include <plat/display.h> | ||
| 48 | |||
| 49 | #include <plat/mcspi.h> | ||
| 50 | #include <linux/input/matrix_keypad.h> | ||
| 51 | #include <linux/spi/spi.h> | ||
| 52 | #include <linux/spi/ads7846.h> | ||
| 53 | #include <linux/usb/otg.h> | ||
| 54 | #include <linux/dm9000.h> | ||
| 55 | #include <linux/interrupt.h> | ||
| 56 | |||
| 57 | #include "sdram-micron-mt46h32m32lf-6.h" | ||
| 58 | |||
| 59 | #include "mux.h" | ||
| 60 | #include "hsmmc.h" | ||
| 61 | |||
| 62 | #define GPMC_CS0_BASE 0x60 | ||
| 63 | #define GPMC_CS_SIZE 0x30 | ||
| 64 | |||
| 65 | #define NAND_BLOCK_SIZE SZ_128K | ||
| 66 | |||
| 67 | #define OMAP_DM9000_GPIO_IRQ 25 | ||
| 68 | #define OMAP3_DEVKIT_TS_GPIO 27 | ||
| 69 | |||
| 70 | static struct mtd_partition devkit8000_nand_partitions[] = { | ||
| 71 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 72 | { | ||
| 73 | .name = "X-Loader", | ||
| 74 | .offset = 0, | ||
| 75 | .size = 4 * NAND_BLOCK_SIZE, | ||
| 76 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 77 | }, | ||
| 78 | { | ||
| 79 | .name = "U-Boot", | ||
| 80 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 81 | .size = 15 * NAND_BLOCK_SIZE, | ||
| 82 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 83 | }, | ||
| 84 | { | ||
| 85 | .name = "U-Boot Env", | ||
| 86 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | ||
| 87 | .size = 1 * NAND_BLOCK_SIZE, | ||
| 88 | }, | ||
| 89 | { | ||
| 90 | .name = "Kernel", | ||
| 91 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | ||
| 92 | .size = 32 * NAND_BLOCK_SIZE, | ||
| 93 | }, | ||
| 94 | { | ||
| 95 | .name = "File System", | ||
| 96 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ | ||
| 97 | .size = MTDPART_SIZ_FULL, | ||
| 98 | }, | ||
| 99 | }; | ||
| 100 | |||
| 101 | static struct omap_nand_platform_data devkit8000_nand_data = { | ||
| 102 | .options = NAND_BUSWIDTH_16, | ||
| 103 | .parts = devkit8000_nand_partitions, | ||
| 104 | .nr_parts = ARRAY_SIZE(devkit8000_nand_partitions), | ||
| 105 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | static struct resource devkit8000_nand_resource = { | ||
| 109 | .flags = IORESOURCE_MEM, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct platform_device devkit8000_nand_device = { | ||
| 113 | .name = "omap2-nand", | ||
| 114 | .id = -1, | ||
| 115 | .dev = { | ||
| 116 | .platform_data = &devkit8000_nand_data, | ||
| 117 | }, | ||
| 118 | .num_resources = 1, | ||
| 119 | .resource = &devkit8000_nand_resource, | ||
| 120 | }; | ||
| 121 | |||
| 122 | static struct omap2_hsmmc_info mmc[] = { | ||
| 123 | { | ||
| 124 | .mmc = 1, | ||
| 125 | .wires = 8, | ||
| 126 | .gpio_wp = 29, | ||
| 127 | }, | ||
| 128 | {} /* Terminator */ | ||
| 129 | }; | ||
| 130 | static struct omap_board_config_kernel devkit8000_config[] __initdata = { | ||
| 131 | }; | ||
| 132 | |||
| 133 | static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) | ||
| 134 | { | ||
| 135 | twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1); | ||
| 136 | twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); | ||
| 137 | |||
| 138 | return 0; | ||
| 139 | } | ||
| 140 | |||
| 141 | static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) | ||
| 142 | { | ||
| 143 | } | ||
| 144 | static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) | ||
| 145 | { | ||
| 146 | return 0; | ||
| 147 | } | ||
| 148 | |||
| 149 | static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) | ||
| 150 | { | ||
| 151 | } | ||
| 152 | |||
| 153 | static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev) | ||
| 154 | { | ||
| 155 | |||
| 156 | return 0; | ||
| 157 | } | ||
| 158 | |||
| 159 | static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 160 | { | ||
| 161 | } | ||
| 162 | |||
| 163 | |||
| 164 | static struct regulator_consumer_supply devkit8000_vmmc1_supply = { | ||
| 165 | .supply = "vmmc", | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct regulator_consumer_supply devkit8000_vsim_supply = { | ||
| 169 | .supply = "vmmc_aux", | ||
| 170 | }; | ||
| 171 | |||
| 172 | |||
| 173 | static struct omap_dss_device devkit8000_lcd_device = { | ||
| 174 | .name = "lcd", | ||
| 175 | .driver_name = "innolux_at_panel", | ||
| 176 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 177 | .phy.dpi.data_lines = 24, | ||
| 178 | .platform_enable = devkit8000_panel_enable_lcd, | ||
| 179 | .platform_disable = devkit8000_panel_disable_lcd, | ||
| 180 | }; | ||
| 181 | static struct omap_dss_device devkit8000_dvi_device = { | ||
| 182 | .name = "dvi", | ||
| 183 | .driver_name = "generic_panel", | ||
| 184 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 185 | .phy.dpi.data_lines = 24, | ||
| 186 | .platform_enable = devkit8000_panel_enable_dvi, | ||
| 187 | .platform_disable = devkit8000_panel_disable_dvi, | ||
| 188 | }; | ||
| 189 | |||
| 190 | static struct omap_dss_device devkit8000_tv_device = { | ||
| 191 | .name = "tv", | ||
| 192 | .driver_name = "venc", | ||
| 193 | .type = OMAP_DISPLAY_TYPE_VENC, | ||
| 194 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | ||
| 195 | .platform_enable = devkit8000_panel_enable_tv, | ||
| 196 | .platform_disable = devkit8000_panel_disable_tv, | ||
| 197 | }; | ||
| 198 | |||
| 199 | |||
| 200 | static struct omap_dss_device *devkit8000_dss_devices[] = { | ||
| 201 | &devkit8000_lcd_device, | ||
| 202 | &devkit8000_dvi_device, | ||
| 203 | &devkit8000_tv_device, | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct omap_dss_board_info devkit8000_dss_data = { | ||
| 207 | .num_devices = ARRAY_SIZE(devkit8000_dss_devices), | ||
| 208 | .devices = devkit8000_dss_devices, | ||
| 209 | .default_device = &devkit8000_lcd_device, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct platform_device devkit8000_dss_device = { | ||
| 213 | .name = "omapdss", | ||
| 214 | .id = -1, | ||
| 215 | .dev = { | ||
| 216 | .platform_data = &devkit8000_dss_data, | ||
| 217 | }, | ||
| 218 | }; | ||
| 219 | |||
| 220 | static struct regulator_consumer_supply devkit8000_vdda_dac_supply = { | ||
| 221 | .supply = "vdda_dac", | ||
| 222 | .dev = &devkit8000_dss_device.dev, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static int board_keymap[] = { | ||
| 226 | KEY(0, 0, KEY_1), | ||
| 227 | KEY(1, 0, KEY_2), | ||
| 228 | KEY(2, 0, KEY_3), | ||
| 229 | KEY(0, 1, KEY_4), | ||
| 230 | KEY(1, 1, KEY_5), | ||
| 231 | KEY(2, 1, KEY_6), | ||
| 232 | KEY(3, 1, KEY_F5), | ||
| 233 | KEY(0, 2, KEY_7), | ||
| 234 | KEY(1, 2, KEY_8), | ||
| 235 | KEY(2, 2, KEY_9), | ||
| 236 | KEY(3, 2, KEY_F6), | ||
| 237 | KEY(0, 3, KEY_F7), | ||
| 238 | KEY(1, 3, KEY_0), | ||
| 239 | KEY(2, 3, KEY_F8), | ||
| 240 | PERSISTENT_KEY(4, 5), | ||
| 241 | KEY(4, 4, KEY_VOLUMEUP), | ||
| 242 | KEY(5, 5, KEY_VOLUMEDOWN), | ||
| 243 | 0 | ||
| 244 | }; | ||
| 245 | |||
| 246 | static struct matrix_keymap_data board_map_data = { | ||
| 247 | .keymap = board_keymap, | ||
| 248 | .keymap_size = ARRAY_SIZE(board_keymap), | ||
| 249 | }; | ||
| 250 | |||
| 251 | static struct twl4030_keypad_data devkit8000_kp_data = { | ||
| 252 | .keymap_data = &board_map_data, | ||
| 253 | .rows = 6, | ||
| 254 | .cols = 6, | ||
| 255 | .rep = 1, | ||
| 256 | }; | ||
| 257 | |||
| 258 | static struct gpio_led gpio_leds[]; | ||
| 259 | |||
| 260 | static int devkit8000_twl_gpio_setup(struct device *dev, | ||
| 261 | unsigned gpio, unsigned ngpio) | ||
| 262 | { | ||
| 263 | omap_mux_init_gpio(29, OMAP_PIN_INPUT); | ||
| 264 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | ||
| 265 | mmc[0].gpio_cd = gpio + 0; | ||
| 266 | omap2_hsmmc_init(mmc); | ||
| 267 | |||
| 268 | /* link regulators to MMC adapters */ | ||
| 269 | devkit8000_vmmc1_supply.dev = mmc[0].dev; | ||
| 270 | devkit8000_vsim_supply.dev = mmc[0].dev; | ||
| 271 | |||
| 272 | /* REVISIT: need ehci-omap hooks for external VBUS | ||
| 273 | * power switch and overcurrent detect | ||
| 274 | */ | ||
| 275 | |||
| 276 | gpio_request(gpio + 1, "EHCI_nOC"); | ||
| 277 | gpio_direction_input(gpio + 1); | ||
| 278 | |||
| 279 | /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ | ||
| 280 | gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); | ||
| 281 | gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); | ||
| 282 | |||
| 283 | /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ | ||
| 284 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; | ||
| 285 | |||
| 286 | return 0; | ||
| 287 | } | ||
| 288 | |||
| 289 | static struct twl4030_gpio_platform_data devkit8000_gpio_data = { | ||
| 290 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 291 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 292 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 293 | .use_leds = true, | ||
| 294 | .pullups = BIT(1), | ||
| 295 | .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) | ||
| 296 | | BIT(15) | BIT(16) | BIT(17), | ||
| 297 | .setup = devkit8000_twl_gpio_setup, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = { | ||
| 301 | { | ||
| 302 | .supply = "vdvi", | ||
| 303 | .dev = &devkit8000_lcd_device.dev, | ||
| 304 | }, | ||
| 305 | { | ||
| 306 | .supply = "vdss_dsi", | ||
| 307 | .dev = &devkit8000_dss_device.dev, | ||
| 308 | } | ||
| 309 | }; | ||
| 310 | |||
| 311 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ | ||
| 312 | static struct regulator_init_data devkit8000_vmmc1 = { | ||
| 313 | .constraints = { | ||
| 314 | .min_uV = 1850000, | ||
| 315 | .max_uV = 3150000, | ||
| 316 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 317 | | REGULATOR_MODE_STANDBY, | ||
| 318 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 319 | | REGULATOR_CHANGE_MODE | ||
| 320 | | REGULATOR_CHANGE_STATUS, | ||
| 321 | }, | ||
| 322 | .num_consumer_supplies = 1, | ||
| 323 | .consumer_supplies = &devkit8000_vmmc1_supply, | ||
| 324 | }; | ||
| 325 | |||
| 326 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | ||
| 327 | static struct regulator_init_data devkit8000_vsim = { | ||
| 328 | .constraints = { | ||
| 329 | .min_uV = 1800000, | ||
| 330 | .max_uV = 3000000, | ||
| 331 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 332 | | REGULATOR_MODE_STANDBY, | ||
| 333 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 334 | | REGULATOR_CHANGE_MODE | ||
| 335 | | REGULATOR_CHANGE_STATUS, | ||
| 336 | }, | ||
| 337 | .num_consumer_supplies = 1, | ||
| 338 | .consumer_supplies = &devkit8000_vsim_supply, | ||
| 339 | }; | ||
| 340 | |||
| 341 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ | ||
| 342 | static struct regulator_init_data devkit8000_vdac = { | ||
| 343 | .constraints = { | ||
| 344 | .min_uV = 1800000, | ||
| 345 | .max_uV = 1800000, | ||
| 346 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 347 | | REGULATOR_MODE_STANDBY, | ||
| 348 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 349 | | REGULATOR_CHANGE_STATUS, | ||
| 350 | }, | ||
| 351 | .num_consumer_supplies = 1, | ||
| 352 | .consumer_supplies = &devkit8000_vdda_dac_supply, | ||
| 353 | }; | ||
| 354 | |||
| 355 | /* VPLL2 for digital video outputs */ | ||
| 356 | static struct regulator_init_data devkit8000_vpll2 = { | ||
| 357 | .constraints = { | ||
| 358 | .name = "VDVI", | ||
| 359 | .min_uV = 1800000, | ||
| 360 | .max_uV = 1800000, | ||
| 361 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 362 | | REGULATOR_MODE_STANDBY, | ||
| 363 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 364 | | REGULATOR_CHANGE_STATUS, | ||
| 365 | }, | ||
| 366 | .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll2_supplies), | ||
| 367 | .consumer_supplies = devkit8000_vpll2_supplies, | ||
| 368 | }; | ||
| 369 | |||
| 370 | static struct twl4030_usb_data devkit8000_usb_data = { | ||
| 371 | .usb_mode = T2_USB_MODE_ULPI, | ||
| 372 | }; | ||
| 373 | |||
| 374 | static struct twl4030_codec_audio_data devkit8000_audio_data = { | ||
| 375 | .audio_mclk = 26000000, | ||
| 376 | }; | ||
| 377 | |||
| 378 | static struct twl4030_codec_data devkit8000_codec_data = { | ||
| 379 | .audio_mclk = 26000000, | ||
| 380 | .audio = &devkit8000_audio_data, | ||
| 381 | }; | ||
| 382 | |||
| 383 | static struct twl4030_platform_data devkit8000_twldata = { | ||
| 384 | .irq_base = TWL4030_IRQ_BASE, | ||
| 385 | .irq_end = TWL4030_IRQ_END, | ||
| 386 | |||
| 387 | /* platform_data for children goes here */ | ||
| 388 | .usb = &devkit8000_usb_data, | ||
| 389 | .gpio = &devkit8000_gpio_data, | ||
| 390 | .codec = &devkit8000_codec_data, | ||
| 391 | .vmmc1 = &devkit8000_vmmc1, | ||
| 392 | .vsim = &devkit8000_vsim, | ||
| 393 | .vdac = &devkit8000_vdac, | ||
| 394 | .vpll2 = &devkit8000_vpll2, | ||
| 395 | .keypad = &devkit8000_kp_data, | ||
| 396 | }; | ||
| 397 | |||
| 398 | static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = { | ||
| 399 | { | ||
| 400 | I2C_BOARD_INFO("twl4030", 0x48), | ||
| 401 | .flags = I2C_CLIENT_WAKE, | ||
| 402 | .irq = INT_34XX_SYS_NIRQ, | ||
| 403 | .platform_data = &devkit8000_twldata, | ||
| 404 | }, | ||
| 405 | }; | ||
| 406 | |||
| 407 | static int __init devkit8000_i2c_init(void) | ||
| 408 | { | ||
| 409 | omap_register_i2c_bus(1, 2600, devkit8000_i2c_boardinfo, | ||
| 410 | ARRAY_SIZE(devkit8000_i2c_boardinfo)); | ||
| 411 | /* Bus 3 is attached to the DVI port where devices like the pico DLP | ||
| 412 | * projector don't work reliably with 400kHz */ | ||
| 413 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 414 | return 0; | ||
| 415 | } | ||
| 416 | |||
| 417 | static struct gpio_led gpio_leds[] = { | ||
| 418 | { | ||
| 419 | .name = "led1", | ||
| 420 | .default_trigger = "heartbeat", | ||
| 421 | .gpio = 186, | ||
| 422 | .active_low = true, | ||
| 423 | }, | ||
| 424 | { | ||
| 425 | .name = "led2", | ||
| 426 | .default_trigger = "mmc0", | ||
| 427 | .gpio = 163, | ||
| 428 | .active_low = true, | ||
| 429 | }, | ||
| 430 | { | ||
| 431 | .name = "ledB", | ||
| 432 | .default_trigger = "none", | ||
| 433 | .gpio = 153, | ||
| 434 | .active_low = true, | ||
| 435 | }, | ||
| 436 | { | ||
| 437 | .name = "led3", | ||
| 438 | .default_trigger = "none", | ||
| 439 | .gpio = 164, | ||
| 440 | .active_low = true, | ||
| 441 | }, | ||
| 442 | }; | ||
| 443 | |||
| 444 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 445 | .leds = gpio_leds, | ||
| 446 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 447 | }; | ||
| 448 | |||
| 449 | static struct platform_device leds_gpio = { | ||
| 450 | .name = "leds-gpio", | ||
| 451 | .id = -1, | ||
| 452 | .dev = { | ||
| 453 | .platform_data = &gpio_led_info, | ||
| 454 | }, | ||
| 455 | }; | ||
| 456 | |||
| 457 | static struct gpio_keys_button gpio_buttons[] = { | ||
| 458 | { | ||
| 459 | .code = BTN_EXTRA, | ||
| 460 | .gpio = 26, | ||
| 461 | .desc = "user", | ||
| 462 | .wakeup = 1, | ||
| 463 | }, | ||
| 464 | }; | ||
| 465 | |||
| 466 | static struct gpio_keys_platform_data gpio_key_info = { | ||
| 467 | .buttons = gpio_buttons, | ||
| 468 | .nbuttons = ARRAY_SIZE(gpio_buttons), | ||
| 469 | }; | ||
| 470 | |||
| 471 | static struct platform_device keys_gpio = { | ||
| 472 | .name = "gpio-keys", | ||
| 473 | .id = -1, | ||
| 474 | .dev = { | ||
| 475 | .platform_data = &gpio_key_info, | ||
| 476 | }, | ||
| 477 | }; | ||
| 478 | |||
| 479 | |||
| 480 | static void __init devkit8000_init_irq(void) | ||
| 481 | { | ||
| 482 | omap_board_config = devkit8000_config; | ||
| 483 | omap_board_config_size = ARRAY_SIZE(devkit8000_config); | ||
| 484 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | ||
| 485 | mt46h32m32lf6_sdrc_params); | ||
| 486 | omap_init_irq(); | ||
| 487 | #ifdef CONFIG_OMAP_32K_TIMER | ||
| 488 | omap2_gp_clockevent_set_gptimer(12); | ||
| 489 | #endif | ||
| 490 | omap_gpio_init(); | ||
| 491 | } | ||
| 492 | |||
| 493 | static void __init devkit8000_ads7846_init(void) | ||
| 494 | { | ||
| 495 | int gpio = OMAP3_DEVKIT_TS_GPIO; | ||
| 496 | int ret; | ||
| 497 | |||
| 498 | ret = gpio_request(gpio, "ads7846_pen_down"); | ||
| 499 | if (ret < 0) { | ||
| 500 | printk(KERN_ERR "Failed to request GPIO %d for " | ||
| 501 | "ads7846 pen down IRQ\n", gpio); | ||
| 502 | return; | ||
| 503 | } | ||
| 504 | |||
| 505 | gpio_direction_input(gpio); | ||
| 506 | } | ||
| 507 | |||
| 508 | static int ads7846_get_pendown_state(void) | ||
| 509 | { | ||
| 510 | return !gpio_get_value(OMAP3_DEVKIT_TS_GPIO); | ||
| 511 | } | ||
| 512 | |||
| 513 | static struct ads7846_platform_data ads7846_config = { | ||
| 514 | .x_max = 0x0fff, | ||
| 515 | .y_max = 0x0fff, | ||
| 516 | .x_plate_ohms = 180, | ||
| 517 | .pressure_max = 255, | ||
| 518 | .debounce_max = 10, | ||
| 519 | .debounce_tol = 5, | ||
| 520 | .debounce_rep = 1, | ||
| 521 | .get_pendown_state = ads7846_get_pendown_state, | ||
| 522 | .keep_vref_on = 1, | ||
| 523 | .settle_delay_usecs = 150, | ||
| 524 | }; | ||
| 525 | |||
| 526 | static struct omap2_mcspi_device_config ads7846_mcspi_config = { | ||
| 527 | .turbo_mode = 0, | ||
| 528 | .single_channel = 1, /* 0: slave, 1: master */ | ||
| 529 | }; | ||
| 530 | |||
| 531 | static struct spi_board_info devkit8000_spi_board_info[] __initdata = { | ||
| 532 | { | ||
| 533 | .modalias = "ads7846", | ||
| 534 | .bus_num = 2, | ||
| 535 | .chip_select = 0, | ||
| 536 | .max_speed_hz = 1500000, | ||
| 537 | .controller_data = &ads7846_mcspi_config, | ||
| 538 | .irq = OMAP_GPIO_IRQ(OMAP3_DEVKIT_TS_GPIO), | ||
| 539 | .platform_data = &ads7846_config, | ||
| 540 | } | ||
| 541 | }; | ||
| 542 | |||
| 543 | #define OMAP_DM9000_BASE 0x2c000000 | ||
| 544 | |||
| 545 | static struct resource omap_dm9000_resources[] = { | ||
| 546 | [0] = { | ||
| 547 | .start = OMAP_DM9000_BASE, | ||
| 548 | .end = (OMAP_DM9000_BASE + 0x4 - 1), | ||
| 549 | .flags = IORESOURCE_MEM, | ||
| 550 | }, | ||
| 551 | [1] = { | ||
| 552 | .start = (OMAP_DM9000_BASE + 0x400), | ||
| 553 | .end = (OMAP_DM9000_BASE + 0x400 + 0x4 - 1), | ||
| 554 | .flags = IORESOURCE_MEM, | ||
| 555 | }, | ||
| 556 | [2] = { | ||
| 557 | .start = OMAP_GPIO_IRQ(OMAP_DM9000_GPIO_IRQ), | ||
| 558 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | ||
| 559 | }, | ||
| 560 | }; | ||
| 561 | |||
| 562 | static struct dm9000_plat_data omap_dm9000_platdata = { | ||
| 563 | .flags = DM9000_PLATF_16BITONLY, | ||
| 564 | }; | ||
| 565 | |||
| 566 | static struct platform_device omap_dm9000_dev = { | ||
| 567 | .name = "dm9000", | ||
| 568 | .id = -1, | ||
| 569 | .num_resources = ARRAY_SIZE(omap_dm9000_resources), | ||
| 570 | .resource = omap_dm9000_resources, | ||
| 571 | .dev = { | ||
| 572 | .platform_data = &omap_dm9000_platdata, | ||
| 573 | }, | ||
| 574 | }; | ||
| 575 | |||
| 576 | static void __init omap_dm9000_init(void) | ||
| 577 | { | ||
| 578 | if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) { | ||
| 579 | printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n", | ||
| 580 | OMAP_DM9000_GPIO_IRQ); | ||
| 581 | return; | ||
| 582 | } | ||
| 583 | |||
| 584 | gpio_direction_input(OMAP_DM9000_GPIO_IRQ); | ||
| 585 | } | ||
| 586 | |||
| 587 | static struct platform_device *devkit8000_devices[] __initdata = { | ||
| 588 | &devkit8000_dss_device, | ||
| 589 | &leds_gpio, | ||
| 590 | &keys_gpio, | ||
| 591 | &omap_dm9000_dev, | ||
| 592 | }; | ||
| 593 | |||
| 594 | static void __init devkit8000_flash_init(void) | ||
| 595 | { | ||
| 596 | u8 cs = 0; | ||
| 597 | u8 nandcs = GPMC_CS_NUM + 1; | ||
| 598 | |||
| 599 | u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; | ||
| 600 | |||
| 601 | /* find out the chip-select on which NAND exists */ | ||
| 602 | while (cs < GPMC_CS_NUM) { | ||
| 603 | u32 ret = 0; | ||
| 604 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 605 | |||
| 606 | if ((ret & 0xC00) == 0x800) { | ||
| 607 | printk(KERN_INFO "Found NAND on CS%d\n", cs); | ||
| 608 | if (nandcs > GPMC_CS_NUM) | ||
| 609 | nandcs = cs; | ||
| 610 | } | ||
| 611 | cs++; | ||
| 612 | } | ||
| 613 | |||
| 614 | if (nandcs > GPMC_CS_NUM) { | ||
| 615 | printk(KERN_INFO "NAND: Unable to find configuration " | ||
| 616 | "in GPMC\n "); | ||
| 617 | return; | ||
| 618 | } | ||
| 619 | |||
| 620 | if (nandcs < GPMC_CS_NUM) { | ||
| 621 | devkit8000_nand_data.cs = nandcs; | ||
| 622 | devkit8000_nand_data.gpmc_cs_baseaddr = (void *) | ||
| 623 | (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); | ||
| 624 | devkit8000_nand_data.gpmc_baseaddr = (void *) | ||
| 625 | (gpmc_base_add); | ||
| 626 | |||
| 627 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); | ||
| 628 | if (platform_device_register(&devkit8000_nand_device) < 0) | ||
| 629 | printk(KERN_ERR "Unable to register NAND device\n"); | ||
| 630 | } | ||
| 631 | } | ||
| 632 | |||
| 633 | static struct omap_musb_board_data musb_board_data = { | ||
| 634 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 635 | .mode = MUSB_OTG, | ||
| 636 | .power = 100, | ||
| 637 | }; | ||
| 638 | |||
| 639 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | ||
| 640 | |||
| 641 | .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, | ||
| 642 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, | ||
| 643 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 644 | |||
| 645 | .phy_reset = true, | ||
| 646 | .reset_gpio_port[0] = -EINVAL, | ||
| 647 | .reset_gpio_port[1] = 147, | ||
| 648 | .reset_gpio_port[2] = -EINVAL | ||
| 649 | }; | ||
| 650 | |||
| 651 | static void __init devkit8000_init(void) | ||
| 652 | { | ||
| 653 | devkit8000_i2c_init(); | ||
| 654 | platform_add_devices(devkit8000_devices, | ||
| 655 | ARRAY_SIZE(devkit8000_devices)); | ||
| 656 | omap_board_config = devkit8000_config; | ||
| 657 | omap_board_config_size = ARRAY_SIZE(devkit8000_config); | ||
| 658 | |||
| 659 | spi_register_board_info(devkit8000_spi_board_info, | ||
| 660 | ARRAY_SIZE(devkit8000_spi_board_info)); | ||
| 661 | |||
| 662 | omap_serial_init(); | ||
| 663 | |||
| 664 | omap_dm9000_init(); | ||
| 665 | |||
| 666 | devkit8000_ads7846_init(); | ||
| 667 | |||
| 668 | omap_mux_init_gpio(170, OMAP_PIN_INPUT); | ||
| 669 | |||
| 670 | gpio_request(170, "DVI_nPD"); | ||
| 671 | /* REVISIT leave DVI powered down until it's needed ... */ | ||
| 672 | gpio_direction_output(170, true); | ||
| 673 | |||
| 674 | usb_musb_init(&musb_board_data); | ||
| 675 | usb_ehci_init(&ehci_pdata); | ||
| 676 | devkit8000_flash_init(); | ||
| 677 | |||
| 678 | /* Ensure SDRC pins are mux'd for self-refresh */ | ||
| 679 | omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT); | ||
| 680 | omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); | ||
| 681 | } | ||
| 682 | |||
| 683 | static void __init devkit8000_map_io(void) | ||
| 684 | { | ||
| 685 | omap2_set_globals_343x(); | ||
| 686 | omap34xx_map_common_io(); | ||
| 687 | } | ||
| 688 | |||
| 689 | MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") | ||
| 690 | .phys_io = 0x48000000, | ||
| 691 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | ||
| 692 | .boot_params = 0x80000100, | ||
| 693 | .map_io = devkit8000_map_io, | ||
| 694 | .init_irq = devkit8000_init_irq, | ||
| 695 | .init_machine = devkit8000_init, | ||
| 696 | .timer = &omap_timer, | ||
| 697 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 7e6e6ca88be5..16cc06860670 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -50,7 +50,7 @@ static void __init omap_generic_init(void) | |||
| 50 | static void __init omap_generic_map_io(void) | 50 | static void __init omap_generic_map_io(void) |
| 51 | { | 51 | { |
| 52 | omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ | 52 | omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ |
| 53 | omap2_map_common_io(); | 53 | omap242x_map_common_io(); |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") | 56 | MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index cfb7f1257d20..0665f2c8dc8e 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/mtd/mtd.h> | 17 | #include <linux/mtd/mtd.h> |
| 18 | #include <linux/mtd/partitions.h> | 18 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/mtd/physmap.h> | ||
| 19 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
| 20 | #include <linux/workqueue.h> | 21 | #include <linux/workqueue.h> |
| 21 | #include <linux/i2c.h> | 22 | #include <linux/i2c.h> |
| @@ -29,7 +30,6 @@ | |||
| 29 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
| 32 | #include <asm/mach/flash.h> | ||
| 33 | 33 | ||
| 34 | #include <plat/control.h> | 34 | #include <plat/control.h> |
| 35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
| @@ -115,8 +115,7 @@ static struct mtd_partition h4_partitions[] = { | |||
| 115 | } | 115 | } |
| 116 | }; | 116 | }; |
| 117 | 117 | ||
| 118 | static struct flash_platform_data h4_flash_data = { | 118 | static struct physmap_flash_data h4_flash_data = { |
| 119 | .map_name = "cfi_probe", | ||
| 120 | .width = 2, | 119 | .width = 2, |
| 121 | .parts = h4_partitions, | 120 | .parts = h4_partitions, |
| 122 | .nr_parts = ARRAY_SIZE(h4_partitions), | 121 | .nr_parts = ARRAY_SIZE(h4_partitions), |
| @@ -127,7 +126,7 @@ static struct resource h4_flash_resource = { | |||
| 127 | }; | 126 | }; |
| 128 | 127 | ||
| 129 | static struct platform_device h4_flash_device = { | 128 | static struct platform_device h4_flash_device = { |
| 130 | .name = "omapflash", | 129 | .name = "physmap-flash", |
| 131 | .id = 0, | 130 | .id = 0, |
| 132 | .dev = { | 131 | .dev = { |
| 133 | .platform_data = &h4_flash_data, | 132 | .platform_data = &h4_flash_data, |
| @@ -370,7 +369,7 @@ static void __init omap_h4_init(void) | |||
| 370 | static void __init omap_h4_map_io(void) | 369 | static void __init omap_h4_map_io(void) |
| 371 | { | 370 | { |
| 372 | omap2_set_globals_242x(); | 371 | omap2_set_globals_242x(); |
| 373 | omap2_map_common_io(); | 372 | omap242x_map_common_io(); |
| 374 | } | 373 | } |
| 375 | 374 | ||
| 376 | MACHINE_START(OMAP_H4, "OMAP2420 H4 board") | 375 | MACHINE_START(OMAP_H4, "OMAP2420 H4 board") |
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 117b8fd7e3a6..9958987a3d0a 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
| 19 | #include <linux/leds.h> | ||
| 19 | #include <linux/interrupt.h> | 20 | #include <linux/interrupt.h> |
| 20 | 21 | ||
| 21 | #include <linux/regulator/machine.h> | 22 | #include <linux/regulator/machine.h> |
| @@ -28,9 +29,12 @@ | |||
| 28 | #include <plat/common.h> | 29 | #include <plat/common.h> |
| 29 | #include <plat/gpmc.h> | 30 | #include <plat/gpmc.h> |
| 30 | #include <plat/usb.h> | 31 | #include <plat/usb.h> |
| 32 | #include <plat/display.h> | ||
| 33 | #include <plat/onenand.h> | ||
| 31 | 34 | ||
| 32 | #include "mux.h" | 35 | #include "mux.h" |
| 33 | #include "mmc-twl4030.h" | 36 | #include "hsmmc.h" |
| 37 | #include "sdram-numonyx-m65kxxxxam.h" | ||
| 34 | 38 | ||
| 35 | #define IGEP2_SMSC911X_CS 5 | 39 | #define IGEP2_SMSC911X_CS 5 |
| 36 | #define IGEP2_SMSC911X_GPIO 176 | 40 | #define IGEP2_SMSC911X_GPIO 176 |
| @@ -38,6 +42,108 @@ | |||
| 38 | #define IGEP2_GPIO_LED0_RED 26 | 42 | #define IGEP2_GPIO_LED0_RED 26 |
| 39 | #define IGEP2_GPIO_LED0_GREEN 27 | 43 | #define IGEP2_GPIO_LED0_GREEN 27 |
| 40 | #define IGEP2_GPIO_LED1_RED 28 | 44 | #define IGEP2_GPIO_LED1_RED 28 |
| 45 | #define IGEP2_GPIO_DVI_PUP 170 | ||
| 46 | #define IGEP2_GPIO_WIFI_NPD 94 | ||
| 47 | #define IGEP2_GPIO_WIFI_NRESET 95 | ||
| 48 | |||
| 49 | #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ | ||
| 50 | defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) | ||
| 51 | |||
| 52 | #define ONENAND_MAP 0x20000000 | ||
| 53 | |||
| 54 | /* NAND04GR4E1A ( x2 Flash built-in COMBO POP MEMORY ) | ||
| 55 | * Since the device is equipped with two DataRAMs, and two-plane NAND | ||
| 56 | * Flash memory array, these two component enables simultaneous program | ||
| 57 | * of 4KiB. Plane1 has only even blocks such as block0, block2, block4 | ||
| 58 | * while Plane2 has only odd blocks such as block1, block3, block5. | ||
| 59 | * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) | ||
| 60 | */ | ||
| 61 | |||
| 62 | static struct mtd_partition igep2_onenand_partitions[] = { | ||
| 63 | { | ||
| 64 | .name = "X-Loader", | ||
| 65 | .offset = 0, | ||
| 66 | .size = 2 * (64*(2*2048)) | ||
| 67 | }, | ||
| 68 | { | ||
| 69 | .name = "U-Boot", | ||
| 70 | .offset = MTDPART_OFS_APPEND, | ||
| 71 | .size = 6 * (64*(2*2048)), | ||
| 72 | }, | ||
| 73 | { | ||
| 74 | .name = "Environment", | ||
| 75 | .offset = MTDPART_OFS_APPEND, | ||
| 76 | .size = 2 * (64*(2*2048)), | ||
| 77 | }, | ||
| 78 | { | ||
| 79 | .name = "Kernel", | ||
| 80 | .offset = MTDPART_OFS_APPEND, | ||
| 81 | .size = 12 * (64*(2*2048)), | ||
| 82 | }, | ||
| 83 | { | ||
| 84 | .name = "File System", | ||
| 85 | .offset = MTDPART_OFS_APPEND, | ||
| 86 | .size = MTDPART_SIZ_FULL, | ||
| 87 | }, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static int igep2_onenand_setup(void __iomem *onenand_base, int freq) | ||
| 91 | { | ||
| 92 | /* nothing is required to be setup for onenand as of now */ | ||
| 93 | return 0; | ||
| 94 | } | ||
| 95 | |||
| 96 | static struct omap_onenand_platform_data igep2_onenand_data = { | ||
| 97 | .parts = igep2_onenand_partitions, | ||
| 98 | .nr_parts = ARRAY_SIZE(igep2_onenand_partitions), | ||
| 99 | .onenand_setup = igep2_onenand_setup, | ||
| 100 | .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct platform_device igep2_onenand_device = { | ||
| 104 | .name = "omap2-onenand", | ||
| 105 | .id = -1, | ||
| 106 | .dev = { | ||
| 107 | .platform_data = &igep2_onenand_data, | ||
| 108 | }, | ||
| 109 | }; | ||
| 110 | |||
| 111 | void __init igep2_flash_init(void) | ||
| 112 | { | ||
| 113 | u8 cs = 0; | ||
| 114 | u8 onenandcs = GPMC_CS_NUM + 1; | ||
| 115 | |||
| 116 | while (cs < GPMC_CS_NUM) { | ||
| 117 | u32 ret = 0; | ||
| 118 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 119 | |||
| 120 | /* Check if NAND/oneNAND is configured */ | ||
| 121 | if ((ret & 0xC00) == 0x800) | ||
| 122 | /* NAND found */ | ||
| 123 | pr_err("IGEP v2: Unsupported NAND found\n"); | ||
| 124 | else { | ||
| 125 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | ||
| 126 | if ((ret & 0x3F) == (ONENAND_MAP >> 24)) | ||
| 127 | /* ONENAND found */ | ||
| 128 | onenandcs = cs; | ||
| 129 | } | ||
| 130 | cs++; | ||
| 131 | } | ||
| 132 | if (onenandcs > GPMC_CS_NUM) { | ||
| 133 | pr_err("IGEP v2: Unable to find configuration in GPMC\n"); | ||
| 134 | return; | ||
| 135 | } | ||
| 136 | |||
| 137 | if (onenandcs < GPMC_CS_NUM) { | ||
| 138 | igep2_onenand_data.cs = onenandcs; | ||
| 139 | if (platform_device_register(&igep2_onenand_device) < 0) | ||
| 140 | pr_err("IGEP v2: Unable to register OneNAND device\n"); | ||
| 141 | } | ||
| 142 | } | ||
| 143 | |||
| 144 | #else | ||
| 145 | void __init igep2_flash_init(void) {} | ||
| 146 | #endif | ||
| 41 | 147 | ||
| 42 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | 148 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 43 | 149 | ||
| @@ -106,6 +212,10 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = { | |||
| 106 | .supply = "vmmc", | 212 | .supply = "vmmc", |
| 107 | }; | 213 | }; |
| 108 | 214 | ||
| 215 | static struct regulator_consumer_supply igep2_vmmc2_supply = { | ||
| 216 | .supply = "vmmc", | ||
| 217 | }; | ||
| 218 | |||
| 109 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | 219 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ |
| 110 | static struct regulator_init_data igep2_vmmc1 = { | 220 | static struct regulator_init_data igep2_vmmc1 = { |
| 111 | .constraints = { | 221 | .constraints = { |
| @@ -121,7 +231,22 @@ static struct regulator_init_data igep2_vmmc1 = { | |||
| 121 | .consumer_supplies = &igep2_vmmc1_supply, | 231 | .consumer_supplies = &igep2_vmmc1_supply, |
| 122 | }; | 232 | }; |
| 123 | 233 | ||
| 124 | static struct twl4030_hsmmc_info mmc[] = { | 234 | /* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */ |
| 235 | static struct regulator_init_data igep2_vmmc2 = { | ||
| 236 | .constraints = { | ||
| 237 | .min_uV = 1850000, | ||
| 238 | .max_uV = 3150000, | ||
| 239 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 240 | | REGULATOR_MODE_STANDBY, | ||
| 241 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 242 | | REGULATOR_CHANGE_MODE | ||
| 243 | | REGULATOR_CHANGE_STATUS, | ||
| 244 | }, | ||
| 245 | .num_consumer_supplies = 1, | ||
| 246 | .consumer_supplies = &igep2_vmmc2_supply, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct omap2_hsmmc_info mmc[] = { | ||
| 125 | { | 250 | { |
| 126 | .mmc = 1, | 251 | .mmc = 1, |
| 127 | .wires = 4, | 252 | .wires = 4, |
| @@ -142,12 +267,13 @@ static int igep2_twl_gpio_setup(struct device *dev, | |||
| 142 | { | 267 | { |
| 143 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 268 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 144 | mmc[0].gpio_cd = gpio + 0; | 269 | mmc[0].gpio_cd = gpio + 0; |
| 145 | twl4030_mmc_init(mmc); | 270 | omap2_hsmmc_init(mmc); |
| 146 | 271 | ||
| 147 | /* link regulators to MMC adapters ... we "know" the | 272 | /* link regulators to MMC adapters ... we "know" the |
| 148 | * regulators will be set up only *after* we return. | 273 | * regulators will be set up only *after* we return. |
| 149 | */ | 274 | */ |
| 150 | igep2_vmmc1_supply.dev = mmc[0].dev; | 275 | igep2_vmmc1_supply.dev = mmc[0].dev; |
| 276 | igep2_vmmc2_supply.dev = mmc[1].dev; | ||
| 151 | 277 | ||
| 152 | return 0; | 278 | return 0; |
| 153 | }; | 279 | }; |
| @@ -164,23 +290,130 @@ static struct twl4030_usb_data igep2_usb_data = { | |||
| 164 | .usb_mode = T2_USB_MODE_ULPI, | 290 | .usb_mode = T2_USB_MODE_ULPI, |
| 165 | }; | 291 | }; |
| 166 | 292 | ||
| 293 | static int igep2_enable_dvi(struct omap_dss_device *dssdev) | ||
| 294 | { | ||
| 295 | gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1); | ||
| 296 | |||
| 297 | return 0; | ||
| 298 | } | ||
| 299 | |||
| 300 | static void igep2_disable_dvi(struct omap_dss_device *dssdev) | ||
| 301 | { | ||
| 302 | gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0); | ||
| 303 | } | ||
| 304 | |||
| 305 | static struct omap_dss_device igep2_dvi_device = { | ||
| 306 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 307 | .name = "dvi", | ||
| 308 | .driver_name = "generic_panel", | ||
| 309 | .phy.dpi.data_lines = 24, | ||
| 310 | .platform_enable = igep2_enable_dvi, | ||
| 311 | .platform_disable = igep2_disable_dvi, | ||
| 312 | }; | ||
| 313 | |||
| 314 | static struct omap_dss_device *igep2_dss_devices[] = { | ||
| 315 | &igep2_dvi_device | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct omap_dss_board_info igep2_dss_data = { | ||
| 319 | .num_devices = ARRAY_SIZE(igep2_dss_devices), | ||
| 320 | .devices = igep2_dss_devices, | ||
| 321 | .default_device = &igep2_dvi_device, | ||
| 322 | }; | ||
| 323 | |||
| 324 | static struct platform_device igep2_dss_device = { | ||
| 325 | .name = "omapdss", | ||
| 326 | .id = -1, | ||
| 327 | .dev = { | ||
| 328 | .platform_data = &igep2_dss_data, | ||
| 329 | }, | ||
| 330 | }; | ||
| 331 | |||
| 332 | static struct regulator_consumer_supply igep2_vpll2_supply = { | ||
| 333 | .supply = "vdds_dsi", | ||
| 334 | .dev = &igep2_dss_device.dev, | ||
| 335 | }; | ||
| 336 | |||
| 337 | static struct regulator_init_data igep2_vpll2 = { | ||
| 338 | .constraints = { | ||
| 339 | .name = "VDVI", | ||
| 340 | .min_uV = 1800000, | ||
| 341 | .max_uV = 1800000, | ||
| 342 | .apply_uV = true, | ||
| 343 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 344 | | REGULATOR_MODE_STANDBY, | ||
| 345 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 346 | | REGULATOR_CHANGE_STATUS, | ||
| 347 | }, | ||
| 348 | .num_consumer_supplies = 1, | ||
| 349 | .consumer_supplies = &igep2_vpll2_supply, | ||
| 350 | }; | ||
| 351 | |||
| 352 | static void __init igep2_display_init(void) | ||
| 353 | { | ||
| 354 | if (gpio_request(IGEP2_GPIO_DVI_PUP, "GPIO_DVI_PUP") && | ||
| 355 | gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1)) | ||
| 356 | pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); | ||
| 357 | } | ||
| 358 | #ifdef CONFIG_LEDS_TRIGGERS | ||
| 359 | static struct gpio_led gpio_leds[] = { | ||
| 360 | { | ||
| 361 | .name = "GPIO_LED1_RED", | ||
| 362 | .default_trigger = "heartbeat", | ||
| 363 | .gpio = IGEP2_GPIO_LED1_RED, | ||
| 364 | }, | ||
| 365 | }; | ||
| 366 | |||
| 367 | static struct gpio_led_platform_data gpio_leds_info = { | ||
| 368 | .leds = gpio_leds, | ||
| 369 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 370 | }; | ||
| 371 | |||
| 372 | static struct platform_device leds_gpio = { | ||
| 373 | .name = "leds-gpio", | ||
| 374 | .id = -1, | ||
| 375 | .dev = { | ||
| 376 | .platform_data = &gpio_leds_info, | ||
| 377 | }, | ||
| 378 | }; | ||
| 379 | #endif | ||
| 380 | |||
| 381 | static struct platform_device *igep2_devices[] __initdata = { | ||
| 382 | &igep2_dss_device, | ||
| 383 | #ifdef CONFIG_LEDS_TRIGGERS | ||
| 384 | &leds_gpio, | ||
| 385 | #endif | ||
| 386 | }; | ||
| 387 | |||
| 167 | static void __init igep2_init_irq(void) | 388 | static void __init igep2_init_irq(void) |
| 168 | { | 389 | { |
| 169 | omap_board_config = igep2_config; | 390 | omap_board_config = igep2_config; |
| 170 | omap_board_config_size = ARRAY_SIZE(igep2_config); | 391 | omap_board_config_size = ARRAY_SIZE(igep2_config); |
| 171 | omap2_init_common_hw(NULL, NULL); | 392 | omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); |
| 172 | omap_init_irq(); | 393 | omap_init_irq(); |
| 173 | omap_gpio_init(); | 394 | omap_gpio_init(); |
| 174 | } | 395 | } |
| 175 | 396 | ||
| 397 | static struct twl4030_codec_audio_data igep2_audio_data = { | ||
| 398 | .audio_mclk = 26000000, | ||
| 399 | }; | ||
| 400 | |||
| 401 | static struct twl4030_codec_data igep2_codec_data = { | ||
| 402 | .audio_mclk = 26000000, | ||
| 403 | .audio = &igep2_audio_data, | ||
| 404 | }; | ||
| 405 | |||
| 176 | static struct twl4030_platform_data igep2_twldata = { | 406 | static struct twl4030_platform_data igep2_twldata = { |
| 177 | .irq_base = TWL4030_IRQ_BASE, | 407 | .irq_base = TWL4030_IRQ_BASE, |
| 178 | .irq_end = TWL4030_IRQ_END, | 408 | .irq_end = TWL4030_IRQ_END, |
| 179 | 409 | ||
| 180 | /* platform_data for children goes here */ | 410 | /* platform_data for children goes here */ |
| 181 | .usb = &igep2_usb_data, | 411 | .usb = &igep2_usb_data, |
| 412 | .codec = &igep2_codec_data, | ||
| 182 | .gpio = &igep2_gpio_data, | 413 | .gpio = &igep2_gpio_data, |
| 183 | .vmmc1 = &igep2_vmmc1, | 414 | .vmmc1 = &igep2_vmmc1, |
| 415 | .vmmc2 = &igep2_vmmc2, | ||
| 416 | .vpll2 = &igep2_vpll2, | ||
| 184 | 417 | ||
| 185 | }; | 418 | }; |
| 186 | 419 | ||
| @@ -203,6 +436,23 @@ static int __init igep2_i2c_init(void) | |||
| 203 | return 0; | 436 | return 0; |
| 204 | } | 437 | } |
| 205 | 438 | ||
| 439 | static struct omap_musb_board_data musb_board_data = { | ||
| 440 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 441 | .mode = MUSB_OTG, | ||
| 442 | .power = 100, | ||
| 443 | }; | ||
| 444 | |||
| 445 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | ||
| 446 | .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 447 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, | ||
| 448 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 449 | |||
| 450 | .phy_reset = true, | ||
| 451 | .reset_gpio_port[0] = -EINVAL, | ||
| 452 | .reset_gpio_port[1] = IGEP2_GPIO_USBH_NRESET, | ||
| 453 | .reset_gpio_port[2] = -EINVAL, | ||
| 454 | }; | ||
| 455 | |||
| 206 | #ifdef CONFIG_OMAP_MUX | 456 | #ifdef CONFIG_OMAP_MUX |
| 207 | static struct omap_board_mux board_mux[] __initdata = { | 457 | static struct omap_board_mux board_mux[] __initdata = { |
| 208 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 458 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| @@ -215,9 +465,13 @@ static void __init igep2_init(void) | |||
| 215 | { | 465 | { |
| 216 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 466 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 217 | igep2_i2c_init(); | 467 | igep2_i2c_init(); |
| 468 | platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); | ||
| 218 | omap_serial_init(); | 469 | omap_serial_init(); |
| 219 | usb_musb_init(); | 470 | usb_musb_init(&musb_board_data); |
| 471 | usb_ehci_init(&ehci_pdata); | ||
| 220 | 472 | ||
| 473 | igep2_flash_init(); | ||
| 474 | igep2_display_init(); | ||
| 221 | igep2_init_smsc911x(); | 475 | igep2_init_smsc911x(); |
| 222 | 476 | ||
| 223 | /* GPIO userspace leds */ | 477 | /* GPIO userspace leds */ |
| @@ -234,19 +488,36 @@ static void __init igep2_init(void) | |||
| 234 | gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); | 488 | gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); |
| 235 | } else | 489 | } else |
| 236 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); | 490 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); |
| 237 | 491 | #ifndef CONFIG_LEDS_TRIGGERS | |
| 238 | if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_LED1_RED") == 0) && | 492 | if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_LED1_RED") == 0) && |
| 239 | (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { | 493 | (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { |
| 240 | gpio_export(IGEP2_GPIO_LED1_RED, 0); | 494 | gpio_export(IGEP2_GPIO_LED1_RED, 0); |
| 241 | gpio_set_value(IGEP2_GPIO_LED1_RED, 0); | 495 | gpio_set_value(IGEP2_GPIO_LED1_RED, 0); |
| 242 | } else | 496 | } else |
| 243 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); | 497 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); |
| 498 | #endif | ||
| 499 | /* GPIO W-LAN + Bluetooth combo module */ | ||
| 500 | if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && | ||
| 501 | (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { | ||
| 502 | gpio_export(IGEP2_GPIO_WIFI_NPD, 0); | ||
| 503 | /* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ | ||
| 504 | } else | ||
| 505 | pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); | ||
| 506 | |||
| 507 | if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && | ||
| 508 | (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) { | ||
| 509 | gpio_export(IGEP2_GPIO_WIFI_NRESET, 0); | ||
| 510 | gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0); | ||
| 511 | udelay(10); | ||
| 512 | gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1); | ||
| 513 | } else | ||
| 514 | pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); | ||
| 244 | } | 515 | } |
| 245 | 516 | ||
| 246 | static void __init igep2_map_io(void) | 517 | static void __init igep2_map_io(void) |
| 247 | { | 518 | { |
| 248 | omap2_set_globals_343x(); | 519 | omap2_set_globals_343x(); |
| 249 | omap2_map_common_io(); | 520 | omap34xx_map_common_io(); |
| 250 | } | 521 | } |
| 251 | 522 | ||
| 252 | MACHINE_START(IGEP0020, "IGEP v2 board") | 523 | MACHINE_START(IGEP0020, "IGEP v2 board") |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 995d4a2b2dfd..5fcb52e71298 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -44,7 +44,7 @@ | |||
| 44 | #include <plat/usb.h> | 44 | #include <plat/usb.h> |
| 45 | 45 | ||
| 46 | #include "mux.h" | 46 | #include "mux.h" |
| 47 | #include "mmc-twl4030.h" | 47 | #include "hsmmc.h" |
| 48 | 48 | ||
| 49 | #define LDP_SMSC911X_CS 1 | 49 | #define LDP_SMSC911X_CS 1 |
| 50 | #define LDP_SMSC911X_GPIO 152 | 50 | #define LDP_SMSC911X_GPIO 152 |
| @@ -359,7 +359,7 @@ static int __init omap_i2c_init(void) | |||
| 359 | return 0; | 359 | return 0; |
| 360 | } | 360 | } |
| 361 | 361 | ||
| 362 | static struct twl4030_hsmmc_info mmc[] __initdata = { | 362 | static struct omap2_hsmmc_info mmc[] __initdata = { |
| 363 | { | 363 | { |
| 364 | .mmc = 1, | 364 | .mmc = 1, |
| 365 | .wires = 4, | 365 | .wires = 4, |
| @@ -383,6 +383,12 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 383 | #define board_mux NULL | 383 | #define board_mux NULL |
| 384 | #endif | 384 | #endif |
| 385 | 385 | ||
| 386 | static struct omap_musb_board_data musb_board_data = { | ||
| 387 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 388 | .mode = MUSB_OTG, | ||
| 389 | .power = 100, | ||
| 390 | }; | ||
| 391 | |||
| 386 | static void __init omap_ldp_init(void) | 392 | static void __init omap_ldp_init(void) |
| 387 | { | 393 | { |
| 388 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 394 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| @@ -394,9 +400,9 @@ static void __init omap_ldp_init(void) | |||
| 394 | ARRAY_SIZE(ldp_spi_board_info)); | 400 | ARRAY_SIZE(ldp_spi_board_info)); |
| 395 | ads7846_dev_init(); | 401 | ads7846_dev_init(); |
| 396 | omap_serial_init(); | 402 | omap_serial_init(); |
| 397 | usb_musb_init(); | 403 | usb_musb_init(&musb_board_data); |
| 398 | 404 | ||
| 399 | twl4030_mmc_init(mmc); | 405 | omap2_hsmmc_init(mmc); |
| 400 | /* link regulators to MMC adapters */ | 406 | /* link regulators to MMC adapters */ |
| 401 | ldp_vmmc1_supply.dev = mmc[0].dev; | 407 | ldp_vmmc1_supply.dev = mmc[0].dev; |
| 402 | } | 408 | } |
| @@ -404,7 +410,7 @@ static void __init omap_ldp_init(void) | |||
| 404 | static void __init omap_ldp_map_io(void) | 410 | static void __init omap_ldp_map_io(void) |
| 405 | { | 411 | { |
| 406 | omap2_set_globals_343x(); | 412 | omap2_set_globals_343x(); |
| 407 | omap2_map_common_io(); | 413 | omap34xx_map_common_io(); |
| 408 | } | 414 | } |
| 409 | 415 | ||
| 410 | MACHINE_START(OMAP_LDP, "OMAP LDP board") | 416 | MACHINE_START(OMAP_LDP, "OMAP LDP board") |
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 764ab1ed576d..4cab0522d7ce 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | #include <linux/stddef.h> | 19 | #include <linux/stddef.h> |
| 20 | #include <linux/i2c.h> | ||
| 20 | #include <linux/spi/spi.h> | 21 | #include <linux/spi/spi.h> |
| 21 | #include <linux/usb/musb.h> | 22 | #include <linux/usb/musb.h> |
| 22 | 23 | ||
| @@ -25,11 +26,17 @@ | |||
| 25 | 26 | ||
| 26 | #include <plat/board.h> | 27 | #include <plat/board.h> |
| 27 | #include <plat/common.h> | 28 | #include <plat/common.h> |
| 29 | #include <plat/menelaus.h> | ||
| 28 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
| 29 | #include <plat/mcspi.h> | 31 | #include <plat/mcspi.h> |
| 30 | #include <plat/onenand.h> | 32 | #include <plat/onenand.h> |
| 33 | #include <plat/mmc.h> | ||
| 31 | #include <plat/serial.h> | 34 | #include <plat/serial.h> |
| 32 | 35 | ||
| 36 | static int slot1_cover_open; | ||
| 37 | static int slot2_cover_open; | ||
| 38 | static struct device *mmc_device; | ||
| 39 | |||
| 33 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { | 40 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { |
| 34 | .turbo_mode = 0, | 41 | .turbo_mode = 0, |
| 35 | .single_channel = 1, | 42 | .single_channel = 1, |
| @@ -96,10 +103,446 @@ static void __init n8x0_onenand_init(void) {} | |||
| 96 | 103 | ||
| 97 | #endif | 104 | #endif |
| 98 | 105 | ||
| 106 | #if defined(CONFIG_MENELAUS) && \ | ||
| 107 | (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)) | ||
| 108 | |||
| 109 | /* | ||
| 110 | * On both N800 and N810, only the first of the two MMC controllers is in use. | ||
| 111 | * The two MMC slots are multiplexed via Menelaus companion chip over I2C. | ||
| 112 | * On N800, both slots are powered via Menelaus. On N810, only one of the | ||
| 113 | * slots is powered via Menelaus. The N810 EMMC is powered via GPIO. | ||
| 114 | * | ||
| 115 | * VMMC slot 1 on both N800 and N810 | ||
| 116 | * VDCDC3_APE and VMCS2_APE slot 2 on N800 | ||
| 117 | * GPIO23 and GPIO9 slot 2 EMMC on N810 | ||
| 118 | * | ||
| 119 | */ | ||
| 120 | #define N8X0_SLOT_SWITCH_GPIO 96 | ||
| 121 | #define N810_EMMC_VSD_GPIO 23 | ||
| 122 | #define NN810_EMMC_VIO_GPIO 9 | ||
| 123 | |||
| 124 | static int n8x0_mmc_switch_slot(struct device *dev, int slot) | ||
| 125 | { | ||
| 126 | #ifdef CONFIG_MMC_DEBUG | ||
| 127 | dev_dbg(dev, "Choose slot %d\n", slot + 1); | ||
| 128 | #endif | ||
| 129 | gpio_set_value(N8X0_SLOT_SWITCH_GPIO, slot); | ||
| 130 | return 0; | ||
| 131 | } | ||
| 132 | |||
| 133 | static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot, | ||
| 134 | int power_on, int vdd) | ||
| 135 | { | ||
| 136 | int mV; | ||
| 137 | |||
| 138 | #ifdef CONFIG_MMC_DEBUG | ||
| 139 | dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, | ||
| 140 | power_on ? "on" : "off", vdd); | ||
| 141 | #endif | ||
| 142 | if (slot == 0) { | ||
| 143 | if (!power_on) | ||
| 144 | return menelaus_set_vmmc(0); | ||
| 145 | switch (1 << vdd) { | ||
| 146 | case MMC_VDD_33_34: | ||
| 147 | case MMC_VDD_32_33: | ||
| 148 | case MMC_VDD_31_32: | ||
| 149 | mV = 3100; | ||
| 150 | break; | ||
| 151 | case MMC_VDD_30_31: | ||
| 152 | mV = 3000; | ||
| 153 | break; | ||
| 154 | case MMC_VDD_28_29: | ||
| 155 | mV = 2800; | ||
| 156 | break; | ||
| 157 | case MMC_VDD_165_195: | ||
| 158 | mV = 1850; | ||
| 159 | break; | ||
| 160 | default: | ||
| 161 | BUG(); | ||
| 162 | } | ||
| 163 | return menelaus_set_vmmc(mV); | ||
| 164 | } else { | ||
| 165 | if (!power_on) | ||
| 166 | return menelaus_set_vdcdc(3, 0); | ||
| 167 | switch (1 << vdd) { | ||
| 168 | case MMC_VDD_33_34: | ||
| 169 | case MMC_VDD_32_33: | ||
| 170 | mV = 3300; | ||
| 171 | break; | ||
| 172 | case MMC_VDD_30_31: | ||
| 173 | case MMC_VDD_29_30: | ||
| 174 | mV = 3000; | ||
| 175 | break; | ||
| 176 | case MMC_VDD_28_29: | ||
| 177 | case MMC_VDD_27_28: | ||
| 178 | mV = 2800; | ||
| 179 | break; | ||
| 180 | case MMC_VDD_24_25: | ||
| 181 | case MMC_VDD_23_24: | ||
| 182 | mV = 2400; | ||
| 183 | break; | ||
| 184 | case MMC_VDD_22_23: | ||
| 185 | case MMC_VDD_21_22: | ||
| 186 | mV = 2200; | ||
| 187 | break; | ||
| 188 | case MMC_VDD_20_21: | ||
| 189 | mV = 2000; | ||
| 190 | break; | ||
| 191 | case MMC_VDD_165_195: | ||
| 192 | mV = 1800; | ||
| 193 | break; | ||
| 194 | default: | ||
| 195 | BUG(); | ||
| 196 | } | ||
| 197 | return menelaus_set_vdcdc(3, mV); | ||
| 198 | } | ||
| 199 | return 0; | ||
| 200 | } | ||
| 201 | |||
| 202 | static void n810_set_power_emmc(struct device *dev, | ||
| 203 | int power_on) | ||
| 204 | { | ||
| 205 | dev_dbg(dev, "Set EMMC power %s\n", power_on ? "on" : "off"); | ||
| 206 | |||
| 207 | if (power_on) { | ||
| 208 | gpio_set_value(N810_EMMC_VSD_GPIO, 1); | ||
| 209 | msleep(1); | ||
| 210 | gpio_set_value(NN810_EMMC_VIO_GPIO, 1); | ||
| 211 | msleep(1); | ||
| 212 | } else { | ||
| 213 | gpio_set_value(NN810_EMMC_VIO_GPIO, 0); | ||
| 214 | msleep(50); | ||
| 215 | gpio_set_value(N810_EMMC_VSD_GPIO, 0); | ||
| 216 | msleep(50); | ||
| 217 | } | ||
| 218 | } | ||
| 219 | |||
| 220 | static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on, | ||
| 221 | int vdd) | ||
| 222 | { | ||
| 223 | if (machine_is_nokia_n800() || slot == 0) | ||
| 224 | return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd); | ||
| 225 | |||
| 226 | n810_set_power_emmc(dev, power_on); | ||
| 227 | |||
| 228 | return 0; | ||
| 229 | } | ||
| 230 | |||
| 231 | static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) | ||
| 232 | { | ||
| 233 | int r; | ||
| 234 | |||
| 235 | dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1, | ||
| 236 | bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); | ||
| 237 | BUG_ON(slot != 0 && slot != 1); | ||
| 238 | slot++; | ||
| 239 | switch (bus_mode) { | ||
| 240 | case MMC_BUSMODE_OPENDRAIN: | ||
| 241 | r = menelaus_set_mmc_opendrain(slot, 1); | ||
| 242 | break; | ||
| 243 | case MMC_BUSMODE_PUSHPULL: | ||
| 244 | r = menelaus_set_mmc_opendrain(slot, 0); | ||
| 245 | break; | ||
| 246 | default: | ||
| 247 | BUG(); | ||
| 248 | } | ||
| 249 | if (r != 0 && printk_ratelimit()) | ||
| 250 | dev_err(dev, "MMC: unable to set bus mode for slot %d\n", | ||
| 251 | slot); | ||
| 252 | return r; | ||
| 253 | } | ||
| 254 | |||
| 255 | static int n8x0_mmc_get_cover_state(struct device *dev, int slot) | ||
| 256 | { | ||
| 257 | slot++; | ||
| 258 | BUG_ON(slot != 1 && slot != 2); | ||
| 259 | if (slot == 1) | ||
| 260 | return slot1_cover_open; | ||
| 261 | else | ||
| 262 | return slot2_cover_open; | ||
| 263 | } | ||
| 264 | |||
| 265 | static void n8x0_mmc_callback(void *data, u8 card_mask) | ||
| 266 | { | ||
| 267 | int bit, *openp, index; | ||
| 268 | |||
| 269 | if (machine_is_nokia_n800()) { | ||
| 270 | bit = 1 << 1; | ||
| 271 | openp = &slot2_cover_open; | ||
| 272 | index = 1; | ||
| 273 | } else { | ||
| 274 | bit = 1; | ||
| 275 | openp = &slot1_cover_open; | ||
| 276 | index = 0; | ||
| 277 | } | ||
| 278 | |||
| 279 | if (card_mask & bit) | ||
| 280 | *openp = 1; | ||
| 281 | else | ||
| 282 | *openp = 0; | ||
| 283 | |||
| 284 | omap_mmc_notify_cover_event(mmc_device, index, *openp); | ||
| 285 | } | ||
| 286 | |||
| 287 | void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state) | ||
| 288 | { | ||
| 289 | if (mmc_device == NULL) | ||
| 290 | return; | ||
| 291 | |||
| 292 | slot1_cover_open = !closed_state; | ||
| 293 | omap_mmc_notify_cover_event(mmc_device, 0, closed_state); | ||
| 294 | } | ||
| 295 | |||
| 296 | static int n8x0_mmc_late_init(struct device *dev) | ||
| 297 | { | ||
| 298 | int r, bit, *openp; | ||
| 299 | int vs2sel; | ||
| 300 | |||
| 301 | mmc_device = dev; | ||
| 302 | |||
| 303 | r = menelaus_set_slot_sel(1); | ||
| 304 | if (r < 0) | ||
| 305 | return r; | ||
| 306 | |||
| 307 | if (machine_is_nokia_n800()) | ||
| 308 | vs2sel = 0; | ||
| 309 | else | ||
| 310 | vs2sel = 2; | ||
| 311 | |||
| 312 | r = menelaus_set_mmc_slot(2, 0, vs2sel, 1); | ||
| 313 | if (r < 0) | ||
| 314 | return r; | ||
| 315 | |||
| 316 | n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */ | ||
| 317 | n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16); | ||
| 318 | |||
| 319 | r = menelaus_set_mmc_slot(1, 1, 0, 1); | ||
| 320 | if (r < 0) | ||
| 321 | return r; | ||
| 322 | r = menelaus_set_mmc_slot(2, 1, vs2sel, 1); | ||
| 323 | if (r < 0) | ||
| 324 | return r; | ||
| 325 | |||
| 326 | r = menelaus_get_slot_pin_states(); | ||
| 327 | if (r < 0) | ||
| 328 | return r; | ||
| 329 | |||
| 330 | if (machine_is_nokia_n800()) { | ||
| 331 | bit = 1 << 1; | ||
| 332 | openp = &slot2_cover_open; | ||
| 333 | } else { | ||
| 334 | bit = 1; | ||
| 335 | openp = &slot1_cover_open; | ||
| 336 | slot2_cover_open = 0; | ||
| 337 | } | ||
| 338 | |||
| 339 | /* All slot pin bits seem to be inversed until first switch change */ | ||
| 340 | if (r == 0xf || r == (0xf & ~bit)) | ||
| 341 | r = ~r; | ||
| 342 | |||
| 343 | if (r & bit) | ||
| 344 | *openp = 1; | ||
| 345 | else | ||
| 346 | *openp = 0; | ||
| 347 | |||
| 348 | r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL); | ||
| 349 | |||
| 350 | return r; | ||
| 351 | } | ||
| 352 | |||
| 353 | static void n8x0_mmc_shutdown(struct device *dev) | ||
| 354 | { | ||
| 355 | int vs2sel; | ||
| 356 | |||
| 357 | if (machine_is_nokia_n800()) | ||
| 358 | vs2sel = 0; | ||
| 359 | else | ||
| 360 | vs2sel = 2; | ||
| 361 | |||
| 362 | menelaus_set_mmc_slot(1, 0, 0, 0); | ||
| 363 | menelaus_set_mmc_slot(2, 0, vs2sel, 0); | ||
| 364 | } | ||
| 365 | |||
| 366 | static void n8x0_mmc_cleanup(struct device *dev) | ||
| 367 | { | ||
| 368 | menelaus_unregister_mmc_callback(); | ||
| 369 | |||
| 370 | gpio_free(N8X0_SLOT_SWITCH_GPIO); | ||
| 371 | |||
| 372 | if (machine_is_nokia_n810()) { | ||
| 373 | gpio_free(N810_EMMC_VSD_GPIO); | ||
| 374 | gpio_free(NN810_EMMC_VIO_GPIO); | ||
| 375 | } | ||
| 376 | } | ||
| 377 | |||
| 378 | /* | ||
| 379 | * MMC controller1 has two slots that are multiplexed via I2C. | ||
| 380 | * MMC controller2 is not in use. | ||
| 381 | */ | ||
| 382 | static struct omap_mmc_platform_data mmc1_data = { | ||
| 383 | .nr_slots = 2, | ||
| 384 | .switch_slot = n8x0_mmc_switch_slot, | ||
| 385 | .init = n8x0_mmc_late_init, | ||
| 386 | .cleanup = n8x0_mmc_cleanup, | ||
| 387 | .shutdown = n8x0_mmc_shutdown, | ||
| 388 | .max_freq = 24000000, | ||
| 389 | .dma_mask = 0xffffffff, | ||
| 390 | .slots[0] = { | ||
| 391 | .wires = 4, | ||
| 392 | .set_power = n8x0_mmc_set_power, | ||
| 393 | .set_bus_mode = n8x0_mmc_set_bus_mode, | ||
| 394 | .get_cover_state = n8x0_mmc_get_cover_state, | ||
| 395 | .ocr_mask = MMC_VDD_165_195 | MMC_VDD_30_31 | | ||
| 396 | MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 397 | .name = "internal", | ||
| 398 | }, | ||
| 399 | .slots[1] = { | ||
| 400 | .set_power = n8x0_mmc_set_power, | ||
| 401 | .set_bus_mode = n8x0_mmc_set_bus_mode, | ||
| 402 | .get_cover_state = n8x0_mmc_get_cover_state, | ||
| 403 | .ocr_mask = MMC_VDD_165_195 | MMC_VDD_20_21 | | ||
| 404 | MMC_VDD_21_22 | MMC_VDD_22_23 | | ||
| 405 | MMC_VDD_23_24 | MMC_VDD_24_25 | | ||
| 406 | MMC_VDD_27_28 | MMC_VDD_28_29 | | ||
| 407 | MMC_VDD_29_30 | MMC_VDD_30_31 | | ||
| 408 | MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 409 | .name = "external", | ||
| 410 | }, | ||
| 411 | }; | ||
| 412 | |||
| 413 | static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC]; | ||
| 414 | |||
| 415 | void __init n8x0_mmc_init(void) | ||
| 416 | |||
| 417 | { | ||
| 418 | int err; | ||
| 419 | |||
| 420 | if (machine_is_nokia_n810()) { | ||
| 421 | mmc1_data.slots[0].name = "external"; | ||
| 422 | |||
| 423 | /* | ||
| 424 | * Some Samsung Movinand chips do not like open-ended | ||
| 425 | * multi-block reads and fall to braind-dead state | ||
| 426 | * while doing so. Reducing the number of blocks in | ||
| 427 | * the transfer or delays in clock disable do not help | ||
| 428 | */ | ||
| 429 | mmc1_data.slots[1].name = "internal"; | ||
| 430 | mmc1_data.slots[1].ban_openended = 1; | ||
| 431 | } | ||
| 432 | |||
| 433 | err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch"); | ||
| 434 | if (err) | ||
| 435 | return err; | ||
| 436 | |||
| 437 | gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0); | ||
| 438 | |||
| 439 | if (machine_is_nokia_n810()) { | ||
| 440 | err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf"); | ||
| 441 | if (err) { | ||
| 442 | gpio_free(N8X0_SLOT_SWITCH_GPIO); | ||
| 443 | return err; | ||
| 444 | } | ||
| 445 | gpio_direction_output(N810_EMMC_VSD_GPIO, 0); | ||
| 446 | |||
| 447 | err = gpio_request(NN810_EMMC_VIO_GPIO, "MMC slot 2 Vdd"); | ||
| 448 | if (err) { | ||
| 449 | gpio_free(N8X0_SLOT_SWITCH_GPIO); | ||
| 450 | gpio_free(N810_EMMC_VSD_GPIO); | ||
| 451 | return err; | ||
| 452 | } | ||
| 453 | gpio_direction_output(NN810_EMMC_VIO_GPIO, 0); | ||
| 454 | } | ||
| 455 | |||
| 456 | mmc_data[0] = &mmc1_data; | ||
| 457 | omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); | ||
| 458 | } | ||
| 459 | #else | ||
| 460 | |||
| 461 | void __init n8x0_mmc_init(void) | ||
| 462 | { | ||
| 463 | } | ||
| 464 | |||
| 465 | void n8x0_mmc_slot1_cover_handler(void *arg, int state) | ||
| 466 | { | ||
| 467 | } | ||
| 468 | |||
| 469 | #endif /* CONFIG_MMC_OMAP */ | ||
| 470 | |||
| 471 | #ifdef CONFIG_MENELAUS | ||
| 472 | |||
| 473 | static int n8x0_auto_sleep_regulators(void) | ||
| 474 | { | ||
| 475 | u32 val; | ||
| 476 | int ret; | ||
| 477 | |||
| 478 | val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \ | ||
| 479 | | EN_VAUX_SLEEP | EN_VIO_SLEEP \ | ||
| 480 | | EN_VMEM_SLEEP | EN_DC3_SLEEP \ | ||
| 481 | | EN_VC_SLEEP | EN_DC2_SLEEP; | ||
| 482 | |||
| 483 | ret = menelaus_set_regulator_sleep(1, val); | ||
| 484 | if (ret < 0) { | ||
| 485 | printk(KERN_ERR "Could not set regulators to sleep on " | ||
| 486 | "menelaus: %u\n", ret); | ||
| 487 | return ret; | ||
| 488 | } | ||
| 489 | return 0; | ||
| 490 | } | ||
| 491 | |||
| 492 | static int n8x0_auto_voltage_scale(void) | ||
| 493 | { | ||
| 494 | int ret; | ||
| 495 | |||
| 496 | ret = menelaus_set_vcore_hw(1400, 1050); | ||
| 497 | if (ret < 0) { | ||
| 498 | printk(KERN_ERR "Could not set VCORE voltage on " | ||
| 499 | "menelaus: %u\n", ret); | ||
| 500 | return ret; | ||
| 501 | } | ||
| 502 | return 0; | ||
| 503 | } | ||
| 504 | |||
| 505 | static int n8x0_menelaus_late_init(struct device *dev) | ||
| 506 | { | ||
| 507 | int ret; | ||
| 508 | |||
| 509 | ret = n8x0_auto_voltage_scale(); | ||
| 510 | if (ret < 0) | ||
| 511 | return ret; | ||
| 512 | ret = n8x0_auto_sleep_regulators(); | ||
| 513 | if (ret < 0) | ||
| 514 | return ret; | ||
| 515 | return 0; | ||
| 516 | } | ||
| 517 | |||
| 518 | static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { | ||
| 519 | { | ||
| 520 | I2C_BOARD_INFO("menelaus", 0x72), | ||
| 521 | .irq = INT_24XX_SYS_NIRQ, | ||
| 522 | }, | ||
| 523 | }; | ||
| 524 | |||
| 525 | static struct menelaus_platform_data n8x0_menelaus_platform_data = { | ||
| 526 | .late_init = n8x0_menelaus_late_init, | ||
| 527 | }; | ||
| 528 | |||
| 529 | static void __init n8x0_menelaus_init(void) | ||
| 530 | { | ||
| 531 | n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; | ||
| 532 | omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, | ||
| 533 | ARRAY_SIZE(n8x0_i2c_board_info_1)); | ||
| 534 | } | ||
| 535 | |||
| 536 | #else | ||
| 537 | static inline void __init n8x0_menelaus_init(void) | ||
| 538 | { | ||
| 539 | } | ||
| 540 | #endif | ||
| 541 | |||
| 99 | static void __init n8x0_map_io(void) | 542 | static void __init n8x0_map_io(void) |
| 100 | { | 543 | { |
| 101 | omap2_set_globals_242x(); | 544 | omap2_set_globals_242x(); |
| 102 | omap2_map_common_io(); | 545 | omap242x_map_common_io(); |
| 103 | } | 546 | } |
| 104 | 547 | ||
| 105 | static void __init n8x0_init_irq(void) | 548 | static void __init n8x0_init_irq(void) |
| @@ -116,7 +559,9 @@ static void __init n8x0_init_machine(void) | |||
| 116 | ARRAY_SIZE(n800_spi_board_info)); | 559 | ARRAY_SIZE(n800_spi_board_info)); |
| 117 | 560 | ||
| 118 | omap_serial_init(); | 561 | omap_serial_init(); |
| 562 | n8x0_menelaus_init(); | ||
| 119 | n8x0_onenand_init(); | 563 | n8x0_onenand_init(); |
| 564 | n8x0_mmc_init(); | ||
| 120 | } | 565 | } |
| 121 | 566 | ||
| 122 | MACHINE_START(NOKIA_N800, "Nokia N800") | 567 | MACHINE_START(NOKIA_N800, "Nokia N800") |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 231cb4ec1847..6eb77e1f7c82 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -45,7 +45,7 @@ | |||
| 45 | #include <plat/timer-gp.h> | 45 | #include <plat/timer-gp.h> |
| 46 | 46 | ||
| 47 | #include "mux.h" | 47 | #include "mux.h" |
| 48 | #include "mmc-twl4030.h" | 48 | #include "hsmmc.h" |
| 49 | 49 | ||
| 50 | #define GPMC_CS0_BASE 0x60 | 50 | #define GPMC_CS0_BASE 0x60 |
| 51 | #define GPMC_CS_SIZE 0x30 | 51 | #define GPMC_CS_SIZE 0x30 |
| @@ -108,7 +108,7 @@ static struct platform_device omap3beagle_nand_device = { | |||
| 108 | 108 | ||
| 109 | #include "sdram-micron-mt46h32m32lf-6.h" | 109 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 110 | 110 | ||
| 111 | static struct twl4030_hsmmc_info mmc[] = { | 111 | static struct omap2_hsmmc_info mmc[] = { |
| 112 | { | 112 | { |
| 113 | .mmc = 1, | 113 | .mmc = 1, |
| 114 | .wires = 8, | 114 | .wires = 8, |
| @@ -147,7 +147,7 @@ static int beagle_twl_gpio_setup(struct device *dev, | |||
| 147 | } | 147 | } |
| 148 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 148 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 149 | mmc[0].gpio_cd = gpio + 0; | 149 | mmc[0].gpio_cd = gpio + 0; |
| 150 | twl4030_mmc_init(mmc); | 150 | omap2_hsmmc_init(mmc); |
| 151 | 151 | ||
| 152 | /* link regulators to MMC adapters */ | 152 | /* link regulators to MMC adapters */ |
| 153 | beagle_vmmc1_supply.dev = mmc[0].dev; | 153 | beagle_vmmc1_supply.dev = mmc[0].dev; |
| @@ -430,6 +430,12 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 430 | #define board_mux NULL | 430 | #define board_mux NULL |
| 431 | #endif | 431 | #endif |
| 432 | 432 | ||
| 433 | static struct omap_musb_board_data musb_board_data = { | ||
| 434 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 435 | .mode = MUSB_OTG, | ||
| 436 | .power = 100, | ||
| 437 | }; | ||
| 438 | |||
| 433 | static void __init omap3_beagle_init(void) | 439 | static void __init omap3_beagle_init(void) |
| 434 | { | 440 | { |
| 435 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 441 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| @@ -443,7 +449,7 @@ static void __init omap3_beagle_init(void) | |||
| 443 | /* REVISIT leave DVI powered down until it's needed ... */ | 449 | /* REVISIT leave DVI powered down until it's needed ... */ |
| 444 | gpio_direction_output(170, true); | 450 | gpio_direction_output(170, true); |
| 445 | 451 | ||
| 446 | usb_musb_init(); | 452 | usb_musb_init(&musb_board_data); |
| 447 | usb_ehci_init(&ehci_pdata); | 453 | usb_ehci_init(&ehci_pdata); |
| 448 | omap3beagle_flash_init(); | 454 | omap3beagle_flash_init(); |
| 449 | 455 | ||
| @@ -455,7 +461,7 @@ static void __init omap3_beagle_init(void) | |||
| 455 | static void __init omap3_beagle_map_io(void) | 461 | static void __init omap3_beagle_map_io(void) |
| 456 | { | 462 | { |
| 457 | omap2_set_globals_343x(); | 463 | omap2_set_globals_343x(); |
| 458 | omap2_map_common_io(); | 464 | omap34xx_map_common_io(); |
| 459 | } | 465 | } |
| 460 | 466 | ||
| 461 | MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") | 467 | MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 34de17851572..d6bc88c426b5 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
| @@ -41,10 +41,11 @@ | |||
| 41 | #include <plat/usb.h> | 41 | #include <plat/usb.h> |
| 42 | #include <plat/common.h> | 42 | #include <plat/common.h> |
| 43 | #include <plat/mcspi.h> | 43 | #include <plat/mcspi.h> |
| 44 | #include <plat/display.h> | ||
| 44 | 45 | ||
| 45 | #include "mux.h" | 46 | #include "mux.h" |
| 46 | #include "sdram-micron-mt46h32m32lf-6.h" | 47 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 47 | #include "mmc-twl4030.h" | 48 | #include "hsmmc.h" |
| 48 | 49 | ||
| 49 | #define OMAP3_EVM_TS_GPIO 175 | 50 | #define OMAP3_EVM_TS_GPIO 175 |
| 50 | #define OMAP3_EVM_EHCI_VBUS 22 | 51 | #define OMAP3_EVM_EHCI_VBUS 22 |
| @@ -147,6 +148,187 @@ static inline void __init omap3evm_init_smsc911x(void) | |||
| 147 | static inline void __init omap3evm_init_smsc911x(void) { return; } | 148 | static inline void __init omap3evm_init_smsc911x(void) { return; } |
| 148 | #endif | 149 | #endif |
| 149 | 150 | ||
| 151 | /* | ||
| 152 | * OMAP3EVM LCD Panel control signals | ||
| 153 | */ | ||
| 154 | #define OMAP3EVM_LCD_PANEL_LR 2 | ||
| 155 | #define OMAP3EVM_LCD_PANEL_UD 3 | ||
| 156 | #define OMAP3EVM_LCD_PANEL_INI 152 | ||
| 157 | #define OMAP3EVM_LCD_PANEL_ENVDD 153 | ||
| 158 | #define OMAP3EVM_LCD_PANEL_QVGA 154 | ||
| 159 | #define OMAP3EVM_LCD_PANEL_RESB 155 | ||
| 160 | #define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 | ||
| 161 | #define OMAP3EVM_DVI_PANEL_EN_GPIO 199 | ||
| 162 | |||
| 163 | static int lcd_enabled; | ||
| 164 | static int dvi_enabled; | ||
| 165 | |||
| 166 | static void __init omap3_evm_display_init(void) | ||
| 167 | { | ||
| 168 | int r; | ||
| 169 | |||
| 170 | r = gpio_request(OMAP3EVM_LCD_PANEL_RESB, "lcd_panel_resb"); | ||
| 171 | if (r) { | ||
| 172 | printk(KERN_ERR "failed to get lcd_panel_resb\n"); | ||
| 173 | return; | ||
| 174 | } | ||
| 175 | gpio_direction_output(OMAP3EVM_LCD_PANEL_RESB, 1); | ||
| 176 | |||
| 177 | r = gpio_request(OMAP3EVM_LCD_PANEL_INI, "lcd_panel_ini"); | ||
| 178 | if (r) { | ||
| 179 | printk(KERN_ERR "failed to get lcd_panel_ini\n"); | ||
| 180 | goto err_1; | ||
| 181 | } | ||
| 182 | gpio_direction_output(OMAP3EVM_LCD_PANEL_INI, 1); | ||
| 183 | |||
| 184 | r = gpio_request(OMAP3EVM_LCD_PANEL_QVGA, "lcd_panel_qvga"); | ||
| 185 | if (r) { | ||
| 186 | printk(KERN_ERR "failed to get lcd_panel_qvga\n"); | ||
| 187 | goto err_2; | ||
| 188 | } | ||
| 189 | gpio_direction_output(OMAP3EVM_LCD_PANEL_QVGA, 0); | ||
| 190 | |||
| 191 | r = gpio_request(OMAP3EVM_LCD_PANEL_LR, "lcd_panel_lr"); | ||
| 192 | if (r) { | ||
| 193 | printk(KERN_ERR "failed to get lcd_panel_lr\n"); | ||
| 194 | goto err_3; | ||
| 195 | } | ||
| 196 | gpio_direction_output(OMAP3EVM_LCD_PANEL_LR, 1); | ||
| 197 | |||
| 198 | r = gpio_request(OMAP3EVM_LCD_PANEL_UD, "lcd_panel_ud"); | ||
| 199 | if (r) { | ||
| 200 | printk(KERN_ERR "failed to get lcd_panel_ud\n"); | ||
| 201 | goto err_4; | ||
| 202 | } | ||
| 203 | gpio_direction_output(OMAP3EVM_LCD_PANEL_UD, 1); | ||
| 204 | |||
| 205 | r = gpio_request(OMAP3EVM_LCD_PANEL_ENVDD, "lcd_panel_envdd"); | ||
| 206 | if (r) { | ||
| 207 | printk(KERN_ERR "failed to get lcd_panel_envdd\n"); | ||
| 208 | goto err_5; | ||
| 209 | } | ||
| 210 | gpio_direction_output(OMAP3EVM_LCD_PANEL_ENVDD, 0); | ||
| 211 | |||
| 212 | return; | ||
| 213 | |||
| 214 | err_5: | ||
| 215 | gpio_free(OMAP3EVM_LCD_PANEL_UD); | ||
| 216 | err_4: | ||
| 217 | gpio_free(OMAP3EVM_LCD_PANEL_LR); | ||
| 218 | err_3: | ||
| 219 | gpio_free(OMAP3EVM_LCD_PANEL_QVGA); | ||
| 220 | err_2: | ||
| 221 | gpio_free(OMAP3EVM_LCD_PANEL_INI); | ||
| 222 | err_1: | ||
| 223 | gpio_free(OMAP3EVM_LCD_PANEL_RESB); | ||
| 224 | |||
| 225 | } | ||
| 226 | |||
| 227 | static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev) | ||
| 228 | { | ||
| 229 | if (dvi_enabled) { | ||
| 230 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | ||
| 231 | return -EINVAL; | ||
| 232 | } | ||
| 233 | gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); | ||
| 234 | |||
| 235 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) | ||
| 236 | gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); | ||
| 237 | else | ||
| 238 | gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); | ||
| 239 | |||
| 240 | lcd_enabled = 1; | ||
| 241 | return 0; | ||
| 242 | } | ||
| 243 | |||
| 244 | static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev) | ||
| 245 | { | ||
| 246 | gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); | ||
| 247 | |||
| 248 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) | ||
| 249 | gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); | ||
| 250 | else | ||
| 251 | gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); | ||
| 252 | |||
| 253 | lcd_enabled = 0; | ||
| 254 | } | ||
| 255 | |||
| 256 | static struct omap_dss_device omap3_evm_lcd_device = { | ||
| 257 | .name = "lcd", | ||
| 258 | .driver_name = "sharp_ls_panel", | ||
| 259 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 260 | .phy.dpi.data_lines = 18, | ||
| 261 | .platform_enable = omap3_evm_enable_lcd, | ||
| 262 | .platform_disable = omap3_evm_disable_lcd, | ||
| 263 | }; | ||
| 264 | |||
| 265 | static int omap3_evm_enable_tv(struct omap_dss_device *dssdev) | ||
| 266 | { | ||
| 267 | return 0; | ||
| 268 | } | ||
| 269 | |||
| 270 | static void omap3_evm_disable_tv(struct omap_dss_device *dssdev) | ||
| 271 | { | ||
| 272 | } | ||
| 273 | |||
| 274 | static struct omap_dss_device omap3_evm_tv_device = { | ||
| 275 | .name = "tv", | ||
| 276 | .driver_name = "venc", | ||
| 277 | .type = OMAP_DISPLAY_TYPE_VENC, | ||
| 278 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | ||
| 279 | .platform_enable = omap3_evm_enable_tv, | ||
| 280 | .platform_disable = omap3_evm_disable_tv, | ||
| 281 | }; | ||
| 282 | |||
| 283 | static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) | ||
| 284 | { | ||
| 285 | if (lcd_enabled) { | ||
| 286 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | ||
| 287 | return -EINVAL; | ||
| 288 | } | ||
| 289 | |||
| 290 | gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); | ||
| 291 | |||
| 292 | dvi_enabled = 1; | ||
| 293 | return 0; | ||
| 294 | } | ||
| 295 | |||
| 296 | static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) | ||
| 297 | { | ||
| 298 | gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); | ||
| 299 | |||
| 300 | dvi_enabled = 0; | ||
| 301 | } | ||
| 302 | |||
| 303 | static struct omap_dss_device omap3_evm_dvi_device = { | ||
| 304 | .name = "dvi", | ||
| 305 | .driver_name = "generic_panel", | ||
| 306 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 307 | .phy.dpi.data_lines = 24, | ||
| 308 | .platform_enable = omap3_evm_enable_dvi, | ||
| 309 | .platform_disable = omap3_evm_disable_dvi, | ||
| 310 | }; | ||
| 311 | |||
| 312 | static struct omap_dss_device *omap3_evm_dss_devices[] = { | ||
| 313 | &omap3_evm_lcd_device, | ||
| 314 | &omap3_evm_tv_device, | ||
| 315 | &omap3_evm_dvi_device, | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct omap_dss_board_info omap3_evm_dss_data = { | ||
| 319 | .num_devices = ARRAY_SIZE(omap3_evm_dss_devices), | ||
| 320 | .devices = omap3_evm_dss_devices, | ||
| 321 | .default_device = &omap3_evm_lcd_device, | ||
| 322 | }; | ||
| 323 | |||
| 324 | static struct platform_device omap3_evm_dss_device = { | ||
| 325 | .name = "omapdss", | ||
| 326 | .id = -1, | ||
| 327 | .dev = { | ||
| 328 | .platform_data = &omap3_evm_dss_data, | ||
| 329 | }, | ||
| 330 | }; | ||
| 331 | |||
| 150 | static struct regulator_consumer_supply omap3evm_vmmc1_supply = { | 332 | static struct regulator_consumer_supply omap3evm_vmmc1_supply = { |
| 151 | .supply = "vmmc", | 333 | .supply = "vmmc", |
| 152 | }; | 334 | }; |
| @@ -185,7 +367,7 @@ static struct regulator_init_data omap3evm_vsim = { | |||
| 185 | .consumer_supplies = &omap3evm_vsim_supply, | 367 | .consumer_supplies = &omap3evm_vsim_supply, |
| 186 | }; | 368 | }; |
| 187 | 369 | ||
| 188 | static struct twl4030_hsmmc_info mmc[] = { | 370 | static struct omap2_hsmmc_info mmc[] = { |
| 189 | { | 371 | { |
| 190 | .mmc = 1, | 372 | .mmc = 1, |
| 191 | .wires = 4, | 373 | .wires = 4, |
| @@ -225,7 +407,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev, | |||
| 225 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 407 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 226 | omap_mux_init_gpio(63, OMAP_PIN_INPUT); | 408 | omap_mux_init_gpio(63, OMAP_PIN_INPUT); |
| 227 | mmc[0].gpio_cd = gpio + 0; | 409 | mmc[0].gpio_cd = gpio + 0; |
| 228 | twl4030_mmc_init(mmc); | 410 | omap2_hsmmc_init(mmc); |
| 229 | 411 | ||
| 230 | /* link regulators to MMC adapters */ | 412 | /* link regulators to MMC adapters */ |
| 231 | omap3evm_vmmc1_supply.dev = mmc[0].dev; | 413 | omap3evm_vmmc1_supply.dev = mmc[0].dev; |
| @@ -236,6 +418,14 @@ static int omap3evm_twl_gpio_setup(struct device *dev, | |||
| 236 | * the P2 connector; notably LEDA for the LCD backlight. | 418 | * the P2 connector; notably LEDA for the LCD backlight. |
| 237 | */ | 419 | */ |
| 238 | 420 | ||
| 421 | /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ | ||
| 422 | gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); | ||
| 423 | gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); | ||
| 424 | |||
| 425 | /* gpio + 7 == DVI Enable */ | ||
| 426 | gpio_request(gpio + 7, "EN_DVI"); | ||
| 427 | gpio_direction_output(gpio + 7, 0); | ||
| 428 | |||
| 239 | /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ | 429 | /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ |
| 240 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; | 430 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; |
| 241 | 431 | ||
| @@ -258,20 +448,23 @@ static struct twl4030_usb_data omap3evm_usb_data = { | |||
| 258 | 448 | ||
| 259 | static int board_keymap[] = { | 449 | static int board_keymap[] = { |
| 260 | KEY(0, 0, KEY_LEFT), | 450 | KEY(0, 0, KEY_LEFT), |
| 261 | KEY(0, 1, KEY_RIGHT), | 451 | KEY(0, 1, KEY_DOWN), |
| 262 | KEY(0, 2, KEY_A), | 452 | KEY(0, 2, KEY_ENTER), |
| 263 | KEY(0, 3, KEY_B), | 453 | KEY(0, 3, KEY_M), |
| 264 | KEY(1, 0, KEY_DOWN), | 454 | |
| 455 | KEY(1, 0, KEY_RIGHT), | ||
| 265 | KEY(1, 1, KEY_UP), | 456 | KEY(1, 1, KEY_UP), |
| 266 | KEY(1, 2, KEY_E), | 457 | KEY(1, 2, KEY_I), |
| 267 | KEY(1, 3, KEY_F), | 458 | KEY(1, 3, KEY_N), |
| 268 | KEY(2, 0, KEY_ENTER), | 459 | |
| 269 | KEY(2, 1, KEY_I), | 460 | KEY(2, 0, KEY_A), |
| 461 | KEY(2, 1, KEY_E), | ||
| 270 | KEY(2, 2, KEY_J), | 462 | KEY(2, 2, KEY_J), |
| 271 | KEY(2, 3, KEY_K), | 463 | KEY(2, 3, KEY_O), |
| 272 | KEY(3, 0, KEY_M), | 464 | |
| 273 | KEY(3, 1, KEY_N), | 465 | KEY(3, 0, KEY_B), |
| 274 | KEY(3, 2, KEY_O), | 466 | KEY(3, 1, KEY_F), |
| 467 | KEY(3, 2, KEY_K), | ||
| 275 | KEY(3, 3, KEY_P) | 468 | KEY(3, 3, KEY_P) |
| 276 | }; | 469 | }; |
| 277 | 470 | ||
| @@ -300,6 +493,47 @@ static struct twl4030_codec_data omap3evm_codec_data = { | |||
| 300 | .audio = &omap3evm_audio_data, | 493 | .audio = &omap3evm_audio_data, |
| 301 | }; | 494 | }; |
| 302 | 495 | ||
| 496 | static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { | ||
| 497 | .supply = "vdda_dac", | ||
| 498 | .dev = &omap3_evm_dss_device.dev, | ||
| 499 | }; | ||
| 500 | |||
| 501 | /* VDAC for DSS driving S-Video */ | ||
| 502 | static struct regulator_init_data omap3_evm_vdac = { | ||
| 503 | .constraints = { | ||
| 504 | .min_uV = 1800000, | ||
| 505 | .max_uV = 1800000, | ||
| 506 | .apply_uV = true, | ||
| 507 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 508 | | REGULATOR_MODE_STANDBY, | ||
| 509 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 510 | | REGULATOR_CHANGE_STATUS, | ||
| 511 | }, | ||
| 512 | .num_consumer_supplies = 1, | ||
| 513 | .consumer_supplies = &omap3_evm_vdda_dac_supply, | ||
| 514 | }; | ||
| 515 | |||
| 516 | /* VPLL2 for digital video outputs */ | ||
| 517 | static struct regulator_consumer_supply omap3_evm_vpll2_supply = { | ||
| 518 | .supply = "vdvi", | ||
| 519 | .dev = &omap3_evm_lcd_device.dev, | ||
| 520 | }; | ||
| 521 | |||
| 522 | static struct regulator_init_data omap3_evm_vpll2 = { | ||
| 523 | .constraints = { | ||
| 524 | .name = "VDVI", | ||
| 525 | .min_uV = 1800000, | ||
| 526 | .max_uV = 1800000, | ||
| 527 | .apply_uV = true, | ||
| 528 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 529 | | REGULATOR_MODE_STANDBY, | ||
| 530 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 531 | | REGULATOR_CHANGE_STATUS, | ||
| 532 | }, | ||
| 533 | .num_consumer_supplies = 1, | ||
| 534 | .consumer_supplies = &omap3_evm_vpll2_supply, | ||
| 535 | }; | ||
| 536 | |||
| 303 | static struct twl4030_platform_data omap3evm_twldata = { | 537 | static struct twl4030_platform_data omap3evm_twldata = { |
| 304 | .irq_base = TWL4030_IRQ_BASE, | 538 | .irq_base = TWL4030_IRQ_BASE, |
| 305 | .irq_end = TWL4030_IRQ_END, | 539 | .irq_end = TWL4030_IRQ_END, |
| @@ -310,6 +544,8 @@ static struct twl4030_platform_data omap3evm_twldata = { | |||
| 310 | .usb = &omap3evm_usb_data, | 544 | .usb = &omap3evm_usb_data, |
| 311 | .gpio = &omap3evm_gpio_data, | 545 | .gpio = &omap3evm_gpio_data, |
| 312 | .codec = &omap3evm_codec_data, | 546 | .codec = &omap3evm_codec_data, |
| 547 | .vdac = &omap3_evm_vdac, | ||
| 548 | .vpll2 = &omap3_evm_vpll2, | ||
| 313 | }; | 549 | }; |
| 314 | 550 | ||
| 315 | static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { | 551 | static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { |
| @@ -337,15 +573,6 @@ static int __init omap3_evm_i2c_init(void) | |||
| 337 | return 0; | 573 | return 0; |
| 338 | } | 574 | } |
| 339 | 575 | ||
| 340 | static struct platform_device omap3_evm_lcd_device = { | ||
| 341 | .name = "omap3evm_lcd", | ||
| 342 | .id = -1, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static struct omap_lcd_config omap3_evm_lcd_config __initdata = { | ||
| 346 | .ctrl_name = "internal", | ||
| 347 | }; | ||
| 348 | |||
| 349 | static void ads7846_dev_init(void) | 576 | static void ads7846_dev_init(void) |
| 350 | { | 577 | { |
| 351 | if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0) | 578 | if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0) |
| @@ -393,7 +620,6 @@ struct spi_board_info omap3evm_spi_board_info[] = { | |||
| 393 | }; | 620 | }; |
| 394 | 621 | ||
| 395 | static struct omap_board_config_kernel omap3_evm_config[] __initdata = { | 622 | static struct omap_board_config_kernel omap3_evm_config[] __initdata = { |
| 396 | { OMAP_TAG_LCD, &omap3_evm_lcd_config }, | ||
| 397 | }; | 623 | }; |
| 398 | 624 | ||
| 399 | static void __init omap3_evm_init_irq(void) | 625 | static void __init omap3_evm_init_irq(void) |
| @@ -406,7 +632,7 @@ static void __init omap3_evm_init_irq(void) | |||
| 406 | } | 632 | } |
| 407 | 633 | ||
| 408 | static struct platform_device *omap3_evm_devices[] __initdata = { | 634 | static struct platform_device *omap3_evm_devices[] __initdata = { |
| 409 | &omap3_evm_lcd_device, | 635 | &omap3_evm_dss_device, |
| 410 | }; | 636 | }; |
| 411 | 637 | ||
| 412 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 638 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
| @@ -424,12 +650,24 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 424 | 650 | ||
| 425 | #ifdef CONFIG_OMAP_MUX | 651 | #ifdef CONFIG_OMAP_MUX |
| 426 | static struct omap_board_mux board_mux[] __initdata = { | 652 | static struct omap_board_mux board_mux[] __initdata = { |
| 653 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | | ||
| 654 | OMAP_PIN_OFF_INPUT_PULLUP | | ||
| 655 | OMAP_PIN_OFF_WAKEUPENABLE), | ||
| 656 | OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | | ||
| 657 | OMAP_PIN_OFF_INPUT_PULLUP | | ||
| 658 | OMAP_PIN_OFF_WAKEUPENABLE), | ||
| 427 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 659 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 428 | }; | 660 | }; |
| 429 | #else | 661 | #else |
| 430 | #define board_mux NULL | 662 | #define board_mux NULL |
| 431 | #endif | 663 | #endif |
| 432 | 664 | ||
| 665 | static struct omap_musb_board_data musb_board_data = { | ||
| 666 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 667 | .mode = MUSB_OTG, | ||
| 668 | .power = 100, | ||
| 669 | }; | ||
| 670 | |||
| 433 | static void __init omap3_evm_init(void) | 671 | static void __init omap3_evm_init(void) |
| 434 | { | 672 | { |
| 435 | omap3_evm_get_revision(); | 673 | omap3_evm_get_revision(); |
| @@ -443,10 +681,10 @@ static void __init omap3_evm_init(void) | |||
| 443 | ARRAY_SIZE(omap3evm_spi_board_info)); | 681 | ARRAY_SIZE(omap3evm_spi_board_info)); |
| 444 | 682 | ||
| 445 | omap_serial_init(); | 683 | omap_serial_init(); |
| 446 | #ifdef CONFIG_NOP_USB_XCEIV | 684 | |
| 447 | /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */ | 685 | /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */ |
| 448 | usb_nop_xceiv_register(); | 686 | usb_nop_xceiv_register(); |
| 449 | #endif | 687 | |
| 450 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { | 688 | if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { |
| 451 | /* enable EHCI VBUS using GPIO22 */ | 689 | /* enable EHCI VBUS using GPIO22 */ |
| 452 | omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP); | 690 | omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP); |
| @@ -469,16 +707,17 @@ static void __init omap3_evm_init(void) | |||
| 469 | omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); | 707 | omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); |
| 470 | ehci_pdata.reset_gpio_port[1] = 135; | 708 | ehci_pdata.reset_gpio_port[1] = 135; |
| 471 | } | 709 | } |
| 472 | usb_musb_init(); | 710 | usb_musb_init(&musb_board_data); |
| 473 | usb_ehci_init(&ehci_pdata); | 711 | usb_ehci_init(&ehci_pdata); |
| 474 | ads7846_dev_init(); | 712 | ads7846_dev_init(); |
| 475 | omap3evm_init_smsc911x(); | 713 | omap3evm_init_smsc911x(); |
| 714 | omap3_evm_display_init(); | ||
| 476 | } | 715 | } |
| 477 | 716 | ||
| 478 | static void __init omap3_evm_map_io(void) | 717 | static void __init omap3_evm_map_io(void) |
| 479 | { | 718 | { |
| 480 | omap2_set_globals_343x(); | 719 | omap2_set_globals_343x(); |
| 481 | omap2_map_common_io(); | 720 | omap34xx_map_common_io(); |
| 482 | } | 721 | } |
| 483 | 722 | ||
| 484 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") | 723 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index ef17cf1ab6d7..4827f4658df3 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -40,10 +40,11 @@ | |||
| 40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
| 41 | #include <plat/mcspi.h> | 41 | #include <plat/mcspi.h> |
| 42 | #include <plat/usb.h> | 42 | #include <plat/usb.h> |
| 43 | #include <plat/display.h> | ||
| 43 | 44 | ||
| 44 | #include "mux.h" | 45 | #include "mux.h" |
| 45 | #include "sdram-micron-mt46h32m32lf-6.h" | 46 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 46 | #include "mmc-twl4030.h" | 47 | #include "hsmmc.h" |
| 47 | 48 | ||
| 48 | #define OMAP3_PANDORA_TS_GPIO 94 | 49 | #define OMAP3_PANDORA_TS_GPIO 94 |
| 49 | 50 | ||
| @@ -192,7 +193,41 @@ static struct twl4030_keypad_data pandora_kp_data = { | |||
| 192 | .rep = 1, | 193 | .rep = 1, |
| 193 | }; | 194 | }; |
| 194 | 195 | ||
| 195 | static struct twl4030_hsmmc_info omap3pandora_mmc[] = { | 196 | static struct omap_dss_device pandora_lcd_device = { |
| 197 | .name = "lcd", | ||
| 198 | .driver_name = "tpo_td043mtea1_panel", | ||
| 199 | .type = OMAP_DISPLAY_TYPE_DPI, | ||
| 200 | .phy.dpi.data_lines = 24, | ||
| 201 | .reset_gpio = 157, | ||
| 202 | }; | ||
| 203 | |||
| 204 | static struct omap_dss_device pandora_tv_device = { | ||
| 205 | .name = "tv", | ||
| 206 | .driver_name = "venc", | ||
| 207 | .type = OMAP_DISPLAY_TYPE_VENC, | ||
| 208 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | ||
| 209 | }; | ||
| 210 | |||
| 211 | static struct omap_dss_device *pandora_dss_devices[] = { | ||
| 212 | &pandora_lcd_device, | ||
| 213 | &pandora_tv_device, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static struct omap_dss_board_info pandora_dss_data = { | ||
| 217 | .num_devices = ARRAY_SIZE(pandora_dss_devices), | ||
| 218 | .devices = pandora_dss_devices, | ||
| 219 | .default_device = &pandora_lcd_device, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static struct platform_device pandora_dss_device = { | ||
| 223 | .name = "omapdss", | ||
| 224 | .id = -1, | ||
| 225 | .dev = { | ||
| 226 | .platform_data = &pandora_dss_data, | ||
| 227 | }, | ||
| 228 | }; | ||
| 229 | |||
| 230 | static struct omap2_hsmmc_info omap3pandora_mmc[] = { | ||
| 196 | { | 231 | { |
| 197 | .mmc = 1, | 232 | .mmc = 1, |
| 198 | .wires = 4, | 233 | .wires = 4, |
| @@ -217,25 +252,13 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = { | |||
| 217 | {} /* Terminator */ | 252 | {} /* Terminator */ |
| 218 | }; | 253 | }; |
| 219 | 254 | ||
| 220 | static struct regulator_consumer_supply pandora_vmmc1_supply = { | ||
| 221 | .supply = "vmmc", | ||
| 222 | }; | ||
| 223 | |||
| 224 | static struct regulator_consumer_supply pandora_vmmc2_supply = { | ||
| 225 | .supply = "vmmc", | ||
| 226 | }; | ||
| 227 | |||
| 228 | static int omap3pandora_twl_gpio_setup(struct device *dev, | 255 | static int omap3pandora_twl_gpio_setup(struct device *dev, |
| 229 | unsigned gpio, unsigned ngpio) | 256 | unsigned gpio, unsigned ngpio) |
| 230 | { | 257 | { |
| 231 | /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ | 258 | /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ |
| 232 | omap3pandora_mmc[0].gpio_cd = gpio + 0; | 259 | omap3pandora_mmc[0].gpio_cd = gpio + 0; |
| 233 | omap3pandora_mmc[1].gpio_cd = gpio + 1; | 260 | omap3pandora_mmc[1].gpio_cd = gpio + 1; |
| 234 | twl4030_mmc_init(omap3pandora_mmc); | 261 | omap2_hsmmc_init(omap3pandora_mmc); |
| 235 | |||
| 236 | /* link regulators to MMC adapters */ | ||
| 237 | pandora_vmmc1_supply.dev = omap3pandora_mmc[0].dev; | ||
| 238 | pandora_vmmc2_supply.dev = omap3pandora_mmc[1].dev; | ||
| 239 | 262 | ||
| 240 | return 0; | 263 | return 0; |
| 241 | } | 264 | } |
| @@ -247,6 +270,36 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { | |||
| 247 | .setup = omap3pandora_twl_gpio_setup, | 270 | .setup = omap3pandora_twl_gpio_setup, |
| 248 | }; | 271 | }; |
| 249 | 272 | ||
| 273 | static struct regulator_consumer_supply pandora_vmmc1_supply = | ||
| 274 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); | ||
| 275 | |||
| 276 | static struct regulator_consumer_supply pandora_vmmc2_supply = | ||
| 277 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); | ||
| 278 | |||
| 279 | static struct regulator_consumer_supply pandora_vdda_dac_supply = | ||
| 280 | REGULATOR_SUPPLY("vdda_dac", "omapdss"); | ||
| 281 | |||
| 282 | static struct regulator_consumer_supply pandora_vdds_supplies[] = { | ||
| 283 | REGULATOR_SUPPLY("vdds_sdi", "omapdss"), | ||
| 284 | REGULATOR_SUPPLY("vdds_dsi", "omapdss"), | ||
| 285 | }; | ||
| 286 | |||
| 287 | static struct regulator_consumer_supply pandora_vcc_lcd_supply = | ||
| 288 | REGULATOR_SUPPLY("vcc", "display0"); | ||
| 289 | |||
| 290 | static struct regulator_consumer_supply pandora_usb_phy_supply = | ||
| 291 | REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"); | ||
| 292 | |||
| 293 | /* ads7846 on SPI and 2 nub controllers on I2C */ | ||
| 294 | static struct regulator_consumer_supply pandora_vaux4_supplies[] = { | ||
| 295 | REGULATOR_SUPPLY("vcc", "spi1.0"), | ||
| 296 | REGULATOR_SUPPLY("vcc", "3-0066"), | ||
| 297 | REGULATOR_SUPPLY("vcc", "3-0067"), | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct regulator_consumer_supply pandora_adac_supply = | ||
| 301 | REGULATOR_SUPPLY("vcc", "soc-audio"); | ||
| 302 | |||
| 250 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ | 303 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
| 251 | static struct regulator_init_data pandora_vmmc1 = { | 304 | static struct regulator_init_data pandora_vmmc1 = { |
| 252 | .constraints = { | 305 | .constraints = { |
| @@ -277,6 +330,96 @@ static struct regulator_init_data pandora_vmmc2 = { | |||
| 277 | .consumer_supplies = &pandora_vmmc2_supply, | 330 | .consumer_supplies = &pandora_vmmc2_supply, |
| 278 | }; | 331 | }; |
| 279 | 332 | ||
| 333 | /* VDAC for DSS driving S-Video */ | ||
| 334 | static struct regulator_init_data pandora_vdac = { | ||
| 335 | .constraints = { | ||
| 336 | .min_uV = 1800000, | ||
| 337 | .max_uV = 1800000, | ||
| 338 | .apply_uV = true, | ||
| 339 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 340 | | REGULATOR_MODE_STANDBY, | ||
| 341 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 342 | | REGULATOR_CHANGE_STATUS, | ||
| 343 | }, | ||
| 344 | .num_consumer_supplies = 1, | ||
| 345 | .consumer_supplies = &pandora_vdda_dac_supply, | ||
| 346 | }; | ||
| 347 | |||
| 348 | /* VPLL2 for digital video outputs */ | ||
| 349 | static struct regulator_init_data pandora_vpll2 = { | ||
| 350 | .constraints = { | ||
| 351 | .min_uV = 1800000, | ||
| 352 | .max_uV = 1800000, | ||
| 353 | .apply_uV = true, | ||
| 354 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 355 | | REGULATOR_MODE_STANDBY, | ||
| 356 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 357 | | REGULATOR_CHANGE_STATUS, | ||
| 358 | }, | ||
| 359 | .num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies), | ||
| 360 | .consumer_supplies = pandora_vdds_supplies, | ||
| 361 | }; | ||
| 362 | |||
| 363 | /* VAUX1 for LCD */ | ||
| 364 | static struct regulator_init_data pandora_vaux1 = { | ||
| 365 | .constraints = { | ||
| 366 | .min_uV = 3000000, | ||
| 367 | .max_uV = 3000000, | ||
| 368 | .apply_uV = true, | ||
| 369 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 370 | | REGULATOR_MODE_STANDBY, | ||
| 371 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 372 | | REGULATOR_CHANGE_STATUS, | ||
| 373 | }, | ||
| 374 | .num_consumer_supplies = 1, | ||
| 375 | .consumer_supplies = &pandora_vcc_lcd_supply, | ||
| 376 | }; | ||
| 377 | |||
| 378 | /* VAUX2 for USB host PHY */ | ||
| 379 | static struct regulator_init_data pandora_vaux2 = { | ||
| 380 | .constraints = { | ||
| 381 | .min_uV = 1800000, | ||
| 382 | .max_uV = 1800000, | ||
| 383 | .apply_uV = true, | ||
| 384 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 385 | | REGULATOR_MODE_STANDBY, | ||
| 386 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 387 | | REGULATOR_CHANGE_STATUS, | ||
| 388 | }, | ||
| 389 | .num_consumer_supplies = 1, | ||
| 390 | .consumer_supplies = &pandora_usb_phy_supply, | ||
| 391 | }; | ||
| 392 | |||
| 393 | /* VAUX4 for ads7846 and nubs */ | ||
| 394 | static struct regulator_init_data pandora_vaux4 = { | ||
| 395 | .constraints = { | ||
| 396 | .min_uV = 2800000, | ||
| 397 | .max_uV = 2800000, | ||
| 398 | .apply_uV = true, | ||
| 399 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 400 | | REGULATOR_MODE_STANDBY, | ||
| 401 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 402 | | REGULATOR_CHANGE_STATUS, | ||
| 403 | }, | ||
| 404 | .num_consumer_supplies = ARRAY_SIZE(pandora_vaux4_supplies), | ||
| 405 | .consumer_supplies = pandora_vaux4_supplies, | ||
| 406 | }; | ||
| 407 | |||
| 408 | /* VSIM for audio DAC */ | ||
| 409 | static struct regulator_init_data pandora_vsim = { | ||
| 410 | .constraints = { | ||
| 411 | .min_uV = 2800000, | ||
| 412 | .max_uV = 2800000, | ||
| 413 | .apply_uV = true, | ||
| 414 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 415 | | REGULATOR_MODE_STANDBY, | ||
| 416 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 417 | | REGULATOR_CHANGE_STATUS, | ||
| 418 | }, | ||
| 419 | .num_consumer_supplies = 1, | ||
| 420 | .consumer_supplies = &pandora_adac_supply, | ||
| 421 | }; | ||
| 422 | |||
| 280 | static struct twl4030_usb_data omap3pandora_usb_data = { | 423 | static struct twl4030_usb_data omap3pandora_usb_data = { |
| 281 | .usb_mode = T2_USB_MODE_ULPI, | 424 | .usb_mode = T2_USB_MODE_ULPI, |
| 282 | }; | 425 | }; |
| @@ -298,6 +441,12 @@ static struct twl4030_platform_data omap3pandora_twldata = { | |||
| 298 | .codec = &omap3pandora_codec_data, | 441 | .codec = &omap3pandora_codec_data, |
| 299 | .vmmc1 = &pandora_vmmc1, | 442 | .vmmc1 = &pandora_vmmc1, |
| 300 | .vmmc2 = &pandora_vmmc2, | 443 | .vmmc2 = &pandora_vmmc2, |
| 444 | .vdac = &pandora_vdac, | ||
| 445 | .vpll2 = &pandora_vpll2, | ||
| 446 | .vaux1 = &pandora_vaux1, | ||
| 447 | .vaux2 = &pandora_vaux2, | ||
| 448 | .vaux4 = &pandora_vaux4, | ||
| 449 | .vsim = &pandora_vsim, | ||
| 301 | .keypad = &pandora_kp_data, | 450 | .keypad = &pandora_kp_data, |
| 302 | }; | 451 | }; |
| 303 | 452 | ||
| @@ -365,6 +514,12 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { | |||
| 365 | .controller_data = &ads7846_mcspi_config, | 514 | .controller_data = &ads7846_mcspi_config, |
| 366 | .irq = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO), | 515 | .irq = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO), |
| 367 | .platform_data = &ads7846_config, | 516 | .platform_data = &ads7846_config, |
| 517 | }, { | ||
| 518 | .modalias = "tpo_td043mtea1_panel_spi", | ||
| 519 | .bus_num = 1, | ||
| 520 | .chip_select = 1, | ||
| 521 | .max_speed_hz = 375000, | ||
| 522 | .platform_data = &pandora_lcd_device, | ||
| 368 | } | 523 | } |
| 369 | }; | 524 | }; |
| 370 | 525 | ||
| @@ -379,6 +534,7 @@ static void __init omap3pandora_init_irq(void) | |||
| 379 | static struct platform_device *omap3pandora_devices[] __initdata = { | 534 | static struct platform_device *omap3pandora_devices[] __initdata = { |
| 380 | &pandora_leds_gpio, | 535 | &pandora_leds_gpio, |
| 381 | &pandora_keys_gpio, | 536 | &pandora_keys_gpio, |
| 537 | &pandora_dss_device, | ||
| 382 | }; | 538 | }; |
| 383 | 539 | ||
| 384 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 540 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
| @@ -401,6 +557,12 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 401 | #define board_mux NULL | 557 | #define board_mux NULL |
| 402 | #endif | 558 | #endif |
| 403 | 559 | ||
| 560 | static struct omap_musb_board_data musb_board_data = { | ||
| 561 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 562 | .mode = MUSB_OTG, | ||
| 563 | .power = 100, | ||
| 564 | }; | ||
| 565 | |||
| 404 | static void __init omap3pandora_init(void) | 566 | static void __init omap3pandora_init(void) |
| 405 | { | 567 | { |
| 406 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 568 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| @@ -413,7 +575,7 @@ static void __init omap3pandora_init(void) | |||
| 413 | omap3pandora_ads7846_init(); | 575 | omap3pandora_ads7846_init(); |
| 414 | usb_ehci_init(&ehci_pdata); | 576 | usb_ehci_init(&ehci_pdata); |
| 415 | pandora_keys_gpio_init(); | 577 | pandora_keys_gpio_init(); |
| 416 | usb_musb_init(); | 578 | usb_musb_init(&musb_board_data); |
| 417 | 579 | ||
| 418 | /* Ensure SDRC pins are mux'd for self-refresh */ | 580 | /* Ensure SDRC pins are mux'd for self-refresh */ |
| 419 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); | 581 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
| @@ -423,7 +585,7 @@ static void __init omap3pandora_init(void) | |||
| 423 | static void __init omap3pandora_map_io(void) | 585 | static void __init omap3pandora_map_io(void) |
| 424 | { | 586 | { |
| 425 | omap2_set_globals_343x(); | 587 | omap2_set_globals_343x(); |
| 426 | omap2_map_common_io(); | 588 | omap34xx_map_common_io(); |
| 427 | } | 589 | } |
| 428 | 590 | ||
| 429 | MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") | 591 | MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") |
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index fe3d22cb2457..3943d0f8322c 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c | |||
| @@ -50,7 +50,7 @@ | |||
| 50 | #include <plat/timer-gp.h> | 50 | #include <plat/timer-gp.h> |
| 51 | 51 | ||
| 52 | #include "mux.h" | 52 | #include "mux.h" |
| 53 | #include "mmc-twl4030.h" | 53 | #include "hsmmc.h" |
| 54 | 54 | ||
| 55 | #include <asm/setup.h> | 55 | #include <asm/setup.h> |
| 56 | 56 | ||
| @@ -122,7 +122,7 @@ static struct platform_device omap3touchbook_nand_device = { | |||
| 122 | 122 | ||
| 123 | #include "sdram-micron-mt46h32m32lf-6.h" | 123 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 124 | 124 | ||
| 125 | static struct twl4030_hsmmc_info mmc[] = { | 125 | static struct omap2_hsmmc_info mmc[] = { |
| 126 | { | 126 | { |
| 127 | .mmc = 1, | 127 | .mmc = 1, |
| 128 | .wires = 8, | 128 | .wires = 8, |
| @@ -161,7 +161,7 @@ static int touchbook_twl_gpio_setup(struct device *dev, | |||
| 161 | } | 161 | } |
| 162 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 162 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 163 | mmc[0].gpio_cd = gpio + 0; | 163 | mmc[0].gpio_cd = gpio + 0; |
| 164 | twl4030_mmc_init(mmc); | 164 | omap2_hsmmc_init(mmc); |
| 165 | 165 | ||
| 166 | /* link regulators to MMC adapters */ | 166 | /* link regulators to MMC adapters */ |
| 167 | touchbook_vmmc1_supply.dev = mmc[0].dev; | 167 | touchbook_vmmc1_supply.dev = mmc[0].dev; |
| @@ -527,6 +527,12 @@ static void __init early_touchbook_revision(char **p) | |||
| 527 | } | 527 | } |
| 528 | __early_param("tbr=", early_touchbook_revision); | 528 | __early_param("tbr=", early_touchbook_revision); |
| 529 | 529 | ||
| 530 | static struct omap_musb_board_data musb_board_data = { | ||
| 531 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 532 | .mode = MUSB_OTG, | ||
| 533 | .power = 100, | ||
| 534 | }; | ||
| 535 | |||
| 530 | static void __init omap3_touchbook_init(void) | 536 | static void __init omap3_touchbook_init(void) |
| 531 | { | 537 | { |
| 532 | pm_power_off = omap3_touchbook_poweroff; | 538 | pm_power_off = omap3_touchbook_poweroff; |
| @@ -545,7 +551,7 @@ static void __init omap3_touchbook_init(void) | |||
| 545 | spi_register_board_info(omap3_ads7846_spi_board_info, | 551 | spi_register_board_info(omap3_ads7846_spi_board_info, |
| 546 | ARRAY_SIZE(omap3_ads7846_spi_board_info)); | 552 | ARRAY_SIZE(omap3_ads7846_spi_board_info)); |
| 547 | omap3_ads7846_init(); | 553 | omap3_ads7846_init(); |
| 548 | usb_musb_init(); | 554 | usb_musb_init(&musb_board_data); |
| 549 | usb_ehci_init(&ehci_pdata); | 555 | usb_ehci_init(&ehci_pdata); |
| 550 | omap3touchbook_flash_init(); | 556 | omap3touchbook_flash_init(); |
| 551 | 557 | ||
| @@ -557,7 +563,7 @@ static void __init omap3_touchbook_init(void) | |||
| 557 | static void __init omap3_touchbook_map_io(void) | 563 | static void __init omap3_touchbook_map_io(void) |
| 558 | { | 564 | { |
| 559 | omap2_set_globals_343x(); | 565 | omap2_set_globals_343x(); |
| 560 | omap2_map_common_io(); | 566 | omap34xx_map_common_io(); |
| 561 | } | 567 | } |
| 562 | 568 | ||
| 563 | MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") | 569 | MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index d192dd98a591..50872a42bec7 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -48,7 +48,7 @@ | |||
| 48 | 48 | ||
| 49 | #include "mux.h" | 49 | #include "mux.h" |
| 50 | #include "sdram-micron-mt46h32m32lf-6.h" | 50 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 51 | #include "mmc-twl4030.h" | 51 | #include "hsmmc.h" |
| 52 | 52 | ||
| 53 | #define OVERO_GPIO_BT_XGATE 15 | 53 | #define OVERO_GPIO_BT_XGATE 15 |
| 54 | #define OVERO_GPIO_W2W_NRESET 16 | 54 | #define OVERO_GPIO_W2W_NRESET 16 |
| @@ -272,7 +272,7 @@ static void __init overo_flash_init(void) | |||
| 272 | } | 272 | } |
| 273 | } | 273 | } |
| 274 | 274 | ||
| 275 | static struct twl4030_hsmmc_info mmc[] = { | 275 | static struct omap2_hsmmc_info mmc[] = { |
| 276 | { | 276 | { |
| 277 | .mmc = 1, | 277 | .mmc = 1, |
| 278 | .wires = 4, | 278 | .wires = 4, |
| @@ -297,7 +297,7 @@ static struct regulator_consumer_supply overo_vmmc1_supply = { | |||
| 297 | static int overo_twl_gpio_setup(struct device *dev, | 297 | static int overo_twl_gpio_setup(struct device *dev, |
| 298 | unsigned gpio, unsigned ngpio) | 298 | unsigned gpio, unsigned ngpio) |
| 299 | { | 299 | { |
| 300 | twl4030_mmc_init(mmc); | 300 | omap2_hsmmc_init(mmc); |
| 301 | 301 | ||
| 302 | overo_vmmc1_supply.dev = mmc[0].dev; | 302 | overo_vmmc1_supply.dev = mmc[0].dev; |
| 303 | 303 | ||
| @@ -413,6 +413,12 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 413 | #define board_mux NULL | 413 | #define board_mux NULL |
| 414 | #endif | 414 | #endif |
| 415 | 415 | ||
| 416 | static struct omap_musb_board_data musb_board_data = { | ||
| 417 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 418 | .mode = MUSB_OTG, | ||
| 419 | .power = 100, | ||
| 420 | }; | ||
| 421 | |||
| 416 | static void __init overo_init(void) | 422 | static void __init overo_init(void) |
| 417 | { | 423 | { |
| 418 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 424 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| @@ -420,7 +426,7 @@ static void __init overo_init(void) | |||
| 420 | platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); | 426 | platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); |
| 421 | omap_serial_init(); | 427 | omap_serial_init(); |
| 422 | overo_flash_init(); | 428 | overo_flash_init(); |
| 423 | usb_musb_init(); | 429 | usb_musb_init(&musb_board_data); |
| 424 | usb_ehci_init(&ehci_pdata); | 430 | usb_ehci_init(&ehci_pdata); |
| 425 | overo_ads7846_init(); | 431 | overo_ads7846_init(); |
| 426 | overo_init_smsc911x(); | 432 | overo_init_smsc911x(); |
| @@ -469,7 +475,7 @@ static void __init overo_init(void) | |||
| 469 | static void __init overo_map_io(void) | 475 | static void __init overo_map_io(void) |
| 470 | { | 476 | { |
| 471 | omap2_set_globals_343x(); | 477 | omap2_set_globals_343x(); |
| 472 | omap2_map_common_io(); | 478 | omap34xx_map_common_io(); |
| 473 | } | 479 | } |
| 474 | 480 | ||
| 475 | MACHINE_START(OVERO, "Gumstix Overo") | 481 | MACHINE_START(OVERO, "Gumstix Overo") |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index acafdbc8aa16..4377a4cf36eb 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -34,7 +34,7 @@ | |||
| 34 | #include <plat/gpmc-smc91x.h> | 34 | #include <plat/gpmc-smc91x.h> |
| 35 | 35 | ||
| 36 | #include "mux.h" | 36 | #include "mux.h" |
| 37 | #include "mmc-twl4030.h" | 37 | #include "hsmmc.h" |
| 38 | 38 | ||
| 39 | #define SYSTEM_REV_B_USES_VAUX3 0x1699 | 39 | #define SYSTEM_REV_B_USES_VAUX3 0x1699 |
| 40 | #define SYSTEM_REV_S_USES_VAUX3 0x8 | 40 | #define SYSTEM_REV_S_USES_VAUX3 0x8 |
| @@ -209,7 +209,47 @@ static struct twl4030_madc_platform_data rx51_madc_data = { | |||
| 209 | .irq_line = 1, | 209 | .irq_line = 1, |
| 210 | }; | 210 | }; |
| 211 | 211 | ||
| 212 | static struct twl4030_hsmmc_info mmc[] = { | 212 | /* Enable input logic and pull all lines up when eMMC is on. */ |
| 213 | static struct omap_board_mux rx51_mmc2_on_mux[] = { | ||
| 214 | OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 215 | OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 216 | OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 217 | OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 218 | OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 219 | OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 220 | OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 221 | OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 222 | OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), | ||
| 223 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 224 | }; | ||
| 225 | |||
| 226 | /* Disable input logic and pull all lines down when eMMC is off. */ | ||
| 227 | static struct omap_board_mux rx51_mmc2_off_mux[] = { | ||
| 228 | OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 229 | OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 230 | OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 231 | OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 232 | OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 233 | OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 234 | OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 235 | OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 236 | OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0), | ||
| 237 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 238 | }; | ||
| 239 | |||
| 240 | /* | ||
| 241 | * Current flows to eMMC when eMMC is off and the data lines are pulled up, | ||
| 242 | * so pull them down. N.B. we pull 8 lines because we are using 8 lines. | ||
| 243 | */ | ||
| 244 | static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) | ||
| 245 | { | ||
| 246 | if (power_on) | ||
| 247 | omap_mux_write_array(rx51_mmc2_on_mux); | ||
| 248 | else | ||
| 249 | omap_mux_write_array(rx51_mmc2_off_mux); | ||
| 250 | } | ||
| 251 | |||
| 252 | static struct omap2_hsmmc_info mmc[] __initdata = { | ||
| 213 | { | 253 | { |
| 214 | .name = "external", | 254 | .name = "external", |
| 215 | .mmc = 1, | 255 | .mmc = 1, |
| @@ -222,25 +262,29 @@ static struct twl4030_hsmmc_info mmc[] = { | |||
| 222 | { | 262 | { |
| 223 | .name = "internal", | 263 | .name = "internal", |
| 224 | .mmc = 2, | 264 | .mmc = 2, |
| 225 | .wires = 8, | 265 | .wires = 8, /* See also rx51_mmc2_remux */ |
| 226 | .gpio_cd = -EINVAL, | 266 | .gpio_cd = -EINVAL, |
| 227 | .gpio_wp = -EINVAL, | 267 | .gpio_wp = -EINVAL, |
| 228 | .nonremovable = true, | 268 | .nonremovable = true, |
| 229 | .power_saving = true, | 269 | .power_saving = true, |
| 270 | .remux = rx51_mmc2_remux, | ||
| 230 | }, | 271 | }, |
| 231 | {} /* Terminator */ | 272 | {} /* Terminator */ |
| 232 | }; | 273 | }; |
| 233 | 274 | ||
| 234 | static struct regulator_consumer_supply rx51_vmmc1_supply = { | 275 | static struct regulator_consumer_supply rx51_vmmc1_supply = { |
| 235 | .supply = "vmmc", | 276 | .supply = "vmmc", |
| 277 | .dev_name = "mmci-omap-hs.0", | ||
| 236 | }; | 278 | }; |
| 237 | 279 | ||
| 238 | static struct regulator_consumer_supply rx51_vmmc2_supply = { | 280 | static struct regulator_consumer_supply rx51_vmmc2_supply = { |
| 239 | .supply = "vmmc", | 281 | .supply = "vmmc", |
| 282 | .dev_name = "mmci-omap-hs.1", | ||
| 240 | }; | 283 | }; |
| 241 | 284 | ||
| 242 | static struct regulator_consumer_supply rx51_vsim_supply = { | 285 | static struct regulator_consumer_supply rx51_vsim_supply = { |
| 243 | .supply = "vmmc_aux", | 286 | .supply = "vmmc_aux", |
| 287 | .dev_name = "mmci-omap-hs.1", | ||
| 244 | }; | 288 | }; |
| 245 | 289 | ||
| 246 | static struct regulator_init_data rx51_vaux1 = { | 290 | static struct regulator_init_data rx51_vaux1 = { |
| @@ -375,12 +419,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) | |||
| 375 | gpio_request(gpio + 7, "speaker_en"); | 419 | gpio_request(gpio + 7, "speaker_en"); |
| 376 | gpio_direction_output(gpio + 7, 1); | 420 | gpio_direction_output(gpio + 7, 1); |
| 377 | 421 | ||
| 378 | /* set up MMC adapters, linking their regulators to them */ | ||
| 379 | twl4030_mmc_init(mmc); | ||
| 380 | rx51_vmmc1_supply.dev = mmc[0].dev; | ||
| 381 | rx51_vmmc2_supply.dev = mmc[1].dev; | ||
| 382 | rx51_vsim_supply.dev = mmc[1].dev; | ||
| 383 | |||
| 384 | return 0; | 422 | return 0; |
| 385 | } | 423 | } |
| 386 | 424 | ||
| @@ -751,5 +789,6 @@ void __init rx51_peripherals_init(void) | |||
| 751 | rx51_init_wl1251(); | 789 | rx51_init_wl1251(); |
| 752 | spi_register_board_info(rx51_peripherals_spi_board_info, | 790 | spi_register_board_info(rx51_peripherals_spi_board_info, |
| 753 | ARRAY_SIZE(rx51_peripherals_spi_board_info)); | 791 | ARRAY_SIZE(rx51_peripherals_spi_board_info)); |
| 792 | omap2_hsmmc_init(mmc); | ||
| 754 | } | 793 | } |
| 755 | 794 | ||
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 67bb3476b707..b155c366c650 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
| 19 | #include <linux/leds.h> | ||
| 19 | 20 | ||
| 20 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 21 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| @@ -30,9 +31,49 @@ | |||
| 30 | #include <plat/usb.h> | 31 | #include <plat/usb.h> |
| 31 | 32 | ||
| 32 | #include "mux.h" | 33 | #include "mux.h" |
| 34 | #include "pm.h" | ||
| 35 | |||
| 36 | #define RX51_GPIO_SLEEP_IND 162 | ||
| 33 | 37 | ||
| 34 | struct omap_sdrc_params *rx51_get_sdram_timings(void); | 38 | struct omap_sdrc_params *rx51_get_sdram_timings(void); |
| 35 | 39 | ||
| 40 | static struct gpio_led gpio_leds[] = { | ||
| 41 | { | ||
| 42 | .name = "sleep_ind", | ||
| 43 | .gpio = RX51_GPIO_SLEEP_IND, | ||
| 44 | }, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 48 | .leds = gpio_leds, | ||
| 49 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 50 | }; | ||
| 51 | |||
| 52 | static struct platform_device leds_gpio = { | ||
| 53 | .name = "leds-gpio", | ||
| 54 | .id = -1, | ||
| 55 | .dev = { | ||
| 56 | .platform_data = &gpio_led_info, | ||
| 57 | }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct cpuidle_params rx51_cpuidle_params[] = { | ||
| 61 | /* C1 */ | ||
| 62 | {1, 110, 162, 5}, | ||
| 63 | /* C2 */ | ||
| 64 | {1, 106, 180, 309}, | ||
| 65 | /* C3 */ | ||
| 66 | {0, 107, 410, 46057}, | ||
| 67 | /* C4 */ | ||
| 68 | {0, 121, 3374, 46057}, | ||
| 69 | /* C5 */ | ||
| 70 | {1, 855, 1146, 46057}, | ||
| 71 | /* C6 */ | ||
| 72 | {0, 7580, 4134, 484329}, | ||
| 73 | /* C7 */ | ||
| 74 | {1, 7505, 15274, 484329}, | ||
| 75 | }; | ||
| 76 | |||
| 36 | static struct omap_lcd_config rx51_lcd_config = { | 77 | static struct omap_lcd_config rx51_lcd_config = { |
| 37 | .ctrl_name = "internal", | 78 | .ctrl_name = "internal", |
| 38 | }; | 79 | }; |
| @@ -62,6 +103,7 @@ static void __init rx51_init_irq(void) | |||
| 62 | 103 | ||
| 63 | omap_board_config = rx51_config; | 104 | omap_board_config = rx51_config; |
| 64 | omap_board_config_size = ARRAY_SIZE(rx51_config); | 105 | omap_board_config_size = ARRAY_SIZE(rx51_config); |
| 106 | omap3_pm_init_cpuidle(rx51_cpuidle_params); | ||
| 65 | sdrc_params = rx51_get_sdram_timings(); | 107 | sdrc_params = rx51_get_sdram_timings(); |
| 66 | omap2_init_common_hw(sdrc_params, sdrc_params); | 108 | omap2_init_common_hw(sdrc_params, sdrc_params); |
| 67 | omap_init_irq(); | 109 | omap_init_irq(); |
| @@ -78,22 +120,30 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 78 | #define board_mux NULL | 120 | #define board_mux NULL |
| 79 | #endif | 121 | #endif |
| 80 | 122 | ||
| 123 | static struct omap_musb_board_data musb_board_data = { | ||
| 124 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 125 | .mode = MUSB_PERIPHERAL, | ||
| 126 | .power = 0, | ||
| 127 | }; | ||
| 128 | |||
| 81 | static void __init rx51_init(void) | 129 | static void __init rx51_init(void) |
| 82 | { | 130 | { |
| 83 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 131 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 84 | omap_serial_init(); | 132 | omap_serial_init(); |
| 85 | usb_musb_init(); | 133 | usb_musb_init(&musb_board_data); |
| 86 | rx51_peripherals_init(); | 134 | rx51_peripherals_init(); |
| 87 | 135 | ||
| 88 | /* Ensure SDRC pins are mux'd for self-refresh */ | 136 | /* Ensure SDRC pins are mux'd for self-refresh */ |
| 89 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); | 137 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
| 90 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); | 138 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
| 139 | |||
| 140 | platform_device_register(&leds_gpio); | ||
| 91 | } | 141 | } |
| 92 | 142 | ||
| 93 | static void __init rx51_map_io(void) | 143 | static void __init rx51_map_io(void) |
| 94 | { | 144 | { |
| 95 | omap2_set_globals_343x(); | 145 | omap2_set_globals_343x(); |
| 96 | omap2_map_common_io(); | 146 | omap34xx_map_common_io(); |
| 97 | } | 147 | } |
| 98 | 148 | ||
| 99 | MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") | 149 | MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") |
diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-sdp-flash.c new file mode 100644 index 000000000000..b1b88deec7f2 --- /dev/null +++ b/arch/arm/mach-omap2/board-sdp-flash.c | |||
| @@ -0,0 +1,272 @@ | |||
| 1 | /* | ||
| 2 | * board-sdp-flash.c | ||
| 3 | * Modified from mach-omap2/board-3430sdp-flash.c | ||
| 4 | * | ||
| 5 | * Copyright (C) 2009 Nokia Corporation | ||
| 6 | * Copyright (C) 2009 Texas Instruments | ||
| 7 | * | ||
| 8 | * Vimal Singh <vimalsingh@ti.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/mtd/physmap.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | |||
| 20 | #include <plat/gpmc.h> | ||
| 21 | #include <plat/nand.h> | ||
| 22 | #include <plat/onenand.h> | ||
| 23 | #include <plat/tc.h> | ||
| 24 | #include <mach/board-sdp.h> | ||
| 25 | |||
| 26 | #define REG_FPGA_REV 0x10 | ||
| 27 | #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 | ||
| 28 | #define MAX_SUPPORTED_GPMC_CONFIG 3 | ||
| 29 | |||
| 30 | #define DEBUG_BASE 0x08000000 /* debug board */ | ||
| 31 | |||
| 32 | #define PDC_NOR 1 | ||
| 33 | #define PDC_NAND 2 | ||
| 34 | #define PDC_ONENAND 3 | ||
| 35 | #define DBG_MPDB 4 | ||
| 36 | |||
| 37 | /* various memory sizes */ | ||
| 38 | #define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ | ||
| 39 | #define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * SDP3430 V2 Board CS organization | ||
| 43 | * Different from SDP3430 V1. Now 4 switches used to specify CS | ||
| 44 | * | ||
| 45 | * See also the Switch S8 settings in the comments. | ||
| 46 | * | ||
| 47 | * REVISIT: Add support for 2430 SDP | ||
| 48 | */ | ||
| 49 | static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = { | ||
| 50 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | ||
| 51 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | ||
| 52 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct physmap_flash_data sdp_nor_data = { | ||
| 56 | .width = 2, | ||
| 57 | }; | ||
| 58 | |||
| 59 | static struct resource sdp_nor_resource = { | ||
| 60 | .flags = IORESOURCE_MEM, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct platform_device sdp_nor_device = { | ||
| 64 | .name = "physmap-flash", | ||
| 65 | .id = 0, | ||
| 66 | .dev = { | ||
| 67 | .platform_data = &sdp_nor_data, | ||
| 68 | }, | ||
| 69 | .num_resources = 1, | ||
| 70 | .resource = &sdp_nor_resource, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static void | ||
| 74 | __init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs) | ||
| 75 | { | ||
| 76 | int err; | ||
| 77 | |||
| 78 | sdp_nor_data.parts = sdp_nor_parts.parts; | ||
| 79 | sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts; | ||
| 80 | |||
| 81 | /* Configure start address and size of NOR device */ | ||
| 82 | if (omap_rev() >= OMAP3430_REV_ES1_0) { | ||
| 83 | err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, | ||
| 84 | (unsigned long *)&sdp_nor_resource.start); | ||
| 85 | sdp_nor_resource.end = sdp_nor_resource.start | ||
| 86 | + FLASH_SIZE_SDPV2 - 1; | ||
| 87 | } else { | ||
| 88 | err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, | ||
| 89 | (unsigned long *)&sdp_nor_resource.start); | ||
| 90 | sdp_nor_resource.end = sdp_nor_resource.start | ||
| 91 | + FLASH_SIZE_SDPV1 - 1; | ||
| 92 | } | ||
| 93 | if (err < 0) { | ||
| 94 | printk(KERN_ERR "NOR: Can't request GPMC CS\n"); | ||
| 95 | return; | ||
| 96 | } | ||
| 97 | if (platform_device_register(&sdp_nor_device) < 0) | ||
| 98 | printk(KERN_ERR "Unable to register NOR device\n"); | ||
| 99 | } | ||
| 100 | |||
| 101 | #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ | ||
| 102 | defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) | ||
| 103 | static struct omap_onenand_platform_data board_onenand_data = { | ||
| 104 | .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ | ||
| 105 | }; | ||
| 106 | |||
| 107 | static void | ||
| 108 | __init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) | ||
| 109 | { | ||
| 110 | board_onenand_data.cs = cs; | ||
| 111 | board_onenand_data.parts = sdp_onenand_parts.parts; | ||
| 112 | board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts; | ||
| 113 | |||
| 114 | gpmc_onenand_init(&board_onenand_data); | ||
| 115 | } | ||
| 116 | #else | ||
| 117 | static void | ||
| 118 | __init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) | ||
| 119 | { | ||
| 120 | } | ||
| 121 | #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ | ||
| 122 | |||
| 123 | #if defined(CONFIG_MTD_NAND_OMAP2) || \ | ||
| 124 | defined(CONFIG_MTD_NAND_OMAP2_MODULE) | ||
| 125 | |||
| 126 | /* Note that all values in this struct are in nanoseconds */ | ||
| 127 | static struct gpmc_timings nand_timings = { | ||
| 128 | |||
| 129 | .sync_clk = 0, | ||
| 130 | |||
| 131 | .cs_on = 0, | ||
| 132 | .cs_rd_off = 36, | ||
| 133 | .cs_wr_off = 36, | ||
| 134 | |||
| 135 | .adv_on = 6, | ||
| 136 | .adv_rd_off = 24, | ||
| 137 | .adv_wr_off = 36, | ||
| 138 | |||
| 139 | .we_off = 30, | ||
| 140 | .oe_off = 48, | ||
| 141 | |||
| 142 | .access = 54, | ||
| 143 | .rd_cycle = 72, | ||
| 144 | .wr_cycle = 72, | ||
| 145 | |||
| 146 | .wr_access = 30, | ||
| 147 | .wr_data_mux_bus = 0, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct omap_nand_platform_data sdp_nand_data = { | ||
| 151 | .nand_setup = NULL, | ||
| 152 | .gpmc_t = &nand_timings, | ||
| 153 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | ||
| 154 | .dev_ready = NULL, | ||
| 155 | .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ | ||
| 156 | }; | ||
| 157 | |||
| 158 | static void | ||
| 159 | __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) | ||
| 160 | { | ||
| 161 | sdp_nand_data.cs = cs; | ||
| 162 | sdp_nand_data.parts = sdp_nand_parts.parts; | ||
| 163 | sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts; | ||
| 164 | |||
| 165 | sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + | ||
| 166 | GPMC_CS0_BASE + | ||
| 167 | cs * GPMC_CS_SIZE); | ||
| 168 | sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); | ||
| 169 | |||
| 170 | gpmc_nand_init(&sdp_nand_data); | ||
| 171 | } | ||
| 172 | #else | ||
| 173 | static void | ||
| 174 | __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) | ||
| 175 | { | ||
| 176 | } | ||
| 177 | #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ | ||
| 178 | |||
| 179 | /** | ||
| 180 | * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get | ||
| 181 | * the various cs values. | ||
| 182 | */ | ||
| 183 | static u8 get_gpmc0_type(void) | ||
| 184 | { | ||
| 185 | u8 cs = 0; | ||
| 186 | void __iomem *fpga_map_addr; | ||
| 187 | |||
| 188 | fpga_map_addr = ioremap(DEBUG_BASE, 4096); | ||
| 189 | if (!fpga_map_addr) | ||
| 190 | return -ENOMEM; | ||
| 191 | |||
| 192 | if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV))) | ||
| 193 | /* we dont have an DEBUG FPGA??? */ | ||
| 194 | /* Depend on #defines!! default to strata boot return param */ | ||
| 195 | goto unmap; | ||
| 196 | |||
| 197 | /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ | ||
| 198 | cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; | ||
| 199 | |||
| 200 | /* ES2.0 SDP's onwards 4 dip switches are provided for CS */ | ||
| 201 | if (omap_rev() >= OMAP3430_REV_ES1_0) | ||
| 202 | /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ | ||
| 203 | cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | | ||
| 204 | ((cs & 2) << 1) | ((cs & 1) << 3); | ||
| 205 | else | ||
| 206 | /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ | ||
| 207 | cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); | ||
| 208 | unmap: | ||
| 209 | iounmap(fpga_map_addr); | ||
| 210 | return cs; | ||
| 211 | } | ||
| 212 | |||
| 213 | /** | ||
| 214 | * sdp3430_flash_init - Identify devices connected to GPMC and register. | ||
| 215 | * | ||
| 216 | * @return - void. | ||
| 217 | */ | ||
| 218 | void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) | ||
| 219 | { | ||
| 220 | u8 cs = 0; | ||
| 221 | u8 norcs = GPMC_CS_NUM + 1; | ||
| 222 | u8 nandcs = GPMC_CS_NUM + 1; | ||
| 223 | u8 onenandcs = GPMC_CS_NUM + 1; | ||
| 224 | u8 idx; | ||
| 225 | unsigned char *config_sel = NULL; | ||
| 226 | |||
| 227 | /* REVISIT: Is this return correct idx for 2430 SDP? | ||
| 228 | * for which cs configuration matches for 2430 SDP? | ||
| 229 | */ | ||
| 230 | idx = get_gpmc0_type(); | ||
| 231 | if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { | ||
| 232 | printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); | ||
| 233 | return; | ||
| 234 | } | ||
| 235 | config_sel = (unsigned char *)(chip_sel_sdp[idx]); | ||
| 236 | |||
| 237 | while (cs < GPMC_CS_NUM) { | ||
| 238 | switch (config_sel[cs]) { | ||
| 239 | case PDC_NOR: | ||
| 240 | if (norcs > GPMC_CS_NUM) | ||
| 241 | norcs = cs; | ||
| 242 | break; | ||
| 243 | case PDC_NAND: | ||
| 244 | if (nandcs > GPMC_CS_NUM) | ||
| 245 | nandcs = cs; | ||
| 246 | break; | ||
| 247 | case PDC_ONENAND: | ||
| 248 | if (onenandcs > GPMC_CS_NUM) | ||
| 249 | onenandcs = cs; | ||
| 250 | break; | ||
| 251 | }; | ||
| 252 | cs++; | ||
| 253 | } | ||
| 254 | |||
| 255 | if (norcs > GPMC_CS_NUM) | ||
| 256 | printk(KERN_INFO "OneNAND: Unable to find configuration " | ||
| 257 | " in GPMC\n "); | ||
| 258 | else | ||
| 259 | board_nor_init(sdp_partition_info[0], norcs); | ||
| 260 | |||
| 261 | if (onenandcs > GPMC_CS_NUM) | ||
| 262 | printk(KERN_INFO "OneNAND: Unable to find configuration " | ||
| 263 | " in GPMC\n "); | ||
| 264 | else | ||
| 265 | board_onenand_init(sdp_partition_info[1], onenandcs); | ||
| 266 | |||
| 267 | if (nandcs > GPMC_CS_NUM) | ||
| 268 | printk(KERN_INFO "NAND: Unable to find configuration " | ||
| 269 | " in GPMC\n "); | ||
| 270 | else | ||
| 271 | board_nand_init(sdp_partition_info[2], nandcs); | ||
| 272 | } | ||
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 1e3dfb652acc..ca95d8d64136 100755 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c | |||
| @@ -24,7 +24,8 @@ | |||
| 24 | #include <plat/common.h> | 24 | #include <plat/common.h> |
| 25 | #include <plat/usb.h> | 25 | #include <plat/usb.h> |
| 26 | 26 | ||
| 27 | #include "mmc-twl4030.h" | 27 | #include "mux.h" |
| 28 | #include "hsmmc.h" | ||
| 28 | 29 | ||
| 29 | /* Zoom2 has Qwerty keyboard*/ | 30 | /* Zoom2 has Qwerty keyboard*/ |
| 30 | static int board_keymap[] = { | 31 | static int board_keymap[] = { |
| @@ -150,7 +151,7 @@ static struct regulator_init_data zoom_vsim = { | |||
| 150 | .consumer_supplies = &zoom_vsim_supply, | 151 | .consumer_supplies = &zoom_vsim_supply, |
| 151 | }; | 152 | }; |
| 152 | 153 | ||
| 153 | static struct twl4030_hsmmc_info mmc[] __initdata = { | 154 | static struct omap2_hsmmc_info mmc[] __initdata = { |
| 154 | { | 155 | { |
| 155 | .name = "external", | 156 | .name = "external", |
| 156 | .mmc = 1, | 157 | .mmc = 1, |
| @@ -175,7 +176,7 @@ static int zoom_twl_gpio_setup(struct device *dev, | |||
| 175 | { | 176 | { |
| 176 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | 177 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ |
| 177 | mmc[0].gpio_cd = gpio + 0; | 178 | mmc[0].gpio_cd = gpio + 0; |
| 178 | twl4030_mmc_init(mmc); | 179 | omap2_hsmmc_init(mmc); |
| 179 | 180 | ||
| 180 | /* link regulators to MMC adapters ... we "know" the | 181 | /* link regulators to MMC adapters ... we "know" the |
| 181 | * regulators will be set up only *after* we return. | 182 | * regulators will be set up only *after* we return. |
| @@ -263,9 +264,23 @@ static int __init omap_i2c_init(void) | |||
| 263 | return 0; | 264 | return 0; |
| 264 | } | 265 | } |
| 265 | 266 | ||
| 267 | static struct omap_musb_board_data musb_board_data = { | ||
| 268 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 269 | .mode = MUSB_OTG, | ||
| 270 | .power = 100, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static void enable_board_wakeup_source(void) | ||
| 274 | { | ||
| 275 | /* T2 interrupt line (keypad) */ | ||
| 276 | omap_mux_init_signal("sys_nirq", | ||
| 277 | OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); | ||
| 278 | } | ||
| 279 | |||
| 266 | void __init zoom_peripherals_init(void) | 280 | void __init zoom_peripherals_init(void) |
| 267 | { | 281 | { |
| 268 | omap_i2c_init(); | 282 | omap_i2c_init(); |
| 269 | omap_serial_init(); | 283 | omap_serial_init(); |
| 270 | usb_musb_init(); | 284 | usb_musb_init(&musb_board_data); |
| 285 | enable_board_wakeup_source(); | ||
| 271 | } | 286 | } |
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index bb87cf7878ff..9a26f84b1141 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c | |||
| @@ -87,7 +87,7 @@ static void __init omap_zoom2_init(void) | |||
| 87 | static void __init omap_zoom2_map_io(void) | 87 | static void __init omap_zoom2_map_io(void) |
| 88 | { | 88 | { |
| 89 | omap2_set_globals_343x(); | 89 | omap2_set_globals_343x(); |
| 90 | omap2_map_common_io(); | 90 | omap34xx_map_common_io(); |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") | 93 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") |
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index a9fe9181b010..d3e3cd5170d1 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c | |||
| @@ -20,14 +20,15 @@ | |||
| 20 | 20 | ||
| 21 | #include <plat/common.h> | 21 | #include <plat/common.h> |
| 22 | #include <plat/board.h> | 22 | #include <plat/board.h> |
| 23 | #include <plat/usb.h> | ||
| 23 | 24 | ||
| 24 | #include "mux.h" | 25 | #include "mux.h" |
| 25 | #include "sdram-hynix-h8mbx00u0mer-0em.h" | 26 | #include "sdram-hynix-h8mbx00u0mer-0em.h" |
| 26 | 27 | ||
| 27 | static void __init omap_zoom_map_io(void) | 28 | static void __init omap_zoom_map_io(void) |
| 28 | { | 29 | { |
| 29 | omap2_set_globals_343x(); | 30 | omap2_set_globals_36xx(); |
| 30 | omap2_map_common_io(); | 31 | omap34xx_map_common_io(); |
| 31 | } | 32 | } |
| 32 | 33 | ||
| 33 | static struct omap_board_config_kernel zoom_config[] __initdata = { | 34 | static struct omap_board_config_kernel zoom_config[] __initdata = { |
| @@ -51,11 +52,24 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 51 | #define board_mux NULL | 52 | #define board_mux NULL |
| 52 | #endif | 53 | #endif |
| 53 | 54 | ||
| 55 | static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | ||
| 56 | .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 57 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, | ||
| 58 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 59 | .phy_reset = true, | ||
| 60 | .reset_gpio_port[0] = -EINVAL, | ||
| 61 | .reset_gpio_port[1] = 64, | ||
| 62 | .reset_gpio_port[2] = -EINVAL, | ||
| 63 | }; | ||
| 64 | |||
| 54 | static void __init omap_zoom_init(void) | 65 | static void __init omap_zoom_init(void) |
| 55 | { | 66 | { |
| 56 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | 67 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); |
| 57 | zoom_peripherals_init(); | 68 | zoom_peripherals_init(); |
| 58 | zoom_debugboard_init(); | 69 | zoom_debugboard_init(); |
| 70 | |||
| 71 | omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); | ||
| 72 | usb_ehci_init(&ehci_pdata); | ||
| 59 | } | 73 | } |
| 60 | 74 | ||
| 61 | MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") | 75 | MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") |
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c new file mode 100644 index 000000000000..43d7246ce335 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c | |||
| @@ -0,0 +1,122 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2xxx APLL clock control functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | #undef DEBUG | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | #include <plat/prcm.h> | ||
| 26 | |||
| 27 | #include "clock.h" | ||
| 28 | #include "clock2xxx.h" | ||
| 29 | #include "cm.h" | ||
| 30 | #include "cm-regbits-24xx.h" | ||
| 31 | |||
| 32 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | ||
| 33 | #define EN_APLL_STOPPED 0 | ||
| 34 | #define EN_APLL_LOCKED 3 | ||
| 35 | |||
| 36 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ | ||
| 37 | #define APLLS_CLKIN_19_2MHZ 0 | ||
| 38 | #define APLLS_CLKIN_13MHZ 2 | ||
| 39 | #define APLLS_CLKIN_12MHZ 3 | ||
| 40 | |||
| 41 | void __iomem *cm_idlest_pll; | ||
| 42 | |||
| 43 | /* Private functions */ | ||
| 44 | |||
| 45 | /* Enable an APLL if off */ | ||
| 46 | static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) | ||
| 47 | { | ||
| 48 | u32 cval, apll_mask; | ||
| 49 | |||
| 50 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
| 51 | |||
| 52 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
| 53 | |||
| 54 | if ((cval & apll_mask) == apll_mask) | ||
| 55 | return 0; /* apll already enabled */ | ||
| 56 | |||
| 57 | cval &= ~apll_mask; | ||
| 58 | cval |= apll_mask; | ||
| 59 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
| 60 | |||
| 61 | omap2_cm_wait_idlest(cm_idlest_pll, status_mask, | ||
| 62 | OMAP24XX_CM_IDLEST_VAL, clk->name); | ||
| 63 | |||
| 64 | /* | ||
| 65 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | ||
| 66 | * fails? | ||
| 67 | */ | ||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | static int omap2_clk_apll96_enable(struct clk *clk) | ||
| 72 | { | ||
| 73 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); | ||
| 74 | } | ||
| 75 | |||
| 76 | static int omap2_clk_apll54_enable(struct clk *clk) | ||
| 77 | { | ||
| 78 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); | ||
| 79 | } | ||
| 80 | |||
| 81 | /* Stop APLL */ | ||
| 82 | static void omap2_clk_apll_disable(struct clk *clk) | ||
| 83 | { | ||
| 84 | u32 cval; | ||
| 85 | |||
| 86 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
| 87 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | ||
| 88 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
| 89 | } | ||
| 90 | |||
| 91 | /* Public data */ | ||
| 92 | |||
| 93 | const struct clkops clkops_apll96 = { | ||
| 94 | .enable = omap2_clk_apll96_enable, | ||
| 95 | .disable = omap2_clk_apll_disable, | ||
| 96 | }; | ||
| 97 | |||
| 98 | const struct clkops clkops_apll54 = { | ||
| 99 | .enable = omap2_clk_apll54_enable, | ||
| 100 | .disable = omap2_clk_apll_disable, | ||
| 101 | }; | ||
| 102 | |||
| 103 | /* Public functions */ | ||
| 104 | |||
| 105 | u32 omap2xxx_get_apll_clkin(void) | ||
| 106 | { | ||
| 107 | u32 aplls, srate = 0; | ||
| 108 | |||
| 109 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | ||
| 110 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | ||
| 111 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | ||
| 112 | |||
| 113 | if (aplls == APLLS_CLKIN_19_2MHZ) | ||
| 114 | srate = 19200000; | ||
| 115 | else if (aplls == APLLS_CLKIN_13MHZ) | ||
| 116 | srate = 13000000; | ||
| 117 | else if (aplls == APLLS_CLKIN_12MHZ) | ||
| 118 | srate = 12000000; | ||
| 119 | |||
| 120 | return srate; | ||
| 121 | } | ||
| 122 | |||
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c new file mode 100644 index 000000000000..019048434f13 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c | |||
| @@ -0,0 +1,173 @@ | |||
| 1 | /* | ||
| 2 | * DPLL + CORE_CLK composite clock functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | * | ||
| 18 | * XXX The DPLL and CORE clocks should be split into two separate clock | ||
| 19 | * types. | ||
| 20 | */ | ||
| 21 | #undef DEBUG | ||
| 22 | |||
| 23 | #include <linux/kernel.h> | ||
| 24 | #include <linux/errno.h> | ||
| 25 | #include <linux/clk.h> | ||
| 26 | #include <linux/io.h> | ||
| 27 | |||
| 28 | #include <plat/clock.h> | ||
| 29 | #include <plat/sram.h> | ||
| 30 | #include <plat/sdrc.h> | ||
| 31 | |||
| 32 | #include "clock.h" | ||
| 33 | #include "clock2xxx.h" | ||
| 34 | #include "opp2xxx.h" | ||
| 35 | #include "cm.h" | ||
| 36 | #include "cm-regbits-24xx.h" | ||
| 37 | |||
| 38 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | ||
| 39 | |||
| 40 | /** | ||
| 41 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | ||
| 42 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
| 43 | * | ||
| 44 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | ||
| 45 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | ||
| 46 | * (the latter is unusual). This currently should be called with | ||
| 47 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | ||
| 48 | * core_ck. | ||
| 49 | */ | ||
| 50 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | ||
| 51 | { | ||
| 52 | long long core_clk; | ||
| 53 | u32 v; | ||
| 54 | |||
| 55 | core_clk = omap2_get_dpll_rate(clk); | ||
| 56 | |||
| 57 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 58 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 59 | |||
| 60 | if (v == CORE_CLK_SRC_32K) | ||
| 61 | core_clk = 32768; | ||
| 62 | else | ||
| 63 | core_clk *= v; | ||
| 64 | |||
| 65 | return core_clk; | ||
| 66 | } | ||
| 67 | |||
| 68 | /* | ||
| 69 | * Uses the current prcm set to tell if a rate is valid. | ||
| 70 | * You can go slower, but not faster within a given rate set. | ||
| 71 | */ | ||
| 72 | static long omap2_dpllcore_round_rate(unsigned long target_rate) | ||
| 73 | { | ||
| 74 | u32 high, low, core_clk_src; | ||
| 75 | |||
| 76 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 77 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 78 | |||
| 79 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | ||
| 80 | high = curr_prcm_set->dpll_speed * 2; | ||
| 81 | low = curr_prcm_set->dpll_speed; | ||
| 82 | } else { /* DPLL clockout x 2 */ | ||
| 83 | high = curr_prcm_set->dpll_speed; | ||
| 84 | low = curr_prcm_set->dpll_speed / 2; | ||
| 85 | } | ||
| 86 | |||
| 87 | #ifdef DOWN_VARIABLE_DPLL | ||
| 88 | if (target_rate > high) | ||
| 89 | return high; | ||
| 90 | else | ||
| 91 | return target_rate; | ||
| 92 | #else | ||
| 93 | if (target_rate > low) | ||
| 94 | return high; | ||
| 95 | else | ||
| 96 | return low; | ||
| 97 | #endif | ||
| 98 | |||
| 99 | } | ||
| 100 | |||
| 101 | unsigned long omap2_dpllcore_recalc(struct clk *clk) | ||
| 102 | { | ||
| 103 | return omap2xxx_clk_get_core_rate(clk); | ||
| 104 | } | ||
| 105 | |||
| 106 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | ||
| 107 | { | ||
| 108 | u32 cur_rate, low, mult, div, valid_rate, done_rate; | ||
| 109 | u32 bypass = 0; | ||
| 110 | struct prcm_config tmpset; | ||
| 111 | const struct dpll_data *dd; | ||
| 112 | |||
| 113 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | ||
| 114 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 115 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 116 | |||
| 117 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | ||
| 118 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
| 119 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | ||
| 120 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 121 | } else if (rate != cur_rate) { | ||
| 122 | valid_rate = omap2_dpllcore_round_rate(rate); | ||
| 123 | if (valid_rate != rate) | ||
| 124 | return -EINVAL; | ||
| 125 | |||
| 126 | if (mult == 1) | ||
| 127 | low = curr_prcm_set->dpll_speed; | ||
| 128 | else | ||
| 129 | low = curr_prcm_set->dpll_speed / 2; | ||
| 130 | |||
| 131 | dd = clk->dpll_data; | ||
| 132 | if (!dd) | ||
| 133 | return -EINVAL; | ||
| 134 | |||
| 135 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | ||
| 136 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | ||
| 137 | dd->div1_mask); | ||
| 138 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | ||
| 139 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 140 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 141 | if (rate > low) { | ||
| 142 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | ||
| 143 | mult = ((rate / 2) / 1000000); | ||
| 144 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
| 145 | } else { | ||
| 146 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; | ||
| 147 | mult = (rate / 1000000); | ||
| 148 | done_rate = CORE_CLK_SRC_DPLL; | ||
| 149 | } | ||
| 150 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); | ||
| 151 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | ||
| 152 | |||
| 153 | /* Worst case */ | ||
| 154 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; | ||
| 155 | |||
| 156 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | ||
| 157 | bypass = 1; | ||
| 158 | |||
| 159 | /* For omap2xxx_sdrc_init_params() */ | ||
| 160 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 161 | |||
| 162 | /* Force dll lock mode */ | ||
| 163 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | ||
| 164 | bypass); | ||
| 165 | |||
| 166 | /* Errata: ret dll entry state */ | ||
| 167 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
| 168 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
| 169 | } | ||
| 170 | |||
| 171 | return 0; | ||
| 172 | } | ||
| 173 | |||
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c new file mode 100644 index 000000000000..2167be84a5bc --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2xxx osc_clk-specific clock code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | #undef DEBUG | ||
| 19 | |||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | |||
| 26 | #include <plat/clock.h> | ||
| 27 | |||
| 28 | #include "clock.h" | ||
| 29 | #include "clock2xxx.h" | ||
| 30 | #include "prm.h" | ||
| 31 | #include "prm-regbits-24xx.h" | ||
| 32 | |||
| 33 | static int omap2_enable_osc_ck(struct clk *clk) | ||
| 34 | { | ||
| 35 | u32 pcc; | ||
| 36 | |||
| 37 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
| 38 | |||
| 39 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
| 40 | |||
| 41 | return 0; | ||
| 42 | } | ||
| 43 | |||
| 44 | static void omap2_disable_osc_ck(struct clk *clk) | ||
| 45 | { | ||
| 46 | u32 pcc; | ||
| 47 | |||
| 48 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
| 49 | |||
| 50 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
| 51 | } | ||
| 52 | |||
| 53 | const struct clkops clkops_oscck = { | ||
| 54 | .enable = omap2_enable_osc_ck, | ||
| 55 | .disable = omap2_disable_osc_ck, | ||
| 56 | }; | ||
| 57 | |||
| 58 | unsigned long omap2_osc_clk_recalc(struct clk *clk) | ||
| 59 | { | ||
| 60 | return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); | ||
| 61 | } | ||
| 62 | |||
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c new file mode 100644 index 000000000000..822b5a79f457 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2xxx sys_clk-specific clock code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | #undef DEBUG | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <plat/clock.h> | ||
| 26 | |||
| 27 | #include "clock.h" | ||
| 28 | #include "clock2xxx.h" | ||
| 29 | #include "prm.h" | ||
| 30 | #include "prm-regbits-24xx.h" | ||
| 31 | |||
| 32 | void __iomem *prcm_clksrc_ctrl; | ||
| 33 | |||
| 34 | u32 omap2xxx_get_sysclkdiv(void) | ||
| 35 | { | ||
| 36 | u32 div; | ||
| 37 | |||
| 38 | div = __raw_readl(prcm_clksrc_ctrl); | ||
| 39 | div &= OMAP_SYSCLKDIV_MASK; | ||
| 40 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
| 41 | |||
| 42 | return div; | ||
| 43 | } | ||
| 44 | |||
| 45 | unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) | ||
| 46 | { | ||
| 47 | return clk->parent->rate / omap2xxx_get_sysclkdiv(); | ||
| 48 | } | ||
| 49 | |||
| 50 | |||
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c new file mode 100644 index 000000000000..3b1eac4d5390 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | |||
| @@ -0,0 +1,254 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2xxx DVFS virtual clock functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | * | ||
| 18 | * XXX Some of this code should be replaceable by the upcoming OPP layer | ||
| 19 | * code. However, some notion of "rate set" is probably still necessary | ||
| 20 | * for OMAP2xxx at least. Rate sets should be generalized so they can be | ||
| 21 | * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff | ||
| 22 | * has in the past expressed a preference to use rate sets for OPP changes, | ||
| 23 | * rather than dynamically recalculating the clock tree, so if someone wants | ||
| 24 | * this badly enough to write the code to handle it, we should support it | ||
| 25 | * as an option. | ||
| 26 | */ | ||
| 27 | #undef DEBUG | ||
| 28 | |||
| 29 | #include <linux/kernel.h> | ||
| 30 | #include <linux/errno.h> | ||
| 31 | #include <linux/clk.h> | ||
| 32 | #include <linux/io.h> | ||
| 33 | #include <linux/cpufreq.h> | ||
| 34 | |||
| 35 | #include <plat/clock.h> | ||
| 36 | #include <plat/sram.h> | ||
| 37 | #include <plat/sdrc.h> | ||
| 38 | |||
| 39 | #include "clock.h" | ||
| 40 | #include "clock2xxx.h" | ||
| 41 | #include "opp2xxx.h" | ||
| 42 | #include "cm.h" | ||
| 43 | #include "cm-regbits-24xx.h" | ||
| 44 | |||
| 45 | const struct prcm_config *curr_prcm_set; | ||
| 46 | const struct prcm_config *rate_table; | ||
| 47 | |||
| 48 | /** | ||
| 49 | * omap2_table_mpu_recalc - just return the MPU speed | ||
| 50 | * @clk: virt_prcm_set struct clk | ||
| 51 | * | ||
| 52 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | ||
| 53 | */ | ||
| 54 | unsigned long omap2_table_mpu_recalc(struct clk *clk) | ||
| 55 | { | ||
| 56 | return curr_prcm_set->mpu_speed; | ||
| 57 | } | ||
| 58 | |||
| 59 | /* | ||
| 60 | * Look for a rate equal or less than the target rate given a configuration set. | ||
| 61 | * | ||
| 62 | * What's not entirely clear is "which" field represents the key field. | ||
| 63 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | ||
| 64 | * just uses the ARM rates. | ||
| 65 | */ | ||
| 66 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) | ||
| 67 | { | ||
| 68 | const struct prcm_config *ptr; | ||
| 69 | long highest_rate; | ||
| 70 | long sys_ck_rate; | ||
| 71 | |||
| 72 | sys_ck_rate = clk_get_rate(sclk); | ||
| 73 | |||
| 74 | highest_rate = -EINVAL; | ||
| 75 | |||
| 76 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | ||
| 77 | if (!(ptr->flags & cpu_mask)) | ||
| 78 | continue; | ||
| 79 | if (ptr->xtal_speed != sys_ck_rate) | ||
| 80 | continue; | ||
| 81 | |||
| 82 | highest_rate = ptr->mpu_speed; | ||
| 83 | |||
| 84 | /* Can check only after xtal frequency check */ | ||
| 85 | if (ptr->mpu_speed <= rate) | ||
| 86 | break; | ||
| 87 | } | ||
| 88 | return highest_rate; | ||
| 89 | } | ||
| 90 | |||
| 91 | /* Sets basic clocks based on the specified rate */ | ||
| 92 | int omap2_select_table_rate(struct clk *clk, unsigned long rate) | ||
| 93 | { | ||
| 94 | u32 cur_rate, done_rate, bypass = 0, tmp; | ||
| 95 | const struct prcm_config *prcm; | ||
| 96 | unsigned long found_speed = 0; | ||
| 97 | unsigned long flags; | ||
| 98 | long sys_ck_rate; | ||
| 99 | |||
| 100 | sys_ck_rate = clk_get_rate(sclk); | ||
| 101 | |||
| 102 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 103 | if (!(prcm->flags & cpu_mask)) | ||
| 104 | continue; | ||
| 105 | |||
| 106 | if (prcm->xtal_speed != sys_ck_rate) | ||
| 107 | continue; | ||
| 108 | |||
| 109 | if (prcm->mpu_speed <= rate) { | ||
| 110 | found_speed = prcm->mpu_speed; | ||
| 111 | break; | ||
| 112 | } | ||
| 113 | } | ||
| 114 | |||
| 115 | if (!found_speed) { | ||
| 116 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | ||
| 117 | rate / 1000000); | ||
| 118 | return -EINVAL; | ||
| 119 | } | ||
| 120 | |||
| 121 | curr_prcm_set = prcm; | ||
| 122 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | ||
| 123 | |||
| 124 | if (prcm->dpll_speed == cur_rate / 2) { | ||
| 125 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
| 126 | } else if (prcm->dpll_speed == cur_rate * 2) { | ||
| 127 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 128 | } else if (prcm->dpll_speed != cur_rate) { | ||
| 129 | local_irq_save(flags); | ||
| 130 | |||
| 131 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 132 | bypass = 1; | ||
| 133 | |||
| 134 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == | ||
| 135 | CORE_CLK_SRC_DPLL_X2) | ||
| 136 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
| 137 | else | ||
| 138 | done_rate = CORE_CLK_SRC_DPLL; | ||
| 139 | |||
| 140 | /* MPU divider */ | ||
| 141 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); | ||
| 142 | |||
| 143 | /* dsp + iva1 div(2420), iva2.1(2430) */ | ||
| 144 | cm_write_mod_reg(prcm->cm_clksel_dsp, | ||
| 145 | OMAP24XX_DSP_MOD, CM_CLKSEL); | ||
| 146 | |||
| 147 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); | ||
| 148 | |||
| 149 | /* Major subsystem dividers */ | ||
| 150 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | ||
| 151 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, | ||
| 152 | CM_CLKSEL1); | ||
| 153 | |||
| 154 | if (cpu_is_omap2430()) | ||
| 155 | cm_write_mod_reg(prcm->cm_clksel_mdm, | ||
| 156 | OMAP2430_MDM_MOD, CM_CLKSEL); | ||
| 157 | |||
| 158 | /* x2 to enter omap2xxx_sdrc_init_params() */ | ||
| 159 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 160 | |||
| 161 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | ||
| 162 | bypass); | ||
| 163 | |||
| 164 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
| 165 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
| 166 | |||
| 167 | local_irq_restore(flags); | ||
| 168 | } | ||
| 169 | |||
| 170 | return 0; | ||
| 171 | } | ||
| 172 | |||
| 173 | #ifdef CONFIG_CPU_FREQ | ||
| 174 | /* | ||
| 175 | * Walk PRCM rate table and fillout cpufreq freq_table | ||
| 176 | * XXX This should be replaced by an OPP layer in the near future | ||
| 177 | */ | ||
| 178 | static struct cpufreq_frequency_table *freq_table; | ||
| 179 | |||
| 180 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 181 | { | ||
| 182 | const struct prcm_config *prcm; | ||
| 183 | long sys_ck_rate; | ||
| 184 | int i = 0; | ||
| 185 | int tbl_sz = 0; | ||
| 186 | |||
| 187 | if (!cpu_is_omap24xx()) | ||
| 188 | return; | ||
| 189 | |||
| 190 | sys_ck_rate = clk_get_rate(sclk); | ||
| 191 | |||
| 192 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 193 | if (!(prcm->flags & cpu_mask)) | ||
| 194 | continue; | ||
| 195 | if (prcm->xtal_speed != sys_ck_rate) | ||
| 196 | continue; | ||
| 197 | |||
| 198 | /* don't put bypass rates in table */ | ||
| 199 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 200 | continue; | ||
| 201 | |||
| 202 | tbl_sz++; | ||
| 203 | } | ||
| 204 | |||
| 205 | /* | ||
| 206 | * XXX Ensure that we're doing what CPUFreq expects for this error | ||
| 207 | * case and the following one | ||
| 208 | */ | ||
| 209 | if (tbl_sz == 0) { | ||
| 210 | pr_warning("%s: no matching entries in rate_table\n", | ||
| 211 | __func__); | ||
| 212 | return; | ||
| 213 | } | ||
| 214 | |||
| 215 | /* Include the CPUFREQ_TABLE_END terminator entry */ | ||
| 216 | tbl_sz++; | ||
| 217 | |||
| 218 | freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz, | ||
| 219 | GFP_ATOMIC); | ||
| 220 | if (!freq_table) { | ||
| 221 | pr_err("%s: could not kzalloc frequency table\n", __func__); | ||
| 222 | return; | ||
| 223 | } | ||
| 224 | |||
| 225 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 226 | if (!(prcm->flags & cpu_mask)) | ||
| 227 | continue; | ||
| 228 | if (prcm->xtal_speed != sys_ck_rate) | ||
| 229 | continue; | ||
| 230 | |||
| 231 | /* don't put bypass rates in table */ | ||
| 232 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 233 | continue; | ||
| 234 | |||
| 235 | freq_table[i].index = i; | ||
| 236 | freq_table[i].frequency = prcm->mpu_speed / 1000; | ||
| 237 | i++; | ||
| 238 | } | ||
| 239 | |||
| 240 | freq_table[i].index = i; | ||
| 241 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
| 242 | |||
| 243 | *table = &freq_table[0]; | ||
| 244 | } | ||
| 245 | |||
| 246 | void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 247 | { | ||
| 248 | if (!cpu_is_omap24xx()) | ||
| 249 | return; | ||
| 250 | |||
| 251 | kfree(freq_table); | ||
| 252 | } | ||
| 253 | |||
| 254 | #endif | ||
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c new file mode 100644 index 000000000000..b2b1e37bb6bb --- /dev/null +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c | |||
| @@ -0,0 +1,121 @@ | |||
| 1 | /* | ||
| 2 | * OMAP34xx M2 divider clock code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley | ||
| 8 | * Jouni Högander | ||
| 9 | * | ||
| 10 | * Parts of this code are based on code written by | ||
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | #undef DEBUG | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | #include <plat/sram.h> | ||
| 26 | #include <plat/sdrc.h> | ||
| 27 | |||
| 28 | #include "clock.h" | ||
| 29 | #include "clock3xxx.h" | ||
| 30 | #include "clock34xx.h" | ||
| 31 | #include "sdrc.h" | ||
| 32 | |||
| 33 | #define CYCLES_PER_MHZ 1000000 | ||
| 34 | |||
| 35 | /* | ||
| 36 | * CORE DPLL (DPLL3) M2 divider rate programming functions | ||
| 37 | * | ||
| 38 | * These call into SRAM code to do the actual CM writes, since the SDRAM | ||
| 39 | * is clocked from DPLL3. | ||
| 40 | */ | ||
| 41 | |||
| 42 | /** | ||
| 43 | * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider | ||
| 44 | * @clk: struct clk * of DPLL to set | ||
| 45 | * @rate: rounded target rate | ||
| 46 | * | ||
| 47 | * Program the DPLL M2 divider with the rounded target rate. Returns | ||
| 48 | * -EINVAL upon error, or 0 upon success. | ||
| 49 | */ | ||
| 50 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | ||
| 51 | { | ||
| 52 | u32 new_div = 0; | ||
| 53 | u32 unlock_dll = 0; | ||
| 54 | u32 c; | ||
| 55 | unsigned long validrate, sdrcrate, _mpurate; | ||
| 56 | struct omap_sdrc_params *sdrc_cs0; | ||
| 57 | struct omap_sdrc_params *sdrc_cs1; | ||
| 58 | int ret; | ||
| 59 | |||
| 60 | if (!clk || !rate) | ||
| 61 | return -EINVAL; | ||
| 62 | |||
| 63 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | ||
| 64 | if (validrate != rate) | ||
| 65 | return -EINVAL; | ||
| 66 | |||
| 67 | sdrcrate = sdrc_ick_p->rate; | ||
| 68 | if (rate > clk->rate) | ||
| 69 | sdrcrate <<= ((rate / clk->rate) >> 1); | ||
| 70 | else | ||
| 71 | sdrcrate >>= ((clk->rate / rate) >> 1); | ||
| 72 | |||
| 73 | ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); | ||
| 74 | if (ret) | ||
| 75 | return -EINVAL; | ||
| 76 | |||
| 77 | if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { | ||
| 78 | pr_debug("clock: will unlock SDRC DLL\n"); | ||
| 79 | unlock_dll = 1; | ||
| 80 | } | ||
| 81 | |||
| 82 | /* | ||
| 83 | * XXX This only needs to be done when the CPU frequency changes | ||
| 84 | */ | ||
| 85 | _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; | ||
| 86 | c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | ||
| 87 | c += 1; /* for safety */ | ||
| 88 | c *= SDRC_MPURATE_LOOPS; | ||
| 89 | c >>= SDRC_MPURATE_SCALE; | ||
| 90 | if (c == 0) | ||
| 91 | c = 1; | ||
| 92 | |||
| 93 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | ||
| 94 | validrate); | ||
| 95 | pr_debug("clock: SDRC CS0 timing params used:" | ||
| 96 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | ||
| 97 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | ||
| 98 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); | ||
| 99 | if (sdrc_cs1) | ||
| 100 | pr_debug("clock: SDRC CS1 timing params used: " | ||
| 101 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | ||
| 102 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | ||
| 103 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | ||
| 104 | |||
| 105 | if (sdrc_cs1) | ||
| 106 | omap3_configure_core_dpll( | ||
| 107 | new_div, unlock_dll, c, rate > clk->rate, | ||
| 108 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | ||
| 109 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | ||
| 110 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | ||
| 111 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | ||
| 112 | else | ||
| 113 | omap3_configure_core_dpll( | ||
| 114 | new_div, unlock_dll, c, rate > clk->rate, | ||
| 115 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | ||
| 116 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | ||
| 117 | 0, 0, 0, 0); | ||
| 118 | |||
| 119 | return 0; | ||
| 120 | } | ||
| 121 | |||
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c new file mode 100644 index 000000000000..e50812dd03fd --- /dev/null +++ b/arch/arm/mach-omap2/clkt_clksel.c | |||
| @@ -0,0 +1,409 @@ | |||
| 1 | /* | ||
| 2 | * clkt_clksel.c - OMAP2/3/4 clksel clock functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * XXX At some point these clksel clocks should be split into | ||
| 16 | * "divider" clocks and "mux" clocks to better match the hardware. | ||
| 17 | * | ||
| 18 | * XXX Currently these clocks are only used in the OMAP2/3/4 code, but | ||
| 19 | * many of the OMAP1 clocks should be convertible to use this | ||
| 20 | * mechanism. | ||
| 21 | */ | ||
| 22 | #undef DEBUG | ||
| 23 | |||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/errno.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | #include <linux/io.h> | ||
| 28 | |||
| 29 | #include <plat/clock.h> | ||
| 30 | |||
| 31 | #include "clock.h" | ||
| 32 | #include "cm.h" | ||
| 33 | #include "cm-regbits-24xx.h" | ||
| 34 | #include "cm-regbits-34xx.h" | ||
| 35 | |||
| 36 | /* Private functions */ | ||
| 37 | |||
| 38 | /** | ||
| 39 | * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent | ||
| 40 | * @clk: OMAP struct clk ptr to inspect | ||
| 41 | * @src_clk: OMAP struct clk ptr of the parent clk to search for | ||
| 42 | * | ||
| 43 | * Scan the struct clksel array associated with the clock to find | ||
| 44 | * the element associated with the supplied parent clock address. | ||
| 45 | * Returns a pointer to the struct clksel on success or NULL on error. | ||
| 46 | */ | ||
| 47 | static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk, | ||
| 48 | struct clk *src_clk) | ||
| 49 | { | ||
| 50 | const struct clksel *clks; | ||
| 51 | |||
| 52 | if (!clk->clksel) | ||
| 53 | return NULL; | ||
| 54 | |||
| 55 | for (clks = clk->clksel; clks->parent; clks++) { | ||
| 56 | if (clks->parent == src_clk) | ||
| 57 | break; /* Found the requested parent */ | ||
| 58 | } | ||
| 59 | |||
| 60 | if (!clks->parent) { | ||
| 61 | printk(KERN_ERR "clock: Could not find parent clock %s in " | ||
| 62 | "clksel array of clock %s\n", src_clk->name, | ||
| 63 | clk->name); | ||
| 64 | return NULL; | ||
| 65 | } | ||
| 66 | |||
| 67 | return clks; | ||
| 68 | } | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Converts encoded control register address into a full address | ||
| 72 | * On error, the return value (parent_div) will be 0. | ||
| 73 | */ | ||
| 74 | static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, | ||
| 75 | u32 *field_val) | ||
| 76 | { | ||
| 77 | const struct clksel *clks; | ||
| 78 | const struct clksel_rate *clkr; | ||
| 79 | |||
| 80 | clks = _omap2_get_clksel_by_parent(clk, src_clk); | ||
| 81 | if (!clks) | ||
| 82 | return 0; | ||
| 83 | |||
| 84 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 85 | if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) | ||
| 86 | break; /* Found the default rate for this platform */ | ||
| 87 | } | ||
| 88 | |||
| 89 | if (!clkr->div) { | ||
| 90 | printk(KERN_ERR "clock: Could not find default rate for " | ||
| 91 | "clock %s parent %s\n", clk->name, | ||
| 92 | src_clk->parent->name); | ||
| 93 | return 0; | ||
| 94 | } | ||
| 95 | |||
| 96 | /* Should never happen. Add a clksel mask to the struct clk. */ | ||
| 97 | WARN_ON(clk->clksel_mask == 0); | ||
| 98 | |||
| 99 | *field_val = clkr->val; | ||
| 100 | |||
| 101 | return clkr->div; | ||
| 102 | } | ||
| 103 | |||
| 104 | |||
| 105 | /* Public functions */ | ||
| 106 | |||
| 107 | /** | ||
| 108 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware | ||
| 109 | * @clk: OMAP clock struct ptr to use | ||
| 110 | * | ||
| 111 | * Given a pointer to a source-selectable struct clk, read the hardware | ||
| 112 | * register and determine what its parent is currently set to. Update the | ||
| 113 | * clk->parent field with the appropriate clk ptr. | ||
| 114 | */ | ||
| 115 | void omap2_init_clksel_parent(struct clk *clk) | ||
| 116 | { | ||
| 117 | const struct clksel *clks; | ||
| 118 | const struct clksel_rate *clkr; | ||
| 119 | u32 r, found = 0; | ||
| 120 | |||
| 121 | if (!clk->clksel) | ||
| 122 | return; | ||
| 123 | |||
| 124 | r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | ||
| 125 | r >>= __ffs(clk->clksel_mask); | ||
| 126 | |||
| 127 | for (clks = clk->clksel; clks->parent && !found; clks++) { | ||
| 128 | for (clkr = clks->rates; clkr->div && !found; clkr++) { | ||
| 129 | if ((clkr->flags & cpu_mask) && (clkr->val == r)) { | ||
| 130 | if (clk->parent != clks->parent) { | ||
| 131 | pr_debug("clock: inited %s parent " | ||
| 132 | "to %s (was %s)\n", | ||
| 133 | clk->name, clks->parent->name, | ||
| 134 | ((clk->parent) ? | ||
| 135 | clk->parent->name : "NULL")); | ||
| 136 | clk_reparent(clk, clks->parent); | ||
| 137 | }; | ||
| 138 | found = 1; | ||
| 139 | } | ||
| 140 | } | ||
| 141 | } | ||
| 142 | |||
| 143 | if (!found) | ||
| 144 | printk(KERN_ERR "clock: init parent: could not find " | ||
| 145 | "regval %0x for clock %s\n", r, clk->name); | ||
| 146 | |||
| 147 | return; | ||
| 148 | } | ||
| 149 | |||
| 150 | /* | ||
| 151 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | ||
| 152 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | ||
| 153 | */ | ||
| 154 | unsigned long omap2_clksel_recalc(struct clk *clk) | ||
| 155 | { | ||
| 156 | unsigned long rate; | ||
| 157 | u32 div = 0; | ||
| 158 | |||
| 159 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); | ||
| 160 | |||
| 161 | div = omap2_clksel_get_divisor(clk); | ||
| 162 | if (div == 0) | ||
| 163 | return clk->rate; | ||
| 164 | |||
| 165 | rate = clk->parent->rate / div; | ||
| 166 | |||
| 167 | pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); | ||
| 168 | |||
| 169 | return rate; | ||
| 170 | } | ||
| 171 | |||
| 172 | /** | ||
| 173 | * omap2_clksel_round_rate_div - find divisor for the given clock and rate | ||
| 174 | * @clk: OMAP struct clk to use | ||
| 175 | * @target_rate: desired clock rate | ||
| 176 | * @new_div: ptr to where we should store the divisor | ||
| 177 | * | ||
| 178 | * Finds 'best' divider value in an array based on the source and target | ||
| 179 | * rates. The divider array must be sorted with smallest divider first. | ||
| 180 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | ||
| 181 | * they are only settable as part of virtual_prcm set. | ||
| 182 | * | ||
| 183 | * Returns the rounded clock rate or returns 0xffffffff on error. | ||
| 184 | */ | ||
| 185 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | ||
| 186 | u32 *new_div) | ||
| 187 | { | ||
| 188 | unsigned long test_rate; | ||
| 189 | const struct clksel *clks; | ||
| 190 | const struct clksel_rate *clkr; | ||
| 191 | u32 last_div = 0; | ||
| 192 | |||
| 193 | pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", | ||
| 194 | clk->name, target_rate); | ||
| 195 | |||
| 196 | *new_div = 1; | ||
| 197 | |||
| 198 | clks = _omap2_get_clksel_by_parent(clk, clk->parent); | ||
| 199 | if (!clks) | ||
| 200 | return ~0; | ||
| 201 | |||
| 202 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 203 | if (!(clkr->flags & cpu_mask)) | ||
| 204 | continue; | ||
| 205 | |||
| 206 | /* Sanity check */ | ||
| 207 | if (clkr->div <= last_div) | ||
| 208 | pr_err("clock: clksel_rate table not sorted " | ||
| 209 | "for clock %s", clk->name); | ||
| 210 | |||
| 211 | last_div = clkr->div; | ||
| 212 | |||
| 213 | test_rate = clk->parent->rate / clkr->div; | ||
| 214 | |||
| 215 | if (test_rate <= target_rate) | ||
| 216 | break; /* found it */ | ||
| 217 | } | ||
| 218 | |||
| 219 | if (!clkr->div) { | ||
| 220 | pr_err("clock: Could not find divisor for target " | ||
| 221 | "rate %ld for clock %s parent %s\n", target_rate, | ||
| 222 | clk->name, clk->parent->name); | ||
| 223 | return ~0; | ||
| 224 | } | ||
| 225 | |||
| 226 | *new_div = clkr->div; | ||
| 227 | |||
| 228 | pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, | ||
| 229 | (clk->parent->rate / clkr->div)); | ||
| 230 | |||
| 231 | return clk->parent->rate / clkr->div; | ||
| 232 | } | ||
| 233 | |||
| 234 | /** | ||
| 235 | * omap2_clksel_round_rate - find rounded rate for the given clock and rate | ||
| 236 | * @clk: OMAP struct clk to use | ||
| 237 | * @target_rate: desired clock rate | ||
| 238 | * | ||
| 239 | * Compatibility wrapper for OMAP clock framework | ||
| 240 | * Finds best target rate based on the source clock and possible dividers. | ||
| 241 | * rates. The divider array must be sorted with smallest divider first. | ||
| 242 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | ||
| 243 | * they are only settable as part of virtual_prcm set. | ||
| 244 | * | ||
| 245 | * Returns the rounded clock rate or returns 0xffffffff on error. | ||
| 246 | */ | ||
| 247 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | ||
| 248 | { | ||
| 249 | u32 new_div; | ||
| 250 | |||
| 251 | return omap2_clksel_round_rate_div(clk, target_rate, &new_div); | ||
| 252 | } | ||
| 253 | |||
| 254 | |||
| 255 | /* Given a clock and a rate apply a clock specific rounding function */ | ||
| 256 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 257 | { | ||
| 258 | if (clk->round_rate) | ||
| 259 | return clk->round_rate(clk, rate); | ||
| 260 | |||
| 261 | return clk->rate; | ||
| 262 | } | ||
| 263 | |||
| 264 | /** | ||
| 265 | * omap2_clksel_to_divisor() - turn clksel field value into integer divider | ||
| 266 | * @clk: OMAP struct clk to use | ||
| 267 | * @field_val: register field value to find | ||
| 268 | * | ||
| 269 | * Given a struct clk of a rate-selectable clksel clock, and a register field | ||
| 270 | * value to search for, find the corresponding clock divisor. The register | ||
| 271 | * field value should be pre-masked and shifted down so the LSB is at bit 0 | ||
| 272 | * before calling. Returns 0 on error | ||
| 273 | */ | ||
| 274 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) | ||
| 275 | { | ||
| 276 | const struct clksel *clks; | ||
| 277 | const struct clksel_rate *clkr; | ||
| 278 | |||
| 279 | clks = _omap2_get_clksel_by_parent(clk, clk->parent); | ||
| 280 | if (!clks) | ||
| 281 | return 0; | ||
| 282 | |||
| 283 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 284 | if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) | ||
| 285 | break; | ||
| 286 | } | ||
| 287 | |||
| 288 | if (!clkr->div) { | ||
| 289 | printk(KERN_ERR "clock: Could not find fieldval %d for " | ||
| 290 | "clock %s parent %s\n", field_val, clk->name, | ||
| 291 | clk->parent->name); | ||
| 292 | return 0; | ||
| 293 | } | ||
| 294 | |||
| 295 | return clkr->div; | ||
| 296 | } | ||
| 297 | |||
| 298 | /** | ||
| 299 | * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value | ||
| 300 | * @clk: OMAP struct clk to use | ||
| 301 | * @div: integer divisor to search for | ||
| 302 | * | ||
| 303 | * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, | ||
| 304 | * find the corresponding register field value. The return register value is | ||
| 305 | * the value before left-shifting. Returns ~0 on error | ||
| 306 | */ | ||
| 307 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | ||
| 308 | { | ||
| 309 | const struct clksel *clks; | ||
| 310 | const struct clksel_rate *clkr; | ||
| 311 | |||
| 312 | /* should never happen */ | ||
| 313 | WARN_ON(div == 0); | ||
| 314 | |||
| 315 | clks = _omap2_get_clksel_by_parent(clk, clk->parent); | ||
| 316 | if (!clks) | ||
| 317 | return ~0; | ||
| 318 | |||
| 319 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 320 | if ((clkr->flags & cpu_mask) && (clkr->div == div)) | ||
| 321 | break; | ||
| 322 | } | ||
| 323 | |||
| 324 | if (!clkr->div) { | ||
| 325 | printk(KERN_ERR "clock: Could not find divisor %d for " | ||
| 326 | "clock %s parent %s\n", div, clk->name, | ||
| 327 | clk->parent->name); | ||
| 328 | return ~0; | ||
| 329 | } | ||
| 330 | |||
| 331 | return clkr->val; | ||
| 332 | } | ||
| 333 | |||
| 334 | /** | ||
| 335 | * omap2_clksel_get_divisor - get current divider applied to parent clock. | ||
| 336 | * @clk: OMAP struct clk to use. | ||
| 337 | * | ||
| 338 | * Returns the integer divisor upon success or 0 on error. | ||
| 339 | */ | ||
| 340 | u32 omap2_clksel_get_divisor(struct clk *clk) | ||
| 341 | { | ||
| 342 | u32 v; | ||
| 343 | |||
| 344 | if (!clk->clksel_mask) | ||
| 345 | return 0; | ||
| 346 | |||
| 347 | v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | ||
| 348 | v >>= __ffs(clk->clksel_mask); | ||
| 349 | |||
| 350 | return omap2_clksel_to_divisor(clk, v); | ||
| 351 | } | ||
| 352 | |||
| 353 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | ||
| 354 | { | ||
| 355 | u32 v, field_val, validrate, new_div = 0; | ||
| 356 | |||
| 357 | if (!clk->clksel_mask) | ||
| 358 | return -EINVAL; | ||
| 359 | |||
| 360 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | ||
| 361 | if (validrate != rate) | ||
| 362 | return -EINVAL; | ||
| 363 | |||
| 364 | field_val = omap2_divisor_to_clksel(clk, new_div); | ||
| 365 | if (field_val == ~0) | ||
| 366 | return -EINVAL; | ||
| 367 | |||
| 368 | v = __raw_readl(clk->clksel_reg); | ||
| 369 | v &= ~clk->clksel_mask; | ||
| 370 | v |= field_val << __ffs(clk->clksel_mask); | ||
| 371 | __raw_writel(v, clk->clksel_reg); | ||
| 372 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | ||
| 373 | |||
| 374 | clk->rate = clk->parent->rate / new_div; | ||
| 375 | |||
| 376 | return 0; | ||
| 377 | } | ||
| 378 | |||
| 379 | int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) | ||
| 380 | { | ||
| 381 | u32 field_val, v, parent_div; | ||
| 382 | |||
| 383 | if (!clk->clksel) | ||
| 384 | return -EINVAL; | ||
| 385 | |||
| 386 | parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); | ||
| 387 | if (!parent_div) | ||
| 388 | return -EINVAL; | ||
| 389 | |||
| 390 | /* Set new source value (previous dividers if any in effect) */ | ||
| 391 | v = __raw_readl(clk->clksel_reg); | ||
| 392 | v &= ~clk->clksel_mask; | ||
| 393 | v |= field_val << __ffs(clk->clksel_mask); | ||
| 394 | __raw_writel(v, clk->clksel_reg); | ||
| 395 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | ||
| 396 | |||
| 397 | clk_reparent(clk, new_parent); | ||
| 398 | |||
| 399 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ | ||
| 400 | clk->rate = new_parent->rate; | ||
| 401 | |||
| 402 | if (parent_div > 0) | ||
| 403 | clk->rate /= parent_div; | ||
| 404 | |||
| 405 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | ||
| 406 | clk->name, clk->parent->name, clk->rate); | ||
| 407 | |||
| 408 | return 0; | ||
| 409 | } | ||
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c new file mode 100644 index 000000000000..6ce512e902c6 --- /dev/null +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
| @@ -0,0 +1,386 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3/4 DPLL clock functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | #undef DEBUG | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/errno.h> | ||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <asm/div64.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | |||
| 26 | #include "clock.h" | ||
| 27 | #include "cm.h" | ||
| 28 | #include "cm-regbits-24xx.h" | ||
| 29 | #include "cm-regbits-34xx.h" | ||
| 30 | |||
| 31 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ | ||
| 32 | #define DPLL_MIN_MULTIPLIER 2 | ||
| 33 | #define DPLL_MIN_DIVIDER 1 | ||
| 34 | |||
| 35 | /* Possible error results from _dpll_test_mult */ | ||
| 36 | #define DPLL_MULT_UNDERFLOW -1 | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. | ||
| 40 | * The higher the scale factor, the greater the risk of arithmetic overflow, | ||
| 41 | * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR | ||
| 42 | * must be a power of DPLL_SCALE_BASE. | ||
| 43 | */ | ||
| 44 | #define DPLL_SCALE_FACTOR 64 | ||
| 45 | #define DPLL_SCALE_BASE 2 | ||
| 46 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | ||
| 47 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | ||
| 48 | |||
| 49 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ | ||
| 50 | #define DPLL_FINT_BAND1_MIN 750000 | ||
| 51 | #define DPLL_FINT_BAND1_MAX 2100000 | ||
| 52 | #define DPLL_FINT_BAND2_MIN 7500000 | ||
| 53 | #define DPLL_FINT_BAND2_MAX 21000000 | ||
| 54 | |||
| 55 | /* _dpll_test_fint() return codes */ | ||
| 56 | #define DPLL_FINT_UNDERFLOW -1 | ||
| 57 | #define DPLL_FINT_INVALID -2 | ||
| 58 | |||
| 59 | /* Private functions */ | ||
| 60 | |||
| 61 | /* | ||
| 62 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL | ||
| 63 | * @clk: DPLL struct clk to test | ||
| 64 | * @n: divider value (N) to test | ||
| 65 | * | ||
| 66 | * Tests whether a particular divider @n will result in a valid DPLL | ||
| 67 | * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter | ||
| 68 | * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate | ||
| 69 | * (assuming that it is counting N upwards), or -2 if the enclosing loop | ||
| 70 | * should skip to the next iteration (again assuming N is increasing). | ||
| 71 | */ | ||
| 72 | static int _dpll_test_fint(struct clk *clk, u8 n) | ||
| 73 | { | ||
| 74 | struct dpll_data *dd; | ||
| 75 | long fint; | ||
| 76 | int ret = 0; | ||
| 77 | |||
| 78 | dd = clk->dpll_data; | ||
| 79 | |||
| 80 | /* DPLL divider must result in a valid jitter correction val */ | ||
| 81 | fint = clk->parent->rate / (n + 1); | ||
| 82 | if (fint < DPLL_FINT_BAND1_MIN) { | ||
| 83 | |||
| 84 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 85 | "lowering max_divider\n", n); | ||
| 86 | dd->max_divider = n; | ||
| 87 | ret = DPLL_FINT_UNDERFLOW; | ||
| 88 | |||
| 89 | } else if (fint > DPLL_FINT_BAND1_MAX && | ||
| 90 | fint < DPLL_FINT_BAND2_MIN) { | ||
| 91 | |||
| 92 | pr_debug("rejecting n=%d due to Fint failure\n", n); | ||
| 93 | ret = DPLL_FINT_INVALID; | ||
| 94 | |||
| 95 | } else if (fint > DPLL_FINT_BAND2_MAX) { | ||
| 96 | |||
| 97 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 98 | "boosting min_divider\n", n); | ||
| 99 | dd->min_divider = n; | ||
| 100 | ret = DPLL_FINT_INVALID; | ||
| 101 | |||
| 102 | } | ||
| 103 | |||
| 104 | return ret; | ||
| 105 | } | ||
| 106 | |||
| 107 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, | ||
| 108 | unsigned int m, unsigned int n) | ||
| 109 | { | ||
| 110 | unsigned long long num; | ||
| 111 | |||
| 112 | num = (unsigned long long)parent_rate * m; | ||
| 113 | do_div(num, n); | ||
| 114 | return num; | ||
| 115 | } | ||
| 116 | |||
| 117 | /* | ||
| 118 | * _dpll_test_mult - test a DPLL multiplier value | ||
| 119 | * @m: pointer to the DPLL m (multiplier) value under test | ||
| 120 | * @n: current DPLL n (divider) value under test | ||
| 121 | * @new_rate: pointer to storage for the resulting rounded rate | ||
| 122 | * @target_rate: the desired DPLL rate | ||
| 123 | * @parent_rate: the DPLL's parent clock rate | ||
| 124 | * | ||
| 125 | * This code tests a DPLL multiplier value, ensuring that the | ||
| 126 | * resulting rate will not be higher than the target_rate, and that | ||
| 127 | * the multiplier value itself is valid for the DPLL. Initially, the | ||
| 128 | * integer pointed to by the m argument should be prescaled by | ||
| 129 | * multiplying by DPLL_SCALE_FACTOR. The code will replace this with | ||
| 130 | * a non-scaled m upon return. This non-scaled m will result in a | ||
| 131 | * new_rate as close as possible to target_rate (but not greater than | ||
| 132 | * target_rate) given the current (parent_rate, n, prescaled m) | ||
| 133 | * triple. Returns DPLL_MULT_UNDERFLOW in the event that the | ||
| 134 | * non-scaled m attempted to underflow, which can allow the calling | ||
| 135 | * function to bail out early; or 0 upon success. | ||
| 136 | */ | ||
| 137 | static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | ||
| 138 | unsigned long target_rate, | ||
| 139 | unsigned long parent_rate) | ||
| 140 | { | ||
| 141 | int r = 0, carry = 0; | ||
| 142 | |||
| 143 | /* Unscale m and round if necessary */ | ||
| 144 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) | ||
| 145 | carry = 1; | ||
| 146 | *m = (*m / DPLL_SCALE_FACTOR) + carry; | ||
| 147 | |||
| 148 | /* | ||
| 149 | * The new rate must be <= the target rate to avoid programming | ||
| 150 | * a rate that is impossible for the hardware to handle | ||
| 151 | */ | ||
| 152 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | ||
| 153 | if (*new_rate > target_rate) { | ||
| 154 | (*m)--; | ||
| 155 | *new_rate = 0; | ||
| 156 | } | ||
| 157 | |||
| 158 | /* Guard against m underflow */ | ||
| 159 | if (*m < DPLL_MIN_MULTIPLIER) { | ||
| 160 | *m = DPLL_MIN_MULTIPLIER; | ||
| 161 | *new_rate = 0; | ||
| 162 | r = DPLL_MULT_UNDERFLOW; | ||
| 163 | } | ||
| 164 | |||
| 165 | if (*new_rate == 0) | ||
| 166 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | ||
| 167 | |||
| 168 | return r; | ||
| 169 | } | ||
| 170 | |||
| 171 | /* Public functions */ | ||
| 172 | |||
| 173 | void omap2_init_dpll_parent(struct clk *clk) | ||
| 174 | { | ||
| 175 | u32 v; | ||
| 176 | struct dpll_data *dd; | ||
| 177 | |||
| 178 | dd = clk->dpll_data; | ||
| 179 | if (!dd) | ||
| 180 | return; | ||
| 181 | |||
| 182 | /* Return bypass rate if DPLL is bypassed */ | ||
| 183 | v = __raw_readl(dd->control_reg); | ||
| 184 | v &= dd->enable_mask; | ||
| 185 | v >>= __ffs(dd->enable_mask); | ||
| 186 | |||
| 187 | /* Reparent in case the dpll is in bypass */ | ||
| 188 | if (cpu_is_omap24xx()) { | ||
| 189 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
| 190 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
| 191 | clk_reparent(clk, dd->clk_bypass); | ||
| 192 | } else if (cpu_is_omap34xx()) { | ||
| 193 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
| 194 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
| 195 | clk_reparent(clk, dd->clk_bypass); | ||
| 196 | } else if (cpu_is_omap44xx()) { | ||
| 197 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
| 198 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
| 199 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
| 200 | clk_reparent(clk, dd->clk_bypass); | ||
| 201 | } | ||
| 202 | return; | ||
| 203 | } | ||
| 204 | |||
| 205 | /** | ||
| 206 | * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate | ||
| 207 | * @clk: struct clk * of a DPLL | ||
| 208 | * | ||
| 209 | * DPLLs can be locked or bypassed - basically, enabled or disabled. | ||
| 210 | * When locked, the DPLL output depends on the M and N values. When | ||
| 211 | * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock | ||
| 212 | * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and | ||
| 213 | * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively | ||
| 214 | * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. | ||
| 215 | * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is | ||
| 216 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 | ||
| 217 | * if the clock @clk is not a DPLL. | ||
| 218 | */ | ||
| 219 | u32 omap2_get_dpll_rate(struct clk *clk) | ||
| 220 | { | ||
| 221 | long long dpll_clk; | ||
| 222 | u32 dpll_mult, dpll_div, v; | ||
| 223 | struct dpll_data *dd; | ||
| 224 | |||
| 225 | dd = clk->dpll_data; | ||
| 226 | if (!dd) | ||
| 227 | return 0; | ||
| 228 | |||
| 229 | /* Return bypass rate if DPLL is bypassed */ | ||
| 230 | v = __raw_readl(dd->control_reg); | ||
| 231 | v &= dd->enable_mask; | ||
| 232 | v >>= __ffs(dd->enable_mask); | ||
| 233 | |||
| 234 | if (cpu_is_omap24xx()) { | ||
| 235 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
| 236 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
| 237 | return dd->clk_bypass->rate; | ||
| 238 | } else if (cpu_is_omap34xx()) { | ||
| 239 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
| 240 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
| 241 | return dd->clk_bypass->rate; | ||
| 242 | } else if (cpu_is_omap44xx()) { | ||
| 243 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
| 244 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
| 245 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
| 246 | return dd->clk_bypass->rate; | ||
| 247 | } | ||
| 248 | |||
| 249 | v = __raw_readl(dd->mult_div1_reg); | ||
| 250 | dpll_mult = v & dd->mult_mask; | ||
| 251 | dpll_mult >>= __ffs(dd->mult_mask); | ||
| 252 | dpll_div = v & dd->div1_mask; | ||
| 253 | dpll_div >>= __ffs(dd->div1_mask); | ||
| 254 | |||
| 255 | dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; | ||
| 256 | do_div(dpll_clk, dpll_div + 1); | ||
| 257 | |||
| 258 | return dpll_clk; | ||
| 259 | } | ||
| 260 | |||
| 261 | /* DPLL rate rounding code */ | ||
| 262 | |||
| 263 | /** | ||
| 264 | * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding | ||
| 265 | * @clk: struct clk * of the DPLL | ||
| 266 | * @tolerance: maximum rate error tolerance | ||
| 267 | * | ||
| 268 | * Set the maximum DPLL rate error tolerance for the rate rounding | ||
| 269 | * algorithm. The rate tolerance is an attempt to balance DPLL power | ||
| 270 | * saving (the least divider value "n") vs. rate fidelity (the least | ||
| 271 | * difference between the desired DPLL target rate and the rounded | ||
| 272 | * rate out of the algorithm). So, increasing the tolerance is likely | ||
| 273 | * to decrease DPLL power consumption and increase DPLL rate error. | ||
| 274 | * Returns -EINVAL if provided a null clock ptr or a clk that is not a | ||
| 275 | * DPLL; or 0 upon success. | ||
| 276 | */ | ||
| 277 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) | ||
| 278 | { | ||
| 279 | if (!clk || !clk->dpll_data) | ||
| 280 | return -EINVAL; | ||
| 281 | |||
| 282 | clk->dpll_data->rate_tolerance = tolerance; | ||
| 283 | |||
| 284 | return 0; | ||
| 285 | } | ||
| 286 | |||
| 287 | /** | ||
| 288 | * omap2_dpll_round_rate - round a target rate for an OMAP DPLL | ||
| 289 | * @clk: struct clk * for a DPLL | ||
| 290 | * @target_rate: desired DPLL clock rate | ||
| 291 | * | ||
| 292 | * Given a DPLL, a desired target rate, and a rate tolerance, round | ||
| 293 | * the target rate to a possible, programmable rate for this DPLL. | ||
| 294 | * Rate tolerance is assumed to be set by the caller before this | ||
| 295 | * function is called. Attempts to select the minimum possible n | ||
| 296 | * within the tolerance to reduce power consumption. Stores the | ||
| 297 | * computed (m, n) in the DPLL's dpll_data structure so set_rate() | ||
| 298 | * will not need to call this (expensive) function again. Returns ~0 | ||
| 299 | * if the target rate cannot be rounded, either because the rate is | ||
| 300 | * too low or because the rate tolerance is set too tightly; or the | ||
| 301 | * rounded rate upon success. | ||
| 302 | */ | ||
| 303 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | ||
| 304 | { | ||
| 305 | int m, n, r, e, scaled_max_m; | ||
| 306 | unsigned long scaled_rt_rp, new_rate; | ||
| 307 | int min_e = -1, min_e_m = -1, min_e_n = -1; | ||
| 308 | struct dpll_data *dd; | ||
| 309 | |||
| 310 | if (!clk || !clk->dpll_data) | ||
| 311 | return ~0; | ||
| 312 | |||
| 313 | dd = clk->dpll_data; | ||
| 314 | |||
| 315 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " | ||
| 316 | "%ld\n", clk->name, target_rate); | ||
| 317 | |||
| 318 | scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); | ||
| 319 | scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; | ||
| 320 | |||
| 321 | dd->last_rounded_rate = 0; | ||
| 322 | |||
| 323 | for (n = dd->min_divider; n <= dd->max_divider; n++) { | ||
| 324 | |||
| 325 | /* Is the (input clk, divider) pair valid for the DPLL? */ | ||
| 326 | r = _dpll_test_fint(clk, n); | ||
| 327 | if (r == DPLL_FINT_UNDERFLOW) | ||
| 328 | break; | ||
| 329 | else if (r == DPLL_FINT_INVALID) | ||
| 330 | continue; | ||
| 331 | |||
| 332 | /* Compute the scaled DPLL multiplier, based on the divider */ | ||
| 333 | m = scaled_rt_rp * n; | ||
| 334 | |||
| 335 | /* | ||
| 336 | * Since we're counting n up, a m overflow means we | ||
| 337 | * can bail out completely (since as n increases in | ||
| 338 | * the next iteration, there's no way that m can | ||
| 339 | * increase beyond the current m) | ||
| 340 | */ | ||
| 341 | if (m > scaled_max_m) | ||
| 342 | break; | ||
| 343 | |||
| 344 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, | ||
| 345 | dd->clk_ref->rate); | ||
| 346 | |||
| 347 | /* m can't be set low enough for this n - try with a larger n */ | ||
| 348 | if (r == DPLL_MULT_UNDERFLOW) | ||
| 349 | continue; | ||
| 350 | |||
| 351 | e = target_rate - new_rate; | ||
| 352 | pr_debug("clock: n = %d: m = %d: rate error is %d " | ||
| 353 | "(new_rate = %ld)\n", n, m, e, new_rate); | ||
| 354 | |||
| 355 | if (min_e == -1 || | ||
| 356 | min_e >= (int)(abs(e) - dd->rate_tolerance)) { | ||
| 357 | min_e = e; | ||
| 358 | min_e_m = m; | ||
| 359 | min_e_n = n; | ||
| 360 | |||
| 361 | pr_debug("clock: found new least error %d\n", min_e); | ||
| 362 | |||
| 363 | /* We found good settings -- bail out now */ | ||
| 364 | if (min_e <= dd->rate_tolerance) | ||
| 365 | break; | ||
| 366 | } | ||
| 367 | } | ||
| 368 | |||
| 369 | if (min_e < 0) { | ||
| 370 | pr_debug("clock: error: target rate or tolerance too low\n"); | ||
| 371 | return ~0; | ||
| 372 | } | ||
| 373 | |||
| 374 | dd->last_rounded_m = min_e_m; | ||
| 375 | dd->last_rounded_n = min_e_n; | ||
| 376 | dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, | ||
| 377 | min_e_m, min_e_n); | ||
| 378 | |||
| 379 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", | ||
| 380 | min_e, min_e_m, min_e_n); | ||
| 381 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", | ||
| 382 | dd->last_rounded_rate, target_rate); | ||
| 383 | |||
| 384 | return dd->last_rounded_rate; | ||
| 385 | } | ||
| 386 | |||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 759c72a48f7f..a6d0b34b7990 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * linux/arch/arm/mach-omap2/clock.c | 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2008 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Contacts: | 7 | * Contacts: |
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| @@ -14,11 +14,10 @@ | |||
| 14 | */ | 14 | */ |
| 15 | #undef DEBUG | 15 | #undef DEBUG |
| 16 | 16 | ||
| 17 | #include <linux/module.h> | ||
| 18 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 19 | #include <linux/device.h> | ||
| 20 | #include <linux/list.h> | 18 | #include <linux/list.h> |
| 21 | #include <linux/errno.h> | 19 | #include <linux/errno.h> |
| 20 | #include <linux/err.h> | ||
| 22 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
| 23 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 24 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| @@ -28,10 +27,7 @@ | |||
| 28 | #include <plat/clockdomain.h> | 27 | #include <plat/clockdomain.h> |
| 29 | #include <plat/cpu.h> | 28 | #include <plat/cpu.h> |
| 30 | #include <plat/prcm.h> | 29 | #include <plat/prcm.h> |
| 31 | #include <asm/div64.h> | ||
| 32 | 30 | ||
| 33 | #include <plat/sdrc.h> | ||
| 34 | #include "sdrc.h" | ||
| 35 | #include "clock.h" | 31 | #include "clock.h" |
| 36 | #include "prm.h" | 32 | #include "prm.h" |
| 37 | #include "prm-regbits-24xx.h" | 33 | #include "prm-regbits-24xx.h" |
| @@ -39,140 +35,44 @@ | |||
| 39 | #include "cm-regbits-24xx.h" | 35 | #include "cm-regbits-24xx.h" |
| 40 | #include "cm-regbits-34xx.h" | 36 | #include "cm-regbits-34xx.h" |
| 41 | 37 | ||
| 42 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ | 38 | u8 cpu_mask; |
| 43 | #define DPLL_MIN_MULTIPLIER 1 | ||
| 44 | #define DPLL_MIN_DIVIDER 1 | ||
| 45 | |||
| 46 | /* Possible error results from _dpll_test_mult */ | ||
| 47 | #define DPLL_MULT_UNDERFLOW -1 | ||
| 48 | 39 | ||
| 49 | /* | 40 | /* |
| 50 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. | 41 | * OMAP2+ specific clock functions |
| 51 | * The higher the scale factor, the greater the risk of arithmetic overflow, | ||
| 52 | * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR | ||
| 53 | * must be a power of DPLL_SCALE_BASE. | ||
| 54 | */ | 42 | */ |
| 55 | #define DPLL_SCALE_FACTOR 64 | ||
| 56 | #define DPLL_SCALE_BASE 2 | ||
| 57 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | ||
| 58 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | ||
| 59 | |||
| 60 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ | ||
| 61 | #define DPLL_FINT_BAND1_MIN 750000 | ||
| 62 | #define DPLL_FINT_BAND1_MAX 2100000 | ||
| 63 | #define DPLL_FINT_BAND2_MIN 7500000 | ||
| 64 | #define DPLL_FINT_BAND2_MAX 21000000 | ||
| 65 | |||
| 66 | /* _dpll_test_fint() return codes */ | ||
| 67 | #define DPLL_FINT_UNDERFLOW -1 | ||
| 68 | #define DPLL_FINT_INVALID -2 | ||
| 69 | |||
| 70 | u8 cpu_mask; | ||
| 71 | |||
| 72 | /*------------------------------------------------------------------------- | ||
| 73 | * OMAP2/3/4 specific clock functions | ||
| 74 | *-------------------------------------------------------------------------*/ | ||
| 75 | |||
| 76 | void omap2_init_dpll_parent(struct clk *clk) | ||
| 77 | { | ||
| 78 | u32 v; | ||
| 79 | struct dpll_data *dd; | ||
| 80 | |||
| 81 | dd = clk->dpll_data; | ||
| 82 | if (!dd) | ||
| 83 | return; | ||
| 84 | 43 | ||
| 85 | /* Return bypass rate if DPLL is bypassed */ | 44 | /* Private functions */ |
| 86 | v = __raw_readl(dd->control_reg); | ||
| 87 | v &= dd->enable_mask; | ||
| 88 | v >>= __ffs(dd->enable_mask); | ||
| 89 | |||
| 90 | /* Reparent in case the dpll is in bypass */ | ||
| 91 | if (cpu_is_omap24xx()) { | ||
| 92 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
| 93 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
| 94 | clk_reparent(clk, dd->clk_bypass); | ||
| 95 | } else if (cpu_is_omap34xx()) { | ||
| 96 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
| 97 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
| 98 | clk_reparent(clk, dd->clk_bypass); | ||
| 99 | } else if (cpu_is_omap44xx()) { | ||
| 100 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
| 101 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
| 102 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
| 103 | clk_reparent(clk, dd->clk_bypass); | ||
| 104 | } | ||
| 105 | return; | ||
| 106 | } | ||
| 107 | 45 | ||
| 108 | /** | 46 | /** |
| 109 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware | 47 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE |
| 110 | * @clk: struct clk * | 48 | * @clk: struct clk * belonging to the module |
| 111 | * | ||
| 112 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | ||
| 113 | * don't take effect until the VALID_CONFIG bit is written, write the | ||
| 114 | * VALID_CONFIG bit and wait for the write to complete. No return value. | ||
| 115 | */ | ||
| 116 | static void _omap2xxx_clk_commit(struct clk *clk) | ||
| 117 | { | ||
| 118 | if (!cpu_is_omap24xx()) | ||
| 119 | return; | ||
| 120 | |||
| 121 | if (!(clk->flags & DELAYED_APP)) | ||
| 122 | return; | ||
| 123 | |||
| 124 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | ||
| 125 | OMAP2_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 126 | /* OCP barrier */ | ||
| 127 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 128 | } | ||
| 129 | |||
| 130 | /* | ||
| 131 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL | ||
| 132 | * @clk: DPLL struct clk to test | ||
| 133 | * @n: divider value (N) to test | ||
| 134 | * | 49 | * |
| 135 | * Tests whether a particular divider @n will result in a valid DPLL | 50 | * If the necessary clocks for the OMAP hardware IP block that |
| 136 | * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter | 51 | * corresponds to clock @clk are enabled, then wait for the module to |
| 137 | * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate | 52 | * indicate readiness (i.e., to leave IDLE). This code does not |
| 138 | * (assuming that it is counting N upwards), or -2 if the enclosing loop | 53 | * belong in the clock code and will be moved in the medium term to |
| 139 | * should skip to the next iteration (again assuming N is increasing). | 54 | * module-dependent code. No return value. |
| 140 | */ | 55 | */ |
| 141 | static int _dpll_test_fint(struct clk *clk, u8 n) | 56 | static void _omap2_module_wait_ready(struct clk *clk) |
| 142 | { | 57 | { |
| 143 | struct dpll_data *dd; | 58 | void __iomem *companion_reg, *idlest_reg; |
| 144 | long fint; | 59 | u8 other_bit, idlest_bit, idlest_val; |
| 145 | int ret = 0; | ||
| 146 | |||
| 147 | dd = clk->dpll_data; | ||
| 148 | |||
| 149 | /* DPLL divider must result in a valid jitter correction val */ | ||
| 150 | fint = clk->parent->rate / (n + 1); | ||
| 151 | if (fint < DPLL_FINT_BAND1_MIN) { | ||
| 152 | |||
| 153 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 154 | "lowering max_divider\n", n); | ||
| 155 | dd->max_divider = n; | ||
| 156 | ret = DPLL_FINT_UNDERFLOW; | ||
| 157 | |||
| 158 | } else if (fint > DPLL_FINT_BAND1_MAX && | ||
| 159 | fint < DPLL_FINT_BAND2_MIN) { | ||
| 160 | |||
| 161 | pr_debug("rejecting n=%d due to Fint failure\n", n); | ||
| 162 | ret = DPLL_FINT_INVALID; | ||
| 163 | |||
| 164 | } else if (fint > DPLL_FINT_BAND2_MAX) { | ||
| 165 | |||
| 166 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 167 | "boosting min_divider\n", n); | ||
| 168 | dd->min_divider = n; | ||
| 169 | ret = DPLL_FINT_INVALID; | ||
| 170 | 60 | ||
| 61 | /* Not all modules have multiple clocks that their IDLEST depends on */ | ||
| 62 | if (clk->ops->find_companion) { | ||
| 63 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | ||
| 64 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | ||
| 65 | return; | ||
| 171 | } | 66 | } |
| 172 | 67 | ||
| 173 | return ret; | 68 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
| 69 | |||
| 70 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, | ||
| 71 | clk->name); | ||
| 174 | } | 72 | } |
| 175 | 73 | ||
| 74 | /* Public functions */ | ||
| 75 | |||
| 176 | /** | 76 | /** |
| 177 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | 77 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
| 178 | * @clk: OMAP clock struct ptr to use | 78 | * @clk: OMAP clock struct ptr to use |
| @@ -181,7 +81,6 @@ static int _dpll_test_fint(struct clk *clk, u8 n) | |||
| 181 | * clockdomain pointer, and save it into the struct clk. Intended to be | 81 | * clockdomain pointer, and save it into the struct clk. Intended to be |
| 182 | * called during clk_register(). No return value. | 82 | * called during clk_register(). No return value. |
| 183 | */ | 83 | */ |
| 184 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
| 185 | void omap2_init_clk_clkdm(struct clk *clk) | 84 | void omap2_init_clk_clkdm(struct clk *clk) |
| 186 | { | 85 | { |
| 187 | struct clockdomain *clkdm; | 86 | struct clockdomain *clkdm; |
| @@ -199,117 +98,6 @@ void omap2_init_clk_clkdm(struct clk *clk) | |||
| 199 | "clkdm %s\n", clk->name, clk->clkdm_name); | 98 | "clkdm %s\n", clk->name, clk->clkdm_name); |
| 200 | } | 99 | } |
| 201 | } | 100 | } |
| 202 | #endif | ||
| 203 | |||
| 204 | /** | ||
| 205 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware | ||
| 206 | * @clk: OMAP clock struct ptr to use | ||
| 207 | * | ||
| 208 | * Given a pointer to a source-selectable struct clk, read the hardware | ||
| 209 | * register and determine what its parent is currently set to. Update the | ||
| 210 | * clk->parent field with the appropriate clk ptr. | ||
| 211 | */ | ||
| 212 | void omap2_init_clksel_parent(struct clk *clk) | ||
| 213 | { | ||
| 214 | const struct clksel *clks; | ||
| 215 | const struct clksel_rate *clkr; | ||
| 216 | u32 r, found = 0; | ||
| 217 | |||
| 218 | if (!clk->clksel) | ||
| 219 | return; | ||
| 220 | |||
| 221 | r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | ||
| 222 | r >>= __ffs(clk->clksel_mask); | ||
| 223 | |||
| 224 | for (clks = clk->clksel; clks->parent && !found; clks++) { | ||
| 225 | for (clkr = clks->rates; clkr->div && !found; clkr++) { | ||
| 226 | if ((clkr->flags & cpu_mask) && (clkr->val == r)) { | ||
| 227 | if (clk->parent != clks->parent) { | ||
| 228 | pr_debug("clock: inited %s parent " | ||
| 229 | "to %s (was %s)\n", | ||
| 230 | clk->name, clks->parent->name, | ||
| 231 | ((clk->parent) ? | ||
| 232 | clk->parent->name : "NULL")); | ||
| 233 | clk_reparent(clk, clks->parent); | ||
| 234 | }; | ||
| 235 | found = 1; | ||
| 236 | } | ||
| 237 | } | ||
| 238 | } | ||
| 239 | |||
| 240 | if (!found) | ||
| 241 | printk(KERN_ERR "clock: init parent: could not find " | ||
| 242 | "regval %0x for clock %s\n", r, clk->name); | ||
| 243 | |||
| 244 | return; | ||
| 245 | } | ||
| 246 | |||
| 247 | /** | ||
| 248 | * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate | ||
| 249 | * @clk: struct clk * of a DPLL | ||
| 250 | * | ||
| 251 | * DPLLs can be locked or bypassed - basically, enabled or disabled. | ||
| 252 | * When locked, the DPLL output depends on the M and N values. When | ||
| 253 | * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock | ||
| 254 | * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and | ||
| 255 | * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively | ||
| 256 | * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. | ||
| 257 | * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is | ||
| 258 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 | ||
| 259 | * if the clock @clk is not a DPLL. | ||
| 260 | */ | ||
| 261 | u32 omap2_get_dpll_rate(struct clk *clk) | ||
| 262 | { | ||
| 263 | long long dpll_clk; | ||
| 264 | u32 dpll_mult, dpll_div, v; | ||
| 265 | struct dpll_data *dd; | ||
| 266 | |||
| 267 | dd = clk->dpll_data; | ||
| 268 | if (!dd) | ||
| 269 | return 0; | ||
| 270 | |||
| 271 | /* Return bypass rate if DPLL is bypassed */ | ||
| 272 | v = __raw_readl(dd->control_reg); | ||
| 273 | v &= dd->enable_mask; | ||
| 274 | v >>= __ffs(dd->enable_mask); | ||
| 275 | |||
| 276 | if (cpu_is_omap24xx()) { | ||
| 277 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
| 278 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
| 279 | return dd->clk_bypass->rate; | ||
| 280 | } else if (cpu_is_omap34xx()) { | ||
| 281 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
| 282 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
| 283 | return dd->clk_bypass->rate; | ||
| 284 | } else if (cpu_is_omap44xx()) { | ||
| 285 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
| 286 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
| 287 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
| 288 | return dd->clk_bypass->rate; | ||
| 289 | } | ||
| 290 | |||
| 291 | v = __raw_readl(dd->mult_div1_reg); | ||
| 292 | dpll_mult = v & dd->mult_mask; | ||
| 293 | dpll_mult >>= __ffs(dd->mult_mask); | ||
| 294 | dpll_div = v & dd->div1_mask; | ||
| 295 | dpll_div >>= __ffs(dd->div1_mask); | ||
| 296 | |||
| 297 | dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; | ||
| 298 | do_div(dpll_clk, dpll_div + 1); | ||
| 299 | |||
| 300 | return dpll_clk; | ||
| 301 | } | ||
| 302 | |||
| 303 | /* | ||
| 304 | * Used for clocks that have the same value as the parent clock, | ||
| 305 | * divided by some factor | ||
| 306 | */ | ||
| 307 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk) | ||
| 308 | { | ||
| 309 | WARN_ON(!clk->fixed_div); | ||
| 310 | |||
| 311 | return clk->parent->rate / clk->fixed_div; | ||
| 312 | } | ||
| 313 | 101 | ||
| 314 | /** | 102 | /** |
| 315 | * omap2_clk_dflt_find_companion - find companion clock to @clk | 103 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
| @@ -351,7 +139,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |||
| 351 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | 139 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk |
| 352 | * @clk: struct clk * to find IDLEST info for | 140 | * @clk: struct clk * to find IDLEST info for |
| 353 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | 141 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in |
| 354 | * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in | 142 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
| 143 | * @idlest_val: u8 * to return the idle status indicator | ||
| 355 | * | 144 | * |
| 356 | * Return the CM_IDLEST register address and bit shift corresponding | 145 | * Return the CM_IDLEST register address and bit shift corresponding |
| 357 | * to the module that "owns" this clock. This default code assumes | 146 | * to the module that "owns" this clock. This default code assumes |
| @@ -361,40 +150,26 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |||
| 361 | * CM_IDLEST2). This is not true for all modules. No return value. | 150 | * CM_IDLEST2). This is not true for all modules. No return value. |
| 362 | */ | 151 | */ |
| 363 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | 152 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
| 364 | u8 *idlest_bit) | 153 | u8 *idlest_bit, u8 *idlest_val) |
| 365 | { | 154 | { |
| 366 | u32 r; | 155 | u32 r; |
| 367 | 156 | ||
| 368 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 157 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 369 | *idlest_reg = (__force void __iomem *)r; | 158 | *idlest_reg = (__force void __iomem *)r; |
| 370 | *idlest_bit = clk->enable_bit; | 159 | *idlest_bit = clk->enable_bit; |
| 371 | } | ||
| 372 | 160 | ||
| 373 | /** | 161 | /* |
| 374 | * omap2_module_wait_ready - wait for an OMAP module to leave IDLE | 162 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 375 | * @clk: struct clk * belonging to the module | 163 | * 34xx reverses this, just to keep us on our toes |
| 376 | * | 164 | * AM35xx uses both, depending on the module. |
| 377 | * If the necessary clocks for the OMAP hardware IP block that | 165 | */ |
| 378 | * corresponds to clock @clk are enabled, then wait for the module to | 166 | if (cpu_is_omap24xx()) |
| 379 | * indicate readiness (i.e., to leave IDLE). This code does not | 167 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; |
| 380 | * belong in the clock code and will be moved in the medium term to | 168 | else if (cpu_is_omap34xx()) |
| 381 | * module-dependent code. No return value. | 169 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; |
| 382 | */ | 170 | else |
| 383 | static void omap2_module_wait_ready(struct clk *clk) | 171 | BUG(); |
| 384 | { | ||
| 385 | void __iomem *companion_reg, *idlest_reg; | ||
| 386 | u8 other_bit, idlest_bit; | ||
| 387 | |||
| 388 | /* Not all modules have multiple clocks that their IDLEST depends on */ | ||
| 389 | if (clk->ops->find_companion) { | ||
| 390 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | ||
| 391 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | ||
| 392 | return; | ||
| 393 | } | ||
| 394 | |||
| 395 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); | ||
| 396 | 172 | ||
| 397 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); | ||
| 398 | } | 173 | } |
| 399 | 174 | ||
| 400 | int omap2_dflt_clk_enable(struct clk *clk) | 175 | int omap2_dflt_clk_enable(struct clk *clk) |
| @@ -416,7 +191,7 @@ int omap2_dflt_clk_enable(struct clk *clk) | |||
| 416 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ | 191 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
| 417 | 192 | ||
| 418 | if (clk->ops->find_idlest) | 193 | if (clk->ops->find_idlest) |
| 419 | omap2_module_wait_ready(clk); | 194 | _omap2_module_wait_ready(clk); |
| 420 | 195 | ||
| 421 | return 0; | 196 | return 0; |
| 422 | } | 197 | } |
| @@ -456,337 +231,109 @@ const struct clkops clkops_omap2_dflt = { | |||
| 456 | .disable = omap2_dflt_clk_disable, | 231 | .disable = omap2_dflt_clk_disable, |
| 457 | }; | 232 | }; |
| 458 | 233 | ||
| 459 | /* Enables clock without considering parent dependencies or use count | 234 | /** |
| 460 | * REVISIT: Maybe change this to use clk->enable like on omap1? | 235 | * omap2_clk_disable - disable a clock, if the system is not using it |
| 236 | * @clk: struct clk * to disable | ||
| 237 | * | ||
| 238 | * Decrements the usecount on struct clk @clk. If there are no users | ||
| 239 | * left, call the clkops-specific clock disable function to disable it | ||
| 240 | * in hardware. If the clock is part of a clockdomain (which they all | ||
| 241 | * should be), request that the clockdomain be disabled. (It too has | ||
| 242 | * a usecount, and so will not be disabled in the hardware until it no | ||
| 243 | * longer has any users.) If the clock has a parent clock (most of | ||
| 244 | * them do), then call ourselves, recursing on the parent clock. This | ||
| 245 | * can cause an entire branch of the clock tree to be powered off by | ||
| 246 | * simply disabling one clock. Intended to be called with the clockfw_lock | ||
| 247 | * spinlock held. No return value. | ||
| 461 | */ | 248 | */ |
| 462 | static int _omap2_clk_enable(struct clk *clk) | ||
| 463 | { | ||
| 464 | return clk->ops->enable(clk); | ||
| 465 | } | ||
| 466 | |||
| 467 | /* Disables clock without considering parent dependencies or use count */ | ||
| 468 | static void _omap2_clk_disable(struct clk *clk) | ||
| 469 | { | ||
| 470 | clk->ops->disable(clk); | ||
| 471 | } | ||
| 472 | |||
| 473 | void omap2_clk_disable(struct clk *clk) | 249 | void omap2_clk_disable(struct clk *clk) |
| 474 | { | 250 | { |
| 475 | if (clk->usecount > 0 && !(--clk->usecount)) { | 251 | if (clk->usecount == 0) { |
| 476 | _omap2_clk_disable(clk); | 252 | WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " |
| 477 | if (clk->parent) | 253 | "already 0?", clk->name); |
| 478 | omap2_clk_disable(clk->parent); | 254 | return; |
| 479 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
| 480 | if (clk->clkdm) | ||
| 481 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
| 482 | #endif | ||
| 483 | |||
| 484 | } | 255 | } |
| 485 | } | ||
| 486 | 256 | ||
| 487 | int omap2_clk_enable(struct clk *clk) | 257 | pr_debug("clock: %s: decrementing usecount\n", clk->name); |
| 488 | { | ||
| 489 | int ret = 0; | ||
| 490 | 258 | ||
| 491 | if (clk->usecount++ == 0) { | 259 | clk->usecount--; |
| 492 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
| 493 | if (clk->clkdm) | ||
| 494 | omap2_clkdm_clk_enable(clk->clkdm, clk); | ||
| 495 | #endif | ||
| 496 | 260 | ||
| 497 | if (clk->parent) { | 261 | if (clk->usecount > 0) |
| 498 | ret = omap2_clk_enable(clk->parent); | 262 | return; |
| 499 | if (ret) | ||
| 500 | goto err; | ||
| 501 | } | ||
| 502 | 263 | ||
| 503 | ret = _omap2_clk_enable(clk); | 264 | pr_debug("clock: %s: disabling in hardware\n", clk->name); |
| 504 | if (ret) { | ||
| 505 | if (clk->parent) | ||
| 506 | omap2_clk_disable(clk->parent); | ||
| 507 | 265 | ||
| 508 | goto err; | 266 | clk->ops->disable(clk); |
| 509 | } | ||
| 510 | } | ||
| 511 | return ret; | ||
| 512 | 267 | ||
| 513 | err: | ||
| 514 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ | ||
| 515 | if (clk->clkdm) | 268 | if (clk->clkdm) |
| 516 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 269 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
| 517 | #endif | ||
| 518 | clk->usecount--; | ||
| 519 | return ret; | ||
| 520 | } | ||
| 521 | |||
| 522 | /* | ||
| 523 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | ||
| 524 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | ||
| 525 | */ | ||
| 526 | unsigned long omap2_clksel_recalc(struct clk *clk) | ||
| 527 | { | ||
| 528 | unsigned long rate; | ||
| 529 | u32 div = 0; | ||
| 530 | |||
| 531 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); | ||
| 532 | |||
| 533 | div = omap2_clksel_get_divisor(clk); | ||
| 534 | if (div == 0) | ||
| 535 | return clk->rate; | ||
| 536 | |||
| 537 | rate = clk->parent->rate / div; | ||
| 538 | |||
| 539 | pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); | ||
| 540 | |||
| 541 | return rate; | ||
| 542 | } | ||
| 543 | |||
| 544 | /** | ||
| 545 | * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent | ||
| 546 | * @clk: OMAP struct clk ptr to inspect | ||
| 547 | * @src_clk: OMAP struct clk ptr of the parent clk to search for | ||
| 548 | * | ||
| 549 | * Scan the struct clksel array associated with the clock to find | ||
| 550 | * the element associated with the supplied parent clock address. | ||
| 551 | * Returns a pointer to the struct clksel on success or NULL on error. | ||
| 552 | */ | ||
| 553 | static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, | ||
| 554 | struct clk *src_clk) | ||
| 555 | { | ||
| 556 | const struct clksel *clks; | ||
| 557 | |||
| 558 | if (!clk->clksel) | ||
| 559 | return NULL; | ||
| 560 | |||
| 561 | for (clks = clk->clksel; clks->parent; clks++) { | ||
| 562 | if (clks->parent == src_clk) | ||
| 563 | break; /* Found the requested parent */ | ||
| 564 | } | ||
| 565 | |||
| 566 | if (!clks->parent) { | ||
| 567 | printk(KERN_ERR "clock: Could not find parent clock %s in " | ||
| 568 | "clksel array of clock %s\n", src_clk->name, | ||
| 569 | clk->name); | ||
| 570 | return NULL; | ||
| 571 | } | ||
| 572 | 270 | ||
| 573 | return clks; | 271 | if (clk->parent) |
| 272 | omap2_clk_disable(clk->parent); | ||
| 574 | } | 273 | } |
| 575 | 274 | ||
| 576 | /** | 275 | /** |
| 577 | * omap2_clksel_round_rate_div - find divisor for the given clock and rate | 276 | * omap2_clk_enable - request that the system enable a clock |
| 578 | * @clk: OMAP struct clk to use | 277 | * @clk: struct clk * to enable |
| 579 | * @target_rate: desired clock rate | ||
| 580 | * @new_div: ptr to where we should store the divisor | ||
| 581 | * | 278 | * |
| 582 | * Finds 'best' divider value in an array based on the source and target | 279 | * Increments the usecount on struct clk @clk. If there were no users |
| 583 | * rates. The divider array must be sorted with smallest divider first. | 280 | * previously, then recurse up the clock tree, enabling all of the |
| 584 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | 281 | * clock's parents and all of the parent clockdomains, and finally, |
| 585 | * they are only settable as part of virtual_prcm set. | 282 | * enabling @clk's clockdomain, and @clk itself. Intended to be |
| 586 | * | 283 | * called with the clockfw_lock spinlock held. Returns 0 upon success |
| 587 | * Returns the rounded clock rate or returns 0xffffffff on error. | 284 | * or a negative error code upon failure. |
| 588 | */ | 285 | */ |
| 589 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | 286 | int omap2_clk_enable(struct clk *clk) |
| 590 | u32 *new_div) | ||
| 591 | { | ||
| 592 | unsigned long test_rate; | ||
| 593 | const struct clksel *clks; | ||
| 594 | const struct clksel_rate *clkr; | ||
| 595 | u32 last_div = 0; | ||
| 596 | |||
| 597 | pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", | ||
| 598 | clk->name, target_rate); | ||
| 599 | |||
| 600 | *new_div = 1; | ||
| 601 | |||
| 602 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | ||
| 603 | if (!clks) | ||
| 604 | return ~0; | ||
| 605 | |||
| 606 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 607 | if (!(clkr->flags & cpu_mask)) | ||
| 608 | continue; | ||
| 609 | |||
| 610 | /* Sanity check */ | ||
| 611 | if (clkr->div <= last_div) | ||
| 612 | pr_err("clock: clksel_rate table not sorted " | ||
| 613 | "for clock %s", clk->name); | ||
| 614 | |||
| 615 | last_div = clkr->div; | ||
| 616 | |||
| 617 | test_rate = clk->parent->rate / clkr->div; | ||
| 618 | |||
| 619 | if (test_rate <= target_rate) | ||
| 620 | break; /* found it */ | ||
| 621 | } | ||
| 622 | |||
| 623 | if (!clkr->div) { | ||
| 624 | pr_err("clock: Could not find divisor for target " | ||
| 625 | "rate %ld for clock %s parent %s\n", target_rate, | ||
| 626 | clk->name, clk->parent->name); | ||
| 627 | return ~0; | ||
| 628 | } | ||
| 629 | |||
| 630 | *new_div = clkr->div; | ||
| 631 | |||
| 632 | pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, | ||
| 633 | (clk->parent->rate / clkr->div)); | ||
| 634 | |||
| 635 | return (clk->parent->rate / clkr->div); | ||
| 636 | } | ||
| 637 | |||
| 638 | /** | ||
| 639 | * omap2_clksel_round_rate - find rounded rate for the given clock and rate | ||
| 640 | * @clk: OMAP struct clk to use | ||
| 641 | * @target_rate: desired clock rate | ||
| 642 | * | ||
| 643 | * Compatibility wrapper for OMAP clock framework | ||
| 644 | * Finds best target rate based on the source clock and possible dividers. | ||
| 645 | * rates. The divider array must be sorted with smallest divider first. | ||
| 646 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | ||
| 647 | * they are only settable as part of virtual_prcm set. | ||
| 648 | * | ||
| 649 | * Returns the rounded clock rate or returns 0xffffffff on error. | ||
| 650 | */ | ||
| 651 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | ||
| 652 | { | ||
| 653 | u32 new_div; | ||
| 654 | |||
| 655 | return omap2_clksel_round_rate_div(clk, target_rate, &new_div); | ||
| 656 | } | ||
| 657 | |||
| 658 | |||
| 659 | /* Given a clock and a rate apply a clock specific rounding function */ | ||
| 660 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 661 | { | 287 | { |
| 662 | if (clk->round_rate) | 288 | int ret; |
| 663 | return clk->round_rate(clk, rate); | ||
| 664 | 289 | ||
| 665 | if (clk->flags & RATE_FIXED) | 290 | pr_debug("clock: %s: incrementing usecount\n", clk->name); |
| 666 | printk(KERN_ERR "clock: generic omap2_clk_round_rate called " | ||
| 667 | "on fixed-rate clock %s\n", clk->name); | ||
| 668 | 291 | ||
| 669 | return clk->rate; | 292 | clk->usecount++; |
| 670 | } | ||
| 671 | |||
| 672 | /** | ||
| 673 | * omap2_clksel_to_divisor() - turn clksel field value into integer divider | ||
| 674 | * @clk: OMAP struct clk to use | ||
| 675 | * @field_val: register field value to find | ||
| 676 | * | ||
| 677 | * Given a struct clk of a rate-selectable clksel clock, and a register field | ||
| 678 | * value to search for, find the corresponding clock divisor. The register | ||
| 679 | * field value should be pre-masked and shifted down so the LSB is at bit 0 | ||
| 680 | * before calling. Returns 0 on error | ||
| 681 | */ | ||
| 682 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) | ||
| 683 | { | ||
| 684 | const struct clksel *clks; | ||
| 685 | const struct clksel_rate *clkr; | ||
| 686 | 293 | ||
| 687 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 294 | if (clk->usecount > 1) |
| 688 | if (!clks) | ||
| 689 | return 0; | 295 | return 0; |
| 690 | 296 | ||
| 691 | for (clkr = clks->rates; clkr->div; clkr++) { | 297 | pr_debug("clock: %s: enabling in hardware\n", clk->name); |
| 692 | if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) | ||
| 693 | break; | ||
| 694 | } | ||
| 695 | 298 | ||
| 696 | if (!clkr->div) { | 299 | if (clk->parent) { |
| 697 | printk(KERN_ERR "clock: Could not find fieldval %d for " | 300 | ret = omap2_clk_enable(clk->parent); |
| 698 | "clock %s parent %s\n", field_val, clk->name, | 301 | if (ret) { |
| 699 | clk->parent->name); | 302 | WARN(1, "clock: %s: could not enable parent %s: %d\n", |
| 700 | return 0; | 303 | clk->name, clk->parent->name, ret); |
| 304 | goto oce_err1; | ||
| 305 | } | ||
| 701 | } | 306 | } |
| 702 | 307 | ||
| 703 | return clkr->div; | 308 | if (clk->clkdm) { |
| 704 | } | 309 | ret = omap2_clkdm_clk_enable(clk->clkdm, clk); |
| 705 | 310 | if (ret) { | |
| 706 | /** | 311 | WARN(1, "clock: %s: could not enable clockdomain %s: " |
| 707 | * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value | 312 | "%d\n", clk->name, clk->clkdm->name, ret); |
| 708 | * @clk: OMAP struct clk to use | 313 | goto oce_err2; |
| 709 | * @div: integer divisor to search for | 314 | } |
| 710 | * | ||
| 711 | * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, | ||
| 712 | * find the corresponding register field value. The return register value is | ||
| 713 | * the value before left-shifting. Returns ~0 on error | ||
| 714 | */ | ||
| 715 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | ||
| 716 | { | ||
| 717 | const struct clksel *clks; | ||
| 718 | const struct clksel_rate *clkr; | ||
| 719 | |||
| 720 | /* should never happen */ | ||
| 721 | WARN_ON(div == 0); | ||
| 722 | |||
| 723 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | ||
| 724 | if (!clks) | ||
| 725 | return ~0; | ||
| 726 | |||
| 727 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 728 | if ((clkr->flags & cpu_mask) && (clkr->div == div)) | ||
| 729 | break; | ||
| 730 | } | 315 | } |
| 731 | 316 | ||
| 732 | if (!clkr->div) { | 317 | ret = clk->ops->enable(clk); |
| 733 | printk(KERN_ERR "clock: Could not find divisor %d for " | 318 | if (ret) { |
| 734 | "clock %s parent %s\n", div, clk->name, | 319 | WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); |
| 735 | clk->parent->name); | 320 | goto oce_err3; |
| 736 | return ~0; | ||
| 737 | } | 321 | } |
| 738 | 322 | ||
| 739 | return clkr->val; | 323 | return 0; |
| 740 | } | ||
| 741 | |||
| 742 | /** | ||
| 743 | * omap2_clksel_get_divisor - get current divider applied to parent clock. | ||
| 744 | * @clk: OMAP struct clk to use. | ||
| 745 | * | ||
| 746 | * Returns the integer divisor upon success or 0 on error. | ||
| 747 | */ | ||
| 748 | u32 omap2_clksel_get_divisor(struct clk *clk) | ||
| 749 | { | ||
| 750 | u32 v; | ||
| 751 | |||
| 752 | if (!clk->clksel_mask) | ||
| 753 | return 0; | ||
| 754 | |||
| 755 | v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | ||
| 756 | v >>= __ffs(clk->clksel_mask); | ||
| 757 | |||
| 758 | return omap2_clksel_to_divisor(clk, v); | ||
| 759 | } | ||
| 760 | |||
| 761 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | ||
| 762 | { | ||
| 763 | u32 v, field_val, validrate, new_div = 0; | ||
| 764 | |||
| 765 | if (!clk->clksel_mask) | ||
| 766 | return -EINVAL; | ||
| 767 | |||
| 768 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | ||
| 769 | if (validrate != rate) | ||
| 770 | return -EINVAL; | ||
| 771 | |||
| 772 | field_val = omap2_divisor_to_clksel(clk, new_div); | ||
| 773 | if (field_val == ~0) | ||
| 774 | return -EINVAL; | ||
| 775 | |||
| 776 | v = __raw_readl(clk->clksel_reg); | ||
| 777 | v &= ~clk->clksel_mask; | ||
| 778 | v |= field_val << __ffs(clk->clksel_mask); | ||
| 779 | __raw_writel(v, clk->clksel_reg); | ||
| 780 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | ||
| 781 | |||
| 782 | clk->rate = clk->parent->rate / new_div; | ||
| 783 | 324 | ||
| 784 | _omap2xxx_clk_commit(clk); | 325 | oce_err3: |
| 326 | if (clk->clkdm) | ||
| 327 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
| 328 | oce_err2: | ||
| 329 | if (clk->parent) | ||
| 330 | omap2_clk_disable(clk->parent); | ||
| 331 | oce_err1: | ||
| 332 | clk->usecount--; | ||
| 785 | 333 | ||
| 786 | return 0; | 334 | return ret; |
| 787 | } | 335 | } |
| 788 | 336 | ||
| 789 | |||
| 790 | /* Set the clock rate for a clock source */ | 337 | /* Set the clock rate for a clock source */ |
| 791 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | 338 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) |
| 792 | { | 339 | { |
| @@ -794,11 +341,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 794 | 341 | ||
| 795 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | 342 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); |
| 796 | 343 | ||
| 797 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the | ||
| 798 | rate table mechanism, driven by mpu_speed */ | ||
| 799 | if (clk->flags & CONFIG_PARTICIPANT) | ||
| 800 | return -EINVAL; | ||
| 801 | |||
| 802 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | 344 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
| 803 | if (clk->set_rate) | 345 | if (clk->set_rate) |
| 804 | ret = clk->set_rate(clk, rate); | 346 | ret = clk->set_rate(clk, rate); |
| @@ -806,289 +348,152 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 806 | return ret; | 348 | return ret; |
| 807 | } | 349 | } |
| 808 | 350 | ||
| 809 | /* | ||
| 810 | * Converts encoded control register address into a full address | ||
| 811 | * On error, the return value (parent_div) will be 0. | ||
| 812 | */ | ||
| 813 | static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, | ||
| 814 | u32 *field_val) | ||
| 815 | { | ||
| 816 | const struct clksel *clks; | ||
| 817 | const struct clksel_rate *clkr; | ||
| 818 | |||
| 819 | clks = omap2_get_clksel_by_parent(clk, src_clk); | ||
| 820 | if (!clks) | ||
| 821 | return 0; | ||
| 822 | |||
| 823 | for (clkr = clks->rates; clkr->div; clkr++) { | ||
| 824 | if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) | ||
| 825 | break; /* Found the default rate for this platform */ | ||
| 826 | } | ||
| 827 | |||
| 828 | if (!clkr->div) { | ||
| 829 | printk(KERN_ERR "clock: Could not find default rate for " | ||
| 830 | "clock %s parent %s\n", clk->name, | ||
| 831 | src_clk->parent->name); | ||
| 832 | return 0; | ||
| 833 | } | ||
| 834 | |||
| 835 | /* Should never happen. Add a clksel mask to the struct clk. */ | ||
| 836 | WARN_ON(clk->clksel_mask == 0); | ||
| 837 | |||
| 838 | *field_val = clkr->val; | ||
| 839 | |||
| 840 | return clkr->div; | ||
| 841 | } | ||
| 842 | |||
| 843 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | 351 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
| 844 | { | 352 | { |
| 845 | u32 field_val, v, parent_div; | ||
| 846 | |||
| 847 | if (clk->flags & CONFIG_PARTICIPANT) | ||
| 848 | return -EINVAL; | ||
| 849 | |||
| 850 | if (!clk->clksel) | 353 | if (!clk->clksel) |
| 851 | return -EINVAL; | 354 | return -EINVAL; |
| 852 | 355 | ||
| 853 | parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); | 356 | if (clk->parent == new_parent) |
| 854 | if (!parent_div) | 357 | return 0; |
| 855 | return -EINVAL; | ||
| 856 | |||
| 857 | /* Set new source value (previous dividers if any in effect) */ | ||
| 858 | v = __raw_readl(clk->clksel_reg); | ||
| 859 | v &= ~clk->clksel_mask; | ||
| 860 | v |= field_val << __ffs(clk->clksel_mask); | ||
| 861 | __raw_writel(v, clk->clksel_reg); | ||
| 862 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | ||
| 863 | |||
| 864 | _omap2xxx_clk_commit(clk); | ||
| 865 | |||
| 866 | clk_reparent(clk, new_parent); | ||
| 867 | |||
| 868 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ | ||
| 869 | clk->rate = new_parent->rate; | ||
| 870 | |||
| 871 | if (parent_div > 0) | ||
| 872 | clk->rate /= parent_div; | ||
| 873 | |||
| 874 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | ||
| 875 | clk->name, clk->parent->name, clk->rate); | ||
| 876 | 358 | ||
| 877 | return 0; | 359 | return omap2_clksel_set_parent(clk, new_parent); |
| 878 | } | 360 | } |
| 879 | 361 | ||
| 880 | /* DPLL rate rounding code */ | 362 | /* OMAP3/4 non-CORE DPLL clkops */ |
| 881 | 363 | ||
| 882 | /** | 364 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
| 883 | * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding | ||
| 884 | * @clk: struct clk * of the DPLL | ||
| 885 | * @tolerance: maximum rate error tolerance | ||
| 886 | * | ||
| 887 | * Set the maximum DPLL rate error tolerance for the rate rounding | ||
| 888 | * algorithm. The rate tolerance is an attempt to balance DPLL power | ||
| 889 | * saving (the least divider value "n") vs. rate fidelity (the least | ||
| 890 | * difference between the desired DPLL target rate and the rounded | ||
| 891 | * rate out of the algorithm). So, increasing the tolerance is likely | ||
| 892 | * to decrease DPLL power consumption and increase DPLL rate error. | ||
| 893 | * Returns -EINVAL if provided a null clock ptr or a clk that is not a | ||
| 894 | * DPLL; or 0 upon success. | ||
| 895 | */ | ||
| 896 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) | ||
| 897 | { | ||
| 898 | if (!clk || !clk->dpll_data) | ||
| 899 | return -EINVAL; | ||
| 900 | |||
| 901 | clk->dpll_data->rate_tolerance = tolerance; | ||
| 902 | 365 | ||
| 903 | return 0; | 366 | const struct clkops clkops_omap3_noncore_dpll_ops = { |
| 904 | } | 367 | .enable = omap3_noncore_dpll_enable, |
| 368 | .disable = omap3_noncore_dpll_disable, | ||
| 369 | }; | ||
| 905 | 370 | ||
| 906 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, | 371 | #endif |
| 907 | unsigned int m, unsigned int n) | ||
| 908 | { | ||
| 909 | unsigned long long num; | ||
| 910 | 372 | ||
| 911 | num = (unsigned long long)parent_rate * m; | ||
| 912 | do_div(num, n); | ||
| 913 | return num; | ||
| 914 | } | ||
| 915 | 373 | ||
| 916 | /* | 374 | /* |
| 917 | * _dpll_test_mult - test a DPLL multiplier value | 375 | * OMAP2+ clock reset and init functions |
| 918 | * @m: pointer to the DPLL m (multiplier) value under test | ||
| 919 | * @n: current DPLL n (divider) value under test | ||
| 920 | * @new_rate: pointer to storage for the resulting rounded rate | ||
| 921 | * @target_rate: the desired DPLL rate | ||
| 922 | * @parent_rate: the DPLL's parent clock rate | ||
| 923 | * | ||
| 924 | * This code tests a DPLL multiplier value, ensuring that the | ||
| 925 | * resulting rate will not be higher than the target_rate, and that | ||
| 926 | * the multiplier value itself is valid for the DPLL. Initially, the | ||
| 927 | * integer pointed to by the m argument should be prescaled by | ||
| 928 | * multiplying by DPLL_SCALE_FACTOR. The code will replace this with | ||
| 929 | * a non-scaled m upon return. This non-scaled m will result in a | ||
| 930 | * new_rate as close as possible to target_rate (but not greater than | ||
| 931 | * target_rate) given the current (parent_rate, n, prescaled m) | ||
| 932 | * triple. Returns DPLL_MULT_UNDERFLOW in the event that the | ||
| 933 | * non-scaled m attempted to underflow, which can allow the calling | ||
| 934 | * function to bail out early; or 0 upon success. | ||
| 935 | */ | 376 | */ |
| 936 | static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | 377 | |
| 937 | unsigned long target_rate, | 378 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 938 | unsigned long parent_rate) | 379 | void omap2_clk_disable_unused(struct clk *clk) |
| 939 | { | 380 | { |
| 940 | int r = 0, carry = 0; | 381 | u32 regval32, v; |
| 941 | 382 | ||
| 942 | /* Unscale m and round if necessary */ | 383 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; |
| 943 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) | ||
| 944 | carry = 1; | ||
| 945 | *m = (*m / DPLL_SCALE_FACTOR) + carry; | ||
| 946 | 384 | ||
| 947 | /* | 385 | regval32 = __raw_readl(clk->enable_reg); |
| 948 | * The new rate must be <= the target rate to avoid programming | 386 | if ((regval32 & (1 << clk->enable_bit)) == v) |
| 949 | * a rate that is impossible for the hardware to handle | 387 | return; |
| 950 | */ | ||
| 951 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | ||
| 952 | if (*new_rate > target_rate) { | ||
| 953 | (*m)--; | ||
| 954 | *new_rate = 0; | ||
| 955 | } | ||
| 956 | 388 | ||
| 957 | /* Guard against m underflow */ | 389 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); |
| 958 | if (*m < DPLL_MIN_MULTIPLIER) { | 390 | if (cpu_is_omap34xx()) { |
| 959 | *m = DPLL_MIN_MULTIPLIER; | 391 | omap2_clk_enable(clk); |
| 960 | *new_rate = 0; | 392 | omap2_clk_disable(clk); |
| 961 | r = DPLL_MULT_UNDERFLOW; | 393 | } else { |
| 394 | clk->ops->disable(clk); | ||
| 962 | } | 395 | } |
| 963 | 396 | if (clk->clkdm != NULL) | |
| 964 | if (*new_rate == 0) | 397 | pwrdm_clkdm_state_switch(clk->clkdm); |
| 965 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | ||
| 966 | |||
| 967 | return r; | ||
| 968 | } | 398 | } |
| 399 | #endif | ||
| 969 | 400 | ||
| 970 | /** | 401 | /** |
| 971 | * omap2_dpll_round_rate - round a target rate for an OMAP DPLL | 402 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument |
| 972 | * @clk: struct clk * for a DPLL | 403 | * @mpurate_ck_name: clk name of the clock to change rate |
| 973 | * @target_rate: desired DPLL clock rate | ||
| 974 | * | 404 | * |
| 975 | * Given a DPLL, a desired target rate, and a rate tolerance, round | 405 | * Change the ARM MPU clock rate to the rate specified on the command |
| 976 | * the target rate to a possible, programmable rate for this DPLL. | 406 | * line, if one was specified. @mpurate_ck_name should be |
| 977 | * Rate tolerance is assumed to be set by the caller before this | 407 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. |
| 978 | * function is called. Attempts to select the minimum possible n | 408 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently |
| 979 | * within the tolerance to reduce power consumption. Stores the | 409 | * handled by the virt_prcm_set clock, but this should be handled by |
| 980 | * computed (m, n) in the DPLL's dpll_data structure so set_rate() | 410 | * the OPP layer. XXX This is intended to be handled by the OPP layer |
| 981 | * will not need to call this (expensive) function again. Returns ~0 | 411 | * code in the near future and should be removed from the clock code. |
| 982 | * if the target rate cannot be rounded, either because the rate is | 412 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects |
| 983 | * too low or because the rate tolerance is set too tightly; or the | 413 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name |
| 984 | * rounded rate upon success. | 414 | * cannot be found, or 0 upon success. |
| 985 | */ | 415 | */ |
| 986 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | 416 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) |
| 987 | { | 417 | { |
| 988 | int m, n, r, e, scaled_max_m; | 418 | struct clk *mpurate_ck; |
| 989 | unsigned long scaled_rt_rp, new_rate; | 419 | int r; |
| 990 | int min_e = -1, min_e_m = -1, min_e_n = -1; | ||
| 991 | struct dpll_data *dd; | ||
| 992 | 420 | ||
| 993 | if (!clk || !clk->dpll_data) | 421 | if (!mpurate) |
| 994 | return ~0; | 422 | return -EINVAL; |
| 995 | |||
| 996 | dd = clk->dpll_data; | ||
| 997 | |||
| 998 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " | ||
| 999 | "%ld\n", clk->name, target_rate); | ||
| 1000 | |||
| 1001 | scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); | ||
| 1002 | scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; | ||
| 1003 | |||
| 1004 | dd->last_rounded_rate = 0; | ||
| 1005 | |||
| 1006 | for (n = dd->min_divider; n <= dd->max_divider; n++) { | ||
| 1007 | |||
| 1008 | /* Is the (input clk, divider) pair valid for the DPLL? */ | ||
| 1009 | r = _dpll_test_fint(clk, n); | ||
| 1010 | if (r == DPLL_FINT_UNDERFLOW) | ||
| 1011 | break; | ||
| 1012 | else if (r == DPLL_FINT_INVALID) | ||
| 1013 | continue; | ||
| 1014 | |||
| 1015 | /* Compute the scaled DPLL multiplier, based on the divider */ | ||
| 1016 | m = scaled_rt_rp * n; | ||
| 1017 | |||
| 1018 | /* | ||
| 1019 | * Since we're counting n up, a m overflow means we | ||
| 1020 | * can bail out completely (since as n increases in | ||
| 1021 | * the next iteration, there's no way that m can | ||
| 1022 | * increase beyond the current m) | ||
| 1023 | */ | ||
| 1024 | if (m > scaled_max_m) | ||
| 1025 | break; | ||
| 1026 | |||
| 1027 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, | ||
| 1028 | dd->clk_ref->rate); | ||
| 1029 | |||
| 1030 | /* m can't be set low enough for this n - try with a larger n */ | ||
| 1031 | if (r == DPLL_MULT_UNDERFLOW) | ||
| 1032 | continue; | ||
| 1033 | |||
| 1034 | e = target_rate - new_rate; | ||
| 1035 | pr_debug("clock: n = %d: m = %d: rate error is %d " | ||
| 1036 | "(new_rate = %ld)\n", n, m, e, new_rate); | ||
| 1037 | |||
| 1038 | if (min_e == -1 || | ||
| 1039 | min_e >= (int)(abs(e) - dd->rate_tolerance)) { | ||
| 1040 | min_e = e; | ||
| 1041 | min_e_m = m; | ||
| 1042 | min_e_n = n; | ||
| 1043 | |||
| 1044 | pr_debug("clock: found new least error %d\n", min_e); | ||
| 1045 | 423 | ||
| 1046 | /* We found good settings -- bail out now */ | 424 | mpurate_ck = clk_get(NULL, mpurate_ck_name); |
| 1047 | if (min_e <= dd->rate_tolerance) | 425 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) |
| 1048 | break; | 426 | return -ENOENT; |
| 1049 | } | ||
| 1050 | } | ||
| 1051 | 427 | ||
| 1052 | if (min_e < 0) { | 428 | r = clk_set_rate(mpurate_ck, mpurate); |
| 1053 | pr_debug("clock: error: target rate or tolerance too low\n"); | 429 | if (IS_ERR_VALUE(r)) { |
| 1054 | return ~0; | 430 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", |
| 431 | mpurate_ck->name, mpurate, r); | ||
| 432 | return -EINVAL; | ||
| 1055 | } | 433 | } |
| 1056 | 434 | ||
| 1057 | dd->last_rounded_m = min_e_m; | 435 | calibrate_delay(); |
| 1058 | dd->last_rounded_n = min_e_n; | 436 | recalculate_root_clocks(); |
| 1059 | dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, | ||
| 1060 | min_e_m, min_e_n); | ||
| 1061 | 437 | ||
| 1062 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", | 438 | clk_put(mpurate_ck); |
| 1063 | min_e, min_e_m, min_e_n); | ||
| 1064 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", | ||
| 1065 | dd->last_rounded_rate, target_rate); | ||
| 1066 | 439 | ||
| 1067 | return dd->last_rounded_rate; | 440 | return 0; |
| 1068 | } | 441 | } |
| 1069 | 442 | ||
| 1070 | /*------------------------------------------------------------------------- | 443 | /** |
| 1071 | * Omap2 clock reset and init functions | 444 | * omap2_clk_print_new_rates - print summary of current clock tree rates |
| 1072 | *-------------------------------------------------------------------------*/ | 445 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator |
| 1073 | 446 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
| 1074 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 447 | * @mpu_ck_name: clk name for the ARM MPU clock |
| 1075 | void omap2_clk_disable_unused(struct clk *clk) | 448 | * |
| 449 | * Prints a short message to the console with the HFCLKIN oscillator | ||
| 450 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | ||
| 451 | * Called by the boot-time MPU rate switching code. XXX This is intended | ||
| 452 | * to be handled by the OPP layer code in the near future and should be | ||
| 453 | * removed from the clock code. No return value. | ||
| 454 | */ | ||
| 455 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | ||
| 456 | const char *core_ck_name, | ||
| 457 | const char *mpu_ck_name) | ||
| 1076 | { | 458 | { |
| 1077 | u32 regval32, v; | 459 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; |
| 460 | unsigned long hfclkin_rate; | ||
| 1078 | 461 | ||
| 1079 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | 462 | mpu_ck = clk_get(NULL, mpu_ck_name); |
| 463 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | ||
| 464 | return; | ||
| 1080 | 465 | ||
| 1081 | regval32 = __raw_readl(clk->enable_reg); | 466 | core_ck = clk_get(NULL, core_ck_name); |
| 1082 | if ((regval32 & (1 << clk->enable_bit)) == v) | 467 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) |
| 1083 | return; | 468 | return; |
| 1084 | 469 | ||
| 1085 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); | 470 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); |
| 1086 | if (cpu_is_omap34xx()) { | 471 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) |
| 1087 | omap2_clk_enable(clk); | 472 | return; |
| 1088 | omap2_clk_disable(clk); | 473 | |
| 1089 | } else | 474 | hfclkin_rate = clk_get_rate(hfclkin_ck); |
| 1090 | _omap2_clk_disable(clk); | 475 | |
| 1091 | if (clk->clkdm != NULL) | 476 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " |
| 1092 | pwrdm_clkdm_state_switch(clk->clkdm); | 477 | "%ld.%01ld/%ld/%ld MHz\n", |
| 1093 | } | 478 | (hfclkin_rate / 1000000), |
| 479 | ((hfclkin_rate / 100000) % 10), | ||
| 480 | (clk_get_rate(core_ck) / 1000000), | ||
| 481 | (clk_get_rate(mpu_ck) / 1000000)); | ||
| 482 | } | ||
| 483 | |||
| 484 | /* Common data */ | ||
| 485 | |||
| 486 | struct clk_functions omap2_clk_functions = { | ||
| 487 | .clk_enable = omap2_clk_enable, | ||
| 488 | .clk_disable = omap2_clk_disable, | ||
| 489 | .clk_round_rate = omap2_clk_round_rate, | ||
| 490 | .clk_set_rate = omap2_clk_set_rate, | ||
| 491 | .clk_set_parent = omap2_clk_set_parent, | ||
| 492 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 493 | #ifdef CONFIG_CPU_FREQ | ||
| 494 | /* These will be removed when the OPP code is integrated */ | ||
| 495 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | ||
| 496 | .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, | ||
| 1094 | #endif | 497 | #endif |
| 498 | }; | ||
| 499 | |||
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 93c48df3b5b1..ad8a1f7c1afc 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
| @@ -47,7 +47,10 @@ | |||
| 47 | #define DPLL_LOW_POWER_BYPASS 0x5 | 47 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 48 | #define DPLL_LOCKED 0x7 | 48 | #define DPLL_LOCKED 0x7 |
| 49 | 49 | ||
| 50 | int omap2_clk_init(void); | 50 | /* DPLL Type and DCO Selection Flags */ |
| 51 | #define DPLL_J_TYPE 0x1 | ||
| 52 | #define DPLL_NO_DCO_SEL 0x2 | ||
| 53 | |||
| 51 | int omap2_clk_enable(struct clk *clk); | 54 | int omap2_clk_enable(struct clk *clk); |
| 52 | void omap2_clk_disable(struct clk *clk); | 55 | void omap2_clk_disable(struct clk *clk); |
| 53 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | 56 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| @@ -78,23 +81,53 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
| 78 | u32 *new_div); | 81 | u32 *new_div); |
| 79 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); | 82 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); |
| 80 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); | 83 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); |
| 81 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk); | ||
| 82 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); | 84 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
| 83 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | 85 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
| 86 | int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); | ||
| 84 | u32 omap2_get_dpll_rate(struct clk *clk); | 87 | u32 omap2_get_dpll_rate(struct clk *clk); |
| 85 | void omap2_init_dpll_parent(struct clk *clk); | 88 | void omap2_init_dpll_parent(struct clk *clk); |
| 86 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | 89 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
| 87 | void omap2_clk_prepare_for_reboot(void); | 90 | |
| 91 | |||
| 92 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 93 | void omap2xxx_clk_prepare_for_reboot(void); | ||
| 94 | #else | ||
| 95 | static inline void omap2xxx_clk_prepare_for_reboot(void) | ||
| 96 | { | ||
| 97 | } | ||
| 98 | #endif | ||
| 99 | |||
| 100 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 101 | void omap3_clk_prepare_for_reboot(void); | ||
| 102 | #else | ||
| 103 | static inline void omap3_clk_prepare_for_reboot(void) | ||
| 104 | { | ||
| 105 | } | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 109 | void omap4_clk_prepare_for_reboot(void); | ||
| 110 | #else | ||
| 111 | static inline void omap4_clk_prepare_for_reboot(void) | ||
| 112 | { | ||
| 113 | } | ||
| 114 | #endif | ||
| 115 | |||
| 88 | int omap2_dflt_clk_enable(struct clk *clk); | 116 | int omap2_dflt_clk_enable(struct clk *clk); |
| 89 | void omap2_dflt_clk_disable(struct clk *clk); | 117 | void omap2_dflt_clk_disable(struct clk *clk); |
| 90 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | 118 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
| 91 | u8 *other_bit); | 119 | u8 *other_bit); |
| 92 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | 120 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
| 93 | u8 *idlest_bit); | 121 | u8 *idlest_bit, u8 *idlest_val); |
| 122 | int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); | ||
| 123 | void omap2_clk_print_new_rates(const char *hfclkin_ck_name, | ||
| 124 | const char *core_ck_name, | ||
| 125 | const char *mpu_ck_name); | ||
| 94 | 126 | ||
| 95 | extern u8 cpu_mask; | 127 | extern u8 cpu_mask; |
| 96 | 128 | ||
| 97 | extern const struct clkops clkops_omap2_dflt_wait; | 129 | extern const struct clkops clkops_omap2_dflt_wait; |
| 130 | extern const struct clkops clkops_dummy; | ||
| 98 | extern const struct clkops clkops_omap2_dflt; | 131 | extern const struct clkops clkops_omap2_dflt; |
| 99 | 132 | ||
| 100 | extern struct clk_functions omap2_clk_functions; | 133 | extern struct clk_functions omap2_clk_functions; |
| @@ -104,5 +137,14 @@ extern const struct clksel_rate gpt_32k_rates[]; | |||
| 104 | extern const struct clksel_rate gpt_sys_rates[]; | 137 | extern const struct clksel_rate gpt_sys_rates[]; |
| 105 | extern const struct clksel_rate gfx_l3_rates[]; | 138 | extern const struct clksel_rate gfx_l3_rates[]; |
| 106 | 139 | ||
| 140 | #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) | ||
| 141 | extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); | ||
| 142 | extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); | ||
| 143 | #else | ||
| 144 | #define omap2_clk_init_cpufreq_table 0 | ||
| 145 | #define omap2_clk_exit_cpufreq_table 0 | ||
| 146 | #endif | ||
| 147 | |||
| 148 | extern const struct clkops clkops_omap3_noncore_dpll_ops; | ||
| 107 | 149 | ||
| 108 | #endif | 150 | #endif |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c new file mode 100644 index 000000000000..f12af95ead45 --- /dev/null +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
| @@ -0,0 +1,1910 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/clock2420_data.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/clk.h> | ||
| 18 | #include <linux/list.h> | ||
| 19 | |||
| 20 | #include <plat/clkdev_omap.h> | ||
| 21 | |||
| 22 | #include "clock.h" | ||
| 23 | #include "clock2xxx.h" | ||
| 24 | #include "opp2xxx.h" | ||
| 25 | #include "prm.h" | ||
| 26 | #include "cm.h" | ||
| 27 | #include "prm-regbits-24xx.h" | ||
| 28 | #include "cm-regbits-24xx.h" | ||
| 29 | #include "sdrc.h" | ||
| 30 | |||
| 31 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR | ||
| 32 | |||
| 33 | /* | ||
| 34 | * 2420 clock tree. | ||
| 35 | * | ||
| 36 | * NOTE:In many cases here we are assigning a 'default' parent. In many | ||
| 37 | * cases the parent is selectable. The get/set parent calls will also | ||
| 38 | * switch sources. | ||
| 39 | * | ||
| 40 | * Many some clocks say always_enabled, but they can be auto idled for | ||
| 41 | * power savings. They will always be available upon clock request. | ||
| 42 | * | ||
| 43 | * Several sources are given initial rates which may be wrong, this will | ||
| 44 | * be fixed up in the init func. | ||
| 45 | * | ||
| 46 | * Things are broadly separated below by clock domains. It is | ||
| 47 | * noteworthy that most periferals have dependencies on multiple clock | ||
| 48 | * domains. Many get their interface clocks from the L4 domain, but get | ||
| 49 | * functional clocks from fixed sources or other core domain derived | ||
| 50 | * clocks. | ||
| 51 | */ | ||
| 52 | |||
| 53 | /* Base external input clocks */ | ||
| 54 | static struct clk func_32k_ck = { | ||
| 55 | .name = "func_32k_ck", | ||
| 56 | .ops = &clkops_null, | ||
| 57 | .rate = 32000, | ||
| 58 | .clkdm_name = "wkup_clkdm", | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct clk secure_32k_ck = { | ||
| 62 | .name = "secure_32k_ck", | ||
| 63 | .ops = &clkops_null, | ||
| 64 | .rate = 32768, | ||
| 65 | .clkdm_name = "wkup_clkdm", | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | ||
| 69 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | ||
| 70 | .name = "osc_ck", | ||
| 71 | .ops = &clkops_oscck, | ||
| 72 | .clkdm_name = "wkup_clkdm", | ||
| 73 | .recalc = &omap2_osc_clk_recalc, | ||
| 74 | }; | ||
| 75 | |||
| 76 | /* Without modem likely 12MHz, with modem likely 13MHz */ | ||
| 77 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | ||
| 78 | .name = "sys_ck", /* ~ ref_clk also */ | ||
| 79 | .ops = &clkops_null, | ||
| 80 | .parent = &osc_ck, | ||
| 81 | .clkdm_name = "wkup_clkdm", | ||
| 82 | .recalc = &omap2xxx_sys_clk_recalc, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | ||
| 86 | .name = "alt_ck", | ||
| 87 | .ops = &clkops_null, | ||
| 88 | .rate = 54000000, | ||
| 89 | .clkdm_name = "wkup_clkdm", | ||
| 90 | }; | ||
| 91 | |||
| 92 | /* | ||
| 93 | * Analog domain root source clocks | ||
| 94 | */ | ||
| 95 | |||
| 96 | /* dpll_ck, is broken out in to special cases through clksel */ | ||
| 97 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... | ||
| 98 | * deal with this | ||
| 99 | */ | ||
| 100 | |||
| 101 | static struct dpll_data dpll_dd = { | ||
| 102 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 103 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | ||
| 104 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | ||
| 105 | .clk_bypass = &sys_ck, | ||
| 106 | .clk_ref = &sys_ck, | ||
| 107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | ||
| 109 | .max_multiplier = 1023, | ||
| 110 | .min_divider = 1, | ||
| 111 | .max_divider = 16, | ||
| 112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* | ||
| 116 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | ||
| 117 | * not just a DPLL | ||
| 118 | */ | ||
| 119 | static struct clk dpll_ck = { | ||
| 120 | .name = "dpll_ck", | ||
| 121 | .ops = &clkops_null, | ||
| 122 | .parent = &sys_ck, /* Can be func_32k also */ | ||
| 123 | .dpll_data = &dpll_dd, | ||
| 124 | .clkdm_name = "wkup_clkdm", | ||
| 125 | .recalc = &omap2_dpllcore_recalc, | ||
| 126 | .set_rate = &omap2_reprogram_dpllcore, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct clk apll96_ck = { | ||
| 130 | .name = "apll96_ck", | ||
| 131 | .ops = &clkops_apll96, | ||
| 132 | .parent = &sys_ck, | ||
| 133 | .rate = 96000000, | ||
| 134 | .flags = ENABLE_ON_INIT, | ||
| 135 | .clkdm_name = "wkup_clkdm", | ||
| 136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static struct clk apll54_ck = { | ||
| 141 | .name = "apll54_ck", | ||
| 142 | .ops = &clkops_apll54, | ||
| 143 | .parent = &sys_ck, | ||
| 144 | .rate = 54000000, | ||
| 145 | .flags = ENABLE_ON_INIT, | ||
| 146 | .clkdm_name = "wkup_clkdm", | ||
| 147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | ||
| 149 | }; | ||
| 150 | |||
| 151 | /* | ||
| 152 | * PRCM digital base sources | ||
| 153 | */ | ||
| 154 | |||
| 155 | /* func_54m_ck */ | ||
| 156 | |||
| 157 | static const struct clksel_rate func_54m_apll54_rates[] = { | ||
| 158 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 159 | { .div = 0 }, | ||
| 160 | }; | ||
| 161 | |||
| 162 | static const struct clksel_rate func_54m_alt_rates[] = { | ||
| 163 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 164 | { .div = 0 }, | ||
| 165 | }; | ||
| 166 | |||
| 167 | static const struct clksel func_54m_clksel[] = { | ||
| 168 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | ||
| 169 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | ||
| 170 | { .parent = NULL }, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct clk func_54m_ck = { | ||
| 174 | .name = "func_54m_ck", | ||
| 175 | .ops = &clkops_null, | ||
| 176 | .parent = &apll54_ck, /* can also be alt_clk */ | ||
| 177 | .clkdm_name = "wkup_clkdm", | ||
| 178 | .init = &omap2_init_clksel_parent, | ||
| 179 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 180 | .clksel_mask = OMAP24XX_54M_SOURCE, | ||
| 181 | .clksel = func_54m_clksel, | ||
| 182 | .recalc = &omap2_clksel_recalc, | ||
| 183 | }; | ||
| 184 | |||
| 185 | static struct clk core_ck = { | ||
| 186 | .name = "core_ck", | ||
| 187 | .ops = &clkops_null, | ||
| 188 | .parent = &dpll_ck, /* can also be 32k */ | ||
| 189 | .clkdm_name = "wkup_clkdm", | ||
| 190 | .recalc = &followparent_recalc, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct clk func_96m_ck = { | ||
| 194 | .name = "func_96m_ck", | ||
| 195 | .ops = &clkops_null, | ||
| 196 | .parent = &apll96_ck, | ||
| 197 | .clkdm_name = "wkup_clkdm", | ||
| 198 | .recalc = &followparent_recalc, | ||
| 199 | }; | ||
| 200 | |||
| 201 | /* func_48m_ck */ | ||
| 202 | |||
| 203 | static const struct clksel_rate func_48m_apll96_rates[] = { | ||
| 204 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 205 | { .div = 0 }, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static const struct clksel_rate func_48m_alt_rates[] = { | ||
| 209 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 210 | { .div = 0 }, | ||
| 211 | }; | ||
| 212 | |||
| 213 | static const struct clksel func_48m_clksel[] = { | ||
| 214 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | ||
| 215 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | ||
| 216 | { .parent = NULL } | ||
| 217 | }; | ||
| 218 | |||
| 219 | static struct clk func_48m_ck = { | ||
| 220 | .name = "func_48m_ck", | ||
| 221 | .ops = &clkops_null, | ||
| 222 | .parent = &apll96_ck, /* 96M or Alt */ | ||
| 223 | .clkdm_name = "wkup_clkdm", | ||
| 224 | .init = &omap2_init_clksel_parent, | ||
| 225 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 226 | .clksel_mask = OMAP24XX_48M_SOURCE, | ||
| 227 | .clksel = func_48m_clksel, | ||
| 228 | .recalc = &omap2_clksel_recalc, | ||
| 229 | .round_rate = &omap2_clksel_round_rate, | ||
| 230 | .set_rate = &omap2_clksel_set_rate | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct clk func_12m_ck = { | ||
| 234 | .name = "func_12m_ck", | ||
| 235 | .ops = &clkops_null, | ||
| 236 | .parent = &func_48m_ck, | ||
| 237 | .fixed_div = 4, | ||
| 238 | .clkdm_name = "wkup_clkdm", | ||
| 239 | .recalc = &omap_fixed_divisor_recalc, | ||
| 240 | }; | ||
| 241 | |||
| 242 | /* Secure timer, only available in secure mode */ | ||
| 243 | static struct clk wdt1_osc_ck = { | ||
| 244 | .name = "ck_wdt1_osc", | ||
| 245 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 246 | .parent = &osc_ck, | ||
| 247 | .recalc = &followparent_recalc, | ||
| 248 | }; | ||
| 249 | |||
| 250 | /* | ||
| 251 | * The common_clkout* clksel_rate structs are common to | ||
| 252 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | ||
| 253 | * sys_clkout2_* are 2420-only, so the | ||
| 254 | * clksel_rate flags fields are inaccurate for those clocks. This is | ||
| 255 | * harmless since access to those clocks are gated by the struct clk | ||
| 256 | * flags fields, which mark them as 2420-only. | ||
| 257 | */ | ||
| 258 | static const struct clksel_rate common_clkout_src_core_rates[] = { | ||
| 259 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 260 | { .div = 0 } | ||
| 261 | }; | ||
| 262 | |||
| 263 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | ||
| 264 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 265 | { .div = 0 } | ||
| 266 | }; | ||
| 267 | |||
| 268 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | ||
| 269 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 270 | { .div = 0 } | ||
| 271 | }; | ||
| 272 | |||
| 273 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | ||
| 274 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 275 | { .div = 0 } | ||
| 276 | }; | ||
| 277 | |||
| 278 | static const struct clksel common_clkout_src_clksel[] = { | ||
| 279 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | ||
| 280 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | ||
| 281 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | ||
| 282 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | ||
| 283 | { .parent = NULL } | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct clk sys_clkout_src = { | ||
| 287 | .name = "sys_clkout_src", | ||
| 288 | .ops = &clkops_omap2_dflt, | ||
| 289 | .parent = &func_54m_ck, | ||
| 290 | .clkdm_name = "wkup_clkdm", | ||
| 291 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
| 292 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | ||
| 293 | .init = &omap2_init_clksel_parent, | ||
| 294 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
| 295 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, | ||
| 296 | .clksel = common_clkout_src_clksel, | ||
| 297 | .recalc = &omap2_clksel_recalc, | ||
| 298 | .round_rate = &omap2_clksel_round_rate, | ||
| 299 | .set_rate = &omap2_clksel_set_rate | ||
| 300 | }; | ||
| 301 | |||
| 302 | static const struct clksel_rate common_clkout_rates[] = { | ||
| 303 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 304 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, | ||
| 305 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | ||
| 306 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | ||
| 307 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | ||
| 308 | { .div = 0 }, | ||
| 309 | }; | ||
| 310 | |||
| 311 | static const struct clksel sys_clkout_clksel[] = { | ||
| 312 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | ||
| 313 | { .parent = NULL } | ||
| 314 | }; | ||
| 315 | |||
| 316 | static struct clk sys_clkout = { | ||
| 317 | .name = "sys_clkout", | ||
| 318 | .ops = &clkops_null, | ||
| 319 | .parent = &sys_clkout_src, | ||
| 320 | .clkdm_name = "wkup_clkdm", | ||
| 321 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
| 322 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | ||
| 323 | .clksel = sys_clkout_clksel, | ||
| 324 | .recalc = &omap2_clksel_recalc, | ||
| 325 | .round_rate = &omap2_clksel_round_rate, | ||
| 326 | .set_rate = &omap2_clksel_set_rate | ||
| 327 | }; | ||
| 328 | |||
| 329 | /* In 2430, new in 2420 ES2 */ | ||
| 330 | static struct clk sys_clkout2_src = { | ||
| 331 | .name = "sys_clkout2_src", | ||
| 332 | .ops = &clkops_omap2_dflt, | ||
| 333 | .parent = &func_54m_ck, | ||
| 334 | .clkdm_name = "wkup_clkdm", | ||
| 335 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
| 336 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | ||
| 337 | .init = &omap2_init_clksel_parent, | ||
| 338 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
| 339 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, | ||
| 340 | .clksel = common_clkout_src_clksel, | ||
| 341 | .recalc = &omap2_clksel_recalc, | ||
| 342 | .round_rate = &omap2_clksel_round_rate, | ||
| 343 | .set_rate = &omap2_clksel_set_rate | ||
| 344 | }; | ||
| 345 | |||
| 346 | static const struct clksel sys_clkout2_clksel[] = { | ||
| 347 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | ||
| 348 | { .parent = NULL } | ||
| 349 | }; | ||
| 350 | |||
| 351 | /* In 2430, new in 2420 ES2 */ | ||
| 352 | static struct clk sys_clkout2 = { | ||
| 353 | .name = "sys_clkout2", | ||
| 354 | .ops = &clkops_null, | ||
| 355 | .parent = &sys_clkout2_src, | ||
| 356 | .clkdm_name = "wkup_clkdm", | ||
| 357 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
| 358 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | ||
| 359 | .clksel = sys_clkout2_clksel, | ||
| 360 | .recalc = &omap2_clksel_recalc, | ||
| 361 | .round_rate = &omap2_clksel_round_rate, | ||
| 362 | .set_rate = &omap2_clksel_set_rate | ||
| 363 | }; | ||
| 364 | |||
| 365 | static struct clk emul_ck = { | ||
| 366 | .name = "emul_ck", | ||
| 367 | .ops = &clkops_omap2_dflt, | ||
| 368 | .parent = &func_54m_ck, | ||
| 369 | .clkdm_name = "wkup_clkdm", | ||
| 370 | .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, | ||
| 371 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | ||
| 372 | .recalc = &followparent_recalc, | ||
| 373 | |||
| 374 | }; | ||
| 375 | |||
| 376 | /* | ||
| 377 | * MPU clock domain | ||
| 378 | * Clocks: | ||
| 379 | * MPU_FCLK, MPU_ICLK | ||
| 380 | * INT_M_FCLK, INT_M_I_CLK | ||
| 381 | * | ||
| 382 | * - Individual clocks are hardware managed. | ||
| 383 | * - Base divider comes from: CM_CLKSEL_MPU | ||
| 384 | * | ||
| 385 | */ | ||
| 386 | static const struct clksel_rate mpu_core_rates[] = { | ||
| 387 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 388 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 389 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
| 390 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 391 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 392 | { .div = 0 }, | ||
| 393 | }; | ||
| 394 | |||
| 395 | static const struct clksel mpu_clksel[] = { | ||
| 396 | { .parent = &core_ck, .rates = mpu_core_rates }, | ||
| 397 | { .parent = NULL } | ||
| 398 | }; | ||
| 399 | |||
| 400 | static struct clk mpu_ck = { /* Control cpu */ | ||
| 401 | .name = "mpu_ck", | ||
| 402 | .ops = &clkops_null, | ||
| 403 | .parent = &core_ck, | ||
| 404 | .clkdm_name = "mpu_clkdm", | ||
| 405 | .init = &omap2_init_clksel_parent, | ||
| 406 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | ||
| 407 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | ||
| 408 | .clksel = mpu_clksel, | ||
| 409 | .recalc = &omap2_clksel_recalc, | ||
| 410 | }; | ||
| 411 | |||
| 412 | /* | ||
| 413 | * DSP (2420-UMA+IVA1) clock domain | ||
| 414 | * Clocks: | ||
| 415 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP | ||
| 416 | * | ||
| 417 | * Won't be too specific here. The core clock comes into this block | ||
| 418 | * it is divided then tee'ed. One branch goes directly to xyz enable | ||
| 419 | * controls. The other branch gets further divided by 2 then possibly | ||
| 420 | * routed into a synchronizer and out of clocks abc. | ||
| 421 | */ | ||
| 422 | static const struct clksel_rate dsp_fck_core_rates[] = { | ||
| 423 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 424 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 425 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
| 426 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 427 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 428 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 429 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 430 | { .div = 0 }, | ||
| 431 | }; | ||
| 432 | |||
| 433 | static const struct clksel dsp_fck_clksel[] = { | ||
| 434 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | ||
| 435 | { .parent = NULL } | ||
| 436 | }; | ||
| 437 | |||
| 438 | static struct clk dsp_fck = { | ||
| 439 | .name = "dsp_fck", | ||
| 440 | .ops = &clkops_omap2_dflt_wait, | ||
| 441 | .parent = &core_ck, | ||
| 442 | .clkdm_name = "dsp_clkdm", | ||
| 443 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 444 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | ||
| 445 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 446 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | ||
| 447 | .clksel = dsp_fck_clksel, | ||
| 448 | .recalc = &omap2_clksel_recalc, | ||
| 449 | }; | ||
| 450 | |||
| 451 | /* DSP interface clock */ | ||
| 452 | static const struct clksel_rate dsp_irate_ick_rates[] = { | ||
| 453 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 454 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 455 | { .div = 0 }, | ||
| 456 | }; | ||
| 457 | |||
| 458 | static const struct clksel dsp_irate_ick_clksel[] = { | ||
| 459 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | ||
| 460 | { .parent = NULL } | ||
| 461 | }; | ||
| 462 | |||
| 463 | /* This clock does not exist as such in the TRM. */ | ||
| 464 | static struct clk dsp_irate_ick = { | ||
| 465 | .name = "dsp_irate_ick", | ||
| 466 | .ops = &clkops_null, | ||
| 467 | .parent = &dsp_fck, | ||
| 468 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 469 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | ||
| 470 | .clksel = dsp_irate_ick_clksel, | ||
| 471 | .recalc = &omap2_clksel_recalc, | ||
| 472 | }; | ||
| 473 | |||
| 474 | /* 2420 only */ | ||
| 475 | static struct clk dsp_ick = { | ||
| 476 | .name = "dsp_ick", /* apparently ipi and isp */ | ||
| 477 | .ops = &clkops_omap2_dflt_wait, | ||
| 478 | .parent = &dsp_irate_ick, | ||
| 479 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | ||
| 480 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | ||
| 481 | }; | ||
| 482 | |||
| 483 | /* | ||
| 484 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | ||
| 485 | * the C54x, but which is contained in the DSP powerdomain. Does not | ||
| 486 | * exist on later OMAPs. | ||
| 487 | */ | ||
| 488 | static struct clk iva1_ifck = { | ||
| 489 | .name = "iva1_ifck", | ||
| 490 | .ops = &clkops_omap2_dflt_wait, | ||
| 491 | .parent = &core_ck, | ||
| 492 | .clkdm_name = "iva1_clkdm", | ||
| 493 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 494 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | ||
| 495 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 496 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | ||
| 497 | .clksel = dsp_fck_clksel, | ||
| 498 | .recalc = &omap2_clksel_recalc, | ||
| 499 | }; | ||
| 500 | |||
| 501 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | ||
| 502 | static struct clk iva1_mpu_int_ifck = { | ||
| 503 | .name = "iva1_mpu_int_ifck", | ||
| 504 | .ops = &clkops_omap2_dflt_wait, | ||
| 505 | .parent = &iva1_ifck, | ||
| 506 | .clkdm_name = "iva1_clkdm", | ||
| 507 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 508 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | ||
| 509 | .fixed_div = 2, | ||
| 510 | .recalc = &omap_fixed_divisor_recalc, | ||
| 511 | }; | ||
| 512 | |||
| 513 | /* | ||
| 514 | * L3 clock domain | ||
| 515 | * L3 clocks are used for both interface and functional clocks to | ||
| 516 | * multiple entities. Some of these clocks are completely managed | ||
| 517 | * by hardware, and some others allow software control. Hardware | ||
| 518 | * managed ones general are based on directly CLK_REQ signals and | ||
| 519 | * various auto idle settings. The functional spec sets many of these | ||
| 520 | * as 'tie-high' for their enables. | ||
| 521 | * | ||
| 522 | * I-CLOCKS: | ||
| 523 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | ||
| 524 | * CAM, HS-USB. | ||
| 525 | * F-CLOCK | ||
| 526 | * SSI. | ||
| 527 | * | ||
| 528 | * GPMC memories and SDRC have timing and clock sensitive registers which | ||
| 529 | * may very well need notification when the clock changes. Currently for low | ||
| 530 | * operating points, these are taken care of in sleep.S. | ||
| 531 | */ | ||
| 532 | static const struct clksel_rate core_l3_core_rates[] = { | ||
| 533 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 534 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
| 535 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 536 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | ||
| 537 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 538 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 539 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | ||
| 540 | { .div = 0 } | ||
| 541 | }; | ||
| 542 | |||
| 543 | static const struct clksel core_l3_clksel[] = { | ||
| 544 | { .parent = &core_ck, .rates = core_l3_core_rates }, | ||
| 545 | { .parent = NULL } | ||
| 546 | }; | ||
| 547 | |||
| 548 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | ||
| 549 | .name = "core_l3_ck", | ||
| 550 | .ops = &clkops_null, | ||
| 551 | .parent = &core_ck, | ||
| 552 | .clkdm_name = "core_l3_clkdm", | ||
| 553 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 554 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | ||
| 555 | .clksel = core_l3_clksel, | ||
| 556 | .recalc = &omap2_clksel_recalc, | ||
| 557 | }; | ||
| 558 | |||
| 559 | /* usb_l4_ick */ | ||
| 560 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | ||
| 561 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 562 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 563 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 564 | { .div = 0 } | ||
| 565 | }; | ||
| 566 | |||
| 567 | static const struct clksel usb_l4_ick_clksel[] = { | ||
| 568 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | ||
| 569 | { .parent = NULL }, | ||
| 570 | }; | ||
| 571 | |||
| 572 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ | ||
| 573 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | ||
| 574 | .name = "usb_l4_ick", | ||
| 575 | .ops = &clkops_omap2_dflt_wait, | ||
| 576 | .parent = &core_l3_ck, | ||
| 577 | .clkdm_name = "core_l4_clkdm", | ||
| 578 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 579 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | ||
| 580 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 581 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | ||
| 582 | .clksel = usb_l4_ick_clksel, | ||
| 583 | .recalc = &omap2_clksel_recalc, | ||
| 584 | }; | ||
| 585 | |||
| 586 | /* | ||
| 587 | * L4 clock management domain | ||
| 588 | * | ||
| 589 | * This domain contains lots of interface clocks from the L4 interface, some | ||
| 590 | * functional clocks. Fixed APLL functional source clocks are managed in | ||
| 591 | * this domain. | ||
| 592 | */ | ||
| 593 | static const struct clksel_rate l4_core_l3_rates[] = { | ||
| 594 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 595 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 596 | { .div = 0 } | ||
| 597 | }; | ||
| 598 | |||
| 599 | static const struct clksel l4_clksel[] = { | ||
| 600 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | ||
| 601 | { .parent = NULL } | ||
| 602 | }; | ||
| 603 | |||
| 604 | static struct clk l4_ck = { /* used both as an ick and fck */ | ||
| 605 | .name = "l4_ck", | ||
| 606 | .ops = &clkops_null, | ||
| 607 | .parent = &core_l3_ck, | ||
| 608 | .clkdm_name = "core_l4_clkdm", | ||
| 609 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 610 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | ||
| 611 | .clksel = l4_clksel, | ||
| 612 | .recalc = &omap2_clksel_recalc, | ||
| 613 | }; | ||
| 614 | |||
| 615 | /* | ||
| 616 | * SSI is in L3 management domain, its direct parent is core not l3, | ||
| 617 | * many core power domain entities are grouped into the L3 clock | ||
| 618 | * domain. | ||
| 619 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK | ||
| 620 | * | ||
| 621 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | ||
| 622 | */ | ||
| 623 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { | ||
| 624 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 625 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 626 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
| 627 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 628 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 629 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 630 | { .div = 0 } | ||
| 631 | }; | ||
| 632 | |||
| 633 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | ||
| 634 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | ||
| 635 | { .parent = NULL } | ||
| 636 | }; | ||
| 637 | |||
| 638 | static struct clk ssi_ssr_sst_fck = { | ||
| 639 | .name = "ssi_fck", | ||
| 640 | .ops = &clkops_omap2_dflt_wait, | ||
| 641 | .parent = &core_ck, | ||
| 642 | .clkdm_name = "core_l3_clkdm", | ||
| 643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 644 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
| 645 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 646 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | ||
| 647 | .clksel = ssi_ssr_sst_fck_clksel, | ||
| 648 | .recalc = &omap2_clksel_recalc, | ||
| 649 | }; | ||
| 650 | |||
| 651 | /* | ||
| 652 | * Presumably this is the same as SSI_ICLK. | ||
| 653 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | ||
| 654 | */ | ||
| 655 | static struct clk ssi_l4_ick = { | ||
| 656 | .name = "ssi_l4_ick", | ||
| 657 | .ops = &clkops_omap2_dflt_wait, | ||
| 658 | .parent = &l4_ck, | ||
| 659 | .clkdm_name = "core_l4_clkdm", | ||
| 660 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 661 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
| 662 | .recalc = &followparent_recalc, | ||
| 663 | }; | ||
| 664 | |||
| 665 | |||
| 666 | /* | ||
| 667 | * GFX clock domain | ||
| 668 | * Clocks: | ||
| 669 | * GFX_FCLK, GFX_ICLK | ||
| 670 | * GFX_CG1(2d), GFX_CG2(3d) | ||
| 671 | * | ||
| 672 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | ||
| 673 | * The 2d and 3d clocks run at a hardware determined | ||
| 674 | * divided value of fclk. | ||
| 675 | * | ||
| 676 | */ | ||
| 677 | |||
| 678 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | ||
| 679 | static const struct clksel gfx_fck_clksel[] = { | ||
| 680 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | ||
| 681 | { .parent = NULL }, | ||
| 682 | }; | ||
| 683 | |||
| 684 | static struct clk gfx_3d_fck = { | ||
| 685 | .name = "gfx_3d_fck", | ||
| 686 | .ops = &clkops_omap2_dflt_wait, | ||
| 687 | .parent = &core_l3_ck, | ||
| 688 | .clkdm_name = "gfx_clkdm", | ||
| 689 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
| 690 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | ||
| 691 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
| 692 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
| 693 | .clksel = gfx_fck_clksel, | ||
| 694 | .recalc = &omap2_clksel_recalc, | ||
| 695 | .round_rate = &omap2_clksel_round_rate, | ||
| 696 | .set_rate = &omap2_clksel_set_rate | ||
| 697 | }; | ||
| 698 | |||
| 699 | static struct clk gfx_2d_fck = { | ||
| 700 | .name = "gfx_2d_fck", | ||
| 701 | .ops = &clkops_omap2_dflt_wait, | ||
| 702 | .parent = &core_l3_ck, | ||
| 703 | .clkdm_name = "gfx_clkdm", | ||
| 704 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
| 705 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | ||
| 706 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
| 707 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
| 708 | .clksel = gfx_fck_clksel, | ||
| 709 | .recalc = &omap2_clksel_recalc, | ||
| 710 | }; | ||
| 711 | |||
| 712 | static struct clk gfx_ick = { | ||
| 713 | .name = "gfx_ick", /* From l3 */ | ||
| 714 | .ops = &clkops_omap2_dflt_wait, | ||
| 715 | .parent = &core_l3_ck, | ||
| 716 | .clkdm_name = "gfx_clkdm", | ||
| 717 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
| 718 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
| 719 | .recalc = &followparent_recalc, | ||
| 720 | }; | ||
| 721 | |||
| 722 | /* | ||
| 723 | * DSS clock domain | ||
| 724 | * CLOCKs: | ||
| 725 | * DSS_L4_ICLK, DSS_L3_ICLK, | ||
| 726 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | ||
| 727 | * | ||
| 728 | * DSS is both initiator and target. | ||
| 729 | */ | ||
| 730 | /* XXX Add RATE_NOT_VALIDATED */ | ||
| 731 | |||
| 732 | static const struct clksel_rate dss1_fck_sys_rates[] = { | ||
| 733 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 734 | { .div = 0 } | ||
| 735 | }; | ||
| 736 | |||
| 737 | static const struct clksel_rate dss1_fck_core_rates[] = { | ||
| 738 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 739 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 740 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
| 741 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 742 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | ||
| 743 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | ||
| 744 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | ||
| 745 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | ||
| 746 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | ||
| 747 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 748 | { .div = 0 } | ||
| 749 | }; | ||
| 750 | |||
| 751 | static const struct clksel dss1_fck_clksel[] = { | ||
| 752 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | ||
| 753 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | ||
| 754 | { .parent = NULL }, | ||
| 755 | }; | ||
| 756 | |||
| 757 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | ||
| 758 | .name = "dss_ick", | ||
| 759 | .ops = &clkops_omap2_dflt, | ||
| 760 | .parent = &l4_ck, /* really both l3 and l4 */ | ||
| 761 | .clkdm_name = "dss_clkdm", | ||
| 762 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 763 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
| 764 | .recalc = &followparent_recalc, | ||
| 765 | }; | ||
| 766 | |||
| 767 | static struct clk dss1_fck = { | ||
| 768 | .name = "dss1_fck", | ||
| 769 | .ops = &clkops_omap2_dflt, | ||
| 770 | .parent = &core_ck, /* Core or sys */ | ||
| 771 | .clkdm_name = "dss_clkdm", | ||
| 772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 773 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
| 774 | .init = &omap2_init_clksel_parent, | ||
| 775 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 776 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | ||
| 777 | .clksel = dss1_fck_clksel, | ||
| 778 | .recalc = &omap2_clksel_recalc, | ||
| 779 | }; | ||
| 780 | |||
| 781 | static const struct clksel_rate dss2_fck_sys_rates[] = { | ||
| 782 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 783 | { .div = 0 } | ||
| 784 | }; | ||
| 785 | |||
| 786 | static const struct clksel_rate dss2_fck_48m_rates[] = { | ||
| 787 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 788 | { .div = 0 } | ||
| 789 | }; | ||
| 790 | |||
| 791 | static const struct clksel dss2_fck_clksel[] = { | ||
| 792 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | ||
| 793 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | ||
| 794 | { .parent = NULL } | ||
| 795 | }; | ||
| 796 | |||
| 797 | static struct clk dss2_fck = { /* Alt clk used in power management */ | ||
| 798 | .name = "dss2_fck", | ||
| 799 | .ops = &clkops_omap2_dflt, | ||
| 800 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | ||
| 801 | .clkdm_name = "dss_clkdm", | ||
| 802 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 803 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | ||
| 804 | .init = &omap2_init_clksel_parent, | ||
| 805 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 806 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | ||
| 807 | .clksel = dss2_fck_clksel, | ||
| 808 | .recalc = &followparent_recalc, | ||
| 809 | }; | ||
| 810 | |||
| 811 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | ||
| 812 | .name = "dss_54m_fck", /* 54m tv clk */ | ||
| 813 | .ops = &clkops_omap2_dflt_wait, | ||
| 814 | .parent = &func_54m_ck, | ||
| 815 | .clkdm_name = "dss_clkdm", | ||
| 816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 817 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | ||
| 818 | .recalc = &followparent_recalc, | ||
| 819 | }; | ||
| 820 | |||
| 821 | /* | ||
| 822 | * CORE power domain ICLK & FCLK defines. | ||
| 823 | * Many of the these can have more than one possible parent. Entries | ||
| 824 | * here will likely have an L4 interface parent, and may have multiple | ||
| 825 | * functional clock parents. | ||
| 826 | */ | ||
| 827 | static const struct clksel_rate gpt_alt_rates[] = { | ||
| 828 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 829 | { .div = 0 } | ||
| 830 | }; | ||
| 831 | |||
| 832 | static const struct clksel omap24xx_gpt_clksel[] = { | ||
| 833 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | ||
| 834 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | ||
| 835 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | ||
| 836 | { .parent = NULL }, | ||
| 837 | }; | ||
| 838 | |||
| 839 | static struct clk gpt1_ick = { | ||
| 840 | .name = "gpt1_ick", | ||
| 841 | .ops = &clkops_omap2_dflt_wait, | ||
| 842 | .parent = &l4_ck, | ||
| 843 | .clkdm_name = "core_l4_clkdm", | ||
| 844 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 845 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
| 846 | .recalc = &followparent_recalc, | ||
| 847 | }; | ||
| 848 | |||
| 849 | static struct clk gpt1_fck = { | ||
| 850 | .name = "gpt1_fck", | ||
| 851 | .ops = &clkops_omap2_dflt_wait, | ||
| 852 | .parent = &func_32k_ck, | ||
| 853 | .clkdm_name = "core_l4_clkdm", | ||
| 854 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 855 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
| 856 | .init = &omap2_init_clksel_parent, | ||
| 857 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | ||
| 858 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | ||
| 859 | .clksel = omap24xx_gpt_clksel, | ||
| 860 | .recalc = &omap2_clksel_recalc, | ||
| 861 | .round_rate = &omap2_clksel_round_rate, | ||
| 862 | .set_rate = &omap2_clksel_set_rate | ||
| 863 | }; | ||
| 864 | |||
| 865 | static struct clk gpt2_ick = { | ||
| 866 | .name = "gpt2_ick", | ||
| 867 | .ops = &clkops_omap2_dflt_wait, | ||
| 868 | .parent = &l4_ck, | ||
| 869 | .clkdm_name = "core_l4_clkdm", | ||
| 870 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 871 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
| 872 | .recalc = &followparent_recalc, | ||
| 873 | }; | ||
| 874 | |||
| 875 | static struct clk gpt2_fck = { | ||
| 876 | .name = "gpt2_fck", | ||
| 877 | .ops = &clkops_omap2_dflt_wait, | ||
| 878 | .parent = &func_32k_ck, | ||
| 879 | .clkdm_name = "core_l4_clkdm", | ||
| 880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 881 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
| 882 | .init = &omap2_init_clksel_parent, | ||
| 883 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 884 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | ||
| 885 | .clksel = omap24xx_gpt_clksel, | ||
| 886 | .recalc = &omap2_clksel_recalc, | ||
| 887 | }; | ||
| 888 | |||
| 889 | static struct clk gpt3_ick = { | ||
| 890 | .name = "gpt3_ick", | ||
| 891 | .ops = &clkops_omap2_dflt_wait, | ||
| 892 | .parent = &l4_ck, | ||
| 893 | .clkdm_name = "core_l4_clkdm", | ||
| 894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 895 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
| 896 | .recalc = &followparent_recalc, | ||
| 897 | }; | ||
| 898 | |||
| 899 | static struct clk gpt3_fck = { | ||
| 900 | .name = "gpt3_fck", | ||
| 901 | .ops = &clkops_omap2_dflt_wait, | ||
| 902 | .parent = &func_32k_ck, | ||
| 903 | .clkdm_name = "core_l4_clkdm", | ||
| 904 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 905 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
| 906 | .init = &omap2_init_clksel_parent, | ||
| 907 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 908 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | ||
| 909 | .clksel = omap24xx_gpt_clksel, | ||
| 910 | .recalc = &omap2_clksel_recalc, | ||
| 911 | }; | ||
| 912 | |||
| 913 | static struct clk gpt4_ick = { | ||
| 914 | .name = "gpt4_ick", | ||
| 915 | .ops = &clkops_omap2_dflt_wait, | ||
| 916 | .parent = &l4_ck, | ||
| 917 | .clkdm_name = "core_l4_clkdm", | ||
| 918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 919 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
| 920 | .recalc = &followparent_recalc, | ||
| 921 | }; | ||
| 922 | |||
| 923 | static struct clk gpt4_fck = { | ||
| 924 | .name = "gpt4_fck", | ||
| 925 | .ops = &clkops_omap2_dflt_wait, | ||
| 926 | .parent = &func_32k_ck, | ||
| 927 | .clkdm_name = "core_l4_clkdm", | ||
| 928 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 929 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
| 930 | .init = &omap2_init_clksel_parent, | ||
| 931 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 932 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | ||
| 933 | .clksel = omap24xx_gpt_clksel, | ||
| 934 | .recalc = &omap2_clksel_recalc, | ||
| 935 | }; | ||
| 936 | |||
| 937 | static struct clk gpt5_ick = { | ||
| 938 | .name = "gpt5_ick", | ||
| 939 | .ops = &clkops_omap2_dflt_wait, | ||
| 940 | .parent = &l4_ck, | ||
| 941 | .clkdm_name = "core_l4_clkdm", | ||
| 942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 943 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
| 944 | .recalc = &followparent_recalc, | ||
| 945 | }; | ||
| 946 | |||
| 947 | static struct clk gpt5_fck = { | ||
| 948 | .name = "gpt5_fck", | ||
| 949 | .ops = &clkops_omap2_dflt_wait, | ||
| 950 | .parent = &func_32k_ck, | ||
| 951 | .clkdm_name = "core_l4_clkdm", | ||
| 952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 953 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
| 954 | .init = &omap2_init_clksel_parent, | ||
| 955 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 956 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | ||
| 957 | .clksel = omap24xx_gpt_clksel, | ||
| 958 | .recalc = &omap2_clksel_recalc, | ||
| 959 | }; | ||
| 960 | |||
| 961 | static struct clk gpt6_ick = { | ||
| 962 | .name = "gpt6_ick", | ||
| 963 | .ops = &clkops_omap2_dflt_wait, | ||
| 964 | .parent = &l4_ck, | ||
| 965 | .clkdm_name = "core_l4_clkdm", | ||
| 966 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 967 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
| 968 | .recalc = &followparent_recalc, | ||
| 969 | }; | ||
| 970 | |||
| 971 | static struct clk gpt6_fck = { | ||
| 972 | .name = "gpt6_fck", | ||
| 973 | .ops = &clkops_omap2_dflt_wait, | ||
| 974 | .parent = &func_32k_ck, | ||
| 975 | .clkdm_name = "core_l4_clkdm", | ||
| 976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 977 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
| 978 | .init = &omap2_init_clksel_parent, | ||
| 979 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 980 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | ||
| 981 | .clksel = omap24xx_gpt_clksel, | ||
| 982 | .recalc = &omap2_clksel_recalc, | ||
| 983 | }; | ||
| 984 | |||
| 985 | static struct clk gpt7_ick = { | ||
| 986 | .name = "gpt7_ick", | ||
| 987 | .ops = &clkops_omap2_dflt_wait, | ||
| 988 | .parent = &l4_ck, | ||
| 989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 990 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
| 991 | .recalc = &followparent_recalc, | ||
| 992 | }; | ||
| 993 | |||
| 994 | static struct clk gpt7_fck = { | ||
| 995 | .name = "gpt7_fck", | ||
| 996 | .ops = &clkops_omap2_dflt_wait, | ||
| 997 | .parent = &func_32k_ck, | ||
| 998 | .clkdm_name = "core_l4_clkdm", | ||
| 999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1000 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
| 1001 | .init = &omap2_init_clksel_parent, | ||
| 1002 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1003 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | ||
| 1004 | .clksel = omap24xx_gpt_clksel, | ||
| 1005 | .recalc = &omap2_clksel_recalc, | ||
| 1006 | }; | ||
| 1007 | |||
| 1008 | static struct clk gpt8_ick = { | ||
| 1009 | .name = "gpt8_ick", | ||
| 1010 | .ops = &clkops_omap2_dflt_wait, | ||
| 1011 | .parent = &l4_ck, | ||
| 1012 | .clkdm_name = "core_l4_clkdm", | ||
| 1013 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1014 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
| 1015 | .recalc = &followparent_recalc, | ||
| 1016 | }; | ||
| 1017 | |||
| 1018 | static struct clk gpt8_fck = { | ||
| 1019 | .name = "gpt8_fck", | ||
| 1020 | .ops = &clkops_omap2_dflt_wait, | ||
| 1021 | .parent = &func_32k_ck, | ||
| 1022 | .clkdm_name = "core_l4_clkdm", | ||
| 1023 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1024 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
| 1025 | .init = &omap2_init_clksel_parent, | ||
| 1026 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1027 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | ||
| 1028 | .clksel = omap24xx_gpt_clksel, | ||
| 1029 | .recalc = &omap2_clksel_recalc, | ||
| 1030 | }; | ||
| 1031 | |||
| 1032 | static struct clk gpt9_ick = { | ||
| 1033 | .name = "gpt9_ick", | ||
| 1034 | .ops = &clkops_omap2_dflt_wait, | ||
| 1035 | .parent = &l4_ck, | ||
| 1036 | .clkdm_name = "core_l4_clkdm", | ||
| 1037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1038 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
| 1039 | .recalc = &followparent_recalc, | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | static struct clk gpt9_fck = { | ||
| 1043 | .name = "gpt9_fck", | ||
| 1044 | .ops = &clkops_omap2_dflt_wait, | ||
| 1045 | .parent = &func_32k_ck, | ||
| 1046 | .clkdm_name = "core_l4_clkdm", | ||
| 1047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1048 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
| 1049 | .init = &omap2_init_clksel_parent, | ||
| 1050 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1051 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | ||
| 1052 | .clksel = omap24xx_gpt_clksel, | ||
| 1053 | .recalc = &omap2_clksel_recalc, | ||
| 1054 | }; | ||
| 1055 | |||
| 1056 | static struct clk gpt10_ick = { | ||
| 1057 | .name = "gpt10_ick", | ||
| 1058 | .ops = &clkops_omap2_dflt_wait, | ||
| 1059 | .parent = &l4_ck, | ||
| 1060 | .clkdm_name = "core_l4_clkdm", | ||
| 1061 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1062 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
| 1063 | .recalc = &followparent_recalc, | ||
| 1064 | }; | ||
| 1065 | |||
| 1066 | static struct clk gpt10_fck = { | ||
| 1067 | .name = "gpt10_fck", | ||
| 1068 | .ops = &clkops_omap2_dflt_wait, | ||
| 1069 | .parent = &func_32k_ck, | ||
| 1070 | .clkdm_name = "core_l4_clkdm", | ||
| 1071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1072 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
| 1073 | .init = &omap2_init_clksel_parent, | ||
| 1074 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1075 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | ||
| 1076 | .clksel = omap24xx_gpt_clksel, | ||
| 1077 | .recalc = &omap2_clksel_recalc, | ||
| 1078 | }; | ||
| 1079 | |||
| 1080 | static struct clk gpt11_ick = { | ||
| 1081 | .name = "gpt11_ick", | ||
| 1082 | .ops = &clkops_omap2_dflt_wait, | ||
| 1083 | .parent = &l4_ck, | ||
| 1084 | .clkdm_name = "core_l4_clkdm", | ||
| 1085 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1086 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
| 1087 | .recalc = &followparent_recalc, | ||
| 1088 | }; | ||
| 1089 | |||
| 1090 | static struct clk gpt11_fck = { | ||
| 1091 | .name = "gpt11_fck", | ||
| 1092 | .ops = &clkops_omap2_dflt_wait, | ||
| 1093 | .parent = &func_32k_ck, | ||
| 1094 | .clkdm_name = "core_l4_clkdm", | ||
| 1095 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1096 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
| 1097 | .init = &omap2_init_clksel_parent, | ||
| 1098 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1099 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | ||
| 1100 | .clksel = omap24xx_gpt_clksel, | ||
| 1101 | .recalc = &omap2_clksel_recalc, | ||
| 1102 | }; | ||
| 1103 | |||
| 1104 | static struct clk gpt12_ick = { | ||
| 1105 | .name = "gpt12_ick", | ||
| 1106 | .ops = &clkops_omap2_dflt_wait, | ||
| 1107 | .parent = &l4_ck, | ||
| 1108 | .clkdm_name = "core_l4_clkdm", | ||
| 1109 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1110 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
| 1111 | .recalc = &followparent_recalc, | ||
| 1112 | }; | ||
| 1113 | |||
| 1114 | static struct clk gpt12_fck = { | ||
| 1115 | .name = "gpt12_fck", | ||
| 1116 | .ops = &clkops_omap2_dflt_wait, | ||
| 1117 | .parent = &secure_32k_ck, | ||
| 1118 | .clkdm_name = "core_l4_clkdm", | ||
| 1119 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1120 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
| 1121 | .init = &omap2_init_clksel_parent, | ||
| 1122 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1123 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | ||
| 1124 | .clksel = omap24xx_gpt_clksel, | ||
| 1125 | .recalc = &omap2_clksel_recalc, | ||
| 1126 | }; | ||
| 1127 | |||
| 1128 | static struct clk mcbsp1_ick = { | ||
| 1129 | .name = "mcbsp1_ick", | ||
| 1130 | .ops = &clkops_omap2_dflt_wait, | ||
| 1131 | .parent = &l4_ck, | ||
| 1132 | .clkdm_name = "core_l4_clkdm", | ||
| 1133 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1134 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
| 1135 | .recalc = &followparent_recalc, | ||
| 1136 | }; | ||
| 1137 | |||
| 1138 | static struct clk mcbsp1_fck = { | ||
| 1139 | .name = "mcbsp1_fck", | ||
| 1140 | .ops = &clkops_omap2_dflt_wait, | ||
| 1141 | .parent = &func_96m_ck, | ||
| 1142 | .clkdm_name = "core_l4_clkdm", | ||
| 1143 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1144 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
| 1145 | .recalc = &followparent_recalc, | ||
| 1146 | }; | ||
| 1147 | |||
| 1148 | static struct clk mcbsp2_ick = { | ||
| 1149 | .name = "mcbsp2_ick", | ||
| 1150 | .ops = &clkops_omap2_dflt_wait, | ||
| 1151 | .parent = &l4_ck, | ||
| 1152 | .clkdm_name = "core_l4_clkdm", | ||
| 1153 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1154 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
| 1155 | .recalc = &followparent_recalc, | ||
| 1156 | }; | ||
| 1157 | |||
| 1158 | static struct clk mcbsp2_fck = { | ||
| 1159 | .name = "mcbsp2_fck", | ||
| 1160 | .ops = &clkops_omap2_dflt_wait, | ||
| 1161 | .parent = &func_96m_ck, | ||
| 1162 | .clkdm_name = "core_l4_clkdm", | ||
| 1163 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1164 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
| 1165 | .recalc = &followparent_recalc, | ||
| 1166 | }; | ||
| 1167 | |||
| 1168 | static struct clk mcspi1_ick = { | ||
| 1169 | .name = "mcspi1_ick", | ||
| 1170 | .ops = &clkops_omap2_dflt_wait, | ||
| 1171 | .parent = &l4_ck, | ||
| 1172 | .clkdm_name = "core_l4_clkdm", | ||
| 1173 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1174 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
| 1175 | .recalc = &followparent_recalc, | ||
| 1176 | }; | ||
| 1177 | |||
| 1178 | static struct clk mcspi1_fck = { | ||
| 1179 | .name = "mcspi1_fck", | ||
| 1180 | .ops = &clkops_omap2_dflt_wait, | ||
| 1181 | .parent = &func_48m_ck, | ||
| 1182 | .clkdm_name = "core_l4_clkdm", | ||
| 1183 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1184 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
| 1185 | .recalc = &followparent_recalc, | ||
| 1186 | }; | ||
| 1187 | |||
| 1188 | static struct clk mcspi2_ick = { | ||
| 1189 | .name = "mcspi2_ick", | ||
| 1190 | .ops = &clkops_omap2_dflt_wait, | ||
| 1191 | .parent = &l4_ck, | ||
| 1192 | .clkdm_name = "core_l4_clkdm", | ||
| 1193 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1194 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
| 1195 | .recalc = &followparent_recalc, | ||
| 1196 | }; | ||
| 1197 | |||
| 1198 | static struct clk mcspi2_fck = { | ||
| 1199 | .name = "mcspi2_fck", | ||
| 1200 | .ops = &clkops_omap2_dflt_wait, | ||
| 1201 | .parent = &func_48m_ck, | ||
| 1202 | .clkdm_name = "core_l4_clkdm", | ||
| 1203 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1204 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
| 1205 | .recalc = &followparent_recalc, | ||
| 1206 | }; | ||
| 1207 | |||
| 1208 | static struct clk uart1_ick = { | ||
| 1209 | .name = "uart1_ick", | ||
| 1210 | .ops = &clkops_omap2_dflt_wait, | ||
| 1211 | .parent = &l4_ck, | ||
| 1212 | .clkdm_name = "core_l4_clkdm", | ||
| 1213 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1214 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | ||
| 1215 | .recalc = &followparent_recalc, | ||
| 1216 | }; | ||
| 1217 | |||
| 1218 | static struct clk uart1_fck = { | ||
| 1219 | .name = "uart1_fck", | ||
| 1220 | .ops = &clkops_omap2_dflt_wait, | ||
| 1221 | .parent = &func_48m_ck, | ||
| 1222 | .clkdm_name = "core_l4_clkdm", | ||
| 1223 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1224 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | ||
| 1225 | .recalc = &followparent_recalc, | ||
| 1226 | }; | ||
| 1227 | |||
| 1228 | static struct clk uart2_ick = { | ||
| 1229 | .name = "uart2_ick", | ||
| 1230 | .ops = &clkops_omap2_dflt_wait, | ||
| 1231 | .parent = &l4_ck, | ||
| 1232 | .clkdm_name = "core_l4_clkdm", | ||
| 1233 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1234 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | ||
| 1235 | .recalc = &followparent_recalc, | ||
| 1236 | }; | ||
| 1237 | |||
| 1238 | static struct clk uart2_fck = { | ||
| 1239 | .name = "uart2_fck", | ||
| 1240 | .ops = &clkops_omap2_dflt_wait, | ||
| 1241 | .parent = &func_48m_ck, | ||
| 1242 | .clkdm_name = "core_l4_clkdm", | ||
| 1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1244 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | ||
| 1245 | .recalc = &followparent_recalc, | ||
| 1246 | }; | ||
| 1247 | |||
| 1248 | static struct clk uart3_ick = { | ||
| 1249 | .name = "uart3_ick", | ||
| 1250 | .ops = &clkops_omap2_dflt_wait, | ||
| 1251 | .parent = &l4_ck, | ||
| 1252 | .clkdm_name = "core_l4_clkdm", | ||
| 1253 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1254 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | ||
| 1255 | .recalc = &followparent_recalc, | ||
| 1256 | }; | ||
| 1257 | |||
| 1258 | static struct clk uart3_fck = { | ||
| 1259 | .name = "uart3_fck", | ||
| 1260 | .ops = &clkops_omap2_dflt_wait, | ||
| 1261 | .parent = &func_48m_ck, | ||
| 1262 | .clkdm_name = "core_l4_clkdm", | ||
| 1263 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1264 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | ||
| 1265 | .recalc = &followparent_recalc, | ||
| 1266 | }; | ||
| 1267 | |||
| 1268 | static struct clk gpios_ick = { | ||
| 1269 | .name = "gpios_ick", | ||
| 1270 | .ops = &clkops_omap2_dflt_wait, | ||
| 1271 | .parent = &l4_ck, | ||
| 1272 | .clkdm_name = "core_l4_clkdm", | ||
| 1273 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1274 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 1275 | .recalc = &followparent_recalc, | ||
| 1276 | }; | ||
| 1277 | |||
| 1278 | static struct clk gpios_fck = { | ||
| 1279 | .name = "gpios_fck", | ||
| 1280 | .ops = &clkops_omap2_dflt_wait, | ||
| 1281 | .parent = &func_32k_ck, | ||
| 1282 | .clkdm_name = "wkup_clkdm", | ||
| 1283 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 1284 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 1285 | .recalc = &followparent_recalc, | ||
| 1286 | }; | ||
| 1287 | |||
| 1288 | static struct clk mpu_wdt_ick = { | ||
| 1289 | .name = "mpu_wdt_ick", | ||
| 1290 | .ops = &clkops_omap2_dflt_wait, | ||
| 1291 | .parent = &l4_ck, | ||
| 1292 | .clkdm_name = "core_l4_clkdm", | ||
| 1293 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1294 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | ||
| 1295 | .recalc = &followparent_recalc, | ||
| 1296 | }; | ||
| 1297 | |||
| 1298 | static struct clk mpu_wdt_fck = { | ||
| 1299 | .name = "mpu_wdt_fck", | ||
| 1300 | .ops = &clkops_omap2_dflt_wait, | ||
| 1301 | .parent = &func_32k_ck, | ||
| 1302 | .clkdm_name = "wkup_clkdm", | ||
| 1303 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 1304 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | ||
| 1305 | .recalc = &followparent_recalc, | ||
| 1306 | }; | ||
| 1307 | |||
| 1308 | static struct clk sync_32k_ick = { | ||
| 1309 | .name = "sync_32k_ick", | ||
| 1310 | .ops = &clkops_omap2_dflt_wait, | ||
| 1311 | .parent = &l4_ck, | ||
| 1312 | .flags = ENABLE_ON_INIT, | ||
| 1313 | .clkdm_name = "core_l4_clkdm", | ||
| 1314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1315 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | ||
| 1316 | .recalc = &followparent_recalc, | ||
| 1317 | }; | ||
| 1318 | |||
| 1319 | static struct clk wdt1_ick = { | ||
| 1320 | .name = "wdt1_ick", | ||
| 1321 | .ops = &clkops_omap2_dflt_wait, | ||
| 1322 | .parent = &l4_ck, | ||
| 1323 | .clkdm_name = "core_l4_clkdm", | ||
| 1324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1325 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | ||
| 1326 | .recalc = &followparent_recalc, | ||
| 1327 | }; | ||
| 1328 | |||
| 1329 | static struct clk omapctrl_ick = { | ||
| 1330 | .name = "omapctrl_ick", | ||
| 1331 | .ops = &clkops_omap2_dflt_wait, | ||
| 1332 | .parent = &l4_ck, | ||
| 1333 | .flags = ENABLE_ON_INIT, | ||
| 1334 | .clkdm_name = "core_l4_clkdm", | ||
| 1335 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1336 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | ||
| 1337 | .recalc = &followparent_recalc, | ||
| 1338 | }; | ||
| 1339 | |||
| 1340 | static struct clk cam_ick = { | ||
| 1341 | .name = "cam_ick", | ||
| 1342 | .ops = &clkops_omap2_dflt, | ||
| 1343 | .parent = &l4_ck, | ||
| 1344 | .clkdm_name = "core_l4_clkdm", | ||
| 1345 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1346 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | ||
| 1347 | .recalc = &followparent_recalc, | ||
| 1348 | }; | ||
| 1349 | |||
| 1350 | /* | ||
| 1351 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | ||
| 1352 | * split into two separate clocks, since the parent clocks are different | ||
| 1353 | * and the clockdomains are also different. | ||
| 1354 | */ | ||
| 1355 | static struct clk cam_fck = { | ||
| 1356 | .name = "cam_fck", | ||
| 1357 | .ops = &clkops_omap2_dflt, | ||
| 1358 | .parent = &func_96m_ck, | ||
| 1359 | .clkdm_name = "core_l3_clkdm", | ||
| 1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1361 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | ||
| 1362 | .recalc = &followparent_recalc, | ||
| 1363 | }; | ||
| 1364 | |||
| 1365 | static struct clk mailboxes_ick = { | ||
| 1366 | .name = "mailboxes_ick", | ||
| 1367 | .ops = &clkops_omap2_dflt_wait, | ||
| 1368 | .parent = &l4_ck, | ||
| 1369 | .clkdm_name = "core_l4_clkdm", | ||
| 1370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1371 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | ||
| 1372 | .recalc = &followparent_recalc, | ||
| 1373 | }; | ||
| 1374 | |||
| 1375 | static struct clk wdt4_ick = { | ||
| 1376 | .name = "wdt4_ick", | ||
| 1377 | .ops = &clkops_omap2_dflt_wait, | ||
| 1378 | .parent = &l4_ck, | ||
| 1379 | .clkdm_name = "core_l4_clkdm", | ||
| 1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1381 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | ||
| 1382 | .recalc = &followparent_recalc, | ||
| 1383 | }; | ||
| 1384 | |||
| 1385 | static struct clk wdt4_fck = { | ||
| 1386 | .name = "wdt4_fck", | ||
| 1387 | .ops = &clkops_omap2_dflt_wait, | ||
| 1388 | .parent = &func_32k_ck, | ||
| 1389 | .clkdm_name = "core_l4_clkdm", | ||
| 1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1391 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | ||
| 1392 | .recalc = &followparent_recalc, | ||
| 1393 | }; | ||
| 1394 | |||
| 1395 | static struct clk wdt3_ick = { | ||
| 1396 | .name = "wdt3_ick", | ||
| 1397 | .ops = &clkops_omap2_dflt_wait, | ||
| 1398 | .parent = &l4_ck, | ||
| 1399 | .clkdm_name = "core_l4_clkdm", | ||
| 1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1401 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
| 1402 | .recalc = &followparent_recalc, | ||
| 1403 | }; | ||
| 1404 | |||
| 1405 | static struct clk wdt3_fck = { | ||
| 1406 | .name = "wdt3_fck", | ||
| 1407 | .ops = &clkops_omap2_dflt_wait, | ||
| 1408 | .parent = &func_32k_ck, | ||
| 1409 | .clkdm_name = "core_l4_clkdm", | ||
| 1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1411 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
| 1412 | .recalc = &followparent_recalc, | ||
| 1413 | }; | ||
| 1414 | |||
| 1415 | static struct clk mspro_ick = { | ||
| 1416 | .name = "mspro_ick", | ||
| 1417 | .ops = &clkops_omap2_dflt_wait, | ||
| 1418 | .parent = &l4_ck, | ||
| 1419 | .clkdm_name = "core_l4_clkdm", | ||
| 1420 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1421 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | ||
| 1422 | .recalc = &followparent_recalc, | ||
| 1423 | }; | ||
| 1424 | |||
| 1425 | static struct clk mspro_fck = { | ||
| 1426 | .name = "mspro_fck", | ||
| 1427 | .ops = &clkops_omap2_dflt_wait, | ||
| 1428 | .parent = &func_96m_ck, | ||
| 1429 | .clkdm_name = "core_l4_clkdm", | ||
| 1430 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1431 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | ||
| 1432 | .recalc = &followparent_recalc, | ||
| 1433 | }; | ||
| 1434 | |||
| 1435 | static struct clk mmc_ick = { | ||
| 1436 | .name = "mmc_ick", | ||
| 1437 | .ops = &clkops_omap2_dflt_wait, | ||
| 1438 | .parent = &l4_ck, | ||
| 1439 | .clkdm_name = "core_l4_clkdm", | ||
| 1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1441 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
| 1442 | .recalc = &followparent_recalc, | ||
| 1443 | }; | ||
| 1444 | |||
| 1445 | static struct clk mmc_fck = { | ||
| 1446 | .name = "mmc_fck", | ||
| 1447 | .ops = &clkops_omap2_dflt_wait, | ||
| 1448 | .parent = &func_96m_ck, | ||
| 1449 | .clkdm_name = "core_l4_clkdm", | ||
| 1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1451 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
| 1452 | .recalc = &followparent_recalc, | ||
| 1453 | }; | ||
| 1454 | |||
| 1455 | static struct clk fac_ick = { | ||
| 1456 | .name = "fac_ick", | ||
| 1457 | .ops = &clkops_omap2_dflt_wait, | ||
| 1458 | .parent = &l4_ck, | ||
| 1459 | .clkdm_name = "core_l4_clkdm", | ||
| 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1461 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | ||
| 1462 | .recalc = &followparent_recalc, | ||
| 1463 | }; | ||
| 1464 | |||
| 1465 | static struct clk fac_fck = { | ||
| 1466 | .name = "fac_fck", | ||
| 1467 | .ops = &clkops_omap2_dflt_wait, | ||
| 1468 | .parent = &func_12m_ck, | ||
| 1469 | .clkdm_name = "core_l4_clkdm", | ||
| 1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1471 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | ||
| 1472 | .recalc = &followparent_recalc, | ||
| 1473 | }; | ||
| 1474 | |||
| 1475 | static struct clk eac_ick = { | ||
| 1476 | .name = "eac_ick", | ||
| 1477 | .ops = &clkops_omap2_dflt_wait, | ||
| 1478 | .parent = &l4_ck, | ||
| 1479 | .clkdm_name = "core_l4_clkdm", | ||
| 1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1481 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
| 1482 | .recalc = &followparent_recalc, | ||
| 1483 | }; | ||
| 1484 | |||
| 1485 | static struct clk eac_fck = { | ||
| 1486 | .name = "eac_fck", | ||
| 1487 | .ops = &clkops_omap2_dflt_wait, | ||
| 1488 | .parent = &func_96m_ck, | ||
| 1489 | .clkdm_name = "core_l4_clkdm", | ||
| 1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1491 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
| 1492 | .recalc = &followparent_recalc, | ||
| 1493 | }; | ||
| 1494 | |||
| 1495 | static struct clk hdq_ick = { | ||
| 1496 | .name = "hdq_ick", | ||
| 1497 | .ops = &clkops_omap2_dflt_wait, | ||
| 1498 | .parent = &l4_ck, | ||
| 1499 | .clkdm_name = "core_l4_clkdm", | ||
| 1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1501 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | ||
| 1502 | .recalc = &followparent_recalc, | ||
| 1503 | }; | ||
| 1504 | |||
| 1505 | static struct clk hdq_fck = { | ||
| 1506 | .name = "hdq_fck", | ||
| 1507 | .ops = &clkops_omap2_dflt_wait, | ||
| 1508 | .parent = &func_12m_ck, | ||
| 1509 | .clkdm_name = "core_l4_clkdm", | ||
| 1510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1511 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | ||
| 1512 | .recalc = &followparent_recalc, | ||
| 1513 | }; | ||
| 1514 | |||
| 1515 | static struct clk i2c2_ick = { | ||
| 1516 | .name = "i2c2_ick", | ||
| 1517 | .ops = &clkops_omap2_dflt_wait, | ||
| 1518 | .parent = &l4_ck, | ||
| 1519 | .clkdm_name = "core_l4_clkdm", | ||
| 1520 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1521 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
| 1522 | .recalc = &followparent_recalc, | ||
| 1523 | }; | ||
| 1524 | |||
| 1525 | static struct clk i2c2_fck = { | ||
| 1526 | .name = "i2c2_fck", | ||
| 1527 | .ops = &clkops_omap2_dflt_wait, | ||
| 1528 | .parent = &func_12m_ck, | ||
| 1529 | .clkdm_name = "core_l4_clkdm", | ||
| 1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1531 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
| 1532 | .recalc = &followparent_recalc, | ||
| 1533 | }; | ||
| 1534 | |||
| 1535 | static struct clk i2c1_ick = { | ||
| 1536 | .name = "i2c1_ick", | ||
| 1537 | .ops = &clkops_omap2_dflt_wait, | ||
| 1538 | .parent = &l4_ck, | ||
| 1539 | .clkdm_name = "core_l4_clkdm", | ||
| 1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1541 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
| 1542 | .recalc = &followparent_recalc, | ||
| 1543 | }; | ||
| 1544 | |||
| 1545 | static struct clk i2c1_fck = { | ||
| 1546 | .name = "i2c1_fck", | ||
| 1547 | .ops = &clkops_omap2_dflt_wait, | ||
| 1548 | .parent = &func_12m_ck, | ||
| 1549 | .clkdm_name = "core_l4_clkdm", | ||
| 1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1551 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
| 1552 | .recalc = &followparent_recalc, | ||
| 1553 | }; | ||
| 1554 | |||
| 1555 | static struct clk gpmc_fck = { | ||
| 1556 | .name = "gpmc_fck", | ||
| 1557 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 1558 | .parent = &core_l3_ck, | ||
| 1559 | .flags = ENABLE_ON_INIT, | ||
| 1560 | .clkdm_name = "core_l3_clkdm", | ||
| 1561 | .recalc = &followparent_recalc, | ||
| 1562 | }; | ||
| 1563 | |||
| 1564 | static struct clk sdma_fck = { | ||
| 1565 | .name = "sdma_fck", | ||
| 1566 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 1567 | .parent = &core_l3_ck, | ||
| 1568 | .clkdm_name = "core_l3_clkdm", | ||
| 1569 | .recalc = &followparent_recalc, | ||
| 1570 | }; | ||
| 1571 | |||
| 1572 | static struct clk sdma_ick = { | ||
| 1573 | .name = "sdma_ick", | ||
| 1574 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 1575 | .parent = &l4_ck, | ||
| 1576 | .clkdm_name = "core_l3_clkdm", | ||
| 1577 | .recalc = &followparent_recalc, | ||
| 1578 | }; | ||
| 1579 | |||
| 1580 | static struct clk vlynq_ick = { | ||
| 1581 | .name = "vlynq_ick", | ||
| 1582 | .ops = &clkops_omap2_dflt_wait, | ||
| 1583 | .parent = &core_l3_ck, | ||
| 1584 | .clkdm_name = "core_l3_clkdm", | ||
| 1585 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1586 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
| 1587 | .recalc = &followparent_recalc, | ||
| 1588 | }; | ||
| 1589 | |||
| 1590 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | ||
| 1591 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
| 1592 | { .div = 0 } | ||
| 1593 | }; | ||
| 1594 | |||
| 1595 | static const struct clksel_rate vlynq_fck_core_rates[] = { | ||
| 1596 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | ||
| 1597 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
| 1598 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | ||
| 1599 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
| 1600 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 1601 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 1602 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | ||
| 1603 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 1604 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
| 1605 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, | ||
| 1606 | { .div = 0 } | ||
| 1607 | }; | ||
| 1608 | |||
| 1609 | static const struct clksel vlynq_fck_clksel[] = { | ||
| 1610 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | ||
| 1611 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | ||
| 1612 | { .parent = NULL } | ||
| 1613 | }; | ||
| 1614 | |||
| 1615 | static struct clk vlynq_fck = { | ||
| 1616 | .name = "vlynq_fck", | ||
| 1617 | .ops = &clkops_omap2_dflt_wait, | ||
| 1618 | .parent = &func_96m_ck, | ||
| 1619 | .clkdm_name = "core_l3_clkdm", | ||
| 1620 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1621 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
| 1622 | .init = &omap2_init_clksel_parent, | ||
| 1623 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1624 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | ||
| 1625 | .clksel = vlynq_fck_clksel, | ||
| 1626 | .recalc = &omap2_clksel_recalc, | ||
| 1627 | }; | ||
| 1628 | |||
| 1629 | static struct clk des_ick = { | ||
| 1630 | .name = "des_ick", | ||
| 1631 | .ops = &clkops_omap2_dflt_wait, | ||
| 1632 | .parent = &l4_ck, | ||
| 1633 | .clkdm_name = "core_l4_clkdm", | ||
| 1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 1635 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | ||
| 1636 | .recalc = &followparent_recalc, | ||
| 1637 | }; | ||
| 1638 | |||
| 1639 | static struct clk sha_ick = { | ||
| 1640 | .name = "sha_ick", | ||
| 1641 | .ops = &clkops_omap2_dflt_wait, | ||
| 1642 | .parent = &l4_ck, | ||
| 1643 | .clkdm_name = "core_l4_clkdm", | ||
| 1644 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 1645 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | ||
| 1646 | .recalc = &followparent_recalc, | ||
| 1647 | }; | ||
| 1648 | |||
| 1649 | static struct clk rng_ick = { | ||
| 1650 | .name = "rng_ick", | ||
| 1651 | .ops = &clkops_omap2_dflt_wait, | ||
| 1652 | .parent = &l4_ck, | ||
| 1653 | .clkdm_name = "core_l4_clkdm", | ||
| 1654 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 1655 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | ||
| 1656 | .recalc = &followparent_recalc, | ||
| 1657 | }; | ||
| 1658 | |||
| 1659 | static struct clk aes_ick = { | ||
| 1660 | .name = "aes_ick", | ||
| 1661 | .ops = &clkops_omap2_dflt_wait, | ||
| 1662 | .parent = &l4_ck, | ||
| 1663 | .clkdm_name = "core_l4_clkdm", | ||
| 1664 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 1665 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | ||
| 1666 | .recalc = &followparent_recalc, | ||
| 1667 | }; | ||
| 1668 | |||
| 1669 | static struct clk pka_ick = { | ||
| 1670 | .name = "pka_ick", | ||
| 1671 | .ops = &clkops_omap2_dflt_wait, | ||
| 1672 | .parent = &l4_ck, | ||
| 1673 | .clkdm_name = "core_l4_clkdm", | ||
| 1674 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 1675 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | ||
| 1676 | .recalc = &followparent_recalc, | ||
| 1677 | }; | ||
| 1678 | |||
| 1679 | static struct clk usb_fck = { | ||
| 1680 | .name = "usb_fck", | ||
| 1681 | .ops = &clkops_omap2_dflt_wait, | ||
| 1682 | .parent = &func_48m_ck, | ||
| 1683 | .clkdm_name = "core_l3_clkdm", | ||
| 1684 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1685 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | ||
| 1686 | .recalc = &followparent_recalc, | ||
| 1687 | }; | ||
| 1688 | |||
| 1689 | /* | ||
| 1690 | * This clock is a composite clock which does entire set changes then | ||
| 1691 | * forces a rebalance. It keys on the MPU speed, but it really could | ||
| 1692 | * be any key speed part of a set in the rate table. | ||
| 1693 | * | ||
| 1694 | * to really change a set, you need memory table sets which get changed | ||
| 1695 | * in sram, pre-notifiers & post notifiers, changing the top set, without | ||
| 1696 | * having low level display recalc's won't work... this is why dpm notifiers | ||
| 1697 | * work, isr's off, walk a list of clocks already _off_ and not messing with | ||
| 1698 | * the bus. | ||
| 1699 | * | ||
| 1700 | * This clock should have no parent. It embodies the entire upper level | ||
| 1701 | * active set. A parent will mess up some of the init also. | ||
| 1702 | */ | ||
| 1703 | static struct clk virt_prcm_set = { | ||
| 1704 | .name = "virt_prcm_set", | ||
| 1705 | .ops = &clkops_null, | ||
| 1706 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | ||
| 1707 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | ||
| 1708 | .set_rate = &omap2_select_table_rate, | ||
| 1709 | .round_rate = &omap2_round_to_table_rate, | ||
| 1710 | }; | ||
| 1711 | |||
| 1712 | |||
| 1713 | /* | ||
| 1714 | * clkdev integration | ||
| 1715 | */ | ||
| 1716 | |||
| 1717 | static struct omap_clk omap2420_clks[] = { | ||
| 1718 | /* external root sources */ | ||
| 1719 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), | ||
| 1720 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), | ||
| 1721 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | ||
| 1722 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | ||
| 1723 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | ||
| 1724 | /* internal analog sources */ | ||
| 1725 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), | ||
| 1726 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), | ||
| 1727 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), | ||
| 1728 | /* internal prcm root sources */ | ||
| 1729 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), | ||
| 1730 | CLK(NULL, "core_ck", &core_ck, CK_242X), | ||
| 1731 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | ||
| 1732 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | ||
| 1733 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | ||
| 1734 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), | ||
| 1735 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), | ||
| 1736 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), | ||
| 1737 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | ||
| 1738 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
| 1739 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
| 1740 | /* mpu domain clocks */ | ||
| 1741 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), | ||
| 1742 | /* dsp domain clocks */ | ||
| 1743 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), | ||
| 1744 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X), | ||
| 1745 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
| 1746 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
| 1747 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
| 1748 | /* GFX domain clocks */ | ||
| 1749 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), | ||
| 1750 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), | ||
| 1751 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), | ||
| 1752 | /* DSS domain clocks */ | ||
| 1753 | CLK("omapdss", "ick", &dss_ick, CK_242X), | ||
| 1754 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), | ||
| 1755 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), | ||
| 1756 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), | ||
| 1757 | /* L3 domain clocks */ | ||
| 1758 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), | ||
| 1759 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), | ||
| 1760 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), | ||
| 1761 | /* L4 domain clocks */ | ||
| 1762 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), | ||
| 1763 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), | ||
| 1764 | /* virtual meta-group clock */ | ||
| 1765 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), | ||
| 1766 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 1767 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), | ||
| 1768 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), | ||
| 1769 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), | ||
| 1770 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), | ||
| 1771 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), | ||
| 1772 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), | ||
| 1773 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), | ||
| 1774 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), | ||
| 1775 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), | ||
| 1776 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), | ||
| 1777 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), | ||
| 1778 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), | ||
| 1779 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), | ||
| 1780 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), | ||
| 1781 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), | ||
| 1782 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), | ||
| 1783 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), | ||
| 1784 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), | ||
| 1785 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), | ||
| 1786 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), | ||
| 1787 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), | ||
| 1788 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), | ||
| 1789 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), | ||
| 1790 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), | ||
| 1791 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), | ||
| 1792 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), | ||
| 1793 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), | ||
| 1794 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), | ||
| 1795 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), | ||
| 1796 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), | ||
| 1797 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), | ||
| 1798 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), | ||
| 1799 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), | ||
| 1800 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), | ||
| 1801 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), | ||
| 1802 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), | ||
| 1803 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), | ||
| 1804 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), | ||
| 1805 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), | ||
| 1806 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), | ||
| 1807 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), | ||
| 1808 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), | ||
| 1809 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), | ||
| 1810 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), | ||
| 1811 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), | ||
| 1812 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), | ||
| 1813 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), | ||
| 1814 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), | ||
| 1815 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), | ||
| 1816 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), | ||
| 1817 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | ||
| 1818 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | ||
| 1819 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), | ||
| 1820 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), | ||
| 1821 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | ||
| 1822 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | ||
| 1823 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), | ||
| 1824 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), | ||
| 1825 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
| 1826 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
| 1827 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), | ||
| 1828 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), | ||
| 1829 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), | ||
| 1830 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
| 1831 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), | ||
| 1832 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
| 1833 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), | ||
| 1834 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), | ||
| 1835 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), | ||
| 1836 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
| 1837 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
| 1838 | CLK(NULL, "des_ick", &des_ick, CK_242X), | ||
| 1839 | CLK(NULL, "sha_ick", &sha_ick, CK_242X), | ||
| 1840 | CLK("omap_rng", "ick", &rng_ick, CK_242X), | ||
| 1841 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), | ||
| 1842 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), | ||
| 1843 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), | ||
| 1844 | }; | ||
| 1845 | |||
| 1846 | /* | ||
| 1847 | * init code | ||
| 1848 | */ | ||
| 1849 | |||
| 1850 | int __init omap2420_clk_init(void) | ||
| 1851 | { | ||
| 1852 | const struct prcm_config *prcm; | ||
| 1853 | struct omap_clk *c; | ||
| 1854 | u32 clkrate; | ||
| 1855 | |||
| 1856 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | ||
| 1857 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); | ||
| 1858 | cpu_mask = RATE_IN_242X; | ||
| 1859 | rate_table = omap2420_rate_table; | ||
| 1860 | |||
| 1861 | clk_init(&omap2_clk_functions); | ||
| 1862 | |||
| 1863 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); | ||
| 1864 | c++) | ||
| 1865 | clk_preinit(c->lk.clk); | ||
| 1866 | |||
| 1867 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | ||
| 1868 | propagate_rate(&osc_ck); | ||
| 1869 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); | ||
| 1870 | propagate_rate(&sys_ck); | ||
| 1871 | |||
| 1872 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); | ||
| 1873 | c++) { | ||
| 1874 | clkdev_add(&c->lk); | ||
| 1875 | clk_register(c->lk.clk); | ||
| 1876 | omap2_init_clk_clkdm(c->lk.clk); | ||
| 1877 | } | ||
| 1878 | |||
| 1879 | /* Check the MPU rate set by bootloader */ | ||
| 1880 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | ||
| 1881 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 1882 | if (!(prcm->flags & cpu_mask)) | ||
| 1883 | continue; | ||
| 1884 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 1885 | continue; | ||
| 1886 | if (prcm->dpll_speed <= clkrate) | ||
| 1887 | break; | ||
| 1888 | } | ||
| 1889 | curr_prcm_set = prcm; | ||
| 1890 | |||
| 1891 | recalculate_root_clocks(); | ||
| 1892 | |||
| 1893 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", | ||
| 1894 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
| 1895 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
| 1896 | |||
| 1897 | /* | ||
| 1898 | * Only enable those clocks we will need, let the drivers | ||
| 1899 | * enable other clocks as necessary | ||
| 1900 | */ | ||
| 1901 | clk_enable_init_clocks(); | ||
| 1902 | |||
| 1903 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | ||
| 1904 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
| 1905 | sclk = clk_get(NULL, "sys_ck"); | ||
| 1906 | dclk = clk_get(NULL, "dpll_ck"); | ||
| 1907 | |||
| 1908 | return 0; | ||
| 1909 | } | ||
| 1910 | |||
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c new file mode 100644 index 000000000000..44d0cccc51a9 --- /dev/null +++ b/arch/arm/mach-omap2/clock2430.c | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * clock2430.c - OMAP2430-specific clock integration code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | #undef DEBUG | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | |||
| 26 | #include "clock.h" | ||
| 27 | #include "clock2xxx.h" | ||
| 28 | #include "cm.h" | ||
| 29 | #include "cm-regbits-24xx.h" | ||
| 30 | |||
| 31 | /** | ||
| 32 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | ||
| 33 | * @clk: struct clk * being enabled | ||
| 34 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
| 35 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
| 36 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
| 37 | * | ||
| 38 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | ||
| 39 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | ||
| 40 | * passes back the correct CM_IDLEST register address for I2CHS | ||
| 41 | * modules. No return value. | ||
| 42 | */ | ||
| 43 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
| 44 | void __iomem **idlest_reg, | ||
| 45 | u8 *idlest_bit, | ||
| 46 | u8 *idlest_val) | ||
| 47 | { | ||
| 48 | *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST); | ||
| 49 | *idlest_bit = clk->enable_bit; | ||
| 50 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | ||
| 51 | } | ||
| 52 | |||
| 53 | /* 2430 I2CHS has non-standard IDLEST register */ | ||
| 54 | const struct clkops clkops_omap2430_i2chs_wait = { | ||
| 55 | .enable = omap2_dflt_clk_enable, | ||
| 56 | .disable = omap2_dflt_clk_disable, | ||
| 57 | .find_idlest = omap2430_clk_i2chs_find_idlest, | ||
| 58 | .find_companion = omap2_clk_dflt_find_companion, | ||
| 59 | }; | ||
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2430_data.c index 97dc7cf7751d..0438b6e4f51a 100644 --- a/arch/arm/mach-omap2/clock2xxx_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock2xxx_data.c | 2 | * linux/arch/arm/mach-omap2/clock2430_data.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2009 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Contacts: | 7 | * Contacts: |
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| @@ -13,9 +13,9 @@ | |||
| 13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
| 18 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/list.h> | ||
| 19 | 19 | ||
| 20 | #include <plat/clkdev_omap.h> | 20 | #include <plat/clkdev_omap.h> |
| 21 | 21 | ||
| @@ -28,8 +28,10 @@ | |||
| 28 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "sdrc.h" | 29 | #include "sdrc.h" |
| 30 | 30 | ||
| 31 | /*------------------------------------------------------------------------- | 31 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR |
| 32 | * 24xx clock tree. | 32 | |
| 33 | /* | ||
| 34 | * 2430 clock tree. | ||
| 33 | * | 35 | * |
| 34 | * NOTE:In many cases here we are assigning a 'default' parent. In many | 36 | * NOTE:In many cases here we are assigning a 'default' parent. In many |
| 35 | * cases the parent is selectable. The get/set parent calls will also | 37 | * cases the parent is selectable. The get/set parent calls will also |
| @@ -46,14 +48,13 @@ | |||
| 46 | * domains. Many get their interface clocks from the L4 domain, but get | 48 | * domains. Many get their interface clocks from the L4 domain, but get |
| 47 | * functional clocks from fixed sources or other core domain derived | 49 | * functional clocks from fixed sources or other core domain derived |
| 48 | * clocks. | 50 | * clocks. |
| 49 | *-------------------------------------------------------------------------*/ | 51 | */ |
| 50 | 52 | ||
| 51 | /* Base external input clocks */ | 53 | /* Base external input clocks */ |
| 52 | static struct clk func_32k_ck = { | 54 | static struct clk func_32k_ck = { |
| 53 | .name = "func_32k_ck", | 55 | .name = "func_32k_ck", |
| 54 | .ops = &clkops_null, | 56 | .ops = &clkops_null, |
| 55 | .rate = 32000, | 57 | .rate = 32000, |
| 56 | .flags = RATE_FIXED, | ||
| 57 | .clkdm_name = "wkup_clkdm", | 58 | .clkdm_name = "wkup_clkdm", |
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| @@ -61,7 +62,6 @@ static struct clk secure_32k_ck = { | |||
| 61 | .name = "secure_32k_ck", | 62 | .name = "secure_32k_ck", |
| 62 | .ops = &clkops_null, | 63 | .ops = &clkops_null, |
| 63 | .rate = 32768, | 64 | .rate = 32768, |
| 64 | .flags = RATE_FIXED, | ||
| 65 | .clkdm_name = "wkup_clkdm", | 65 | .clkdm_name = "wkup_clkdm", |
| 66 | }; | 66 | }; |
| 67 | 67 | ||
| @@ -79,14 +79,13 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | |||
| 79 | .ops = &clkops_null, | 79 | .ops = &clkops_null, |
| 80 | .parent = &osc_ck, | 80 | .parent = &osc_ck, |
| 81 | .clkdm_name = "wkup_clkdm", | 81 | .clkdm_name = "wkup_clkdm", |
| 82 | .recalc = &omap2_sys_clk_recalc, | 82 | .recalc = &omap2xxx_sys_clk_recalc, |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | 85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 86 | .name = "alt_ck", | 86 | .name = "alt_ck", |
| 87 | .ops = &clkops_null, | 87 | .ops = &clkops_null, |
| 88 | .rate = 54000000, | 88 | .rate = 54000000, |
| 89 | .flags = RATE_FIXED, | ||
| 90 | .clkdm_name = "wkup_clkdm", | 89 | .clkdm_name = "wkup_clkdm", |
| 91 | }; | 90 | }; |
| 92 | 91 | ||
| @@ -107,7 +106,7 @@ static struct dpll_data dpll_dd = { | |||
| 107 | .clk_ref = &sys_ck, | 106 | .clk_ref = &sys_ck, |
| 108 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 109 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | 108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, |
| 110 | .max_multiplier = 1024, | 109 | .max_multiplier = 1023, |
| 111 | .min_divider = 1, | 110 | .min_divider = 1, |
| 112 | .max_divider = 16, | 111 | .max_divider = 16, |
| 113 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| @@ -132,7 +131,7 @@ static struct clk apll96_ck = { | |||
| 132 | .ops = &clkops_apll96, | 131 | .ops = &clkops_apll96, |
| 133 | .parent = &sys_ck, | 132 | .parent = &sys_ck, |
| 134 | .rate = 96000000, | 133 | .rate = 96000000, |
| 135 | .flags = RATE_FIXED | ENABLE_ON_INIT, | 134 | .flags = ENABLE_ON_INIT, |
| 136 | .clkdm_name = "wkup_clkdm", | 135 | .clkdm_name = "wkup_clkdm", |
| 137 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 138 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | 137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
| @@ -143,7 +142,7 @@ static struct clk apll54_ck = { | |||
| 143 | .ops = &clkops_apll54, | 142 | .ops = &clkops_apll54, |
| 144 | .parent = &sys_ck, | 143 | .parent = &sys_ck, |
| 145 | .rate = 54000000, | 144 | .rate = 54000000, |
| 146 | .flags = RATE_FIXED | ENABLE_ON_INIT, | 145 | .flags = ENABLE_ON_INIT, |
| 147 | .clkdm_name = "wkup_clkdm", | 146 | .clkdm_name = "wkup_clkdm", |
| 148 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 149 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | 148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
| @@ -208,7 +207,6 @@ static const struct clksel func_96m_clksel[] = { | |||
| 208 | { .parent = NULL } | 207 | { .parent = NULL } |
| 209 | }; | 208 | }; |
| 210 | 209 | ||
| 211 | /* The parent of this clock is not selectable on 2420. */ | ||
| 212 | static struct clk func_96m_ck = { | 210 | static struct clk func_96m_ck = { |
| 213 | .name = "func_96m_ck", | 211 | .name = "func_96m_ck", |
| 214 | .ops = &clkops_null, | 212 | .ops = &clkops_null, |
| @@ -219,8 +217,6 @@ static struct clk func_96m_ck = { | |||
| 219 | .clksel_mask = OMAP2430_96M_SOURCE, | 217 | .clksel_mask = OMAP2430_96M_SOURCE, |
| 220 | .clksel = func_96m_clksel, | 218 | .clksel = func_96m_clksel, |
| 221 | .recalc = &omap2_clksel_recalc, | 219 | .recalc = &omap2_clksel_recalc, |
| 222 | .round_rate = &omap2_clksel_round_rate, | ||
| 223 | .set_rate = &omap2_clksel_set_rate | ||
| 224 | }; | 220 | }; |
| 225 | 221 | ||
| 226 | /* func_48m_ck */ | 222 | /* func_48m_ck */ |
| @@ -261,7 +257,7 @@ static struct clk func_12m_ck = { | |||
| 261 | .parent = &func_48m_ck, | 257 | .parent = &func_48m_ck, |
| 262 | .fixed_div = 4, | 258 | .fixed_div = 4, |
| 263 | .clkdm_name = "wkup_clkdm", | 259 | .clkdm_name = "wkup_clkdm", |
| 264 | .recalc = &omap2_fixed_divisor_recalc, | 260 | .recalc = &omap_fixed_divisor_recalc, |
| 265 | }; | 261 | }; |
| 266 | 262 | ||
| 267 | /* Secure timer, only available in secure mode */ | 263 | /* Secure timer, only available in secure mode */ |
| @@ -313,10 +309,10 @@ static struct clk sys_clkout_src = { | |||
| 313 | .ops = &clkops_omap2_dflt, | 309 | .ops = &clkops_omap2_dflt, |
| 314 | .parent = &func_54m_ck, | 310 | .parent = &func_54m_ck, |
| 315 | .clkdm_name = "wkup_clkdm", | 311 | .clkdm_name = "wkup_clkdm", |
| 316 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 312 | .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
| 317 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | 313 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| 318 | .init = &omap2_init_clksel_parent, | 314 | .init = &omap2_init_clksel_parent, |
| 319 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 315 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
| 320 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, | 316 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
| 321 | .clksel = common_clkout_src_clksel, | 317 | .clksel = common_clkout_src_clksel, |
| 322 | .recalc = &omap2_clksel_recalc, | 318 | .recalc = &omap2_clksel_recalc, |
| @@ -343,7 +339,7 @@ static struct clk sys_clkout = { | |||
| 343 | .ops = &clkops_null, | 339 | .ops = &clkops_null, |
| 344 | .parent = &sys_clkout_src, | 340 | .parent = &sys_clkout_src, |
| 345 | .clkdm_name = "wkup_clkdm", | 341 | .clkdm_name = "wkup_clkdm", |
| 346 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 342 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
| 347 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | 343 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| 348 | .clksel = sys_clkout_clksel, | 344 | .clksel = sys_clkout_clksel, |
| 349 | .recalc = &omap2_clksel_recalc, | 345 | .recalc = &omap2_clksel_recalc, |
| @@ -351,48 +347,12 @@ static struct clk sys_clkout = { | |||
| 351 | .set_rate = &omap2_clksel_set_rate | 347 | .set_rate = &omap2_clksel_set_rate |
| 352 | }; | 348 | }; |
| 353 | 349 | ||
| 354 | /* In 2430, new in 2420 ES2 */ | ||
| 355 | static struct clk sys_clkout2_src = { | ||
| 356 | .name = "sys_clkout2_src", | ||
| 357 | .ops = &clkops_omap2_dflt, | ||
| 358 | .parent = &func_54m_ck, | ||
| 359 | .clkdm_name = "wkup_clkdm", | ||
| 360 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 361 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | ||
| 362 | .init = &omap2_init_clksel_parent, | ||
| 363 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 364 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, | ||
| 365 | .clksel = common_clkout_src_clksel, | ||
| 366 | .recalc = &omap2_clksel_recalc, | ||
| 367 | .round_rate = &omap2_clksel_round_rate, | ||
| 368 | .set_rate = &omap2_clksel_set_rate | ||
| 369 | }; | ||
| 370 | |||
| 371 | static const struct clksel sys_clkout2_clksel[] = { | ||
| 372 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | ||
| 373 | { .parent = NULL } | ||
| 374 | }; | ||
| 375 | |||
| 376 | /* In 2430, new in 2420 ES2 */ | ||
| 377 | static struct clk sys_clkout2 = { | ||
| 378 | .name = "sys_clkout2", | ||
| 379 | .ops = &clkops_null, | ||
| 380 | .parent = &sys_clkout2_src, | ||
| 381 | .clkdm_name = "wkup_clkdm", | ||
| 382 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 383 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | ||
| 384 | .clksel = sys_clkout2_clksel, | ||
| 385 | .recalc = &omap2_clksel_recalc, | ||
| 386 | .round_rate = &omap2_clksel_round_rate, | ||
| 387 | .set_rate = &omap2_clksel_set_rate | ||
| 388 | }; | ||
| 389 | |||
| 390 | static struct clk emul_ck = { | 350 | static struct clk emul_ck = { |
| 391 | .name = "emul_ck", | 351 | .name = "emul_ck", |
| 392 | .ops = &clkops_omap2_dflt, | 352 | .ops = &clkops_omap2_dflt, |
| 393 | .parent = &func_54m_ck, | 353 | .parent = &func_54m_ck, |
| 394 | .clkdm_name = "wkup_clkdm", | 354 | .clkdm_name = "wkup_clkdm", |
| 395 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, | 355 | .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, |
| 396 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | 356 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| 397 | .recalc = &followparent_recalc, | 357 | .recalc = &followparent_recalc, |
| 398 | 358 | ||
| @@ -411,9 +371,6 @@ static struct clk emul_ck = { | |||
| 411 | static const struct clksel_rate mpu_core_rates[] = { | 371 | static const struct clksel_rate mpu_core_rates[] = { |
| 412 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | 372 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 413 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | 373 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 414 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
| 415 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 416 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 417 | { .div = 0 }, | 374 | { .div = 0 }, |
| 418 | }; | 375 | }; |
| 419 | 376 | ||
| @@ -426,22 +383,18 @@ static struct clk mpu_ck = { /* Control cpu */ | |||
| 426 | .name = "mpu_ck", | 383 | .name = "mpu_ck", |
| 427 | .ops = &clkops_null, | 384 | .ops = &clkops_null, |
| 428 | .parent = &core_ck, | 385 | .parent = &core_ck, |
| 429 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 430 | .clkdm_name = "mpu_clkdm", | 386 | .clkdm_name = "mpu_clkdm", |
| 431 | .init = &omap2_init_clksel_parent, | 387 | .init = &omap2_init_clksel_parent, |
| 432 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 388 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| 433 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | 389 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
| 434 | .clksel = mpu_clksel, | 390 | .clksel = mpu_clksel, |
| 435 | .recalc = &omap2_clksel_recalc, | 391 | .recalc = &omap2_clksel_recalc, |
| 436 | .round_rate = &omap2_clksel_round_rate, | ||
| 437 | .set_rate = &omap2_clksel_set_rate | ||
| 438 | }; | 392 | }; |
| 439 | 393 | ||
| 440 | /* | 394 | /* |
| 441 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain | 395 | * DSP (2430-IVA2.1) clock domain |
| 442 | * Clocks: | 396 | * Clocks: |
| 443 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK | 397 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
| 444 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP | ||
| 445 | * | 398 | * |
| 446 | * Won't be too specific here. The core clock comes into this block | 399 | * Won't be too specific here. The core clock comes into this block |
| 447 | * it is divided then tee'ed. One branch goes directly to xyz enable | 400 | * it is divided then tee'ed. One branch goes directly to xyz enable |
| @@ -453,9 +406,6 @@ static const struct clksel_rate dsp_fck_core_rates[] = { | |||
| 453 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | 406 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 454 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | 407 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 455 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | 408 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 456 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 457 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 458 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 459 | { .div = 0 }, | 409 | { .div = 0 }, |
| 460 | }; | 410 | }; |
| 461 | 411 | ||
| @@ -468,7 +418,6 @@ static struct clk dsp_fck = { | |||
| 468 | .name = "dsp_fck", | 418 | .name = "dsp_fck", |
| 469 | .ops = &clkops_omap2_dflt_wait, | 419 | .ops = &clkops_omap2_dflt_wait, |
| 470 | .parent = &core_ck, | 420 | .parent = &core_ck, |
| 471 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 472 | .clkdm_name = "dsp_clkdm", | 421 | .clkdm_name = "dsp_clkdm", |
| 473 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 422 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 474 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 423 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| @@ -476,8 +425,6 @@ static struct clk dsp_fck = { | |||
| 476 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | 425 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, |
| 477 | .clksel = dsp_fck_clksel, | 426 | .clksel = dsp_fck_clksel, |
| 478 | .recalc = &omap2_clksel_recalc, | 427 | .recalc = &omap2_clksel_recalc, |
| 479 | .round_rate = &omap2_clksel_round_rate, | ||
| 480 | .set_rate = &omap2_clksel_set_rate | ||
| 481 | }; | 428 | }; |
| 482 | 429 | ||
| 483 | /* DSP interface clock */ | 430 | /* DSP interface clock */ |
| @@ -498,23 +445,10 @@ static struct clk dsp_irate_ick = { | |||
| 498 | .name = "dsp_irate_ick", | 445 | .name = "dsp_irate_ick", |
| 499 | .ops = &clkops_null, | 446 | .ops = &clkops_null, |
| 500 | .parent = &dsp_fck, | 447 | .parent = &dsp_fck, |
| 501 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 502 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 448 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 503 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | 449 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 504 | .clksel = dsp_irate_ick_clksel, | 450 | .clksel = dsp_irate_ick_clksel, |
| 505 | .recalc = &omap2_clksel_recalc, | 451 | .recalc = &omap2_clksel_recalc, |
| 506 | .round_rate = &omap2_clksel_round_rate, | ||
| 507 | .set_rate = &omap2_clksel_set_rate | ||
| 508 | }; | ||
| 509 | |||
| 510 | /* 2420 only */ | ||
| 511 | static struct clk dsp_ick = { | ||
| 512 | .name = "dsp_ick", /* apparently ipi and isp */ | ||
| 513 | .ops = &clkops_omap2_dflt_wait, | ||
| 514 | .parent = &dsp_irate_ick, | ||
| 515 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 516 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | ||
| 517 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | ||
| 518 | }; | 452 | }; |
| 519 | 453 | ||
| 520 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ | 454 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
| @@ -522,45 +456,11 @@ static struct clk iva2_1_ick = { | |||
| 522 | .name = "iva2_1_ick", | 456 | .name = "iva2_1_ick", |
| 523 | .ops = &clkops_omap2_dflt_wait, | 457 | .ops = &clkops_omap2_dflt_wait, |
| 524 | .parent = &dsp_irate_ick, | 458 | .parent = &dsp_irate_ick, |
| 525 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 526 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 459 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 527 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 460 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 528 | }; | 461 | }; |
| 529 | 462 | ||
| 530 | /* | 463 | /* |
| 531 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | ||
| 532 | * the C54x, but which is contained in the DSP powerdomain. Does not | ||
| 533 | * exist on later OMAPs. | ||
| 534 | */ | ||
| 535 | static struct clk iva1_ifck = { | ||
| 536 | .name = "iva1_ifck", | ||
| 537 | .ops = &clkops_omap2_dflt_wait, | ||
| 538 | .parent = &core_ck, | ||
| 539 | .flags = CONFIG_PARTICIPANT | DELAYED_APP, | ||
| 540 | .clkdm_name = "iva1_clkdm", | ||
| 541 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 542 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | ||
| 543 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 544 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | ||
| 545 | .clksel = dsp_fck_clksel, | ||
| 546 | .recalc = &omap2_clksel_recalc, | ||
| 547 | .round_rate = &omap2_clksel_round_rate, | ||
| 548 | .set_rate = &omap2_clksel_set_rate | ||
| 549 | }; | ||
| 550 | |||
| 551 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | ||
| 552 | static struct clk iva1_mpu_int_ifck = { | ||
| 553 | .name = "iva1_mpu_int_ifck", | ||
| 554 | .ops = &clkops_omap2_dflt_wait, | ||
| 555 | .parent = &iva1_ifck, | ||
| 556 | .clkdm_name = "iva1_clkdm", | ||
| 557 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 558 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | ||
| 559 | .fixed_div = 2, | ||
| 560 | .recalc = &omap2_fixed_divisor_recalc, | ||
| 561 | }; | ||
| 562 | |||
| 563 | /* | ||
| 564 | * L3 clock domain | 464 | * L3 clock domain |
| 565 | * L3 clocks are used for both interface and functional clocks to | 465 | * L3 clocks are used for both interface and functional clocks to |
| 566 | * multiple entities. Some of these clocks are completely managed | 466 | * multiple entities. Some of these clocks are completely managed |
| @@ -581,12 +481,8 @@ static struct clk iva1_mpu_int_ifck = { | |||
| 581 | */ | 481 | */ |
| 582 | static const struct clksel_rate core_l3_core_rates[] = { | 482 | static const struct clksel_rate core_l3_core_rates[] = { |
| 583 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | 483 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 584 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
| 585 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, | 484 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 586 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | 485 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 587 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 588 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 589 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | ||
| 590 | { .div = 0 } | 486 | { .div = 0 } |
| 591 | }; | 487 | }; |
| 592 | 488 | ||
| @@ -599,14 +495,11 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | |||
| 599 | .name = "core_l3_ck", | 495 | .name = "core_l3_ck", |
| 600 | .ops = &clkops_null, | 496 | .ops = &clkops_null, |
| 601 | .parent = &core_ck, | 497 | .parent = &core_ck, |
| 602 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 603 | .clkdm_name = "core_l3_clkdm", | 498 | .clkdm_name = "core_l3_clkdm", |
| 604 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 499 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 605 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 500 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| 606 | .clksel = core_l3_clksel, | 501 | .clksel = core_l3_clksel, |
| 607 | .recalc = &omap2_clksel_recalc, | 502 | .recalc = &omap2_clksel_recalc, |
| 608 | .round_rate = &omap2_clksel_round_rate, | ||
| 609 | .set_rate = &omap2_clksel_set_rate | ||
| 610 | }; | 503 | }; |
| 611 | 504 | ||
| 612 | /* usb_l4_ick */ | 505 | /* usb_l4_ick */ |
| @@ -627,7 +520,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ | |||
| 627 | .name = "usb_l4_ick", | 520 | .name = "usb_l4_ick", |
| 628 | .ops = &clkops_omap2_dflt_wait, | 521 | .ops = &clkops_omap2_dflt_wait, |
| 629 | .parent = &core_l3_ck, | 522 | .parent = &core_l3_ck, |
| 630 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 631 | .clkdm_name = "core_l4_clkdm", | 523 | .clkdm_name = "core_l4_clkdm", |
| 632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 524 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 633 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 525 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| @@ -635,8 +527,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ | |||
| 635 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | 527 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, |
| 636 | .clksel = usb_l4_ick_clksel, | 528 | .clksel = usb_l4_ick_clksel, |
| 637 | .recalc = &omap2_clksel_recalc, | 529 | .recalc = &omap2_clksel_recalc, |
| 638 | .round_rate = &omap2_clksel_round_rate, | ||
| 639 | .set_rate = &omap2_clksel_set_rate | ||
| 640 | }; | 530 | }; |
| 641 | 531 | ||
| 642 | /* | 532 | /* |
| @@ -661,14 +551,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */ | |||
| 661 | .name = "l4_ck", | 551 | .name = "l4_ck", |
| 662 | .ops = &clkops_null, | 552 | .ops = &clkops_null, |
| 663 | .parent = &core_l3_ck, | 553 | .parent = &core_l3_ck, |
| 664 | .flags = DELAYED_APP, | ||
| 665 | .clkdm_name = "core_l4_clkdm", | 554 | .clkdm_name = "core_l4_clkdm", |
| 666 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 555 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 667 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | 556 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| 668 | .clksel = l4_clksel, | 557 | .clksel = l4_clksel, |
| 669 | .recalc = &omap2_clksel_recalc, | 558 | .recalc = &omap2_clksel_recalc, |
| 670 | .round_rate = &omap2_clksel_round_rate, | ||
| 671 | .set_rate = &omap2_clksel_set_rate | ||
| 672 | }; | 559 | }; |
| 673 | 560 | ||
| 674 | /* | 561 | /* |
| @@ -685,8 +572,6 @@ static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { | |||
| 685 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | 572 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 686 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | 573 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 687 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | 574 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, |
| 688 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 689 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 690 | { .div = 0 } | 575 | { .div = 0 } |
| 691 | }; | 576 | }; |
| 692 | 577 | ||
| @@ -699,7 +584,6 @@ static struct clk ssi_ssr_sst_fck = { | |||
| 699 | .name = "ssi_fck", | 584 | .name = "ssi_fck", |
| 700 | .ops = &clkops_omap2_dflt_wait, | 585 | .ops = &clkops_omap2_dflt_wait, |
| 701 | .parent = &core_ck, | 586 | .parent = &core_ck, |
| 702 | .flags = DELAYED_APP, | ||
| 703 | .clkdm_name = "core_l3_clkdm", | 587 | .clkdm_name = "core_l3_clkdm", |
| 704 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 588 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 705 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | 589 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| @@ -707,8 +591,6 @@ static struct clk ssi_ssr_sst_fck = { | |||
| 707 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | 591 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
| 708 | .clksel = ssi_ssr_sst_fck_clksel, | 592 | .clksel = ssi_ssr_sst_fck_clksel, |
| 709 | .recalc = &omap2_clksel_recalc, | 593 | .recalc = &omap2_clksel_recalc, |
| 710 | .round_rate = &omap2_clksel_round_rate, | ||
| 711 | .set_rate = &omap2_clksel_set_rate | ||
| 712 | }; | 594 | }; |
| 713 | 595 | ||
| 714 | /* | 596 | /* |
| @@ -737,7 +619,6 @@ static struct clk ssi_l4_ick = { | |||
| 737 | * divided value of fclk. | 619 | * divided value of fclk. |
| 738 | * | 620 | * |
| 739 | */ | 621 | */ |
| 740 | /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ | ||
| 741 | 622 | ||
| 742 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | 623 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ |
| 743 | static const struct clksel gfx_fck_clksel[] = { | 624 | static const struct clksel gfx_fck_clksel[] = { |
| @@ -771,8 +652,6 @@ static struct clk gfx_2d_fck = { | |||
| 771 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | 652 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 772 | .clksel = gfx_fck_clksel, | 653 | .clksel = gfx_fck_clksel, |
| 773 | .recalc = &omap2_clksel_recalc, | 654 | .recalc = &omap2_clksel_recalc, |
| 774 | .round_rate = &omap2_clksel_round_rate, | ||
| 775 | .set_rate = &omap2_clksel_set_rate | ||
| 776 | }; | 655 | }; |
| 777 | 656 | ||
| 778 | static struct clk gfx_ick = { | 657 | static struct clk gfx_ick = { |
| @@ -809,7 +688,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
| 809 | .name = "mdm_ick", | 688 | .name = "mdm_ick", |
| 810 | .ops = &clkops_omap2_dflt_wait, | 689 | .ops = &clkops_omap2_dflt_wait, |
| 811 | .parent = &core_ck, | 690 | .parent = &core_ck, |
| 812 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 813 | .clkdm_name = "mdm_clkdm", | 691 | .clkdm_name = "mdm_clkdm", |
| 814 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | 692 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
| 815 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | 693 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
| @@ -817,8 +695,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
| 817 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, | 695 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, |
| 818 | .clksel = mdm_ick_clksel, | 696 | .clksel = mdm_ick_clksel, |
| 819 | .recalc = &omap2_clksel_recalc, | 697 | .recalc = &omap2_clksel_recalc, |
| 820 | .round_rate = &omap2_clksel_round_rate, | ||
| 821 | .set_rate = &omap2_clksel_set_rate | ||
| 822 | }; | 698 | }; |
| 823 | 699 | ||
| 824 | static struct clk mdm_osc_ck = { | 700 | static struct clk mdm_osc_ck = { |
| @@ -880,7 +756,6 @@ static struct clk dss1_fck = { | |||
| 880 | .name = "dss1_fck", | 756 | .name = "dss1_fck", |
| 881 | .ops = &clkops_omap2_dflt, | 757 | .ops = &clkops_omap2_dflt, |
| 882 | .parent = &core_ck, /* Core or sys */ | 758 | .parent = &core_ck, /* Core or sys */ |
| 883 | .flags = DELAYED_APP, | ||
| 884 | .clkdm_name = "dss_clkdm", | 759 | .clkdm_name = "dss_clkdm", |
| 885 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 760 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 886 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 761 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| @@ -889,8 +764,6 @@ static struct clk dss1_fck = { | |||
| 889 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | 764 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
| 890 | .clksel = dss1_fck_clksel, | 765 | .clksel = dss1_fck_clksel, |
| 891 | .recalc = &omap2_clksel_recalc, | 766 | .recalc = &omap2_clksel_recalc, |
| 892 | .round_rate = &omap2_clksel_round_rate, | ||
| 893 | .set_rate = &omap2_clksel_set_rate | ||
| 894 | }; | 767 | }; |
| 895 | 768 | ||
| 896 | static const struct clksel_rate dss2_fck_sys_rates[] = { | 769 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
| @@ -913,7 +786,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
| 913 | .name = "dss2_fck", | 786 | .name = "dss2_fck", |
| 914 | .ops = &clkops_omap2_dflt, | 787 | .ops = &clkops_omap2_dflt, |
| 915 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | 788 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
| 916 | .flags = DELAYED_APP, | ||
| 917 | .clkdm_name = "dss_clkdm", | 789 | .clkdm_name = "dss_clkdm", |
| 918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 790 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 919 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | 791 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| @@ -1242,9 +1114,8 @@ static struct clk gpt12_fck = { | |||
| 1242 | }; | 1114 | }; |
| 1243 | 1115 | ||
| 1244 | static struct clk mcbsp1_ick = { | 1116 | static struct clk mcbsp1_ick = { |
| 1245 | .name = "mcbsp_ick", | 1117 | .name = "mcbsp1_ick", |
| 1246 | .ops = &clkops_omap2_dflt_wait, | 1118 | .ops = &clkops_omap2_dflt_wait, |
| 1247 | .id = 1, | ||
| 1248 | .parent = &l4_ck, | 1119 | .parent = &l4_ck, |
| 1249 | .clkdm_name = "core_l4_clkdm", | 1120 | .clkdm_name = "core_l4_clkdm", |
| 1250 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1121 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1253,9 +1124,8 @@ static struct clk mcbsp1_ick = { | |||
| 1253 | }; | 1124 | }; |
| 1254 | 1125 | ||
| 1255 | static struct clk mcbsp1_fck = { | 1126 | static struct clk mcbsp1_fck = { |
| 1256 | .name = "mcbsp_fck", | 1127 | .name = "mcbsp1_fck", |
| 1257 | .ops = &clkops_omap2_dflt_wait, | 1128 | .ops = &clkops_omap2_dflt_wait, |
| 1258 | .id = 1, | ||
| 1259 | .parent = &func_96m_ck, | 1129 | .parent = &func_96m_ck, |
| 1260 | .clkdm_name = "core_l4_clkdm", | 1130 | .clkdm_name = "core_l4_clkdm", |
| 1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1131 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1264,9 +1134,8 @@ static struct clk mcbsp1_fck = { | |||
| 1264 | }; | 1134 | }; |
| 1265 | 1135 | ||
| 1266 | static struct clk mcbsp2_ick = { | 1136 | static struct clk mcbsp2_ick = { |
| 1267 | .name = "mcbsp_ick", | 1137 | .name = "mcbsp2_ick", |
| 1268 | .ops = &clkops_omap2_dflt_wait, | 1138 | .ops = &clkops_omap2_dflt_wait, |
| 1269 | .id = 2, | ||
| 1270 | .parent = &l4_ck, | 1139 | .parent = &l4_ck, |
| 1271 | .clkdm_name = "core_l4_clkdm", | 1140 | .clkdm_name = "core_l4_clkdm", |
| 1272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1141 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1275,9 +1144,8 @@ static struct clk mcbsp2_ick = { | |||
| 1275 | }; | 1144 | }; |
| 1276 | 1145 | ||
| 1277 | static struct clk mcbsp2_fck = { | 1146 | static struct clk mcbsp2_fck = { |
| 1278 | .name = "mcbsp_fck", | 1147 | .name = "mcbsp2_fck", |
| 1279 | .ops = &clkops_omap2_dflt_wait, | 1148 | .ops = &clkops_omap2_dflt_wait, |
| 1280 | .id = 2, | ||
| 1281 | .parent = &func_96m_ck, | 1149 | .parent = &func_96m_ck, |
| 1282 | .clkdm_name = "core_l4_clkdm", | 1150 | .clkdm_name = "core_l4_clkdm", |
| 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1151 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1286,9 +1154,8 @@ static struct clk mcbsp2_fck = { | |||
| 1286 | }; | 1154 | }; |
| 1287 | 1155 | ||
| 1288 | static struct clk mcbsp3_ick = { | 1156 | static struct clk mcbsp3_ick = { |
| 1289 | .name = "mcbsp_ick", | 1157 | .name = "mcbsp3_ick", |
| 1290 | .ops = &clkops_omap2_dflt_wait, | 1158 | .ops = &clkops_omap2_dflt_wait, |
| 1291 | .id = 3, | ||
| 1292 | .parent = &l4_ck, | 1159 | .parent = &l4_ck, |
| 1293 | .clkdm_name = "core_l4_clkdm", | 1160 | .clkdm_name = "core_l4_clkdm", |
| 1294 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1161 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| @@ -1297,9 +1164,8 @@ static struct clk mcbsp3_ick = { | |||
| 1297 | }; | 1164 | }; |
| 1298 | 1165 | ||
| 1299 | static struct clk mcbsp3_fck = { | 1166 | static struct clk mcbsp3_fck = { |
| 1300 | .name = "mcbsp_fck", | 1167 | .name = "mcbsp3_fck", |
| 1301 | .ops = &clkops_omap2_dflt_wait, | 1168 | .ops = &clkops_omap2_dflt_wait, |
| 1302 | .id = 3, | ||
| 1303 | .parent = &func_96m_ck, | 1169 | .parent = &func_96m_ck, |
| 1304 | .clkdm_name = "core_l4_clkdm", | 1170 | .clkdm_name = "core_l4_clkdm", |
| 1305 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1171 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -1308,9 +1174,8 @@ static struct clk mcbsp3_fck = { | |||
| 1308 | }; | 1174 | }; |
| 1309 | 1175 | ||
| 1310 | static struct clk mcbsp4_ick = { | 1176 | static struct clk mcbsp4_ick = { |
| 1311 | .name = "mcbsp_ick", | 1177 | .name = "mcbsp4_ick", |
| 1312 | .ops = &clkops_omap2_dflt_wait, | 1178 | .ops = &clkops_omap2_dflt_wait, |
| 1313 | .id = 4, | ||
| 1314 | .parent = &l4_ck, | 1179 | .parent = &l4_ck, |
| 1315 | .clkdm_name = "core_l4_clkdm", | 1180 | .clkdm_name = "core_l4_clkdm", |
| 1316 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1181 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| @@ -1319,9 +1184,8 @@ static struct clk mcbsp4_ick = { | |||
| 1319 | }; | 1184 | }; |
| 1320 | 1185 | ||
| 1321 | static struct clk mcbsp4_fck = { | 1186 | static struct clk mcbsp4_fck = { |
| 1322 | .name = "mcbsp_fck", | 1187 | .name = "mcbsp4_fck", |
| 1323 | .ops = &clkops_omap2_dflt_wait, | 1188 | .ops = &clkops_omap2_dflt_wait, |
| 1324 | .id = 4, | ||
| 1325 | .parent = &func_96m_ck, | 1189 | .parent = &func_96m_ck, |
| 1326 | .clkdm_name = "core_l4_clkdm", | 1190 | .clkdm_name = "core_l4_clkdm", |
| 1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1191 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -1330,9 +1194,8 @@ static struct clk mcbsp4_fck = { | |||
| 1330 | }; | 1194 | }; |
| 1331 | 1195 | ||
| 1332 | static struct clk mcbsp5_ick = { | 1196 | static struct clk mcbsp5_ick = { |
| 1333 | .name = "mcbsp_ick", | 1197 | .name = "mcbsp5_ick", |
| 1334 | .ops = &clkops_omap2_dflt_wait, | 1198 | .ops = &clkops_omap2_dflt_wait, |
| 1335 | .id = 5, | ||
| 1336 | .parent = &l4_ck, | 1199 | .parent = &l4_ck, |
| 1337 | .clkdm_name = "core_l4_clkdm", | 1200 | .clkdm_name = "core_l4_clkdm", |
| 1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1201 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| @@ -1341,9 +1204,8 @@ static struct clk mcbsp5_ick = { | |||
| 1341 | }; | 1204 | }; |
| 1342 | 1205 | ||
| 1343 | static struct clk mcbsp5_fck = { | 1206 | static struct clk mcbsp5_fck = { |
| 1344 | .name = "mcbsp_fck", | 1207 | .name = "mcbsp5_fck", |
| 1345 | .ops = &clkops_omap2_dflt_wait, | 1208 | .ops = &clkops_omap2_dflt_wait, |
| 1346 | .id = 5, | ||
| 1347 | .parent = &func_96m_ck, | 1209 | .parent = &func_96m_ck, |
| 1348 | .clkdm_name = "core_l4_clkdm", | 1210 | .clkdm_name = "core_l4_clkdm", |
| 1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -1352,9 +1214,8 @@ static struct clk mcbsp5_fck = { | |||
| 1352 | }; | 1214 | }; |
| 1353 | 1215 | ||
| 1354 | static struct clk mcspi1_ick = { | 1216 | static struct clk mcspi1_ick = { |
| 1355 | .name = "mcspi_ick", | 1217 | .name = "mcspi1_ick", |
| 1356 | .ops = &clkops_omap2_dflt_wait, | 1218 | .ops = &clkops_omap2_dflt_wait, |
| 1357 | .id = 1, | ||
| 1358 | .parent = &l4_ck, | 1219 | .parent = &l4_ck, |
| 1359 | .clkdm_name = "core_l4_clkdm", | 1220 | .clkdm_name = "core_l4_clkdm", |
| 1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1221 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1363,9 +1224,8 @@ static struct clk mcspi1_ick = { | |||
| 1363 | }; | 1224 | }; |
| 1364 | 1225 | ||
| 1365 | static struct clk mcspi1_fck = { | 1226 | static struct clk mcspi1_fck = { |
| 1366 | .name = "mcspi_fck", | 1227 | .name = "mcspi1_fck", |
| 1367 | .ops = &clkops_omap2_dflt_wait, | 1228 | .ops = &clkops_omap2_dflt_wait, |
| 1368 | .id = 1, | ||
| 1369 | .parent = &func_48m_ck, | 1229 | .parent = &func_48m_ck, |
| 1370 | .clkdm_name = "core_l4_clkdm", | 1230 | .clkdm_name = "core_l4_clkdm", |
| 1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1231 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1374,9 +1234,8 @@ static struct clk mcspi1_fck = { | |||
| 1374 | }; | 1234 | }; |
| 1375 | 1235 | ||
| 1376 | static struct clk mcspi2_ick = { | 1236 | static struct clk mcspi2_ick = { |
| 1377 | .name = "mcspi_ick", | 1237 | .name = "mcspi2_ick", |
| 1378 | .ops = &clkops_omap2_dflt_wait, | 1238 | .ops = &clkops_omap2_dflt_wait, |
| 1379 | .id = 2, | ||
| 1380 | .parent = &l4_ck, | 1239 | .parent = &l4_ck, |
| 1381 | .clkdm_name = "core_l4_clkdm", | 1240 | .clkdm_name = "core_l4_clkdm", |
| 1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1241 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1385,9 +1244,8 @@ static struct clk mcspi2_ick = { | |||
| 1385 | }; | 1244 | }; |
| 1386 | 1245 | ||
| 1387 | static struct clk mcspi2_fck = { | 1246 | static struct clk mcspi2_fck = { |
| 1388 | .name = "mcspi_fck", | 1247 | .name = "mcspi2_fck", |
| 1389 | .ops = &clkops_omap2_dflt_wait, | 1248 | .ops = &clkops_omap2_dflt_wait, |
| 1390 | .id = 2, | ||
| 1391 | .parent = &func_48m_ck, | 1249 | .parent = &func_48m_ck, |
| 1392 | .clkdm_name = "core_l4_clkdm", | 1250 | .clkdm_name = "core_l4_clkdm", |
| 1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1251 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1396,9 +1254,8 @@ static struct clk mcspi2_fck = { | |||
| 1396 | }; | 1254 | }; |
| 1397 | 1255 | ||
| 1398 | static struct clk mcspi3_ick = { | 1256 | static struct clk mcspi3_ick = { |
| 1399 | .name = "mcspi_ick", | 1257 | .name = "mcspi3_ick", |
| 1400 | .ops = &clkops_omap2_dflt_wait, | 1258 | .ops = &clkops_omap2_dflt_wait, |
| 1401 | .id = 3, | ||
| 1402 | .parent = &l4_ck, | 1259 | .parent = &l4_ck, |
| 1403 | .clkdm_name = "core_l4_clkdm", | 1260 | .clkdm_name = "core_l4_clkdm", |
| 1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| @@ -1407,9 +1264,8 @@ static struct clk mcspi3_ick = { | |||
| 1407 | }; | 1264 | }; |
| 1408 | 1265 | ||
| 1409 | static struct clk mcspi3_fck = { | 1266 | static struct clk mcspi3_fck = { |
| 1410 | .name = "mcspi_fck", | 1267 | .name = "mcspi3_fck", |
| 1411 | .ops = &clkops_omap2_dflt_wait, | 1268 | .ops = &clkops_omap2_dflt_wait, |
| 1412 | .id = 3, | ||
| 1413 | .parent = &func_48m_ck, | 1269 | .parent = &func_48m_ck, |
| 1414 | .clkdm_name = "core_l4_clkdm", | 1270 | .clkdm_name = "core_l4_clkdm", |
| 1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1271 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -1614,26 +1470,6 @@ static struct clk wdt4_fck = { | |||
| 1614 | .recalc = &followparent_recalc, | 1470 | .recalc = &followparent_recalc, |
| 1615 | }; | 1471 | }; |
| 1616 | 1472 | ||
| 1617 | static struct clk wdt3_ick = { | ||
| 1618 | .name = "wdt3_ick", | ||
| 1619 | .ops = &clkops_omap2_dflt_wait, | ||
| 1620 | .parent = &l4_ck, | ||
| 1621 | .clkdm_name = "core_l4_clkdm", | ||
| 1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1623 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
| 1624 | .recalc = &followparent_recalc, | ||
| 1625 | }; | ||
| 1626 | |||
| 1627 | static struct clk wdt3_fck = { | ||
| 1628 | .name = "wdt3_fck", | ||
| 1629 | .ops = &clkops_omap2_dflt_wait, | ||
| 1630 | .parent = &func_32k_ck, | ||
| 1631 | .clkdm_name = "core_l4_clkdm", | ||
| 1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1633 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
| 1634 | .recalc = &followparent_recalc, | ||
| 1635 | }; | ||
| 1636 | |||
| 1637 | static struct clk mspro_ick = { | 1473 | static struct clk mspro_ick = { |
| 1638 | .name = "mspro_ick", | 1474 | .name = "mspro_ick", |
| 1639 | .ops = &clkops_omap2_dflt_wait, | 1475 | .ops = &clkops_omap2_dflt_wait, |
| @@ -1654,26 +1490,6 @@ static struct clk mspro_fck = { | |||
| 1654 | .recalc = &followparent_recalc, | 1490 | .recalc = &followparent_recalc, |
| 1655 | }; | 1491 | }; |
| 1656 | 1492 | ||
| 1657 | static struct clk mmc_ick = { | ||
| 1658 | .name = "mmc_ick", | ||
| 1659 | .ops = &clkops_omap2_dflt_wait, | ||
| 1660 | .parent = &l4_ck, | ||
| 1661 | .clkdm_name = "core_l4_clkdm", | ||
| 1662 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1663 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
| 1664 | .recalc = &followparent_recalc, | ||
| 1665 | }; | ||
| 1666 | |||
| 1667 | static struct clk mmc_fck = { | ||
| 1668 | .name = "mmc_fck", | ||
| 1669 | .ops = &clkops_omap2_dflt_wait, | ||
| 1670 | .parent = &func_96m_ck, | ||
| 1671 | .clkdm_name = "core_l4_clkdm", | ||
| 1672 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1673 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
| 1674 | .recalc = &followparent_recalc, | ||
| 1675 | }; | ||
| 1676 | |||
| 1677 | static struct clk fac_ick = { | 1493 | static struct clk fac_ick = { |
| 1678 | .name = "fac_ick", | 1494 | .name = "fac_ick", |
| 1679 | .ops = &clkops_omap2_dflt_wait, | 1495 | .ops = &clkops_omap2_dflt_wait, |
| @@ -1694,26 +1510,6 @@ static struct clk fac_fck = { | |||
| 1694 | .recalc = &followparent_recalc, | 1510 | .recalc = &followparent_recalc, |
| 1695 | }; | 1511 | }; |
| 1696 | 1512 | ||
| 1697 | static struct clk eac_ick = { | ||
| 1698 | .name = "eac_ick", | ||
| 1699 | .ops = &clkops_omap2_dflt_wait, | ||
| 1700 | .parent = &l4_ck, | ||
| 1701 | .clkdm_name = "core_l4_clkdm", | ||
| 1702 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1703 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
| 1704 | .recalc = &followparent_recalc, | ||
| 1705 | }; | ||
| 1706 | |||
| 1707 | static struct clk eac_fck = { | ||
| 1708 | .name = "eac_fck", | ||
| 1709 | .ops = &clkops_omap2_dflt_wait, | ||
| 1710 | .parent = &func_96m_ck, | ||
| 1711 | .clkdm_name = "core_l4_clkdm", | ||
| 1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1713 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
| 1714 | .recalc = &followparent_recalc, | ||
| 1715 | }; | ||
| 1716 | |||
| 1717 | static struct clk hdq_ick = { | 1513 | static struct clk hdq_ick = { |
| 1718 | .name = "hdq_ick", | 1514 | .name = "hdq_ick", |
| 1719 | .ops = &clkops_omap2_dflt_wait, | 1515 | .ops = &clkops_omap2_dflt_wait, |
| @@ -1734,10 +1530,13 @@ static struct clk hdq_fck = { | |||
| 1734 | .recalc = &followparent_recalc, | 1530 | .recalc = &followparent_recalc, |
| 1735 | }; | 1531 | }; |
| 1736 | 1532 | ||
| 1533 | /* | ||
| 1534 | * XXX This is marked as a 2420-only define, but it claims to be present | ||
| 1535 | * on 2430 also. Double-check. | ||
| 1536 | */ | ||
| 1737 | static struct clk i2c2_ick = { | 1537 | static struct clk i2c2_ick = { |
| 1738 | .name = "i2c_ick", | 1538 | .name = "i2c2_ick", |
| 1739 | .ops = &clkops_omap2_dflt_wait, | 1539 | .ops = &clkops_omap2_dflt_wait, |
| 1740 | .id = 2, | ||
| 1741 | .parent = &l4_ck, | 1540 | .parent = &l4_ck, |
| 1742 | .clkdm_name = "core_l4_clkdm", | 1541 | .clkdm_name = "core_l4_clkdm", |
| 1743 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1745,21 +1544,9 @@ static struct clk i2c2_ick = { | |||
| 1745 | .recalc = &followparent_recalc, | 1544 | .recalc = &followparent_recalc, |
| 1746 | }; | 1545 | }; |
| 1747 | 1546 | ||
| 1748 | static struct clk i2c2_fck = { | ||
| 1749 | .name = "i2c_fck", | ||
| 1750 | .ops = &clkops_omap2_dflt_wait, | ||
| 1751 | .id = 2, | ||
| 1752 | .parent = &func_12m_ck, | ||
| 1753 | .clkdm_name = "core_l4_clkdm", | ||
| 1754 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1755 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
| 1756 | .recalc = &followparent_recalc, | ||
| 1757 | }; | ||
| 1758 | |||
| 1759 | static struct clk i2chs2_fck = { | 1547 | static struct clk i2chs2_fck = { |
| 1760 | .name = "i2c_fck", | 1548 | .name = "i2chs2_fck", |
| 1761 | .ops = &clkops_omap2430_i2chs_wait, | 1549 | .ops = &clkops_omap2430_i2chs_wait, |
| 1762 | .id = 2, | ||
| 1763 | .parent = &func_96m_ck, | 1550 | .parent = &func_96m_ck, |
| 1764 | .clkdm_name = "core_l4_clkdm", | 1551 | .clkdm_name = "core_l4_clkdm", |
| 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1552 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -1767,10 +1554,13 @@ static struct clk i2chs2_fck = { | |||
| 1767 | .recalc = &followparent_recalc, | 1554 | .recalc = &followparent_recalc, |
| 1768 | }; | 1555 | }; |
| 1769 | 1556 | ||
| 1557 | /* | ||
| 1558 | * XXX This is marked as a 2420-only define, but it claims to be present | ||
| 1559 | * on 2430 also. Double-check. | ||
| 1560 | */ | ||
| 1770 | static struct clk i2c1_ick = { | 1561 | static struct clk i2c1_ick = { |
| 1771 | .name = "i2c_ick", | 1562 | .name = "i2c1_ick", |
| 1772 | .ops = &clkops_omap2_dflt_wait, | 1563 | .ops = &clkops_omap2_dflt_wait, |
| 1773 | .id = 1, | ||
| 1774 | .parent = &l4_ck, | 1564 | .parent = &l4_ck, |
| 1775 | .clkdm_name = "core_l4_clkdm", | 1565 | .clkdm_name = "core_l4_clkdm", |
| 1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1566 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1778,21 +1568,9 @@ static struct clk i2c1_ick = { | |||
| 1778 | .recalc = &followparent_recalc, | 1568 | .recalc = &followparent_recalc, |
| 1779 | }; | 1569 | }; |
| 1780 | 1570 | ||
| 1781 | static struct clk i2c1_fck = { | ||
| 1782 | .name = "i2c_fck", | ||
| 1783 | .ops = &clkops_omap2_dflt_wait, | ||
| 1784 | .id = 1, | ||
| 1785 | .parent = &func_12m_ck, | ||
| 1786 | .clkdm_name = "core_l4_clkdm", | ||
| 1787 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1788 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
| 1789 | .recalc = &followparent_recalc, | ||
| 1790 | }; | ||
| 1791 | |||
| 1792 | static struct clk i2chs1_fck = { | 1571 | static struct clk i2chs1_fck = { |
| 1793 | .name = "i2c_fck", | 1572 | .name = "i2chs1_fck", |
| 1794 | .ops = &clkops_omap2430_i2chs_wait, | 1573 | .ops = &clkops_omap2430_i2chs_wait, |
| 1795 | .id = 1, | ||
| 1796 | .parent = &func_96m_ck, | 1574 | .parent = &func_96m_ck, |
| 1797 | .clkdm_name = "core_l4_clkdm", | 1575 | .clkdm_name = "core_l4_clkdm", |
| 1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1576 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -1825,58 +1603,6 @@ static struct clk sdma_ick = { | |||
| 1825 | .recalc = &followparent_recalc, | 1603 | .recalc = &followparent_recalc, |
| 1826 | }; | 1604 | }; |
| 1827 | 1605 | ||
| 1828 | static struct clk vlynq_ick = { | ||
| 1829 | .name = "vlynq_ick", | ||
| 1830 | .ops = &clkops_omap2_dflt_wait, | ||
| 1831 | .parent = &core_l3_ck, | ||
| 1832 | .clkdm_name = "core_l3_clkdm", | ||
| 1833 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1834 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
| 1835 | .recalc = &followparent_recalc, | ||
| 1836 | }; | ||
| 1837 | |||
| 1838 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | ||
| 1839 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
| 1840 | { .div = 0 } | ||
| 1841 | }; | ||
| 1842 | |||
| 1843 | static const struct clksel_rate vlynq_fck_core_rates[] = { | ||
| 1844 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | ||
| 1845 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
| 1846 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | ||
| 1847 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
| 1848 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 1849 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 1850 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | ||
| 1851 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 1852 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
| 1853 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, | ||
| 1854 | { .div = 0 } | ||
| 1855 | }; | ||
| 1856 | |||
| 1857 | static const struct clksel vlynq_fck_clksel[] = { | ||
| 1858 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | ||
| 1859 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | ||
| 1860 | { .parent = NULL } | ||
| 1861 | }; | ||
| 1862 | |||
| 1863 | static struct clk vlynq_fck = { | ||
| 1864 | .name = "vlynq_fck", | ||
| 1865 | .ops = &clkops_omap2_dflt_wait, | ||
| 1866 | .parent = &func_96m_ck, | ||
| 1867 | .flags = DELAYED_APP, | ||
| 1868 | .clkdm_name = "core_l3_clkdm", | ||
| 1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1870 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
| 1871 | .init = &omap2_init_clksel_parent, | ||
| 1872 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1873 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | ||
| 1874 | .clksel = vlynq_fck_clksel, | ||
| 1875 | .recalc = &omap2_clksel_recalc, | ||
| 1876 | .round_rate = &omap2_clksel_round_rate, | ||
| 1877 | .set_rate = &omap2_clksel_set_rate | ||
| 1878 | }; | ||
| 1879 | |||
| 1880 | static struct clk sdrc_ick = { | 1606 | static struct clk sdrc_ick = { |
| 1881 | .name = "sdrc_ick", | 1607 | .name = "sdrc_ick", |
| 1882 | .ops = &clkops_omap2_dflt_wait, | 1608 | .ops = &clkops_omap2_dflt_wait, |
| @@ -1959,7 +1685,7 @@ static struct clk usbhs_ick = { | |||
| 1959 | }; | 1685 | }; |
| 1960 | 1686 | ||
| 1961 | static struct clk mmchs1_ick = { | 1687 | static struct clk mmchs1_ick = { |
| 1962 | .name = "mmchs_ick", | 1688 | .name = "mmchs1_ick", |
| 1963 | .ops = &clkops_omap2_dflt_wait, | 1689 | .ops = &clkops_omap2_dflt_wait, |
| 1964 | .parent = &l4_ck, | 1690 | .parent = &l4_ck, |
| 1965 | .clkdm_name = "core_l4_clkdm", | 1691 | .clkdm_name = "core_l4_clkdm", |
| @@ -1969,7 +1695,7 @@ static struct clk mmchs1_ick = { | |||
| 1969 | }; | 1695 | }; |
| 1970 | 1696 | ||
| 1971 | static struct clk mmchs1_fck = { | 1697 | static struct clk mmchs1_fck = { |
| 1972 | .name = "mmchs_fck", | 1698 | .name = "mmchs1_fck", |
| 1973 | .ops = &clkops_omap2_dflt_wait, | 1699 | .ops = &clkops_omap2_dflt_wait, |
| 1974 | .parent = &func_96m_ck, | 1700 | .parent = &func_96m_ck, |
| 1975 | .clkdm_name = "core_l3_clkdm", | 1701 | .clkdm_name = "core_l3_clkdm", |
| @@ -1979,9 +1705,8 @@ static struct clk mmchs1_fck = { | |||
| 1979 | }; | 1705 | }; |
| 1980 | 1706 | ||
| 1981 | static struct clk mmchs2_ick = { | 1707 | static struct clk mmchs2_ick = { |
| 1982 | .name = "mmchs_ick", | 1708 | .name = "mmchs2_ick", |
| 1983 | .ops = &clkops_omap2_dflt_wait, | 1709 | .ops = &clkops_omap2_dflt_wait, |
| 1984 | .id = 1, | ||
| 1985 | .parent = &l4_ck, | 1710 | .parent = &l4_ck, |
| 1986 | .clkdm_name = "core_l4_clkdm", | 1711 | .clkdm_name = "core_l4_clkdm", |
| 1987 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| @@ -1990,9 +1715,8 @@ static struct clk mmchs2_ick = { | |||
| 1990 | }; | 1715 | }; |
| 1991 | 1716 | ||
| 1992 | static struct clk mmchs2_fck = { | 1717 | static struct clk mmchs2_fck = { |
| 1993 | .name = "mmchs_fck", | 1718 | .name = "mmchs2_fck", |
| 1994 | .ops = &clkops_omap2_dflt_wait, | 1719 | .ops = &clkops_omap2_dflt_wait, |
| 1995 | .id = 1, | ||
| 1996 | .parent = &func_96m_ck, | 1720 | .parent = &func_96m_ck, |
| 1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1721 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1998 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 1722 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| @@ -2030,7 +1754,7 @@ static struct clk mdm_intc_ick = { | |||
| 2030 | }; | 1754 | }; |
| 2031 | 1755 | ||
| 2032 | static struct clk mmchsdb1_fck = { | 1756 | static struct clk mmchsdb1_fck = { |
| 2033 | .name = "mmchsdb_fck", | 1757 | .name = "mmchsdb1_fck", |
| 2034 | .ops = &clkops_omap2_dflt_wait, | 1758 | .ops = &clkops_omap2_dflt_wait, |
| 2035 | .parent = &func_32k_ck, | 1759 | .parent = &func_32k_ck, |
| 2036 | .clkdm_name = "core_l4_clkdm", | 1760 | .clkdm_name = "core_l4_clkdm", |
| @@ -2040,9 +1764,8 @@ static struct clk mmchsdb1_fck = { | |||
| 2040 | }; | 1764 | }; |
| 2041 | 1765 | ||
| 2042 | static struct clk mmchsdb2_fck = { | 1766 | static struct clk mmchsdb2_fck = { |
| 2043 | .name = "mmchsdb_fck", | 1767 | .name = "mmchsdb2_fck", |
| 2044 | .ops = &clkops_omap2_dflt_wait, | 1768 | .ops = &clkops_omap2_dflt_wait, |
| 2045 | .id = 1, | ||
| 2046 | .parent = &func_32k_ck, | 1769 | .parent = &func_32k_ck, |
| 2047 | .clkdm_name = "core_l4_clkdm", | 1770 | .clkdm_name = "core_l4_clkdm", |
| 2048 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| @@ -2067,7 +1790,6 @@ static struct clk mmchsdb2_fck = { | |||
| 2067 | static struct clk virt_prcm_set = { | 1790 | static struct clk virt_prcm_set = { |
| 2068 | .name = "virt_prcm_set", | 1791 | .name = "virt_prcm_set", |
| 2069 | .ops = &clkops_null, | 1792 | .ops = &clkops_null, |
| 2070 | .flags = DELAYED_APP, | ||
| 2071 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | 1793 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
| 2072 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | 1794 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
| 2073 | .set_rate = &omap2_select_table_rate, | 1795 | .set_rate = &omap2_select_table_rate, |
| @@ -2079,149 +1801,134 @@ static struct clk virt_prcm_set = { | |||
| 2079 | * clkdev integration | 1801 | * clkdev integration |
| 2080 | */ | 1802 | */ |
| 2081 | 1803 | ||
| 2082 | static struct omap_clk omap24xx_clks[] = { | 1804 | static struct omap_clk omap2430_clks[] = { |
| 2083 | /* external root sources */ | 1805 | /* external root sources */ |
| 2084 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | 1806 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), |
| 2085 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), | 1807 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), |
| 2086 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | 1808 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), |
| 2087 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | 1809 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), |
| 2088 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | 1810 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), |
| 2089 | /* internal analog sources */ | 1811 | /* internal analog sources */ |
| 2090 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | 1812 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
| 2091 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | 1813 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), |
| 2092 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | 1814 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), |
| 2093 | /* internal prcm root sources */ | 1815 | /* internal prcm root sources */ |
| 2094 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | 1816 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
| 2095 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | 1817 | CLK(NULL, "core_ck", &core_ck, CK_243X), |
| 2096 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | 1818 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), |
| 2097 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | 1819 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), |
| 2098 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | 1820 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), |
| 2099 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | 1821 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), |
| 2100 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | 1822 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), |
| 2101 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | 1823 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), |
| 2102 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | 1824 | CLK(NULL, "emul_ck", &emul_ck, CK_243X), |
| 2103 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
| 2104 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
| 2105 | /* mpu domain clocks */ | 1825 | /* mpu domain clocks */ |
| 2106 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | 1826 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), |
| 2107 | /* dsp domain clocks */ | 1827 | /* dsp domain clocks */ |
| 2108 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | 1828 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), |
| 2109 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | 1829 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X), |
| 2110 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
| 2111 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | 1830 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), |
| 2112 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
| 2113 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
| 2114 | /* GFX domain clocks */ | 1831 | /* GFX domain clocks */ |
| 2115 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | 1832 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), |
| 2116 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | 1833 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), |
| 2117 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | 1834 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), |
| 2118 | /* Modem domain clocks */ | 1835 | /* Modem domain clocks */ |
| 2119 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | 1836 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), |
| 2120 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | 1837 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), |
| 2121 | /* DSS domain clocks */ | 1838 | /* DSS domain clocks */ |
| 2122 | CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), | 1839 | CLK("omapdss", "ick", &dss_ick, CK_243X), |
| 2123 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), | 1840 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), |
| 2124 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), | 1841 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), |
| 2125 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), | 1842 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), |
| 2126 | /* L3 domain clocks */ | 1843 | /* L3 domain clocks */ |
| 2127 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | 1844 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), |
| 2128 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | 1845 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), |
| 2129 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | 1846 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), |
| 2130 | /* L4 domain clocks */ | 1847 | /* L4 domain clocks */ |
| 2131 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | 1848 | CLK(NULL, "l4_ck", &l4_ck, CK_243X), |
| 2132 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | 1849 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), |
| 2133 | /* virtual meta-group clock */ | 1850 | /* virtual meta-group clock */ |
| 2134 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | 1851 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), |
| 2135 | /* general l4 interface ck, multi-parent functional clk */ | 1852 | /* general l4 interface ck, multi-parent functional clk */ |
| 2136 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | 1853 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), |
| 2137 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | 1854 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), |
| 2138 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | 1855 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), |
| 2139 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | 1856 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), |
| 2140 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | 1857 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), |
| 2141 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | 1858 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), |
| 2142 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | 1859 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), |
| 2143 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | 1860 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), |
| 2144 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | 1861 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), |
| 2145 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | 1862 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), |
| 2146 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | 1863 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), |
| 2147 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | 1864 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), |
| 2148 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | 1865 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), |
| 2149 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | 1866 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), |
| 2150 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | 1867 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), |
| 2151 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | 1868 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), |
| 2152 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | 1869 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), |
| 2153 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | 1870 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), |
| 2154 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | 1871 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), |
| 2155 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | 1872 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), |
| 2156 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | 1873 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), |
| 2157 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | 1874 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), |
| 2158 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | 1875 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), |
| 2159 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | 1876 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), |
| 2160 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | 1877 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), |
| 2161 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | 1878 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), |
| 2162 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | 1879 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), |
| 2163 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | 1880 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X), |
| 2164 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | 1881 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), |
| 2165 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | 1882 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), |
| 2166 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | 1883 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), |
| 2167 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | 1884 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), |
| 2168 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | 1885 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), |
| 2169 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | 1886 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), |
| 2170 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | 1887 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), |
| 2171 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | 1888 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X), |
| 2172 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | 1889 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), |
| 2173 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | 1890 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X), |
| 2174 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | 1891 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), |
| 2175 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | 1892 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), |
| 2176 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | 1893 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), |
| 2177 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | 1894 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), |
| 2178 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | 1895 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), |
| 2179 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | 1896 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), |
| 2180 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | 1897 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), |
| 2181 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | 1898 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), |
| 2182 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | 1899 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), |
| 2183 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | 1900 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), |
| 2184 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | 1901 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), |
| 2185 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | 1902 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X), |
| 2186 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | 1903 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), |
| 2187 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | 1904 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), |
| 2188 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | 1905 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), |
| 2189 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | 1906 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), |
| 2190 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | 1907 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X), |
| 2191 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | 1908 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X), |
| 2192 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | 1909 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), |
| 2193 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | 1910 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), |
| 2194 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | 1911 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), |
| 2195 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | 1912 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), |
| 2196 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | 1913 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), |
| 2197 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | 1914 | CLK(NULL, "fac_ick", &fac_ick, CK_243X), |
| 2198 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | 1915 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), |
| 2199 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | 1916 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), |
| 2200 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | 1917 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), |
| 2201 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | 1918 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X), |
| 2202 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | ||
| 2203 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
| 2204 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
| 2205 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | ||
| 2206 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | ||
| 2207 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | ||
| 2208 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
| 2209 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | 1919 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), |
| 2210 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | 1920 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X), |
| 2211 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
| 2212 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | 1921 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), |
| 2213 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | 1922 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), |
| 2214 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | 1923 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), |
| 2215 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | 1924 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), |
| 2216 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
| 2217 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
| 2218 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | 1925 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), |
| 2219 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | 1926 | CLK(NULL, "des_ick", &des_ick, CK_243X), |
| 2220 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | 1927 | CLK(NULL, "sha_ick", &sha_ick, CK_243X), |
| 2221 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | 1928 | CLK("omap_rng", "ick", &rng_ick, CK_243X), |
| 2222 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | 1929 | CLK(NULL, "aes_ick", &aes_ick, CK_243X), |
| 2223 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | 1930 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), |
| 2224 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | 1931 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), |
| 2225 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), | 1932 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), |
| 2226 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | 1933 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
| 2227 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | 1934 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), |
| @@ -2238,41 +1945,34 @@ static struct omap_clk omap24xx_clks[] = { | |||
| 2238 | * init code | 1945 | * init code |
| 2239 | */ | 1946 | */ |
| 2240 | 1947 | ||
| 2241 | int __init omap2_clk_init(void) | 1948 | int __init omap2430_clk_init(void) |
| 2242 | { | 1949 | { |
| 2243 | const struct prcm_config *prcm; | 1950 | const struct prcm_config *prcm; |
| 2244 | struct omap_clk *c; | 1951 | struct omap_clk *c; |
| 2245 | u32 clkrate; | 1952 | u32 clkrate; |
| 2246 | u16 cpu_clkflg; | 1953 | |
| 2247 | 1954 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | |
| 2248 | if (cpu_is_omap242x()) { | 1955 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); |
| 2249 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | 1956 | cpu_mask = RATE_IN_243X; |
| 2250 | cpu_mask = RATE_IN_242X; | 1957 | rate_table = omap2430_rate_table; |
| 2251 | cpu_clkflg = CK_242X; | ||
| 2252 | rate_table = omap2420_rate_table; | ||
| 2253 | } else if (cpu_is_omap2430()) { | ||
| 2254 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | ||
| 2255 | cpu_mask = RATE_IN_243X; | ||
| 2256 | cpu_clkflg = CK_243X; | ||
| 2257 | rate_table = omap2430_rate_table; | ||
| 2258 | } | ||
| 2259 | 1958 | ||
| 2260 | clk_init(&omap2_clk_functions); | 1959 | clk_init(&omap2_clk_functions); |
| 2261 | 1960 | ||
| 2262 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | 1961 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
| 1962 | c++) | ||
| 2263 | clk_preinit(c->lk.clk); | 1963 | clk_preinit(c->lk.clk); |
| 2264 | 1964 | ||
| 2265 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | 1965 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
| 2266 | propagate_rate(&osc_ck); | 1966 | propagate_rate(&osc_ck); |
| 2267 | sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); | 1967 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
| 2268 | propagate_rate(&sys_ck); | 1968 | propagate_rate(&sys_ck); |
| 2269 | 1969 | ||
| 2270 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | 1970 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
| 2271 | if (c->cpu & cpu_clkflg) { | 1971 | c++) { |
| 2272 | clkdev_add(&c->lk); | 1972 | clkdev_add(&c->lk); |
| 2273 | clk_register(c->lk.clk); | 1973 | clk_register(c->lk.clk); |
| 2274 | omap2_init_clk_clkdm(c->lk.clk); | 1974 | omap2_init_clk_clkdm(c->lk.clk); |
| 2275 | } | 1975 | } |
| 2276 | 1976 | ||
| 2277 | /* Check the MPU rate set by bootloader */ | 1977 | /* Check the MPU rate set by bootloader */ |
| 2278 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | 1978 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| @@ -2288,10 +1988,9 @@ int __init omap2_clk_init(void) | |||
| 2288 | 1988 | ||
| 2289 | recalculate_root_clocks(); | 1989 | recalculate_root_clocks(); |
| 2290 | 1990 | ||
| 2291 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | 1991 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 2292 | "%ld.%01ld/%ld/%ld MHz\n", | 1992 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 2293 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | 1993 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
| 2294 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
| 2295 | 1994 | ||
| 2296 | /* | 1995 | /* |
| 2297 | * Only enable those clocks we will need, let the drivers | 1996 | * Only enable those clocks we will need, let the drivers |
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 5420356eb407..80bb0f0e92e6 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c | |||
| @@ -1,15 +1,15 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c | 2 | * clock2xxx.c - OMAP2xxx-specific clock integration code |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2008 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Contacts: | 7 | * Contacts: |
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| 9 | * Paul Walmsley | 9 | * Paul Walmsley |
| 10 | * | 10 | * |
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, |
| 12 | * Gordon McNutt and RidgeRun, Inc. | 12 | * Gordon McNutt and RidgeRun, Inc. |
| 13 | * | 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify | 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
| @@ -17,568 +17,28 @@ | |||
| 17 | */ | 17 | */ |
| 18 | #undef DEBUG | 18 | #undef DEBUG |
| 19 | 19 | ||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 22 | #include <linux/device.h> | ||
| 23 | #include <linux/list.h> | ||
| 24 | #include <linux/errno.h> | 21 | #include <linux/errno.h> |
| 25 | #include <linux/delay.h> | ||
| 26 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 27 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 28 | #include <linux/cpufreq.h> | ||
| 29 | #include <linux/bitops.h> | ||
| 30 | 24 | ||
| 31 | #include <plat/clock.h> | 25 | #include <plat/clock.h> |
| 32 | #include <plat/sram.h> | ||
| 33 | #include <plat/prcm.h> | ||
| 34 | #include <plat/clkdev_omap.h> | ||
| 35 | #include <asm/div64.h> | ||
| 36 | #include <asm/clkdev.h> | ||
| 37 | 26 | ||
| 38 | #include <plat/sdrc.h> | ||
| 39 | #include "clock.h" | 27 | #include "clock.h" |
| 40 | #include "clock2xxx.h" | 28 | #include "clock2xxx.h" |
| 41 | #include "opp2xxx.h" | ||
| 42 | #include "prm.h" | ||
| 43 | #include "prm-regbits-24xx.h" | ||
| 44 | #include "cm.h" | 29 | #include "cm.h" |
| 45 | #include "cm-regbits-24xx.h" | 30 | #include "cm-regbits-24xx.h" |
| 46 | 31 | ||
| 47 | |||
| 48 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | ||
| 49 | #define EN_APLL_STOPPED 0 | ||
| 50 | #define EN_APLL_LOCKED 3 | ||
| 51 | |||
| 52 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ | ||
| 53 | #define APLLS_CLKIN_19_2MHZ 0 | ||
| 54 | #define APLLS_CLKIN_13MHZ 2 | ||
| 55 | #define APLLS_CLKIN_12MHZ 3 | ||
| 56 | |||
| 57 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | ||
| 58 | |||
| 59 | const struct prcm_config *curr_prcm_set; | ||
| 60 | const struct prcm_config *rate_table; | ||
| 61 | |||
| 62 | struct clk *vclk, *sclk, *dclk; | 32 | struct clk *vclk, *sclk, *dclk; |
| 63 | 33 | ||
| 64 | void __iomem *prcm_clksrc_ctrl; | ||
| 65 | |||
| 66 | /*------------------------------------------------------------------------- | ||
| 67 | * Omap24xx specific clock functions | ||
| 68 | *-------------------------------------------------------------------------*/ | ||
| 69 | |||
| 70 | /** | ||
| 71 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | ||
| 72 | * @clk: struct clk * being enabled | ||
| 73 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
| 74 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
| 75 | * | ||
| 76 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | ||
| 77 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | ||
| 78 | * passes back the correct CM_IDLEST register address for I2CHS | ||
| 79 | * modules. No return value. | ||
| 80 | */ | ||
| 81 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
| 82 | void __iomem **idlest_reg, | ||
| 83 | u8 *idlest_bit) | ||
| 84 | { | ||
| 85 | *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); | ||
| 86 | *idlest_bit = clk->enable_bit; | ||
| 87 | } | ||
| 88 | |||
| 89 | /* 2430 I2CHS has non-standard IDLEST register */ | ||
| 90 | const struct clkops clkops_omap2430_i2chs_wait = { | ||
| 91 | .enable = omap2_dflt_clk_enable, | ||
| 92 | .disable = omap2_dflt_clk_disable, | ||
| 93 | .find_idlest = omap2430_clk_i2chs_find_idlest, | ||
| 94 | .find_companion = omap2_clk_dflt_find_companion, | ||
| 95 | }; | ||
| 96 | |||
| 97 | /** | ||
| 98 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | ||
| 99 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
| 100 | * | ||
| 101 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | ||
| 102 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | ||
| 103 | * (the latter is unusual). This currently should be called with | ||
| 104 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | ||
| 105 | * core_ck. | ||
| 106 | */ | ||
| 107 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | ||
| 108 | { | ||
| 109 | long long core_clk; | ||
| 110 | u32 v; | ||
| 111 | |||
| 112 | core_clk = omap2_get_dpll_rate(clk); | ||
| 113 | |||
| 114 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 115 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 116 | |||
| 117 | if (v == CORE_CLK_SRC_32K) | ||
| 118 | core_clk = 32768; | ||
| 119 | else | ||
| 120 | core_clk *= v; | ||
| 121 | |||
| 122 | return core_clk; | ||
| 123 | } | ||
| 124 | |||
| 125 | static int omap2_enable_osc_ck(struct clk *clk) | ||
| 126 | { | ||
| 127 | u32 pcc; | ||
| 128 | |||
| 129 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
| 130 | |||
| 131 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
| 132 | |||
| 133 | return 0; | ||
| 134 | } | ||
| 135 | |||
| 136 | static void omap2_disable_osc_ck(struct clk *clk) | ||
| 137 | { | ||
| 138 | u32 pcc; | ||
| 139 | |||
| 140 | pcc = __raw_readl(prcm_clksrc_ctrl); | ||
| 141 | |||
| 142 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); | ||
| 143 | } | ||
| 144 | |||
| 145 | const struct clkops clkops_oscck = { | ||
| 146 | .enable = omap2_enable_osc_ck, | ||
| 147 | .disable = omap2_disable_osc_ck, | ||
| 148 | }; | ||
| 149 | |||
| 150 | #ifdef OLD_CK | ||
| 151 | /* Recalculate SYST_CLK */ | ||
| 152 | static void omap2_sys_clk_recalc(struct clk *clk) | ||
| 153 | { | ||
| 154 | u32 div = PRCM_CLKSRC_CTRL; | ||
| 155 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ | ||
| 156 | div >>= clk->rate_offset; | ||
| 157 | clk->rate = (clk->parent->rate / div); | ||
| 158 | propagate_rate(clk); | ||
| 159 | } | ||
| 160 | #endif /* OLD_CK */ | ||
| 161 | |||
| 162 | /* Enable an APLL if off */ | ||
| 163 | static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) | ||
| 164 | { | ||
| 165 | u32 cval, apll_mask; | ||
| 166 | |||
| 167 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
| 168 | |||
| 169 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
| 170 | |||
| 171 | if ((cval & apll_mask) == apll_mask) | ||
| 172 | return 0; /* apll already enabled */ | ||
| 173 | |||
| 174 | cval &= ~apll_mask; | ||
| 175 | cval |= apll_mask; | ||
| 176 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
| 177 | |||
| 178 | omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, | ||
| 179 | clk->name); | ||
| 180 | |||
| 181 | /* | ||
| 182 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | ||
| 183 | * fails? | ||
| 184 | */ | ||
| 185 | return 0; | ||
| 186 | } | ||
| 187 | |||
| 188 | static int omap2_clk_apll96_enable(struct clk *clk) | ||
| 189 | { | ||
| 190 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); | ||
| 191 | } | ||
| 192 | |||
| 193 | static int omap2_clk_apll54_enable(struct clk *clk) | ||
| 194 | { | ||
| 195 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); | ||
| 196 | } | ||
| 197 | |||
| 198 | /* Stop APLL */ | ||
| 199 | static void omap2_clk_apll_disable(struct clk *clk) | ||
| 200 | { | ||
| 201 | u32 cval; | ||
| 202 | |||
| 203 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
| 204 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | ||
| 205 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
| 206 | } | ||
| 207 | |||
| 208 | const struct clkops clkops_apll96 = { | ||
| 209 | .enable = omap2_clk_apll96_enable, | ||
| 210 | .disable = omap2_clk_apll_disable, | ||
| 211 | }; | ||
| 212 | |||
| 213 | const struct clkops clkops_apll54 = { | ||
| 214 | .enable = omap2_clk_apll54_enable, | ||
| 215 | .disable = omap2_clk_apll_disable, | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* | ||
| 219 | * Uses the current prcm set to tell if a rate is valid. | ||
| 220 | * You can go slower, but not faster within a given rate set. | ||
| 221 | */ | ||
| 222 | long omap2_dpllcore_round_rate(unsigned long target_rate) | ||
| 223 | { | ||
| 224 | u32 high, low, core_clk_src; | ||
| 225 | |||
| 226 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 227 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 228 | |||
| 229 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | ||
| 230 | high = curr_prcm_set->dpll_speed * 2; | ||
| 231 | low = curr_prcm_set->dpll_speed; | ||
| 232 | } else { /* DPLL clockout x 2 */ | ||
| 233 | high = curr_prcm_set->dpll_speed; | ||
| 234 | low = curr_prcm_set->dpll_speed / 2; | ||
| 235 | } | ||
| 236 | |||
| 237 | #ifdef DOWN_VARIABLE_DPLL | ||
| 238 | if (target_rate > high) | ||
| 239 | return high; | ||
| 240 | else | ||
| 241 | return target_rate; | ||
| 242 | #else | ||
| 243 | if (target_rate > low) | ||
| 244 | return high; | ||
| 245 | else | ||
| 246 | return low; | ||
| 247 | #endif | ||
| 248 | |||
| 249 | } | ||
| 250 | |||
| 251 | unsigned long omap2_dpllcore_recalc(struct clk *clk) | ||
| 252 | { | ||
| 253 | return omap2xxx_clk_get_core_rate(clk); | ||
| 254 | } | ||
| 255 | |||
| 256 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | ||
| 257 | { | ||
| 258 | u32 cur_rate, low, mult, div, valid_rate, done_rate; | ||
| 259 | u32 bypass = 0; | ||
| 260 | struct prcm_config tmpset; | ||
| 261 | const struct dpll_data *dd; | ||
| 262 | |||
| 263 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | ||
| 264 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 265 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 266 | |||
| 267 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | ||
| 268 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
| 269 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | ||
| 270 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 271 | } else if (rate != cur_rate) { | ||
| 272 | valid_rate = omap2_dpllcore_round_rate(rate); | ||
| 273 | if (valid_rate != rate) | ||
| 274 | return -EINVAL; | ||
| 275 | |||
| 276 | if (mult == 1) | ||
| 277 | low = curr_prcm_set->dpll_speed; | ||
| 278 | else | ||
| 279 | low = curr_prcm_set->dpll_speed / 2; | ||
| 280 | |||
| 281 | dd = clk->dpll_data; | ||
| 282 | if (!dd) | ||
| 283 | return -EINVAL; | ||
| 284 | |||
| 285 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | ||
| 286 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | ||
| 287 | dd->div1_mask); | ||
| 288 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | ||
| 289 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 290 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 291 | if (rate > low) { | ||
| 292 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | ||
| 293 | mult = ((rate / 2) / 1000000); | ||
| 294 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
| 295 | } else { | ||
| 296 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; | ||
| 297 | mult = (rate / 1000000); | ||
| 298 | done_rate = CORE_CLK_SRC_DPLL; | ||
| 299 | } | ||
| 300 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); | ||
| 301 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | ||
| 302 | |||
| 303 | /* Worst case */ | ||
| 304 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; | ||
| 305 | |||
| 306 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | ||
| 307 | bypass = 1; | ||
| 308 | |||
| 309 | /* For omap2xxx_sdrc_init_params() */ | ||
| 310 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 311 | |||
| 312 | /* Force dll lock mode */ | ||
| 313 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | ||
| 314 | bypass); | ||
| 315 | |||
| 316 | /* Errata: ret dll entry state */ | ||
| 317 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
| 318 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
| 319 | } | ||
| 320 | |||
| 321 | return 0; | ||
| 322 | } | ||
| 323 | |||
| 324 | /** | ||
| 325 | * omap2_table_mpu_recalc - just return the MPU speed | ||
| 326 | * @clk: virt_prcm_set struct clk | ||
| 327 | * | ||
| 328 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | ||
| 329 | */ | ||
| 330 | unsigned long omap2_table_mpu_recalc(struct clk *clk) | ||
| 331 | { | ||
| 332 | return curr_prcm_set->mpu_speed; | ||
| 333 | } | ||
| 334 | |||
| 335 | /* | ||
| 336 | * Look for a rate equal or less than the target rate given a configuration set. | ||
| 337 | * | ||
| 338 | * What's not entirely clear is "which" field represents the key field. | ||
| 339 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | ||
| 340 | * just uses the ARM rates. | ||
| 341 | */ | ||
| 342 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) | ||
| 343 | { | ||
| 344 | const struct prcm_config *ptr; | ||
| 345 | long highest_rate; | ||
| 346 | long sys_ck_rate; | ||
| 347 | |||
| 348 | sys_ck_rate = clk_get_rate(sclk); | ||
| 349 | |||
| 350 | highest_rate = -EINVAL; | ||
| 351 | |||
| 352 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | ||
| 353 | if (!(ptr->flags & cpu_mask)) | ||
| 354 | continue; | ||
| 355 | if (ptr->xtal_speed != sys_ck_rate) | ||
| 356 | continue; | ||
| 357 | |||
| 358 | highest_rate = ptr->mpu_speed; | ||
| 359 | |||
| 360 | /* Can check only after xtal frequency check */ | ||
| 361 | if (ptr->mpu_speed <= rate) | ||
| 362 | break; | ||
| 363 | } | ||
| 364 | return highest_rate; | ||
| 365 | } | ||
| 366 | |||
| 367 | /* Sets basic clocks based on the specified rate */ | ||
| 368 | int omap2_select_table_rate(struct clk *clk, unsigned long rate) | ||
| 369 | { | ||
| 370 | u32 cur_rate, done_rate, bypass = 0, tmp; | ||
| 371 | const struct prcm_config *prcm; | ||
| 372 | unsigned long found_speed = 0; | ||
| 373 | unsigned long flags; | ||
| 374 | long sys_ck_rate; | ||
| 375 | |||
| 376 | sys_ck_rate = clk_get_rate(sclk); | ||
| 377 | |||
| 378 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 379 | if (!(prcm->flags & cpu_mask)) | ||
| 380 | continue; | ||
| 381 | |||
| 382 | if (prcm->xtal_speed != sys_ck_rate) | ||
| 383 | continue; | ||
| 384 | |||
| 385 | if (prcm->mpu_speed <= rate) { | ||
| 386 | found_speed = prcm->mpu_speed; | ||
| 387 | break; | ||
| 388 | } | ||
| 389 | } | ||
| 390 | |||
| 391 | if (!found_speed) { | ||
| 392 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | ||
| 393 | rate / 1000000); | ||
| 394 | return -EINVAL; | ||
| 395 | } | ||
| 396 | |||
| 397 | curr_prcm_set = prcm; | ||
| 398 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | ||
| 399 | |||
| 400 | if (prcm->dpll_speed == cur_rate / 2) { | ||
| 401 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | ||
| 402 | } else if (prcm->dpll_speed == cur_rate * 2) { | ||
| 403 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 404 | } else if (prcm->dpll_speed != cur_rate) { | ||
| 405 | local_irq_save(flags); | ||
| 406 | |||
| 407 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 408 | bypass = 1; | ||
| 409 | |||
| 410 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == | ||
| 411 | CORE_CLK_SRC_DPLL_X2) | ||
| 412 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
| 413 | else | ||
| 414 | done_rate = CORE_CLK_SRC_DPLL; | ||
| 415 | |||
| 416 | /* MPU divider */ | ||
| 417 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); | ||
| 418 | |||
| 419 | /* dsp + iva1 div(2420), iva2.1(2430) */ | ||
| 420 | cm_write_mod_reg(prcm->cm_clksel_dsp, | ||
| 421 | OMAP24XX_DSP_MOD, CM_CLKSEL); | ||
| 422 | |||
| 423 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); | ||
| 424 | |||
| 425 | /* Major subsystem dividers */ | ||
| 426 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | ||
| 427 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, | ||
| 428 | CM_CLKSEL1); | ||
| 429 | |||
| 430 | if (cpu_is_omap2430()) | ||
| 431 | cm_write_mod_reg(prcm->cm_clksel_mdm, | ||
| 432 | OMAP2430_MDM_MOD, CM_CLKSEL); | ||
| 433 | |||
| 434 | /* x2 to enter omap2xxx_sdrc_init_params() */ | ||
| 435 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 436 | |||
| 437 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | ||
| 438 | bypass); | ||
| 439 | |||
| 440 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | ||
| 441 | omap2xxx_sdrc_reprogram(done_rate, 0); | ||
| 442 | |||
| 443 | local_irq_restore(flags); | ||
| 444 | } | ||
| 445 | |||
| 446 | return 0; | ||
| 447 | } | ||
| 448 | |||
| 449 | #ifdef CONFIG_CPU_FREQ | ||
| 450 | /* | 34 | /* |
| 451 | * Walk PRCM rate table and fillout cpufreq freq_table | 35 | * Omap24xx specific clock functions |
| 452 | * XXX This should be replaced by an OPP layer in the near future | ||
| 453 | */ | 36 | */ |
| 454 | static struct cpufreq_frequency_table *freq_table; | ||
| 455 | |||
| 456 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 457 | { | ||
| 458 | const struct prcm_config *prcm; | ||
| 459 | long sys_ck_rate; | ||
| 460 | int i = 0; | ||
| 461 | int tbl_sz = 0; | ||
| 462 | |||
| 463 | sys_ck_rate = clk_get_rate(sclk); | ||
| 464 | |||
| 465 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 466 | if (!(prcm->flags & cpu_mask)) | ||
| 467 | continue; | ||
| 468 | if (prcm->xtal_speed != sys_ck_rate) | ||
| 469 | continue; | ||
| 470 | |||
| 471 | /* don't put bypass rates in table */ | ||
| 472 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 473 | continue; | ||
| 474 | |||
| 475 | tbl_sz++; | ||
| 476 | } | ||
| 477 | |||
| 478 | /* | ||
| 479 | * XXX Ensure that we're doing what CPUFreq expects for this error | ||
| 480 | * case and the following one | ||
| 481 | */ | ||
| 482 | if (tbl_sz == 0) { | ||
| 483 | pr_warning("%s: no matching entries in rate_table\n", | ||
| 484 | __func__); | ||
| 485 | return; | ||
| 486 | } | ||
| 487 | |||
| 488 | /* Include the CPUFREQ_TABLE_END terminator entry */ | ||
| 489 | tbl_sz++; | ||
| 490 | |||
| 491 | freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz, | ||
| 492 | GFP_ATOMIC); | ||
| 493 | if (!freq_table) { | ||
| 494 | pr_err("%s: could not kzalloc frequency table\n", __func__); | ||
| 495 | return; | ||
| 496 | } | ||
| 497 | |||
| 498 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 499 | if (!(prcm->flags & cpu_mask)) | ||
| 500 | continue; | ||
| 501 | if (prcm->xtal_speed != sys_ck_rate) | ||
| 502 | continue; | ||
| 503 | |||
| 504 | /* don't put bypass rates in table */ | ||
| 505 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 506 | continue; | ||
| 507 | |||
| 508 | freq_table[i].index = i; | ||
| 509 | freq_table[i].frequency = prcm->mpu_speed / 1000; | ||
| 510 | i++; | ||
| 511 | } | ||
| 512 | |||
| 513 | freq_table[i].index = i; | ||
| 514 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
| 515 | |||
| 516 | *table = &freq_table[0]; | ||
| 517 | } | ||
| 518 | |||
| 519 | void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 520 | { | ||
| 521 | kfree(freq_table); | ||
| 522 | } | ||
| 523 | |||
| 524 | #endif | ||
| 525 | |||
| 526 | struct clk_functions omap2_clk_functions = { | ||
| 527 | .clk_enable = omap2_clk_enable, | ||
| 528 | .clk_disable = omap2_clk_disable, | ||
| 529 | .clk_round_rate = omap2_clk_round_rate, | ||
| 530 | .clk_set_rate = omap2_clk_set_rate, | ||
| 531 | .clk_set_parent = omap2_clk_set_parent, | ||
| 532 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 533 | #ifdef CONFIG_CPU_FREQ | ||
| 534 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | ||
| 535 | .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, | ||
| 536 | #endif | ||
| 537 | }; | ||
| 538 | |||
| 539 | static u32 omap2_get_apll_clkin(void) | ||
| 540 | { | ||
| 541 | u32 aplls, srate = 0; | ||
| 542 | |||
| 543 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | ||
| 544 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | ||
| 545 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | ||
| 546 | |||
| 547 | if (aplls == APLLS_CLKIN_19_2MHZ) | ||
| 548 | srate = 19200000; | ||
| 549 | else if (aplls == APLLS_CLKIN_13MHZ) | ||
| 550 | srate = 13000000; | ||
| 551 | else if (aplls == APLLS_CLKIN_12MHZ) | ||
| 552 | srate = 12000000; | ||
| 553 | |||
| 554 | return srate; | ||
| 555 | } | ||
| 556 | |||
| 557 | static u32 omap2_get_sysclkdiv(void) | ||
| 558 | { | ||
| 559 | u32 div; | ||
| 560 | |||
| 561 | div = __raw_readl(prcm_clksrc_ctrl); | ||
| 562 | div &= OMAP_SYSCLKDIV_MASK; | ||
| 563 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
| 564 | |||
| 565 | return div; | ||
| 566 | } | ||
| 567 | |||
| 568 | unsigned long omap2_osc_clk_recalc(struct clk *clk) | ||
| 569 | { | ||
| 570 | return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | ||
| 571 | } | ||
| 572 | |||
| 573 | unsigned long omap2_sys_clk_recalc(struct clk *clk) | ||
| 574 | { | ||
| 575 | return clk->parent->rate / omap2_get_sysclkdiv(); | ||
| 576 | } | ||
| 577 | 37 | ||
| 578 | /* | 38 | /* |
| 579 | * Set clocks for bypass mode for reboot to work. | 39 | * Set clocks for bypass mode for reboot to work. |
| 580 | */ | 40 | */ |
| 581 | void omap2_clk_prepare_for_reboot(void) | 41 | void omap2xxx_clk_prepare_for_reboot(void) |
| 582 | { | 42 | { |
| 583 | u32 rate; | 43 | u32 rate; |
| 584 | 44 | ||
| @@ -590,37 +50,24 @@ void omap2_clk_prepare_for_reboot(void) | |||
| 590 | } | 50 | } |
| 591 | 51 | ||
| 592 | /* | 52 | /* |
| 593 | * Switch the MPU rate if specified on cmdline. | 53 | * Switch the MPU rate if specified on cmdline. We cannot do this |
| 594 | * We cannot do this early until cmdline is parsed. | 54 | * early until cmdline is parsed. XXX This should be removed from the |
| 55 | * clock code and handled by the OPP layer code in the near future. | ||
| 595 | */ | 56 | */ |
| 596 | static int __init omap2_clk_arch_init(void) | 57 | static int __init omap2xxx_clk_arch_init(void) |
| 597 | { | 58 | { |
| 598 | struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; | 59 | int ret; |
| 599 | unsigned long sys_ck_rate; | ||
| 600 | 60 | ||
| 601 | if (!mpurate) | 61 | if (!cpu_is_omap24xx()) |
| 602 | return -EINVAL; | 62 | return 0; |
| 603 | 63 | ||
| 604 | virt_prcm_set = clk_get(NULL, "virt_prcm_set"); | 64 | ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set"); |
| 605 | sys_ck = clk_get(NULL, "sys_ck"); | 65 | if (!ret) |
| 606 | dpll_ck = clk_get(NULL, "dpll_ck"); | 66 | omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck"); |
| 607 | mpu_ck = clk_get(NULL, "mpu_ck"); | ||
| 608 | 67 | ||
| 609 | if (clk_set_rate(virt_prcm_set, mpurate)) | 68 | return ret; |
| 610 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
| 611 | |||
| 612 | recalculate_root_clocks(); | ||
| 613 | |||
| 614 | sys_ck_rate = clk_get_rate(sys_ck); | ||
| 615 | |||
| 616 | pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): " | ||
| 617 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 618 | (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10, | ||
| 619 | (clk_get_rate(dpll_ck) / 1000000), | ||
| 620 | (clk_get_rate(mpu_ck) / 1000000)); | ||
| 621 | |||
| 622 | return 0; | ||
| 623 | } | 69 | } |
| 624 | arch_initcall(omap2_clk_arch_init); | 70 | |
| 71 | arch_initcall(omap2xxx_clk_arch_init); | ||
| 625 | 72 | ||
| 626 | 73 | ||
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index e35efde4bd80..6a658b890c17 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
| @@ -1,35 +1,38 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP2 clock function prototypes and macros | 2 | * OMAP2 clock function prototypes and macros |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2009 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H |
| 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H |
| 10 | 10 | ||
| 11 | unsigned long omap2_table_mpu_recalc(struct clk *clk); | 11 | unsigned long omap2_table_mpu_recalc(struct clk *clk); |
| 12 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); | 12 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); |
| 13 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); | 13 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); |
| 14 | unsigned long omap2_sys_clk_recalc(struct clk *clk); | 14 | unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); |
| 15 | unsigned long omap2_osc_clk_recalc(struct clk *clk); | 15 | unsigned long omap2_osc_clk_recalc(struct clk *clk); |
| 16 | unsigned long omap2_sys_clk_recalc(struct clk *clk); | ||
| 17 | unsigned long omap2_dpllcore_recalc(struct clk *clk); | 16 | unsigned long omap2_dpllcore_recalc(struct clk *clk); |
| 18 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); | 17 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); |
| 19 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); | 18 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); |
| 19 | u32 omap2xxx_get_apll_clkin(void); | ||
| 20 | u32 omap2xxx_get_sysclkdiv(void); | ||
| 21 | void omap2xxx_clk_prepare_for_reboot(void); | ||
| 20 | 22 | ||
| 21 | /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ | ||
| 22 | #ifdef CONFIG_ARCH_OMAP2420 | 23 | #ifdef CONFIG_ARCH_OMAP2420 |
| 23 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR | 24 | int omap2420_clk_init(void); |
| 24 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL | ||
| 25 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL | ||
| 26 | #else | 25 | #else |
| 27 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR | 26 | #define omap2420_clk_init() 0 |
| 28 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL | ||
| 29 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL | ||
| 30 | #endif | 27 | #endif |
| 31 | 28 | ||
| 32 | extern void __iomem *prcm_clksrc_ctrl; | 29 | #ifdef CONFIG_ARCH_OMAP2430 |
| 30 | int omap2430_clk_init(void); | ||
| 31 | #else | ||
| 32 | #define omap2430_clk_init() 0 | ||
| 33 | #endif | ||
| 34 | |||
| 35 | extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; | ||
| 33 | 36 | ||
| 34 | extern struct clk *dclk; | 37 | extern struct clk *dclk; |
| 35 | 38 | ||
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index d4217b93e10b..6febd5f11e85 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
| @@ -2,13 +2,14 @@ | |||
| 2 | * OMAP3-specific clock framework functions | 2 | * OMAP3-specific clock framework functions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Paul Walmsley |
| 8 | * Testing and integration fixes by Jouni Högander | 8 | * Jouni Högander |
| 9 | * | 9 | * |
| 10 | * Parts of this code are based on code written by | 10 | * Parts of this code are based on code written by |
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, |
| 12 | * Russell King | ||
| 12 | * | 13 | * |
| 13 | * This program is free software; you can redistribute it and/or modify | 14 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
| @@ -16,49 +17,23 @@ | |||
| 16 | */ | 17 | */ |
| 17 | #undef DEBUG | 18 | #undef DEBUG |
| 18 | 19 | ||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/device.h> | ||
| 22 | #include <linux/list.h> | ||
| 23 | #include <linux/errno.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 26 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 27 | #include <linux/limits.h> | ||
| 28 | #include <linux/bitops.h> | ||
| 29 | 23 | ||
| 30 | #include <plat/cpu.h> | ||
| 31 | #include <plat/clock.h> | 24 | #include <plat/clock.h> |
| 32 | #include <plat/sram.h> | ||
| 33 | #include <plat/sdrc.h> | ||
| 34 | #include <asm/div64.h> | ||
| 35 | #include <asm/clkdev.h> | ||
| 36 | 25 | ||
| 37 | #include "clock.h" | 26 | #include "clock.h" |
| 38 | #include "clock34xx.h" | 27 | #include "clock34xx.h" |
| 39 | #include "sdrc.h" | ||
| 40 | #include "prm.h" | ||
| 41 | #include "prm-regbits-34xx.h" | ||
| 42 | #include "cm.h" | 28 | #include "cm.h" |
| 43 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
| 44 | 30 | ||
| 45 | #define CYCLES_PER_MHZ 1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | ||
| 49 | * that are sourced by DPLL5, and both of these require this clock | ||
| 50 | * to be at 120 MHz for proper operation. | ||
| 51 | */ | ||
| 52 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | ||
| 53 | |||
| 54 | /* needed by omap3_core_dpll_m2_set_rate() */ | ||
| 55 | struct clk *sdrc_ick_p, *arm_fck_p; | ||
| 56 | |||
| 57 | /** | 31 | /** |
| 58 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI | 32 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI |
| 59 | * @clk: struct clk * being enabled | 33 | * @clk: struct clk * being enabled |
| 60 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 34 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
| 61 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 35 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
| 36 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
| 62 | * | 37 | * |
| 63 | * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift | 38 | * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift |
| 64 | * from the CM_{I,F}CLKEN bit. Pass back the correct info via | 39 | * from the CM_{I,F}CLKEN bit. Pass back the correct info via |
| @@ -66,13 +41,15 @@ struct clk *sdrc_ick_p, *arm_fck_p; | |||
| 66 | */ | 41 | */ |
| 67 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | 42 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, |
| 68 | void __iomem **idlest_reg, | 43 | void __iomem **idlest_reg, |
| 69 | u8 *idlest_bit) | 44 | u8 *idlest_bit, |
| 45 | u8 *idlest_val) | ||
| 70 | { | 46 | { |
| 71 | u32 r; | 47 | u32 r; |
| 72 | 48 | ||
| 73 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 49 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 74 | *idlest_reg = (__force void __iomem *)r; | 50 | *idlest_reg = (__force void __iomem *)r; |
| 75 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; | 51 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; |
| 52 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
| 76 | } | 53 | } |
| 77 | 54 | ||
| 78 | const struct clkops clkops_omap3430es2_ssi_wait = { | 55 | const struct clkops clkops_omap3430es2_ssi_wait = { |
| @@ -87,6 +64,7 @@ const struct clkops clkops_omap3430es2_ssi_wait = { | |||
| 87 | * @clk: struct clk * being enabled | 64 | * @clk: struct clk * being enabled |
| 88 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 65 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
| 89 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 66 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
| 67 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
| 90 | * | 68 | * |
| 91 | * Some OMAP modules on OMAP3 ES2+ chips have both initiator and | 69 | * Some OMAP modules on OMAP3 ES2+ chips have both initiator and |
| 92 | * target IDLEST bits. For our purposes, we are concerned with the | 70 | * target IDLEST bits. For our purposes, we are concerned with the |
| @@ -97,7 +75,8 @@ const struct clkops clkops_omap3430es2_ssi_wait = { | |||
| 97 | */ | 75 | */ |
| 98 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | 76 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, |
| 99 | void __iomem **idlest_reg, | 77 | void __iomem **idlest_reg, |
| 100 | u8 *idlest_bit) | 78 | u8 *idlest_bit, |
| 79 | u8 *idlest_val) | ||
| 101 | { | 80 | { |
| 102 | u32 r; | 81 | u32 r; |
| 103 | 82 | ||
| @@ -105,6 +84,7 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | |||
| 105 | *idlest_reg = (__force void __iomem *)r; | 84 | *idlest_reg = (__force void __iomem *)r; |
| 106 | /* USBHOST_IDLE has same shift */ | 85 | /* USBHOST_IDLE has same shift */ |
| 107 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; | 86 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; |
| 87 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
| 108 | } | 88 | } |
| 109 | 89 | ||
| 110 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | 90 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { |
| @@ -119,6 +99,7 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | |||
| 119 | * @clk: struct clk * being enabled | 99 | * @clk: struct clk * being enabled |
| 120 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 100 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
| 121 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 101 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
| 102 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
| 122 | * | 103 | * |
| 123 | * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different | 104 | * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different |
| 124 | * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via | 105 | * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via |
| @@ -126,13 +107,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | |||
| 126 | */ | 107 | */ |
| 127 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | 108 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, |
| 128 | void __iomem **idlest_reg, | 109 | void __iomem **idlest_reg, |
| 129 | u8 *idlest_bit) | 110 | u8 *idlest_bit, |
| 111 | u8 *idlest_val) | ||
| 130 | { | 112 | { |
| 131 | u32 r; | 113 | u32 r; |
| 132 | 114 | ||
| 133 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 115 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 134 | *idlest_reg = (__force void __iomem *)r; | 116 | *idlest_reg = (__force void __iomem *)r; |
| 135 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; | 117 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; |
| 118 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
| 136 | } | 119 | } |
| 137 | 120 | ||
| 138 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { | 121 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { |
| @@ -141,213 +124,3 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = { | |||
| 141 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, | 124 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, |
| 142 | .find_companion = omap2_clk_dflt_find_companion, | 125 | .find_companion = omap2_clk_dflt_find_companion, |
| 143 | }; | 126 | }; |
| 144 | |||
| 145 | const struct clkops clkops_noncore_dpll_ops = { | ||
| 146 | .enable = omap3_noncore_dpll_enable, | ||
| 147 | .disable = omap3_noncore_dpll_disable, | ||
| 148 | }; | ||
| 149 | |||
| 150 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | ||
| 151 | { | ||
| 152 | /* | ||
| 153 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | ||
| 154 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | ||
| 155 | * on DPLL4. | ||
| 156 | */ | ||
| 157 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
| 158 | printk(KERN_ERR "clock: DPLL4 cannot change rate due to " | ||
| 159 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | ||
| 160 | return -EINVAL; | ||
| 161 | } | ||
| 162 | return omap3_noncore_dpll_set_rate(clk, rate); | ||
| 163 | } | ||
| 164 | |||
| 165 | |||
| 166 | /* | ||
| 167 | * CORE DPLL (DPLL3) rate programming functions | ||
| 168 | * | ||
| 169 | * These call into SRAM code to do the actual CM writes, since the SDRAM | ||
| 170 | * is clocked from DPLL3. | ||
| 171 | */ | ||
| 172 | |||
| 173 | /** | ||
| 174 | * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider | ||
| 175 | * @clk: struct clk * of DPLL to set | ||
| 176 | * @rate: rounded target rate | ||
| 177 | * | ||
| 178 | * Program the DPLL M2 divider with the rounded target rate. Returns | ||
| 179 | * -EINVAL upon error, or 0 upon success. | ||
| 180 | */ | ||
| 181 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | ||
| 182 | { | ||
| 183 | u32 new_div = 0; | ||
| 184 | u32 unlock_dll = 0; | ||
| 185 | u32 c; | ||
| 186 | unsigned long validrate, sdrcrate, _mpurate; | ||
| 187 | struct omap_sdrc_params *sdrc_cs0; | ||
| 188 | struct omap_sdrc_params *sdrc_cs1; | ||
| 189 | int ret; | ||
| 190 | |||
| 191 | if (!clk || !rate) | ||
| 192 | return -EINVAL; | ||
| 193 | |||
| 194 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | ||
| 195 | if (validrate != rate) | ||
| 196 | return -EINVAL; | ||
| 197 | |||
| 198 | sdrcrate = sdrc_ick_p->rate; | ||
| 199 | if (rate > clk->rate) | ||
| 200 | sdrcrate <<= ((rate / clk->rate) >> 1); | ||
| 201 | else | ||
| 202 | sdrcrate >>= ((clk->rate / rate) >> 1); | ||
| 203 | |||
| 204 | ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); | ||
| 205 | if (ret) | ||
| 206 | return -EINVAL; | ||
| 207 | |||
| 208 | if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { | ||
| 209 | pr_debug("clock: will unlock SDRC DLL\n"); | ||
| 210 | unlock_dll = 1; | ||
| 211 | } | ||
| 212 | |||
| 213 | /* | ||
| 214 | * XXX This only needs to be done when the CPU frequency changes | ||
| 215 | */ | ||
| 216 | _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; | ||
| 217 | c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | ||
| 218 | c += 1; /* for safety */ | ||
| 219 | c *= SDRC_MPURATE_LOOPS; | ||
| 220 | c >>= SDRC_MPURATE_SCALE; | ||
| 221 | if (c == 0) | ||
| 222 | c = 1; | ||
| 223 | |||
| 224 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | ||
| 225 | validrate); | ||
| 226 | pr_debug("clock: SDRC CS0 timing params used:" | ||
| 227 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | ||
| 228 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | ||
| 229 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); | ||
| 230 | if (sdrc_cs1) | ||
| 231 | pr_debug("clock: SDRC CS1 timing params used: " | ||
| 232 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | ||
| 233 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | ||
| 234 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | ||
| 235 | |||
| 236 | if (sdrc_cs1) | ||
| 237 | omap3_configure_core_dpll( | ||
| 238 | new_div, unlock_dll, c, rate > clk->rate, | ||
| 239 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | ||
| 240 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | ||
| 241 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | ||
| 242 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | ||
| 243 | else | ||
| 244 | omap3_configure_core_dpll( | ||
| 245 | new_div, unlock_dll, c, rate > clk->rate, | ||
| 246 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | ||
| 247 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | ||
| 248 | 0, 0, 0, 0); | ||
| 249 | |||
| 250 | return 0; | ||
| 251 | } | ||
| 252 | |||
| 253 | /* Common clock code */ | ||
| 254 | |||
| 255 | /* | ||
| 256 | * As it is structured now, this will prevent an OMAP2/3 multiboot | ||
| 257 | * kernel from compiling. This will need further attention. | ||
| 258 | */ | ||
| 259 | #if defined(CONFIG_ARCH_OMAP3) | ||
| 260 | |||
| 261 | struct clk_functions omap2_clk_functions = { | ||
| 262 | .clk_enable = omap2_clk_enable, | ||
| 263 | .clk_disable = omap2_clk_disable, | ||
| 264 | .clk_round_rate = omap2_clk_round_rate, | ||
| 265 | .clk_set_rate = omap2_clk_set_rate, | ||
| 266 | .clk_set_parent = omap2_clk_set_parent, | ||
| 267 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 268 | }; | ||
| 269 | |||
| 270 | /* | ||
| 271 | * Set clocks for bypass mode for reboot to work. | ||
| 272 | */ | ||
| 273 | void omap2_clk_prepare_for_reboot(void) | ||
| 274 | { | ||
| 275 | /* REVISIT: Not ready for 343x */ | ||
| 276 | #if 0 | ||
| 277 | u32 rate; | ||
| 278 | |||
| 279 | if (vclk == NULL || sclk == NULL) | ||
| 280 | return; | ||
| 281 | |||
| 282 | rate = clk_get_rate(sclk); | ||
| 283 | clk_set_rate(vclk, rate); | ||
| 284 | #endif | ||
| 285 | } | ||
| 286 | |||
| 287 | void omap3_clk_lock_dpll5(void) | ||
| 288 | { | ||
| 289 | struct clk *dpll5_clk; | ||
| 290 | struct clk *dpll5_m2_clk; | ||
| 291 | |||
| 292 | dpll5_clk = clk_get(NULL, "dpll5_ck"); | ||
| 293 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); | ||
| 294 | clk_enable(dpll5_clk); | ||
| 295 | |||
| 296 | /* Enable autoidle to allow it to enter low power bypass */ | ||
| 297 | omap3_dpll_allow_idle(dpll5_clk); | ||
| 298 | |||
| 299 | /* Program dpll5_m2_clk divider for no division */ | ||
| 300 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); | ||
| 301 | clk_enable(dpll5_m2_clk); | ||
| 302 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); | ||
| 303 | |||
| 304 | clk_disable(dpll5_m2_clk); | ||
| 305 | clk_disable(dpll5_clk); | ||
| 306 | return; | ||
| 307 | } | ||
| 308 | |||
| 309 | /* REVISIT: Move this init stuff out into clock.c */ | ||
| 310 | |||
| 311 | /* | ||
| 312 | * Switch the MPU rate if specified on cmdline. | ||
| 313 | * We cannot do this early until cmdline is parsed. | ||
| 314 | */ | ||
| 315 | static int __init omap2_clk_arch_init(void) | ||
| 316 | { | ||
| 317 | struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; | ||
| 318 | unsigned long osc_sys_rate; | ||
| 319 | |||
| 320 | if (!mpurate) | ||
| 321 | return -EINVAL; | ||
| 322 | |||
| 323 | /* XXX test these for success */ | ||
| 324 | dpll1_ck = clk_get(NULL, "dpll1_ck"); | ||
| 325 | arm_fck = clk_get(NULL, "arm_fck"); | ||
| 326 | core_ck = clk_get(NULL, "core_ck"); | ||
| 327 | osc_sys_ck = clk_get(NULL, "osc_sys_ck"); | ||
| 328 | |||
| 329 | /* REVISIT: not yet ready for 343x */ | ||
| 330 | if (clk_set_rate(dpll1_ck, mpurate)) | ||
| 331 | printk(KERN_ERR "*** Unable to set MPU rate\n"); | ||
| 332 | |||
| 333 | recalculate_root_clocks(); | ||
| 334 | |||
| 335 | osc_sys_rate = clk_get_rate(osc_sys_ck); | ||
| 336 | |||
| 337 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " | ||
| 338 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 339 | (osc_sys_rate / 1000000), | ||
| 340 | ((osc_sys_rate / 100000) % 10), | ||
| 341 | (clk_get_rate(core_ck) / 1000000), | ||
| 342 | (clk_get_rate(arm_fck) / 1000000)); | ||
| 343 | |||
| 344 | calibrate_delay(); | ||
| 345 | |||
| 346 | return 0; | ||
| 347 | } | ||
| 348 | arch_initcall(omap2_clk_arch_init); | ||
| 349 | |||
| 350 | |||
| 351 | #endif | ||
| 352 | |||
| 353 | |||
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 9a2c07eac9ad..628e8de57680 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
| @@ -1,24 +1,15 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP3 clock function prototypes and macros | 2 | * OMAP34xx clock function prototypes and macros |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 10 | 10 | ||
| 11 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | ||
| 12 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
| 13 | void omap3_clk_lock_dpll5(void); | ||
| 14 | |||
| 15 | extern struct clk *sdrc_ick_p; | ||
| 16 | extern struct clk *arm_fck_p; | ||
| 17 | |||
| 18 | /* OMAP34xx-specific clkops */ | ||
| 19 | extern const struct clkops clkops_omap3430es2_ssi_wait; | 11 | extern const struct clkops clkops_omap3430es2_ssi_wait; |
| 20 | extern const struct clkops clkops_omap3430es2_hsotgusb_wait; | 12 | extern const struct clkops clkops_omap3430es2_hsotgusb_wait; |
| 21 | extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; | 13 | extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; |
| 22 | extern const struct clkops clkops_noncore_dpll_ops; | ||
| 23 | 14 | ||
| 24 | #endif | 15 | #endif |
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c new file mode 100644 index 000000000000..b496a9305e1c --- /dev/null +++ b/arch/arm/mach-omap2/clock3517.c | |||
| @@ -0,0 +1,124 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3517/3505-specific clock framework functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Ranjith Lohithakshan | ||
| 8 | * Paul Walmsley | ||
| 9 | * | ||
| 10 | * Parts of this code are based on code written by | ||
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, | ||
| 12 | * Russell King | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | #undef DEBUG | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | |||
| 26 | #include "clock.h" | ||
| 27 | #include "clock3517.h" | ||
| 28 | #include "cm.h" | ||
| 29 | #include "cm-regbits-34xx.h" | ||
| 30 | |||
| 31 | /* | ||
| 32 | * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported | ||
| 33 | * in the same register at a bit offset of 0x8. The EN_ACK for ICK is | ||
| 34 | * at an offset of 4 from ICK enable bit. | ||
| 35 | */ | ||
| 36 | #define AM35XX_IPSS_ICK_MASK 0xF | ||
| 37 | #define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 | ||
| 38 | #define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 | ||
| 39 | #define AM35XX_IPSS_CLK_IDLEST_VAL 0 | ||
| 40 | |||
| 41 | /** | ||
| 42 | * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS | ||
| 43 | * @clk: struct clk * being enabled | ||
| 44 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
| 45 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
| 46 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
| 47 | * | ||
| 48 | * The interface clocks on AM35xx IPSS reflects the clock idle status | ||
| 49 | * in the enable register itsel at a bit offset of 4 from the enable | ||
| 50 | * bit. A value of 1 indicates that clock is enabled. | ||
| 51 | */ | ||
| 52 | static void am35xx_clk_find_idlest(struct clk *clk, | ||
| 53 | void __iomem **idlest_reg, | ||
| 54 | u8 *idlest_bit, | ||
| 55 | u8 *idlest_val) | ||
| 56 | { | ||
| 57 | *idlest_reg = (__force void __iomem *)(clk->enable_reg); | ||
| 58 | *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; | ||
| 59 | *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; | ||
| 60 | } | ||
| 61 | |||
| 62 | /** | ||
| 63 | * am35xx_clk_find_companion - find companion clock to @clk | ||
| 64 | * @clk: struct clk * to find the companion clock of | ||
| 65 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | ||
| 66 | * @other_bit: u8 ** to return the companion clock bit shift in | ||
| 67 | * | ||
| 68 | * Some clocks don't have companion clocks. For example, modules with | ||
| 69 | * only an interface clock (such as HECC) don't have a companion | ||
| 70 | * clock. Right now, this code relies on the hardware exporting a bit | ||
| 71 | * in the correct companion register that indicates that the | ||
| 72 | * nonexistent 'companion clock' is active. Future patches will | ||
| 73 | * associate this type of code with per-module data structures to | ||
| 74 | * avoid this issue, and remove the casts. No return value. | ||
| 75 | */ | ||
| 76 | static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, | ||
| 77 | u8 *other_bit) | ||
| 78 | { | ||
| 79 | *other_reg = (__force void __iomem *)(clk->enable_reg); | ||
| 80 | if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) | ||
| 81 | *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; | ||
| 82 | else | ||
| 83 | *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; | ||
| 84 | } | ||
| 85 | |||
| 86 | const struct clkops clkops_am35xx_ipss_module_wait = { | ||
| 87 | .enable = omap2_dflt_clk_enable, | ||
| 88 | .disable = omap2_dflt_clk_disable, | ||
| 89 | .find_idlest = am35xx_clk_find_idlest, | ||
| 90 | .find_companion = am35xx_clk_find_companion, | ||
| 91 | }; | ||
| 92 | |||
| 93 | /** | ||
| 94 | * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS | ||
| 95 | * @clk: struct clk * being enabled | ||
| 96 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
| 97 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
| 98 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
| 99 | * | ||
| 100 | * The IPSS target CM_IDLEST bit is at a different shift from the | ||
| 101 | * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg | ||
| 102 | * and @idlest_bit. No return value. | ||
| 103 | */ | ||
| 104 | static void am35xx_clk_ipss_find_idlest(struct clk *clk, | ||
| 105 | void __iomem **idlest_reg, | ||
| 106 | u8 *idlest_bit, | ||
| 107 | u8 *idlest_val) | ||
| 108 | { | ||
| 109 | u32 r; | ||
| 110 | |||
| 111 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | ||
| 112 | *idlest_reg = (__force void __iomem *)r; | ||
| 113 | *idlest_bit = AM35XX_ST_IPSS_SHIFT; | ||
| 114 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
| 115 | } | ||
| 116 | |||
| 117 | const struct clkops clkops_am35xx_ipss_wait = { | ||
| 118 | .enable = omap2_dflt_clk_enable, | ||
| 119 | .disable = omap2_dflt_clk_disable, | ||
| 120 | .find_idlest = am35xx_clk_ipss_find_idlest, | ||
| 121 | .find_companion = omap2_clk_dflt_find_companion, | ||
| 122 | }; | ||
| 123 | |||
| 124 | |||
diff --git a/arch/arm/mach-omap2/clock3517.h b/arch/arm/mach-omap2/clock3517.h new file mode 100644 index 000000000000..ca5e5a64c2e2 --- /dev/null +++ b/arch/arm/mach-omap2/clock3517.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3517/3505 clock function prototypes and macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3517_H | ||
| 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK3517_H | ||
| 10 | |||
| 11 | extern const struct clkops clkops_am35xx_ipss_module_wait; | ||
| 12 | extern const struct clkops clkops_am35xx_ipss_wait; | ||
| 13 | |||
| 14 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c new file mode 100644 index 000000000000..0c5e25ed8879 --- /dev/null +++ b/arch/arm/mach-omap2/clock36xx.c | |||
| @@ -0,0 +1,72 @@ | |||
| 1 | /* | ||
| 2 | * OMAP36xx-specific clkops | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Mike Turquette | ||
| 8 | * Vijaykumar GN | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Parts of this code are based on code written by | ||
| 12 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, | ||
| 13 | * Russell King | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | #undef DEBUG | ||
| 20 | |||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <plat/clock.h> | ||
| 26 | |||
| 27 | #include "clock.h" | ||
| 28 | #include "clock36xx.h" | ||
| 29 | |||
| 30 | |||
| 31 | /** | ||
| 32 | * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering | ||
| 33 | * from HSDivider PWRDN problem Implements Errata ID: i556. | ||
| 34 | * @clk: DPLL output struct clk | ||
| 35 | * | ||
| 36 | * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, | ||
| 37 | * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset | ||
| 38 | * valueafter their respective PWRDN bits are set. Any dummy write | ||
| 39 | * (Any other value different from the Read value) to the | ||
| 40 | * corresponding CM_CLKSEL register will refresh the dividers. | ||
| 41 | */ | ||
| 42 | static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) | ||
| 43 | { | ||
| 44 | u32 dummy_v, orig_v, clksel_shift; | ||
| 45 | int ret; | ||
| 46 | |||
| 47 | /* Clear PWRDN bit of HSDIVIDER */ | ||
| 48 | ret = omap2_dflt_clk_enable(clk); | ||
| 49 | |||
| 50 | /* Restore the dividers */ | ||
| 51 | if (!ret) { | ||
| 52 | clksel_shift = __ffs(clk->parent->clksel_mask); | ||
| 53 | orig_v = __raw_readl(clk->parent->clksel_reg); | ||
| 54 | dummy_v = orig_v; | ||
| 55 | |||
| 56 | /* Write any other value different from the Read value */ | ||
| 57 | dummy_v ^= (1 << clksel_shift); | ||
| 58 | __raw_writel(dummy_v, clk->parent->clksel_reg); | ||
| 59 | |||
| 60 | /* Write the original divider */ | ||
| 61 | __raw_writel(orig_v, clk->parent->clksel_reg); | ||
| 62 | } | ||
| 63 | |||
| 64 | return ret; | ||
| 65 | } | ||
| 66 | |||
| 67 | const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { | ||
| 68 | .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, | ||
| 69 | .disable = omap2_dflt_clk_disable, | ||
| 70 | .find_companion = omap2_clk_dflt_find_companion, | ||
| 71 | .find_idlest = omap2_clk_dflt_find_idlest, | ||
| 72 | }; | ||
diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h new file mode 100644 index 000000000000..a7dee5bc6364 --- /dev/null +++ b/arch/arm/mach-omap2/clock36xx.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * OMAP36xx clock function prototypes and macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H | ||
| 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H | ||
| 10 | |||
| 11 | extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c new file mode 100644 index 000000000000..a447c4d2c28a --- /dev/null +++ b/arch/arm/mach-omap2/clock3xxx.c | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3-specific clock framework functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley | ||
| 8 | * Jouni Högander | ||
| 9 | * | ||
| 10 | * Parts of this code are based on code written by | ||
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | #undef DEBUG | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | |||
| 26 | #include "clock.h" | ||
| 27 | #include "clock3xxx.h" | ||
| 28 | #include "prm.h" | ||
| 29 | #include "prm-regbits-34xx.h" | ||
| 30 | #include "cm.h" | ||
| 31 | #include "cm-regbits-34xx.h" | ||
| 32 | |||
| 33 | /* | ||
| 34 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | ||
| 35 | * that are sourced by DPLL5, and both of these require this clock | ||
| 36 | * to be at 120 MHz for proper operation. | ||
| 37 | */ | ||
| 38 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | ||
| 39 | |||
| 40 | /* needed by omap3_core_dpll_m2_set_rate() */ | ||
| 41 | struct clk *sdrc_ick_p, *arm_fck_p; | ||
| 42 | |||
| 43 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | ||
| 44 | { | ||
| 45 | /* | ||
| 46 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | ||
| 47 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | ||
| 48 | * on DPLL4. | ||
| 49 | */ | ||
| 50 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
| 51 | pr_err("clock: DPLL4 cannot change rate due to " | ||
| 52 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | ||
| 53 | return -EINVAL; | ||
| 54 | } | ||
| 55 | |||
| 56 | return omap3_noncore_dpll_set_rate(clk, rate); | ||
| 57 | } | ||
| 58 | |||
| 59 | void __init omap3_clk_lock_dpll5(void) | ||
| 60 | { | ||
| 61 | struct clk *dpll5_clk; | ||
| 62 | struct clk *dpll5_m2_clk; | ||
| 63 | |||
| 64 | dpll5_clk = clk_get(NULL, "dpll5_ck"); | ||
| 65 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); | ||
| 66 | clk_enable(dpll5_clk); | ||
| 67 | |||
| 68 | /* Enable autoidle to allow it to enter low power bypass */ | ||
| 69 | omap3_dpll_allow_idle(dpll5_clk); | ||
| 70 | |||
| 71 | /* Program dpll5_m2_clk divider for no division */ | ||
| 72 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); | ||
| 73 | clk_enable(dpll5_m2_clk); | ||
| 74 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); | ||
| 75 | |||
| 76 | clk_disable(dpll5_m2_clk); | ||
| 77 | clk_disable(dpll5_clk); | ||
| 78 | return; | ||
| 79 | } | ||
| 80 | |||
| 81 | /* Common clock code */ | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Switch the MPU rate if specified on cmdline. We cannot do this | ||
| 85 | * early until cmdline is parsed. XXX This should be removed from the | ||
| 86 | * clock code and handled by the OPP layer code in the near future. | ||
| 87 | */ | ||
| 88 | static int __init omap3xxx_clk_arch_init(void) | ||
| 89 | { | ||
| 90 | int ret; | ||
| 91 | |||
| 92 | if (!cpu_is_omap34xx()) | ||
| 93 | return 0; | ||
| 94 | |||
| 95 | ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); | ||
| 96 | if (!ret) | ||
| 97 | omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck"); | ||
| 98 | |||
| 99 | return ret; | ||
| 100 | } | ||
| 101 | |||
| 102 | arch_initcall(omap3xxx_clk_arch_init); | ||
| 103 | |||
| 104 | |||
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h new file mode 100644 index 000000000000..8bbeeaf399e2 --- /dev/null +++ b/arch/arm/mach-omap2/clock3xxx.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3-common clock function prototypes and macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H | ||
| 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H | ||
| 10 | |||
| 11 | int omap3xxx_clk_init(void); | ||
| 12 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | ||
| 13 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
| 14 | void omap3_clk_lock_dpll5(void); | ||
| 15 | |||
| 16 | extern struct clk *sdrc_ick_p; | ||
| 17 | extern struct clk *arm_fck_p; | ||
| 18 | |||
| 19 | extern const struct clkops clkops_noncore_dpll_ops; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 74930e3158e3..d5153b6bd6cb 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP3 clock data | 2 | * OMAP3 clock data |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander | 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
| @@ -16,15 +16,19 @@ | |||
| 16 | * to be requested from drivers directly. | 16 | * to be requested from drivers directly. |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
| 21 | #include <linux/clk.h> | 20 | #include <linux/clk.h> |
| 21 | #include <linux/list.h> | ||
| 22 | 22 | ||
| 23 | #include <plat/control.h> | 23 | #include <plat/control.h> |
| 24 | #include <plat/clkdev_omap.h> | 24 | #include <plat/clkdev_omap.h> |
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | #include "clock3xxx.h" | ||
| 27 | #include "clock34xx.h" | 28 | #include "clock34xx.h" |
| 29 | #include "clock36xx.h" | ||
| 30 | #include "clock3517.h" | ||
| 31 | |||
| 28 | #include "cm.h" | 32 | #include "cm.h" |
| 29 | #include "cm-regbits-34xx.h" | 33 | #include "cm-regbits-34xx.h" |
| 30 | #include "prm.h" | 34 | #include "prm.h" |
| @@ -37,7 +41,8 @@ | |||
| 37 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR | 41 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR |
| 38 | 42 | ||
| 39 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | 43 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
| 40 | #define OMAP3_MAX_DPLL_MULT 2048 | 44 | #define OMAP3_MAX_DPLL_MULT 2047 |
| 45 | #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 | ||
| 41 | #define OMAP3_MAX_DPLL_DIV 128 | 46 | #define OMAP3_MAX_DPLL_DIV 128 |
| 42 | 47 | ||
| 43 | /* | 48 | /* |
| @@ -59,14 +64,12 @@ static struct clk omap_32k_fck = { | |||
| 59 | .name = "omap_32k_fck", | 64 | .name = "omap_32k_fck", |
| 60 | .ops = &clkops_null, | 65 | .ops = &clkops_null, |
| 61 | .rate = 32768, | 66 | .rate = 32768, |
| 62 | .flags = RATE_FIXED, | ||
| 63 | }; | 67 | }; |
| 64 | 68 | ||
| 65 | static struct clk secure_32k_fck = { | 69 | static struct clk secure_32k_fck = { |
| 66 | .name = "secure_32k_fck", | 70 | .name = "secure_32k_fck", |
| 67 | .ops = &clkops_null, | 71 | .ops = &clkops_null, |
| 68 | .rate = 32768, | 72 | .rate = 32768, |
| 69 | .flags = RATE_FIXED, | ||
| 70 | }; | 73 | }; |
| 71 | 74 | ||
| 72 | /* Virtual source clocks for osc_sys_ck */ | 75 | /* Virtual source clocks for osc_sys_ck */ |
| @@ -74,42 +77,36 @@ static struct clk virt_12m_ck = { | |||
| 74 | .name = "virt_12m_ck", | 77 | .name = "virt_12m_ck", |
| 75 | .ops = &clkops_null, | 78 | .ops = &clkops_null, |
| 76 | .rate = 12000000, | 79 | .rate = 12000000, |
| 77 | .flags = RATE_FIXED, | ||
| 78 | }; | 80 | }; |
| 79 | 81 | ||
| 80 | static struct clk virt_13m_ck = { | 82 | static struct clk virt_13m_ck = { |
| 81 | .name = "virt_13m_ck", | 83 | .name = "virt_13m_ck", |
| 82 | .ops = &clkops_null, | 84 | .ops = &clkops_null, |
| 83 | .rate = 13000000, | 85 | .rate = 13000000, |
| 84 | .flags = RATE_FIXED, | ||
| 85 | }; | 86 | }; |
| 86 | 87 | ||
| 87 | static struct clk virt_16_8m_ck = { | 88 | static struct clk virt_16_8m_ck = { |
| 88 | .name = "virt_16_8m_ck", | 89 | .name = "virt_16_8m_ck", |
| 89 | .ops = &clkops_null, | 90 | .ops = &clkops_null, |
| 90 | .rate = 16800000, | 91 | .rate = 16800000, |
| 91 | .flags = RATE_FIXED, | ||
| 92 | }; | 92 | }; |
| 93 | 93 | ||
| 94 | static struct clk virt_19_2m_ck = { | 94 | static struct clk virt_19_2m_ck = { |
| 95 | .name = "virt_19_2m_ck", | 95 | .name = "virt_19_2m_ck", |
| 96 | .ops = &clkops_null, | 96 | .ops = &clkops_null, |
| 97 | .rate = 19200000, | 97 | .rate = 19200000, |
| 98 | .flags = RATE_FIXED, | ||
| 99 | }; | 98 | }; |
| 100 | 99 | ||
| 101 | static struct clk virt_26m_ck = { | 100 | static struct clk virt_26m_ck = { |
| 102 | .name = "virt_26m_ck", | 101 | .name = "virt_26m_ck", |
| 103 | .ops = &clkops_null, | 102 | .ops = &clkops_null, |
| 104 | .rate = 26000000, | 103 | .rate = 26000000, |
| 105 | .flags = RATE_FIXED, | ||
| 106 | }; | 104 | }; |
| 107 | 105 | ||
| 108 | static struct clk virt_38_4m_ck = { | 106 | static struct clk virt_38_4m_ck = { |
| 109 | .name = "virt_38_4m_ck", | 107 | .name = "virt_38_4m_ck", |
| 110 | .ops = &clkops_null, | 108 | .ops = &clkops_null, |
| 111 | .rate = 38400000, | 109 | .rate = 38400000, |
| 112 | .flags = RATE_FIXED, | ||
| 113 | }; | 110 | }; |
| 114 | 111 | ||
| 115 | static const struct clksel_rate osc_sys_12m_rates[] = { | 112 | static const struct clksel_rate osc_sys_12m_rates[] = { |
| @@ -162,7 +159,6 @@ static struct clk osc_sys_ck = { | |||
| 162 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | 159 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 163 | .clksel = osc_sys_clksel, | 160 | .clksel = osc_sys_clksel, |
| 164 | /* REVISIT: deal with autoextclkmode? */ | 161 | /* REVISIT: deal with autoextclkmode? */ |
| 165 | .flags = RATE_FIXED, | ||
| 166 | .recalc = &omap2_clksel_recalc, | 162 | .recalc = &omap2_clksel_recalc, |
| 167 | }; | 163 | }; |
| 168 | 164 | ||
| @@ -236,6 +232,42 @@ static const struct clksel_rate div16_dpll_rates[] = { | |||
| 236 | { .div = 0 } | 232 | { .div = 0 } |
| 237 | }; | 233 | }; |
| 238 | 234 | ||
| 235 | static const struct clksel_rate div32_dpll4_rates_3630[] = { | ||
| 236 | { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
| 237 | { .div = 2, .val = 2, .flags = RATE_IN_36XX }, | ||
| 238 | { .div = 3, .val = 3, .flags = RATE_IN_36XX }, | ||
| 239 | { .div = 4, .val = 4, .flags = RATE_IN_36XX }, | ||
| 240 | { .div = 5, .val = 5, .flags = RATE_IN_36XX }, | ||
| 241 | { .div = 6, .val = 6, .flags = RATE_IN_36XX }, | ||
| 242 | { .div = 7, .val = 7, .flags = RATE_IN_36XX }, | ||
| 243 | { .div = 8, .val = 8, .flags = RATE_IN_36XX }, | ||
| 244 | { .div = 9, .val = 9, .flags = RATE_IN_36XX }, | ||
| 245 | { .div = 10, .val = 10, .flags = RATE_IN_36XX }, | ||
| 246 | { .div = 11, .val = 11, .flags = RATE_IN_36XX }, | ||
| 247 | { .div = 12, .val = 12, .flags = RATE_IN_36XX }, | ||
| 248 | { .div = 13, .val = 13, .flags = RATE_IN_36XX }, | ||
| 249 | { .div = 14, .val = 14, .flags = RATE_IN_36XX }, | ||
| 250 | { .div = 15, .val = 15, .flags = RATE_IN_36XX }, | ||
| 251 | { .div = 16, .val = 16, .flags = RATE_IN_36XX }, | ||
| 252 | { .div = 17, .val = 17, .flags = RATE_IN_36XX }, | ||
| 253 | { .div = 18, .val = 18, .flags = RATE_IN_36XX }, | ||
| 254 | { .div = 19, .val = 19, .flags = RATE_IN_36XX }, | ||
| 255 | { .div = 20, .val = 20, .flags = RATE_IN_36XX }, | ||
| 256 | { .div = 21, .val = 21, .flags = RATE_IN_36XX }, | ||
| 257 | { .div = 22, .val = 22, .flags = RATE_IN_36XX }, | ||
| 258 | { .div = 23, .val = 23, .flags = RATE_IN_36XX }, | ||
| 259 | { .div = 24, .val = 24, .flags = RATE_IN_36XX }, | ||
| 260 | { .div = 25, .val = 25, .flags = RATE_IN_36XX }, | ||
| 261 | { .div = 26, .val = 26, .flags = RATE_IN_36XX }, | ||
| 262 | { .div = 27, .val = 27, .flags = RATE_IN_36XX }, | ||
| 263 | { .div = 28, .val = 28, .flags = RATE_IN_36XX }, | ||
| 264 | { .div = 29, .val = 29, .flags = RATE_IN_36XX }, | ||
| 265 | { .div = 30, .val = 30, .flags = RATE_IN_36XX }, | ||
| 266 | { .div = 31, .val = 31, .flags = RATE_IN_36XX }, | ||
| 267 | { .div = 32, .val = 32, .flags = RATE_IN_36XX }, | ||
| 268 | { .div = 0 } | ||
| 269 | }; | ||
| 270 | |||
| 239 | /* DPLL1 */ | 271 | /* DPLL1 */ |
| 240 | /* MPU clock source */ | 272 | /* MPU clock source */ |
| 241 | /* Type: DPLL */ | 273 | /* Type: DPLL */ |
| @@ -337,7 +369,7 @@ static struct dpll_data dpll2_dd = { | |||
| 337 | 369 | ||
| 338 | static struct clk dpll2_ck = { | 370 | static struct clk dpll2_ck = { |
| 339 | .name = "dpll2_ck", | 371 | .name = "dpll2_ck", |
| 340 | .ops = &clkops_noncore_dpll_ops, | 372 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 341 | .parent = &sys_ck, | 373 | .parent = &sys_ck, |
| 342 | .dpll_data = &dpll2_dd, | 374 | .dpll_data = &dpll2_dd, |
| 343 | .round_rate = &omap2_dpll_round_rate, | 375 | .round_rate = &omap2_dpll_round_rate, |
| @@ -529,7 +561,8 @@ static struct clk emu_core_alwon_ck = { | |||
| 529 | /* DPLL4 */ | 561 | /* DPLL4 */ |
| 530 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | 562 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ |
| 531 | /* Type: DPLL */ | 563 | /* Type: DPLL */ |
| 532 | static struct dpll_data dpll4_dd = { | 564 | static struct dpll_data dpll4_dd; |
| 565 | static struct dpll_data dpll4_dd_34xx __initdata = { | ||
| 533 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | 566 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 534 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | 567 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 535 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | 568 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
| @@ -552,9 +585,32 @@ static struct dpll_data dpll4_dd = { | |||
| 552 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 585 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 553 | }; | 586 | }; |
| 554 | 587 | ||
| 588 | static struct dpll_data dpll4_dd_3630 __initdata = { | ||
| 589 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | ||
| 590 | .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, | ||
| 591 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | ||
| 592 | .clk_bypass = &sys_ck, | ||
| 593 | .clk_ref = &sys_ck, | ||
| 594 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 595 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | ||
| 596 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | ||
| 597 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | ||
| 598 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
| 599 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | ||
| 600 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | ||
| 601 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | ||
| 602 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 603 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 604 | .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, | ||
| 605 | .min_divider = 1, | ||
| 606 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
| 607 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE, | ||
| 608 | .flags = DPLL_J_TYPE | ||
| 609 | }; | ||
| 610 | |||
| 555 | static struct clk dpll4_ck = { | 611 | static struct clk dpll4_ck = { |
| 556 | .name = "dpll4_ck", | 612 | .name = "dpll4_ck", |
| 557 | .ops = &clkops_noncore_dpll_ops, | 613 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 558 | .parent = &sys_ck, | 614 | .parent = &sys_ck, |
| 559 | .dpll_data = &dpll4_dd, | 615 | .dpll_data = &dpll4_dd, |
| 560 | .round_rate = &omap2_dpll_round_rate, | 616 | .round_rate = &omap2_dpll_round_rate, |
| @@ -581,8 +637,15 @@ static const struct clksel div16_dpll4_clksel[] = { | |||
| 581 | { .parent = NULL } | 637 | { .parent = NULL } |
| 582 | }; | 638 | }; |
| 583 | 639 | ||
| 640 | static const struct clksel div32_dpll4_clksel[] = { | ||
| 641 | { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 }, | ||
| 642 | { .parent = NULL } | ||
| 643 | }; | ||
| 644 | |||
| 584 | /* This virtual clock is the source for dpll4_m2x2_ck */ | 645 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
| 585 | static struct clk dpll4_m2_ck = { | 646 | static struct clk dpll4_m2_ck; |
| 647 | |||
| 648 | static struct clk dpll4_m2_ck_34xx __initdata = { | ||
| 586 | .name = "dpll4_m2_ck", | 649 | .name = "dpll4_m2_ck", |
| 587 | .ops = &clkops_null, | 650 | .ops = &clkops_null, |
| 588 | .parent = &dpll4_ck, | 651 | .parent = &dpll4_ck, |
| @@ -594,6 +657,18 @@ static struct clk dpll4_m2_ck = { | |||
| 594 | .recalc = &omap2_clksel_recalc, | 657 | .recalc = &omap2_clksel_recalc, |
| 595 | }; | 658 | }; |
| 596 | 659 | ||
| 660 | static struct clk dpll4_m2_ck_3630 __initdata = { | ||
| 661 | .name = "dpll4_m2_ck", | ||
| 662 | .ops = &clkops_null, | ||
| 663 | .parent = &dpll4_ck, | ||
| 664 | .init = &omap2_init_clksel_parent, | ||
| 665 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | ||
| 666 | .clksel_mask = OMAP3630_DIV_96M_MASK, | ||
| 667 | .clksel = div32_dpll4_clksel, | ||
| 668 | .clkdm_name = "dpll4_clkdm", | ||
| 669 | .recalc = &omap2_clksel_recalc, | ||
| 670 | }; | ||
| 671 | |||
| 597 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 672 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 598 | static struct clk dpll4_m2x2_ck = { | 673 | static struct clk dpll4_m2x2_ck = { |
| 599 | .name = "dpll4_m2x2_ck", | 674 | .name = "dpll4_m2x2_ck", |
| @@ -612,18 +687,24 @@ static struct clk dpll4_m2x2_ck = { | |||
| 612 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and | 687 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and |
| 613 | * CM_96K_(F)CLK. | 688 | * CM_96K_(F)CLK. |
| 614 | */ | 689 | */ |
| 615 | static struct clk omap_96m_alwon_fck = { | 690 | |
| 616 | .name = "omap_96m_alwon_fck", | 691 | /* Adding 192MHz Clock node needed by SGX */ |
| 692 | static struct clk omap_192m_alwon_fck = { | ||
| 693 | .name = "omap_192m_alwon_fck", | ||
| 617 | .ops = &clkops_null, | 694 | .ops = &clkops_null, |
| 618 | .parent = &dpll4_m2x2_ck, | 695 | .parent = &dpll4_m2x2_ck, |
| 619 | .recalc = &followparent_recalc, | 696 | .recalc = &followparent_recalc, |
| 620 | }; | 697 | }; |
| 621 | 698 | ||
| 622 | static struct clk cm_96m_fck = { | 699 | static const struct clksel_rate omap_96m_alwon_fck_rates[] = { |
| 623 | .name = "cm_96m_fck", | 700 | { .div = 1, .val = 1, .flags = RATE_IN_36XX }, |
| 624 | .ops = &clkops_null, | 701 | { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, |
| 625 | .parent = &omap_96m_alwon_fck, | 702 | { .div = 0 } |
| 626 | .recalc = &followparent_recalc, | 703 | }; |
| 704 | |||
| 705 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | ||
| 706 | { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, | ||
| 707 | { .parent = NULL } | ||
| 627 | }; | 708 | }; |
| 628 | 709 | ||
| 629 | static const struct clksel_rate omap_96m_dpll_rates[] = { | 710 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
| @@ -636,6 +717,31 @@ static const struct clksel_rate omap_96m_sys_rates[] = { | |||
| 636 | { .div = 0 } | 717 | { .div = 0 } |
| 637 | }; | 718 | }; |
| 638 | 719 | ||
| 720 | static struct clk omap_96m_alwon_fck = { | ||
| 721 | .name = "omap_96m_alwon_fck", | ||
| 722 | .ops = &clkops_null, | ||
| 723 | .parent = &dpll4_m2x2_ck, | ||
| 724 | .recalc = &followparent_recalc, | ||
| 725 | }; | ||
| 726 | |||
| 727 | static struct clk omap_96m_alwon_fck_3630 = { | ||
| 728 | .name = "omap_96m_alwon_fck", | ||
| 729 | .parent = &omap_192m_alwon_fck, | ||
| 730 | .init = &omap2_init_clksel_parent, | ||
| 731 | .ops = &clkops_null, | ||
| 732 | .recalc = &omap2_clksel_recalc, | ||
| 733 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 734 | .clksel_mask = OMAP3630_CLKSEL_96M_MASK, | ||
| 735 | .clksel = omap_96m_alwon_fck_clksel | ||
| 736 | }; | ||
| 737 | |||
| 738 | static struct clk cm_96m_fck = { | ||
| 739 | .name = "cm_96m_fck", | ||
| 740 | .ops = &clkops_null, | ||
| 741 | .parent = &omap_96m_alwon_fck, | ||
| 742 | .recalc = &followparent_recalc, | ||
| 743 | }; | ||
| 744 | |||
| 639 | static const struct clksel omap_96m_fck_clksel[] = { | 745 | static const struct clksel omap_96m_fck_clksel[] = { |
| 640 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | 746 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, |
| 641 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | 747 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, |
| @@ -654,7 +760,9 @@ static struct clk omap_96m_fck = { | |||
| 654 | }; | 760 | }; |
| 655 | 761 | ||
| 656 | /* This virtual clock is the source for dpll4_m3x2_ck */ | 762 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
| 657 | static struct clk dpll4_m3_ck = { | 763 | static struct clk dpll4_m3_ck; |
| 764 | |||
| 765 | static struct clk dpll4_m3_ck_34xx __initdata = { | ||
| 658 | .name = "dpll4_m3_ck", | 766 | .name = "dpll4_m3_ck", |
| 659 | .ops = &clkops_null, | 767 | .ops = &clkops_null, |
| 660 | .parent = &dpll4_ck, | 768 | .parent = &dpll4_ck, |
| @@ -666,6 +774,18 @@ static struct clk dpll4_m3_ck = { | |||
| 666 | .recalc = &omap2_clksel_recalc, | 774 | .recalc = &omap2_clksel_recalc, |
| 667 | }; | 775 | }; |
| 668 | 776 | ||
| 777 | static struct clk dpll4_m3_ck_3630 __initdata = { | ||
| 778 | .name = "dpll4_m3_ck", | ||
| 779 | .ops = &clkops_null, | ||
| 780 | .parent = &dpll4_ck, | ||
| 781 | .init = &omap2_init_clksel_parent, | ||
| 782 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
| 783 | .clksel_mask = OMAP3630_CLKSEL_TV_MASK, | ||
| 784 | .clksel = div32_dpll4_clksel, | ||
| 785 | .clkdm_name = "dpll4_clkdm", | ||
| 786 | .recalc = &omap2_clksel_recalc, | ||
| 787 | }; | ||
| 788 | |||
| 669 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 789 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 670 | static struct clk dpll4_m3x2_ck = { | 790 | static struct clk dpll4_m3x2_ck = { |
| 671 | .name = "dpll4_m3x2_ck", | 791 | .name = "dpll4_m3x2_ck", |
| @@ -735,11 +855,13 @@ static struct clk omap_12m_fck = { | |||
| 735 | .ops = &clkops_null, | 855 | .ops = &clkops_null, |
| 736 | .parent = &omap_48m_fck, | 856 | .parent = &omap_48m_fck, |
| 737 | .fixed_div = 4, | 857 | .fixed_div = 4, |
| 738 | .recalc = &omap2_fixed_divisor_recalc, | 858 | .recalc = &omap_fixed_divisor_recalc, |
| 739 | }; | 859 | }; |
| 740 | 860 | ||
| 741 | /* This virstual clock is the source for dpll4_m4x2_ck */ | 861 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
| 742 | static struct clk dpll4_m4_ck = { | 862 | static struct clk dpll4_m4_ck; |
| 863 | |||
| 864 | static struct clk dpll4_m4_ck_34xx __initdata = { | ||
| 743 | .name = "dpll4_m4_ck", | 865 | .name = "dpll4_m4_ck", |
| 744 | .ops = &clkops_null, | 866 | .ops = &clkops_null, |
| 745 | .parent = &dpll4_ck, | 867 | .parent = &dpll4_ck, |
| @@ -753,6 +875,20 @@ static struct clk dpll4_m4_ck = { | |||
| 753 | .round_rate = &omap2_clksel_round_rate, | 875 | .round_rate = &omap2_clksel_round_rate, |
| 754 | }; | 876 | }; |
| 755 | 877 | ||
| 878 | static struct clk dpll4_m4_ck_3630 __initdata = { | ||
| 879 | .name = "dpll4_m4_ck", | ||
| 880 | .ops = &clkops_null, | ||
| 881 | .parent = &dpll4_ck, | ||
| 882 | .init = &omap2_init_clksel_parent, | ||
| 883 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
| 884 | .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, | ||
| 885 | .clksel = div32_dpll4_clksel, | ||
| 886 | .clkdm_name = "dpll4_clkdm", | ||
| 887 | .recalc = &omap2_clksel_recalc, | ||
| 888 | .set_rate = &omap2_clksel_set_rate, | ||
| 889 | .round_rate = &omap2_clksel_round_rate, | ||
| 890 | }; | ||
| 891 | |||
| 756 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 892 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 757 | static struct clk dpll4_m4x2_ck = { | 893 | static struct clk dpll4_m4x2_ck = { |
| 758 | .name = "dpll4_m4x2_ck", | 894 | .name = "dpll4_m4x2_ck", |
| @@ -766,7 +902,9 @@ static struct clk dpll4_m4x2_ck = { | |||
| 766 | }; | 902 | }; |
| 767 | 903 | ||
| 768 | /* This virtual clock is the source for dpll4_m5x2_ck */ | 904 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
| 769 | static struct clk dpll4_m5_ck = { | 905 | static struct clk dpll4_m5_ck; |
| 906 | |||
| 907 | static struct clk dpll4_m5_ck_34xx __initdata = { | ||
| 770 | .name = "dpll4_m5_ck", | 908 | .name = "dpll4_m5_ck", |
| 771 | .ops = &clkops_null, | 909 | .ops = &clkops_null, |
| 772 | .parent = &dpll4_ck, | 910 | .parent = &dpll4_ck, |
| @@ -780,6 +918,20 @@ static struct clk dpll4_m5_ck = { | |||
| 780 | .recalc = &omap2_clksel_recalc, | 918 | .recalc = &omap2_clksel_recalc, |
| 781 | }; | 919 | }; |
| 782 | 920 | ||
| 921 | static struct clk dpll4_m5_ck_3630 __initdata = { | ||
| 922 | .name = "dpll4_m5_ck", | ||
| 923 | .ops = &clkops_null, | ||
| 924 | .parent = &dpll4_ck, | ||
| 925 | .init = &omap2_init_clksel_parent, | ||
| 926 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | ||
| 927 | .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, | ||
| 928 | .clksel = div32_dpll4_clksel, | ||
| 929 | .clkdm_name = "dpll4_clkdm", | ||
| 930 | .set_rate = &omap2_clksel_set_rate, | ||
| 931 | .round_rate = &omap2_clksel_round_rate, | ||
| 932 | .recalc = &omap2_clksel_recalc, | ||
| 933 | }; | ||
| 934 | |||
| 783 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 935 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 784 | static struct clk dpll4_m5x2_ck = { | 936 | static struct clk dpll4_m5x2_ck = { |
| 785 | .name = "dpll4_m5x2_ck", | 937 | .name = "dpll4_m5x2_ck", |
| @@ -793,7 +945,9 @@ static struct clk dpll4_m5x2_ck = { | |||
| 793 | }; | 945 | }; |
| 794 | 946 | ||
| 795 | /* This virtual clock is the source for dpll4_m6x2_ck */ | 947 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
| 796 | static struct clk dpll4_m6_ck = { | 948 | static struct clk dpll4_m6_ck; |
| 949 | |||
| 950 | static struct clk dpll4_m6_ck_34xx __initdata = { | ||
| 797 | .name = "dpll4_m6_ck", | 951 | .name = "dpll4_m6_ck", |
| 798 | .ops = &clkops_null, | 952 | .ops = &clkops_null, |
| 799 | .parent = &dpll4_ck, | 953 | .parent = &dpll4_ck, |
| @@ -805,6 +959,18 @@ static struct clk dpll4_m6_ck = { | |||
| 805 | .recalc = &omap2_clksel_recalc, | 959 | .recalc = &omap2_clksel_recalc, |
| 806 | }; | 960 | }; |
| 807 | 961 | ||
| 962 | static struct clk dpll4_m6_ck_3630 __initdata = { | ||
| 963 | .name = "dpll4_m6_ck", | ||
| 964 | .ops = &clkops_null, | ||
| 965 | .parent = &dpll4_ck, | ||
| 966 | .init = &omap2_init_clksel_parent, | ||
| 967 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 968 | .clksel_mask = OMAP3630_DIV_DPLL4_MASK, | ||
| 969 | .clksel = div32_dpll4_clksel, | ||
| 970 | .clkdm_name = "dpll4_clkdm", | ||
| 971 | .recalc = &omap2_clksel_recalc, | ||
| 972 | }; | ||
| 973 | |||
| 808 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 974 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 809 | static struct clk dpll4_m6x2_ck = { | 975 | static struct clk dpll4_m6x2_ck = { |
| 810 | .name = "dpll4_m6x2_ck", | 976 | .name = "dpll4_m6x2_ck", |
| @@ -854,7 +1020,7 @@ static struct dpll_data dpll5_dd = { | |||
| 854 | 1020 | ||
| 855 | static struct clk dpll5_ck = { | 1021 | static struct clk dpll5_ck = { |
| 856 | .name = "dpll5_ck", | 1022 | .name = "dpll5_ck", |
| 857 | .ops = &clkops_noncore_dpll_ops, | 1023 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 858 | .parent = &sys_ck, | 1024 | .parent = &sys_ck, |
| 859 | .dpll_data = &dpll5_dd, | 1025 | .dpll_data = &dpll5_dd, |
| 860 | .round_rate = &omap2_dpll_round_rate, | 1026 | .round_rate = &omap2_dpll_round_rate, |
| @@ -1166,12 +1332,24 @@ static struct clk gfx_cg2_ck = { | |||
| 1166 | /* SGX power domain - 3430ES2 only */ | 1332 | /* SGX power domain - 3430ES2 only */ |
| 1167 | 1333 | ||
| 1168 | static const struct clksel_rate sgx_core_rates[] = { | 1334 | static const struct clksel_rate sgx_core_rates[] = { |
| 1335 | { .div = 2, .val = 5, .flags = RATE_IN_36XX }, | ||
| 1169 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | 1336 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1170 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | 1337 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, |
| 1171 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | 1338 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, |
| 1172 | { .div = 0 }, | 1339 | { .div = 0 }, |
| 1173 | }; | 1340 | }; |
| 1174 | 1341 | ||
| 1342 | static const struct clksel_rate sgx_192m_rates[] = { | ||
| 1343 | { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
| 1344 | { .div = 0 }, | ||
| 1345 | }; | ||
| 1346 | |||
| 1347 | static const struct clksel_rate sgx_corex2_rates[] = { | ||
| 1348 | { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
| 1349 | { .div = 5, .val = 7, .flags = RATE_IN_36XX }, | ||
| 1350 | { .div = 0 }, | ||
| 1351 | }; | ||
| 1352 | |||
| 1175 | static const struct clksel_rate sgx_96m_rates[] = { | 1353 | static const struct clksel_rate sgx_96m_rates[] = { |
| 1176 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | 1354 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1177 | { .div = 0 }, | 1355 | { .div = 0 }, |
| @@ -1180,7 +1358,9 @@ static const struct clksel_rate sgx_96m_rates[] = { | |||
| 1180 | static const struct clksel sgx_clksel[] = { | 1358 | static const struct clksel sgx_clksel[] = { |
| 1181 | { .parent = &core_ck, .rates = sgx_core_rates }, | 1359 | { .parent = &core_ck, .rates = sgx_core_rates }, |
| 1182 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | 1360 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
| 1183 | { .parent = NULL }, | 1361 | { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, |
| 1362 | { .parent = &corex2_fck, .rates = sgx_corex2_rates }, | ||
| 1363 | { .parent = NULL } | ||
| 1184 | }; | 1364 | }; |
| 1185 | 1365 | ||
| 1186 | static struct clk sgx_fck = { | 1366 | static struct clk sgx_fck = { |
| @@ -1194,6 +1374,8 @@ static struct clk sgx_fck = { | |||
| 1194 | .clksel = sgx_clksel, | 1374 | .clksel = sgx_clksel, |
| 1195 | .clkdm_name = "sgx_clkdm", | 1375 | .clkdm_name = "sgx_clkdm", |
| 1196 | .recalc = &omap2_clksel_recalc, | 1376 | .recalc = &omap2_clksel_recalc, |
| 1377 | .set_rate = &omap2_clksel_set_rate, | ||
| 1378 | .round_rate = &omap2_clksel_round_rate | ||
| 1197 | }; | 1379 | }; |
| 1198 | 1380 | ||
| 1199 | static struct clk sgx_ick = { | 1381 | static struct clk sgx_ick = { |
| @@ -1320,9 +1502,8 @@ static struct clk core_96m_fck = { | |||
| 1320 | }; | 1502 | }; |
| 1321 | 1503 | ||
| 1322 | static struct clk mmchs3_fck = { | 1504 | static struct clk mmchs3_fck = { |
| 1323 | .name = "mmchs_fck", | 1505 | .name = "mmchs3_fck", |
| 1324 | .ops = &clkops_omap2_dflt_wait, | 1506 | .ops = &clkops_omap2_dflt_wait, |
| 1325 | .id = 2, | ||
| 1326 | .parent = &core_96m_fck, | 1507 | .parent = &core_96m_fck, |
| 1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1328 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1509 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| @@ -1331,9 +1512,8 @@ static struct clk mmchs3_fck = { | |||
| 1331 | }; | 1512 | }; |
| 1332 | 1513 | ||
| 1333 | static struct clk mmchs2_fck = { | 1514 | static struct clk mmchs2_fck = { |
| 1334 | .name = "mmchs_fck", | 1515 | .name = "mmchs2_fck", |
| 1335 | .ops = &clkops_omap2_dflt_wait, | 1516 | .ops = &clkops_omap2_dflt_wait, |
| 1336 | .id = 1, | ||
| 1337 | .parent = &core_96m_fck, | 1517 | .parent = &core_96m_fck, |
| 1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1339 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1519 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| @@ -1352,7 +1532,7 @@ static struct clk mspro_fck = { | |||
| 1352 | }; | 1532 | }; |
| 1353 | 1533 | ||
| 1354 | static struct clk mmchs1_fck = { | 1534 | static struct clk mmchs1_fck = { |
| 1355 | .name = "mmchs_fck", | 1535 | .name = "mmchs1_fck", |
| 1356 | .ops = &clkops_omap2_dflt_wait, | 1536 | .ops = &clkops_omap2_dflt_wait, |
| 1357 | .parent = &core_96m_fck, | 1537 | .parent = &core_96m_fck, |
| 1358 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1538 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1362,9 +1542,8 @@ static struct clk mmchs1_fck = { | |||
| 1362 | }; | 1542 | }; |
| 1363 | 1543 | ||
| 1364 | static struct clk i2c3_fck = { | 1544 | static struct clk i2c3_fck = { |
| 1365 | .name = "i2c_fck", | 1545 | .name = "i2c3_fck", |
| 1366 | .ops = &clkops_omap2_dflt_wait, | 1546 | .ops = &clkops_omap2_dflt_wait, |
| 1367 | .id = 3, | ||
| 1368 | .parent = &core_96m_fck, | 1547 | .parent = &core_96m_fck, |
| 1369 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1548 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1370 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1549 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| @@ -1373,9 +1552,8 @@ static struct clk i2c3_fck = { | |||
| 1373 | }; | 1552 | }; |
| 1374 | 1553 | ||
| 1375 | static struct clk i2c2_fck = { | 1554 | static struct clk i2c2_fck = { |
| 1376 | .name = "i2c_fck", | 1555 | .name = "i2c2_fck", |
| 1377 | .ops = &clkops_omap2_dflt_wait, | 1556 | .ops = &clkops_omap2_dflt_wait, |
| 1378 | .id = 2, | ||
| 1379 | .parent = &core_96m_fck, | 1557 | .parent = &core_96m_fck, |
| 1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1558 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1381 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1559 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| @@ -1384,9 +1562,8 @@ static struct clk i2c2_fck = { | |||
| 1384 | }; | 1562 | }; |
| 1385 | 1563 | ||
| 1386 | static struct clk i2c1_fck = { | 1564 | static struct clk i2c1_fck = { |
| 1387 | .name = "i2c_fck", | 1565 | .name = "i2c1_fck", |
| 1388 | .ops = &clkops_omap2_dflt_wait, | 1566 | .ops = &clkops_omap2_dflt_wait, |
| 1389 | .id = 1, | ||
| 1390 | .parent = &core_96m_fck, | 1567 | .parent = &core_96m_fck, |
| 1391 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1568 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1392 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1569 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| @@ -1415,9 +1592,8 @@ static const struct clksel mcbsp_15_clksel[] = { | |||
| 1415 | }; | 1592 | }; |
| 1416 | 1593 | ||
| 1417 | static struct clk mcbsp5_fck = { | 1594 | static struct clk mcbsp5_fck = { |
| 1418 | .name = "mcbsp_fck", | 1595 | .name = "mcbsp5_fck", |
| 1419 | .ops = &clkops_omap2_dflt_wait, | 1596 | .ops = &clkops_omap2_dflt_wait, |
| 1420 | .id = 5, | ||
| 1421 | .init = &omap2_init_clksel_parent, | 1597 | .init = &omap2_init_clksel_parent, |
| 1422 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1598 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1423 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 1599 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| @@ -1429,9 +1605,8 @@ static struct clk mcbsp5_fck = { | |||
| 1429 | }; | 1605 | }; |
| 1430 | 1606 | ||
| 1431 | static struct clk mcbsp1_fck = { | 1607 | static struct clk mcbsp1_fck = { |
| 1432 | .name = "mcbsp_fck", | 1608 | .name = "mcbsp1_fck", |
| 1433 | .ops = &clkops_omap2_dflt_wait, | 1609 | .ops = &clkops_omap2_dflt_wait, |
| 1434 | .id = 1, | ||
| 1435 | .init = &omap2_init_clksel_parent, | 1610 | .init = &omap2_init_clksel_parent, |
| 1436 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1611 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1437 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 1612 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| @@ -1453,9 +1628,8 @@ static struct clk core_48m_fck = { | |||
| 1453 | }; | 1628 | }; |
| 1454 | 1629 | ||
| 1455 | static struct clk mcspi4_fck = { | 1630 | static struct clk mcspi4_fck = { |
| 1456 | .name = "mcspi_fck", | 1631 | .name = "mcspi4_fck", |
| 1457 | .ops = &clkops_omap2_dflt_wait, | 1632 | .ops = &clkops_omap2_dflt_wait, |
| 1458 | .id = 4, | ||
| 1459 | .parent = &core_48m_fck, | 1633 | .parent = &core_48m_fck, |
| 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1461 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1635 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| @@ -1463,9 +1637,8 @@ static struct clk mcspi4_fck = { | |||
| 1463 | }; | 1637 | }; |
| 1464 | 1638 | ||
| 1465 | static struct clk mcspi3_fck = { | 1639 | static struct clk mcspi3_fck = { |
| 1466 | .name = "mcspi_fck", | 1640 | .name = "mcspi3_fck", |
| 1467 | .ops = &clkops_omap2_dflt_wait, | 1641 | .ops = &clkops_omap2_dflt_wait, |
| 1468 | .id = 3, | ||
| 1469 | .parent = &core_48m_fck, | 1642 | .parent = &core_48m_fck, |
| 1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1471 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1644 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| @@ -1473,9 +1646,8 @@ static struct clk mcspi3_fck = { | |||
| 1473 | }; | 1646 | }; |
| 1474 | 1647 | ||
| 1475 | static struct clk mcspi2_fck = { | 1648 | static struct clk mcspi2_fck = { |
| 1476 | .name = "mcspi_fck", | 1649 | .name = "mcspi2_fck", |
| 1477 | .ops = &clkops_omap2_dflt_wait, | 1650 | .ops = &clkops_omap2_dflt_wait, |
| 1478 | .id = 2, | ||
| 1479 | .parent = &core_48m_fck, | 1651 | .parent = &core_48m_fck, |
| 1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1481 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1653 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| @@ -1483,9 +1655,8 @@ static struct clk mcspi2_fck = { | |||
| 1483 | }; | 1655 | }; |
| 1484 | 1656 | ||
| 1485 | static struct clk mcspi1_fck = { | 1657 | static struct clk mcspi1_fck = { |
| 1486 | .name = "mcspi_fck", | 1658 | .name = "mcspi1_fck", |
| 1487 | .ops = &clkops_omap2_dflt_wait, | 1659 | .ops = &clkops_omap2_dflt_wait, |
| 1488 | .id = 1, | ||
| 1489 | .parent = &core_48m_fck, | 1660 | .parent = &core_48m_fck, |
| 1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1661 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1491 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1662 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| @@ -1588,7 +1759,7 @@ static struct clk ssi_sst_fck_3430es1 = { | |||
| 1588 | .ops = &clkops_null, | 1759 | .ops = &clkops_null, |
| 1589 | .parent = &ssi_ssr_fck_3430es1, | 1760 | .parent = &ssi_ssr_fck_3430es1, |
| 1590 | .fixed_div = 2, | 1761 | .fixed_div = 2, |
| 1591 | .recalc = &omap2_fixed_divisor_recalc, | 1762 | .recalc = &omap_fixed_divisor_recalc, |
| 1592 | }; | 1763 | }; |
| 1593 | 1764 | ||
| 1594 | static struct clk ssi_sst_fck_3430es2 = { | 1765 | static struct clk ssi_sst_fck_3430es2 = { |
| @@ -1596,7 +1767,7 @@ static struct clk ssi_sst_fck_3430es2 = { | |||
| 1596 | .ops = &clkops_null, | 1767 | .ops = &clkops_null, |
| 1597 | .parent = &ssi_ssr_fck_3430es2, | 1768 | .parent = &ssi_ssr_fck_3430es2, |
| 1598 | .fixed_div = 2, | 1769 | .fixed_div = 2, |
| 1599 | .recalc = &omap2_fixed_divisor_recalc, | 1770 | .recalc = &omap_fixed_divisor_recalc, |
| 1600 | }; | 1771 | }; |
| 1601 | 1772 | ||
| 1602 | 1773 | ||
| @@ -1694,9 +1865,8 @@ static struct clk usbtll_ick = { | |||
| 1694 | }; | 1865 | }; |
| 1695 | 1866 | ||
| 1696 | static struct clk mmchs3_ick = { | 1867 | static struct clk mmchs3_ick = { |
| 1697 | .name = "mmchs_ick", | 1868 | .name = "mmchs3_ick", |
| 1698 | .ops = &clkops_omap2_dflt_wait, | 1869 | .ops = &clkops_omap2_dflt_wait, |
| 1699 | .id = 2, | ||
| 1700 | .parent = &core_l4_ick, | 1870 | .parent = &core_l4_ick, |
| 1701 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1871 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1702 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1872 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| @@ -1746,9 +1916,8 @@ static struct clk des2_ick = { | |||
| 1746 | }; | 1916 | }; |
| 1747 | 1917 | ||
| 1748 | static struct clk mmchs2_ick = { | 1918 | static struct clk mmchs2_ick = { |
| 1749 | .name = "mmchs_ick", | 1919 | .name = "mmchs2_ick", |
| 1750 | .ops = &clkops_omap2_dflt_wait, | 1920 | .ops = &clkops_omap2_dflt_wait, |
| 1751 | .id = 1, | ||
| 1752 | .parent = &core_l4_ick, | 1921 | .parent = &core_l4_ick, |
| 1753 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1754 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1923 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| @@ -1757,7 +1926,7 @@ static struct clk mmchs2_ick = { | |||
| 1757 | }; | 1926 | }; |
| 1758 | 1927 | ||
| 1759 | static struct clk mmchs1_ick = { | 1928 | static struct clk mmchs1_ick = { |
| 1760 | .name = "mmchs_ick", | 1929 | .name = "mmchs1_ick", |
| 1761 | .ops = &clkops_omap2_dflt_wait, | 1930 | .ops = &clkops_omap2_dflt_wait, |
| 1762 | .parent = &core_l4_ick, | 1931 | .parent = &core_l4_ick, |
| 1763 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -1787,9 +1956,8 @@ static struct clk hdq_ick = { | |||
| 1787 | }; | 1956 | }; |
| 1788 | 1957 | ||
| 1789 | static struct clk mcspi4_ick = { | 1958 | static struct clk mcspi4_ick = { |
| 1790 | .name = "mcspi_ick", | 1959 | .name = "mcspi4_ick", |
| 1791 | .ops = &clkops_omap2_dflt_wait, | 1960 | .ops = &clkops_omap2_dflt_wait, |
| 1792 | .id = 4, | ||
| 1793 | .parent = &core_l4_ick, | 1961 | .parent = &core_l4_ick, |
| 1794 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1795 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1963 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| @@ -1798,9 +1966,8 @@ static struct clk mcspi4_ick = { | |||
| 1798 | }; | 1966 | }; |
| 1799 | 1967 | ||
| 1800 | static struct clk mcspi3_ick = { | 1968 | static struct clk mcspi3_ick = { |
| 1801 | .name = "mcspi_ick", | 1969 | .name = "mcspi3_ick", |
| 1802 | .ops = &clkops_omap2_dflt_wait, | 1970 | .ops = &clkops_omap2_dflt_wait, |
| 1803 | .id = 3, | ||
| 1804 | .parent = &core_l4_ick, | 1971 | .parent = &core_l4_ick, |
| 1805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1806 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1973 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| @@ -1809,9 +1976,8 @@ static struct clk mcspi3_ick = { | |||
| 1809 | }; | 1976 | }; |
| 1810 | 1977 | ||
| 1811 | static struct clk mcspi2_ick = { | 1978 | static struct clk mcspi2_ick = { |
| 1812 | .name = "mcspi_ick", | 1979 | .name = "mcspi2_ick", |
| 1813 | .ops = &clkops_omap2_dflt_wait, | 1980 | .ops = &clkops_omap2_dflt_wait, |
| 1814 | .id = 2, | ||
| 1815 | .parent = &core_l4_ick, | 1981 | .parent = &core_l4_ick, |
| 1816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1982 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1817 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1983 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| @@ -1820,9 +1986,8 @@ static struct clk mcspi2_ick = { | |||
| 1820 | }; | 1986 | }; |
| 1821 | 1987 | ||
| 1822 | static struct clk mcspi1_ick = { | 1988 | static struct clk mcspi1_ick = { |
| 1823 | .name = "mcspi_ick", | 1989 | .name = "mcspi1_ick", |
| 1824 | .ops = &clkops_omap2_dflt_wait, | 1990 | .ops = &clkops_omap2_dflt_wait, |
| 1825 | .id = 1, | ||
| 1826 | .parent = &core_l4_ick, | 1991 | .parent = &core_l4_ick, |
| 1827 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1992 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1828 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1993 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| @@ -1831,9 +1996,8 @@ static struct clk mcspi1_ick = { | |||
| 1831 | }; | 1996 | }; |
| 1832 | 1997 | ||
| 1833 | static struct clk i2c3_ick = { | 1998 | static struct clk i2c3_ick = { |
| 1834 | .name = "i2c_ick", | 1999 | .name = "i2c3_ick", |
| 1835 | .ops = &clkops_omap2_dflt_wait, | 2000 | .ops = &clkops_omap2_dflt_wait, |
| 1836 | .id = 3, | ||
| 1837 | .parent = &core_l4_ick, | 2001 | .parent = &core_l4_ick, |
| 1838 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2002 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1839 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 2003 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| @@ -1842,9 +2006,8 @@ static struct clk i2c3_ick = { | |||
| 1842 | }; | 2006 | }; |
| 1843 | 2007 | ||
| 1844 | static struct clk i2c2_ick = { | 2008 | static struct clk i2c2_ick = { |
| 1845 | .name = "i2c_ick", | 2009 | .name = "i2c2_ick", |
| 1846 | .ops = &clkops_omap2_dflt_wait, | 2010 | .ops = &clkops_omap2_dflt_wait, |
| 1847 | .id = 2, | ||
| 1848 | .parent = &core_l4_ick, | 2011 | .parent = &core_l4_ick, |
| 1849 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2012 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1850 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 2013 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| @@ -1853,9 +2016,8 @@ static struct clk i2c2_ick = { | |||
| 1853 | }; | 2016 | }; |
| 1854 | 2017 | ||
| 1855 | static struct clk i2c1_ick = { | 2018 | static struct clk i2c1_ick = { |
| 1856 | .name = "i2c_ick", | 2019 | .name = "i2c1_ick", |
| 1857 | .ops = &clkops_omap2_dflt_wait, | 2020 | .ops = &clkops_omap2_dflt_wait, |
| 1858 | .id = 1, | ||
| 1859 | .parent = &core_l4_ick, | 2021 | .parent = &core_l4_ick, |
| 1860 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2022 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1861 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 2023 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| @@ -1904,9 +2066,8 @@ static struct clk gpt10_ick = { | |||
| 1904 | }; | 2066 | }; |
| 1905 | 2067 | ||
| 1906 | static struct clk mcbsp5_ick = { | 2068 | static struct clk mcbsp5_ick = { |
| 1907 | .name = "mcbsp_ick", | 2069 | .name = "mcbsp5_ick", |
| 1908 | .ops = &clkops_omap2_dflt_wait, | 2070 | .ops = &clkops_omap2_dflt_wait, |
| 1909 | .id = 5, | ||
| 1910 | .parent = &core_l4_ick, | 2071 | .parent = &core_l4_ick, |
| 1911 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2072 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1912 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 2073 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| @@ -1915,9 +2076,8 @@ static struct clk mcbsp5_ick = { | |||
| 1915 | }; | 2076 | }; |
| 1916 | 2077 | ||
| 1917 | static struct clk mcbsp1_ick = { | 2078 | static struct clk mcbsp1_ick = { |
| 1918 | .name = "mcbsp_ick", | 2079 | .name = "mcbsp1_ick", |
| 1919 | .ops = &clkops_omap2_dflt_wait, | 2080 | .ops = &clkops_omap2_dflt_wait, |
| 1920 | .id = 1, | ||
| 1921 | .parent = &core_l4_ick, | 2081 | .parent = &core_l4_ick, |
| 1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2082 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1923 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 2083 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| @@ -2712,9 +2872,8 @@ static struct clk gpt2_ick = { | |||
| 2712 | }; | 2872 | }; |
| 2713 | 2873 | ||
| 2714 | static struct clk mcbsp2_ick = { | 2874 | static struct clk mcbsp2_ick = { |
| 2715 | .name = "mcbsp_ick", | 2875 | .name = "mcbsp2_ick", |
| 2716 | .ops = &clkops_omap2_dflt_wait, | 2876 | .ops = &clkops_omap2_dflt_wait, |
| 2717 | .id = 2, | ||
| 2718 | .parent = &per_l4_ick, | 2877 | .parent = &per_l4_ick, |
| 2719 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2878 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2720 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2879 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| @@ -2723,9 +2882,8 @@ static struct clk mcbsp2_ick = { | |||
| 2723 | }; | 2882 | }; |
| 2724 | 2883 | ||
| 2725 | static struct clk mcbsp3_ick = { | 2884 | static struct clk mcbsp3_ick = { |
| 2726 | .name = "mcbsp_ick", | 2885 | .name = "mcbsp3_ick", |
| 2727 | .ops = &clkops_omap2_dflt_wait, | 2886 | .ops = &clkops_omap2_dflt_wait, |
| 2728 | .id = 3, | ||
| 2729 | .parent = &per_l4_ick, | 2887 | .parent = &per_l4_ick, |
| 2730 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2888 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2731 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2889 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| @@ -2734,9 +2892,8 @@ static struct clk mcbsp3_ick = { | |||
| 2734 | }; | 2892 | }; |
| 2735 | 2893 | ||
| 2736 | static struct clk mcbsp4_ick = { | 2894 | static struct clk mcbsp4_ick = { |
| 2737 | .name = "mcbsp_ick", | 2895 | .name = "mcbsp4_ick", |
| 2738 | .ops = &clkops_omap2_dflt_wait, | 2896 | .ops = &clkops_omap2_dflt_wait, |
| 2739 | .id = 4, | ||
| 2740 | .parent = &per_l4_ick, | 2897 | .parent = &per_l4_ick, |
| 2741 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2898 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2742 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2899 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| @@ -2751,9 +2908,8 @@ static const struct clksel mcbsp_234_clksel[] = { | |||
| 2751 | }; | 2908 | }; |
| 2752 | 2909 | ||
| 2753 | static struct clk mcbsp2_fck = { | 2910 | static struct clk mcbsp2_fck = { |
| 2754 | .name = "mcbsp_fck", | 2911 | .name = "mcbsp2_fck", |
| 2755 | .ops = &clkops_omap2_dflt_wait, | 2912 | .ops = &clkops_omap2_dflt_wait, |
| 2756 | .id = 2, | ||
| 2757 | .init = &omap2_init_clksel_parent, | 2913 | .init = &omap2_init_clksel_parent, |
| 2758 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2914 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2759 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2915 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| @@ -2765,9 +2921,8 @@ static struct clk mcbsp2_fck = { | |||
| 2765 | }; | 2921 | }; |
| 2766 | 2922 | ||
| 2767 | static struct clk mcbsp3_fck = { | 2923 | static struct clk mcbsp3_fck = { |
| 2768 | .name = "mcbsp_fck", | 2924 | .name = "mcbsp3_fck", |
| 2769 | .ops = &clkops_omap2_dflt_wait, | 2925 | .ops = &clkops_omap2_dflt_wait, |
| 2770 | .id = 3, | ||
| 2771 | .init = &omap2_init_clksel_parent, | 2926 | .init = &omap2_init_clksel_parent, |
| 2772 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2927 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2773 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2928 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| @@ -2779,9 +2934,8 @@ static struct clk mcbsp3_fck = { | |||
| 2779 | }; | 2934 | }; |
| 2780 | 2935 | ||
| 2781 | static struct clk mcbsp4_fck = { | 2936 | static struct clk mcbsp4_fck = { |
| 2782 | .name = "mcbsp_fck", | 2937 | .name = "mcbsp4_fck", |
| 2783 | .ops = &clkops_omap2_dflt_wait, | 2938 | .ops = &clkops_omap2_dflt_wait, |
| 2784 | .id = 4, | ||
| 2785 | .init = &omap2_init_clksel_parent, | 2939 | .init = &omap2_init_clksel_parent, |
| 2786 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2940 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2787 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2941 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| @@ -2983,144 +3137,251 @@ static struct clk wdt1_fck = { | |||
| 2983 | .recalc = &followparent_recalc, | 3137 | .recalc = &followparent_recalc, |
| 2984 | }; | 3138 | }; |
| 2985 | 3139 | ||
| 3140 | /* Clocks for AM35XX */ | ||
| 3141 | static struct clk ipss_ick = { | ||
| 3142 | .name = "ipss_ick", | ||
| 3143 | .ops = &clkops_am35xx_ipss_wait, | ||
| 3144 | .parent = &core_l3_ick, | ||
| 3145 | .clkdm_name = "core_l3_clkdm", | ||
| 3146 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 3147 | .enable_bit = AM35XX_EN_IPSS_SHIFT, | ||
| 3148 | .recalc = &followparent_recalc, | ||
| 3149 | }; | ||
| 3150 | |||
| 3151 | static struct clk emac_ick = { | ||
| 3152 | .name = "emac_ick", | ||
| 3153 | .ops = &clkops_am35xx_ipss_module_wait, | ||
| 3154 | .parent = &ipss_ick, | ||
| 3155 | .clkdm_name = "core_l3_clkdm", | ||
| 3156 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3157 | .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, | ||
| 3158 | .recalc = &followparent_recalc, | ||
| 3159 | }; | ||
| 3160 | |||
| 3161 | static struct clk rmii_ck = { | ||
| 3162 | .name = "rmii_ck", | ||
| 3163 | .ops = &clkops_null, | ||
| 3164 | .rate = 50000000, | ||
| 3165 | }; | ||
| 3166 | |||
| 3167 | static struct clk emac_fck = { | ||
| 3168 | .name = "emac_fck", | ||
| 3169 | .ops = &clkops_omap2_dflt, | ||
| 3170 | .parent = &rmii_ck, | ||
| 3171 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3172 | .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, | ||
| 3173 | .recalc = &followparent_recalc, | ||
| 3174 | }; | ||
| 3175 | |||
| 3176 | static struct clk hsotgusb_ick_am35xx = { | ||
| 3177 | .name = "hsotgusb_ick", | ||
| 3178 | .ops = &clkops_am35xx_ipss_module_wait, | ||
| 3179 | .parent = &ipss_ick, | ||
| 3180 | .clkdm_name = "core_l3_clkdm", | ||
| 3181 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3182 | .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, | ||
| 3183 | .recalc = &followparent_recalc, | ||
| 3184 | }; | ||
| 3185 | |||
| 3186 | static struct clk hsotgusb_fck_am35xx = { | ||
| 3187 | .name = "hsotgusb_fck", | ||
| 3188 | .ops = &clkops_omap2_dflt, | ||
| 3189 | .parent = &sys_ck, | ||
| 3190 | .clkdm_name = "core_l3_clkdm", | ||
| 3191 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3192 | .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, | ||
| 3193 | .recalc = &followparent_recalc, | ||
| 3194 | }; | ||
| 3195 | |||
| 3196 | static struct clk hecc_ck = { | ||
| 3197 | .name = "hecc_ck", | ||
| 3198 | .ops = &clkops_am35xx_ipss_module_wait, | ||
| 3199 | .parent = &sys_ck, | ||
| 3200 | .clkdm_name = "core_l3_clkdm", | ||
| 3201 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3202 | .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, | ||
| 3203 | .recalc = &followparent_recalc, | ||
| 3204 | }; | ||
| 3205 | |||
| 3206 | static struct clk vpfe_ick = { | ||
| 3207 | .name = "vpfe_ick", | ||
| 3208 | .ops = &clkops_am35xx_ipss_module_wait, | ||
| 3209 | .parent = &ipss_ick, | ||
| 3210 | .clkdm_name = "core_l3_clkdm", | ||
| 3211 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3212 | .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, | ||
| 3213 | .recalc = &followparent_recalc, | ||
| 3214 | }; | ||
| 3215 | |||
| 3216 | static struct clk pclk_ck = { | ||
| 3217 | .name = "pclk_ck", | ||
| 3218 | .ops = &clkops_null, | ||
| 3219 | .rate = 27000000, | ||
| 3220 | }; | ||
| 3221 | |||
| 3222 | static struct clk vpfe_fck = { | ||
| 3223 | .name = "vpfe_fck", | ||
| 3224 | .ops = &clkops_omap2_dflt, | ||
| 3225 | .parent = &pclk_ck, | ||
| 3226 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
| 3227 | .enable_bit = AM35XX_VPFE_FCLK_SHIFT, | ||
| 3228 | .recalc = &followparent_recalc, | ||
| 3229 | }; | ||
| 3230 | |||
| 3231 | /* | ||
| 3232 | * The UART1/2 functional clock acts as the functional | ||
| 3233 | * clock for UART4. No separate fclk control available. | ||
| 3234 | */ | ||
| 3235 | static struct clk uart4_ick_am35xx = { | ||
| 3236 | .name = "uart4_ick", | ||
| 3237 | .ops = &clkops_omap2_dflt_wait, | ||
| 3238 | .parent = &core_l4_ick, | ||
| 3239 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 3240 | .enable_bit = AM35XX_EN_UART4_SHIFT, | ||
| 3241 | .clkdm_name = "core_l4_clkdm", | ||
| 3242 | .recalc = &followparent_recalc, | ||
| 3243 | }; | ||
| 3244 | |||
| 2986 | 3245 | ||
| 2987 | /* | 3246 | /* |
| 2988 | * clkdev | 3247 | * clkdev |
| 2989 | */ | 3248 | */ |
| 2990 | 3249 | ||
| 2991 | static struct omap_clk omap34xx_clks[] = { | 3250 | /* XXX At some point we should rename this file to clock3xxx_data.c */ |
| 2992 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | 3251 | static struct omap_clk omap3xxx_clks[] = { |
| 2993 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | 3252 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), |
| 2994 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | 3253 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), |
| 2995 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | 3254 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), |
| 2996 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | 3255 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), |
| 2997 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | 3256 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), |
| 2998 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | 3257 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), |
| 2999 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | 3258 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), |
| 3000 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | 3259 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), |
| 3001 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | 3260 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), |
| 3002 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | 3261 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), |
| 3003 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | 3262 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), |
| 3004 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | 3263 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), |
| 3005 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | 3264 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), |
| 3006 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | 3265 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), |
| 3266 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), | ||
| 3007 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | 3267 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), |
| 3008 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | 3268 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), |
| 3009 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | 3269 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), |
| 3010 | CLK(NULL, "core_ck", &core_ck, CK_343X), | 3270 | CLK(NULL, "core_ck", &core_ck, CK_3XXX), |
| 3011 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | 3271 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), |
| 3012 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | 3272 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), |
| 3013 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | 3273 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), |
| 3014 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | 3274 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), |
| 3015 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | 3275 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), |
| 3016 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | 3276 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), |
| 3017 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | 3277 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), |
| 3018 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | 3278 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), |
| 3019 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | 3279 | CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), |
| 3020 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | 3280 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), |
| 3021 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | 3281 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), |
| 3022 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | 3282 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), |
| 3023 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | 3283 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), |
| 3024 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | 3284 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), |
| 3025 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | 3285 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), |
| 3026 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | 3286 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), |
| 3027 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | 3287 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), |
| 3028 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | 3288 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), |
| 3029 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | 3289 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), |
| 3030 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | 3290 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), |
| 3031 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | 3291 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), |
| 3032 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | 3292 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), |
| 3033 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | 3293 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), |
| 3034 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | 3294 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), |
| 3035 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | 3295 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), |
| 3036 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | 3296 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), |
| 3037 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | 3297 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), |
| 3038 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | 3298 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), |
| 3039 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | 3299 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), |
| 3040 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | 3300 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), |
| 3041 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | 3301 | CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), |
| 3042 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | 3302 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), |
| 3043 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | 3303 | CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), |
| 3044 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | 3304 | CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), |
| 3305 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), | ||
| 3045 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | 3306 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), |
| 3046 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | 3307 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), |
| 3047 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | 3308 | CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), |
| 3048 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | 3309 | CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), |
| 3049 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | 3310 | CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), |
| 3050 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | 3311 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), |
| 3051 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | 3312 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), |
| 3052 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | 3313 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), |
| 3053 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | 3314 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), |
| 3054 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | 3315 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), |
| 3055 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | 3316 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), |
| 3056 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | 3317 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), |
| 3057 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | 3318 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), |
| 3058 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), | 3319 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), |
| 3059 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | 3320 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), |
| 3060 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | 3321 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), |
| 3061 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | 3322 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), |
| 3062 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | 3323 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), |
| 3063 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | 3324 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), |
| 3064 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | 3325 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), |
| 3065 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | 3326 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), |
| 3066 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | 3327 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), |
| 3067 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | 3328 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), |
| 3068 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | 3329 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), |
| 3069 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | 3330 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), |
| 3070 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | 3331 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), |
| 3071 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | 3332 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX), |
| 3072 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | 3333 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX), |
| 3073 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | 3334 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX), |
| 3074 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | 3335 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), |
| 3075 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | 3336 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), |
| 3076 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | 3337 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), |
| 3077 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | 3338 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX), |
| 3078 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | 3339 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX), |
| 3079 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | 3340 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX), |
| 3080 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | 3341 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX), |
| 3081 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | 3342 | CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), |
| 3082 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | 3343 | CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), |
| 3083 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | 3344 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), |
| 3084 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | 3345 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), |
| 3085 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | 3346 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), |
| 3086 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | 3347 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), |
| 3087 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | 3348 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), |
| 3088 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | 3349 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), |
| 3089 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | 3350 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), |
| 3090 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | 3351 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), |
| 3091 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | 3352 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), |
| 3092 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | 3353 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), |
| 3093 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | 3354 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), |
| 3094 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | 3355 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), |
| 3095 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | 3356 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), |
| 3096 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | 3357 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), |
| 3097 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | 3358 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), |
| 3098 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | 3359 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), |
| 3099 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | 3360 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), |
| 3100 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | 3361 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), |
| 3101 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | 3362 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), |
| 3102 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | 3363 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), |
| 3103 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | 3364 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), |
| 3104 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | 3365 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), |
| 3105 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | 3366 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), |
| 3106 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | 3367 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), |
| 3107 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | 3368 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), |
| 3108 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | 3369 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), |
| 3109 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | 3370 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), |
| 3110 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | 3371 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), |
| 3111 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | 3372 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), |
| 3112 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | 3373 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX), |
| 3113 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | 3374 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX), |
| 3114 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | 3375 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX), |
| 3115 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | 3376 | CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), |
| 3116 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | 3377 | CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), |
| 3117 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | 3378 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), |
| 3118 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | 3379 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), |
| 3119 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | 3380 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), |
| 3120 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | 3381 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), |
| 3121 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | 3382 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), |
| 3122 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | 3383 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), |
| 3123 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | 3384 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), |
| 3124 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | 3385 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), |
| 3125 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | 3386 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), |
| 3126 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | 3387 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), |
| @@ -3131,96 +3392,111 @@ static struct omap_clk omap34xx_clks[] = { | |||
| 3131 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | 3392 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), |
| 3132 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | 3393 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), |
| 3133 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | 3394 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), |
| 3134 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), | 3395 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), |
| 3135 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), | 3396 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), |
| 3136 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), | 3397 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), |
| 3137 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), | 3398 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), |
| 3138 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | 3399 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), |
| 3139 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), | 3400 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), |
| 3140 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | 3401 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), |
| 3141 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | 3402 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), |
| 3142 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | 3403 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), |
| 3143 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | 3404 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), |
| 3144 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | 3405 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), |
| 3145 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | 3406 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), |
| 3146 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | 3407 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), |
| 3147 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | 3408 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), |
| 3148 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | 3409 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), |
| 3149 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | 3410 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), |
| 3150 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | 3411 | CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), |
| 3151 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | 3412 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), |
| 3152 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | 3413 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), |
| 3153 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | 3414 | CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), |
| 3154 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | 3415 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), |
| 3155 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | 3416 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), |
| 3156 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | 3417 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), |
| 3157 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | 3418 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), |
| 3158 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | 3419 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), |
| 3159 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | 3420 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), |
| 3160 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | 3421 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), |
| 3161 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | 3422 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), |
| 3162 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | 3423 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), |
| 3163 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | 3424 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), |
| 3164 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | 3425 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), |
| 3165 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | 3426 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), |
| 3166 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | 3427 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), |
| 3167 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | 3428 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), |
| 3168 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | 3429 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), |
| 3169 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | 3430 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), |
| 3170 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | 3431 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), |
| 3171 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | 3432 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), |
| 3172 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | 3433 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), |
| 3173 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | 3434 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), |
| 3174 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | 3435 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), |
| 3175 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | 3436 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), |
| 3176 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | 3437 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), |
| 3177 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | 3438 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), |
| 3178 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | 3439 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), |
| 3179 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | 3440 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), |
| 3180 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | 3441 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), |
| 3181 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | 3442 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), |
| 3182 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | 3443 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), |
| 3183 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | 3444 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), |
| 3184 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | 3445 | CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), |
| 3185 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | 3446 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), |
| 3186 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | 3447 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), |
| 3187 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | 3448 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), |
| 3188 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | 3449 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), |
| 3189 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | 3450 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), |
| 3190 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | 3451 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), |
| 3191 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | 3452 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), |
| 3192 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | 3453 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), |
| 3193 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | 3454 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), |
| 3194 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | 3455 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), |
| 3195 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | 3456 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), |
| 3196 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | 3457 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX), |
| 3197 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | 3458 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX), |
| 3198 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | 3459 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX), |
| 3199 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), | 3460 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), |
| 3200 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | 3461 | CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), |
| 3201 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | 3462 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), |
| 3202 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | 3463 | CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), |
| 3203 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | 3464 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), |
| 3204 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | 3465 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), |
| 3205 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | 3466 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), |
| 3206 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | 3467 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), |
| 3207 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | 3468 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), |
| 3208 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | 3469 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), |
| 3209 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | 3470 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), |
| 3210 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | 3471 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), |
| 3211 | }; | 3472 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), |
| 3212 | 3473 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), | |
| 3213 | 3474 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), | |
| 3214 | int __init omap2_clk_init(void) | 3475 | CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX), |
| 3476 | CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX), | ||
| 3477 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | ||
| 3478 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | ||
| 3479 | CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), | ||
| 3480 | CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), | ||
| 3481 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), | ||
| 3482 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), | ||
| 3483 | }; | ||
| 3484 | |||
| 3485 | |||
| 3486 | int __init omap3xxx_clk_init(void) | ||
| 3215 | { | 3487 | { |
| 3216 | /* struct prcm_config *prcm; */ | ||
| 3217 | struct omap_clk *c; | 3488 | struct omap_clk *c; |
| 3218 | /* u32 clkrate; */ | 3489 | u32 cpu_clkflg = CK_3XXX; |
| 3219 | u32 cpu_clkflg; | 3490 | |
| 3220 | 3491 | if (cpu_is_omap3517()) { | |
| 3221 | if (cpu_is_omap34xx()) { | 3492 | cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; |
| 3493 | cpu_clkflg |= CK_3517; | ||
| 3494 | } else if (cpu_is_omap3505()) { | ||
| 3495 | cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; | ||
| 3496 | cpu_clkflg |= CK_3505; | ||
| 3497 | } else if (cpu_is_omap34xx()) { | ||
| 3222 | cpu_mask = RATE_IN_343X; | 3498 | cpu_mask = RATE_IN_343X; |
| 3223 | cpu_clkflg = CK_343X; | 3499 | cpu_clkflg |= CK_343X; |
| 3224 | 3500 | ||
| 3225 | /* | 3501 | /* |
| 3226 | * Update this if there are further clock changes between ES2 | 3502 | * Update this if there are further clock changes between ES2 |
| @@ -3234,34 +3510,70 @@ int __init omap2_clk_init(void) | |||
| 3234 | cpu_clkflg |= CK_3430ES2; | 3510 | cpu_clkflg |= CK_3430ES2; |
| 3235 | } | 3511 | } |
| 3236 | } | 3512 | } |
| 3513 | if (omap3_has_192mhz_clk()) | ||
| 3514 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; | ||
| 3515 | |||
| 3516 | if (cpu_is_omap3630()) { | ||
| 3517 | cpu_mask |= RATE_IN_36XX; | ||
| 3518 | cpu_clkflg |= CK_36XX; | ||
| 3519 | |||
| 3520 | /* | ||
| 3521 | * XXX This type of dynamic rewriting of the clock tree is | ||
| 3522 | * deprecated and should be revised soon. | ||
| 3523 | */ | ||
| 3524 | dpll4_m2_ck = dpll4_m2_ck_3630; | ||
| 3525 | dpll4_m3_ck = dpll4_m3_ck_3630; | ||
| 3526 | dpll4_m4_ck = dpll4_m4_ck_3630; | ||
| 3527 | dpll4_m5_ck = dpll4_m5_ck_3630; | ||
| 3528 | dpll4_m6_ck = dpll4_m6_ck_3630; | ||
| 3529 | |||
| 3530 | /* | ||
| 3531 | * For 3630: override clkops_omap2_dflt_wait for the | ||
| 3532 | * clocks affected from PWRDN reset Limitation | ||
| 3533 | */ | ||
| 3534 | dpll3_m3x2_ck.ops = | ||
| 3535 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 3536 | dpll4_m2x2_ck.ops = | ||
| 3537 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 3538 | dpll4_m3x2_ck.ops = | ||
| 3539 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 3540 | dpll4_m4x2_ck.ops = | ||
| 3541 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 3542 | dpll4_m5x2_ck.ops = | ||
| 3543 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 3544 | dpll4_m6x2_ck.ops = | ||
| 3545 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
| 3546 | } else { | ||
| 3547 | /* | ||
| 3548 | * XXX This type of dynamic rewriting of the clock tree is | ||
| 3549 | * deprecated and should be revised soon. | ||
| 3550 | */ | ||
| 3551 | dpll4_m2_ck = dpll4_m2_ck_34xx; | ||
| 3552 | dpll4_m3_ck = dpll4_m3_ck_34xx; | ||
| 3553 | dpll4_m4_ck = dpll4_m4_ck_34xx; | ||
| 3554 | dpll4_m5_ck = dpll4_m5_ck_34xx; | ||
| 3555 | dpll4_m6_ck = dpll4_m6_ck_34xx; | ||
| 3556 | } | ||
| 3557 | |||
| 3558 | if (cpu_is_omap3630()) | ||
| 3559 | dpll4_dd = dpll4_dd_3630; | ||
| 3560 | else | ||
| 3561 | dpll4_dd = dpll4_dd_34xx; | ||
| 3237 | 3562 | ||
| 3238 | clk_init(&omap2_clk_functions); | 3563 | clk_init(&omap2_clk_functions); |
| 3239 | 3564 | ||
| 3240 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | 3565 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); |
| 3566 | c++) | ||
| 3241 | clk_preinit(c->lk.clk); | 3567 | clk_preinit(c->lk.clk); |
| 3242 | 3568 | ||
| 3243 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | 3569 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); |
| 3570 | c++) | ||
| 3244 | if (c->cpu & cpu_clkflg) { | 3571 | if (c->cpu & cpu_clkflg) { |
| 3245 | clkdev_add(&c->lk); | 3572 | clkdev_add(&c->lk); |
| 3246 | clk_register(c->lk.clk); | 3573 | clk_register(c->lk.clk); |
| 3247 | omap2_init_clk_clkdm(c->lk.clk); | 3574 | omap2_init_clk_clkdm(c->lk.clk); |
| 3248 | } | 3575 | } |
| 3249 | 3576 | ||
| 3250 | /* REVISIT: Not yet ready for OMAP3 */ | ||
| 3251 | #if 0 | ||
| 3252 | /* Check the MPU rate set by bootloader */ | ||
| 3253 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 3254 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 3255 | if (!(prcm->flags & cpu_mask)) | ||
| 3256 | continue; | ||
| 3257 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 3258 | continue; | ||
| 3259 | if (prcm->dpll_speed <= clkrate) | ||
| 3260 | break; | ||
| 3261 | } | ||
| 3262 | curr_prcm_set = prcm; | ||
| 3263 | #endif | ||
| 3264 | |||
| 3265 | recalculate_root_clocks(); | 3577 | recalculate_root_clocks(); |
| 3266 | 3578 | ||
| 3267 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | 3579 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " |
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c deleted file mode 100644 index e370868a79a8..000000000000 --- a/arch/arm/mach-omap2/clock44xx.c +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4-specific clock framework functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Rajendra Nayak (rnayak@ti.com) | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/errno.h> | ||
| 14 | #include "clock.h" | ||
| 15 | |||
| 16 | struct clk_functions omap2_clk_functions = { | ||
| 17 | .clk_enable = omap2_clk_enable, | ||
| 18 | .clk_disable = omap2_clk_disable, | ||
| 19 | .clk_round_rate = omap2_clk_round_rate, | ||
| 20 | .clk_set_rate = omap2_clk_set_rate, | ||
| 21 | .clk_set_parent = omap2_clk_set_parent, | ||
| 22 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 23 | }; | ||
| 24 | |||
| 25 | const struct clkops clkops_noncore_dpll_ops = { | ||
| 26 | .enable = &omap3_noncore_dpll_enable, | ||
| 27 | .disable = &omap3_noncore_dpll_disable, | ||
| 28 | }; | ||
| 29 | |||
| 30 | void omap2_clk_prepare_for_reboot(void) | ||
| 31 | { | ||
| 32 | return; | ||
| 33 | } | ||
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h index 59b9ced4daa1..6be1095936db 100644 --- a/arch/arm/mach-omap2/clock44xx.h +++ b/arch/arm/mach-omap2/clock44xx.h | |||
| @@ -2,14 +2,19 @@ | |||
| 2 | * OMAP4 clock function prototypes and macros | 2 | * OMAP4 clock function prototypes and macros |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 5 | */ | 6 | */ |
| 6 | 7 | ||
| 7 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H |
| 8 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H |
| 9 | 10 | ||
| 10 | #define OMAP4430_MAX_DPLL_MULT 2048 | 11 | /* |
| 12 | * XXX Missing values for the OMAP4 DPLL_USB | ||
| 13 | * XXX Missing min_multiplier values for all OMAP4 DPLLs | ||
| 14 | */ | ||
| 15 | #define OMAP4430_MAX_DPLL_MULT 2047 | ||
| 11 | #define OMAP4430_MAX_DPLL_DIV 128 | 16 | #define OMAP4430_MAX_DPLL_DIV 128 |
| 12 | 17 | ||
| 13 | extern const struct clkops clkops_noncore_dpll_ops; | 18 | int omap4xxx_clk_init(void); |
| 14 | 19 | ||
| 15 | #endif | 20 | #endif |
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 9d882bcb56e3..28b107967c86 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP4 Clock data | 2 | * OMAP4 Clock data |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009 Nokia Corporation | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | 7 | * Paul Walmsley (paul@pwsan.com) |
| 8 | * Rajendra Nayak (rnayak@ti.com) | 8 | * Rajendra Nayak (rnayak@ti.com) |
| @@ -20,7 +20,7 @@ | |||
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/module.h> | 23 | #include <linux/list.h> |
| 24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 25 | 25 | ||
| 26 | #include <plat/control.h> | 26 | #include <plat/control.h> |
| @@ -39,42 +39,36 @@ static struct clk extalt_clkin_ck = { | |||
| 39 | .name = "extalt_clkin_ck", | 39 | .name = "extalt_clkin_ck", |
| 40 | .rate = 59000000, | 40 | .rate = 59000000, |
| 41 | .ops = &clkops_null, | 41 | .ops = &clkops_null, |
| 42 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 43 | }; | 42 | }; |
| 44 | 43 | ||
| 45 | static struct clk pad_clks_ck = { | 44 | static struct clk pad_clks_ck = { |
| 46 | .name = "pad_clks_ck", | 45 | .name = "pad_clks_ck", |
| 47 | .rate = 12000000, | 46 | .rate = 12000000, |
| 48 | .ops = &clkops_null, | 47 | .ops = &clkops_null, |
| 49 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 50 | }; | 48 | }; |
| 51 | 49 | ||
| 52 | static struct clk pad_slimbus_core_clks_ck = { | 50 | static struct clk pad_slimbus_core_clks_ck = { |
| 53 | .name = "pad_slimbus_core_clks_ck", | 51 | .name = "pad_slimbus_core_clks_ck", |
| 54 | .rate = 12000000, | 52 | .rate = 12000000, |
| 55 | .ops = &clkops_null, | 53 | .ops = &clkops_null, |
| 56 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 57 | }; | 54 | }; |
| 58 | 55 | ||
| 59 | static struct clk secure_32k_clk_src_ck = { | 56 | static struct clk secure_32k_clk_src_ck = { |
| 60 | .name = "secure_32k_clk_src_ck", | 57 | .name = "secure_32k_clk_src_ck", |
| 61 | .rate = 32768, | 58 | .rate = 32768, |
| 62 | .ops = &clkops_null, | 59 | .ops = &clkops_null, |
| 63 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 64 | }; | 60 | }; |
| 65 | 61 | ||
| 66 | static struct clk slimbus_clk = { | 62 | static struct clk slimbus_clk = { |
| 67 | .name = "slimbus_clk", | 63 | .name = "slimbus_clk", |
| 68 | .rate = 12000000, | 64 | .rate = 12000000, |
| 69 | .ops = &clkops_null, | 65 | .ops = &clkops_null, |
| 70 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 71 | }; | 66 | }; |
| 72 | 67 | ||
| 73 | static struct clk sys_32k_ck = { | 68 | static struct clk sys_32k_ck = { |
| 74 | .name = "sys_32k_ck", | 69 | .name = "sys_32k_ck", |
| 75 | .rate = 32768, | 70 | .rate = 32768, |
| 76 | .ops = &clkops_null, | 71 | .ops = &clkops_null, |
| 77 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 78 | }; | 72 | }; |
| 79 | 73 | ||
| 80 | static struct clk virt_12000000_ck = { | 74 | static struct clk virt_12000000_ck = { |
| @@ -179,35 +173,30 @@ static struct clk sys_clkin_ck = { | |||
| 179 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | 173 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, |
| 180 | .ops = &clkops_null, | 174 | .ops = &clkops_null, |
| 181 | .recalc = &omap2_clksel_recalc, | 175 | .recalc = &omap2_clksel_recalc, |
| 182 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 183 | }; | 176 | }; |
| 184 | 177 | ||
| 185 | static struct clk utmi_phy_clkout_ck = { | 178 | static struct clk utmi_phy_clkout_ck = { |
| 186 | .name = "utmi_phy_clkout_ck", | 179 | .name = "utmi_phy_clkout_ck", |
| 187 | .rate = 12000000, | 180 | .rate = 12000000, |
| 188 | .ops = &clkops_null, | 181 | .ops = &clkops_null, |
| 189 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 190 | }; | 182 | }; |
| 191 | 183 | ||
| 192 | static struct clk xclk60mhsp1_ck = { | 184 | static struct clk xclk60mhsp1_ck = { |
| 193 | .name = "xclk60mhsp1_ck", | 185 | .name = "xclk60mhsp1_ck", |
| 194 | .rate = 12000000, | 186 | .rate = 12000000, |
| 195 | .ops = &clkops_null, | 187 | .ops = &clkops_null, |
| 196 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 197 | }; | 188 | }; |
| 198 | 189 | ||
| 199 | static struct clk xclk60mhsp2_ck = { | 190 | static struct clk xclk60mhsp2_ck = { |
| 200 | .name = "xclk60mhsp2_ck", | 191 | .name = "xclk60mhsp2_ck", |
| 201 | .rate = 12000000, | 192 | .rate = 12000000, |
| 202 | .ops = &clkops_null, | 193 | .ops = &clkops_null, |
| 203 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 204 | }; | 194 | }; |
| 205 | 195 | ||
| 206 | static struct clk xclk60motg_ck = { | 196 | static struct clk xclk60motg_ck = { |
| 207 | .name = "xclk60motg_ck", | 197 | .name = "xclk60motg_ck", |
| 208 | .rate = 60000000, | 198 | .rate = 60000000, |
| 209 | .ops = &clkops_null, | 199 | .ops = &clkops_null, |
| 210 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
| 211 | }; | 200 | }; |
| 212 | 201 | ||
| 213 | /* Module clocks and DPLL outputs */ | 202 | /* Module clocks and DPLL outputs */ |
| @@ -233,7 +222,6 @@ static struct clk dpll_sys_ref_clk = { | |||
| 233 | .recalc = &omap2_clksel_recalc, | 222 | .recalc = &omap2_clksel_recalc, |
| 234 | .round_rate = &omap2_clksel_round_rate, | 223 | .round_rate = &omap2_clksel_round_rate, |
| 235 | .set_rate = &omap2_clksel_set_rate, | 224 | .set_rate = &omap2_clksel_set_rate, |
| 236 | .flags = CLOCK_IN_OMAP4430, | ||
| 237 | }; | 225 | }; |
| 238 | 226 | ||
| 239 | static const struct clksel abe_dpll_refclk_mux_sel[] = { | 227 | static const struct clksel abe_dpll_refclk_mux_sel[] = { |
| @@ -251,7 +239,6 @@ static struct clk abe_dpll_refclk_mux_ck = { | |||
| 251 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | 239 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 252 | .ops = &clkops_null, | 240 | .ops = &clkops_null, |
| 253 | .recalc = &omap2_clksel_recalc, | 241 | .recalc = &omap2_clksel_recalc, |
| 254 | .flags = CLOCK_IN_OMAP4430, | ||
| 255 | }; | 242 | }; |
| 256 | 243 | ||
| 257 | /* DPLL_ABE */ | 244 | /* DPLL_ABE */ |
| @@ -279,11 +266,10 @@ static struct clk dpll_abe_ck = { | |||
| 279 | .parent = &abe_dpll_refclk_mux_ck, | 266 | .parent = &abe_dpll_refclk_mux_ck, |
| 280 | .dpll_data = &dpll_abe_dd, | 267 | .dpll_data = &dpll_abe_dd, |
| 281 | .init = &omap2_init_dpll_parent, | 268 | .init = &omap2_init_dpll_parent, |
| 282 | .ops = &clkops_noncore_dpll_ops, | 269 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 283 | .recalc = &omap3_dpll_recalc, | 270 | .recalc = &omap3_dpll_recalc, |
| 284 | .round_rate = &omap2_dpll_round_rate, | 271 | .round_rate = &omap2_dpll_round_rate, |
| 285 | .set_rate = &omap3_noncore_dpll_set_rate, | 272 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 286 | .flags = CLOCK_IN_OMAP4430, | ||
| 287 | }; | 273 | }; |
| 288 | 274 | ||
| 289 | static struct clk dpll_abe_m2x2_ck = { | 275 | static struct clk dpll_abe_m2x2_ck = { |
| @@ -291,7 +277,6 @@ static struct clk dpll_abe_m2x2_ck = { | |||
| 291 | .parent = &dpll_abe_ck, | 277 | .parent = &dpll_abe_ck, |
| 292 | .ops = &clkops_null, | 278 | .ops = &clkops_null, |
| 293 | .recalc = &followparent_recalc, | 279 | .recalc = &followparent_recalc, |
| 294 | .flags = CLOCK_IN_OMAP4430, | ||
| 295 | }; | 280 | }; |
| 296 | 281 | ||
| 297 | static struct clk abe_24m_fclk = { | 282 | static struct clk abe_24m_fclk = { |
| @@ -299,7 +284,6 @@ static struct clk abe_24m_fclk = { | |||
| 299 | .parent = &dpll_abe_m2x2_ck, | 284 | .parent = &dpll_abe_m2x2_ck, |
| 300 | .ops = &clkops_null, | 285 | .ops = &clkops_null, |
| 301 | .recalc = &followparent_recalc, | 286 | .recalc = &followparent_recalc, |
| 302 | .flags = CLOCK_IN_OMAP4430, | ||
| 303 | }; | 287 | }; |
| 304 | 288 | ||
| 305 | static const struct clksel_rate div3_1to4_rates[] = { | 289 | static const struct clksel_rate div3_1to4_rates[] = { |
| @@ -324,7 +308,6 @@ static struct clk abe_clk = { | |||
| 324 | .recalc = &omap2_clksel_recalc, | 308 | .recalc = &omap2_clksel_recalc, |
| 325 | .round_rate = &omap2_clksel_round_rate, | 309 | .round_rate = &omap2_clksel_round_rate, |
| 326 | .set_rate = &omap2_clksel_set_rate, | 310 | .set_rate = &omap2_clksel_set_rate, |
| 327 | .flags = CLOCK_IN_OMAP4430, | ||
| 328 | }; | 311 | }; |
| 329 | 312 | ||
| 330 | static const struct clksel aess_fclk_div[] = { | 313 | static const struct clksel aess_fclk_div[] = { |
| @@ -342,7 +325,6 @@ static struct clk aess_fclk = { | |||
| 342 | .recalc = &omap2_clksel_recalc, | 325 | .recalc = &omap2_clksel_recalc, |
| 343 | .round_rate = &omap2_clksel_round_rate, | 326 | .round_rate = &omap2_clksel_round_rate, |
| 344 | .set_rate = &omap2_clksel_set_rate, | 327 | .set_rate = &omap2_clksel_set_rate, |
| 345 | .flags = CLOCK_IN_OMAP4430, | ||
| 346 | }; | 328 | }; |
| 347 | 329 | ||
| 348 | static const struct clksel_rate div31_1to31_rates[] = { | 330 | static const struct clksel_rate div31_1to31_rates[] = { |
| @@ -395,7 +377,6 @@ static struct clk dpll_abe_m3_ck = { | |||
| 395 | .recalc = &omap2_clksel_recalc, | 377 | .recalc = &omap2_clksel_recalc, |
| 396 | .round_rate = &omap2_clksel_round_rate, | 378 | .round_rate = &omap2_clksel_round_rate, |
| 397 | .set_rate = &omap2_clksel_set_rate, | 379 | .set_rate = &omap2_clksel_set_rate, |
| 398 | .flags = CLOCK_IN_OMAP4430, | ||
| 399 | }; | 380 | }; |
| 400 | 381 | ||
| 401 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | 382 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { |
| @@ -413,7 +394,6 @@ static struct clk core_hsd_byp_clk_mux_ck = { | |||
| 413 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | 394 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
| 414 | .ops = &clkops_null, | 395 | .ops = &clkops_null, |
| 415 | .recalc = &omap2_clksel_recalc, | 396 | .recalc = &omap2_clksel_recalc, |
| 416 | .flags = CLOCK_IN_OMAP4430, | ||
| 417 | }; | 397 | }; |
| 418 | 398 | ||
| 419 | /* DPLL_CORE */ | 399 | /* DPLL_CORE */ |
| @@ -443,7 +423,6 @@ static struct clk dpll_core_ck = { | |||
| 443 | .init = &omap2_init_dpll_parent, | 423 | .init = &omap2_init_dpll_parent, |
| 444 | .ops = &clkops_null, | 424 | .ops = &clkops_null, |
| 445 | .recalc = &omap3_dpll_recalc, | 425 | .recalc = &omap3_dpll_recalc, |
| 446 | .flags = CLOCK_IN_OMAP4430, | ||
| 447 | }; | 426 | }; |
| 448 | 427 | ||
| 449 | static const struct clksel dpll_core_m6_div[] = { | 428 | static const struct clksel dpll_core_m6_div[] = { |
| @@ -461,7 +440,6 @@ static struct clk dpll_core_m6_ck = { | |||
| 461 | .recalc = &omap2_clksel_recalc, | 440 | .recalc = &omap2_clksel_recalc, |
| 462 | .round_rate = &omap2_clksel_round_rate, | 441 | .round_rate = &omap2_clksel_round_rate, |
| 463 | .set_rate = &omap2_clksel_set_rate, | 442 | .set_rate = &omap2_clksel_set_rate, |
| 464 | .flags = CLOCK_IN_OMAP4430, | ||
| 465 | }; | 443 | }; |
| 466 | 444 | ||
| 467 | static const struct clksel dbgclk_mux_sel[] = { | 445 | static const struct clksel dbgclk_mux_sel[] = { |
| @@ -475,7 +453,6 @@ static struct clk dbgclk_mux_ck = { | |||
| 475 | .parent = &sys_clkin_ck, | 453 | .parent = &sys_clkin_ck, |
| 476 | .ops = &clkops_null, | 454 | .ops = &clkops_null, |
| 477 | .recalc = &followparent_recalc, | 455 | .recalc = &followparent_recalc, |
| 478 | .flags = CLOCK_IN_OMAP4430, | ||
| 479 | }; | 456 | }; |
| 480 | 457 | ||
| 481 | static struct clk dpll_core_m2_ck = { | 458 | static struct clk dpll_core_m2_ck = { |
| @@ -488,7 +465,6 @@ static struct clk dpll_core_m2_ck = { | |||
| 488 | .recalc = &omap2_clksel_recalc, | 465 | .recalc = &omap2_clksel_recalc, |
| 489 | .round_rate = &omap2_clksel_round_rate, | 466 | .round_rate = &omap2_clksel_round_rate, |
| 490 | .set_rate = &omap2_clksel_set_rate, | 467 | .set_rate = &omap2_clksel_set_rate, |
| 491 | .flags = CLOCK_IN_OMAP4430, | ||
| 492 | }; | 468 | }; |
| 493 | 469 | ||
| 494 | static struct clk ddrphy_ck = { | 470 | static struct clk ddrphy_ck = { |
| @@ -496,7 +472,6 @@ static struct clk ddrphy_ck = { | |||
| 496 | .parent = &dpll_core_m2_ck, | 472 | .parent = &dpll_core_m2_ck, |
| 497 | .ops = &clkops_null, | 473 | .ops = &clkops_null, |
| 498 | .recalc = &followparent_recalc, | 474 | .recalc = &followparent_recalc, |
| 499 | .flags = CLOCK_IN_OMAP4430, | ||
| 500 | }; | 475 | }; |
| 501 | 476 | ||
| 502 | static struct clk dpll_core_m5_ck = { | 477 | static struct clk dpll_core_m5_ck = { |
| @@ -509,7 +484,6 @@ static struct clk dpll_core_m5_ck = { | |||
| 509 | .recalc = &omap2_clksel_recalc, | 484 | .recalc = &omap2_clksel_recalc, |
| 510 | .round_rate = &omap2_clksel_round_rate, | 485 | .round_rate = &omap2_clksel_round_rate, |
| 511 | .set_rate = &omap2_clksel_set_rate, | 486 | .set_rate = &omap2_clksel_set_rate, |
| 512 | .flags = CLOCK_IN_OMAP4430, | ||
| 513 | }; | 487 | }; |
| 514 | 488 | ||
| 515 | static const struct clksel div_core_div[] = { | 489 | static const struct clksel div_core_div[] = { |
| @@ -527,7 +501,6 @@ static struct clk div_core_ck = { | |||
| 527 | .recalc = &omap2_clksel_recalc, | 501 | .recalc = &omap2_clksel_recalc, |
| 528 | .round_rate = &omap2_clksel_round_rate, | 502 | .round_rate = &omap2_clksel_round_rate, |
| 529 | .set_rate = &omap2_clksel_set_rate, | 503 | .set_rate = &omap2_clksel_set_rate, |
| 530 | .flags = CLOCK_IN_OMAP4430, | ||
| 531 | }; | 504 | }; |
| 532 | 505 | ||
| 533 | static const struct clksel_rate div4_1to8_rates[] = { | 506 | static const struct clksel_rate div4_1to8_rates[] = { |
| @@ -553,7 +526,6 @@ static struct clk div_iva_hs_clk = { | |||
| 553 | .recalc = &omap2_clksel_recalc, | 526 | .recalc = &omap2_clksel_recalc, |
| 554 | .round_rate = &omap2_clksel_round_rate, | 527 | .round_rate = &omap2_clksel_round_rate, |
| 555 | .set_rate = &omap2_clksel_set_rate, | 528 | .set_rate = &omap2_clksel_set_rate, |
| 556 | .flags = CLOCK_IN_OMAP4430, | ||
| 557 | }; | 529 | }; |
| 558 | 530 | ||
| 559 | static struct clk div_mpu_hs_clk = { | 531 | static struct clk div_mpu_hs_clk = { |
| @@ -566,7 +538,6 @@ static struct clk div_mpu_hs_clk = { | |||
| 566 | .recalc = &omap2_clksel_recalc, | 538 | .recalc = &omap2_clksel_recalc, |
| 567 | .round_rate = &omap2_clksel_round_rate, | 539 | .round_rate = &omap2_clksel_round_rate, |
| 568 | .set_rate = &omap2_clksel_set_rate, | 540 | .set_rate = &omap2_clksel_set_rate, |
| 569 | .flags = CLOCK_IN_OMAP4430, | ||
| 570 | }; | 541 | }; |
| 571 | 542 | ||
| 572 | static struct clk dpll_core_m4_ck = { | 543 | static struct clk dpll_core_m4_ck = { |
| @@ -579,7 +550,6 @@ static struct clk dpll_core_m4_ck = { | |||
| 579 | .recalc = &omap2_clksel_recalc, | 550 | .recalc = &omap2_clksel_recalc, |
| 580 | .round_rate = &omap2_clksel_round_rate, | 551 | .round_rate = &omap2_clksel_round_rate, |
| 581 | .set_rate = &omap2_clksel_set_rate, | 552 | .set_rate = &omap2_clksel_set_rate, |
| 582 | .flags = CLOCK_IN_OMAP4430, | ||
| 583 | }; | 553 | }; |
| 584 | 554 | ||
| 585 | static struct clk dll_clk_div_ck = { | 555 | static struct clk dll_clk_div_ck = { |
| @@ -587,7 +557,6 @@ static struct clk dll_clk_div_ck = { | |||
| 587 | .parent = &dpll_core_m4_ck, | 557 | .parent = &dpll_core_m4_ck, |
| 588 | .ops = &clkops_null, | 558 | .ops = &clkops_null, |
| 589 | .recalc = &followparent_recalc, | 559 | .recalc = &followparent_recalc, |
| 590 | .flags = CLOCK_IN_OMAP4430, | ||
| 591 | }; | 560 | }; |
| 592 | 561 | ||
| 593 | static struct clk dpll_abe_m2_ck = { | 562 | static struct clk dpll_abe_m2_ck = { |
| @@ -600,7 +569,6 @@ static struct clk dpll_abe_m2_ck = { | |||
| 600 | .recalc = &omap2_clksel_recalc, | 569 | .recalc = &omap2_clksel_recalc, |
| 601 | .round_rate = &omap2_clksel_round_rate, | 570 | .round_rate = &omap2_clksel_round_rate, |
| 602 | .set_rate = &omap2_clksel_set_rate, | 571 | .set_rate = &omap2_clksel_set_rate, |
| 603 | .flags = CLOCK_IN_OMAP4430, | ||
| 604 | }; | 572 | }; |
| 605 | 573 | ||
| 606 | static struct clk dpll_core_m3_ck = { | 574 | static struct clk dpll_core_m3_ck = { |
| @@ -613,7 +581,6 @@ static struct clk dpll_core_m3_ck = { | |||
| 613 | .recalc = &omap2_clksel_recalc, | 581 | .recalc = &omap2_clksel_recalc, |
| 614 | .round_rate = &omap2_clksel_round_rate, | 582 | .round_rate = &omap2_clksel_round_rate, |
| 615 | .set_rate = &omap2_clksel_set_rate, | 583 | .set_rate = &omap2_clksel_set_rate, |
| 616 | .flags = CLOCK_IN_OMAP4430, | ||
| 617 | }; | 584 | }; |
| 618 | 585 | ||
| 619 | static struct clk dpll_core_m7_ck = { | 586 | static struct clk dpll_core_m7_ck = { |
| @@ -626,7 +593,6 @@ static struct clk dpll_core_m7_ck = { | |||
| 626 | .recalc = &omap2_clksel_recalc, | 593 | .recalc = &omap2_clksel_recalc, |
| 627 | .round_rate = &omap2_clksel_round_rate, | 594 | .round_rate = &omap2_clksel_round_rate, |
| 628 | .set_rate = &omap2_clksel_set_rate, | 595 | .set_rate = &omap2_clksel_set_rate, |
| 629 | .flags = CLOCK_IN_OMAP4430, | ||
| 630 | }; | 596 | }; |
| 631 | 597 | ||
| 632 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | 598 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { |
| @@ -640,7 +606,6 @@ static struct clk iva_hsd_byp_clk_mux_ck = { | |||
| 640 | .parent = &dpll_sys_ref_clk, | 606 | .parent = &dpll_sys_ref_clk, |
| 641 | .ops = &clkops_null, | 607 | .ops = &clkops_null, |
| 642 | .recalc = &followparent_recalc, | 608 | .recalc = &followparent_recalc, |
| 643 | .flags = CLOCK_IN_OMAP4430, | ||
| 644 | }; | 609 | }; |
| 645 | 610 | ||
| 646 | /* DPLL_IVA */ | 611 | /* DPLL_IVA */ |
| @@ -668,11 +633,10 @@ static struct clk dpll_iva_ck = { | |||
| 668 | .parent = &dpll_sys_ref_clk, | 633 | .parent = &dpll_sys_ref_clk, |
| 669 | .dpll_data = &dpll_iva_dd, | 634 | .dpll_data = &dpll_iva_dd, |
| 670 | .init = &omap2_init_dpll_parent, | 635 | .init = &omap2_init_dpll_parent, |
| 671 | .ops = &clkops_noncore_dpll_ops, | 636 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 672 | .recalc = &omap3_dpll_recalc, | 637 | .recalc = &omap3_dpll_recalc, |
| 673 | .round_rate = &omap2_dpll_round_rate, | 638 | .round_rate = &omap2_dpll_round_rate, |
| 674 | .set_rate = &omap3_noncore_dpll_set_rate, | 639 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 675 | .flags = CLOCK_IN_OMAP4430, | ||
| 676 | }; | 640 | }; |
| 677 | 641 | ||
| 678 | static const struct clksel dpll_iva_m4_div[] = { | 642 | static const struct clksel dpll_iva_m4_div[] = { |
| @@ -690,7 +654,6 @@ static struct clk dpll_iva_m4_ck = { | |||
| 690 | .recalc = &omap2_clksel_recalc, | 654 | .recalc = &omap2_clksel_recalc, |
| 691 | .round_rate = &omap2_clksel_round_rate, | 655 | .round_rate = &omap2_clksel_round_rate, |
| 692 | .set_rate = &omap2_clksel_set_rate, | 656 | .set_rate = &omap2_clksel_set_rate, |
| 693 | .flags = CLOCK_IN_OMAP4430, | ||
| 694 | }; | 657 | }; |
| 695 | 658 | ||
| 696 | static struct clk dpll_iva_m5_ck = { | 659 | static struct clk dpll_iva_m5_ck = { |
| @@ -703,7 +666,6 @@ static struct clk dpll_iva_m5_ck = { | |||
| 703 | .recalc = &omap2_clksel_recalc, | 666 | .recalc = &omap2_clksel_recalc, |
| 704 | .round_rate = &omap2_clksel_round_rate, | 667 | .round_rate = &omap2_clksel_round_rate, |
| 705 | .set_rate = &omap2_clksel_set_rate, | 668 | .set_rate = &omap2_clksel_set_rate, |
| 706 | .flags = CLOCK_IN_OMAP4430, | ||
| 707 | }; | 669 | }; |
| 708 | 670 | ||
| 709 | /* DPLL_MPU */ | 671 | /* DPLL_MPU */ |
| @@ -731,11 +693,10 @@ static struct clk dpll_mpu_ck = { | |||
| 731 | .parent = &dpll_sys_ref_clk, | 693 | .parent = &dpll_sys_ref_clk, |
| 732 | .dpll_data = &dpll_mpu_dd, | 694 | .dpll_data = &dpll_mpu_dd, |
| 733 | .init = &omap2_init_dpll_parent, | 695 | .init = &omap2_init_dpll_parent, |
| 734 | .ops = &clkops_noncore_dpll_ops, | 696 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 735 | .recalc = &omap3_dpll_recalc, | 697 | .recalc = &omap3_dpll_recalc, |
| 736 | .round_rate = &omap2_dpll_round_rate, | 698 | .round_rate = &omap2_dpll_round_rate, |
| 737 | .set_rate = &omap3_noncore_dpll_set_rate, | 699 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 738 | .flags = CLOCK_IN_OMAP4430, | ||
| 739 | }; | 700 | }; |
| 740 | 701 | ||
| 741 | static const struct clksel dpll_mpu_m2_div[] = { | 702 | static const struct clksel dpll_mpu_m2_div[] = { |
| @@ -753,7 +714,6 @@ static struct clk dpll_mpu_m2_ck = { | |||
| 753 | .recalc = &omap2_clksel_recalc, | 714 | .recalc = &omap2_clksel_recalc, |
| 754 | .round_rate = &omap2_clksel_round_rate, | 715 | .round_rate = &omap2_clksel_round_rate, |
| 755 | .set_rate = &omap2_clksel_set_rate, | 716 | .set_rate = &omap2_clksel_set_rate, |
| 756 | .flags = CLOCK_IN_OMAP4430, | ||
| 757 | }; | 717 | }; |
| 758 | 718 | ||
| 759 | static struct clk per_hs_clk_div_ck = { | 719 | static struct clk per_hs_clk_div_ck = { |
| @@ -761,7 +721,6 @@ static struct clk per_hs_clk_div_ck = { | |||
| 761 | .parent = &dpll_abe_m3_ck, | 721 | .parent = &dpll_abe_m3_ck, |
| 762 | .ops = &clkops_null, | 722 | .ops = &clkops_null, |
| 763 | .recalc = &followparent_recalc, | 723 | .recalc = &followparent_recalc, |
| 764 | .flags = CLOCK_IN_OMAP4430, | ||
| 765 | }; | 724 | }; |
| 766 | 725 | ||
| 767 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | 726 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { |
| @@ -779,7 +738,6 @@ static struct clk per_hsd_byp_clk_mux_ck = { | |||
| 779 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | 738 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
| 780 | .ops = &clkops_null, | 739 | .ops = &clkops_null, |
| 781 | .recalc = &omap2_clksel_recalc, | 740 | .recalc = &omap2_clksel_recalc, |
| 782 | .flags = CLOCK_IN_OMAP4430, | ||
| 783 | }; | 741 | }; |
| 784 | 742 | ||
| 785 | /* DPLL_PER */ | 743 | /* DPLL_PER */ |
| @@ -807,11 +765,10 @@ static struct clk dpll_per_ck = { | |||
| 807 | .parent = &dpll_sys_ref_clk, | 765 | .parent = &dpll_sys_ref_clk, |
| 808 | .dpll_data = &dpll_per_dd, | 766 | .dpll_data = &dpll_per_dd, |
| 809 | .init = &omap2_init_dpll_parent, | 767 | .init = &omap2_init_dpll_parent, |
| 810 | .ops = &clkops_noncore_dpll_ops, | 768 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 811 | .recalc = &omap3_dpll_recalc, | 769 | .recalc = &omap3_dpll_recalc, |
| 812 | .round_rate = &omap2_dpll_round_rate, | 770 | .round_rate = &omap2_dpll_round_rate, |
| 813 | .set_rate = &omap3_noncore_dpll_set_rate, | 771 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 814 | .flags = CLOCK_IN_OMAP4430, | ||
| 815 | }; | 772 | }; |
| 816 | 773 | ||
| 817 | static const struct clksel dpll_per_m2_div[] = { | 774 | static const struct clksel dpll_per_m2_div[] = { |
| @@ -829,7 +786,6 @@ static struct clk dpll_per_m2_ck = { | |||
| 829 | .recalc = &omap2_clksel_recalc, | 786 | .recalc = &omap2_clksel_recalc, |
| 830 | .round_rate = &omap2_clksel_round_rate, | 787 | .round_rate = &omap2_clksel_round_rate, |
| 831 | .set_rate = &omap2_clksel_set_rate, | 788 | .set_rate = &omap2_clksel_set_rate, |
| 832 | .flags = CLOCK_IN_OMAP4430, | ||
| 833 | }; | 789 | }; |
| 834 | 790 | ||
| 835 | static struct clk dpll_per_m2x2_ck = { | 791 | static struct clk dpll_per_m2x2_ck = { |
| @@ -837,7 +793,6 @@ static struct clk dpll_per_m2x2_ck = { | |||
| 837 | .parent = &dpll_per_ck, | 793 | .parent = &dpll_per_ck, |
| 838 | .ops = &clkops_null, | 794 | .ops = &clkops_null, |
| 839 | .recalc = &followparent_recalc, | 795 | .recalc = &followparent_recalc, |
| 840 | .flags = CLOCK_IN_OMAP4430, | ||
| 841 | }; | 796 | }; |
| 842 | 797 | ||
| 843 | static struct clk dpll_per_m3_ck = { | 798 | static struct clk dpll_per_m3_ck = { |
| @@ -850,7 +805,6 @@ static struct clk dpll_per_m3_ck = { | |||
| 850 | .recalc = &omap2_clksel_recalc, | 805 | .recalc = &omap2_clksel_recalc, |
| 851 | .round_rate = &omap2_clksel_round_rate, | 806 | .round_rate = &omap2_clksel_round_rate, |
| 852 | .set_rate = &omap2_clksel_set_rate, | 807 | .set_rate = &omap2_clksel_set_rate, |
| 853 | .flags = CLOCK_IN_OMAP4430, | ||
| 854 | }; | 808 | }; |
| 855 | 809 | ||
| 856 | static struct clk dpll_per_m4_ck = { | 810 | static struct clk dpll_per_m4_ck = { |
| @@ -863,7 +817,6 @@ static struct clk dpll_per_m4_ck = { | |||
| 863 | .recalc = &omap2_clksel_recalc, | 817 | .recalc = &omap2_clksel_recalc, |
| 864 | .round_rate = &omap2_clksel_round_rate, | 818 | .round_rate = &omap2_clksel_round_rate, |
| 865 | .set_rate = &omap2_clksel_set_rate, | 819 | .set_rate = &omap2_clksel_set_rate, |
| 866 | .flags = CLOCK_IN_OMAP4430, | ||
| 867 | }; | 820 | }; |
| 868 | 821 | ||
| 869 | static struct clk dpll_per_m5_ck = { | 822 | static struct clk dpll_per_m5_ck = { |
| @@ -876,7 +829,6 @@ static struct clk dpll_per_m5_ck = { | |||
| 876 | .recalc = &omap2_clksel_recalc, | 829 | .recalc = &omap2_clksel_recalc, |
| 877 | .round_rate = &omap2_clksel_round_rate, | 830 | .round_rate = &omap2_clksel_round_rate, |
| 878 | .set_rate = &omap2_clksel_set_rate, | 831 | .set_rate = &omap2_clksel_set_rate, |
| 879 | .flags = CLOCK_IN_OMAP4430, | ||
| 880 | }; | 832 | }; |
| 881 | 833 | ||
| 882 | static struct clk dpll_per_m6_ck = { | 834 | static struct clk dpll_per_m6_ck = { |
| @@ -889,7 +841,6 @@ static struct clk dpll_per_m6_ck = { | |||
| 889 | .recalc = &omap2_clksel_recalc, | 841 | .recalc = &omap2_clksel_recalc, |
| 890 | .round_rate = &omap2_clksel_round_rate, | 842 | .round_rate = &omap2_clksel_round_rate, |
| 891 | .set_rate = &omap2_clksel_set_rate, | 843 | .set_rate = &omap2_clksel_set_rate, |
| 892 | .flags = CLOCK_IN_OMAP4430, | ||
| 893 | }; | 844 | }; |
| 894 | 845 | ||
| 895 | static struct clk dpll_per_m7_ck = { | 846 | static struct clk dpll_per_m7_ck = { |
| @@ -902,7 +853,6 @@ static struct clk dpll_per_m7_ck = { | |||
| 902 | .recalc = &omap2_clksel_recalc, | 853 | .recalc = &omap2_clksel_recalc, |
| 903 | .round_rate = &omap2_clksel_round_rate, | 854 | .round_rate = &omap2_clksel_round_rate, |
| 904 | .set_rate = &omap2_clksel_set_rate, | 855 | .set_rate = &omap2_clksel_set_rate, |
| 905 | .flags = CLOCK_IN_OMAP4430, | ||
| 906 | }; | 856 | }; |
| 907 | 857 | ||
| 908 | /* DPLL_UNIPRO */ | 858 | /* DPLL_UNIPRO */ |
| @@ -930,11 +880,10 @@ static struct clk dpll_unipro_ck = { | |||
| 930 | .parent = &dpll_sys_ref_clk, | 880 | .parent = &dpll_sys_ref_clk, |
| 931 | .dpll_data = &dpll_unipro_dd, | 881 | .dpll_data = &dpll_unipro_dd, |
| 932 | .init = &omap2_init_dpll_parent, | 882 | .init = &omap2_init_dpll_parent, |
| 933 | .ops = &clkops_noncore_dpll_ops, | 883 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 934 | .recalc = &omap3_dpll_recalc, | 884 | .recalc = &omap3_dpll_recalc, |
| 935 | .round_rate = &omap2_dpll_round_rate, | 885 | .round_rate = &omap2_dpll_round_rate, |
| 936 | .set_rate = &omap3_noncore_dpll_set_rate, | 886 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 937 | .flags = CLOCK_IN_OMAP4430, | ||
| 938 | }; | 887 | }; |
| 939 | 888 | ||
| 940 | static const struct clksel dpll_unipro_m2x2_div[] = { | 889 | static const struct clksel dpll_unipro_m2x2_div[] = { |
| @@ -952,7 +901,6 @@ static struct clk dpll_unipro_m2x2_ck = { | |||
| 952 | .recalc = &omap2_clksel_recalc, | 901 | .recalc = &omap2_clksel_recalc, |
| 953 | .round_rate = &omap2_clksel_round_rate, | 902 | .round_rate = &omap2_clksel_round_rate, |
| 954 | .set_rate = &omap2_clksel_set_rate, | 903 | .set_rate = &omap2_clksel_set_rate, |
| 955 | .flags = CLOCK_IN_OMAP4430, | ||
| 956 | }; | 904 | }; |
| 957 | 905 | ||
| 958 | static struct clk usb_hs_clk_div_ck = { | 906 | static struct clk usb_hs_clk_div_ck = { |
| @@ -960,7 +908,6 @@ static struct clk usb_hs_clk_div_ck = { | |||
| 960 | .parent = &dpll_abe_m3_ck, | 908 | .parent = &dpll_abe_m3_ck, |
| 961 | .ops = &clkops_null, | 909 | .ops = &clkops_null, |
| 962 | .recalc = &followparent_recalc, | 910 | .recalc = &followparent_recalc, |
| 963 | .flags = CLOCK_IN_OMAP4430, | ||
| 964 | }; | 911 | }; |
| 965 | 912 | ||
| 966 | /* DPLL_USB */ | 913 | /* DPLL_USB */ |
| @@ -980,6 +927,7 @@ static struct dpll_data dpll_usb_dd = { | |||
| 980 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | 927 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 981 | .max_divider = OMAP4430_MAX_DPLL_DIV, | 928 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 982 | .min_divider = 1, | 929 | .min_divider = 1, |
| 930 | .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL | ||
| 983 | }; | 931 | }; |
| 984 | 932 | ||
| 985 | 933 | ||
| @@ -988,11 +936,10 @@ static struct clk dpll_usb_ck = { | |||
| 988 | .parent = &dpll_sys_ref_clk, | 936 | .parent = &dpll_sys_ref_clk, |
| 989 | .dpll_data = &dpll_usb_dd, | 937 | .dpll_data = &dpll_usb_dd, |
| 990 | .init = &omap2_init_dpll_parent, | 938 | .init = &omap2_init_dpll_parent, |
| 991 | .ops = &clkops_noncore_dpll_ops, | 939 | .ops = &clkops_omap3_noncore_dpll_ops, |
| 992 | .recalc = &omap3_dpll_recalc, | 940 | .recalc = &omap3_dpll_recalc, |
| 993 | .round_rate = &omap2_dpll_round_rate, | 941 | .round_rate = &omap2_dpll_round_rate, |
| 994 | .set_rate = &omap3_noncore_dpll_set_rate, | 942 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 995 | .flags = CLOCK_IN_OMAP4430, | ||
| 996 | }; | 943 | }; |
| 997 | 944 | ||
| 998 | static struct clk dpll_usb_clkdcoldo_ck = { | 945 | static struct clk dpll_usb_clkdcoldo_ck = { |
| @@ -1000,7 +947,6 @@ static struct clk dpll_usb_clkdcoldo_ck = { | |||
| 1000 | .parent = &dpll_usb_ck, | 947 | .parent = &dpll_usb_ck, |
| 1001 | .ops = &clkops_null, | 948 | .ops = &clkops_null, |
| 1002 | .recalc = &followparent_recalc, | 949 | .recalc = &followparent_recalc, |
| 1003 | .flags = CLOCK_IN_OMAP4430, | ||
| 1004 | }; | 950 | }; |
| 1005 | 951 | ||
| 1006 | static const struct clksel dpll_usb_m2_div[] = { | 952 | static const struct clksel dpll_usb_m2_div[] = { |
| @@ -1018,7 +964,6 @@ static struct clk dpll_usb_m2_ck = { | |||
| 1018 | .recalc = &omap2_clksel_recalc, | 964 | .recalc = &omap2_clksel_recalc, |
| 1019 | .round_rate = &omap2_clksel_round_rate, | 965 | .round_rate = &omap2_clksel_round_rate, |
| 1020 | .set_rate = &omap2_clksel_set_rate, | 966 | .set_rate = &omap2_clksel_set_rate, |
| 1021 | .flags = CLOCK_IN_OMAP4430, | ||
| 1022 | }; | 967 | }; |
| 1023 | 968 | ||
| 1024 | static const struct clksel ducati_clk_mux_sel[] = { | 969 | static const struct clksel ducati_clk_mux_sel[] = { |
| @@ -1036,7 +981,6 @@ static struct clk ducati_clk_mux_ck = { | |||
| 1036 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | 981 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1037 | .ops = &clkops_null, | 982 | .ops = &clkops_null, |
| 1038 | .recalc = &omap2_clksel_recalc, | 983 | .recalc = &omap2_clksel_recalc, |
| 1039 | .flags = CLOCK_IN_OMAP4430, | ||
| 1040 | }; | 984 | }; |
| 1041 | 985 | ||
| 1042 | static struct clk func_12m_fclk = { | 986 | static struct clk func_12m_fclk = { |
| @@ -1044,7 +988,6 @@ static struct clk func_12m_fclk = { | |||
| 1044 | .parent = &dpll_per_m2x2_ck, | 988 | .parent = &dpll_per_m2x2_ck, |
| 1045 | .ops = &clkops_null, | 989 | .ops = &clkops_null, |
| 1046 | .recalc = &followparent_recalc, | 990 | .recalc = &followparent_recalc, |
| 1047 | .flags = CLOCK_IN_OMAP4430, | ||
| 1048 | }; | 991 | }; |
| 1049 | 992 | ||
| 1050 | static struct clk func_24m_clk = { | 993 | static struct clk func_24m_clk = { |
| @@ -1052,7 +995,6 @@ static struct clk func_24m_clk = { | |||
| 1052 | .parent = &dpll_per_m2_ck, | 995 | .parent = &dpll_per_m2_ck, |
| 1053 | .ops = &clkops_null, | 996 | .ops = &clkops_null, |
| 1054 | .recalc = &followparent_recalc, | 997 | .recalc = &followparent_recalc, |
| 1055 | .flags = CLOCK_IN_OMAP4430, | ||
| 1056 | }; | 998 | }; |
| 1057 | 999 | ||
| 1058 | static struct clk func_24mc_fclk = { | 1000 | static struct clk func_24mc_fclk = { |
| @@ -1060,7 +1002,6 @@ static struct clk func_24mc_fclk = { | |||
| 1060 | .parent = &dpll_per_m2x2_ck, | 1002 | .parent = &dpll_per_m2x2_ck, |
| 1061 | .ops = &clkops_null, | 1003 | .ops = &clkops_null, |
| 1062 | .recalc = &followparent_recalc, | 1004 | .recalc = &followparent_recalc, |
| 1063 | .flags = CLOCK_IN_OMAP4430, | ||
| 1064 | }; | 1005 | }; |
| 1065 | 1006 | ||
| 1066 | static const struct clksel_rate div2_4to8_rates[] = { | 1007 | static const struct clksel_rate div2_4to8_rates[] = { |
| @@ -1084,7 +1025,6 @@ static struct clk func_48m_fclk = { | |||
| 1084 | .recalc = &omap2_clksel_recalc, | 1025 | .recalc = &omap2_clksel_recalc, |
| 1085 | .round_rate = &omap2_clksel_round_rate, | 1026 | .round_rate = &omap2_clksel_round_rate, |
| 1086 | .set_rate = &omap2_clksel_set_rate, | 1027 | .set_rate = &omap2_clksel_set_rate, |
| 1087 | .flags = CLOCK_IN_OMAP4430, | ||
| 1088 | }; | 1028 | }; |
| 1089 | 1029 | ||
| 1090 | static struct clk func_48mc_fclk = { | 1030 | static struct clk func_48mc_fclk = { |
| @@ -1092,7 +1032,6 @@ static struct clk func_48mc_fclk = { | |||
| 1092 | .parent = &dpll_per_m2x2_ck, | 1032 | .parent = &dpll_per_m2x2_ck, |
| 1093 | .ops = &clkops_null, | 1033 | .ops = &clkops_null, |
| 1094 | .recalc = &followparent_recalc, | 1034 | .recalc = &followparent_recalc, |
| 1095 | .flags = CLOCK_IN_OMAP4430, | ||
| 1096 | }; | 1035 | }; |
| 1097 | 1036 | ||
| 1098 | static const struct clksel_rate div2_2to4_rates[] = { | 1037 | static const struct clksel_rate div2_2to4_rates[] = { |
| @@ -1116,7 +1055,6 @@ static struct clk func_64m_fclk = { | |||
| 1116 | .recalc = &omap2_clksel_recalc, | 1055 | .recalc = &omap2_clksel_recalc, |
| 1117 | .round_rate = &omap2_clksel_round_rate, | 1056 | .round_rate = &omap2_clksel_round_rate, |
| 1118 | .set_rate = &omap2_clksel_set_rate, | 1057 | .set_rate = &omap2_clksel_set_rate, |
| 1119 | .flags = CLOCK_IN_OMAP4430, | ||
| 1120 | }; | 1058 | }; |
| 1121 | 1059 | ||
| 1122 | static const struct clksel func_96m_fclk_div[] = { | 1060 | static const struct clksel func_96m_fclk_div[] = { |
| @@ -1134,7 +1072,6 @@ static struct clk func_96m_fclk = { | |||
| 1134 | .recalc = &omap2_clksel_recalc, | 1072 | .recalc = &omap2_clksel_recalc, |
| 1135 | .round_rate = &omap2_clksel_round_rate, | 1073 | .round_rate = &omap2_clksel_round_rate, |
| 1136 | .set_rate = &omap2_clksel_set_rate, | 1074 | .set_rate = &omap2_clksel_set_rate, |
| 1137 | .flags = CLOCK_IN_OMAP4430, | ||
| 1138 | }; | 1075 | }; |
| 1139 | 1076 | ||
| 1140 | static const struct clksel hsmmc6_fclk_sel[] = { | 1077 | static const struct clksel hsmmc6_fclk_sel[] = { |
| @@ -1148,7 +1085,6 @@ static struct clk hsmmc6_fclk = { | |||
| 1148 | .parent = &func_64m_fclk, | 1085 | .parent = &func_64m_fclk, |
| 1149 | .ops = &clkops_null, | 1086 | .ops = &clkops_null, |
| 1150 | .recalc = &followparent_recalc, | 1087 | .recalc = &followparent_recalc, |
| 1151 | .flags = CLOCK_IN_OMAP4430, | ||
| 1152 | }; | 1088 | }; |
| 1153 | 1089 | ||
| 1154 | static const struct clksel_rate div2_1to8_rates[] = { | 1090 | static const struct clksel_rate div2_1to8_rates[] = { |
| @@ -1172,7 +1108,6 @@ static struct clk init_60m_fclk = { | |||
| 1172 | .recalc = &omap2_clksel_recalc, | 1108 | .recalc = &omap2_clksel_recalc, |
| 1173 | .round_rate = &omap2_clksel_round_rate, | 1109 | .round_rate = &omap2_clksel_round_rate, |
| 1174 | .set_rate = &omap2_clksel_set_rate, | 1110 | .set_rate = &omap2_clksel_set_rate, |
| 1175 | .flags = CLOCK_IN_OMAP4430, | ||
| 1176 | }; | 1111 | }; |
| 1177 | 1112 | ||
| 1178 | static const struct clksel l3_div_div[] = { | 1113 | static const struct clksel l3_div_div[] = { |
| @@ -1190,7 +1125,6 @@ static struct clk l3_div_ck = { | |||
| 1190 | .recalc = &omap2_clksel_recalc, | 1125 | .recalc = &omap2_clksel_recalc, |
| 1191 | .round_rate = &omap2_clksel_round_rate, | 1126 | .round_rate = &omap2_clksel_round_rate, |
| 1192 | .set_rate = &omap2_clksel_set_rate, | 1127 | .set_rate = &omap2_clksel_set_rate, |
| 1193 | .flags = CLOCK_IN_OMAP4430, | ||
| 1194 | }; | 1128 | }; |
| 1195 | 1129 | ||
| 1196 | static const struct clksel l4_div_div[] = { | 1130 | static const struct clksel l4_div_div[] = { |
| @@ -1208,7 +1142,6 @@ static struct clk l4_div_ck = { | |||
| 1208 | .recalc = &omap2_clksel_recalc, | 1142 | .recalc = &omap2_clksel_recalc, |
| 1209 | .round_rate = &omap2_clksel_round_rate, | 1143 | .round_rate = &omap2_clksel_round_rate, |
| 1210 | .set_rate = &omap2_clksel_set_rate, | 1144 | .set_rate = &omap2_clksel_set_rate, |
| 1211 | .flags = CLOCK_IN_OMAP4430, | ||
| 1212 | }; | 1145 | }; |
| 1213 | 1146 | ||
| 1214 | static struct clk lp_clk_div_ck = { | 1147 | static struct clk lp_clk_div_ck = { |
| @@ -1216,7 +1149,6 @@ static struct clk lp_clk_div_ck = { | |||
| 1216 | .parent = &dpll_abe_m2x2_ck, | 1149 | .parent = &dpll_abe_m2x2_ck, |
| 1217 | .ops = &clkops_null, | 1150 | .ops = &clkops_null, |
| 1218 | .recalc = &followparent_recalc, | 1151 | .recalc = &followparent_recalc, |
| 1219 | .flags = CLOCK_IN_OMAP4430, | ||
| 1220 | }; | 1152 | }; |
| 1221 | 1153 | ||
| 1222 | static const struct clksel l4_wkup_clk_mux_sel[] = { | 1154 | static const struct clksel l4_wkup_clk_mux_sel[] = { |
| @@ -1234,7 +1166,6 @@ static struct clk l4_wkup_clk_mux_ck = { | |||
| 1234 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | 1166 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1235 | .ops = &clkops_null, | 1167 | .ops = &clkops_null, |
| 1236 | .recalc = &omap2_clksel_recalc, | 1168 | .recalc = &omap2_clksel_recalc, |
| 1237 | .flags = CLOCK_IN_OMAP4430, | ||
| 1238 | }; | 1169 | }; |
| 1239 | 1170 | ||
| 1240 | static const struct clksel per_abe_nc_fclk_div[] = { | 1171 | static const struct clksel per_abe_nc_fclk_div[] = { |
| @@ -1252,7 +1183,6 @@ static struct clk per_abe_nc_fclk = { | |||
| 1252 | .recalc = &omap2_clksel_recalc, | 1183 | .recalc = &omap2_clksel_recalc, |
| 1253 | .round_rate = &omap2_clksel_round_rate, | 1184 | .round_rate = &omap2_clksel_round_rate, |
| 1254 | .set_rate = &omap2_clksel_set_rate, | 1185 | .set_rate = &omap2_clksel_set_rate, |
| 1255 | .flags = CLOCK_IN_OMAP4430, | ||
| 1256 | }; | 1186 | }; |
| 1257 | 1187 | ||
| 1258 | static const struct clksel mcasp2_fclk_sel[] = { | 1188 | static const struct clksel mcasp2_fclk_sel[] = { |
| @@ -1266,7 +1196,6 @@ static struct clk mcasp2_fclk = { | |||
| 1266 | .parent = &func_96m_fclk, | 1196 | .parent = &func_96m_fclk, |
| 1267 | .ops = &clkops_null, | 1197 | .ops = &clkops_null, |
| 1268 | .recalc = &followparent_recalc, | 1198 | .recalc = &followparent_recalc, |
| 1269 | .flags = CLOCK_IN_OMAP4430, | ||
| 1270 | }; | 1199 | }; |
| 1271 | 1200 | ||
| 1272 | static struct clk mcasp3_fclk = { | 1201 | static struct clk mcasp3_fclk = { |
| @@ -1274,7 +1203,6 @@ static struct clk mcasp3_fclk = { | |||
| 1274 | .parent = &func_96m_fclk, | 1203 | .parent = &func_96m_fclk, |
| 1275 | .ops = &clkops_null, | 1204 | .ops = &clkops_null, |
| 1276 | .recalc = &followparent_recalc, | 1205 | .recalc = &followparent_recalc, |
| 1277 | .flags = CLOCK_IN_OMAP4430, | ||
| 1278 | }; | 1206 | }; |
| 1279 | 1207 | ||
| 1280 | static struct clk ocp_abe_iclk = { | 1208 | static struct clk ocp_abe_iclk = { |
| @@ -1282,7 +1210,6 @@ static struct clk ocp_abe_iclk = { | |||
| 1282 | .parent = &aess_fclk, | 1210 | .parent = &aess_fclk, |
| 1283 | .ops = &clkops_null, | 1211 | .ops = &clkops_null, |
| 1284 | .recalc = &followparent_recalc, | 1212 | .recalc = &followparent_recalc, |
| 1285 | .flags = CLOCK_IN_OMAP4430, | ||
| 1286 | }; | 1213 | }; |
| 1287 | 1214 | ||
| 1288 | static struct clk per_abe_24m_fclk = { | 1215 | static struct clk per_abe_24m_fclk = { |
| @@ -1290,7 +1217,6 @@ static struct clk per_abe_24m_fclk = { | |||
| 1290 | .parent = &dpll_abe_m2_ck, | 1217 | .parent = &dpll_abe_m2_ck, |
| 1291 | .ops = &clkops_null, | 1218 | .ops = &clkops_null, |
| 1292 | .recalc = &followparent_recalc, | 1219 | .recalc = &followparent_recalc, |
| 1293 | .flags = CLOCK_IN_OMAP4430, | ||
| 1294 | }; | 1220 | }; |
| 1295 | 1221 | ||
| 1296 | static const struct clksel pmd_stm_clock_mux_sel[] = { | 1222 | static const struct clksel pmd_stm_clock_mux_sel[] = { |
| @@ -1305,7 +1231,6 @@ static struct clk pmd_stm_clock_mux_ck = { | |||
| 1305 | .parent = &sys_clkin_ck, | 1231 | .parent = &sys_clkin_ck, |
| 1306 | .ops = &clkops_null, | 1232 | .ops = &clkops_null, |
| 1307 | .recalc = &followparent_recalc, | 1233 | .recalc = &followparent_recalc, |
| 1308 | .flags = CLOCK_IN_OMAP4430, | ||
| 1309 | }; | 1234 | }; |
| 1310 | 1235 | ||
| 1311 | static struct clk pmd_trace_clk_mux_ck = { | 1236 | static struct clk pmd_trace_clk_mux_ck = { |
| @@ -1313,7 +1238,6 @@ static struct clk pmd_trace_clk_mux_ck = { | |||
| 1313 | .parent = &sys_clkin_ck, | 1238 | .parent = &sys_clkin_ck, |
| 1314 | .ops = &clkops_null, | 1239 | .ops = &clkops_null, |
| 1315 | .recalc = &followparent_recalc, | 1240 | .recalc = &followparent_recalc, |
| 1316 | .flags = CLOCK_IN_OMAP4430, | ||
| 1317 | }; | 1241 | }; |
| 1318 | 1242 | ||
| 1319 | static struct clk syc_clk_div_ck = { | 1243 | static struct clk syc_clk_div_ck = { |
| @@ -1326,13 +1250,12 @@ static struct clk syc_clk_div_ck = { | |||
| 1326 | .recalc = &omap2_clksel_recalc, | 1250 | .recalc = &omap2_clksel_recalc, |
| 1327 | .round_rate = &omap2_clksel_round_rate, | 1251 | .round_rate = &omap2_clksel_round_rate, |
| 1328 | .set_rate = &omap2_clksel_set_rate, | 1252 | .set_rate = &omap2_clksel_set_rate, |
| 1329 | .flags = CLOCK_IN_OMAP4430, | ||
| 1330 | }; | 1253 | }; |
| 1331 | 1254 | ||
| 1332 | /* Leaf clocks controlled by modules */ | 1255 | /* Leaf clocks controlled by modules */ |
| 1333 | 1256 | ||
| 1334 | static struct clk aes1_ck = { | 1257 | static struct clk aes1_fck = { |
| 1335 | .name = "aes1_ck", | 1258 | .name = "aes1_fck", |
| 1336 | .ops = &clkops_omap2_dflt, | 1259 | .ops = &clkops_omap2_dflt, |
| 1337 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, | 1260 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, |
| 1338 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1261 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1341,8 +1264,8 @@ static struct clk aes1_ck = { | |||
| 1341 | .recalc = &followparent_recalc, | 1264 | .recalc = &followparent_recalc, |
| 1342 | }; | 1265 | }; |
| 1343 | 1266 | ||
| 1344 | static struct clk aes2_ck = { | 1267 | static struct clk aes2_fck = { |
| 1345 | .name = "aes2_ck", | 1268 | .name = "aes2_fck", |
| 1346 | .ops = &clkops_omap2_dflt, | 1269 | .ops = &clkops_omap2_dflt, |
| 1347 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, | 1270 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, |
| 1348 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1271 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1351,8 +1274,8 @@ static struct clk aes2_ck = { | |||
| 1351 | .recalc = &followparent_recalc, | 1274 | .recalc = &followparent_recalc, |
| 1352 | }; | 1275 | }; |
| 1353 | 1276 | ||
| 1354 | static struct clk aess_ck = { | 1277 | static struct clk aess_fck = { |
| 1355 | .name = "aess_ck", | 1278 | .name = "aess_fck", |
| 1356 | .ops = &clkops_omap2_dflt, | 1279 | .ops = &clkops_omap2_dflt, |
| 1357 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | 1280 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
| 1358 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1281 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1361,8 +1284,8 @@ static struct clk aess_ck = { | |||
| 1361 | .recalc = &followparent_recalc, | 1284 | .recalc = &followparent_recalc, |
| 1362 | }; | 1285 | }; |
| 1363 | 1286 | ||
| 1364 | static struct clk cust_efuse_ck = { | 1287 | static struct clk cust_efuse_fck = { |
| 1365 | .name = "cust_efuse_ck", | 1288 | .name = "cust_efuse_fck", |
| 1366 | .ops = &clkops_omap2_dflt, | 1289 | .ops = &clkops_omap2_dflt, |
| 1367 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, | 1290 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
| 1368 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1291 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1371,8 +1294,8 @@ static struct clk cust_efuse_ck = { | |||
| 1371 | .recalc = &followparent_recalc, | 1294 | .recalc = &followparent_recalc, |
| 1372 | }; | 1295 | }; |
| 1373 | 1296 | ||
| 1374 | static struct clk des3des_ck = { | 1297 | static struct clk des3des_fck = { |
| 1375 | .name = "des3des_ck", | 1298 | .name = "des3des_fck", |
| 1376 | .ops = &clkops_omap2_dflt, | 1299 | .ops = &clkops_omap2_dflt, |
| 1377 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | 1300 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, |
| 1378 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1301 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1397,7 +1320,6 @@ static struct clk dmic_sync_mux_ck = { | |||
| 1397 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1320 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1398 | .ops = &clkops_null, | 1321 | .ops = &clkops_null, |
| 1399 | .recalc = &omap2_clksel_recalc, | 1322 | .recalc = &omap2_clksel_recalc, |
| 1400 | .flags = CLOCK_IN_OMAP4430, | ||
| 1401 | }; | 1323 | }; |
| 1402 | 1324 | ||
| 1403 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | 1325 | static const struct clksel func_dmic_abe_gfclk_sel[] = { |
| @@ -1407,9 +1329,9 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = { | |||
| 1407 | { .parent = NULL }, | 1329 | { .parent = NULL }, |
| 1408 | }; | 1330 | }; |
| 1409 | 1331 | ||
| 1410 | /* Merged func_dmic_abe_gfclk into dmic_ck */ | 1332 | /* Merged func_dmic_abe_gfclk into dmic */ |
| 1411 | static struct clk dmic_ck = { | 1333 | static struct clk dmic_fck = { |
| 1412 | .name = "dmic_ck", | 1334 | .name = "dmic_fck", |
| 1413 | .parent = &dmic_sync_mux_ck, | 1335 | .parent = &dmic_sync_mux_ck, |
| 1414 | .clksel = func_dmic_abe_gfclk_sel, | 1336 | .clksel = func_dmic_abe_gfclk_sel, |
| 1415 | .init = &omap2_init_clksel_parent, | 1337 | .init = &omap2_init_clksel_parent, |
| @@ -1417,14 +1339,13 @@ static struct clk dmic_ck = { | |||
| 1417 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1339 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1418 | .ops = &clkops_omap2_dflt, | 1340 | .ops = &clkops_omap2_dflt, |
| 1419 | .recalc = &omap2_clksel_recalc, | 1341 | .recalc = &omap2_clksel_recalc, |
| 1420 | .flags = CLOCK_IN_OMAP4430, | ||
| 1421 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | 1342 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1422 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1343 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1423 | .clkdm_name = "abe_clkdm", | 1344 | .clkdm_name = "abe_clkdm", |
| 1424 | }; | 1345 | }; |
| 1425 | 1346 | ||
| 1426 | static struct clk dss_ck = { | 1347 | static struct clk dss_fck = { |
| 1427 | .name = "dss_ck", | 1348 | .name = "dss_fck", |
| 1428 | .ops = &clkops_omap2_dflt, | 1349 | .ops = &clkops_omap2_dflt, |
| 1429 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1350 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1430 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1351 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1433,8 +1354,8 @@ static struct clk dss_ck = { | |||
| 1433 | .recalc = &followparent_recalc, | 1354 | .recalc = &followparent_recalc, |
| 1434 | }; | 1355 | }; |
| 1435 | 1356 | ||
| 1436 | static struct clk ducati_ck = { | 1357 | static struct clk ducati_ick = { |
| 1437 | .name = "ducati_ck", | 1358 | .name = "ducati_ick", |
| 1438 | .ops = &clkops_omap2_dflt, | 1359 | .ops = &clkops_omap2_dflt, |
| 1439 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | 1360 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, |
| 1440 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1361 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1443,8 +1364,8 @@ static struct clk ducati_ck = { | |||
| 1443 | .recalc = &followparent_recalc, | 1364 | .recalc = &followparent_recalc, |
| 1444 | }; | 1365 | }; |
| 1445 | 1366 | ||
| 1446 | static struct clk emif1_ck = { | 1367 | static struct clk emif1_ick = { |
| 1447 | .name = "emif1_ck", | 1368 | .name = "emif1_ick", |
| 1448 | .ops = &clkops_omap2_dflt, | 1369 | .ops = &clkops_omap2_dflt, |
| 1449 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | 1370 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, |
| 1450 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1371 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1453,8 +1374,8 @@ static struct clk emif1_ck = { | |||
| 1453 | .recalc = &followparent_recalc, | 1374 | .recalc = &followparent_recalc, |
| 1454 | }; | 1375 | }; |
| 1455 | 1376 | ||
| 1456 | static struct clk emif2_ck = { | 1377 | static struct clk emif2_ick = { |
| 1457 | .name = "emif2_ck", | 1378 | .name = "emif2_ick", |
| 1458 | .ops = &clkops_omap2_dflt, | 1379 | .ops = &clkops_omap2_dflt, |
| 1459 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | 1380 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, |
| 1460 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1381 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1468,9 +1389,9 @@ static const struct clksel fdif_fclk_div[] = { | |||
| 1468 | { .parent = NULL }, | 1389 | { .parent = NULL }, |
| 1469 | }; | 1390 | }; |
| 1470 | 1391 | ||
| 1471 | /* Merged fdif_fclk into fdif_ck */ | 1392 | /* Merged fdif_fclk into fdif */ |
| 1472 | static struct clk fdif_ck = { | 1393 | static struct clk fdif_fck = { |
| 1473 | .name = "fdif_ck", | 1394 | .name = "fdif_fck", |
| 1474 | .parent = &dpll_per_m4_ck, | 1395 | .parent = &dpll_per_m4_ck, |
| 1475 | .clksel = fdif_fclk_div, | 1396 | .clksel = fdif_fclk_div, |
| 1476 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | 1397 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| @@ -1479,7 +1400,6 @@ static struct clk fdif_ck = { | |||
| 1479 | .recalc = &omap2_clksel_recalc, | 1400 | .recalc = &omap2_clksel_recalc, |
| 1480 | .round_rate = &omap2_clksel_round_rate, | 1401 | .round_rate = &omap2_clksel_round_rate, |
| 1481 | .set_rate = &omap2_clksel_set_rate, | 1402 | .set_rate = &omap2_clksel_set_rate, |
| 1482 | .flags = CLOCK_IN_OMAP4430, | ||
| 1483 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | 1403 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| 1484 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1404 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1485 | .clkdm_name = "iss_clkdm", | 1405 | .clkdm_name = "iss_clkdm", |
| @@ -1500,7 +1420,6 @@ static struct clk per_sgx_fclk = { | |||
| 1500 | .recalc = &omap2_clksel_recalc, | 1420 | .recalc = &omap2_clksel_recalc, |
| 1501 | .round_rate = &omap2_clksel_round_rate, | 1421 | .round_rate = &omap2_clksel_round_rate, |
| 1502 | .set_rate = &omap2_clksel_set_rate, | 1422 | .set_rate = &omap2_clksel_set_rate, |
| 1503 | .flags = CLOCK_IN_OMAP4430, | ||
| 1504 | }; | 1423 | }; |
| 1505 | 1424 | ||
| 1506 | static const struct clksel sgx_clk_mux_sel[] = { | 1425 | static const struct clksel sgx_clk_mux_sel[] = { |
| @@ -1509,9 +1428,9 @@ static const struct clksel sgx_clk_mux_sel[] = { | |||
| 1509 | { .parent = NULL }, | 1428 | { .parent = NULL }, |
| 1510 | }; | 1429 | }; |
| 1511 | 1430 | ||
| 1512 | /* Merged sgx_clk_mux into gfx_ck */ | 1431 | /* Merged sgx_clk_mux into gfx */ |
| 1513 | static struct clk gfx_ck = { | 1432 | static struct clk gfx_fck = { |
| 1514 | .name = "gfx_ck", | 1433 | .name = "gfx_fck", |
| 1515 | .parent = &dpll_core_m7_ck, | 1434 | .parent = &dpll_core_m7_ck, |
| 1516 | .clksel = sgx_clk_mux_sel, | 1435 | .clksel = sgx_clk_mux_sel, |
| 1517 | .init = &omap2_init_clksel_parent, | 1436 | .init = &omap2_init_clksel_parent, |
| @@ -1519,14 +1438,13 @@ static struct clk gfx_ck = { | |||
| 1519 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, | 1438 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, |
| 1520 | .ops = &clkops_omap2_dflt, | 1439 | .ops = &clkops_omap2_dflt, |
| 1521 | .recalc = &omap2_clksel_recalc, | 1440 | .recalc = &omap2_clksel_recalc, |
| 1522 | .flags = CLOCK_IN_OMAP4430, | ||
| 1523 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, | 1441 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
| 1524 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1442 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1525 | .clkdm_name = "l3_gfx_clkdm", | 1443 | .clkdm_name = "l3_gfx_clkdm", |
| 1526 | }; | 1444 | }; |
| 1527 | 1445 | ||
| 1528 | static struct clk gpio1_ck = { | 1446 | static struct clk gpio1_ick = { |
| 1529 | .name = "gpio1_ck", | 1447 | .name = "gpio1_ick", |
| 1530 | .ops = &clkops_omap2_dflt, | 1448 | .ops = &clkops_omap2_dflt, |
| 1531 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | 1449 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
| 1532 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1450 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1535,8 +1453,8 @@ static struct clk gpio1_ck = { | |||
| 1535 | .recalc = &followparent_recalc, | 1453 | .recalc = &followparent_recalc, |
| 1536 | }; | 1454 | }; |
| 1537 | 1455 | ||
| 1538 | static struct clk gpio2_ck = { | 1456 | static struct clk gpio2_ick = { |
| 1539 | .name = "gpio2_ck", | 1457 | .name = "gpio2_ick", |
| 1540 | .ops = &clkops_omap2_dflt, | 1458 | .ops = &clkops_omap2_dflt, |
| 1541 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | 1459 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
| 1542 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1460 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1545,8 +1463,8 @@ static struct clk gpio2_ck = { | |||
| 1545 | .recalc = &followparent_recalc, | 1463 | .recalc = &followparent_recalc, |
| 1546 | }; | 1464 | }; |
| 1547 | 1465 | ||
| 1548 | static struct clk gpio3_ck = { | 1466 | static struct clk gpio3_ick = { |
| 1549 | .name = "gpio3_ck", | 1467 | .name = "gpio3_ick", |
| 1550 | .ops = &clkops_omap2_dflt, | 1468 | .ops = &clkops_omap2_dflt, |
| 1551 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | 1469 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
| 1552 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1470 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1555,8 +1473,8 @@ static struct clk gpio3_ck = { | |||
| 1555 | .recalc = &followparent_recalc, | 1473 | .recalc = &followparent_recalc, |
| 1556 | }; | 1474 | }; |
| 1557 | 1475 | ||
| 1558 | static struct clk gpio4_ck = { | 1476 | static struct clk gpio4_ick = { |
| 1559 | .name = "gpio4_ck", | 1477 | .name = "gpio4_ick", |
| 1560 | .ops = &clkops_omap2_dflt, | 1478 | .ops = &clkops_omap2_dflt, |
| 1561 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | 1479 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
| 1562 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1480 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1565,8 +1483,8 @@ static struct clk gpio4_ck = { | |||
| 1565 | .recalc = &followparent_recalc, | 1483 | .recalc = &followparent_recalc, |
| 1566 | }; | 1484 | }; |
| 1567 | 1485 | ||
| 1568 | static struct clk gpio5_ck = { | 1486 | static struct clk gpio5_ick = { |
| 1569 | .name = "gpio5_ck", | 1487 | .name = "gpio5_ick", |
| 1570 | .ops = &clkops_omap2_dflt, | 1488 | .ops = &clkops_omap2_dflt, |
| 1571 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | 1489 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
| 1572 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1490 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1575,8 +1493,8 @@ static struct clk gpio5_ck = { | |||
| 1575 | .recalc = &followparent_recalc, | 1493 | .recalc = &followparent_recalc, |
| 1576 | }; | 1494 | }; |
| 1577 | 1495 | ||
| 1578 | static struct clk gpio6_ck = { | 1496 | static struct clk gpio6_ick = { |
| 1579 | .name = "gpio6_ck", | 1497 | .name = "gpio6_ick", |
| 1580 | .ops = &clkops_omap2_dflt, | 1498 | .ops = &clkops_omap2_dflt, |
| 1581 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | 1499 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, |
| 1582 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1500 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1585,8 +1503,8 @@ static struct clk gpio6_ck = { | |||
| 1585 | .recalc = &followparent_recalc, | 1503 | .recalc = &followparent_recalc, |
| 1586 | }; | 1504 | }; |
| 1587 | 1505 | ||
| 1588 | static struct clk gpmc_ck = { | 1506 | static struct clk gpmc_ick = { |
| 1589 | .name = "gpmc_ck", | 1507 | .name = "gpmc_ick", |
| 1590 | .ops = &clkops_omap2_dflt, | 1508 | .ops = &clkops_omap2_dflt, |
| 1591 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, | 1509 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, |
| 1592 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1510 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1601,9 +1519,12 @@ static const struct clksel dmt1_clk_mux_sel[] = { | |||
| 1601 | { .parent = NULL }, | 1519 | { .parent = NULL }, |
| 1602 | }; | 1520 | }; |
| 1603 | 1521 | ||
| 1604 | /* Merged dmt1_clk_mux into gptimer1_ck */ | 1522 | /* |
| 1605 | static struct clk gptimer1_ck = { | 1523 | * Merged dmt1_clk_mux into gptimer1 |
| 1606 | .name = "gptimer1_ck", | 1524 | * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention |
| 1525 | */ | ||
| 1526 | static struct clk gpt1_fck = { | ||
| 1527 | .name = "gpt1_fck", | ||
| 1607 | .parent = &sys_clkin_ck, | 1528 | .parent = &sys_clkin_ck, |
| 1608 | .clksel = dmt1_clk_mux_sel, | 1529 | .clksel = dmt1_clk_mux_sel, |
| 1609 | .init = &omap2_init_clksel_parent, | 1530 | .init = &omap2_init_clksel_parent, |
| @@ -1611,15 +1532,17 @@ static struct clk gptimer1_ck = { | |||
| 1611 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1532 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1612 | .ops = &clkops_omap2_dflt, | 1533 | .ops = &clkops_omap2_dflt, |
| 1613 | .recalc = &omap2_clksel_recalc, | 1534 | .recalc = &omap2_clksel_recalc, |
| 1614 | .flags = CLOCK_IN_OMAP4430, | ||
| 1615 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | 1535 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, |
| 1616 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1536 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1617 | .clkdm_name = "l4_wkup_clkdm", | 1537 | .clkdm_name = "l4_wkup_clkdm", |
| 1618 | }; | 1538 | }; |
| 1619 | 1539 | ||
| 1620 | /* Merged cm2_dm10_mux into gptimer10_ck */ | 1540 | /* |
| 1621 | static struct clk gptimer10_ck = { | 1541 | * Merged cm2_dm10_mux into gptimer10 |
| 1622 | .name = "gptimer10_ck", | 1542 | * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention |
| 1543 | */ | ||
| 1544 | static struct clk gpt10_fck = { | ||
| 1545 | .name = "gpt10_fck", | ||
| 1623 | .parent = &sys_clkin_ck, | 1546 | .parent = &sys_clkin_ck, |
| 1624 | .clksel = dmt1_clk_mux_sel, | 1547 | .clksel = dmt1_clk_mux_sel, |
| 1625 | .init = &omap2_init_clksel_parent, | 1548 | .init = &omap2_init_clksel_parent, |
| @@ -1627,15 +1550,17 @@ static struct clk gptimer10_ck = { | |||
| 1627 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1550 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1628 | .ops = &clkops_omap2_dflt, | 1551 | .ops = &clkops_omap2_dflt, |
| 1629 | .recalc = &omap2_clksel_recalc, | 1552 | .recalc = &omap2_clksel_recalc, |
| 1630 | .flags = CLOCK_IN_OMAP4430, | ||
| 1631 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | 1553 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, |
| 1632 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1554 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1633 | .clkdm_name = "l4_per_clkdm", | 1555 | .clkdm_name = "l4_per_clkdm", |
| 1634 | }; | 1556 | }; |
| 1635 | 1557 | ||
| 1636 | /* Merged cm2_dm11_mux into gptimer11_ck */ | 1558 | /* |
| 1637 | static struct clk gptimer11_ck = { | 1559 | * Merged cm2_dm11_mux into gptimer11 |
| 1638 | .name = "gptimer11_ck", | 1560 | * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention |
| 1561 | */ | ||
| 1562 | static struct clk gpt11_fck = { | ||
| 1563 | .name = "gpt11_fck", | ||
| 1639 | .parent = &sys_clkin_ck, | 1564 | .parent = &sys_clkin_ck, |
| 1640 | .clksel = dmt1_clk_mux_sel, | 1565 | .clksel = dmt1_clk_mux_sel, |
| 1641 | .init = &omap2_init_clksel_parent, | 1566 | .init = &omap2_init_clksel_parent, |
| @@ -1643,15 +1568,17 @@ static struct clk gptimer11_ck = { | |||
| 1643 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1568 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1644 | .ops = &clkops_omap2_dflt, | 1569 | .ops = &clkops_omap2_dflt, |
| 1645 | .recalc = &omap2_clksel_recalc, | 1570 | .recalc = &omap2_clksel_recalc, |
| 1646 | .flags = CLOCK_IN_OMAP4430, | ||
| 1647 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | 1571 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, |
| 1648 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1572 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1649 | .clkdm_name = "l4_per_clkdm", | 1573 | .clkdm_name = "l4_per_clkdm", |
| 1650 | }; | 1574 | }; |
| 1651 | 1575 | ||
| 1652 | /* Merged cm2_dm2_mux into gptimer2_ck */ | 1576 | /* |
| 1653 | static struct clk gptimer2_ck = { | 1577 | * Merged cm2_dm2_mux into gptimer2 |
| 1654 | .name = "gptimer2_ck", | 1578 | * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention |
| 1579 | */ | ||
| 1580 | static struct clk gpt2_fck = { | ||
| 1581 | .name = "gpt2_fck", | ||
| 1655 | .parent = &sys_clkin_ck, | 1582 | .parent = &sys_clkin_ck, |
| 1656 | .clksel = dmt1_clk_mux_sel, | 1583 | .clksel = dmt1_clk_mux_sel, |
| 1657 | .init = &omap2_init_clksel_parent, | 1584 | .init = &omap2_init_clksel_parent, |
| @@ -1659,15 +1586,17 @@ static struct clk gptimer2_ck = { | |||
| 1659 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1586 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1660 | .ops = &clkops_omap2_dflt, | 1587 | .ops = &clkops_omap2_dflt, |
| 1661 | .recalc = &omap2_clksel_recalc, | 1588 | .recalc = &omap2_clksel_recalc, |
| 1662 | .flags = CLOCK_IN_OMAP4430, | ||
| 1663 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | 1589 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, |
| 1664 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1590 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1665 | .clkdm_name = "l4_per_clkdm", | 1591 | .clkdm_name = "l4_per_clkdm", |
| 1666 | }; | 1592 | }; |
| 1667 | 1593 | ||
| 1668 | /* Merged cm2_dm3_mux into gptimer3_ck */ | 1594 | /* |
| 1669 | static struct clk gptimer3_ck = { | 1595 | * Merged cm2_dm3_mux into gptimer3 |
| 1670 | .name = "gptimer3_ck", | 1596 | * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention |
| 1597 | */ | ||
| 1598 | static struct clk gpt3_fck = { | ||
| 1599 | .name = "gpt3_fck", | ||
| 1671 | .parent = &sys_clkin_ck, | 1600 | .parent = &sys_clkin_ck, |
| 1672 | .clksel = dmt1_clk_mux_sel, | 1601 | .clksel = dmt1_clk_mux_sel, |
| 1673 | .init = &omap2_init_clksel_parent, | 1602 | .init = &omap2_init_clksel_parent, |
| @@ -1675,15 +1604,17 @@ static struct clk gptimer3_ck = { | |||
| 1675 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1604 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1676 | .ops = &clkops_omap2_dflt, | 1605 | .ops = &clkops_omap2_dflt, |
| 1677 | .recalc = &omap2_clksel_recalc, | 1606 | .recalc = &omap2_clksel_recalc, |
| 1678 | .flags = CLOCK_IN_OMAP4430, | ||
| 1679 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | 1607 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, |
| 1680 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1608 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1681 | .clkdm_name = "l4_per_clkdm", | 1609 | .clkdm_name = "l4_per_clkdm", |
| 1682 | }; | 1610 | }; |
| 1683 | 1611 | ||
| 1684 | /* Merged cm2_dm4_mux into gptimer4_ck */ | 1612 | /* |
| 1685 | static struct clk gptimer4_ck = { | 1613 | * Merged cm2_dm4_mux into gptimer4 |
| 1686 | .name = "gptimer4_ck", | 1614 | * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention |
| 1615 | */ | ||
| 1616 | static struct clk gpt4_fck = { | ||
| 1617 | .name = "gpt4_fck", | ||
| 1687 | .parent = &sys_clkin_ck, | 1618 | .parent = &sys_clkin_ck, |
| 1688 | .clksel = dmt1_clk_mux_sel, | 1619 | .clksel = dmt1_clk_mux_sel, |
| 1689 | .init = &omap2_init_clksel_parent, | 1620 | .init = &omap2_init_clksel_parent, |
| @@ -1691,7 +1622,6 @@ static struct clk gptimer4_ck = { | |||
| 1691 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1622 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1692 | .ops = &clkops_omap2_dflt, | 1623 | .ops = &clkops_omap2_dflt, |
| 1693 | .recalc = &omap2_clksel_recalc, | 1624 | .recalc = &omap2_clksel_recalc, |
| 1694 | .flags = CLOCK_IN_OMAP4430, | ||
| 1695 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | 1625 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, |
| 1696 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1626 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1697 | .clkdm_name = "l4_per_clkdm", | 1627 | .clkdm_name = "l4_per_clkdm", |
| @@ -1703,9 +1633,12 @@ static const struct clksel timer5_sync_mux_sel[] = { | |||
| 1703 | { .parent = NULL }, | 1633 | { .parent = NULL }, |
| 1704 | }; | 1634 | }; |
| 1705 | 1635 | ||
| 1706 | /* Merged timer5_sync_mux into gptimer5_ck */ | 1636 | /* |
| 1707 | static struct clk gptimer5_ck = { | 1637 | * Merged timer5_sync_mux into gptimer5 |
| 1708 | .name = "gptimer5_ck", | 1638 | * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention |
| 1639 | */ | ||
| 1640 | static struct clk gpt5_fck = { | ||
| 1641 | .name = "gpt5_fck", | ||
| 1709 | .parent = &syc_clk_div_ck, | 1642 | .parent = &syc_clk_div_ck, |
| 1710 | .clksel = timer5_sync_mux_sel, | 1643 | .clksel = timer5_sync_mux_sel, |
| 1711 | .init = &omap2_init_clksel_parent, | 1644 | .init = &omap2_init_clksel_parent, |
| @@ -1713,15 +1646,17 @@ static struct clk gptimer5_ck = { | |||
| 1713 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1646 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1714 | .ops = &clkops_omap2_dflt, | 1647 | .ops = &clkops_omap2_dflt, |
| 1715 | .recalc = &omap2_clksel_recalc, | 1648 | .recalc = &omap2_clksel_recalc, |
| 1716 | .flags = CLOCK_IN_OMAP4430, | ||
| 1717 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | 1649 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, |
| 1718 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1650 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1719 | .clkdm_name = "abe_clkdm", | 1651 | .clkdm_name = "abe_clkdm", |
| 1720 | }; | 1652 | }; |
| 1721 | 1653 | ||
| 1722 | /* Merged timer6_sync_mux into gptimer6_ck */ | 1654 | /* |
| 1723 | static struct clk gptimer6_ck = { | 1655 | * Merged timer6_sync_mux into gptimer6 |
| 1724 | .name = "gptimer6_ck", | 1656 | * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention |
| 1657 | */ | ||
| 1658 | static struct clk gpt6_fck = { | ||
| 1659 | .name = "gpt6_fck", | ||
| 1725 | .parent = &syc_clk_div_ck, | 1660 | .parent = &syc_clk_div_ck, |
| 1726 | .clksel = timer5_sync_mux_sel, | 1661 | .clksel = timer5_sync_mux_sel, |
| 1727 | .init = &omap2_init_clksel_parent, | 1662 | .init = &omap2_init_clksel_parent, |
| @@ -1729,15 +1664,17 @@ static struct clk gptimer6_ck = { | |||
| 1729 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1664 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1730 | .ops = &clkops_omap2_dflt, | 1665 | .ops = &clkops_omap2_dflt, |
| 1731 | .recalc = &omap2_clksel_recalc, | 1666 | .recalc = &omap2_clksel_recalc, |
| 1732 | .flags = CLOCK_IN_OMAP4430, | ||
| 1733 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | 1667 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, |
| 1734 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1668 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1735 | .clkdm_name = "abe_clkdm", | 1669 | .clkdm_name = "abe_clkdm", |
| 1736 | }; | 1670 | }; |
| 1737 | 1671 | ||
| 1738 | /* Merged timer7_sync_mux into gptimer7_ck */ | 1672 | /* |
| 1739 | static struct clk gptimer7_ck = { | 1673 | * Merged timer7_sync_mux into gptimer7 |
| 1740 | .name = "gptimer7_ck", | 1674 | * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention |
| 1675 | */ | ||
| 1676 | static struct clk gpt7_fck = { | ||
| 1677 | .name = "gpt7_fck", | ||
| 1741 | .parent = &syc_clk_div_ck, | 1678 | .parent = &syc_clk_div_ck, |
| 1742 | .clksel = timer5_sync_mux_sel, | 1679 | .clksel = timer5_sync_mux_sel, |
| 1743 | .init = &omap2_init_clksel_parent, | 1680 | .init = &omap2_init_clksel_parent, |
| @@ -1745,15 +1682,17 @@ static struct clk gptimer7_ck = { | |||
| 1745 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1682 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1746 | .ops = &clkops_omap2_dflt, | 1683 | .ops = &clkops_omap2_dflt, |
| 1747 | .recalc = &omap2_clksel_recalc, | 1684 | .recalc = &omap2_clksel_recalc, |
| 1748 | .flags = CLOCK_IN_OMAP4430, | ||
| 1749 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | 1685 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, |
| 1750 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1686 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1751 | .clkdm_name = "abe_clkdm", | 1687 | .clkdm_name = "abe_clkdm", |
| 1752 | }; | 1688 | }; |
| 1753 | 1689 | ||
| 1754 | /* Merged timer8_sync_mux into gptimer8_ck */ | 1690 | /* |
| 1755 | static struct clk gptimer8_ck = { | 1691 | * Merged timer8_sync_mux into gptimer8 |
| 1756 | .name = "gptimer8_ck", | 1692 | * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention |
| 1693 | */ | ||
| 1694 | static struct clk gpt8_fck = { | ||
| 1695 | .name = "gpt8_fck", | ||
| 1757 | .parent = &syc_clk_div_ck, | 1696 | .parent = &syc_clk_div_ck, |
| 1758 | .clksel = timer5_sync_mux_sel, | 1697 | .clksel = timer5_sync_mux_sel, |
| 1759 | .init = &omap2_init_clksel_parent, | 1698 | .init = &omap2_init_clksel_parent, |
| @@ -1761,15 +1700,17 @@ static struct clk gptimer8_ck = { | |||
| 1761 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1700 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1762 | .ops = &clkops_omap2_dflt, | 1701 | .ops = &clkops_omap2_dflt, |
| 1763 | .recalc = &omap2_clksel_recalc, | 1702 | .recalc = &omap2_clksel_recalc, |
| 1764 | .flags = CLOCK_IN_OMAP4430, | ||
| 1765 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | 1703 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, |
| 1766 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1704 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1767 | .clkdm_name = "abe_clkdm", | 1705 | .clkdm_name = "abe_clkdm", |
| 1768 | }; | 1706 | }; |
| 1769 | 1707 | ||
| 1770 | /* Merged cm2_dm9_mux into gptimer9_ck */ | 1708 | /* |
| 1771 | static struct clk gptimer9_ck = { | 1709 | * Merged cm2_dm9_mux into gptimer9 |
| 1772 | .name = "gptimer9_ck", | 1710 | * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention |
| 1711 | */ | ||
| 1712 | static struct clk gpt9_fck = { | ||
| 1713 | .name = "gpt9_fck", | ||
| 1773 | .parent = &sys_clkin_ck, | 1714 | .parent = &sys_clkin_ck, |
| 1774 | .clksel = dmt1_clk_mux_sel, | 1715 | .clksel = dmt1_clk_mux_sel, |
| 1775 | .init = &omap2_init_clksel_parent, | 1716 | .init = &omap2_init_clksel_parent, |
| @@ -1777,14 +1718,13 @@ static struct clk gptimer9_ck = { | |||
| 1777 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1718 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 1778 | .ops = &clkops_omap2_dflt, | 1719 | .ops = &clkops_omap2_dflt, |
| 1779 | .recalc = &omap2_clksel_recalc, | 1720 | .recalc = &omap2_clksel_recalc, |
| 1780 | .flags = CLOCK_IN_OMAP4430, | ||
| 1781 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | 1721 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, |
| 1782 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1722 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1783 | .clkdm_name = "l4_per_clkdm", | 1723 | .clkdm_name = "l4_per_clkdm", |
| 1784 | }; | 1724 | }; |
| 1785 | 1725 | ||
| 1786 | static struct clk hdq1w_ck = { | 1726 | static struct clk hdq1w_fck = { |
| 1787 | .name = "hdq1w_ck", | 1727 | .name = "hdq1w_fck", |
| 1788 | .ops = &clkops_omap2_dflt, | 1728 | .ops = &clkops_omap2_dflt, |
| 1789 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | 1729 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, |
| 1790 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1730 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1793,9 +1733,9 @@ static struct clk hdq1w_ck = { | |||
| 1793 | .recalc = &followparent_recalc, | 1733 | .recalc = &followparent_recalc, |
| 1794 | }; | 1734 | }; |
| 1795 | 1735 | ||
| 1796 | /* Merged hsi_fclk into hsi_ck */ | 1736 | /* Merged hsi_fclk into hsi */ |
| 1797 | static struct clk hsi_ck = { | 1737 | static struct clk hsi_ick = { |
| 1798 | .name = "hsi_ck", | 1738 | .name = "hsi_ick", |
| 1799 | .parent = &dpll_per_m2x2_ck, | 1739 | .parent = &dpll_per_m2x2_ck, |
| 1800 | .clksel = per_sgx_fclk_div, | 1740 | .clksel = per_sgx_fclk_div, |
| 1801 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | 1741 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
| @@ -1804,14 +1744,13 @@ static struct clk hsi_ck = { | |||
| 1804 | .recalc = &omap2_clksel_recalc, | 1744 | .recalc = &omap2_clksel_recalc, |
| 1805 | .round_rate = &omap2_clksel_round_rate, | 1745 | .round_rate = &omap2_clksel_round_rate, |
| 1806 | .set_rate = &omap2_clksel_set_rate, | 1746 | .set_rate = &omap2_clksel_set_rate, |
| 1807 | .flags = CLOCK_IN_OMAP4430, | ||
| 1808 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | 1747 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
| 1809 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1748 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1810 | .clkdm_name = "l3_init_clkdm", | 1749 | .clkdm_name = "l3_init_clkdm", |
| 1811 | }; | 1750 | }; |
| 1812 | 1751 | ||
| 1813 | static struct clk i2c1_ck = { | 1752 | static struct clk i2c1_fck = { |
| 1814 | .name = "i2c1_ck", | 1753 | .name = "i2c1_fck", |
| 1815 | .ops = &clkops_omap2_dflt, | 1754 | .ops = &clkops_omap2_dflt, |
| 1816 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | 1755 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
| 1817 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1756 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1820,8 +1759,8 @@ static struct clk i2c1_ck = { | |||
| 1820 | .recalc = &followparent_recalc, | 1759 | .recalc = &followparent_recalc, |
| 1821 | }; | 1760 | }; |
| 1822 | 1761 | ||
| 1823 | static struct clk i2c2_ck = { | 1762 | static struct clk i2c2_fck = { |
| 1824 | .name = "i2c2_ck", | 1763 | .name = "i2c2_fck", |
| 1825 | .ops = &clkops_omap2_dflt, | 1764 | .ops = &clkops_omap2_dflt, |
| 1826 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | 1765 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
| 1827 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1766 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1830,8 +1769,8 @@ static struct clk i2c2_ck = { | |||
| 1830 | .recalc = &followparent_recalc, | 1769 | .recalc = &followparent_recalc, |
| 1831 | }; | 1770 | }; |
| 1832 | 1771 | ||
| 1833 | static struct clk i2c3_ck = { | 1772 | static struct clk i2c3_fck = { |
| 1834 | .name = "i2c3_ck", | 1773 | .name = "i2c3_fck", |
| 1835 | .ops = &clkops_omap2_dflt, | 1774 | .ops = &clkops_omap2_dflt, |
| 1836 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | 1775 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
| 1837 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1776 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1840,8 +1779,8 @@ static struct clk i2c3_ck = { | |||
| 1840 | .recalc = &followparent_recalc, | 1779 | .recalc = &followparent_recalc, |
| 1841 | }; | 1780 | }; |
| 1842 | 1781 | ||
| 1843 | static struct clk i2c4_ck = { | 1782 | static struct clk i2c4_fck = { |
| 1844 | .name = "i2c4_ck", | 1783 | .name = "i2c4_fck", |
| 1845 | .ops = &clkops_omap2_dflt, | 1784 | .ops = &clkops_omap2_dflt, |
| 1846 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | 1785 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
| 1847 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1786 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1850,8 +1789,8 @@ static struct clk i2c4_ck = { | |||
| 1850 | .recalc = &followparent_recalc, | 1789 | .recalc = &followparent_recalc, |
| 1851 | }; | 1790 | }; |
| 1852 | 1791 | ||
| 1853 | static struct clk iss_ck = { | 1792 | static struct clk iss_fck = { |
| 1854 | .name = "iss_ck", | 1793 | .name = "iss_fck", |
| 1855 | .ops = &clkops_omap2_dflt, | 1794 | .ops = &clkops_omap2_dflt, |
| 1856 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | 1795 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
| 1857 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1796 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1860,8 +1799,8 @@ static struct clk iss_ck = { | |||
| 1860 | .recalc = &followparent_recalc, | 1799 | .recalc = &followparent_recalc, |
| 1861 | }; | 1800 | }; |
| 1862 | 1801 | ||
| 1863 | static struct clk ivahd_ck = { | 1802 | static struct clk ivahd_ick = { |
| 1864 | .name = "ivahd_ck", | 1803 | .name = "ivahd_ick", |
| 1865 | .ops = &clkops_omap2_dflt, | 1804 | .ops = &clkops_omap2_dflt, |
| 1866 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | 1805 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, |
| 1867 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1806 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1870,8 +1809,8 @@ static struct clk ivahd_ck = { | |||
| 1870 | .recalc = &followparent_recalc, | 1809 | .recalc = &followparent_recalc, |
| 1871 | }; | 1810 | }; |
| 1872 | 1811 | ||
| 1873 | static struct clk keyboard_ck = { | 1812 | static struct clk keyboard_fck = { |
| 1874 | .name = "keyboard_ck", | 1813 | .name = "keyboard_fck", |
| 1875 | .ops = &clkops_omap2_dflt, | 1814 | .ops = &clkops_omap2_dflt, |
| 1876 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | 1815 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, |
| 1877 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1816 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -1880,8 +1819,8 @@ static struct clk keyboard_ck = { | |||
| 1880 | .recalc = &followparent_recalc, | 1819 | .recalc = &followparent_recalc, |
| 1881 | }; | 1820 | }; |
| 1882 | 1821 | ||
| 1883 | static struct clk l3_instr_interconnect_ck = { | 1822 | static struct clk l3_instr_interconnect_ick = { |
| 1884 | .name = "l3_instr_interconnect_ck", | 1823 | .name = "l3_instr_interconnect_ick", |
| 1885 | .ops = &clkops_omap2_dflt, | 1824 | .ops = &clkops_omap2_dflt, |
| 1886 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | 1825 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, |
| 1887 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1826 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1890,8 +1829,8 @@ static struct clk l3_instr_interconnect_ck = { | |||
| 1890 | .recalc = &followparent_recalc, | 1829 | .recalc = &followparent_recalc, |
| 1891 | }; | 1830 | }; |
| 1892 | 1831 | ||
| 1893 | static struct clk l3_interconnect_3_ck = { | 1832 | static struct clk l3_interconnect_3_ick = { |
| 1894 | .name = "l3_interconnect_3_ck", | 1833 | .name = "l3_interconnect_3_ick", |
| 1895 | .ops = &clkops_omap2_dflt, | 1834 | .ops = &clkops_omap2_dflt, |
| 1896 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | 1835 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, |
| 1897 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1836 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -1909,7 +1848,6 @@ static struct clk mcasp_sync_mux_ck = { | |||
| 1909 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1848 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1910 | .ops = &clkops_null, | 1849 | .ops = &clkops_null, |
| 1911 | .recalc = &omap2_clksel_recalc, | 1850 | .recalc = &omap2_clksel_recalc, |
| 1912 | .flags = CLOCK_IN_OMAP4430, | ||
| 1913 | }; | 1851 | }; |
| 1914 | 1852 | ||
| 1915 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | 1853 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { |
| @@ -1919,9 +1857,9 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |||
| 1919 | { .parent = NULL }, | 1857 | { .parent = NULL }, |
| 1920 | }; | 1858 | }; |
| 1921 | 1859 | ||
| 1922 | /* Merged func_mcasp_abe_gfclk into mcasp_ck */ | 1860 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
| 1923 | static struct clk mcasp_ck = { | 1861 | static struct clk mcasp_fck = { |
| 1924 | .name = "mcasp_ck", | 1862 | .name = "mcasp_fck", |
| 1925 | .parent = &mcasp_sync_mux_ck, | 1863 | .parent = &mcasp_sync_mux_ck, |
| 1926 | .clksel = func_mcasp_abe_gfclk_sel, | 1864 | .clksel = func_mcasp_abe_gfclk_sel, |
| 1927 | .init = &omap2_init_clksel_parent, | 1865 | .init = &omap2_init_clksel_parent, |
| @@ -1929,7 +1867,6 @@ static struct clk mcasp_ck = { | |||
| 1929 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1867 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1930 | .ops = &clkops_omap2_dflt, | 1868 | .ops = &clkops_omap2_dflt, |
| 1931 | .recalc = &omap2_clksel_recalc, | 1869 | .recalc = &omap2_clksel_recalc, |
| 1932 | .flags = CLOCK_IN_OMAP4430, | ||
| 1933 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | 1870 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1934 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1871 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1935 | .clkdm_name = "abe_clkdm", | 1872 | .clkdm_name = "abe_clkdm", |
| @@ -1944,7 +1881,6 @@ static struct clk mcbsp1_sync_mux_ck = { | |||
| 1944 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1881 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1945 | .ops = &clkops_null, | 1882 | .ops = &clkops_null, |
| 1946 | .recalc = &omap2_clksel_recalc, | 1883 | .recalc = &omap2_clksel_recalc, |
| 1947 | .flags = CLOCK_IN_OMAP4430, | ||
| 1948 | }; | 1884 | }; |
| 1949 | 1885 | ||
| 1950 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | 1886 | static const struct clksel func_mcbsp1_gfclk_sel[] = { |
| @@ -1954,9 +1890,9 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = { | |||
| 1954 | { .parent = NULL }, | 1890 | { .parent = NULL }, |
| 1955 | }; | 1891 | }; |
| 1956 | 1892 | ||
| 1957 | /* Merged func_mcbsp1_gfclk into mcbsp1_ck */ | 1893 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
| 1958 | static struct clk mcbsp1_ck = { | 1894 | static struct clk mcbsp1_fck = { |
| 1959 | .name = "mcbsp1_ck", | 1895 | .name = "mcbsp1_fck", |
| 1960 | .parent = &mcbsp1_sync_mux_ck, | 1896 | .parent = &mcbsp1_sync_mux_ck, |
| 1961 | .clksel = func_mcbsp1_gfclk_sel, | 1897 | .clksel = func_mcbsp1_gfclk_sel, |
| 1962 | .init = &omap2_init_clksel_parent, | 1898 | .init = &omap2_init_clksel_parent, |
| @@ -1964,7 +1900,6 @@ static struct clk mcbsp1_ck = { | |||
| 1964 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1900 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1965 | .ops = &clkops_omap2_dflt, | 1901 | .ops = &clkops_omap2_dflt, |
| 1966 | .recalc = &omap2_clksel_recalc, | 1902 | .recalc = &omap2_clksel_recalc, |
| 1967 | .flags = CLOCK_IN_OMAP4430, | ||
| 1968 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | 1903 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1969 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1904 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1970 | .clkdm_name = "abe_clkdm", | 1905 | .clkdm_name = "abe_clkdm", |
| @@ -1979,7 +1914,6 @@ static struct clk mcbsp2_sync_mux_ck = { | |||
| 1979 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1914 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1980 | .ops = &clkops_null, | 1915 | .ops = &clkops_null, |
| 1981 | .recalc = &omap2_clksel_recalc, | 1916 | .recalc = &omap2_clksel_recalc, |
| 1982 | .flags = CLOCK_IN_OMAP4430, | ||
| 1983 | }; | 1917 | }; |
| 1984 | 1918 | ||
| 1985 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | 1919 | static const struct clksel func_mcbsp2_gfclk_sel[] = { |
| @@ -1989,9 +1923,9 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = { | |||
| 1989 | { .parent = NULL }, | 1923 | { .parent = NULL }, |
| 1990 | }; | 1924 | }; |
| 1991 | 1925 | ||
| 1992 | /* Merged func_mcbsp2_gfclk into mcbsp2_ck */ | 1926 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
| 1993 | static struct clk mcbsp2_ck = { | 1927 | static struct clk mcbsp2_fck = { |
| 1994 | .name = "mcbsp2_ck", | 1928 | .name = "mcbsp2_fck", |
| 1995 | .parent = &mcbsp2_sync_mux_ck, | 1929 | .parent = &mcbsp2_sync_mux_ck, |
| 1996 | .clksel = func_mcbsp2_gfclk_sel, | 1930 | .clksel = func_mcbsp2_gfclk_sel, |
| 1997 | .init = &omap2_init_clksel_parent, | 1931 | .init = &omap2_init_clksel_parent, |
| @@ -1999,7 +1933,6 @@ static struct clk mcbsp2_ck = { | |||
| 1999 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1933 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 2000 | .ops = &clkops_omap2_dflt, | 1934 | .ops = &clkops_omap2_dflt, |
| 2001 | .recalc = &omap2_clksel_recalc, | 1935 | .recalc = &omap2_clksel_recalc, |
| 2002 | .flags = CLOCK_IN_OMAP4430, | ||
| 2003 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | 1936 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 2004 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1937 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2005 | .clkdm_name = "abe_clkdm", | 1938 | .clkdm_name = "abe_clkdm", |
| @@ -2014,7 +1947,6 @@ static struct clk mcbsp3_sync_mux_ck = { | |||
| 2014 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1947 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 2015 | .ops = &clkops_null, | 1948 | .ops = &clkops_null, |
| 2016 | .recalc = &omap2_clksel_recalc, | 1949 | .recalc = &omap2_clksel_recalc, |
| 2017 | .flags = CLOCK_IN_OMAP4430, | ||
| 2018 | }; | 1950 | }; |
| 2019 | 1951 | ||
| 2020 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | 1952 | static const struct clksel func_mcbsp3_gfclk_sel[] = { |
| @@ -2024,9 +1956,9 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = { | |||
| 2024 | { .parent = NULL }, | 1956 | { .parent = NULL }, |
| 2025 | }; | 1957 | }; |
| 2026 | 1958 | ||
| 2027 | /* Merged func_mcbsp3_gfclk into mcbsp3_ck */ | 1959 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
| 2028 | static struct clk mcbsp3_ck = { | 1960 | static struct clk mcbsp3_fck = { |
| 2029 | .name = "mcbsp3_ck", | 1961 | .name = "mcbsp3_fck", |
| 2030 | .parent = &mcbsp3_sync_mux_ck, | 1962 | .parent = &mcbsp3_sync_mux_ck, |
| 2031 | .clksel = func_mcbsp3_gfclk_sel, | 1963 | .clksel = func_mcbsp3_gfclk_sel, |
| 2032 | .init = &omap2_init_clksel_parent, | 1964 | .init = &omap2_init_clksel_parent, |
| @@ -2034,7 +1966,6 @@ static struct clk mcbsp3_ck = { | |||
| 2034 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1966 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 2035 | .ops = &clkops_omap2_dflt, | 1967 | .ops = &clkops_omap2_dflt, |
| 2036 | .recalc = &omap2_clksel_recalc, | 1968 | .recalc = &omap2_clksel_recalc, |
| 2037 | .flags = CLOCK_IN_OMAP4430, | ||
| 2038 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | 1969 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 2039 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1970 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2040 | .clkdm_name = "abe_clkdm", | 1971 | .clkdm_name = "abe_clkdm", |
| @@ -2049,7 +1980,6 @@ static struct clk mcbsp4_sync_mux_ck = { | |||
| 2049 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1980 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 2050 | .ops = &clkops_null, | 1981 | .ops = &clkops_null, |
| 2051 | .recalc = &omap2_clksel_recalc, | 1982 | .recalc = &omap2_clksel_recalc, |
| 2052 | .flags = CLOCK_IN_OMAP4430, | ||
| 2053 | }; | 1983 | }; |
| 2054 | 1984 | ||
| 2055 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | 1985 | static const struct clksel per_mcbsp4_gfclk_sel[] = { |
| @@ -2058,9 +1988,9 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = { | |||
| 2058 | { .parent = NULL }, | 1988 | { .parent = NULL }, |
| 2059 | }; | 1989 | }; |
| 2060 | 1990 | ||
| 2061 | /* Merged per_mcbsp4_gfclk into mcbsp4_ck */ | 1991 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
| 2062 | static struct clk mcbsp4_ck = { | 1992 | static struct clk mcbsp4_fck = { |
| 2063 | .name = "mcbsp4_ck", | 1993 | .name = "mcbsp4_fck", |
| 2064 | .parent = &mcbsp4_sync_mux_ck, | 1994 | .parent = &mcbsp4_sync_mux_ck, |
| 2065 | .clksel = per_mcbsp4_gfclk_sel, | 1995 | .clksel = per_mcbsp4_gfclk_sel, |
| 2066 | .init = &omap2_init_clksel_parent, | 1996 | .init = &omap2_init_clksel_parent, |
| @@ -2068,14 +1998,13 @@ static struct clk mcbsp4_ck = { | |||
| 2068 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, | 1998 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, |
| 2069 | .ops = &clkops_omap2_dflt, | 1999 | .ops = &clkops_omap2_dflt, |
| 2070 | .recalc = &omap2_clksel_recalc, | 2000 | .recalc = &omap2_clksel_recalc, |
| 2071 | .flags = CLOCK_IN_OMAP4430, | ||
| 2072 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | 2001 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 2073 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2002 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2074 | .clkdm_name = "l4_per_clkdm", | 2003 | .clkdm_name = "l4_per_clkdm", |
| 2075 | }; | 2004 | }; |
| 2076 | 2005 | ||
| 2077 | static struct clk mcspi1_ck = { | 2006 | static struct clk mcspi1_fck = { |
| 2078 | .name = "mcspi1_ck", | 2007 | .name = "mcspi1_fck", |
| 2079 | .ops = &clkops_omap2_dflt, | 2008 | .ops = &clkops_omap2_dflt, |
| 2080 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | 2009 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, |
| 2081 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2010 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2084,8 +2013,8 @@ static struct clk mcspi1_ck = { | |||
| 2084 | .recalc = &followparent_recalc, | 2013 | .recalc = &followparent_recalc, |
| 2085 | }; | 2014 | }; |
| 2086 | 2015 | ||
| 2087 | static struct clk mcspi2_ck = { | 2016 | static struct clk mcspi2_fck = { |
| 2088 | .name = "mcspi2_ck", | 2017 | .name = "mcspi2_fck", |
| 2089 | .ops = &clkops_omap2_dflt, | 2018 | .ops = &clkops_omap2_dflt, |
| 2090 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | 2019 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, |
| 2091 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2020 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2094,8 +2023,8 @@ static struct clk mcspi2_ck = { | |||
| 2094 | .recalc = &followparent_recalc, | 2023 | .recalc = &followparent_recalc, |
| 2095 | }; | 2024 | }; |
| 2096 | 2025 | ||
| 2097 | static struct clk mcspi3_ck = { | 2026 | static struct clk mcspi3_fck = { |
| 2098 | .name = "mcspi3_ck", | 2027 | .name = "mcspi3_fck", |
| 2099 | .ops = &clkops_omap2_dflt, | 2028 | .ops = &clkops_omap2_dflt, |
| 2100 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | 2029 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, |
| 2101 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2030 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2104,8 +2033,8 @@ static struct clk mcspi3_ck = { | |||
| 2104 | .recalc = &followparent_recalc, | 2033 | .recalc = &followparent_recalc, |
| 2105 | }; | 2034 | }; |
| 2106 | 2035 | ||
| 2107 | static struct clk mcspi4_ck = { | 2036 | static struct clk mcspi4_fck = { |
| 2108 | .name = "mcspi4_ck", | 2037 | .name = "mcspi4_fck", |
| 2109 | .ops = &clkops_omap2_dflt, | 2038 | .ops = &clkops_omap2_dflt, |
| 2110 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | 2039 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, |
| 2111 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2040 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2114,9 +2043,9 @@ static struct clk mcspi4_ck = { | |||
| 2114 | .recalc = &followparent_recalc, | 2043 | .recalc = &followparent_recalc, |
| 2115 | }; | 2044 | }; |
| 2116 | 2045 | ||
| 2117 | /* Merged hsmmc1_fclk into mmc1_ck */ | 2046 | /* Merged hsmmc1_fclk into mmc1 */ |
| 2118 | static struct clk mmc1_ck = { | 2047 | static struct clk mmc1_fck = { |
| 2119 | .name = "mmc1_ck", | 2048 | .name = "mmc1_fck", |
| 2120 | .parent = &func_64m_fclk, | 2049 | .parent = &func_64m_fclk, |
| 2121 | .clksel = hsmmc6_fclk_sel, | 2050 | .clksel = hsmmc6_fclk_sel, |
| 2122 | .init = &omap2_init_clksel_parent, | 2051 | .init = &omap2_init_clksel_parent, |
| @@ -2124,15 +2053,14 @@ static struct clk mmc1_ck = { | |||
| 2124 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 2053 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2125 | .ops = &clkops_omap2_dflt, | 2054 | .ops = &clkops_omap2_dflt, |
| 2126 | .recalc = &omap2_clksel_recalc, | 2055 | .recalc = &omap2_clksel_recalc, |
| 2127 | .flags = CLOCK_IN_OMAP4430, | ||
| 2128 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | 2056 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
| 2129 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2057 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2130 | .clkdm_name = "l3_init_clkdm", | 2058 | .clkdm_name = "l3_init_clkdm", |
| 2131 | }; | 2059 | }; |
| 2132 | 2060 | ||
| 2133 | /* Merged hsmmc2_fclk into mmc2_ck */ | 2061 | /* Merged hsmmc2_fclk into mmc2 */ |
| 2134 | static struct clk mmc2_ck = { | 2062 | static struct clk mmc2_fck = { |
| 2135 | .name = "mmc2_ck", | 2063 | .name = "mmc2_fck", |
| 2136 | .parent = &func_64m_fclk, | 2064 | .parent = &func_64m_fclk, |
| 2137 | .clksel = hsmmc6_fclk_sel, | 2065 | .clksel = hsmmc6_fclk_sel, |
| 2138 | .init = &omap2_init_clksel_parent, | 2066 | .init = &omap2_init_clksel_parent, |
| @@ -2140,14 +2068,13 @@ static struct clk mmc2_ck = { | |||
| 2140 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 2068 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2141 | .ops = &clkops_omap2_dflt, | 2069 | .ops = &clkops_omap2_dflt, |
| 2142 | .recalc = &omap2_clksel_recalc, | 2070 | .recalc = &omap2_clksel_recalc, |
| 2143 | .flags = CLOCK_IN_OMAP4430, | ||
| 2144 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | 2071 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
| 2145 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2072 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2146 | .clkdm_name = "l3_init_clkdm", | 2073 | .clkdm_name = "l3_init_clkdm", |
| 2147 | }; | 2074 | }; |
| 2148 | 2075 | ||
| 2149 | static struct clk mmc3_ck = { | 2076 | static struct clk mmc3_fck = { |
| 2150 | .name = "mmc3_ck", | 2077 | .name = "mmc3_fck", |
| 2151 | .ops = &clkops_omap2_dflt, | 2078 | .ops = &clkops_omap2_dflt, |
| 2152 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | 2079 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, |
| 2153 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2080 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2156,8 +2083,8 @@ static struct clk mmc3_ck = { | |||
| 2156 | .recalc = &followparent_recalc, | 2083 | .recalc = &followparent_recalc, |
| 2157 | }; | 2084 | }; |
| 2158 | 2085 | ||
| 2159 | static struct clk mmc4_ck = { | 2086 | static struct clk mmc4_fck = { |
| 2160 | .name = "mmc4_ck", | 2087 | .name = "mmc4_fck", |
| 2161 | .ops = &clkops_omap2_dflt, | 2088 | .ops = &clkops_omap2_dflt, |
| 2162 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | 2089 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, |
| 2163 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2090 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2166,8 +2093,8 @@ static struct clk mmc4_ck = { | |||
| 2166 | .recalc = &followparent_recalc, | 2093 | .recalc = &followparent_recalc, |
| 2167 | }; | 2094 | }; |
| 2168 | 2095 | ||
| 2169 | static struct clk mmc5_ck = { | 2096 | static struct clk mmc5_fck = { |
| 2170 | .name = "mmc5_ck", | 2097 | .name = "mmc5_fck", |
| 2171 | .ops = &clkops_omap2_dflt, | 2098 | .ops = &clkops_omap2_dflt, |
| 2172 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | 2099 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, |
| 2173 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2100 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2176,8 +2103,8 @@ static struct clk mmc5_ck = { | |||
| 2176 | .recalc = &followparent_recalc, | 2103 | .recalc = &followparent_recalc, |
| 2177 | }; | 2104 | }; |
| 2178 | 2105 | ||
| 2179 | static struct clk ocp_wp1_ck = { | 2106 | static struct clk ocp_wp1_ick = { |
| 2180 | .name = "ocp_wp1_ck", | 2107 | .name = "ocp_wp1_ick", |
| 2181 | .ops = &clkops_omap2_dflt, | 2108 | .ops = &clkops_omap2_dflt, |
| 2182 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | 2109 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, |
| 2183 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2110 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2186,8 +2113,8 @@ static struct clk ocp_wp1_ck = { | |||
| 2186 | .recalc = &followparent_recalc, | 2113 | .recalc = &followparent_recalc, |
| 2187 | }; | 2114 | }; |
| 2188 | 2115 | ||
| 2189 | static struct clk pdm_ck = { | 2116 | static struct clk pdm_fck = { |
| 2190 | .name = "pdm_ck", | 2117 | .name = "pdm_fck", |
| 2191 | .ops = &clkops_omap2_dflt, | 2118 | .ops = &clkops_omap2_dflt, |
| 2192 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | 2119 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, |
| 2193 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2120 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2196,8 +2123,8 @@ static struct clk pdm_ck = { | |||
| 2196 | .recalc = &followparent_recalc, | 2123 | .recalc = &followparent_recalc, |
| 2197 | }; | 2124 | }; |
| 2198 | 2125 | ||
| 2199 | static struct clk pkaeip29_ck = { | 2126 | static struct clk pkaeip29_fck = { |
| 2200 | .name = "pkaeip29_ck", | 2127 | .name = "pkaeip29_fck", |
| 2201 | .ops = &clkops_omap2_dflt, | 2128 | .ops = &clkops_omap2_dflt, |
| 2202 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, | 2129 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
| 2203 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2130 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2206,8 +2133,8 @@ static struct clk pkaeip29_ck = { | |||
| 2206 | .recalc = &followparent_recalc, | 2133 | .recalc = &followparent_recalc, |
| 2207 | }; | 2134 | }; |
| 2208 | 2135 | ||
| 2209 | static struct clk rng_ck = { | 2136 | static struct clk rng_ick = { |
| 2210 | .name = "rng_ck", | 2137 | .name = "rng_ick", |
| 2211 | .ops = &clkops_omap2_dflt, | 2138 | .ops = &clkops_omap2_dflt, |
| 2212 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, | 2139 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, |
| 2213 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2140 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2216,8 +2143,8 @@ static struct clk rng_ck = { | |||
| 2216 | .recalc = &followparent_recalc, | 2143 | .recalc = &followparent_recalc, |
| 2217 | }; | 2144 | }; |
| 2218 | 2145 | ||
| 2219 | static struct clk sha2md51_ck = { | 2146 | static struct clk sha2md51_fck = { |
| 2220 | .name = "sha2md51_ck", | 2147 | .name = "sha2md51_fck", |
| 2221 | .ops = &clkops_omap2_dflt, | 2148 | .ops = &clkops_omap2_dflt, |
| 2222 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | 2149 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, |
| 2223 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2150 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2226,8 +2153,8 @@ static struct clk sha2md51_ck = { | |||
| 2226 | .recalc = &followparent_recalc, | 2153 | .recalc = &followparent_recalc, |
| 2227 | }; | 2154 | }; |
| 2228 | 2155 | ||
| 2229 | static struct clk sl2_ck = { | 2156 | static struct clk sl2_ick = { |
| 2230 | .name = "sl2_ck", | 2157 | .name = "sl2_ick", |
| 2231 | .ops = &clkops_omap2_dflt, | 2158 | .ops = &clkops_omap2_dflt, |
| 2232 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | 2159 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, |
| 2233 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2160 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2236,8 +2163,8 @@ static struct clk sl2_ck = { | |||
| 2236 | .recalc = &followparent_recalc, | 2163 | .recalc = &followparent_recalc, |
| 2237 | }; | 2164 | }; |
| 2238 | 2165 | ||
| 2239 | static struct clk slimbus1_ck = { | 2166 | static struct clk slimbus1_fck = { |
| 2240 | .name = "slimbus1_ck", | 2167 | .name = "slimbus1_fck", |
| 2241 | .ops = &clkops_omap2_dflt, | 2168 | .ops = &clkops_omap2_dflt, |
| 2242 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | 2169 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2243 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2170 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2246,8 +2173,8 @@ static struct clk slimbus1_ck = { | |||
| 2246 | .recalc = &followparent_recalc, | 2173 | .recalc = &followparent_recalc, |
| 2247 | }; | 2174 | }; |
| 2248 | 2175 | ||
| 2249 | static struct clk slimbus2_ck = { | 2176 | static struct clk slimbus2_fck = { |
| 2250 | .name = "slimbus2_ck", | 2177 | .name = "slimbus2_fck", |
| 2251 | .ops = &clkops_omap2_dflt, | 2178 | .ops = &clkops_omap2_dflt, |
| 2252 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | 2179 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2253 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2180 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2256,8 +2183,8 @@ static struct clk slimbus2_ck = { | |||
| 2256 | .recalc = &followparent_recalc, | 2183 | .recalc = &followparent_recalc, |
| 2257 | }; | 2184 | }; |
| 2258 | 2185 | ||
| 2259 | static struct clk sr_core_ck = { | 2186 | static struct clk sr_core_fck = { |
| 2260 | .name = "sr_core_ck", | 2187 | .name = "sr_core_fck", |
| 2261 | .ops = &clkops_omap2_dflt, | 2188 | .ops = &clkops_omap2_dflt, |
| 2262 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | 2189 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, |
| 2263 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2190 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2266,8 +2193,8 @@ static struct clk sr_core_ck = { | |||
| 2266 | .recalc = &followparent_recalc, | 2193 | .recalc = &followparent_recalc, |
| 2267 | }; | 2194 | }; |
| 2268 | 2195 | ||
| 2269 | static struct clk sr_iva_ck = { | 2196 | static struct clk sr_iva_fck = { |
| 2270 | .name = "sr_iva_ck", | 2197 | .name = "sr_iva_fck", |
| 2271 | .ops = &clkops_omap2_dflt, | 2198 | .ops = &clkops_omap2_dflt, |
| 2272 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | 2199 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, |
| 2273 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2200 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2276,8 +2203,8 @@ static struct clk sr_iva_ck = { | |||
| 2276 | .recalc = &followparent_recalc, | 2203 | .recalc = &followparent_recalc, |
| 2277 | }; | 2204 | }; |
| 2278 | 2205 | ||
| 2279 | static struct clk sr_mpu_ck = { | 2206 | static struct clk sr_mpu_fck = { |
| 2280 | .name = "sr_mpu_ck", | 2207 | .name = "sr_mpu_fck", |
| 2281 | .ops = &clkops_omap2_dflt, | 2208 | .ops = &clkops_omap2_dflt, |
| 2282 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | 2209 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, |
| 2283 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2210 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2286,8 +2213,8 @@ static struct clk sr_mpu_ck = { | |||
| 2286 | .recalc = &followparent_recalc, | 2213 | .recalc = &followparent_recalc, |
| 2287 | }; | 2214 | }; |
| 2288 | 2215 | ||
| 2289 | static struct clk tesla_ck = { | 2216 | static struct clk tesla_ick = { |
| 2290 | .name = "tesla_ck", | 2217 | .name = "tesla_ick", |
| 2291 | .ops = &clkops_omap2_dflt, | 2218 | .ops = &clkops_omap2_dflt, |
| 2292 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | 2219 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, |
| 2293 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2220 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2296,8 +2223,8 @@ static struct clk tesla_ck = { | |||
| 2296 | .recalc = &followparent_recalc, | 2223 | .recalc = &followparent_recalc, |
| 2297 | }; | 2224 | }; |
| 2298 | 2225 | ||
| 2299 | static struct clk uart1_ck = { | 2226 | static struct clk uart1_fck = { |
| 2300 | .name = "uart1_ck", | 2227 | .name = "uart1_fck", |
| 2301 | .ops = &clkops_omap2_dflt, | 2228 | .ops = &clkops_omap2_dflt, |
| 2302 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | 2229 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
| 2303 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2230 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2306,8 +2233,8 @@ static struct clk uart1_ck = { | |||
| 2306 | .recalc = &followparent_recalc, | 2233 | .recalc = &followparent_recalc, |
| 2307 | }; | 2234 | }; |
| 2308 | 2235 | ||
| 2309 | static struct clk uart2_ck = { | 2236 | static struct clk uart2_fck = { |
| 2310 | .name = "uart2_ck", | 2237 | .name = "uart2_fck", |
| 2311 | .ops = &clkops_omap2_dflt, | 2238 | .ops = &clkops_omap2_dflt, |
| 2312 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | 2239 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
| 2313 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2240 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2316,8 +2243,8 @@ static struct clk uart2_ck = { | |||
| 2316 | .recalc = &followparent_recalc, | 2243 | .recalc = &followparent_recalc, |
| 2317 | }; | 2244 | }; |
| 2318 | 2245 | ||
| 2319 | static struct clk uart3_ck = { | 2246 | static struct clk uart3_fck = { |
| 2320 | .name = "uart3_ck", | 2247 | .name = "uart3_fck", |
| 2321 | .ops = &clkops_omap2_dflt, | 2248 | .ops = &clkops_omap2_dflt, |
| 2322 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | 2249 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
| 2323 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2250 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2326,8 +2253,8 @@ static struct clk uart3_ck = { | |||
| 2326 | .recalc = &followparent_recalc, | 2253 | .recalc = &followparent_recalc, |
| 2327 | }; | 2254 | }; |
| 2328 | 2255 | ||
| 2329 | static struct clk uart4_ck = { | 2256 | static struct clk uart4_fck = { |
| 2330 | .name = "uart4_ck", | 2257 | .name = "uart4_fck", |
| 2331 | .ops = &clkops_omap2_dflt, | 2258 | .ops = &clkops_omap2_dflt, |
| 2332 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | 2259 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
| 2333 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2260 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2336,8 +2263,8 @@ static struct clk uart4_ck = { | |||
| 2336 | .recalc = &followparent_recalc, | 2263 | .recalc = &followparent_recalc, |
| 2337 | }; | 2264 | }; |
| 2338 | 2265 | ||
| 2339 | static struct clk unipro1_ck = { | 2266 | static struct clk unipro1_fck = { |
| 2340 | .name = "unipro1_ck", | 2267 | .name = "unipro1_fck", |
| 2341 | .ops = &clkops_omap2_dflt, | 2268 | .ops = &clkops_omap2_dflt, |
| 2342 | .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, | 2269 | .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, |
| 2343 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2270 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2346,8 +2273,8 @@ static struct clk unipro1_ck = { | |||
| 2346 | .recalc = &followparent_recalc, | 2273 | .recalc = &followparent_recalc, |
| 2347 | }; | 2274 | }; |
| 2348 | 2275 | ||
| 2349 | static struct clk usb_host_ck = { | 2276 | static struct clk usb_host_fck = { |
| 2350 | .name = "usb_host_ck", | 2277 | .name = "usb_host_fck", |
| 2351 | .ops = &clkops_omap2_dflt, | 2278 | .ops = &clkops_omap2_dflt, |
| 2352 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | 2279 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2353 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2280 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2356,8 +2283,8 @@ static struct clk usb_host_ck = { | |||
| 2356 | .recalc = &followparent_recalc, | 2283 | .recalc = &followparent_recalc, |
| 2357 | }; | 2284 | }; |
| 2358 | 2285 | ||
| 2359 | static struct clk usb_host_fs_ck = { | 2286 | static struct clk usb_host_fs_fck = { |
| 2360 | .name = "usb_host_fs_ck", | 2287 | .name = "usb_host_fs_fck", |
| 2361 | .ops = &clkops_omap2_dflt, | 2288 | .ops = &clkops_omap2_dflt, |
| 2362 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, | 2289 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| 2363 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2290 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2366,8 +2293,8 @@ static struct clk usb_host_fs_ck = { | |||
| 2366 | .recalc = &followparent_recalc, | 2293 | .recalc = &followparent_recalc, |
| 2367 | }; | 2294 | }; |
| 2368 | 2295 | ||
| 2369 | static struct clk usb_otg_ck = { | 2296 | static struct clk usb_otg_ick = { |
| 2370 | .name = "usb_otg_ck", | 2297 | .name = "usb_otg_ick", |
| 2371 | .ops = &clkops_omap2_dflt, | 2298 | .ops = &clkops_omap2_dflt, |
| 2372 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | 2299 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2373 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2300 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2376,8 +2303,8 @@ static struct clk usb_otg_ck = { | |||
| 2376 | .recalc = &followparent_recalc, | 2303 | .recalc = &followparent_recalc, |
| 2377 | }; | 2304 | }; |
| 2378 | 2305 | ||
| 2379 | static struct clk usb_tll_ck = { | 2306 | static struct clk usb_tll_ick = { |
| 2380 | .name = "usb_tll_ck", | 2307 | .name = "usb_tll_ick", |
| 2381 | .ops = &clkops_omap2_dflt, | 2308 | .ops = &clkops_omap2_dflt, |
| 2382 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | 2309 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2383 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2310 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2386,8 +2313,8 @@ static struct clk usb_tll_ck = { | |||
| 2386 | .recalc = &followparent_recalc, | 2313 | .recalc = &followparent_recalc, |
| 2387 | }; | 2314 | }; |
| 2388 | 2315 | ||
| 2389 | static struct clk usbphyocp2scp_ck = { | 2316 | static struct clk usbphyocp2scp_ick = { |
| 2390 | .name = "usbphyocp2scp_ck", | 2317 | .name = "usbphyocp2scp_ick", |
| 2391 | .ops = &clkops_omap2_dflt, | 2318 | .ops = &clkops_omap2_dflt, |
| 2392 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | 2319 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| 2393 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2320 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| @@ -2396,8 +2323,8 @@ static struct clk usbphyocp2scp_ck = { | |||
| 2396 | .recalc = &followparent_recalc, | 2323 | .recalc = &followparent_recalc, |
| 2397 | }; | 2324 | }; |
| 2398 | 2325 | ||
| 2399 | static struct clk usim_ck = { | 2326 | static struct clk usim_fck = { |
| 2400 | .name = "usim_ck", | 2327 | .name = "usim_fck", |
| 2401 | .ops = &clkops_omap2_dflt, | 2328 | .ops = &clkops_omap2_dflt, |
| 2402 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | 2329 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
| 2403 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2330 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2406,8 +2333,8 @@ static struct clk usim_ck = { | |||
| 2406 | .recalc = &followparent_recalc, | 2333 | .recalc = &followparent_recalc, |
| 2407 | }; | 2334 | }; |
| 2408 | 2335 | ||
| 2409 | static struct clk wdt2_ck = { | 2336 | static struct clk wdt2_fck = { |
| 2410 | .name = "wdt2_ck", | 2337 | .name = "wdt2_fck", |
| 2411 | .ops = &clkops_omap2_dflt, | 2338 | .ops = &clkops_omap2_dflt, |
| 2412 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | 2339 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
| 2413 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2340 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2416,8 +2343,8 @@ static struct clk wdt2_ck = { | |||
| 2416 | .recalc = &followparent_recalc, | 2343 | .recalc = &followparent_recalc, |
| 2417 | }; | 2344 | }; |
| 2418 | 2345 | ||
| 2419 | static struct clk wdt3_ck = { | 2346 | static struct clk wdt3_fck = { |
| 2420 | .name = "wdt3_ck", | 2347 | .name = "wdt3_fck", |
| 2421 | .ops = &clkops_omap2_dflt, | 2348 | .ops = &clkops_omap2_dflt, |
| 2422 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | 2349 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
| 2423 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2350 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| @@ -2442,7 +2369,6 @@ static struct clk otg_60m_gfclk_ck = { | |||
| 2442 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, | 2369 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, |
| 2443 | .ops = &clkops_null, | 2370 | .ops = &clkops_null, |
| 2444 | .recalc = &omap2_clksel_recalc, | 2371 | .recalc = &omap2_clksel_recalc, |
| 2445 | .flags = CLOCK_IN_OMAP4430, | ||
| 2446 | }; | 2372 | }; |
| 2447 | 2373 | ||
| 2448 | static const struct clksel stm_clk_div_div[] = { | 2374 | static const struct clksel stm_clk_div_div[] = { |
| @@ -2460,7 +2386,6 @@ static struct clk stm_clk_div_ck = { | |||
| 2460 | .recalc = &omap2_clksel_recalc, | 2386 | .recalc = &omap2_clksel_recalc, |
| 2461 | .round_rate = &omap2_clksel_round_rate, | 2387 | .round_rate = &omap2_clksel_round_rate, |
| 2462 | .set_rate = &omap2_clksel_set_rate, | 2388 | .set_rate = &omap2_clksel_set_rate, |
| 2463 | .flags = CLOCK_IN_OMAP4430, | ||
| 2464 | }; | 2389 | }; |
| 2465 | 2390 | ||
| 2466 | static const struct clksel trace_clk_div_div[] = { | 2391 | static const struct clksel trace_clk_div_div[] = { |
| @@ -2478,7 +2403,6 @@ static struct clk trace_clk_div_ck = { | |||
| 2478 | .recalc = &omap2_clksel_recalc, | 2403 | .recalc = &omap2_clksel_recalc, |
| 2479 | .round_rate = &omap2_clksel_round_rate, | 2404 | .round_rate = &omap2_clksel_round_rate, |
| 2480 | .set_rate = &omap2_clksel_set_rate, | 2405 | .set_rate = &omap2_clksel_set_rate, |
| 2481 | .flags = CLOCK_IN_OMAP4430, | ||
| 2482 | }; | 2406 | }; |
| 2483 | 2407 | ||
| 2484 | static const struct clksel_rate div2_14to18_rates[] = { | 2408 | static const struct clksel_rate div2_14to18_rates[] = { |
| @@ -2502,7 +2426,6 @@ static struct clk usim_fclk = { | |||
| 2502 | .recalc = &omap2_clksel_recalc, | 2426 | .recalc = &omap2_clksel_recalc, |
| 2503 | .round_rate = &omap2_clksel_round_rate, | 2427 | .round_rate = &omap2_clksel_round_rate, |
| 2504 | .set_rate = &omap2_clksel_set_rate, | 2428 | .set_rate = &omap2_clksel_set_rate, |
| 2505 | .flags = CLOCK_IN_OMAP4430, | ||
| 2506 | }; | 2429 | }; |
| 2507 | 2430 | ||
| 2508 | static const struct clksel utmi_p1_gfclk_sel[] = { | 2431 | static const struct clksel utmi_p1_gfclk_sel[] = { |
| @@ -2520,7 +2443,6 @@ static struct clk utmi_p1_gfclk_ck = { | |||
| 2520 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, | 2443 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, |
| 2521 | .ops = &clkops_null, | 2444 | .ops = &clkops_null, |
| 2522 | .recalc = &omap2_clksel_recalc, | 2445 | .recalc = &omap2_clksel_recalc, |
| 2523 | .flags = CLOCK_IN_OMAP4430, | ||
| 2524 | }; | 2446 | }; |
| 2525 | 2447 | ||
| 2526 | static const struct clksel utmi_p2_gfclk_sel[] = { | 2448 | static const struct clksel utmi_p2_gfclk_sel[] = { |
| @@ -2538,7 +2460,6 @@ static struct clk utmi_p2_gfclk_ck = { | |||
| 2538 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, | 2460 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, |
| 2539 | .ops = &clkops_null, | 2461 | .ops = &clkops_null, |
| 2540 | .recalc = &omap2_clksel_recalc, | 2462 | .recalc = &omap2_clksel_recalc, |
| 2541 | .flags = CLOCK_IN_OMAP4430, | ||
| 2542 | }; | 2463 | }; |
| 2543 | 2464 | ||
| 2544 | /* | 2465 | /* |
| @@ -2631,106 +2552,139 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 2631 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | 2552 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), |
| 2632 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | 2553 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), |
| 2633 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | 2554 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), |
| 2634 | CLK(NULL, "aes1_ck", &aes1_ck, CK_443X), | 2555 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
| 2635 | CLK(NULL, "aes2_ck", &aes2_ck, CK_443X), | 2556 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), |
| 2636 | CLK(NULL, "aess_ck", &aess_ck, CK_443X), | 2557 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), |
| 2637 | CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X), | 2558 | CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), |
| 2638 | CLK(NULL, "des3des_ck", &des3des_ck, CK_443X), | 2559 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
| 2639 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), | 2560 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
| 2640 | CLK(NULL, "dmic_ck", &dmic_ck, CK_443X), | 2561 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
| 2641 | CLK(NULL, "dss_ck", &dss_ck, CK_443X), | 2562 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), |
| 2642 | CLK(NULL, "ducati_ck", &ducati_ck, CK_443X), | 2563 | CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), |
| 2643 | CLK(NULL, "emif1_ck", &emif1_ck, CK_443X), | 2564 | CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), |
| 2644 | CLK(NULL, "emif2_ck", &emif2_ck, CK_443X), | 2565 | CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), |
| 2645 | CLK(NULL, "fdif_ck", &fdif_ck, CK_443X), | 2566 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
| 2646 | CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), | 2567 | CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), |
| 2647 | CLK(NULL, "gfx_ck", &gfx_ck, CK_443X), | 2568 | CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), |
| 2648 | CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X), | 2569 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
| 2649 | CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X), | 2570 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
| 2650 | CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X), | 2571 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
| 2651 | CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X), | 2572 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
| 2652 | CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X), | 2573 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
| 2653 | CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X), | 2574 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
| 2654 | CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X), | 2575 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), |
| 2655 | CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X), | 2576 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), |
| 2656 | CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X), | 2577 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), |
| 2657 | CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X), | 2578 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), |
| 2658 | CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X), | 2579 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), |
| 2659 | CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X), | 2580 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), |
| 2660 | CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X), | 2581 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), |
| 2661 | CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X), | 2582 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), |
| 2662 | CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X), | 2583 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), |
| 2663 | CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X), | 2584 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), |
| 2664 | CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X), | 2585 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), |
| 2665 | CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X), | 2586 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), |
| 2666 | CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X), | 2587 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), |
| 2667 | CLK(NULL, "hsi_ck", &hsi_ck, CK_443X), | 2588 | CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), |
| 2668 | CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X), | 2589 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), |
| 2669 | CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X), | 2590 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), |
| 2670 | CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X), | 2591 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), |
| 2671 | CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X), | 2592 | CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), |
| 2672 | CLK(NULL, "iss_ck", &iss_ck, CK_443X), | 2593 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
| 2673 | CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X), | 2594 | CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), |
| 2674 | CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X), | 2595 | CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), |
| 2675 | CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X), | 2596 | CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), |
| 2676 | CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X), | 2597 | CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), |
| 2677 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), | 2598 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
| 2678 | CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X), | 2599 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
| 2679 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), | 2600 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
| 2680 | CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X), | 2601 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), |
| 2681 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), | 2602 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
| 2682 | CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X), | 2603 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), |
| 2683 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), | 2604 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
| 2684 | CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X), | 2605 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), |
| 2685 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), | 2606 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
| 2686 | CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X), | 2607 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), |
| 2687 | CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X), | 2608 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), |
| 2688 | CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X), | 2609 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), |
| 2689 | CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X), | 2610 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), |
| 2690 | CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X), | 2611 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), |
| 2691 | CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X), | 2612 | CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), |
| 2692 | CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X), | 2613 | CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), |
| 2693 | CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X), | 2614 | CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), |
| 2694 | CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X), | 2615 | CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), |
| 2695 | CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X), | 2616 | CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), |
| 2696 | CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X), | 2617 | CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), |
| 2697 | CLK(NULL, "pdm_ck", &pdm_ck, CK_443X), | 2618 | CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), |
| 2698 | CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X), | 2619 | CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), |
| 2699 | CLK("omap_rng", "ick", &rng_ck, CK_443X), | 2620 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
| 2700 | CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X), | 2621 | CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), |
| 2701 | CLK(NULL, "sl2_ck", &sl2_ck, CK_443X), | 2622 | CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), |
| 2702 | CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X), | 2623 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
| 2703 | CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X), | 2624 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
| 2704 | CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X), | 2625 | CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), |
| 2705 | CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X), | 2626 | CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), |
| 2706 | CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X), | 2627 | CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), |
| 2707 | CLK(NULL, "tesla_ck", &tesla_ck, CK_443X), | 2628 | CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), |
| 2708 | CLK(NULL, "uart1_ck", &uart1_ck, CK_443X), | 2629 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
| 2709 | CLK(NULL, "uart2_ck", &uart2_ck, CK_443X), | 2630 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), |
| 2710 | CLK(NULL, "uart3_ck", &uart3_ck, CK_443X), | 2631 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), |
| 2711 | CLK(NULL, "uart4_ck", &uart4_ck, CK_443X), | 2632 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), |
| 2712 | CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X), | 2633 | CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X), |
| 2713 | CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X), | 2634 | CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X), |
| 2714 | CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X), | 2635 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
| 2715 | CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X), | 2636 | CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), |
| 2716 | CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X), | 2637 | CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), |
| 2717 | CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X), | 2638 | CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), |
| 2718 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), | 2639 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
| 2719 | CLK("omap_wdt", "fck", &wdt2_ck, CK_443X), | 2640 | CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), |
| 2720 | CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X), | 2641 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), |
| 2721 | CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), | 2642 | CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), |
| 2722 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), | 2643 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
| 2723 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | 2644 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), |
| 2724 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | 2645 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), |
| 2725 | CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), | 2646 | CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), |
| 2726 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), | 2647 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), |
| 2727 | }; | 2648 | CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X), |
| 2728 | 2649 | CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X), | |
| 2729 | int __init omap2_clk_init(void) | 2650 | CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X), |
| 2651 | CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X), | ||
| 2652 | CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X), | ||
| 2653 | CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X), | ||
| 2654 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), | ||
| 2655 | CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), | ||
| 2656 | CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), | ||
| 2657 | CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), | ||
| 2658 | CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), | ||
| 2659 | CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), | ||
| 2660 | CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), | ||
| 2661 | CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), | ||
| 2662 | CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), | ||
| 2663 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), | ||
| 2664 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), | ||
| 2665 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), | ||
| 2666 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X), | ||
| 2667 | CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), | ||
| 2668 | CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), | ||
| 2669 | CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), | ||
| 2670 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), | ||
| 2671 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | ||
| 2672 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | ||
| 2673 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | ||
| 2674 | CLK("omap-mcspi.1", "ick", &dummy_ck, CK_443X), | ||
| 2675 | CLK("omap-mcspi.2", "ick", &dummy_ck, CK_443X), | ||
| 2676 | CLK("omap-mcspi.3", "ick", &dummy_ck, CK_443X), | ||
| 2677 | CLK("omap-mcspi.4", "ick", &dummy_ck, CK_443X), | ||
| 2678 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), | ||
| 2679 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | ||
| 2680 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | ||
| 2681 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | ||
| 2682 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | ||
| 2683 | }; | ||
| 2684 | |||
| 2685 | int __init omap4xxx_clk_init(void) | ||
| 2730 | { | 2686 | { |
| 2731 | /* struct prcm_config *prcm; */ | ||
| 2732 | struct omap_clk *c; | 2687 | struct omap_clk *c; |
| 2733 | /* u32 clkrate; */ | ||
| 2734 | u32 cpu_clkflg; | 2688 | u32 cpu_clkflg; |
| 2735 | 2689 | ||
| 2736 | if (cpu_is_omap44xx()) { | 2690 | if (cpu_is_omap44xx()) { |
| @@ -2749,9 +2703,7 @@ int __init omap2_clk_init(void) | |||
| 2749 | if (c->cpu & cpu_clkflg) { | 2703 | if (c->cpu & cpu_clkflg) { |
| 2750 | clkdev_add(&c->lk); | 2704 | clkdev_add(&c->lk); |
| 2751 | clk_register(c->lk.clk); | 2705 | clk_register(c->lk.clk); |
| 2752 | /* TODO | ||
| 2753 | omap2_init_clk_clkdm(c->lk.clk); | 2706 | omap2_init_clk_clkdm(c->lk.clk); |
| 2754 | */ | ||
| 2755 | } | 2707 | } |
| 2756 | 2708 | ||
| 2757 | recalculate_root_clocks(); | 2709 | recalculate_root_clocks(); |
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index dd285f001467..b87ad66f083e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
| @@ -1,10 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP2/3 clockdomain framework functions | 2 | * OMAP2/3/4 clockdomain framework functions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2008-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2008-2009 Nokia Corporation | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley and Jouni Högander | 7 | * Written by Paul Walmsley and Jouni Högander |
| 8 | * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> | ||
| 8 | * | 9 | * |
| 9 | * This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as | 11 | * it under the terms of the GNU General Public License version 2 as |
| @@ -26,43 +27,124 @@ | |||
| 26 | 27 | ||
| 27 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 28 | 29 | ||
| 29 | #include <plat/clock.h> | ||
| 30 | |||
| 31 | #include "prm.h" | 30 | #include "prm.h" |
| 32 | #include "prm-regbits-24xx.h" | 31 | #include "prm-regbits-24xx.h" |
| 33 | #include "cm.h" | 32 | #include "cm.h" |
| 34 | 33 | ||
| 34 | #include <plat/clock.h> | ||
| 35 | #include <plat/powerdomain.h> | 35 | #include <plat/powerdomain.h> |
| 36 | #include <plat/clockdomain.h> | 36 | #include <plat/clockdomain.h> |
| 37 | #include <plat/prcm.h> | ||
| 37 | 38 | ||
| 38 | /* clkdm_list contains all registered struct clockdomains */ | 39 | /* clkdm_list contains all registered struct clockdomains */ |
| 39 | static LIST_HEAD(clkdm_list); | 40 | static LIST_HEAD(clkdm_list); |
| 40 | 41 | ||
| 41 | /* clkdm_mutex protects clkdm_list add and del ops */ | 42 | /* array of clockdomain deps to be added/removed when clkdm in hwsup mode */ |
| 42 | static DEFINE_MUTEX(clkdm_mutex); | 43 | static struct clkdm_autodep *autodeps; |
| 43 | |||
| 44 | /* array of powerdomain deps to be added/removed when clkdm in hwsup mode */ | ||
| 45 | static struct clkdm_pwrdm_autodep *autodeps; | ||
| 46 | 44 | ||
| 47 | 45 | ||
| 48 | /* Private functions */ | 46 | /* Private functions */ |
| 49 | 47 | ||
| 48 | static struct clockdomain *_clkdm_lookup(const char *name) | ||
| 49 | { | ||
| 50 | struct clockdomain *clkdm, *temp_clkdm; | ||
| 51 | |||
| 52 | if (!name) | ||
| 53 | return NULL; | ||
| 54 | |||
| 55 | clkdm = NULL; | ||
| 56 | |||
| 57 | list_for_each_entry(temp_clkdm, &clkdm_list, node) { | ||
| 58 | if (!strcmp(name, temp_clkdm->name)) { | ||
| 59 | clkdm = temp_clkdm; | ||
| 60 | break; | ||
| 61 | } | ||
| 62 | } | ||
| 63 | |||
| 64 | return clkdm; | ||
| 65 | } | ||
| 66 | |||
| 67 | /** | ||
| 68 | * _clkdm_register - register a clockdomain | ||
| 69 | * @clkdm: struct clockdomain * to register | ||
| 70 | * | ||
| 71 | * Adds a clockdomain to the internal clockdomain list. | ||
| 72 | * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is | ||
| 73 | * already registered by the provided name, or 0 upon success. | ||
| 74 | */ | ||
| 75 | static int _clkdm_register(struct clockdomain *clkdm) | ||
| 76 | { | ||
| 77 | struct powerdomain *pwrdm; | ||
| 78 | |||
| 79 | if (!clkdm || !clkdm->name) | ||
| 80 | return -EINVAL; | ||
| 81 | |||
| 82 | if (!omap_chip_is(clkdm->omap_chip)) | ||
| 83 | return -EINVAL; | ||
| 84 | |||
| 85 | pwrdm = pwrdm_lookup(clkdm->pwrdm.name); | ||
| 86 | if (!pwrdm) { | ||
| 87 | pr_err("clockdomain: %s: powerdomain %s does not exist\n", | ||
| 88 | clkdm->name, clkdm->pwrdm.name); | ||
| 89 | return -EINVAL; | ||
| 90 | } | ||
| 91 | clkdm->pwrdm.ptr = pwrdm; | ||
| 92 | |||
| 93 | /* Verify that the clockdomain is not already registered */ | ||
| 94 | if (_clkdm_lookup(clkdm->name)) | ||
| 95 | return -EEXIST; | ||
| 96 | |||
| 97 | list_add(&clkdm->node, &clkdm_list); | ||
| 98 | |||
| 99 | pwrdm_add_clkdm(pwrdm, clkdm); | ||
| 100 | |||
| 101 | pr_debug("clockdomain: registered %s\n", clkdm->name); | ||
| 102 | |||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | |||
| 106 | /* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */ | ||
| 107 | static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm, | ||
| 108 | struct clkdm_dep *deps) | ||
| 109 | { | ||
| 110 | struct clkdm_dep *cd; | ||
| 111 | |||
| 112 | if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip)) | ||
| 113 | return ERR_PTR(-EINVAL); | ||
| 114 | |||
| 115 | for (cd = deps; cd->clkdm_name; cd++) { | ||
| 116 | if (!omap_chip_is(cd->omap_chip)) | ||
| 117 | continue; | ||
| 118 | |||
| 119 | if (!cd->clkdm && cd->clkdm_name) | ||
| 120 | cd->clkdm = _clkdm_lookup(cd->clkdm_name); | ||
| 121 | |||
| 122 | if (cd->clkdm == clkdm) | ||
| 123 | break; | ||
| 124 | } | ||
| 125 | |||
| 126 | if (!cd->clkdm_name) | ||
| 127 | return ERR_PTR(-ENOENT); | ||
| 128 | |||
| 129 | return cd; | ||
| 130 | } | ||
| 131 | |||
| 50 | /* | 132 | /* |
| 51 | * _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store | 133 | * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store |
| 52 | * @autodep: struct clkdm_pwrdm_autodep * to resolve | 134 | * @autodep: struct clkdm_autodep * to resolve |
| 53 | * | 135 | * |
| 54 | * Resolve autodep powerdomain names to powerdomain pointers via | 136 | * Resolve autodep clockdomain names to clockdomain pointers via |
| 55 | * pwrdm_lookup() and store the pointers in the autodep structure. An | 137 | * clkdm_lookup() and store the pointers in the autodep structure. An |
| 56 | * "autodep" is a powerdomain sleep/wakeup dependency that is | 138 | * "autodep" is a clockdomain sleep/wakeup dependency that is |
| 57 | * automatically added and removed whenever clocks in the associated | 139 | * automatically added and removed whenever clocks in the associated |
| 58 | * clockdomain are enabled or disabled (respectively) when the | 140 | * clockdomain are enabled or disabled (respectively) when the |
| 59 | * clockdomain is in hardware-supervised mode. Meant to be called | 141 | * clockdomain is in hardware-supervised mode. Meant to be called |
| 60 | * once at clockdomain layer initialization, since these should remain | 142 | * once at clockdomain layer initialization, since these should remain |
| 61 | * fixed for a particular architecture. No return value. | 143 | * fixed for a particular architecture. No return value. |
| 62 | */ | 144 | */ |
| 63 | static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) | 145 | static void _autodep_lookup(struct clkdm_autodep *autodep) |
| 64 | { | 146 | { |
| 65 | struct powerdomain *pwrdm; | 147 | struct clockdomain *clkdm; |
| 66 | 148 | ||
| 67 | if (!autodep) | 149 | if (!autodep) |
| 68 | return; | 150 | return; |
| @@ -70,13 +152,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) | |||
| 70 | if (!omap_chip_is(autodep->omap_chip)) | 152 | if (!omap_chip_is(autodep->omap_chip)) |
| 71 | return; | 153 | return; |
| 72 | 154 | ||
| 73 | pwrdm = pwrdm_lookup(autodep->pwrdm.name); | 155 | clkdm = clkdm_lookup(autodep->clkdm.name); |
| 74 | if (!pwrdm) { | 156 | if (!clkdm) { |
| 75 | pr_err("clockdomain: autodeps: powerdomain %s does not exist\n", | 157 | pr_err("clockdomain: autodeps: clockdomain %s does not exist\n", |
| 76 | autodep->pwrdm.name); | 158 | autodep->clkdm.name); |
| 77 | pwrdm = ERR_PTR(-ENOENT); | 159 | clkdm = ERR_PTR(-ENOENT); |
| 78 | } | 160 | } |
| 79 | autodep->pwrdm.ptr = pwrdm; | 161 | autodep->clkdm.ptr = clkdm; |
| 80 | } | 162 | } |
| 81 | 163 | ||
| 82 | /* | 164 | /* |
| @@ -89,21 +171,24 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) | |||
| 89 | */ | 171 | */ |
| 90 | static void _clkdm_add_autodeps(struct clockdomain *clkdm) | 172 | static void _clkdm_add_autodeps(struct clockdomain *clkdm) |
| 91 | { | 173 | { |
| 92 | struct clkdm_pwrdm_autodep *autodep; | 174 | struct clkdm_autodep *autodep; |
| 93 | 175 | ||
| 94 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { | 176 | if (!autodeps) |
| 95 | if (IS_ERR(autodep->pwrdm.ptr)) | 177 | return; |
| 178 | |||
| 179 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { | ||
| 180 | if (IS_ERR(autodep->clkdm.ptr)) | ||
| 96 | continue; | 181 | continue; |
| 97 | 182 | ||
| 98 | if (!omap_chip_is(autodep->omap_chip)) | 183 | if (!omap_chip_is(autodep->omap_chip)) |
| 99 | continue; | 184 | continue; |
| 100 | 185 | ||
| 101 | pr_debug("clockdomain: adding %s sleepdep/wkdep for " | 186 | pr_debug("clockdomain: adding %s sleepdep/wkdep for " |
| 102 | "pwrdm %s\n", autodep->pwrdm.ptr->name, | 187 | "clkdm %s\n", autodep->clkdm.ptr->name, |
| 103 | clkdm->pwrdm.ptr->name); | 188 | clkdm->name); |
| 104 | 189 | ||
| 105 | pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); | 190 | clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); |
| 106 | pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); | 191 | clkdm_add_wkdep(clkdm, autodep->clkdm.ptr); |
| 107 | } | 192 | } |
| 108 | } | 193 | } |
| 109 | 194 | ||
| @@ -117,21 +202,24 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) | |||
| 117 | */ | 202 | */ |
| 118 | static void _clkdm_del_autodeps(struct clockdomain *clkdm) | 203 | static void _clkdm_del_autodeps(struct clockdomain *clkdm) |
| 119 | { | 204 | { |
| 120 | struct clkdm_pwrdm_autodep *autodep; | 205 | struct clkdm_autodep *autodep; |
| 206 | |||
| 207 | if (!autodeps) | ||
| 208 | return; | ||
| 121 | 209 | ||
| 122 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { | 210 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { |
| 123 | if (IS_ERR(autodep->pwrdm.ptr)) | 211 | if (IS_ERR(autodep->clkdm.ptr)) |
| 124 | continue; | 212 | continue; |
| 125 | 213 | ||
| 126 | if (!omap_chip_is(autodep->omap_chip)) | 214 | if (!omap_chip_is(autodep->omap_chip)) |
| 127 | continue; | 215 | continue; |
| 128 | 216 | ||
| 129 | pr_debug("clockdomain: removing %s sleepdep/wkdep for " | 217 | pr_debug("clockdomain: removing %s sleepdep/wkdep for " |
| 130 | "pwrdm %s\n", autodep->pwrdm.ptr->name, | 218 | "clkdm %s\n", autodep->clkdm.ptr->name, |
| 131 | clkdm->pwrdm.ptr->name); | 219 | clkdm->name); |
| 132 | 220 | ||
| 133 | pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); | 221 | clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); |
| 134 | pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); | 222 | clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); |
| 135 | } | 223 | } |
| 136 | } | 224 | } |
| 137 | 225 | ||
| @@ -145,152 +233,167 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) | |||
| 145 | */ | 233 | */ |
| 146 | static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) | 234 | static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) |
| 147 | { | 235 | { |
| 148 | u32 v; | 236 | u32 bits, v; |
| 149 | 237 | ||
| 150 | if (cpu_is_omap24xx()) { | 238 | if (cpu_is_omap24xx()) { |
| 151 | if (enable) | 239 | if (enable) |
| 152 | v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; | 240 | bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; |
| 153 | else | 241 | else |
| 154 | v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; | 242 | bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; |
| 155 | } else if (cpu_is_omap34xx()) { | 243 | } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { |
| 156 | if (enable) | 244 | if (enable) |
| 157 | v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; | 245 | bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; |
| 158 | else | 246 | else |
| 159 | v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; | 247 | bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; |
| 160 | } else { | 248 | } else { |
| 161 | BUG(); | 249 | BUG(); |
| 162 | } | 250 | } |
| 163 | 251 | ||
| 164 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, | 252 | bits = bits << __ffs(clkdm->clktrctrl_mask); |
| 165 | v << __ffs(clkdm->clktrctrl_mask), | ||
| 166 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); | ||
| 167 | } | ||
| 168 | |||
| 169 | static struct clockdomain *_clkdm_lookup(const char *name) | ||
| 170 | { | ||
| 171 | struct clockdomain *clkdm, *temp_clkdm; | ||
| 172 | |||
| 173 | if (!name) | ||
| 174 | return NULL; | ||
| 175 | |||
| 176 | clkdm = NULL; | ||
| 177 | 253 | ||
| 178 | list_for_each_entry(temp_clkdm, &clkdm_list, node) { | 254 | v = __raw_readl(clkdm->clkstctrl_reg); |
| 179 | if (!strcmp(name, temp_clkdm->name)) { | 255 | v &= ~(clkdm->clktrctrl_mask); |
| 180 | clkdm = temp_clkdm; | 256 | v |= bits; |
| 181 | break; | 257 | __raw_writel(v, clkdm->clkstctrl_reg); |
| 182 | } | ||
| 183 | } | ||
| 184 | 258 | ||
| 185 | return clkdm; | ||
| 186 | } | 259 | } |
| 187 | 260 | ||
| 188 | |||
| 189 | /* Public functions */ | ||
| 190 | |||
| 191 | /** | 261 | /** |
| 192 | * clkdm_init - set up the clockdomain layer | 262 | * _init_wkdep_usecount - initialize wkdep usecounts to match hardware |
| 193 | * @clkdms: optional pointer to an array of clockdomains to register | 263 | * @clkdm: clockdomain to initialize wkdep usecounts |
| 194 | * @init_autodeps: optional pointer to an array of autodeps to register | ||
| 195 | * | 264 | * |
| 196 | * Set up internal state. If a pointer to an array of clockdomains | 265 | * Initialize the wakeup dependency usecount variables for clockdomain @clkdm. |
| 197 | * was supplied, loop through the list of clockdomains, register all | 266 | * If a wakeup dependency is present in the hardware, the usecount will be |
| 198 | * that are available on the current platform. Similarly, if a | 267 | * set to 1; otherwise, it will be set to 0. Software should clear all |
| 199 | * pointer to an array of clockdomain-powerdomain autodependencies was | 268 | * software wakeup dependencies prior to calling this function if it wishes |
| 200 | * provided, register those. No return value. | 269 | * to ensure that all usecounts start at 0. No return value. |
| 201 | */ | 270 | */ |
| 202 | void clkdm_init(struct clockdomain **clkdms, | 271 | static void _init_wkdep_usecount(struct clockdomain *clkdm) |
| 203 | struct clkdm_pwrdm_autodep *init_autodeps) | ||
| 204 | { | 272 | { |
| 205 | struct clockdomain **c = NULL; | 273 | u32 v; |
| 206 | struct clkdm_pwrdm_autodep *autodep = NULL; | 274 | struct clkdm_dep *cd; |
| 207 | 275 | ||
| 208 | if (clkdms) | 276 | if (!clkdm->wkdep_srcs) |
| 209 | for (c = clkdms; *c; c++) | 277 | return; |
| 210 | clkdm_register(*c); | ||
| 211 | 278 | ||
| 212 | autodeps = init_autodeps; | 279 | for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) { |
| 213 | if (autodeps) | 280 | if (!omap_chip_is(cd->omap_chip)) |
| 214 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) | 281 | continue; |
| 215 | _autodep_lookup(autodep); | 282 | |
| 283 | if (!cd->clkdm && cd->clkdm_name) | ||
| 284 | cd->clkdm = _clkdm_lookup(cd->clkdm_name); | ||
| 285 | |||
| 286 | if (!cd->clkdm) { | ||
| 287 | WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not " | ||
| 288 | "found\n", clkdm->name, cd->clkdm_name); | ||
| 289 | continue; | ||
| 290 | } | ||
| 291 | |||
| 292 | v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, | ||
| 293 | PM_WKDEP, | ||
| 294 | (1 << cd->clkdm->dep_bit)); | ||
| 295 | |||
| 296 | if (v) | ||
| 297 | pr_debug("clockdomain: %s: wakeup dependency already " | ||
| 298 | "set to wake up when %s wakes\n", | ||
| 299 | clkdm->name, cd->clkdm->name); | ||
| 300 | |||
| 301 | atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0); | ||
| 302 | } | ||
| 216 | } | 303 | } |
| 217 | 304 | ||
| 218 | /** | 305 | /** |
| 219 | * clkdm_register - register a clockdomain | 306 | * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware |
| 220 | * @clkdm: struct clockdomain * to register | 307 | * @clkdm: clockdomain to initialize sleepdep usecounts |
| 221 | * | 308 | * |
| 222 | * Adds a clockdomain to the internal clockdomain list. | 309 | * Initialize the sleep dependency usecount variables for clockdomain @clkdm. |
| 223 | * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is | 310 | * If a sleep dependency is present in the hardware, the usecount will be |
| 224 | * already registered by the provided name, or 0 upon success. | 311 | * set to 1; otherwise, it will be set to 0. Software should clear all |
| 312 | * software sleep dependencies prior to calling this function if it wishes | ||
| 313 | * to ensure that all usecounts start at 0. No return value. | ||
| 225 | */ | 314 | */ |
| 226 | int clkdm_register(struct clockdomain *clkdm) | 315 | static void _init_sleepdep_usecount(struct clockdomain *clkdm) |
| 227 | { | 316 | { |
| 228 | int ret = -EINVAL; | 317 | u32 v; |
| 229 | struct powerdomain *pwrdm; | 318 | struct clkdm_dep *cd; |
| 230 | 319 | ||
| 231 | if (!clkdm || !clkdm->name) | 320 | if (!cpu_is_omap34xx()) |
| 232 | return -EINVAL; | 321 | return; |
| 233 | 322 | ||
| 234 | if (!omap_chip_is(clkdm->omap_chip)) | 323 | if (!clkdm->sleepdep_srcs) |
| 235 | return -EINVAL; | 324 | return; |
| 236 | 325 | ||
| 237 | pwrdm = pwrdm_lookup(clkdm->pwrdm.name); | 326 | for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) { |
| 238 | if (!pwrdm) { | 327 | if (!omap_chip_is(cd->omap_chip)) |
| 239 | pr_err("clockdomain: %s: powerdomain %s does not exist\n", | 328 | continue; |
| 240 | clkdm->name, clkdm->pwrdm.name); | ||
| 241 | return -EINVAL; | ||
| 242 | } | ||
| 243 | clkdm->pwrdm.ptr = pwrdm; | ||
| 244 | 329 | ||
| 245 | mutex_lock(&clkdm_mutex); | 330 | if (!cd->clkdm && cd->clkdm_name) |
| 246 | /* Verify that the clockdomain is not already registered */ | 331 | cd->clkdm = _clkdm_lookup(cd->clkdm_name); |
| 247 | if (_clkdm_lookup(clkdm->name)) { | ||
| 248 | ret = -EEXIST; | ||
| 249 | goto cr_unlock; | ||
| 250 | } | ||
| 251 | 332 | ||
| 252 | list_add(&clkdm->node, &clkdm_list); | 333 | if (!cd->clkdm) { |
| 334 | WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s " | ||
| 335 | "not found\n", clkdm->name, cd->clkdm_name); | ||
| 336 | continue; | ||
| 337 | } | ||
| 253 | 338 | ||
| 254 | pwrdm_add_clkdm(pwrdm, clkdm); | 339 | v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, |
| 340 | OMAP3430_CM_SLEEPDEP, | ||
| 341 | (1 << cd->clkdm->dep_bit)); | ||
| 255 | 342 | ||
| 256 | pr_debug("clockdomain: registered %s\n", clkdm->name); | 343 | if (v) |
| 257 | ret = 0; | 344 | pr_debug("clockdomain: %s: sleep dependency already " |
| 345 | "set to prevent from idling until %s " | ||
| 346 | "idles\n", clkdm->name, cd->clkdm->name); | ||
| 258 | 347 | ||
| 259 | cr_unlock: | 348 | atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0); |
| 260 | mutex_unlock(&clkdm_mutex); | 349 | } |
| 350 | }; | ||
| 261 | 351 | ||
| 262 | return ret; | 352 | /* Public functions */ |
| 263 | } | ||
| 264 | 353 | ||
| 265 | /** | 354 | /** |
| 266 | * clkdm_unregister - unregister a clockdomain | 355 | * clkdm_init - set up the clockdomain layer |
| 267 | * @clkdm: struct clockdomain * to unregister | 356 | * @clkdms: optional pointer to an array of clockdomains to register |
| 357 | * @init_autodeps: optional pointer to an array of autodeps to register | ||
| 268 | * | 358 | * |
| 269 | * Removes a clockdomain from the internal clockdomain list. Returns | 359 | * Set up internal state. If a pointer to an array of clockdomains |
| 270 | * -EINVAL if clkdm argument is NULL. | 360 | * @clkdms was supplied, loop through the list of clockdomains, |
| 361 | * register all that are available on the current platform. Similarly, | ||
| 362 | * if a pointer to an array of clockdomain autodependencies | ||
| 363 | * @init_autodeps was provided, register those. No return value. | ||
| 271 | */ | 364 | */ |
| 272 | int clkdm_unregister(struct clockdomain *clkdm) | 365 | void clkdm_init(struct clockdomain **clkdms, |
| 366 | struct clkdm_autodep *init_autodeps) | ||
| 273 | { | 367 | { |
| 274 | if (!clkdm) | 368 | struct clockdomain **c = NULL; |
| 275 | return -EINVAL; | 369 | struct clockdomain *clkdm; |
| 276 | 370 | struct clkdm_autodep *autodep = NULL; | |
| 277 | pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm); | ||
| 278 | 371 | ||
| 279 | mutex_lock(&clkdm_mutex); | 372 | if (clkdms) |
| 280 | list_del(&clkdm->node); | 373 | for (c = clkdms; *c; c++) |
| 281 | mutex_unlock(&clkdm_mutex); | 374 | _clkdm_register(*c); |
| 282 | 375 | ||
| 283 | pr_debug("clockdomain: unregistered %s\n", clkdm->name); | 376 | autodeps = init_autodeps; |
| 377 | if (autodeps) | ||
| 378 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) | ||
| 379 | _autodep_lookup(autodep); | ||
| 284 | 380 | ||
| 285 | return 0; | 381 | /* |
| 382 | * Ensure that the *dep_usecount registers reflect the current | ||
| 383 | * state of the PRCM. | ||
| 384 | */ | ||
| 385 | list_for_each_entry(clkdm, &clkdm_list, node) { | ||
| 386 | _init_wkdep_usecount(clkdm); | ||
| 387 | _init_sleepdep_usecount(clkdm); | ||
| 388 | } | ||
| 286 | } | 389 | } |
| 287 | 390 | ||
| 288 | /** | 391 | /** |
| 289 | * clkdm_lookup - look up a clockdomain by name, return a pointer | 392 | * clkdm_lookup - look up a clockdomain by name, return a pointer |
| 290 | * @name: name of clockdomain | 393 | * @name: name of clockdomain |
| 291 | * | 394 | * |
| 292 | * Find a registered clockdomain by its name. Returns a pointer to the | 395 | * Find a registered clockdomain by its name @name. Returns a pointer |
| 293 | * struct clockdomain if found, or NULL otherwise. | 396 | * to the struct clockdomain if found, or NULL otherwise. |
| 294 | */ | 397 | */ |
| 295 | struct clockdomain *clkdm_lookup(const char *name) | 398 | struct clockdomain *clkdm_lookup(const char *name) |
| 296 | { | 399 | { |
| @@ -301,14 +404,12 @@ struct clockdomain *clkdm_lookup(const char *name) | |||
| 301 | 404 | ||
| 302 | clkdm = NULL; | 405 | clkdm = NULL; |
| 303 | 406 | ||
| 304 | mutex_lock(&clkdm_mutex); | ||
| 305 | list_for_each_entry(temp_clkdm, &clkdm_list, node) { | 407 | list_for_each_entry(temp_clkdm, &clkdm_list, node) { |
| 306 | if (!strcmp(name, temp_clkdm->name)) { | 408 | if (!strcmp(name, temp_clkdm->name)) { |
| 307 | clkdm = temp_clkdm; | 409 | clkdm = temp_clkdm; |
| 308 | break; | 410 | break; |
| 309 | } | 411 | } |
| 310 | } | 412 | } |
| 311 | mutex_unlock(&clkdm_mutex); | ||
| 312 | 413 | ||
| 313 | return clkdm; | 414 | return clkdm; |
| 314 | } | 415 | } |
| @@ -317,8 +418,8 @@ struct clockdomain *clkdm_lookup(const char *name) | |||
| 317 | * clkdm_for_each - call function on each registered clockdomain | 418 | * clkdm_for_each - call function on each registered clockdomain |
| 318 | * @fn: callback function * | 419 | * @fn: callback function * |
| 319 | * | 420 | * |
| 320 | * Call the supplied function for each registered clockdomain. | 421 | * Call the supplied function @fn for each registered clockdomain. |
| 321 | * The callback function can return anything but 0 to bail | 422 | * The callback function @fn can return anything but 0 to bail |
| 322 | * out early from the iterator. The callback function is called with | 423 | * out early from the iterator. The callback function is called with |
| 323 | * the clkdm_mutex held, so no clockdomain structure manipulation | 424 | * the clkdm_mutex held, so no clockdomain structure manipulation |
| 324 | * functions should be called from the callback, although hardware | 425 | * functions should be called from the callback, although hardware |
| @@ -336,13 +437,11 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), | |||
| 336 | if (!fn) | 437 | if (!fn) |
| 337 | return -EINVAL; | 438 | return -EINVAL; |
| 338 | 439 | ||
| 339 | mutex_lock(&clkdm_mutex); | ||
| 340 | list_for_each_entry(clkdm, &clkdm_list, node) { | 440 | list_for_each_entry(clkdm, &clkdm_list, node) { |
| 341 | ret = (*fn)(clkdm, user); | 441 | ret = (*fn)(clkdm, user); |
| 342 | if (ret) | 442 | if (ret) |
| 343 | break; | 443 | break; |
| 344 | } | 444 | } |
| 345 | mutex_unlock(&clkdm_mutex); | ||
| 346 | 445 | ||
| 347 | return ret; | 446 | return ret; |
| 348 | } | 447 | } |
| @@ -353,7 +452,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), | |||
| 353 | * @clkdm: struct clockdomain * | 452 | * @clkdm: struct clockdomain * |
| 354 | * | 453 | * |
| 355 | * Return a pointer to the struct powerdomain that the specified clockdomain | 454 | * Return a pointer to the struct powerdomain that the specified clockdomain |
| 356 | * 'clkdm' exists in, or returns NULL if clkdm argument is NULL. | 455 | * @clkdm exists in, or returns NULL if @clkdm is NULL. |
| 357 | */ | 456 | */ |
| 358 | struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) | 457 | struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) |
| 359 | { | 458 | { |
| @@ -367,11 +466,309 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) | |||
| 367 | /* Hardware clockdomain control */ | 466 | /* Hardware clockdomain control */ |
| 368 | 467 | ||
| 369 | /** | 468 | /** |
| 469 | * clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 | ||
| 470 | * @clkdm1: wake this struct clockdomain * up (dependent) | ||
| 471 | * @clkdm2: when this struct clockdomain * wakes up (source) | ||
| 472 | * | ||
| 473 | * When the clockdomain represented by @clkdm2 wakes up, wake up | ||
| 474 | * @clkdm1. Implemented in hardware on the OMAP, this feature is | ||
| 475 | * designed to reduce wakeup latency of the dependent clockdomain @clkdm1. | ||
| 476 | * Returns -EINVAL if presented with invalid clockdomain pointers, | ||
| 477 | * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon | ||
| 478 | * success. | ||
| 479 | */ | ||
| 480 | int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | ||
| 481 | { | ||
| 482 | struct clkdm_dep *cd; | ||
| 483 | |||
| 484 | if (!clkdm1 || !clkdm2) | ||
| 485 | return -EINVAL; | ||
| 486 | |||
| 487 | cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); | ||
| 488 | if (IS_ERR(cd)) { | ||
| 489 | pr_debug("clockdomain: hardware cannot set/clear wake up of " | ||
| 490 | "%s when %s wakes up\n", clkdm1->name, clkdm2->name); | ||
| 491 | return PTR_ERR(cd); | ||
| 492 | } | ||
| 493 | |||
| 494 | if (atomic_inc_return(&cd->wkdep_usecount) == 1) { | ||
| 495 | pr_debug("clockdomain: hardware will wake up %s when %s wakes " | ||
| 496 | "up\n", clkdm1->name, clkdm2->name); | ||
| 497 | |||
| 498 | prm_set_mod_reg_bits((1 << clkdm2->dep_bit), | ||
| 499 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | ||
| 500 | } | ||
| 501 | |||
| 502 | return 0; | ||
| 503 | } | ||
| 504 | |||
| 505 | /** | ||
| 506 | * clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1 | ||
| 507 | * @clkdm1: wake this struct clockdomain * up (dependent) | ||
| 508 | * @clkdm2: when this struct clockdomain * wakes up (source) | ||
| 509 | * | ||
| 510 | * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2 | ||
| 511 | * wakes up. Returns -EINVAL if presented with invalid clockdomain | ||
| 512 | * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or | ||
| 513 | * 0 upon success. | ||
| 514 | */ | ||
| 515 | int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | ||
| 516 | { | ||
| 517 | struct clkdm_dep *cd; | ||
| 518 | |||
| 519 | if (!clkdm1 || !clkdm2) | ||
| 520 | return -EINVAL; | ||
| 521 | |||
| 522 | cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); | ||
| 523 | if (IS_ERR(cd)) { | ||
| 524 | pr_debug("clockdomain: hardware cannot set/clear wake up of " | ||
| 525 | "%s when %s wakes up\n", clkdm1->name, clkdm2->name); | ||
| 526 | return PTR_ERR(cd); | ||
| 527 | } | ||
| 528 | |||
| 529 | if (atomic_dec_return(&cd->wkdep_usecount) == 0) { | ||
| 530 | pr_debug("clockdomain: hardware will no longer wake up %s " | ||
| 531 | "after %s wakes up\n", clkdm1->name, clkdm2->name); | ||
| 532 | |||
| 533 | prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | ||
| 534 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | ||
| 535 | } | ||
| 536 | |||
| 537 | return 0; | ||
| 538 | } | ||
| 539 | |||
| 540 | /** | ||
| 541 | * clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1 | ||
| 542 | * @clkdm1: wake this struct clockdomain * up (dependent) | ||
| 543 | * @clkdm2: when this struct clockdomain * wakes up (source) | ||
| 544 | * | ||
| 545 | * Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be | ||
| 546 | * awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL | ||
| 547 | * if either clockdomain pointer is invalid; or -ENOENT if the hardware | ||
| 548 | * is incapable. | ||
| 549 | * | ||
| 550 | * REVISIT: Currently this function only represents software-controllable | ||
| 551 | * wakeup dependencies. Wakeup dependencies fixed in hardware are not | ||
| 552 | * yet handled here. | ||
| 553 | */ | ||
| 554 | int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | ||
| 555 | { | ||
| 556 | struct clkdm_dep *cd; | ||
| 557 | |||
| 558 | if (!clkdm1 || !clkdm2) | ||
| 559 | return -EINVAL; | ||
| 560 | |||
| 561 | cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); | ||
| 562 | if (IS_ERR(cd)) { | ||
| 563 | pr_debug("clockdomain: hardware cannot set/clear wake up of " | ||
| 564 | "%s when %s wakes up\n", clkdm1->name, clkdm2->name); | ||
| 565 | return PTR_ERR(cd); | ||
| 566 | } | ||
| 567 | |||
| 568 | /* XXX It's faster to return the atomic wkdep_usecount */ | ||
| 569 | return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, | ||
| 570 | (1 << clkdm2->dep_bit)); | ||
| 571 | } | ||
| 572 | |||
| 573 | /** | ||
| 574 | * clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm | ||
| 575 | * @clkdm: struct clockdomain * to remove all wakeup dependencies from | ||
| 576 | * | ||
| 577 | * Remove all inter-clockdomain wakeup dependencies that could cause | ||
| 578 | * @clkdm to wake. Intended to be used during boot to initialize the | ||
| 579 | * PRCM to a known state, after all clockdomains are put into swsup idle | ||
| 580 | * and woken up. Returns -EINVAL if @clkdm pointer is invalid, or | ||
| 581 | * 0 upon success. | ||
| 582 | */ | ||
| 583 | int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) | ||
| 584 | { | ||
| 585 | struct clkdm_dep *cd; | ||
| 586 | u32 mask = 0; | ||
| 587 | |||
| 588 | if (!clkdm) | ||
| 589 | return -EINVAL; | ||
| 590 | |||
| 591 | for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { | ||
| 592 | if (!omap_chip_is(cd->omap_chip)) | ||
| 593 | continue; | ||
| 594 | |||
| 595 | /* PRM accesses are slow, so minimize them */ | ||
| 596 | mask |= 1 << cd->clkdm->dep_bit; | ||
| 597 | atomic_set(&cd->wkdep_usecount, 0); | ||
| 598 | } | ||
| 599 | |||
| 600 | prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); | ||
| 601 | |||
| 602 | return 0; | ||
| 603 | } | ||
| 604 | |||
| 605 | /** | ||
| 606 | * clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 | ||
| 607 | * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) | ||
| 608 | * @clkdm2: when this struct clockdomain * is active (source) | ||
| 609 | * | ||
| 610 | * Prevent @clkdm1 from automatically going inactive (and then to | ||
| 611 | * retention or off) if @clkdm2 is active. Returns -EINVAL if | ||
| 612 | * presented with invalid clockdomain pointers or called on a machine | ||
| 613 | * that does not support software-configurable hardware sleep | ||
| 614 | * dependencies, -ENOENT if the specified dependency cannot be set in | ||
| 615 | * hardware, or 0 upon success. | ||
| 616 | */ | ||
| 617 | int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | ||
| 618 | { | ||
| 619 | struct clkdm_dep *cd; | ||
| 620 | |||
| 621 | if (!cpu_is_omap34xx()) | ||
| 622 | return -EINVAL; | ||
| 623 | |||
| 624 | if (!clkdm1 || !clkdm2) | ||
| 625 | return -EINVAL; | ||
| 626 | |||
| 627 | cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); | ||
| 628 | if (IS_ERR(cd)) { | ||
| 629 | pr_debug("clockdomain: hardware cannot set/clear sleep " | ||
| 630 | "dependency affecting %s from %s\n", clkdm1->name, | ||
| 631 | clkdm2->name); | ||
| 632 | return PTR_ERR(cd); | ||
| 633 | } | ||
| 634 | |||
| 635 | if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { | ||
| 636 | pr_debug("clockdomain: will prevent %s from sleeping if %s " | ||
| 637 | "is active\n", clkdm1->name, clkdm2->name); | ||
| 638 | |||
| 639 | cm_set_mod_reg_bits((1 << clkdm2->dep_bit), | ||
| 640 | clkdm1->pwrdm.ptr->prcm_offs, | ||
| 641 | OMAP3430_CM_SLEEPDEP); | ||
| 642 | } | ||
| 643 | |||
| 644 | return 0; | ||
| 645 | } | ||
| 646 | |||
| 647 | /** | ||
| 648 | * clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1 | ||
| 649 | * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) | ||
| 650 | * @clkdm2: when this struct clockdomain * is active (source) | ||
| 651 | * | ||
| 652 | * Allow @clkdm1 to automatically go inactive (and then to retention or | ||
| 653 | * off), independent of the activity state of @clkdm2. Returns -EINVAL | ||
| 654 | * if presented with invalid clockdomain pointers or called on a machine | ||
| 655 | * that does not support software-configurable hardware sleep dependencies, | ||
| 656 | * -ENOENT if the specified dependency cannot be cleared in hardware, or | ||
| 657 | * 0 upon success. | ||
| 658 | */ | ||
| 659 | int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | ||
| 660 | { | ||
| 661 | struct clkdm_dep *cd; | ||
| 662 | |||
| 663 | if (!cpu_is_omap34xx()) | ||
| 664 | return -EINVAL; | ||
| 665 | |||
| 666 | if (!clkdm1 || !clkdm2) | ||
| 667 | return -EINVAL; | ||
| 668 | |||
| 669 | cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); | ||
| 670 | if (IS_ERR(cd)) { | ||
| 671 | pr_debug("clockdomain: hardware cannot set/clear sleep " | ||
| 672 | "dependency affecting %s from %s\n", clkdm1->name, | ||
| 673 | clkdm2->name); | ||
| 674 | return PTR_ERR(cd); | ||
| 675 | } | ||
| 676 | |||
| 677 | if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { | ||
| 678 | pr_debug("clockdomain: will no longer prevent %s from " | ||
| 679 | "sleeping if %s is active\n", clkdm1->name, | ||
| 680 | clkdm2->name); | ||
| 681 | |||
| 682 | cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | ||
| 683 | clkdm1->pwrdm.ptr->prcm_offs, | ||
| 684 | OMAP3430_CM_SLEEPDEP); | ||
| 685 | } | ||
| 686 | |||
| 687 | return 0; | ||
| 688 | } | ||
| 689 | |||
| 690 | /** | ||
| 691 | * clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1 | ||
| 692 | * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) | ||
| 693 | * @clkdm2: when this struct clockdomain * is active (source) | ||
| 694 | * | ||
| 695 | * Return 1 if a hardware sleep dependency exists wherein @clkdm1 will | ||
| 696 | * not be allowed to automatically go inactive if @clkdm2 is active; | ||
| 697 | * 0 if @clkdm1's automatic power state inactivity transition is independent | ||
| 698 | * of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called | ||
| 699 | * on a machine that does not support software-configurable hardware sleep | ||
| 700 | * dependencies; or -ENOENT if the hardware is incapable. | ||
| 701 | * | ||
| 702 | * REVISIT: Currently this function only represents software-controllable | ||
| 703 | * sleep dependencies. Sleep dependencies fixed in hardware are not | ||
| 704 | * yet handled here. | ||
| 705 | */ | ||
| 706 | int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | ||
| 707 | { | ||
| 708 | struct clkdm_dep *cd; | ||
| 709 | |||
| 710 | if (!cpu_is_omap34xx()) | ||
| 711 | return -EINVAL; | ||
| 712 | |||
| 713 | if (!clkdm1 || !clkdm2) | ||
| 714 | return -EINVAL; | ||
| 715 | |||
| 716 | cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); | ||
| 717 | if (IS_ERR(cd)) { | ||
| 718 | pr_debug("clockdomain: hardware cannot set/clear sleep " | ||
| 719 | "dependency affecting %s from %s\n", clkdm1->name, | ||
| 720 | clkdm2->name); | ||
| 721 | return PTR_ERR(cd); | ||
| 722 | } | ||
| 723 | |||
| 724 | /* XXX It's faster to return the atomic sleepdep_usecount */ | ||
| 725 | return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, | ||
| 726 | OMAP3430_CM_SLEEPDEP, | ||
| 727 | (1 << clkdm2->dep_bit)); | ||
| 728 | } | ||
| 729 | |||
| 730 | /** | ||
| 731 | * clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm | ||
| 732 | * @clkdm: struct clockdomain * to remove all sleep dependencies from | ||
| 733 | * | ||
| 734 | * Remove all inter-clockdomain sleep dependencies that could prevent | ||
| 735 | * @clkdm from idling. Intended to be used during boot to initialize the | ||
| 736 | * PRCM to a known state, after all clockdomains are put into swsup idle | ||
| 737 | * and woken up. Returns -EINVAL if @clkdm pointer is invalid, or | ||
| 738 | * 0 upon success. | ||
| 739 | */ | ||
| 740 | int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) | ||
| 741 | { | ||
| 742 | struct clkdm_dep *cd; | ||
| 743 | u32 mask = 0; | ||
| 744 | |||
| 745 | if (!cpu_is_omap34xx()) | ||
| 746 | return -EINVAL; | ||
| 747 | |||
| 748 | if (!clkdm) | ||
| 749 | return -EINVAL; | ||
| 750 | |||
| 751 | for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { | ||
| 752 | if (!omap_chip_is(cd->omap_chip)) | ||
| 753 | continue; | ||
| 754 | |||
| 755 | /* PRM accesses are slow, so minimize them */ | ||
| 756 | mask |= 1 << cd->clkdm->dep_bit; | ||
| 757 | atomic_set(&cd->sleepdep_usecount, 0); | ||
| 758 | } | ||
| 759 | |||
| 760 | prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, | ||
| 761 | OMAP3430_CM_SLEEPDEP); | ||
| 762 | |||
| 763 | return 0; | ||
| 764 | } | ||
| 765 | |||
| 766 | /** | ||
| 370 | * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode | 767 | * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode |
| 371 | * @clk: struct clk * of a clockdomain | 768 | * @clkdm: struct clkdm * of a clockdomain |
| 372 | * | 769 | * |
| 373 | * Return the clockdomain's current state transition mode from the | 770 | * Return the clockdomain @clkdm current state transition mode from the |
| 374 | * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk | 771 | * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if @clkdm |
| 375 | * is NULL or the current mode upon success. | 772 | * is NULL or the current mode upon success. |
| 376 | */ | 773 | */ |
| 377 | static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) | 774 | static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) |
| @@ -381,7 +778,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) | |||
| 381 | if (!clkdm) | 778 | if (!clkdm) |
| 382 | return -EINVAL; | 779 | return -EINVAL; |
| 383 | 780 | ||
| 384 | v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); | 781 | v = __raw_readl(clkdm->clkstctrl_reg); |
| 385 | v &= clkdm->clktrctrl_mask; | 782 | v &= clkdm->clktrctrl_mask; |
| 386 | v >>= __ffs(clkdm->clktrctrl_mask); | 783 | v >>= __ffs(clkdm->clktrctrl_mask); |
| 387 | 784 | ||
| @@ -393,7 +790,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) | |||
| 393 | * @clkdm: struct clockdomain * | 790 | * @clkdm: struct clockdomain * |
| 394 | * | 791 | * |
| 395 | * Instruct the CM to force a sleep transition on the specified | 792 | * Instruct the CM to force a sleep transition on the specified |
| 396 | * clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if | 793 | * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if |
| 397 | * clockdomain does not support software-initiated sleep; 0 upon | 794 | * clockdomain does not support software-initiated sleep; 0 upon |
| 398 | * success. | 795 | * success. |
| 399 | */ | 796 | */ |
| @@ -413,15 +810,17 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 413 | if (cpu_is_omap24xx()) { | 810 | if (cpu_is_omap24xx()) { |
| 414 | 811 | ||
| 415 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, | 812 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, |
| 416 | clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); | 813 | clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); |
| 417 | 814 | ||
| 418 | } else if (cpu_is_omap34xx()) { | 815 | } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { |
| 419 | 816 | ||
| 420 | u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << | 817 | u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << |
| 421 | __ffs(clkdm->clktrctrl_mask)); | 818 | __ffs(clkdm->clktrctrl_mask)); |
| 422 | 819 | ||
| 423 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, | 820 | u32 v = __raw_readl(clkdm->clkstctrl_reg); |
| 424 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); | 821 | v &= ~(clkdm->clktrctrl_mask); |
| 822 | v |= bits; | ||
| 823 | __raw_writel(v, clkdm->clkstctrl_reg); | ||
| 425 | 824 | ||
| 426 | } else { | 825 | } else { |
| 427 | BUG(); | 826 | BUG(); |
| @@ -435,7 +834,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 435 | * @clkdm: struct clockdomain * | 834 | * @clkdm: struct clockdomain * |
| 436 | * | 835 | * |
| 437 | * Instruct the CM to force a wakeup transition on the specified | 836 | * Instruct the CM to force a wakeup transition on the specified |
| 438 | * clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the | 837 | * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the |
| 439 | * clockdomain does not support software-controlled wakeup; 0 upon | 838 | * clockdomain does not support software-controlled wakeup; 0 upon |
| 440 | * success. | 839 | * success. |
| 441 | */ | 840 | */ |
| @@ -455,15 +854,17 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 455 | if (cpu_is_omap24xx()) { | 854 | if (cpu_is_omap24xx()) { |
| 456 | 855 | ||
| 457 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, | 856 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, |
| 458 | clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); | 857 | clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); |
| 459 | 858 | ||
| 460 | } else if (cpu_is_omap34xx()) { | 859 | } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { |
| 461 | 860 | ||
| 462 | u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << | 861 | u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << |
| 463 | __ffs(clkdm->clktrctrl_mask)); | 862 | __ffs(clkdm->clktrctrl_mask)); |
| 464 | 863 | ||
| 465 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, | 864 | u32 v = __raw_readl(clkdm->clkstctrl_reg); |
| 466 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); | 865 | v &= ~(clkdm->clktrctrl_mask); |
| 866 | v |= bits; | ||
| 867 | __raw_writel(v, clkdm->clkstctrl_reg); | ||
| 467 | 868 | ||
| 468 | } else { | 869 | } else { |
| 469 | BUG(); | 870 | BUG(); |
| @@ -476,7 +877,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 476 | * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm | 877 | * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm |
| 477 | * @clkdm: struct clockdomain * | 878 | * @clkdm: struct clockdomain * |
| 478 | * | 879 | * |
| 479 | * Allow the hardware to automatically switch the clockdomain into | 880 | * Allow the hardware to automatically switch the clockdomain @clkdm into |
| 480 | * active or idle states, as needed by downstream clocks. If the | 881 | * active or idle states, as needed by downstream clocks. If the |
| 481 | * clockdomain has any downstream clocks enabled in the clock | 882 | * clockdomain has any downstream clocks enabled in the clock |
| 482 | * framework, wkdep/sleepdep autodependencies are added; this is so | 883 | * framework, wkdep/sleepdep autodependencies are added; this is so |
| @@ -496,8 +897,17 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) | |||
| 496 | pr_debug("clockdomain: enabling automatic idle transitions for %s\n", | 897 | pr_debug("clockdomain: enabling automatic idle transitions for %s\n", |
| 497 | clkdm->name); | 898 | clkdm->name); |
| 498 | 899 | ||
| 499 | if (atomic_read(&clkdm->usecount) > 0) | 900 | /* |
| 500 | _clkdm_add_autodeps(clkdm); | 901 | * XXX This should be removed once TI adds wakeup/sleep |
| 902 | * dependency code and data for OMAP4. | ||
| 903 | */ | ||
| 904 | if (cpu_is_omap44xx()) { | ||
| 905 | WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency " | ||
| 906 | "support is not yet implemented\n"); | ||
| 907 | } else { | ||
| 908 | if (atomic_read(&clkdm->usecount) > 0) | ||
| 909 | _clkdm_add_autodeps(clkdm); | ||
| 910 | } | ||
| 501 | 911 | ||
| 502 | _omap2_clkdm_set_hwsup(clkdm, 1); | 912 | _omap2_clkdm_set_hwsup(clkdm, 1); |
| 503 | 913 | ||
| @@ -509,8 +919,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) | |||
| 509 | * @clkdm: struct clockdomain * | 919 | * @clkdm: struct clockdomain * |
| 510 | * | 920 | * |
| 511 | * Prevent the hardware from automatically switching the clockdomain | 921 | * Prevent the hardware from automatically switching the clockdomain |
| 512 | * into inactive or idle states. If the clockdomain has downstream | 922 | * @clkdm into inactive or idle states. If the clockdomain has |
| 513 | * clocks enabled in the clock framework, wkdep/sleepdep | 923 | * downstream clocks enabled in the clock framework, wkdep/sleepdep |
| 514 | * autodependencies are removed. No return value. | 924 | * autodependencies are removed. No return value. |
| 515 | */ | 925 | */ |
| 516 | void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | 926 | void omap2_clkdm_deny_idle(struct clockdomain *clkdm) |
| @@ -529,8 +939,17 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 529 | 939 | ||
| 530 | _omap2_clkdm_set_hwsup(clkdm, 0); | 940 | _omap2_clkdm_set_hwsup(clkdm, 0); |
| 531 | 941 | ||
| 532 | if (atomic_read(&clkdm->usecount) > 0) | 942 | /* |
| 533 | _clkdm_del_autodeps(clkdm); | 943 | * XXX This should be removed once TI adds wakeup/sleep |
| 944 | * dependency code and data for OMAP4. | ||
| 945 | */ | ||
| 946 | if (cpu_is_omap44xx()) { | ||
| 947 | WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency " | ||
| 948 | "support is not yet implemented\n"); | ||
| 949 | } else { | ||
| 950 | if (atomic_read(&clkdm->usecount) > 0) | ||
| 951 | _clkdm_del_autodeps(clkdm); | ||
| 952 | } | ||
| 534 | } | 953 | } |
| 535 | 954 | ||
| 536 | 955 | ||
| @@ -541,14 +960,14 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 541 | * @clkdm: struct clockdomain * | 960 | * @clkdm: struct clockdomain * |
| 542 | * @clk: struct clk * of the enabled downstream clock | 961 | * @clk: struct clk * of the enabled downstream clock |
| 543 | * | 962 | * |
| 544 | * Increment the usecount of this clockdomain 'clkdm' and ensure that | 963 | * Increment the usecount of the clockdomain @clkdm and ensure that it |
| 545 | * it is awake. Intended to be called by clk_enable() code. If the | 964 | * is awake before @clk is enabled. Intended to be called by |
| 546 | * clockdomain is in software-supervised idle mode, force the | 965 | * clk_enable() code. If the clockdomain is in software-supervised |
| 547 | * clockdomain to wake. If the clockdomain is in hardware-supervised | 966 | * idle mode, force the clockdomain to wake. If the clockdomain is in |
| 548 | * idle mode, add clkdm-pwrdm autodependencies, to ensure that devices | 967 | * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to |
| 549 | * in the clockdomain can be read from/written to by on-chip processors. | 968 | * ensure that devices in the clockdomain can be read from/written to |
| 550 | * Returns -EINVAL if passed null pointers; returns 0 upon success or | 969 | * by on-chip processors. Returns -EINVAL if passed null pointers; |
| 551 | * if the clockdomain is in hwsup idle mode. | 970 | * returns 0 upon success or if the clockdomain is in hwsup idle mode. |
| 552 | */ | 971 | */ |
| 553 | int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | 972 | int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) |
| 554 | { | 973 | { |
| @@ -559,7 +978,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 559 | * downstream clocks for debugging purposes? | 978 | * downstream clocks for debugging purposes? |
| 560 | */ | 979 | */ |
| 561 | 980 | ||
| 562 | if (!clkdm || !clk || !clkdm->clktrctrl_mask) | 981 | if (!clkdm || !clk) |
| 563 | return -EINVAL; | 982 | return -EINVAL; |
| 564 | 983 | ||
| 565 | if (atomic_inc_return(&clkdm->usecount) > 1) | 984 | if (atomic_inc_return(&clkdm->usecount) > 1) |
| @@ -570,6 +989,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 570 | pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, | 989 | pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, |
| 571 | clk->name); | 990 | clk->name); |
| 572 | 991 | ||
| 992 | if (!clkdm->clkstctrl_reg) | ||
| 993 | return 0; | ||
| 994 | |||
| 573 | v = omap2_clkdm_clktrctrl_read(clkdm); | 995 | v = omap2_clkdm_clktrctrl_read(clkdm); |
| 574 | 996 | ||
| 575 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || | 997 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || |
| @@ -593,13 +1015,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 593 | * @clkdm: struct clockdomain * | 1015 | * @clkdm: struct clockdomain * |
| 594 | * @clk: struct clk * of the disabled downstream clock | 1016 | * @clk: struct clk * of the disabled downstream clock |
| 595 | * | 1017 | * |
| 596 | * Decrement the usecount of this clockdomain 'clkdm'. Intended to be | 1018 | * Decrement the usecount of this clockdomain @clkdm when @clk is |
| 597 | * called by clk_disable() code. If the usecount goes to 0, put the | 1019 | * disabled. Intended to be called by clk_disable() code. If the |
| 598 | * clockdomain to sleep (software-supervised mode) or remove the | 1020 | * clockdomain usecount goes to 0, put the clockdomain to sleep |
| 599 | * clkdm-pwrdm autodependencies (hardware-supervised mode). Returns | 1021 | * (software-supervised mode) or remove the clkdm autodependencies |
| 600 | * -EINVAL if passed null pointers; -ERANGE if the clkdm usecount | 1022 | * (hardware-supervised mode). Returns -EINVAL if passed null |
| 601 | * underflows and debugging is enabled; or returns 0 upon success or | 1023 | * pointers; -ERANGE if the @clkdm usecount underflows and debugging |
| 602 | * if the clockdomain is in hwsup idle mode. | 1024 | * is enabled; or returns 0 upon success or if the clockdomain is in |
| 1025 | * hwsup idle mode. | ||
| 603 | */ | 1026 | */ |
| 604 | int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | 1027 | int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) |
| 605 | { | 1028 | { |
| @@ -610,7 +1033,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | |||
| 610 | * downstream clocks for debugging purposes? | 1033 | * downstream clocks for debugging purposes? |
| 611 | */ | 1034 | */ |
| 612 | 1035 | ||
| 613 | if (!clkdm || !clk || !clkdm->clktrctrl_mask) | 1036 | if (!clkdm || !clk) |
| 614 | return -EINVAL; | 1037 | return -EINVAL; |
| 615 | 1038 | ||
| 616 | #ifdef DEBUG | 1039 | #ifdef DEBUG |
| @@ -628,6 +1051,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | |||
| 628 | pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, | 1051 | pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, |
| 629 | clk->name); | 1052 | clk->name); |
| 630 | 1053 | ||
| 1054 | if (!clkdm->clkstctrl_reg) | ||
| 1055 | return 0; | ||
| 1056 | |||
| 631 | v = omap2_clkdm_clktrctrl_read(clkdm); | 1057 | v = omap2_clkdm_clktrctrl_read(clkdm); |
| 632 | 1058 | ||
| 633 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || | 1059 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || |
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index c4ee0761d908..8fc19ff2cd89 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h | |||
| @@ -1,16 +1,420 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP2/3 clockdomains | 2 | * OMAP2/3 clockdomains |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2008-2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2008 Nokia Corporation | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley and Jouni Högander |
| 8 | * | ||
| 9 | * This file contains clockdomains and clockdomain wakeup/sleep | ||
| 10 | * dependencies for the OMAP2/3 chips. Some notes: | ||
| 11 | * | ||
| 12 | * A useful validation rule for struct clockdomain: Any clockdomain | ||
| 13 | * referenced by a wkdep_srcs or sleepdep_srcs array must have a | ||
| 14 | * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just | ||
| 15 | * software-controllable dependencies. Non-software-controllable | ||
| 16 | * dependencies do exist, but they are not encoded below (yet). | ||
| 17 | * | ||
| 18 | * 24xx does not support programmable sleep dependencies (SLEEPDEP) | ||
| 19 | * | ||
| 20 | * The overly-specific dep_bit names are due to a bit name collision | ||
| 21 | * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift | ||
| 22 | * value are the same for all powerdomains: 2 | ||
| 23 | * | ||
| 24 | * XXX should dep_bit be a mask, so we can test to see if it is 0 as a | ||
| 25 | * sanity check? | ||
| 26 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE | ||
| 27 | */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * To-Do List | ||
| 31 | * -> Port the Sleep/Wakeup dependencies for the domains | ||
| 32 | * from the Power domain framework | ||
| 8 | */ | 33 | */ |
| 9 | 34 | ||
| 10 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H | 35 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H |
| 11 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H | 36 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H |
| 12 | 37 | ||
| 13 | #include <plat/clockdomain.h> | 38 | #include <plat/clockdomain.h> |
| 39 | #include "cm.h" | ||
| 40 | #include "prm.h" | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Clockdomain dependencies for wkdeps/sleepdeps | ||
| 44 | * | ||
| 45 | * XXX Hardware dependencies (e.g., dependencies that cannot be | ||
| 46 | * changed in software) are not included here yet, but should be. | ||
| 47 | */ | ||
| 48 | |||
| 49 | /* OMAP2/3-common wakeup dependencies */ | ||
| 50 | |||
| 51 | /* | ||
| 52 | * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP | ||
| 53 | * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE | ||
| 54 | * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE | ||
| 55 | * These can share data since they will never be present simultaneously | ||
| 56 | * on the same device. | ||
| 57 | */ | ||
| 58 | static struct clkdm_dep gfx_sgx_wkdeps[] = { | ||
| 59 | { | ||
| 60 | .clkdm_name = "core_l3_clkdm", | ||
| 61 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 62 | }, | ||
| 63 | { | ||
| 64 | .clkdm_name = "core_l4_clkdm", | ||
| 65 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 66 | }, | ||
| 67 | { | ||
| 68 | .clkdm_name = "iva2_clkdm", | ||
| 69 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 70 | }, | ||
| 71 | { | ||
| 72 | .clkdm_name = "mpu_clkdm", | ||
| 73 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | ||
| 74 | CHIP_IS_OMAP3430) | ||
| 75 | }, | ||
| 76 | { | ||
| 77 | .clkdm_name = "wkup_clkdm", | ||
| 78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | ||
| 79 | CHIP_IS_OMAP3430) | ||
| 80 | }, | ||
| 81 | { NULL }, | ||
| 82 | }; | ||
| 83 | |||
| 84 | |||
| 85 | /* 24XX-specific possible dependencies */ | ||
| 86 | |||
| 87 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 88 | |||
| 89 | /* Wakeup dependency source arrays */ | ||
| 90 | |||
| 91 | /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ | ||
| 92 | static struct clkdm_dep dsp_24xx_wkdeps[] = { | ||
| 93 | { | ||
| 94 | .clkdm_name = "core_l3_clkdm", | ||
| 95 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 96 | }, | ||
| 97 | { | ||
| 98 | .clkdm_name = "core_l4_clkdm", | ||
| 99 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 100 | }, | ||
| 101 | { | ||
| 102 | .clkdm_name = "mpu_clkdm", | ||
| 103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .clkdm_name = "wkup_clkdm", | ||
| 107 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 108 | }, | ||
| 109 | { NULL }, | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP | ||
| 114 | * 2430 adds MDM | ||
| 115 | */ | ||
| 116 | static struct clkdm_dep mpu_24xx_wkdeps[] = { | ||
| 117 | { | ||
| 118 | .clkdm_name = "core_l3_clkdm", | ||
| 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 120 | }, | ||
| 121 | { | ||
| 122 | .clkdm_name = "core_l4_clkdm", | ||
| 123 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 124 | }, | ||
| 125 | { | ||
| 126 | .clkdm_name = "dsp_clkdm", | ||
| 127 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 128 | }, | ||
| 129 | { | ||
| 130 | .clkdm_name = "wkup_clkdm", | ||
| 131 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 132 | }, | ||
| 133 | { | ||
| 134 | .clkdm_name = "mdm_clkdm", | ||
| 135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | ||
| 136 | }, | ||
| 137 | { NULL }, | ||
| 138 | }; | ||
| 139 | |||
| 140 | /* | ||
| 141 | * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP | ||
| 142 | * 2430 adds MDM | ||
| 143 | */ | ||
| 144 | static struct clkdm_dep core_24xx_wkdeps[] = { | ||
| 145 | { | ||
| 146 | .clkdm_name = "dsp_clkdm", | ||
| 147 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 148 | }, | ||
| 149 | { | ||
| 150 | .clkdm_name = "gfx_clkdm", | ||
| 151 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 152 | }, | ||
| 153 | { | ||
| 154 | .clkdm_name = "mpu_clkdm", | ||
| 155 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 156 | }, | ||
| 157 | { | ||
| 158 | .clkdm_name = "wkup_clkdm", | ||
| 159 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 160 | }, | ||
| 161 | { | ||
| 162 | .clkdm_name = "mdm_clkdm", | ||
| 163 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | ||
| 164 | }, | ||
| 165 | { NULL }, | ||
| 166 | }; | ||
| 167 | |||
| 168 | #endif | ||
| 169 | |||
| 170 | |||
| 171 | /* 2430-specific possible wakeup dependencies */ | ||
| 172 | |||
| 173 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 174 | |||
| 175 | /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ | ||
| 176 | static struct clkdm_dep mdm_2430_wkdeps[] = { | ||
| 177 | { | ||
| 178 | .clkdm_name = "core_l3_clkdm", | ||
| 179 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 180 | }, | ||
| 181 | { | ||
| 182 | .clkdm_name = "core_l4_clkdm", | ||
| 183 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 184 | }, | ||
| 185 | { | ||
| 186 | .clkdm_name = "mpu_clkdm", | ||
| 187 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 188 | }, | ||
| 189 | { | ||
| 190 | .clkdm_name = "wkup_clkdm", | ||
| 191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 192 | }, | ||
| 193 | { NULL }, | ||
| 194 | }; | ||
| 195 | |||
| 196 | #endif /* CONFIG_ARCH_OMAP2430 */ | ||
| 197 | |||
| 198 | |||
| 199 | /* OMAP3-specific possible dependencies */ | ||
| 200 | |||
| 201 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 202 | |||
| 203 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ | ||
| 204 | static struct clkdm_dep per_wkdeps[] = { | ||
| 205 | { | ||
| 206 | .clkdm_name = "core_l3_clkdm", | ||
| 207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 208 | }, | ||
| 209 | { | ||
| 210 | .clkdm_name = "core_l4_clkdm", | ||
| 211 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 212 | }, | ||
| 213 | { | ||
| 214 | .clkdm_name = "iva2_clkdm", | ||
| 215 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 216 | }, | ||
| 217 | { | ||
| 218 | .clkdm_name = "mpu_clkdm", | ||
| 219 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 220 | }, | ||
| 221 | { | ||
| 222 | .clkdm_name = "wkup_clkdm", | ||
| 223 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 224 | }, | ||
| 225 | { NULL }, | ||
| 226 | }; | ||
| 227 | |||
| 228 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ | ||
| 229 | static struct clkdm_dep usbhost_wkdeps[] = { | ||
| 230 | { | ||
| 231 | .clkdm_name = "core_l3_clkdm", | ||
| 232 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 233 | }, | ||
| 234 | { | ||
| 235 | .clkdm_name = "core_l4_clkdm", | ||
| 236 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 237 | }, | ||
| 238 | { | ||
| 239 | .clkdm_name = "iva2_clkdm", | ||
| 240 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 241 | }, | ||
| 242 | { | ||
| 243 | .clkdm_name = "mpu_clkdm", | ||
| 244 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 245 | }, | ||
| 246 | { | ||
| 247 | .clkdm_name = "wkup_clkdm", | ||
| 248 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 249 | }, | ||
| 250 | { NULL }, | ||
| 251 | }; | ||
| 252 | |||
| 253 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ | ||
| 254 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { | ||
| 255 | { | ||
| 256 | .clkdm_name = "core_l3_clkdm", | ||
| 257 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 258 | }, | ||
| 259 | { | ||
| 260 | .clkdm_name = "core_l4_clkdm", | ||
| 261 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 262 | }, | ||
| 263 | { | ||
| 264 | .clkdm_name = "iva2_clkdm", | ||
| 265 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 266 | }, | ||
| 267 | { | ||
| 268 | .clkdm_name = "dss_clkdm", | ||
| 269 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 270 | }, | ||
| 271 | { | ||
| 272 | .clkdm_name = "per_clkdm", | ||
| 273 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 274 | }, | ||
| 275 | { NULL }, | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ | ||
| 279 | static struct clkdm_dep iva2_wkdeps[] = { | ||
| 280 | { | ||
| 281 | .clkdm_name = "core_l3_clkdm", | ||
| 282 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 283 | }, | ||
| 284 | { | ||
| 285 | .clkdm_name = "core_l4_clkdm", | ||
| 286 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 287 | }, | ||
| 288 | { | ||
| 289 | .clkdm_name = "mpu_clkdm", | ||
| 290 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 291 | }, | ||
| 292 | { | ||
| 293 | .clkdm_name = "wkup_clkdm", | ||
| 294 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 295 | }, | ||
| 296 | { | ||
| 297 | .clkdm_name = "dss_clkdm", | ||
| 298 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 299 | }, | ||
| 300 | { | ||
| 301 | .clkdm_name = "per_clkdm", | ||
| 302 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 303 | }, | ||
| 304 | { NULL }, | ||
| 305 | }; | ||
| 306 | |||
| 307 | |||
| 308 | /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */ | ||
| 309 | static struct clkdm_dep cam_wkdeps[] = { | ||
| 310 | { | ||
| 311 | .clkdm_name = "iva2_clkdm", | ||
| 312 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 313 | }, | ||
| 314 | { | ||
| 315 | .clkdm_name = "mpu_clkdm", | ||
| 316 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 317 | }, | ||
| 318 | { | ||
| 319 | .clkdm_name = "wkup_clkdm", | ||
| 320 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 321 | }, | ||
| 322 | { NULL }, | ||
| 323 | }; | ||
| 324 | |||
| 325 | /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */ | ||
| 326 | static struct clkdm_dep dss_wkdeps[] = { | ||
| 327 | { | ||
| 328 | .clkdm_name = "iva2_clkdm", | ||
| 329 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 330 | }, | ||
| 331 | { | ||
| 332 | .clkdm_name = "mpu_clkdm", | ||
| 333 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 334 | }, | ||
| 335 | { | ||
| 336 | .clkdm_name = "wkup_clkdm", | ||
| 337 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 338 | }, | ||
| 339 | { NULL }, | ||
| 340 | }; | ||
| 341 | |||
| 342 | /* 3430: PM_WKDEP_NEON: MPU */ | ||
| 343 | static struct clkdm_dep neon_wkdeps[] = { | ||
| 344 | { | ||
| 345 | .clkdm_name = "mpu_clkdm", | ||
| 346 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 347 | }, | ||
| 348 | { NULL }, | ||
| 349 | }; | ||
| 350 | |||
| 351 | |||
| 352 | /* Sleep dependency source arrays for OMAP3-specific clkdms */ | ||
| 353 | |||
| 354 | /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */ | ||
| 355 | static struct clkdm_dep dss_sleepdeps[] = { | ||
| 356 | { | ||
| 357 | .clkdm_name = "mpu_clkdm", | ||
| 358 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 359 | }, | ||
| 360 | { | ||
| 361 | .clkdm_name = "iva2_clkdm", | ||
| 362 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 363 | }, | ||
| 364 | { NULL }, | ||
| 365 | }; | ||
| 366 | |||
| 367 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ | ||
| 368 | static struct clkdm_dep per_sleepdeps[] = { | ||
| 369 | { | ||
| 370 | .clkdm_name = "mpu_clkdm", | ||
| 371 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 372 | }, | ||
| 373 | { | ||
| 374 | .clkdm_name = "iva2_clkdm", | ||
| 375 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 376 | }, | ||
| 377 | { NULL }, | ||
| 378 | }; | ||
| 379 | |||
| 380 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ | ||
| 381 | static struct clkdm_dep usbhost_sleepdeps[] = { | ||
| 382 | { | ||
| 383 | .clkdm_name = "mpu_clkdm", | ||
| 384 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 385 | }, | ||
| 386 | { | ||
| 387 | .clkdm_name = "iva2_clkdm", | ||
| 388 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 389 | }, | ||
| 390 | { NULL }, | ||
| 391 | }; | ||
| 392 | |||
| 393 | /* 3430: CM_SLEEPDEP_CAM: MPU */ | ||
| 394 | static struct clkdm_dep cam_sleepdeps[] = { | ||
| 395 | { | ||
| 396 | .clkdm_name = "mpu_clkdm", | ||
| 397 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 398 | }, | ||
| 399 | { NULL }, | ||
| 400 | }; | ||
| 401 | |||
| 402 | /* | ||
| 403 | * 3430ES1: CM_SLEEPDEP_GFX: MPU | ||
| 404 | * 3430ES2: CM_SLEEPDEP_SGX: MPU | ||
| 405 | * These can share data since they will never be present simultaneously | ||
| 406 | * on the same device. | ||
| 407 | */ | ||
| 408 | static struct clkdm_dep gfx_sgx_sleepdeps[] = { | ||
| 409 | { | ||
| 410 | .clkdm_name = "mpu_clkdm", | ||
| 411 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 412 | }, | ||
| 413 | { NULL }, | ||
| 414 | }; | ||
| 415 | |||
| 416 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
| 417 | |||
| 14 | 418 | ||
| 15 | /* | 419 | /* |
| 16 | * OMAP2/3-common clockdomains | 420 | * OMAP2/3-common clockdomains |
| @@ -21,10 +425,13 @@ | |||
| 21 | * sys_clkout/sys_clkout2. | 425 | * sys_clkout/sys_clkout2. |
| 22 | */ | 426 | */ |
| 23 | 427 | ||
| 428 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 429 | |||
| 24 | /* This is an implicit clockdomain - it is never defined as such in TRM */ | 430 | /* This is an implicit clockdomain - it is never defined as such in TRM */ |
| 25 | static struct clockdomain wkup_clkdm = { | 431 | static struct clockdomain wkup_clkdm = { |
| 26 | .name = "wkup_clkdm", | 432 | .name = "wkup_clkdm", |
| 27 | .pwrdm = { .name = "wkup_pwrdm" }, | 433 | .pwrdm = { .name = "wkup_pwrdm" }, |
| 434 | .dep_bit = OMAP_EN_WKUP_SHIFT, | ||
| 28 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 435 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 29 | }; | 436 | }; |
| 30 | 437 | ||
| @@ -40,6 +447,8 @@ static struct clockdomain cm_clkdm = { | |||
| 40 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 447 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 41 | }; | 448 | }; |
| 42 | 449 | ||
| 450 | #endif | ||
| 451 | |||
| 43 | /* | 452 | /* |
| 44 | * 2420-only clockdomains | 453 | * 2420-only clockdomains |
| 45 | */ | 454 | */ |
| @@ -50,6 +459,8 @@ static struct clockdomain mpu_2420_clkdm = { | |||
| 50 | .name = "mpu_clkdm", | 459 | .name = "mpu_clkdm", |
| 51 | .pwrdm = { .name = "mpu_pwrdm" }, | 460 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 52 | .flags = CLKDM_CAN_HWSUP, | 461 | .flags = CLKDM_CAN_HWSUP, |
| 462 | .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 463 | .wkdep_srcs = mpu_24xx_wkdeps, | ||
| 53 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 464 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 54 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 465 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 55 | }; | 466 | }; |
| @@ -58,11 +469,64 @@ static struct clockdomain iva1_2420_clkdm = { | |||
| 58 | .name = "iva1_clkdm", | 469 | .name = "iva1_clkdm", |
| 59 | .pwrdm = { .name = "dsp_pwrdm" }, | 470 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 60 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 471 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 472 | .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, | ||
| 473 | OMAP2_CM_CLKSTCTRL), | ||
| 474 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, | ||
| 475 | .wkdep_srcs = dsp_24xx_wkdeps, | ||
| 61 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, | 476 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
| 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 477 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 63 | }; | 478 | }; |
| 64 | 479 | ||
| 65 | #endif /* CONFIG_ARCH_OMAP2420 */ | 480 | static struct clockdomain dsp_2420_clkdm = { |
| 481 | .name = "dsp_clkdm", | ||
| 482 | .pwrdm = { .name = "dsp_pwrdm" }, | ||
| 483 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 484 | .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, | ||
| 485 | OMAP2_CM_CLKSTCTRL), | ||
| 486 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | ||
| 487 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 488 | }; | ||
| 489 | |||
| 490 | static struct clockdomain gfx_2420_clkdm = { | ||
| 491 | .name = "gfx_clkdm", | ||
| 492 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
| 493 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 494 | .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 495 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
| 496 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | ||
| 497 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 498 | }; | ||
| 499 | |||
| 500 | static struct clockdomain core_l3_2420_clkdm = { | ||
| 501 | .name = "core_l3_clkdm", | ||
| 502 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 503 | .flags = CLKDM_CAN_HWSUP, | ||
| 504 | .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 505 | .wkdep_srcs = core_24xx_wkdeps, | ||
| 506 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | ||
| 507 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 508 | }; | ||
| 509 | |||
| 510 | static struct clockdomain core_l4_2420_clkdm = { | ||
| 511 | .name = "core_l4_clkdm", | ||
| 512 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 513 | .flags = CLKDM_CAN_HWSUP, | ||
| 514 | .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 515 | .wkdep_srcs = core_24xx_wkdeps, | ||
| 516 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | ||
| 517 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 518 | }; | ||
| 519 | |||
| 520 | static struct clockdomain dss_2420_clkdm = { | ||
| 521 | .name = "dss_clkdm", | ||
| 522 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 523 | .flags = CLKDM_CAN_HWSUP, | ||
| 524 | .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 525 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | ||
| 526 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 527 | }; | ||
| 528 | |||
| 529 | #endif /* CONFIG_ARCH_OMAP2420 */ | ||
| 66 | 530 | ||
| 67 | 531 | ||
| 68 | /* | 532 | /* |
| @@ -75,80 +539,105 @@ static struct clockdomain mpu_2430_clkdm = { | |||
| 75 | .name = "mpu_clkdm", | 539 | .name = "mpu_clkdm", |
| 76 | .pwrdm = { .name = "mpu_pwrdm" }, | 540 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 77 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 541 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 542 | .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD, | ||
| 543 | OMAP2_CM_CLKSTCTRL), | ||
| 544 | .wkdep_srcs = mpu_24xx_wkdeps, | ||
| 78 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 545 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 546 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 80 | }; | 547 | }; |
| 81 | 548 | ||
| 549 | /* Another case of bit name collisions between several registers: EN_MDM */ | ||
| 82 | static struct clockdomain mdm_clkdm = { | 550 | static struct clockdomain mdm_clkdm = { |
| 83 | .name = "mdm_clkdm", | 551 | .name = "mdm_clkdm", |
| 84 | .pwrdm = { .name = "mdm_pwrdm" }, | 552 | .pwrdm = { .name = "mdm_pwrdm" }, |
| 85 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 553 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 554 | .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD, | ||
| 555 | OMAP2_CM_CLKSTCTRL), | ||
| 556 | .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, | ||
| 557 | .wkdep_srcs = mdm_2430_wkdeps, | ||
| 86 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, | 558 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, |
| 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 559 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 88 | }; | 560 | }; |
| 89 | 561 | ||
| 90 | #endif /* CONFIG_ARCH_OMAP2430 */ | 562 | static struct clockdomain dsp_2430_clkdm = { |
| 91 | |||
| 92 | |||
| 93 | /* | ||
| 94 | * 24XX-only clockdomains | ||
| 95 | */ | ||
| 96 | |||
| 97 | #if defined(CONFIG_ARCH_OMAP24XX) | ||
| 98 | |||
| 99 | static struct clockdomain dsp_clkdm = { | ||
| 100 | .name = "dsp_clkdm", | 563 | .name = "dsp_clkdm", |
| 101 | .pwrdm = { .name = "dsp_pwrdm" }, | 564 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 102 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 565 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 566 | .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD, | ||
| 567 | OMAP2_CM_CLKSTCTRL), | ||
| 568 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, | ||
| 569 | .wkdep_srcs = dsp_24xx_wkdeps, | ||
| 103 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | 570 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
| 104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 571 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 105 | }; | 572 | }; |
| 106 | 573 | ||
| 107 | static struct clockdomain gfx_24xx_clkdm = { | 574 | static struct clockdomain gfx_2430_clkdm = { |
| 108 | .name = "gfx_clkdm", | 575 | .name = "gfx_clkdm", |
| 109 | .pwrdm = { .name = "gfx_pwrdm" }, | 576 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 110 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 577 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 578 | .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 579 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
| 111 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | 580 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
| 112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 581 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 113 | }; | 582 | }; |
| 114 | 583 | ||
| 115 | static struct clockdomain core_l3_24xx_clkdm = { | 584 | /* |
| 585 | * XXX add usecounting for clkdm dependencies, otherwise the presence | ||
| 586 | * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm | ||
| 587 | * could cause trouble | ||
| 588 | */ | ||
| 589 | static struct clockdomain core_l3_2430_clkdm = { | ||
| 116 | .name = "core_l3_clkdm", | 590 | .name = "core_l3_clkdm", |
| 117 | .pwrdm = { .name = "core_pwrdm" }, | 591 | .pwrdm = { .name = "core_pwrdm" }, |
| 118 | .flags = CLKDM_CAN_HWSUP, | 592 | .flags = CLKDM_CAN_HWSUP, |
| 593 | .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 594 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, | ||
| 595 | .wkdep_srcs = core_24xx_wkdeps, | ||
| 119 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | 596 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
| 120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 597 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 121 | }; | 598 | }; |
| 122 | 599 | ||
| 123 | static struct clockdomain core_l4_24xx_clkdm = { | 600 | /* |
| 601 | * XXX add usecounting for clkdm dependencies, otherwise the presence | ||
| 602 | * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm | ||
| 603 | * could cause trouble | ||
| 604 | */ | ||
| 605 | static struct clockdomain core_l4_2430_clkdm = { | ||
| 124 | .name = "core_l4_clkdm", | 606 | .name = "core_l4_clkdm", |
| 125 | .pwrdm = { .name = "core_pwrdm" }, | 607 | .pwrdm = { .name = "core_pwrdm" }, |
| 126 | .flags = CLKDM_CAN_HWSUP, | 608 | .flags = CLKDM_CAN_HWSUP, |
| 609 | .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 610 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, | ||
| 611 | .wkdep_srcs = core_24xx_wkdeps, | ||
| 127 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | 612 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
| 128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 613 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 129 | }; | 614 | }; |
| 130 | 615 | ||
| 131 | static struct clockdomain dss_24xx_clkdm = { | 616 | static struct clockdomain dss_2430_clkdm = { |
| 132 | .name = "dss_clkdm", | 617 | .name = "dss_clkdm", |
| 133 | .pwrdm = { .name = "core_pwrdm" }, | 618 | .pwrdm = { .name = "core_pwrdm" }, |
| 134 | .flags = CLKDM_CAN_HWSUP, | 619 | .flags = CLKDM_CAN_HWSUP, |
| 620 | .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 135 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | 621 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
| 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 622 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 137 | }; | 623 | }; |
| 138 | 624 | ||
| 139 | #endif /* CONFIG_ARCH_OMAP24XX */ | 625 | #endif /* CONFIG_ARCH_OMAP2430 */ |
| 140 | 626 | ||
| 141 | 627 | ||
| 142 | /* | 628 | /* |
| 143 | * 34xx clockdomains | 629 | * OMAP3 clockdomains |
| 144 | */ | 630 | */ |
| 145 | 631 | ||
| 146 | #if defined(CONFIG_ARCH_OMAP34XX) | 632 | #if defined(CONFIG_ARCH_OMAP3) |
| 147 | 633 | ||
| 148 | static struct clockdomain mpu_34xx_clkdm = { | 634 | static struct clockdomain mpu_3xxx_clkdm = { |
| 149 | .name = "mpu_clkdm", | 635 | .name = "mpu_clkdm", |
| 150 | .pwrdm = { .name = "mpu_pwrdm" }, | 636 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 151 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | 637 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
| 638 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 639 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | ||
| 640 | .wkdep_srcs = mpu_3xxx_wkdeps, | ||
| 152 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 641 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
| 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 642 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 154 | }; | 643 | }; |
| @@ -157,6 +646,9 @@ static struct clockdomain neon_clkdm = { | |||
| 157 | .name = "neon_clkdm", | 646 | .name = "neon_clkdm", |
| 158 | .pwrdm = { .name = "neon_pwrdm" }, | 647 | .pwrdm = { .name = "neon_pwrdm" }, |
| 159 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 648 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 649 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD, | ||
| 650 | OMAP2_CM_CLKSTCTRL), | ||
| 651 | .wkdep_srcs = neon_wkdeps, | ||
| 160 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, | 652 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
| 161 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 653 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 162 | }; | 654 | }; |
| @@ -165,6 +657,10 @@ static struct clockdomain iva2_clkdm = { | |||
| 165 | .name = "iva2_clkdm", | 657 | .name = "iva2_clkdm", |
| 166 | .pwrdm = { .name = "iva2_pwrdm" }, | 658 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 167 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 659 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 660 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
| 661 | OMAP2_CM_CLKSTCTRL), | ||
| 662 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, | ||
| 663 | .wkdep_srcs = iva2_wkdeps, | ||
| 168 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, | 664 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
| 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 665 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 170 | }; | 666 | }; |
| @@ -173,6 +669,9 @@ static struct clockdomain gfx_3430es1_clkdm = { | |||
| 173 | .name = "gfx_clkdm", | 669 | .name = "gfx_clkdm", |
| 174 | .pwrdm = { .name = "gfx_pwrdm" }, | 670 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 175 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 671 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 672 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 673 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
| 674 | .sleepdep_srcs = gfx_sgx_sleepdeps, | ||
| 176 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, | 675 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
| 177 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | 676 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), |
| 178 | }; | 677 | }; |
| @@ -181,6 +680,10 @@ static struct clockdomain sgx_clkdm = { | |||
| 181 | .name = "sgx_clkdm", | 680 | .name = "sgx_clkdm", |
| 182 | .pwrdm = { .name = "sgx_pwrdm" }, | 681 | .pwrdm = { .name = "sgx_pwrdm" }, |
| 183 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 682 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 683 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, | ||
| 684 | OMAP2_CM_CLKSTCTRL), | ||
| 685 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
| 686 | .sleepdep_srcs = gfx_sgx_sleepdeps, | ||
| 184 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 687 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
| 185 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 688 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 186 | }; | 689 | }; |
| @@ -196,30 +699,51 @@ static struct clockdomain d2d_clkdm = { | |||
| 196 | .name = "d2d_clkdm", | 699 | .name = "d2d_clkdm", |
| 197 | .pwrdm = { .name = "core_pwrdm" }, | 700 | .pwrdm = { .name = "core_pwrdm" }, |
| 198 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 701 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 702 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 199 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, | 703 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
| 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 704 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 201 | }; | 705 | }; |
| 202 | 706 | ||
| 203 | static struct clockdomain core_l3_34xx_clkdm = { | 707 | /* |
| 708 | * XXX add usecounting for clkdm dependencies, otherwise the presence | ||
| 709 | * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm | ||
| 710 | * could cause trouble | ||
| 711 | */ | ||
| 712 | static struct clockdomain core_l3_3xxx_clkdm = { | ||
| 204 | .name = "core_l3_clkdm", | 713 | .name = "core_l3_clkdm", |
| 205 | .pwrdm = { .name = "core_pwrdm" }, | 714 | .pwrdm = { .name = "core_pwrdm" }, |
| 206 | .flags = CLKDM_CAN_HWSUP, | 715 | .flags = CLKDM_CAN_HWSUP, |
| 716 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 717 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | ||
| 207 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, | 718 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
| 208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 719 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 209 | }; | 720 | }; |
| 210 | 721 | ||
| 211 | static struct clockdomain core_l4_34xx_clkdm = { | 722 | /* |
| 723 | * XXX add usecounting for clkdm dependencies, otherwise the presence | ||
| 724 | * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm | ||
| 725 | * could cause trouble | ||
| 726 | */ | ||
| 727 | static struct clockdomain core_l4_3xxx_clkdm = { | ||
| 212 | .name = "core_l4_clkdm", | 728 | .name = "core_l4_clkdm", |
| 213 | .pwrdm = { .name = "core_pwrdm" }, | 729 | .pwrdm = { .name = "core_pwrdm" }, |
| 214 | .flags = CLKDM_CAN_HWSUP, | 730 | .flags = CLKDM_CAN_HWSUP, |
| 731 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 732 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | ||
| 215 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, | 733 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
| 216 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 734 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 217 | }; | 735 | }; |
| 218 | 736 | ||
| 219 | static struct clockdomain dss_34xx_clkdm = { | 737 | /* Another case of bit name collisions between several registers: EN_DSS */ |
| 738 | static struct clockdomain dss_3xxx_clkdm = { | ||
| 220 | .name = "dss_clkdm", | 739 | .name = "dss_clkdm", |
| 221 | .pwrdm = { .name = "dss_pwrdm" }, | 740 | .pwrdm = { .name = "dss_pwrdm" }, |
| 222 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 741 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 742 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, | ||
| 743 | OMAP2_CM_CLKSTCTRL), | ||
| 744 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | ||
| 745 | .wkdep_srcs = dss_wkdeps, | ||
| 746 | .sleepdep_srcs = dss_sleepdeps, | ||
| 223 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | 747 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
| 224 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 748 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 225 | }; | 749 | }; |
| @@ -228,6 +752,10 @@ static struct clockdomain cam_clkdm = { | |||
| 228 | .name = "cam_clkdm", | 752 | .name = "cam_clkdm", |
| 229 | .pwrdm = { .name = "cam_pwrdm" }, | 753 | .pwrdm = { .name = "cam_pwrdm" }, |
| 230 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 754 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 755 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, | ||
| 756 | OMAP2_CM_CLKSTCTRL), | ||
| 757 | .wkdep_srcs = cam_wkdeps, | ||
| 758 | .sleepdep_srcs = cam_sleepdeps, | ||
| 231 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, | 759 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
| 232 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 760 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 233 | }; | 761 | }; |
| @@ -236,6 +764,10 @@ static struct clockdomain usbhost_clkdm = { | |||
| 236 | .name = "usbhost_clkdm", | 764 | .name = "usbhost_clkdm", |
| 237 | .pwrdm = { .name = "usbhost_pwrdm" }, | 765 | .pwrdm = { .name = "usbhost_pwrdm" }, |
| 238 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 766 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 767 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, | ||
| 768 | OMAP2_CM_CLKSTCTRL), | ||
| 769 | .wkdep_srcs = usbhost_wkdeps, | ||
| 770 | .sleepdep_srcs = usbhost_sleepdeps, | ||
| 239 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 771 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
| 240 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 772 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 241 | }; | 773 | }; |
| @@ -244,6 +776,11 @@ static struct clockdomain per_clkdm = { | |||
| 244 | .name = "per_clkdm", | 776 | .name = "per_clkdm", |
| 245 | .pwrdm = { .name = "per_pwrdm" }, | 777 | .pwrdm = { .name = "per_pwrdm" }, |
| 246 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 778 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 779 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, | ||
| 780 | OMAP2_CM_CLKSTCTRL), | ||
| 781 | .dep_bit = OMAP3430_EN_PER_SHIFT, | ||
| 782 | .wkdep_srcs = per_wkdeps, | ||
| 783 | .sleepdep_srcs = per_sleepdeps, | ||
| 247 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | 784 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
| 248 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 785 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 249 | }; | 786 | }; |
| @@ -256,6 +793,8 @@ static struct clockdomain emu_clkdm = { | |||
| 256 | .name = "emu_clkdm", | 793 | .name = "emu_clkdm", |
| 257 | .pwrdm = { .name = "emu_pwrdm" }, | 794 | .pwrdm = { .name = "emu_pwrdm" }, |
| 258 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, | 795 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
| 796 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, | ||
| 797 | OMAP2_CM_CLKSTCTRL), | ||
| 259 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, | 798 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
| 260 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 799 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 261 | }; | 800 | }; |
| @@ -290,64 +829,70 @@ static struct clockdomain dpll5_clkdm = { | |||
| 290 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 829 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 291 | }; | 830 | }; |
| 292 | 831 | ||
| 293 | #endif /* CONFIG_ARCH_OMAP34XX */ | 832 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 833 | |||
| 834 | #include "clockdomains44xx.h" | ||
| 294 | 835 | ||
| 295 | /* | 836 | /* |
| 296 | * Clockdomain-powerdomain hwsup dependencies (34XX only) | 837 | * Clockdomain hwsup dependencies (OMAP3 only) |
| 297 | */ | 838 | */ |
| 298 | 839 | ||
| 299 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | 840 | static struct clkdm_autodep clkdm_autodeps[] = { |
| 300 | { | 841 | { |
| 301 | .pwrdm = { .name = "mpu_pwrdm" }, | 842 | .clkdm = { .name = "mpu_clkdm" }, |
| 302 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 843 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 303 | }, | 844 | }, |
| 304 | { | 845 | { |
| 305 | .pwrdm = { .name = "iva2_pwrdm" }, | 846 | .clkdm = { .name = "iva2_clkdm" }, |
| 306 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 847 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 307 | }, | 848 | }, |
| 308 | { | 849 | { |
| 309 | .pwrdm = { .name = NULL }, | 850 | .clkdm = { .name = NULL }, |
| 310 | } | 851 | } |
| 311 | }; | 852 | }; |
| 312 | 853 | ||
| 313 | /* | 854 | /* |
| 314 | * | 855 | * List of clockdomain pointers per platform |
| 315 | */ | 856 | */ |
| 316 | 857 | ||
| 317 | static struct clockdomain *clockdomains_omap[] = { | 858 | static struct clockdomain *clockdomains_omap[] = { |
| 318 | 859 | ||
| 860 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 319 | &wkup_clkdm, | 861 | &wkup_clkdm, |
| 320 | &cm_clkdm, | 862 | &cm_clkdm, |
| 321 | &prm_clkdm, | 863 | &prm_clkdm, |
| 864 | #endif | ||
| 322 | 865 | ||
| 323 | #ifdef CONFIG_ARCH_OMAP2420 | 866 | #ifdef CONFIG_ARCH_OMAP2420 |
| 324 | &mpu_2420_clkdm, | 867 | &mpu_2420_clkdm, |
| 325 | &iva1_2420_clkdm, | 868 | &iva1_2420_clkdm, |
| 869 | &dsp_2420_clkdm, | ||
| 870 | &gfx_2420_clkdm, | ||
| 871 | &core_l3_2420_clkdm, | ||
| 872 | &core_l4_2420_clkdm, | ||
| 873 | &dss_2420_clkdm, | ||
| 326 | #endif | 874 | #endif |
| 327 | 875 | ||
| 328 | #ifdef CONFIG_ARCH_OMAP2430 | 876 | #ifdef CONFIG_ARCH_OMAP2430 |
| 329 | &mpu_2430_clkdm, | 877 | &mpu_2430_clkdm, |
| 330 | &mdm_clkdm, | 878 | &mdm_clkdm, |
| 879 | &dsp_2430_clkdm, | ||
| 880 | &gfx_2430_clkdm, | ||
| 881 | &core_l3_2430_clkdm, | ||
| 882 | &core_l4_2430_clkdm, | ||
| 883 | &dss_2430_clkdm, | ||
| 331 | #endif | 884 | #endif |
| 332 | 885 | ||
| 333 | #ifdef CONFIG_ARCH_OMAP24XX | 886 | #ifdef CONFIG_ARCH_OMAP3 |
| 334 | &dsp_clkdm, | 887 | &mpu_3xxx_clkdm, |
| 335 | &gfx_24xx_clkdm, | ||
| 336 | &core_l3_24xx_clkdm, | ||
| 337 | &core_l4_24xx_clkdm, | ||
| 338 | &dss_24xx_clkdm, | ||
| 339 | #endif | ||
| 340 | |||
| 341 | #ifdef CONFIG_ARCH_OMAP34XX | ||
| 342 | &mpu_34xx_clkdm, | ||
| 343 | &neon_clkdm, | 888 | &neon_clkdm, |
| 344 | &iva2_clkdm, | 889 | &iva2_clkdm, |
| 345 | &gfx_3430es1_clkdm, | 890 | &gfx_3430es1_clkdm, |
| 346 | &sgx_clkdm, | 891 | &sgx_clkdm, |
| 347 | &d2d_clkdm, | 892 | &d2d_clkdm, |
| 348 | &core_l3_34xx_clkdm, | 893 | &core_l3_3xxx_clkdm, |
| 349 | &core_l4_34xx_clkdm, | 894 | &core_l4_3xxx_clkdm, |
| 350 | &dss_34xx_clkdm, | 895 | &dss_3xxx_clkdm, |
| 351 | &cam_clkdm, | 896 | &cam_clkdm, |
| 352 | &usbhost_clkdm, | 897 | &usbhost_clkdm, |
| 353 | &per_clkdm, | 898 | &per_clkdm, |
| @@ -359,6 +904,33 @@ static struct clockdomain *clockdomains_omap[] = { | |||
| 359 | &dpll5_clkdm, | 904 | &dpll5_clkdm, |
| 360 | #endif | 905 | #endif |
| 361 | 906 | ||
| 907 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 908 | &l4_cefuse_44xx_clkdm, | ||
| 909 | &l4_cfg_44xx_clkdm, | ||
| 910 | &tesla_44xx_clkdm, | ||
| 911 | &l3_gfx_44xx_clkdm, | ||
| 912 | &ivahd_44xx_clkdm, | ||
| 913 | &l4_secure_44xx_clkdm, | ||
| 914 | &l4_per_44xx_clkdm, | ||
| 915 | &abe_44xx_clkdm, | ||
| 916 | &l3_instr_44xx_clkdm, | ||
| 917 | &l3_init_44xx_clkdm, | ||
| 918 | &mpuss_44xx_clkdm, | ||
| 919 | &mpu0_44xx_clkdm, | ||
| 920 | &mpu1_44xx_clkdm, | ||
| 921 | &l3_emif_44xx_clkdm, | ||
| 922 | &l4_ao_44xx_clkdm, | ||
| 923 | &ducati_44xx_clkdm, | ||
| 924 | &l3_2_44xx_clkdm, | ||
| 925 | &l3_1_44xx_clkdm, | ||
| 926 | &l3_d2d_44xx_clkdm, | ||
| 927 | &iss_44xx_clkdm, | ||
| 928 | &l3_dss_44xx_clkdm, | ||
| 929 | &l4_wkup_44xx_clkdm, | ||
| 930 | &emu_sys_44xx_clkdm, | ||
| 931 | &l3_dma_44xx_clkdm, | ||
| 932 | #endif | ||
| 933 | |||
| 362 | NULL, | 934 | NULL, |
| 363 | }; | 935 | }; |
| 364 | 936 | ||
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h new file mode 100644 index 000000000000..438aaee2e392 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains44xx.h | |||
| @@ -0,0 +1,250 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Clock domains framework | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2009 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Abhijit Pagare (abhijitpagare@ti.com) | ||
| 8 | * Benoit Cousson (b-cousson@ti.com) | ||
| 9 | * | ||
| 10 | * This file is automatically generated from the OMAP hardware databases. | ||
| 11 | * We respectfully ask that any modifications to this file be coordinated | ||
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 13 | * authors above to ensure that the autogeneration scripts are kept | ||
| 14 | * up-to-date with the file contents. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * To-Do List | ||
| 23 | * -> Populate the Sleep/Wakeup dependencies for the domains | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H | ||
| 27 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H | ||
| 28 | |||
| 29 | #include <plat/clockdomain.h> | ||
| 30 | |||
| 31 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 32 | |||
| 33 | static struct clockdomain l4_cefuse_44xx_clkdm = { | ||
| 34 | .name = "l4_cefuse_clkdm", | ||
| 35 | .pwrdm = { .name = "cefuse_pwrdm" }, | ||
| 36 | .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL, | ||
| 37 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 38 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 39 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct clockdomain l4_cfg_44xx_clkdm = { | ||
| 43 | .name = "l4_cfg_clkdm", | ||
| 44 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 45 | .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL, | ||
| 46 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 47 | .flags = CLKDM_CAN_HWSUP, | ||
| 48 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct clockdomain tesla_44xx_clkdm = { | ||
| 52 | .name = "tesla_clkdm", | ||
| 53 | .pwrdm = { .name = "tesla_pwrdm" }, | ||
| 54 | .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL, | ||
| 55 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 56 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 57 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct clockdomain l3_gfx_44xx_clkdm = { | ||
| 61 | .name = "l3_gfx_clkdm", | ||
| 62 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
| 63 | .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL, | ||
| 64 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 65 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 66 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 67 | }; | ||
| 68 | |||
| 69 | static struct clockdomain ivahd_44xx_clkdm = { | ||
| 70 | .name = "ivahd_clkdm", | ||
| 71 | .pwrdm = { .name = "ivahd_pwrdm" }, | ||
| 72 | .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL, | ||
| 73 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 74 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 75 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct clockdomain l4_secure_44xx_clkdm = { | ||
| 79 | .name = "l4_secure_clkdm", | ||
| 80 | .pwrdm = { .name = "l4per_pwrdm" }, | ||
| 81 | .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL, | ||
| 82 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 83 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 84 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 85 | }; | ||
| 86 | |||
| 87 | static struct clockdomain l4_per_44xx_clkdm = { | ||
| 88 | .name = "l4_per_clkdm", | ||
| 89 | .pwrdm = { .name = "l4per_pwrdm" }, | ||
| 90 | .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL, | ||
| 91 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 92 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 93 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct clockdomain abe_44xx_clkdm = { | ||
| 97 | .name = "abe_clkdm", | ||
| 98 | .pwrdm = { .name = "abe_pwrdm" }, | ||
| 99 | .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL, | ||
| 100 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 101 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct clockdomain l3_instr_44xx_clkdm = { | ||
| 106 | .name = "l3_instr_clkdm", | ||
| 107 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 108 | .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL, | ||
| 109 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 110 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct clockdomain l3_init_44xx_clkdm = { | ||
| 114 | .name = "l3_init_clkdm", | ||
| 115 | .pwrdm = { .name = "l3init_pwrdm" }, | ||
| 116 | .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL, | ||
| 117 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 118 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 120 | }; | ||
| 121 | |||
| 122 | static struct clockdomain mpuss_44xx_clkdm = { | ||
| 123 | .name = "mpuss_clkdm", | ||
| 124 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
| 125 | .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL, | ||
| 126 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 127 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct clockdomain mpu0_44xx_clkdm = { | ||
| 132 | .name = "mpu0_clkdm", | ||
| 133 | .pwrdm = { .name = "cpu0_pwrdm" }, | ||
| 134 | .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL, | ||
| 135 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 136 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 138 | }; | ||
| 139 | |||
| 140 | static struct clockdomain mpu1_44xx_clkdm = { | ||
| 141 | .name = "mpu1_clkdm", | ||
| 142 | .pwrdm = { .name = "cpu1_pwrdm" }, | ||
| 143 | .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL, | ||
| 144 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 145 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 146 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct clockdomain l3_emif_44xx_clkdm = { | ||
| 150 | .name = "l3_emif_clkdm", | ||
| 151 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 152 | .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL, | ||
| 153 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 154 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 155 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 156 | }; | ||
| 157 | |||
| 158 | static struct clockdomain l4_ao_44xx_clkdm = { | ||
| 159 | .name = "l4_ao_clkdm", | ||
| 160 | .pwrdm = { .name = "always_on_core_pwrdm" }, | ||
| 161 | .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL, | ||
| 162 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 163 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 164 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 165 | }; | ||
| 166 | |||
| 167 | static struct clockdomain ducati_44xx_clkdm = { | ||
| 168 | .name = "ducati_clkdm", | ||
| 169 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 170 | .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL, | ||
| 171 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 172 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 173 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct clockdomain l3_2_44xx_clkdm = { | ||
| 177 | .name = "l3_2_clkdm", | ||
| 178 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 179 | .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL, | ||
| 180 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 181 | .flags = CLKDM_CAN_HWSUP, | ||
| 182 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 183 | }; | ||
| 184 | |||
| 185 | static struct clockdomain l3_1_44xx_clkdm = { | ||
| 186 | .name = "l3_1_clkdm", | ||
| 187 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 188 | .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL, | ||
| 189 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 190 | .flags = CLKDM_CAN_HWSUP, | ||
| 191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct clockdomain l3_d2d_44xx_clkdm = { | ||
| 195 | .name = "l3_d2d_clkdm", | ||
| 196 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 197 | .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL, | ||
| 198 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 199 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 201 | }; | ||
| 202 | |||
| 203 | static struct clockdomain iss_44xx_clkdm = { | ||
| 204 | .name = "iss_clkdm", | ||
| 205 | .pwrdm = { .name = "cam_pwrdm" }, | ||
| 206 | .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL, | ||
| 207 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 208 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 209 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct clockdomain l3_dss_44xx_clkdm = { | ||
| 213 | .name = "l3_dss_clkdm", | ||
| 214 | .pwrdm = { .name = "dss_pwrdm" }, | ||
| 215 | .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL, | ||
| 216 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 217 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 218 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 219 | }; | ||
| 220 | |||
| 221 | static struct clockdomain l4_wkup_44xx_clkdm = { | ||
| 222 | .name = "l4_wkup_clkdm", | ||
| 223 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 224 | .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL, | ||
| 225 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 226 | .flags = CLKDM_CAN_HWSUP, | ||
| 227 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 228 | }; | ||
| 229 | |||
| 230 | static struct clockdomain emu_sys_44xx_clkdm = { | ||
| 231 | .name = "emu_sys_clkdm", | ||
| 232 | .pwrdm = { .name = "emu_pwrdm" }, | ||
| 233 | .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL, | ||
| 234 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 235 | .flags = CLKDM_CAN_HWSUP, | ||
| 236 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct clockdomain l3_dma_44xx_clkdm = { | ||
| 240 | .name = "l3_dma_clkdm", | ||
| 241 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 242 | .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL, | ||
| 243 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | ||
| 244 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
| 245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 246 | }; | ||
| 247 | |||
| 248 | #endif | ||
| 249 | |||
| 250 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 6923deb98a28..a3a3ca07e383 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -55,7 +55,7 @@ | |||
| 55 | /* Bits specific to each register */ | 55 | /* Bits specific to each register */ |
| 56 | 56 | ||
| 57 | /* CM_FCLKEN_IVA2 */ | 57 | /* CM_FCLKEN_IVA2 */ |
| 58 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) | 58 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
| 59 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 | 59 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
| 60 | 60 | ||
| 61 | /* CM_CLKEN_PLL_IVA2 */ | 61 | /* CM_CLKEN_PLL_IVA2 */ |
| @@ -168,6 +168,12 @@ | |||
| 168 | #define OMAP3430_EN_SDRC (1 << 1) | 168 | #define OMAP3430_EN_SDRC (1 << 1) |
| 169 | #define OMAP3430_EN_SDRC_SHIFT 1 | 169 | #define OMAP3430_EN_SDRC_SHIFT 1 |
| 170 | 170 | ||
| 171 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | ||
| 172 | #define AM35XX_EN_IPSS_MASK (1 << 4) | ||
| 173 | #define AM35XX_EN_IPSS_SHIFT 4 | ||
| 174 | #define AM35XX_EN_UART4_MASK (1 << 23) | ||
| 175 | #define AM35XX_EN_UART4_SHIFT 23 | ||
| 176 | |||
| 171 | /* CM_ICLKEN2_CORE */ | 177 | /* CM_ICLKEN2_CORE */ |
| 172 | #define OMAP3430_EN_PKA (1 << 4) | 178 | #define OMAP3430_EN_PKA (1 << 4) |
| 173 | #define OMAP3430_EN_PKA_SHIFT 4 | 179 | #define OMAP3430_EN_PKA_SHIFT 4 |
| @@ -220,6 +226,10 @@ | |||
| 220 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | 226 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 |
| 221 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | 227 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) |
| 222 | 228 | ||
| 229 | /* AM35xx specific CM_IDLEST1_CORE bits */ | ||
| 230 | #define AM35XX_ST_IPSS_SHIFT 5 | ||
| 231 | #define AM35XX_ST_IPSS_MASK (1 << 5) | ||
| 232 | |||
| 223 | /* CM_IDLEST2_CORE */ | 233 | /* CM_IDLEST2_CORE */ |
| 224 | #define OMAP3430_ST_PKA_SHIFT 4 | 234 | #define OMAP3430_ST_PKA_SHIFT 4 |
| 225 | #define OMAP3430_ST_PKA_MASK (1 << 4) | 235 | #define OMAP3430_ST_PKA_MASK (1 << 4) |
| @@ -336,6 +346,8 @@ | |||
| 336 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | 346 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) |
| 337 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | 347 | #define OMAP3430_CLKSEL_L3_SHIFT 0 |
| 338 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | 348 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) |
| 349 | #define OMAP3630_CLKSEL_96M_SHIFT 12 | ||
| 350 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | ||
| 339 | 351 | ||
| 340 | /* CM_CLKSTCTRL_CORE */ | 352 | /* CM_CLKSTCTRL_CORE */ |
| 341 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | 353 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 |
| @@ -379,6 +391,10 @@ | |||
| 379 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 | 391 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 380 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | 392 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) |
| 381 | 393 | ||
| 394 | /* CM_IDLEST_SGX */ | ||
| 395 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | ||
| 396 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | ||
| 397 | |||
| 382 | /* CM_ICLKEN_SGX */ | 398 | /* CM_ICLKEN_SGX */ |
| 383 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | 399 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 |
| 384 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | 400 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) |
| @@ -517,12 +533,18 @@ | |||
| 517 | /* CM_CLKSEL2_PLL */ | 533 | /* CM_CLKSEL2_PLL */ |
| 518 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | 534 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 |
| 519 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | 535 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) |
| 536 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) | ||
| 520 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | 537 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 |
| 521 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | 538 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) |
| 539 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 | ||
| 540 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | ||
| 541 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | ||
| 542 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | ||
| 522 | 543 | ||
| 523 | /* CM_CLKSEL3_PLL */ | 544 | /* CM_CLKSEL3_PLL */ |
| 524 | #define OMAP3430_DIV_96M_SHIFT 0 | 545 | #define OMAP3430_DIV_96M_SHIFT 0 |
| 525 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | 546 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) |
| 547 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | ||
| 526 | 548 | ||
| 527 | /* CM_CLKSEL4_PLL */ | 549 | /* CM_CLKSEL4_PLL */ |
| 528 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | 550 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 |
| @@ -569,8 +591,10 @@ | |||
| 569 | /* CM_CLKSEL_DSS */ | 591 | /* CM_CLKSEL_DSS */ |
| 570 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 592 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
| 571 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | 593 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) |
| 594 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | ||
| 572 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 595 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
| 573 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | 596 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) |
| 597 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | ||
| 574 | 598 | ||
| 575 | /* CM_SLEEPDEP_DSS specific bits */ | 599 | /* CM_SLEEPDEP_DSS specific bits */ |
| 576 | 600 | ||
| @@ -598,6 +622,7 @@ | |||
| 598 | /* CM_CLKSEL_CAM */ | 622 | /* CM_CLKSEL_CAM */ |
| 599 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 623 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
| 600 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | 624 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) |
| 625 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | ||
| 601 | 626 | ||
| 602 | /* CM_SLEEPDEP_CAM specific bits */ | 627 | /* CM_SLEEPDEP_CAM specific bits */ |
| 603 | 628 | ||
| @@ -693,6 +718,7 @@ | |||
| 693 | /* CM_CLKSEL1_EMU */ | 718 | /* CM_CLKSEL1_EMU */ |
| 694 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 719 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
| 695 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | 720 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) |
| 721 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | ||
| 696 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 722 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
| 697 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | 723 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) |
| 698 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 724 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 0e67f75aa35c..ac8458e43252 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | 27 | ||
| 28 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | 28 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
| 29 | #define OMAP4430_ABE_DYNDEP_SHIFT (1 << 3) | 29 | #define OMAP4430_ABE_DYNDEP_SHIFT 3 |
| 30 | #define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) | 30 | #define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) |
| 31 | 31 | ||
| 32 | /* | 32 | /* |
| @@ -34,15 +34,15 @@ | |||
| 34 | * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, | 34 | * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, |
| 35 | * CM_TESLA_STATICDEP | 35 | * CM_TESLA_STATICDEP |
| 36 | */ | 36 | */ |
| 37 | #define OMAP4430_ABE_STATDEP_SHIFT (1 << 3) | 37 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
| 38 | #define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) | 38 | #define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) |
| 39 | 39 | ||
| 40 | /* Used by CM_L4CFG_DYNAMICDEP */ | 40 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 41 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT (1 << 16) | 41 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 |
| 42 | #define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) | 42 | #define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) |
| 43 | 43 | ||
| 44 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | 44 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ |
| 45 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT (1 << 16) | 45 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 |
| 46 | #define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) | 46 | #define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) |
| 47 | 47 | ||
| 48 | /* | 48 | /* |
| @@ -50,371 +50,371 @@ | |||
| 50 | * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, | 50 | * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, |
| 51 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU | 51 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU |
| 52 | */ | 52 | */ |
| 53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT (1 << 0) | 53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 |
| 54 | #define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) | 54 | #define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) |
| 55 | 55 | ||
| 56 | /* Used by CM_L4CFG_DYNAMICDEP */ | 56 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 57 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT (1 << 17) | 57 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 |
| 58 | #define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) | 58 | #define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) |
| 59 | 59 | ||
| 60 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | 60 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ |
| 61 | #define OMAP4430_CEFUSE_STATDEP_SHIFT (1 << 17) | 61 | #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 |
| 62 | #define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) | 62 | #define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) |
| 63 | 63 | ||
| 64 | /* Used by CM1_ABE_CLKSTCTRL */ | 64 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 65 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT (1 << 13) | 65 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 |
| 66 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) | 66 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) |
| 67 | 67 | ||
| 68 | /* Used by CM1_ABE_CLKSTCTRL */ | 68 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 69 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT (1 << 12) | 69 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 |
| 70 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) | 70 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) |
| 71 | 71 | ||
| 72 | /* Used by CM_WKUP_CLKSTCTRL */ | 72 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 73 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT (1 << 9) | 73 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 |
| 74 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) | 74 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) |
| 75 | 75 | ||
| 76 | /* Used by CM1_ABE_CLKSTCTRL */ | 76 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 77 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT (1 << 11) | 77 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 |
| 78 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) | 78 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) |
| 79 | 79 | ||
| 80 | /* Used by CM1_ABE_CLKSTCTRL */ | 80 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 81 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT (1 << 8) | 81 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 |
| 82 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) | 82 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) |
| 83 | 83 | ||
| 84 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | 84 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ |
| 85 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT (1 << 11) | 85 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 |
| 86 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) | 86 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) |
| 87 | 87 | ||
| 88 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | 88 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ |
| 89 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT (1 << 12) | 89 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 |
| 90 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) | 90 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) |
| 91 | 91 | ||
| 92 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | 92 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ |
| 93 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT (1 << 13) | 93 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 |
| 94 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) | 94 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) |
| 95 | 95 | ||
| 96 | /* Used by CM_CAM_CLKSTCTRL */ | 96 | /* Used by CM_CAM_CLKSTCTRL */ |
| 97 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT (1 << 9) | 97 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 |
| 98 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) | 98 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) |
| 99 | 99 | ||
| 100 | /* Used by CM_EMU_CLKSTCTRL */ | 100 | /* Used by CM_EMU_CLKSTCTRL */ |
| 101 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT (1 << 9) | 101 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 |
| 102 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) | 102 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) |
| 103 | 103 | ||
| 104 | /* Used by CM_CEFUSE_CLKSTCTRL */ | 104 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| 105 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT (1 << 9) | 105 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 |
| 106 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) | 106 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) |
| 107 | 107 | ||
| 108 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | 108 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ |
| 109 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT (1 << 9) | 109 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 |
| 110 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) | 110 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) |
| 111 | 111 | ||
| 112 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 112 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 113 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT (1 << 9) | 113 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 |
| 114 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) | 114 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) |
| 115 | 115 | ||
| 116 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 116 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 117 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT (1 << 10) | 117 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 |
| 118 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) | 118 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) |
| 119 | 119 | ||
| 120 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 120 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 121 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT (1 << 11) | 121 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 |
| 122 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) | 122 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) |
| 123 | 123 | ||
| 124 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 124 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 125 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT (1 << 12) | 125 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 |
| 126 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) | 126 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) |
| 127 | 127 | ||
| 128 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 128 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 129 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT (1 << 13) | 129 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 |
| 130 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) | 130 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) |
| 131 | 131 | ||
| 132 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 132 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 133 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT (1 << 14) | 133 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 |
| 134 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) | 134 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) |
| 135 | 135 | ||
| 136 | /* Used by CM_DSS_CLKSTCTRL */ | 136 | /* Used by CM_DSS_CLKSTCTRL */ |
| 137 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT (1 << 10) | 137 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 |
| 138 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) | 138 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) |
| 139 | 139 | ||
| 140 | /* Used by CM_DSS_CLKSTCTRL */ | 140 | /* Used by CM_DSS_CLKSTCTRL */ |
| 141 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT (1 << 9) | 141 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 |
| 142 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) | 142 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) |
| 143 | 143 | ||
| 144 | /* Used by CM_DUCATI_CLKSTCTRL */ | 144 | /* Used by CM_DUCATI_CLKSTCTRL */ |
| 145 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT (1 << 8) | 145 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 |
| 146 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) | 146 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) |
| 147 | 147 | ||
| 148 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 148 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 149 | #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT (1 << 10) | 149 | #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 |
| 150 | #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) | 150 | #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) |
| 151 | 151 | ||
| 152 | /* Used by CM_EMU_CLKSTCTRL */ | 152 | /* Used by CM_EMU_CLKSTCTRL */ |
| 153 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT (1 << 8) | 153 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 |
| 154 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) | 154 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) |
| 155 | 155 | ||
| 156 | /* Used by CM_CAM_CLKSTCTRL */ | 156 | /* Used by CM_CAM_CLKSTCTRL */ |
| 157 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT (1 << 10) | 157 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 |
| 158 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) | 158 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) |
| 159 | 159 | ||
| 160 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 160 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 161 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT (1 << 15) | 161 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 |
| 162 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) | 162 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) |
| 163 | 163 | ||
| 164 | /* Used by CM1_ABE_CLKSTCTRL */ | 164 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 165 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT (1 << 10) | 165 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 |
| 166 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) | 166 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) |
| 167 | 167 | ||
| 168 | /* Used by CM_DSS_CLKSTCTRL */ | 168 | /* Used by CM_DSS_CLKSTCTRL */ |
| 169 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT (1 << 11) | 169 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 |
| 170 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) | 170 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) |
| 171 | 171 | ||
| 172 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 172 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 173 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT (1 << 20) | 173 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 |
| 174 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) | 174 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) |
| 175 | 175 | ||
| 176 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 176 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 177 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT (1 << 26) | 177 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 |
| 178 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) | 178 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) |
| 179 | 179 | ||
| 180 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 180 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 181 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT (1 << 21) | 181 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 |
| 182 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) | 182 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) |
| 183 | 183 | ||
| 184 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 184 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 185 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT (1 << 27) | 185 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 |
| 186 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) | 186 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) |
| 187 | 187 | ||
| 188 | /* Used by CM_L3INIT_CLKSTCTRL */ | 188 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| 189 | #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT (1 << 31) | 189 | #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 |
| 190 | #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) | 190 | #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) |
| 191 | 191 | ||
| 192 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 192 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 193 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT (1 << 13) | 193 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 |
| 194 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) | 194 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) |
| 195 | 195 | ||
| 196 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 196 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 197 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT (1 << 12) | 197 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 |
| 198 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) | 198 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) |
| 199 | 199 | ||
| 200 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 200 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 201 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT (1 << 28) | 201 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 |
| 202 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) | 202 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) |
| 203 | 203 | ||
| 204 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 204 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 205 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT (1 << 29) | 205 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 |
| 206 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) | 206 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) |
| 207 | 207 | ||
| 208 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 208 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 209 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT (1 << 11) | 209 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 |
| 210 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) | 210 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) |
| 211 | 211 | ||
| 212 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 212 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 213 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT (1 << 16) | 213 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 |
| 214 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) | 214 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) |
| 215 | 215 | ||
| 216 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 216 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 217 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT (1 << 17) | 217 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 |
| 218 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) | 218 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) |
| 219 | 219 | ||
| 220 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 220 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 221 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT (1 << 18) | 221 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 |
| 222 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) | 222 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) |
| 223 | 223 | ||
| 224 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 224 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 225 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT (1 << 19) | 225 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 |
| 226 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) | 226 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) |
| 227 | 227 | ||
| 228 | /* Used by CM_CAM_CLKSTCTRL */ | 228 | /* Used by CM_CAM_CLKSTCTRL */ |
| 229 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT (1 << 8) | 229 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 |
| 230 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) | 230 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) |
| 231 | 231 | ||
| 232 | /* Used by CM_IVAHD_CLKSTCTRL */ | 232 | /* Used by CM_IVAHD_CLKSTCTRL */ |
| 233 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT (1 << 8) | 233 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 |
| 234 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) | 234 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) |
| 235 | 235 | ||
| 236 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 236 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 237 | #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT (1 << 14) | 237 | #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 |
| 238 | #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) | 238 | #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) |
| 239 | 239 | ||
| 240 | /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ | 240 | /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ |
| 241 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT (1 << 8) | 241 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 |
| 242 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) | 242 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) |
| 243 | 243 | ||
| 244 | /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ | 244 | /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ |
| 245 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT (1 << 8) | 245 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 |
| 246 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) | 246 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) |
| 247 | 247 | ||
| 248 | /* Used by CM_D2D_CLKSTCTRL */ | 248 | /* Used by CM_D2D_CLKSTCTRL */ |
| 249 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT (1 << 8) | 249 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 |
| 250 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) | 250 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) |
| 251 | 251 | ||
| 252 | /* Used by CM_SDMA_CLKSTCTRL */ | 252 | /* Used by CM_SDMA_CLKSTCTRL */ |
| 253 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT (1 << 8) | 253 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 |
| 254 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) | 254 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) |
| 255 | 255 | ||
| 256 | /* Used by CM_DSS_CLKSTCTRL */ | 256 | /* Used by CM_DSS_CLKSTCTRL */ |
| 257 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT (1 << 8) | 257 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 |
| 258 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) | 258 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) |
| 259 | 259 | ||
| 260 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | 260 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ |
| 261 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT (1 << 8) | 261 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 |
| 262 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) | 262 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) |
| 263 | 263 | ||
| 264 | /* Used by CM_GFX_CLKSTCTRL */ | 264 | /* Used by CM_GFX_CLKSTCTRL */ |
| 265 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT (1 << 8) | 265 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 |
| 266 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) | 266 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) |
| 267 | 267 | ||
| 268 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 268 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 269 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT (1 << 8) | 269 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 |
| 270 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) | 270 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) |
| 271 | 271 | ||
| 272 | /* Used by CM_L3INSTR_CLKSTCTRL */ | 272 | /* Used by CM_L3INSTR_CLKSTCTRL */ |
| 273 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT (1 << 8) | 273 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 |
| 274 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) | 274 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) |
| 275 | 275 | ||
| 276 | /* Used by CM_L4SEC_CLKSTCTRL */ | 276 | /* Used by CM_L4SEC_CLKSTCTRL */ |
| 277 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT (1 << 8) | 277 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 |
| 278 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) | 278 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) |
| 279 | 279 | ||
| 280 | /* Used by CM_ALWON_CLKSTCTRL */ | 280 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 281 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT (1 << 8) | 281 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 |
| 282 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) | 282 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) |
| 283 | 283 | ||
| 284 | /* Used by CM_CEFUSE_CLKSTCTRL */ | 284 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| 285 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT (1 << 8) | 285 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 |
| 286 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) | 286 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) |
| 287 | 287 | ||
| 288 | /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ | 288 | /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ |
| 289 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT (1 << 8) | 289 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 |
| 290 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) | 290 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) |
| 291 | 291 | ||
| 292 | /* Used by CM_D2D_CLKSTCTRL */ | 292 | /* Used by CM_D2D_CLKSTCTRL */ |
| 293 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT (1 << 9) | 293 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 |
| 294 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) | 294 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) |
| 295 | 295 | ||
| 296 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 296 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 297 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT (1 << 9) | 297 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 |
| 298 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) | 298 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) |
| 299 | 299 | ||
| 300 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 300 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 301 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT (1 << 8) | 301 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 |
| 302 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) | 302 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) |
| 303 | 303 | ||
| 304 | /* Used by CM_L4SEC_CLKSTCTRL */ | 304 | /* Used by CM_L4SEC_CLKSTCTRL */ |
| 305 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT (1 << 9) | 305 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 |
| 306 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) | 306 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) |
| 307 | 307 | ||
| 308 | /* Used by CM_WKUP_CLKSTCTRL */ | 308 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 309 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT (1 << 12) | 309 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 |
| 310 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) | 310 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) |
| 311 | 311 | ||
| 312 | /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ | 312 | /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ |
| 313 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT (1 << 8) | 313 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 |
| 314 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) | 314 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) |
| 315 | 315 | ||
| 316 | /* Used by CM1_ABE_CLKSTCTRL */ | 316 | /* Used by CM1_ABE_CLKSTCTRL */ |
| 317 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT (1 << 9) | 317 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 |
| 318 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) | 318 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) |
| 319 | 319 | ||
| 320 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 320 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 321 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT (1 << 16) | 321 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 |
| 322 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) | 322 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) |
| 323 | 323 | ||
| 324 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 324 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 325 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT (1 << 17) | 325 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 |
| 326 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) | 326 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) |
| 327 | 327 | ||
| 328 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 328 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 329 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT (1 << 18) | 329 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 |
| 330 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) | 330 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) |
| 331 | 331 | ||
| 332 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 332 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 333 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT (1 << 19) | 333 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 |
| 334 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) | 334 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) |
| 335 | 335 | ||
| 336 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 336 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 337 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT (1 << 25) | 337 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 |
| 338 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) | 338 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) |
| 339 | 339 | ||
| 340 | /* Used by CM_EMU_CLKSTCTRL */ | 340 | /* Used by CM_EMU_CLKSTCTRL */ |
| 341 | #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT (1 << 10) | 341 | #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 |
| 342 | #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) | 342 | #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) |
| 343 | 343 | ||
| 344 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 344 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 345 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT (1 << 20) | 345 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 |
| 346 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) | 346 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) |
| 347 | 347 | ||
| 348 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 348 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 349 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT (1 << 21) | 349 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 |
| 350 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) | 350 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) |
| 351 | 351 | ||
| 352 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 352 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 353 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT (1 << 22) | 353 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 |
| 354 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) | 354 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) |
| 355 | 355 | ||
| 356 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ | 356 | /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ |
| 357 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT (1 << 24) | 357 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 |
| 358 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) | 358 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) |
| 359 | 359 | ||
| 360 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ | 360 | /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ |
| 361 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT (1 << 10) | 361 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 |
| 362 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) | 362 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) |
| 363 | 363 | ||
| 364 | /* Used by CM_GFX_CLKSTCTRL */ | 364 | /* Used by CM_GFX_CLKSTCTRL */ |
| 365 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT (1 << 9) | 365 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 |
| 366 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) | 366 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) |
| 367 | 367 | ||
| 368 | /* Used by CM_ALWON_CLKSTCTRL */ | 368 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 369 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT (1 << 11) | 369 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 |
| 370 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) | 370 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) |
| 371 | 371 | ||
| 372 | /* Used by CM_ALWON_CLKSTCTRL */ | 372 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 373 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT (1 << 10) | 373 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 |
| 374 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) | 374 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) |
| 375 | 375 | ||
| 376 | /* Used by CM_ALWON_CLKSTCTRL */ | 376 | /* Used by CM_ALWON_CLKSTCTRL */ |
| 377 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT (1 << 9) | 377 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 |
| 378 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) | 378 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) |
| 379 | 379 | ||
| 380 | /* Used by CM_WKUP_CLKSTCTRL */ | 380 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 381 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT (1 << 8) | 381 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 |
| 382 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) | 382 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) |
| 383 | 383 | ||
| 384 | /* Used by CM_TESLA_CLKSTCTRL */ | 384 | /* Used by CM_TESLA_CLKSTCTRL */ |
| 385 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT (1 << 8) | 385 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 |
| 386 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) | 386 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) |
| 387 | 387 | ||
| 388 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 388 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 389 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT (1 << 22) | 389 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 |
| 390 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) | 390 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) |
| 391 | 391 | ||
| 392 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 392 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 393 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT (1 << 23) | 393 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 |
| 394 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) | 394 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) |
| 395 | 395 | ||
| 396 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 396 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 397 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT (1 << 24) | 397 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 |
| 398 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) | 398 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) |
| 399 | 399 | ||
| 400 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 400 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 401 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT (1 << 15) | 401 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 |
| 402 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) | 402 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) |
| 403 | 403 | ||
| 404 | /* Used by CM_WKUP_CLKSTCTRL */ | 404 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 405 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT (1 << 10) | 405 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 |
| 406 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) | 406 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) |
| 407 | 407 | ||
| 408 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 408 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 409 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT (1 << 30) | 409 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 |
| 410 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) | 410 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) |
| 411 | 411 | ||
| 412 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ | 412 | /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ |
| 413 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT (1 << 25) | 413 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 |
| 414 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) | 414 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) |
| 415 | 415 | ||
| 416 | /* Used by CM_WKUP_CLKSTCTRL */ | 416 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 417 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT (1 << 11) | 417 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 |
| 418 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) | 418 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) |
| 419 | 419 | ||
| 420 | /* | 420 | /* |
| @@ -426,7 +426,7 @@ | |||
| 426 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | 426 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, |
| 427 | * CM1_ABE_TIMER8_CLKCTRL | 427 | * CM1_ABE_TIMER8_CLKCTRL |
| 428 | */ | 428 | */ |
| 429 | #define OMAP4430_CLKSEL_SHIFT (1 << 24) | 429 | #define OMAP4430_CLKSEL_SHIFT 24 |
| 430 | #define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) | 430 | #define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) |
| 431 | 431 | ||
| 432 | /* | 432 | /* |
| @@ -434,43 +434,43 @@ | |||
| 434 | * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, | 434 | * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, |
| 435 | * CM_CLKSEL_USB_60MHZ | 435 | * CM_CLKSEL_USB_60MHZ |
| 436 | */ | 436 | */ |
| 437 | #define OMAP4430_CLKSEL_0_0_SHIFT (1 << 0) | 437 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
| 438 | #define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) | 438 | #define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) |
| 439 | 439 | ||
| 440 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ | 440 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ |
| 441 | #define OMAP4430_CLKSEL_0_1_SHIFT (1 << 0) | 441 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
| 442 | #define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) | 442 | #define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) |
| 443 | 443 | ||
| 444 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ | 444 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ |
| 445 | #define OMAP4430_CLKSEL_24_25_SHIFT (1 << 24) | 445 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
| 446 | #define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) | 446 | #define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) |
| 447 | 447 | ||
| 448 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | 448 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ |
| 449 | #define OMAP4430_CLKSEL_60M_SHIFT (1 << 24) | 449 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
| 450 | #define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) | 450 | #define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) |
| 451 | 451 | ||
| 452 | /* Used by CM1_ABE_AESS_CLKCTRL */ | 452 | /* Used by CM1_ABE_AESS_CLKCTRL */ |
| 453 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT (1 << 24) | 453 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
| 454 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) | 454 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) |
| 455 | 455 | ||
| 456 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ | 456 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ |
| 457 | #define OMAP4430_CLKSEL_CORE_SHIFT (1 << 0) | 457 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
| 458 | #define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) | 458 | #define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) |
| 459 | 459 | ||
| 460 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ | 460 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 461 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT (1 << 1) | 461 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 |
| 462 | #define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) | 462 | #define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) |
| 463 | 463 | ||
| 464 | /* Used by CM_WKUP_USIM_CLKCTRL */ | 464 | /* Used by CM_WKUP_USIM_CLKCTRL */ |
| 465 | #define OMAP4430_CLKSEL_DIV_SHIFT (1 << 24) | 465 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
| 466 | #define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) | 466 | #define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) |
| 467 | 467 | ||
| 468 | /* Used by CM_CAM_FDIF_CLKCTRL */ | 468 | /* Used by CM_CAM_FDIF_CLKCTRL */ |
| 469 | #define OMAP4430_CLKSEL_FCLK_SHIFT (1 << 24) | 469 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
| 470 | #define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) | 470 | #define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) |
| 471 | 471 | ||
| 472 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ | 472 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ |
| 473 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT (1 << 25) | 473 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
| 474 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) | 474 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) |
| 475 | 475 | ||
| 476 | /* | 476 | /* |
| @@ -478,58 +478,58 @@ | |||
| 478 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | 478 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| 479 | * CM1_ABE_MCBSP3_CLKCTRL | 479 | * CM1_ABE_MCBSP3_CLKCTRL |
| 480 | */ | 480 | */ |
| 481 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT (1 << 26) | 481 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 |
| 482 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) | 482 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) |
| 483 | 483 | ||
| 484 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ | 484 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ |
| 485 | #define OMAP4430_CLKSEL_L3_SHIFT (1 << 4) | 485 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
| 486 | #define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) | 486 | #define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) |
| 487 | 487 | ||
| 488 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ | 488 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 489 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT (1 << 2) | 489 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 |
| 490 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) | 490 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) |
| 491 | 491 | ||
| 492 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ | 492 | /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ |
| 493 | #define OMAP4430_CLKSEL_L4_SHIFT (1 << 8) | 493 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
| 494 | #define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) | 494 | #define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) |
| 495 | 495 | ||
| 496 | /* Used by CM_CLKSEL_ABE */ | 496 | /* Used by CM_CLKSEL_ABE */ |
| 497 | #define OMAP4430_CLKSEL_OPP_SHIFT (1 << 0) | 497 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
| 498 | #define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) | 498 | #define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) |
| 499 | 499 | ||
| 500 | /* Used by CM_GFX_GFX_CLKCTRL */ | 500 | /* Used by CM_GFX_GFX_CLKCTRL */ |
| 501 | #define OMAP4430_CLKSEL_PER_192M_SHIFT (1 << 25) | 501 | #define OMAP4430_CLKSEL_PER_192M_SHIFT 25 |
| 502 | #define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) | 502 | #define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) |
| 503 | 503 | ||
| 504 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | 504 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 505 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT (1 << 27) | 505 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
| 506 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) | 506 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) |
| 507 | 507 | ||
| 508 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | 508 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 509 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT (1 << 24) | 509 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 |
| 510 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) | 510 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) |
| 511 | 511 | ||
| 512 | /* Used by CM_GFX_GFX_CLKCTRL */ | 512 | /* Used by CM_GFX_GFX_CLKCTRL */ |
| 513 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT (1 << 24) | 513 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 |
| 514 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) | 514 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) |
| 515 | 515 | ||
| 516 | /* | 516 | /* |
| 517 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, | 517 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, |
| 518 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL | 518 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL |
| 519 | */ | 519 | */ |
| 520 | #define OMAP4430_CLKSEL_SOURCE_SHIFT (1 << 24) | 520 | #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 |
| 521 | #define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) | 521 | #define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) |
| 522 | 522 | ||
| 523 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ | 523 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ |
| 524 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT (1 << 24) | 524 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 |
| 525 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) | 525 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) |
| 526 | 526 | ||
| 527 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 527 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 528 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT (1 << 24) | 528 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
| 529 | #define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) | 529 | #define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) |
| 530 | 530 | ||
| 531 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 531 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 532 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT (1 << 25) | 532 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
| 533 | #define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) | 533 | #define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) |
| 534 | 534 | ||
| 535 | /* | 535 | /* |
| @@ -544,23 +544,23 @@ | |||
| 544 | * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, | 544 | * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, |
| 545 | * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE | 545 | * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE |
| 546 | */ | 546 | */ |
| 547 | #define OMAP4430_CLKTRCTRL_SHIFT (1 << 0) | 547 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
| 548 | #define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) | 548 | #define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) |
| 549 | 549 | ||
| 550 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | 550 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| 551 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT (1 << 0) | 551 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 |
| 552 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) | 552 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) |
| 553 | 553 | ||
| 554 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | 554 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| 555 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT (1 << 8) | 555 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 |
| 556 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) | 556 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) |
| 557 | 557 | ||
| 558 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | 558 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
| 559 | #define OMAP4430_D2D_DYNDEP_SHIFT (1 << 18) | 559 | #define OMAP4430_D2D_DYNDEP_SHIFT 18 |
| 560 | #define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) | 560 | #define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) |
| 561 | 561 | ||
| 562 | /* Used by CM_MPU_STATICDEP */ | 562 | /* Used by CM_MPU_STATICDEP */ |
| 563 | #define OMAP4430_D2D_STATDEP_SHIFT (1 << 18) | 563 | #define OMAP4430_D2D_STATDEP_SHIFT 18 |
| 564 | #define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) | 564 | #define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) |
| 565 | 565 | ||
| 566 | /* | 566 | /* |
| @@ -570,19 +570,19 @@ | |||
| 570 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, | 570 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, |
| 571 | * CM_SSC_DELTAMSTEP_DPLL_MPU | 571 | * CM_SSC_DELTAMSTEP_DPLL_MPU |
| 572 | */ | 572 | */ |
| 573 | #define OMAP4430_DELTAMSTEP_SHIFT (1 << 0) | 573 | #define OMAP4430_DELTAMSTEP_SHIFT 0 |
| 574 | #define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) | 574 | #define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) |
| 575 | 575 | ||
| 576 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | 576 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ |
| 577 | #define OMAP4430_DLL_OVERRIDE_SHIFT (1 << 2) | 577 | #define OMAP4430_DLL_OVERRIDE_SHIFT 2 |
| 578 | #define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) | 578 | #define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) |
| 579 | 579 | ||
| 580 | /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ | 580 | /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ |
| 581 | #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT (1 << 0) | 581 | #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 |
| 582 | #define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) | 582 | #define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) |
| 583 | 583 | ||
| 584 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | 584 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ |
| 585 | #define OMAP4430_DLL_RESET_SHIFT (1 << 3) | 585 | #define OMAP4430_DLL_RESET_SHIFT 3 |
| 586 | #define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) | 586 | #define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) |
| 587 | 587 | ||
| 588 | /* | 588 | /* |
| @@ -590,40 +590,40 @@ | |||
| 590 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, | 590 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, |
| 591 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU | 591 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU |
| 592 | */ | 592 | */ |
| 593 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT (1 << 23) | 593 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
| 594 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) | 594 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) |
| 595 | 595 | ||
| 596 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | 596 | /* Used by CM_CLKDCOLDO_DPLL_USB */ |
| 597 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT (1 << 8) | 597 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 |
| 598 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) | 598 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) |
| 599 | 599 | ||
| 600 | /* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ | 600 | /* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ |
| 601 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT (1 << 20) | 601 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 |
| 602 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) | 602 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) |
| 603 | 603 | ||
| 604 | /* | 604 | /* |
| 605 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | 605 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, |
| 606 | * CM_DIV_M3_DPLL_CORE | 606 | * CM_DIV_M3_DPLL_CORE |
| 607 | */ | 607 | */ |
| 608 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT (1 << 0) | 608 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 |
| 609 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) | 609 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) |
| 610 | 610 | ||
| 611 | /* | 611 | /* |
| 612 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | 612 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, |
| 613 | * CM_DIV_M3_DPLL_CORE | 613 | * CM_DIV_M3_DPLL_CORE |
| 614 | */ | 614 | */ |
| 615 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT (1 << 5) | 615 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 |
| 616 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) | 616 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) |
| 617 | 617 | ||
| 618 | /* | 618 | /* |
| 619 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | 619 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, |
| 620 | * CM_DIV_M3_DPLL_CORE | 620 | * CM_DIV_M3_DPLL_CORE |
| 621 | */ | 621 | */ |
| 622 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT (1 << 8) | 622 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
| 623 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) | 623 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) |
| 624 | 624 | ||
| 625 | /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ | 625 | /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ |
| 626 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT (1 << 10) | 626 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 |
| 627 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) | 627 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) |
| 628 | 628 | ||
| 629 | /* | 629 | /* |
| @@ -631,11 +631,11 @@ | |||
| 631 | * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, | 631 | * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, |
| 632 | * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU | 632 | * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU |
| 633 | */ | 633 | */ |
| 634 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT (1 << 0) | 634 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
| 635 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) | 635 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) |
| 636 | 636 | ||
| 637 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ | 637 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ |
| 638 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT (1 << 0) | 638 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 |
| 639 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) | 639 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) |
| 640 | 640 | ||
| 641 | /* | 641 | /* |
| @@ -643,11 +643,11 @@ | |||
| 643 | * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, | 643 | * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, |
| 644 | * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU | 644 | * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU |
| 645 | */ | 645 | */ |
| 646 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT (1 << 5) | 646 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 |
| 647 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) | 647 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) |
| 648 | 648 | ||
| 649 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ | 649 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ |
| 650 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT (1 << 7) | 650 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 |
| 651 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) | 651 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) |
| 652 | 652 | ||
| 653 | /* | 653 | /* |
| @@ -655,23 +655,23 @@ | |||
| 655 | * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | 655 | * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| 656 | * CM_DIV_M2_DPLL_MPU | 656 | * CM_DIV_M2_DPLL_MPU |
| 657 | */ | 657 | */ |
| 658 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT (1 << 8) | 658 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 |
| 659 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) | 659 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) |
| 660 | 660 | ||
| 661 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | 661 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ |
| 662 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT (1 << 8) | 662 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 |
| 663 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) | 663 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) |
| 664 | 664 | ||
| 665 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | 665 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ |
| 666 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT (1 << 11) | 666 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 |
| 667 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) | 667 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) |
| 668 | 668 | ||
| 669 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | 669 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 670 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT (1 << 3) | 670 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 |
| 671 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) | 671 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) |
| 672 | 672 | ||
| 673 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | 673 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ |
| 674 | #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT (1 << 1) | 674 | #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 |
| 675 | #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) | 675 | #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) |
| 676 | 676 | ||
| 677 | /* | 677 | /* |
| @@ -679,11 +679,11 @@ | |||
| 679 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, | 679 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, |
| 680 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU | 680 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU |
| 681 | */ | 681 | */ |
| 682 | #define OMAP4430_DPLL_DIV_SHIFT (1 << 0) | 682 | #define OMAP4430_DPLL_DIV_SHIFT 0 |
| 683 | #define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) | 683 | #define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) |
| 684 | 684 | ||
| 685 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ | 685 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ |
| 686 | #define OMAP4430_DPLL_DIV_0_7_SHIFT (1 << 0) | 686 | #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 |
| 687 | #define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) | 687 | #define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) |
| 688 | 688 | ||
| 689 | /* | 689 | /* |
| @@ -691,11 +691,11 @@ | |||
| 691 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 691 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 692 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 692 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 693 | */ | 693 | */ |
| 694 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT (1 << 8) | 694 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 |
| 695 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) | 695 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) |
| 696 | 696 | ||
| 697 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ | 697 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ |
| 698 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT (1 << 3) | 698 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 |
| 699 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) | 699 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) |
| 700 | 700 | ||
| 701 | /* | 701 | /* |
| @@ -703,7 +703,7 @@ | |||
| 703 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 703 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 704 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 704 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 705 | */ | 705 | */ |
| 706 | #define OMAP4430_DPLL_EN_SHIFT (1 << 0) | 706 | #define OMAP4430_DPLL_EN_SHIFT 0 |
| 707 | #define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) | 707 | #define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) |
| 708 | 708 | ||
| 709 | /* | 709 | /* |
| @@ -711,7 +711,7 @@ | |||
| 711 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 711 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 712 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 712 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 713 | */ | 713 | */ |
| 714 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT (1 << 10) | 714 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 |
| 715 | #define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) | 715 | #define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) |
| 716 | 716 | ||
| 717 | /* | 717 | /* |
| @@ -719,11 +719,11 @@ | |||
| 719 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, | 719 | * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, |
| 720 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU | 720 | * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU |
| 721 | */ | 721 | */ |
| 722 | #define OMAP4430_DPLL_MULT_SHIFT (1 << 8) | 722 | #define OMAP4430_DPLL_MULT_SHIFT 8 |
| 723 | #define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) | 723 | #define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) |
| 724 | 724 | ||
| 725 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ | 725 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ |
| 726 | #define OMAP4430_DPLL_MULT_USB_SHIFT (1 << 8) | 726 | #define OMAP4430_DPLL_MULT_USB_SHIFT 8 |
| 727 | #define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) | 727 | #define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) |
| 728 | 728 | ||
| 729 | /* | 729 | /* |
| @@ -731,11 +731,11 @@ | |||
| 731 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 731 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 732 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 732 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 733 | */ | 733 | */ |
| 734 | #define OMAP4430_DPLL_REGM4XEN_SHIFT (1 << 11) | 734 | #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 |
| 735 | #define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) | 735 | #define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) |
| 736 | 736 | ||
| 737 | /* Used by CM_CLKSEL_DPLL_USB */ | 737 | /* Used by CM_CLKSEL_DPLL_USB */ |
| 738 | #define OMAP4430_DPLL_SD_DIV_SHIFT (1 << 24) | 738 | #define OMAP4430_DPLL_SD_DIV_SHIFT 24 |
| 739 | #define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) | 739 | #define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) |
| 740 | 740 | ||
| 741 | /* | 741 | /* |
| @@ -743,7 +743,7 @@ | |||
| 743 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 743 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 744 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 744 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 745 | */ | 745 | */ |
| 746 | #define OMAP4430_DPLL_SSC_ACK_SHIFT (1 << 13) | 746 | #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 |
| 747 | #define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) | 747 | #define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) |
| 748 | 748 | ||
| 749 | /* | 749 | /* |
| @@ -751,7 +751,7 @@ | |||
| 751 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 751 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 752 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 752 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 753 | */ | 753 | */ |
| 754 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT (1 << 14) | 754 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 |
| 755 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) | 755 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) |
| 756 | 756 | ||
| 757 | /* | 757 | /* |
| @@ -759,154 +759,154 @@ | |||
| 759 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, | 759 | * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, |
| 760 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU | 760 | * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU |
| 761 | */ | 761 | */ |
| 762 | #define OMAP4430_DPLL_SSC_EN_SHIFT (1 << 12) | 762 | #define OMAP4430_DPLL_SSC_EN_SHIFT 12 |
| 763 | #define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) | 763 | #define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) |
| 764 | 764 | ||
| 765 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | 765 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| 766 | #define OMAP4430_DSS_DYNDEP_SHIFT (1 << 8) | 766 | #define OMAP4430_DSS_DYNDEP_SHIFT 8 |
| 767 | #define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) | 767 | #define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) |
| 768 | 768 | ||
| 769 | /* | 769 | /* |
| 770 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, | 770 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, |
| 771 | * CM_MPU_STATICDEP | 771 | * CM_MPU_STATICDEP |
| 772 | */ | 772 | */ |
| 773 | #define OMAP4430_DSS_STATDEP_SHIFT (1 << 8) | 773 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
| 774 | #define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) | 774 | #define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) |
| 775 | 775 | ||
| 776 | /* Used by CM_L3_2_DYNAMICDEP */ | 776 | /* Used by CM_L3_2_DYNAMICDEP */ |
| 777 | #define OMAP4430_DUCATI_DYNDEP_SHIFT (1 << 0) | 777 | #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 |
| 778 | #define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) | 778 | #define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) |
| 779 | 779 | ||
| 780 | /* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ | 780 | /* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ |
| 781 | #define OMAP4430_DUCATI_STATDEP_SHIFT (1 << 0) | 781 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
| 782 | #define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) | 782 | #define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) |
| 783 | 783 | ||
| 784 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ | 784 | /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ |
| 785 | #define OMAP4430_FREQ_UPDATE_SHIFT (1 << 0) | 785 | #define OMAP4430_FREQ_UPDATE_SHIFT 0 |
| 786 | #define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) | 786 | #define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) |
| 787 | 787 | ||
| 788 | /* Used by CM_L3_2_DYNAMICDEP */ | 788 | /* Used by CM_L3_2_DYNAMICDEP */ |
| 789 | #define OMAP4430_GFX_DYNDEP_SHIFT (1 << 10) | 789 | #define OMAP4430_GFX_DYNDEP_SHIFT 10 |
| 790 | #define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) | 790 | #define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) |
| 791 | 791 | ||
| 792 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | 792 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| 793 | #define OMAP4430_GFX_STATDEP_SHIFT (1 << 10) | 793 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
| 794 | #define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) | 794 | #define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) |
| 795 | 795 | ||
| 796 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | 796 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
| 797 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT (1 << 0) | 797 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 |
| 798 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) | 798 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) |
| 799 | 799 | ||
| 800 | /* | 800 | /* |
| 801 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | 801 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, |
| 802 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | 802 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA |
| 803 | */ | 803 | */ |
| 804 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT (1 << 0) | 804 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
| 805 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) | 805 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) |
| 806 | 806 | ||
| 807 | /* | 807 | /* |
| 808 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | 808 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, |
| 809 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | 809 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA |
| 810 | */ | 810 | */ |
| 811 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT (1 << 5) | 811 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 |
| 812 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) | 812 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) |
| 813 | 813 | ||
| 814 | /* | 814 | /* |
| 815 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | 815 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, |
| 816 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | 816 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA |
| 817 | */ | 817 | */ |
| 818 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT (1 << 8) | 818 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 |
| 819 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) | 819 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) |
| 820 | 820 | ||
| 821 | /* | 821 | /* |
| 822 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | 822 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, |
| 823 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | 823 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA |
| 824 | */ | 824 | */ |
| 825 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT (1 << 12) | 825 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 |
| 826 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) | 826 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) |
| 827 | 827 | ||
| 828 | /* | 828 | /* |
| 829 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | 829 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, |
| 830 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | 830 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA |
| 831 | */ | 831 | */ |
| 832 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT (1 << 0) | 832 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
| 833 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) | 833 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) |
| 834 | 834 | ||
| 835 | /* | 835 | /* |
| 836 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | 836 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, |
| 837 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | 837 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA |
| 838 | */ | 838 | */ |
| 839 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT (1 << 5) | 839 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 |
| 840 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) | 840 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) |
| 841 | 841 | ||
| 842 | /* | 842 | /* |
| 843 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | 843 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, |
| 844 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | 844 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA |
| 845 | */ | 845 | */ |
| 846 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT (1 << 8) | 846 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 |
| 847 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) | 847 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) |
| 848 | 848 | ||
| 849 | /* | 849 | /* |
| 850 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | 850 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, |
| 851 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | 851 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA |
| 852 | */ | 852 | */ |
| 853 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT (1 << 12) | 853 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 |
| 854 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) | 854 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) |
| 855 | 855 | ||
| 856 | /* | 856 | /* |
| 857 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | 857 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, |
| 858 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | 858 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY |
| 859 | */ | 859 | */ |
| 860 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT (1 << 0) | 860 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
| 861 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) | 861 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) |
| 862 | 862 | ||
| 863 | /* | 863 | /* |
| 864 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | 864 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, |
| 865 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | 865 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY |
| 866 | */ | 866 | */ |
| 867 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT (1 << 5) | 867 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 |
| 868 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) | 868 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) |
| 869 | 869 | ||
| 870 | /* | 870 | /* |
| 871 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | 871 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, |
| 872 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | 872 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY |
| 873 | */ | 873 | */ |
| 874 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT (1 << 8) | 874 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 |
| 875 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) | 875 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) |
| 876 | 876 | ||
| 877 | /* | 877 | /* |
| 878 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | 878 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, |
| 879 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | 879 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY |
| 880 | */ | 880 | */ |
| 881 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT (1 << 12) | 881 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 |
| 882 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) | 882 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) |
| 883 | 883 | ||
| 884 | /* | 884 | /* |
| 885 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | 885 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, |
| 886 | * CM_DIV_M7_DPLL_CORE | 886 | * CM_DIV_M7_DPLL_CORE |
| 887 | */ | 887 | */ |
| 888 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT (1 << 0) | 888 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 |
| 889 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) | 889 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) |
| 890 | 890 | ||
| 891 | /* | 891 | /* |
| 892 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | 892 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, |
| 893 | * CM_DIV_M7_DPLL_CORE | 893 | * CM_DIV_M7_DPLL_CORE |
| 894 | */ | 894 | */ |
| 895 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT (1 << 5) | 895 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 |
| 896 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) | 896 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) |
| 897 | 897 | ||
| 898 | /* | 898 | /* |
| 899 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | 899 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, |
| 900 | * CM_DIV_M7_DPLL_CORE | 900 | * CM_DIV_M7_DPLL_CORE |
| 901 | */ | 901 | */ |
| 902 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT (1 << 8) | 902 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 |
| 903 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) | 903 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) |
| 904 | 904 | ||
| 905 | /* | 905 | /* |
| 906 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | 906 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, |
| 907 | * CM_DIV_M7_DPLL_CORE | 907 | * CM_DIV_M7_DPLL_CORE |
| 908 | */ | 908 | */ |
| 909 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT (1 << 12) | 909 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 |
| 910 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) | 910 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) |
| 911 | 911 | ||
| 912 | /* | 912 | /* |
| @@ -962,22 +962,22 @@ | |||
| 962 | * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, | 962 | * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, |
| 963 | * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL | 963 | * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL |
| 964 | */ | 964 | */ |
| 965 | #define OMAP4430_IDLEST_SHIFT (1 << 16) | 965 | #define OMAP4430_IDLEST_SHIFT 16 |
| 966 | #define OMAP4430_IDLEST_MASK BITFIELD(16, 17) | 966 | #define OMAP4430_IDLEST_MASK BITFIELD(16, 17) |
| 967 | 967 | ||
| 968 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | 968 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
| 969 | #define OMAP4430_ISS_DYNDEP_SHIFT (1 << 9) | 969 | #define OMAP4430_ISS_DYNDEP_SHIFT 9 |
| 970 | #define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) | 970 | #define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) |
| 971 | 971 | ||
| 972 | /* | 972 | /* |
| 973 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, | 973 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, |
| 974 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 974 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 975 | */ | 975 | */ |
| 976 | #define OMAP4430_ISS_STATDEP_SHIFT (1 << 9) | 976 | #define OMAP4430_ISS_STATDEP_SHIFT 9 |
| 977 | #define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) | 977 | #define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) |
| 978 | 978 | ||
| 979 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | 979 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
| 980 | #define OMAP4430_IVAHD_DYNDEP_SHIFT (1 << 2) | 980 | #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 |
| 981 | #define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) | 981 | #define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) |
| 982 | 982 | ||
| 983 | /* | 983 | /* |
| @@ -986,25 +986,25 @@ | |||
| 986 | * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, | 986 | * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, |
| 987 | * CM_TESLA_STATICDEP | 987 | * CM_TESLA_STATICDEP |
| 988 | */ | 988 | */ |
| 989 | #define OMAP4430_IVAHD_STATDEP_SHIFT (1 << 2) | 989 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
| 990 | #define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) | 990 | #define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) |
| 991 | 991 | ||
| 992 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | 992 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| 993 | #define OMAP4430_L3INIT_DYNDEP_SHIFT (1 << 7) | 993 | #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 |
| 994 | #define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) | 994 | #define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) |
| 995 | 995 | ||
| 996 | /* | 996 | /* |
| 997 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, | 997 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, |
| 998 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 998 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 999 | */ | 999 | */ |
| 1000 | #define OMAP4430_L3INIT_STATDEP_SHIFT (1 << 7) | 1000 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
| 1001 | #define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) | 1001 | #define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) |
| 1002 | 1002 | ||
| 1003 | /* | 1003 | /* |
| 1004 | * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, | 1004 | * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, |
| 1005 | * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | 1005 | * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
| 1006 | */ | 1006 | */ |
| 1007 | #define OMAP4430_L3_1_DYNDEP_SHIFT (1 << 5) | 1007 | #define OMAP4430_L3_1_DYNDEP_SHIFT 5 |
| 1008 | #define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) | 1008 | #define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) |
| 1009 | 1009 | ||
| 1010 | /* | 1010 | /* |
| @@ -1013,7 +1013,7 @@ | |||
| 1013 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, | 1013 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, |
| 1014 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 1014 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 1015 | */ | 1015 | */ |
| 1016 | #define OMAP4430_L3_1_STATDEP_SHIFT (1 << 5) | 1016 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
| 1017 | #define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) | 1017 | #define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) |
| 1018 | 1018 | ||
| 1019 | /* | 1019 | /* |
| @@ -1022,7 +1022,7 @@ | |||
| 1022 | * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, | 1022 | * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, |
| 1023 | * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP | 1023 | * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP |
| 1024 | */ | 1024 | */ |
| 1025 | #define OMAP4430_L3_2_DYNDEP_SHIFT (1 << 6) | 1025 | #define OMAP4430_L3_2_DYNDEP_SHIFT 6 |
| 1026 | #define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) | 1026 | #define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) |
| 1027 | 1027 | ||
| 1028 | /* | 1028 | /* |
| @@ -1031,11 +1031,11 @@ | |||
| 1031 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, | 1031 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, |
| 1032 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 1032 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 1033 | */ | 1033 | */ |
| 1034 | #define OMAP4430_L3_2_STATDEP_SHIFT (1 << 6) | 1034 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
| 1035 | #define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) | 1035 | #define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) |
| 1036 | 1036 | ||
| 1037 | /* Used by CM_L3_1_DYNAMICDEP */ | 1037 | /* Used by CM_L3_1_DYNAMICDEP */ |
| 1038 | #define OMAP4430_L4CFG_DYNDEP_SHIFT (1 << 12) | 1038 | #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 |
| 1039 | #define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) | 1039 | #define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) |
| 1040 | 1040 | ||
| 1041 | /* | 1041 | /* |
| @@ -1043,11 +1043,11 @@ | |||
| 1043 | * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, | 1043 | * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, |
| 1044 | * CM_TESLA_STATICDEP | 1044 | * CM_TESLA_STATICDEP |
| 1045 | */ | 1045 | */ |
| 1046 | #define OMAP4430_L4CFG_STATDEP_SHIFT (1 << 12) | 1046 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
| 1047 | #define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) | 1047 | #define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) |
| 1048 | 1048 | ||
| 1049 | /* Used by CM_L3_2_DYNAMICDEP */ | 1049 | /* Used by CM_L3_2_DYNAMICDEP */ |
| 1050 | #define OMAP4430_L4PER_DYNDEP_SHIFT (1 << 13) | 1050 | #define OMAP4430_L4PER_DYNDEP_SHIFT 13 |
| 1051 | #define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) | 1051 | #define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) |
| 1052 | 1052 | ||
| 1053 | /* | 1053 | /* |
| @@ -1055,36 +1055,36 @@ | |||
| 1055 | * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, | 1055 | * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, |
| 1056 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 1056 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 1057 | */ | 1057 | */ |
| 1058 | #define OMAP4430_L4PER_STATDEP_SHIFT (1 << 13) | 1058 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
| 1059 | #define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) | 1059 | #define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) |
| 1060 | 1060 | ||
| 1061 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | 1061 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| 1062 | #define OMAP4430_L4SEC_DYNDEP_SHIFT (1 << 14) | 1062 | #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 |
| 1063 | #define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) | 1063 | #define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) |
| 1064 | 1064 | ||
| 1065 | /* | 1065 | /* |
| 1066 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, | 1066 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, |
| 1067 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP | 1067 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP |
| 1068 | */ | 1068 | */ |
| 1069 | #define OMAP4430_L4SEC_STATDEP_SHIFT (1 << 14) | 1069 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
| 1070 | #define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) | 1070 | #define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) |
| 1071 | 1071 | ||
| 1072 | /* Used by CM_L4CFG_DYNAMICDEP */ | 1072 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1073 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT (1 << 15) | 1073 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 |
| 1074 | #define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) | 1074 | #define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) |
| 1075 | 1075 | ||
| 1076 | /* | 1076 | /* |
| 1077 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, | 1077 | * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, |
| 1078 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 1078 | * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 1079 | */ | 1079 | */ |
| 1080 | #define OMAP4430_L4WKUP_STATDEP_SHIFT (1 << 15) | 1080 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
| 1081 | #define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) | 1081 | #define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) |
| 1082 | 1082 | ||
| 1083 | /* | 1083 | /* |
| 1084 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | 1084 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| 1085 | * CM_MPU_DYNAMICDEP | 1085 | * CM_MPU_DYNAMICDEP |
| 1086 | */ | 1086 | */ |
| 1087 | #define OMAP4430_MEMIF_DYNDEP_SHIFT (1 << 4) | 1087 | #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 |
| 1088 | #define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) | 1088 | #define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) |
| 1089 | 1089 | ||
| 1090 | /* | 1090 | /* |
| @@ -1093,7 +1093,7 @@ | |||
| 1093 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, | 1093 | * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, |
| 1094 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP | 1094 | * CM_MPU_STATICDEP, CM_TESLA_STATICDEP |
| 1095 | */ | 1095 | */ |
| 1096 | #define OMAP4430_MEMIF_STATDEP_SHIFT (1 << 4) | 1096 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
| 1097 | #define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) | 1097 | #define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) |
| 1098 | 1098 | ||
| 1099 | /* | 1099 | /* |
| @@ -1103,7 +1103,7 @@ | |||
| 1103 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | 1103 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
| 1104 | * CM_SSC_MODFREQDIV_DPLL_MPU | 1104 | * CM_SSC_MODFREQDIV_DPLL_MPU |
| 1105 | */ | 1105 | */ |
| 1106 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT (1 << 8) | 1106 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 |
| 1107 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) | 1107 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) |
| 1108 | 1108 | ||
| 1109 | /* | 1109 | /* |
| @@ -1113,7 +1113,7 @@ | |||
| 1113 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | 1113 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
| 1114 | * CM_SSC_MODFREQDIV_DPLL_MPU | 1114 | * CM_SSC_MODFREQDIV_DPLL_MPU |
| 1115 | */ | 1115 | */ |
| 1116 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT (1 << 0) | 1116 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 |
| 1117 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) | 1117 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) |
| 1118 | 1118 | ||
| 1119 | /* | 1119 | /* |
| @@ -1169,23 +1169,23 @@ | |||
| 1169 | * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, | 1169 | * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, |
| 1170 | * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL | 1170 | * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL |
| 1171 | */ | 1171 | */ |
| 1172 | #define OMAP4430_MODULEMODE_SHIFT (1 << 0) | 1172 | #define OMAP4430_MODULEMODE_SHIFT 0 |
| 1173 | #define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) | 1173 | #define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) |
| 1174 | 1174 | ||
| 1175 | /* Used by CM_DSS_DSS_CLKCTRL */ | 1175 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1176 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT (1 << 9) | 1176 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
| 1177 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) | 1177 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) |
| 1178 | 1178 | ||
| 1179 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | 1179 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ |
| 1180 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT (1 << 8) | 1180 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
| 1181 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) | 1181 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) |
| 1182 | 1182 | ||
| 1183 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | 1183 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ |
| 1184 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT (1 << 9) | 1184 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 |
| 1185 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) | 1185 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) |
| 1186 | 1186 | ||
| 1187 | /* Used by CM_CAM_ISS_CLKCTRL */ | 1187 | /* Used by CM_CAM_ISS_CLKCTRL */ |
| 1188 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT (1 << 8) | 1188 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
| 1189 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) | 1189 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) |
| 1190 | 1190 | ||
| 1191 | /* | 1191 | /* |
| @@ -1195,119 +1195,119 @@ | |||
| 1195 | * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, | 1195 | * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, |
| 1196 | * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE | 1196 | * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE |
| 1197 | */ | 1197 | */ |
| 1198 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT (1 << 8) | 1198 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
| 1199 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) | 1199 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) |
| 1200 | 1200 | ||
| 1201 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ | 1201 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ |
| 1202 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT (1 << 8) | 1202 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 |
| 1203 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) | 1203 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) |
| 1204 | 1204 | ||
| 1205 | /* Used by CM_DSS_DSS_CLKCTRL */ | 1205 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1206 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT (1 << 8) | 1206 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
| 1207 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) | 1207 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) |
| 1208 | 1208 | ||
| 1209 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | 1209 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1210 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT (1 << 8) | 1210 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
| 1211 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) | 1211 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) |
| 1212 | 1212 | ||
| 1213 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | 1213 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1214 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT (1 << 9) | 1214 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
| 1215 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) | 1215 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) |
| 1216 | 1216 | ||
| 1217 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | 1217 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1218 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT (1 << 10) | 1218 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
| 1219 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) | 1219 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) |
| 1220 | 1220 | ||
| 1221 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1221 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1222 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT (1 << 15) | 1222 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
| 1223 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) | 1223 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) |
| 1224 | 1224 | ||
| 1225 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1225 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1226 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT (1 << 13) | 1226 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
| 1227 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) | 1227 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) |
| 1228 | 1228 | ||
| 1229 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1229 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1230 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT (1 << 14) | 1230 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
| 1231 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) | 1231 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) |
| 1232 | 1232 | ||
| 1233 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1233 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1234 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT (1 << 11) | 1234 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
| 1235 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) | 1235 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) |
| 1236 | 1236 | ||
| 1237 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1237 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1238 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT (1 << 12) | 1238 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
| 1239 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) | 1239 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) |
| 1240 | 1240 | ||
| 1241 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | 1241 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| 1242 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT (1 << 8) | 1242 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
| 1243 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) | 1243 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) |
| 1244 | 1244 | ||
| 1245 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | 1245 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| 1246 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT (1 << 9) | 1246 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
| 1247 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) | 1247 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) |
| 1248 | 1248 | ||
| 1249 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | 1249 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ |
| 1250 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT (1 << 8) | 1250 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
| 1251 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) | 1251 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) |
| 1252 | 1252 | ||
| 1253 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | 1253 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| 1254 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT (1 << 10) | 1254 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
| 1255 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) | 1255 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) |
| 1256 | 1256 | ||
| 1257 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ | 1257 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| 1258 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT (1 << 11) | 1258 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
| 1259 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) | 1259 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) |
| 1260 | 1260 | ||
| 1261 | /* Used by CM_DSS_DSS_CLKCTRL */ | 1261 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1262 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT (1 << 10) | 1262 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
| 1263 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) | 1263 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) |
| 1264 | 1264 | ||
| 1265 | /* Used by CM_DSS_DSS_CLKCTRL */ | 1265 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| 1266 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT (1 << 11) | 1266 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
| 1267 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) | 1267 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) |
| 1268 | 1268 | ||
| 1269 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ | 1269 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ |
| 1270 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT (1 << 8) | 1270 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 |
| 1271 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) | 1271 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) |
| 1272 | 1272 | ||
| 1273 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ | 1273 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ |
| 1274 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT (1 << 8) | 1274 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
| 1275 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) | 1275 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) |
| 1276 | 1276 | ||
| 1277 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ | 1277 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ |
| 1278 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT (1 << 9) | 1278 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
| 1279 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) | 1279 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) |
| 1280 | 1280 | ||
| 1281 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ | 1281 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ |
| 1282 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT (1 << 10) | 1282 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
| 1283 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) | 1283 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) |
| 1284 | 1284 | ||
| 1285 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1285 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1286 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT (1 << 8) | 1286 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
| 1287 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) | 1287 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) |
| 1288 | 1288 | ||
| 1289 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1289 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1290 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT (1 << 9) | 1290 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
| 1291 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) | 1291 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) |
| 1292 | 1292 | ||
| 1293 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ | 1293 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ |
| 1294 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT (1 << 10) | 1294 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
| 1295 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) | 1295 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) |
| 1296 | 1296 | ||
| 1297 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | 1297 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ |
| 1298 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT (1 << 8) | 1298 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
| 1299 | #define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) | 1299 | #define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) |
| 1300 | 1300 | ||
| 1301 | /* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ | 1301 | /* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ |
| 1302 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT (1 << 19) | 1302 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 |
| 1303 | #define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) | 1303 | #define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) |
| 1304 | 1304 | ||
| 1305 | /* Used by CM_CLKSEL_ABE */ | 1305 | /* Used by CM_CLKSEL_ABE */ |
| 1306 | #define OMAP4430_PAD_CLKS_GATE_SHIFT (1 << 8) | 1306 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
| 1307 | #define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) | 1307 | #define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) |
| 1308 | 1308 | ||
| 1309 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ | 1309 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ |
| 1310 | #define OMAP4430_PERF_CURRENT_SHIFT (1 << 0) | 1310 | #define OMAP4430_PERF_CURRENT_SHIFT 0 |
| 1311 | #define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) | 1311 | #define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) |
| 1312 | 1312 | ||
| 1313 | /* | 1313 | /* |
| @@ -1315,66 +1315,66 @@ | |||
| 1315 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, | 1315 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, |
| 1316 | * CM_IVA_DVFS_PERF_TESLA | 1316 | * CM_IVA_DVFS_PERF_TESLA |
| 1317 | */ | 1317 | */ |
| 1318 | #define OMAP4430_PERF_REQ_SHIFT (1 << 0) | 1318 | #define OMAP4430_PERF_REQ_SHIFT 0 |
| 1319 | #define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) | 1319 | #define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) |
| 1320 | 1320 | ||
| 1321 | /* Used by CM_EMU_OVERRIDE_DPLL_PER */ | 1321 | /* Used by CM_EMU_OVERRIDE_DPLL_PER */ |
| 1322 | #define OMAP4430_PER_DPLL_EMU_DIV_SHIFT (1 << 0) | 1322 | #define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 |
| 1323 | #define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) | 1323 | #define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) |
| 1324 | 1324 | ||
| 1325 | /* Used by CM_EMU_OVERRIDE_DPLL_PER */ | 1325 | /* Used by CM_EMU_OVERRIDE_DPLL_PER */ |
| 1326 | #define OMAP4430_PER_DPLL_EMU_MULT_SHIFT (1 << 8) | 1326 | #define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 |
| 1327 | #define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) | 1327 | #define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) |
| 1328 | 1328 | ||
| 1329 | /* Used by CM_RESTORE_ST */ | 1329 | /* Used by CM_RESTORE_ST */ |
| 1330 | #define OMAP4430_PHASE1_COMPLETED_SHIFT (1 << 0) | 1330 | #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 |
| 1331 | #define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) | 1331 | #define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) |
| 1332 | 1332 | ||
| 1333 | /* Used by CM_RESTORE_ST */ | 1333 | /* Used by CM_RESTORE_ST */ |
| 1334 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT (1 << 1) | 1334 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 |
| 1335 | #define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) | 1335 | #define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) |
| 1336 | 1336 | ||
| 1337 | /* Used by CM_RESTORE_ST */ | 1337 | /* Used by CM_RESTORE_ST */ |
| 1338 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT (1 << 2) | 1338 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 |
| 1339 | #define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) | 1339 | #define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) |
| 1340 | 1340 | ||
| 1341 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | 1341 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 1342 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT (1 << 20) | 1342 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
| 1343 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) | 1343 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) |
| 1344 | 1344 | ||
| 1345 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | 1345 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| 1346 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT (1 << 22) | 1346 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
| 1347 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) | 1347 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) |
| 1348 | 1348 | ||
| 1349 | /* Used by CM_DYN_DEP_PRESCAL */ | 1349 | /* Used by CM_DYN_DEP_PRESCAL */ |
| 1350 | #define OMAP4430_PRESCAL_SHIFT (1 << 0) | 1350 | #define OMAP4430_PRESCAL_SHIFT 0 |
| 1351 | #define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) | 1351 | #define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) |
| 1352 | 1352 | ||
| 1353 | /* Used by REVISION_CM2, REVISION_CM1 */ | 1353 | /* Used by REVISION_CM2, REVISION_CM1 */ |
| 1354 | #define OMAP4430_REV_SHIFT (1 << 0) | 1354 | #define OMAP4430_REV_SHIFT 0 |
| 1355 | #define OMAP4430_REV_MASK BITFIELD(0, 7) | 1355 | #define OMAP4430_REV_MASK BITFIELD(0, 7) |
| 1356 | 1356 | ||
| 1357 | /* | 1357 | /* |
| 1358 | * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | 1358 | * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, |
| 1359 | * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE | 1359 | * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE |
| 1360 | */ | 1360 | */ |
| 1361 | #define OMAP4430_SAR_MODE_SHIFT (1 << 4) | 1361 | #define OMAP4430_SAR_MODE_SHIFT 4 |
| 1362 | #define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) | 1362 | #define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) |
| 1363 | 1363 | ||
| 1364 | /* Used by CM_SCALE_FCLK */ | 1364 | /* Used by CM_SCALE_FCLK */ |
| 1365 | #define OMAP4430_SCALE_FCLK_SHIFT (1 << 0) | 1365 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
| 1366 | #define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) | 1366 | #define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) |
| 1367 | 1367 | ||
| 1368 | /* Used by CM_L4CFG_DYNAMICDEP */ | 1368 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1369 | #define OMAP4430_SDMA_DYNDEP_SHIFT (1 << 11) | 1369 | #define OMAP4430_SDMA_DYNDEP_SHIFT 11 |
| 1370 | #define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) | 1370 | #define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) |
| 1371 | 1371 | ||
| 1372 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | 1372 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| 1373 | #define OMAP4430_SDMA_STATDEP_SHIFT (1 << 11) | 1373 | #define OMAP4430_SDMA_STATDEP_SHIFT 11 |
| 1374 | #define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) | 1374 | #define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) |
| 1375 | 1375 | ||
| 1376 | /* Used by CM_CLKSEL_ABE */ | 1376 | /* Used by CM_CLKSEL_ABE */ |
| 1377 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT (1 << 10) | 1377 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
| 1378 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) | 1378 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) |
| 1379 | 1379 | ||
| 1380 | /* | 1380 | /* |
| @@ -1390,7 +1390,7 @@ | |||
| 1390 | * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, | 1390 | * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, |
| 1391 | * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL | 1391 | * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL |
| 1392 | */ | 1392 | */ |
| 1393 | #define OMAP4430_STBYST_SHIFT (1 << 18) | 1393 | #define OMAP4430_STBYST_SHIFT 18 |
| 1394 | #define OMAP4430_STBYST_MASK BITFIELD(18, 18) | 1394 | #define OMAP4430_STBYST_MASK BITFIELD(18, 18) |
| 1395 | 1395 | ||
| 1396 | /* | 1396 | /* |
| @@ -1398,11 +1398,11 @@ | |||
| 1398 | * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | 1398 | * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, |
| 1399 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU | 1399 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU |
| 1400 | */ | 1400 | */ |
| 1401 | #define OMAP4430_ST_DPLL_CLK_SHIFT (1 << 0) | 1401 | #define OMAP4430_ST_DPLL_CLK_SHIFT 0 |
| 1402 | #define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) | 1402 | #define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) |
| 1403 | 1403 | ||
| 1404 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | 1404 | /* Used by CM_CLKDCOLDO_DPLL_USB */ |
| 1405 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT (1 << 9) | 1405 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 |
| 1406 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) | 1406 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) |
| 1407 | 1407 | ||
| 1408 | /* | 1408 | /* |
| @@ -1410,58 +1410,58 @@ | |||
| 1410 | * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | 1410 | * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| 1411 | * CM_DIV_M2_DPLL_MPU | 1411 | * CM_DIV_M2_DPLL_MPU |
| 1412 | */ | 1412 | */ |
| 1413 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT (1 << 9) | 1413 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 |
| 1414 | #define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) | 1414 | #define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) |
| 1415 | 1415 | ||
| 1416 | /* | 1416 | /* |
| 1417 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, | 1417 | * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, |
| 1418 | * CM_DIV_M3_DPLL_CORE | 1418 | * CM_DIV_M3_DPLL_CORE |
| 1419 | */ | 1419 | */ |
| 1420 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT (1 << 9) | 1420 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 |
| 1421 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) | 1421 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) |
| 1422 | 1422 | ||
| 1423 | /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ | 1423 | /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ |
| 1424 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT (1 << 11) | 1424 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 |
| 1425 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) | 1425 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) |
| 1426 | 1426 | ||
| 1427 | /* | 1427 | /* |
| 1428 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, | 1428 | * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, |
| 1429 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA | 1429 | * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA |
| 1430 | */ | 1430 | */ |
| 1431 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT (1 << 9) | 1431 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 |
| 1432 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) | 1432 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) |
| 1433 | 1433 | ||
| 1434 | /* | 1434 | /* |
| 1435 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, | 1435 | * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, |
| 1436 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA | 1436 | * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA |
| 1437 | */ | 1437 | */ |
| 1438 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT (1 << 9) | 1438 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 |
| 1439 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) | 1439 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) |
| 1440 | 1440 | ||
| 1441 | /* | 1441 | /* |
| 1442 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, | 1442 | * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, |
| 1443 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY | 1443 | * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY |
| 1444 | */ | 1444 | */ |
| 1445 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT (1 << 9) | 1445 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 |
| 1446 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) | 1446 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) |
| 1447 | 1447 | ||
| 1448 | /* | 1448 | /* |
| 1449 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, | 1449 | * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, |
| 1450 | * CM_DIV_M7_DPLL_CORE | 1450 | * CM_DIV_M7_DPLL_CORE |
| 1451 | */ | 1451 | */ |
| 1452 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT (1 << 9) | 1452 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 |
| 1453 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) | 1453 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) |
| 1454 | 1454 | ||
| 1455 | /* Used by CM_SYS_CLKSEL */ | 1455 | /* Used by CM_SYS_CLKSEL */ |
| 1456 | #define OMAP4430_SYS_CLKSEL_SHIFT (1 << 0) | 1456 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
| 1457 | #define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) | 1457 | #define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) |
| 1458 | 1458 | ||
| 1459 | /* Used by CM_L4CFG_DYNAMICDEP */ | 1459 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| 1460 | #define OMAP4430_TESLA_DYNDEP_SHIFT (1 << 1) | 1460 | #define OMAP4430_TESLA_DYNDEP_SHIFT 1 |
| 1461 | #define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) | 1461 | #define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) |
| 1462 | 1462 | ||
| 1463 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | 1463 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| 1464 | #define OMAP4430_TESLA_STATDEP_SHIFT (1 << 1) | 1464 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
| 1465 | #define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) | 1465 | #define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) |
| 1466 | 1466 | ||
| 1467 | /* | 1467 | /* |
| @@ -1469,6 +1469,6 @@ | |||
| 1469 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | 1469 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| 1470 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | 1470 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
| 1471 | */ | 1471 | */ |
| 1472 | #define OMAP4430_WINDOWSIZE_SHIFT (1 << 24) | 1472 | #define OMAP4430_WINDOWSIZE_SHIFT 24 |
| 1473 | #define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) | 1473 | #define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) |
| 1474 | #endif | 1474 | #endif |
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 90a4086fbdf4..94728b1ee3c4 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h | |||
| @@ -67,7 +67,8 @@ | |||
| 67 | #define CM_CLKSEL 0x0040 | 67 | #define CM_CLKSEL 0x0040 |
| 68 | #define CM_CLKSEL1 CM_CLKSEL | 68 | #define CM_CLKSEL1 CM_CLKSEL |
| 69 | #define CM_CLKSEL2 0x0044 | 69 | #define CM_CLKSEL2 0x0044 |
| 70 | #define CM_CLKSTCTRL 0x0048 | 70 | #define OMAP2_CM_CLKSTCTRL 0x0048 |
| 71 | #define OMAP4_CM_CLKSTCTRL 0x0000 | ||
| 71 | 72 | ||
| 72 | 73 | ||
| 73 | /* Architecture-specific registers */ | 74 | /* Architecture-specific registers */ |
| @@ -88,7 +89,7 @@ | |||
| 88 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL | 89 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL |
| 89 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 | 90 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 |
| 90 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 | 91 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 |
| 91 | #define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL | 92 | #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL |
| 92 | #define OMAP3430_CM_CLKSTST 0x004c | 93 | #define OMAP3430_CM_CLKSTST 0x004c |
| 93 | #define OMAP3430ES2_CM_CLKSEL4 0x004c | 94 | #define OMAP3430ES2_CM_CLKSEL4 0x004c |
| 94 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 | 95 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 |
| @@ -138,5 +139,8 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | |||
| 138 | /* CM_IDLEST_GFX */ | 139 | /* CM_IDLEST_GFX */ |
| 139 | #define OMAP_ST_GFX (1 << 0) | 140 | #define OMAP_ST_GFX (1 << 0) |
| 140 | 141 | ||
| 142 | /* CM_IDLEST indicator */ | ||
| 143 | #define OMAP24XX_CM_IDLEST_VAL 0 | ||
| 144 | #define OMAP34XX_CM_IDLEST_VAL 1 | ||
| 141 | 145 | ||
| 142 | #endif | 146 | #endif |
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index cdd1f35636dd..43f8a33655d4 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
| @@ -140,7 +140,11 @@ static struct omap3_control_regs control_context; | |||
| 140 | 140 | ||
| 141 | void __init omap2_set_globals_control(struct omap_globals *omap2_globals) | 141 | void __init omap2_set_globals_control(struct omap_globals *omap2_globals) |
| 142 | { | 142 | { |
| 143 | omap2_ctrl_base = omap2_globals->ctrl; | 143 | /* Static mapping, never released */ |
| 144 | if (omap2_globals->ctrl) { | ||
| 145 | omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); | ||
| 146 | WARN_ON(!omap2_ctrl_base); | ||
| 147 | } | ||
| 144 | } | 148 | } |
| 145 | 149 | ||
| 146 | void __iomem *omap_ctrl_base_get(void) | 150 | void __iomem *omap_ctrl_base_get(void) |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 12f0cbfc2894..3d3d035db9af 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
| @@ -45,6 +45,8 @@ | |||
| 45 | #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */ | 45 | #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */ |
| 46 | #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */ | 46 | #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */ |
| 47 | 47 | ||
| 48 | #define OMAP3_STATE_MAX OMAP3_STATE_C7 | ||
| 49 | |||
| 48 | struct omap3_processor_cx { | 50 | struct omap3_processor_cx { |
| 49 | u8 valid; | 51 | u8 valid; |
| 50 | u8 type; | 52 | u8 type; |
| @@ -60,6 +62,30 @@ struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; | |||
| 60 | struct omap3_processor_cx current_cx_state; | 62 | struct omap3_processor_cx current_cx_state; |
| 61 | struct powerdomain *mpu_pd, *core_pd; | 63 | struct powerdomain *mpu_pd, *core_pd; |
| 62 | 64 | ||
| 65 | /* | ||
| 66 | * The latencies/thresholds for various C states have | ||
| 67 | * to be configured from the respective board files. | ||
| 68 | * These are some default values (which might not provide | ||
| 69 | * the best power savings) used on boards which do not | ||
| 70 | * pass these details from the board file. | ||
| 71 | */ | ||
| 72 | static struct cpuidle_params cpuidle_params_table[] = { | ||
| 73 | /* C1 */ | ||
| 74 | {1, 2, 2, 5}, | ||
| 75 | /* C2 */ | ||
| 76 | {1, 10, 10, 30}, | ||
| 77 | /* C3 */ | ||
| 78 | {1, 50, 50, 300}, | ||
| 79 | /* C4 */ | ||
| 80 | {1, 1500, 1800, 4000}, | ||
| 81 | /* C5 */ | ||
| 82 | {1, 2500, 7500, 12000}, | ||
| 83 | /* C6 */ | ||
| 84 | {1, 3000, 8500, 15000}, | ||
| 85 | /* C7 */ | ||
| 86 | {1, 10000, 30000, 300000}, | ||
| 87 | }; | ||
| 88 | |||
| 63 | static int omap3_idle_bm_check(void) | 89 | static int omap3_idle_bm_check(void) |
| 64 | { | 90 | { |
| 65 | if (!omap3_can_sleep()) | 91 | if (!omap3_can_sleep()) |
| @@ -104,13 +130,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev, | |||
| 104 | local_irq_disable(); | 130 | local_irq_disable(); |
| 105 | local_fiq_disable(); | 131 | local_fiq_disable(); |
| 106 | 132 | ||
| 107 | if (!enable_off_mode) { | ||
| 108 | if (mpu_state < PWRDM_POWER_RET) | ||
| 109 | mpu_state = PWRDM_POWER_RET; | ||
| 110 | if (core_state < PWRDM_POWER_RET) | ||
| 111 | core_state = PWRDM_POWER_RET; | ||
| 112 | } | ||
| 113 | |||
| 114 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); | 133 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); |
| 115 | pwrdm_set_next_pwrst(core_pd, core_state); | 134 | pwrdm_set_next_pwrst(core_pd, core_state); |
| 116 | 135 | ||
| @@ -141,6 +160,67 @@ return_sleep_time: | |||
| 141 | } | 160 | } |
| 142 | 161 | ||
| 143 | /** | 162 | /** |
| 163 | * next_valid_state - Find next valid c-state | ||
| 164 | * @dev: cpuidle device | ||
| 165 | * @state: Currently selected c-state | ||
| 166 | * | ||
| 167 | * If the current state is valid, it is returned back to the caller. | ||
| 168 | * Else, this function searches for a lower c-state which is still | ||
| 169 | * valid (as defined in omap3_power_states[]). | ||
| 170 | */ | ||
| 171 | static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev, | ||
| 172 | struct cpuidle_state *curr) | ||
| 173 | { | ||
| 174 | struct cpuidle_state *next = NULL; | ||
| 175 | struct omap3_processor_cx *cx; | ||
| 176 | |||
| 177 | cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr); | ||
| 178 | |||
| 179 | /* Check if current state is valid */ | ||
| 180 | if (cx->valid) { | ||
| 181 | return curr; | ||
| 182 | } else { | ||
| 183 | u8 idx = OMAP3_STATE_MAX; | ||
| 184 | |||
| 185 | /* | ||
| 186 | * Reach the current state starting at highest C-state | ||
| 187 | */ | ||
| 188 | for (; idx >= OMAP3_STATE_C1; idx--) { | ||
| 189 | if (&dev->states[idx] == curr) { | ||
| 190 | next = &dev->states[idx]; | ||
| 191 | break; | ||
| 192 | } | ||
| 193 | } | ||
| 194 | |||
| 195 | /* | ||
| 196 | * Should never hit this condition. | ||
| 197 | */ | ||
| 198 | WARN_ON(next == NULL); | ||
| 199 | |||
| 200 | /* | ||
| 201 | * Drop to next valid state. | ||
| 202 | * Start search from the next (lower) state. | ||
| 203 | */ | ||
| 204 | idx--; | ||
| 205 | for (; idx >= OMAP3_STATE_C1; idx--) { | ||
| 206 | struct omap3_processor_cx *cx; | ||
| 207 | |||
| 208 | cx = cpuidle_get_statedata(&dev->states[idx]); | ||
| 209 | if (cx->valid) { | ||
| 210 | next = &dev->states[idx]; | ||
| 211 | break; | ||
| 212 | } | ||
| 213 | } | ||
| 214 | /* | ||
| 215 | * C1 and C2 are always valid. | ||
| 216 | * So, no need to check for 'next==NULL' outside this loop. | ||
| 217 | */ | ||
| 218 | } | ||
| 219 | |||
| 220 | return next; | ||
| 221 | } | ||
| 222 | |||
| 223 | /** | ||
| 144 | * omap3_enter_idle_bm - Checks for any bus activity | 224 | * omap3_enter_idle_bm - Checks for any bus activity |
| 145 | * @dev: cpuidle device | 225 | * @dev: cpuidle device |
| 146 | * @state: The target state to be programmed | 226 | * @state: The target state to be programmed |
| @@ -152,7 +232,7 @@ return_sleep_time: | |||
| 152 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, | 232 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
| 153 | struct cpuidle_state *state) | 233 | struct cpuidle_state *state) |
| 154 | { | 234 | { |
| 155 | struct cpuidle_state *new_state = state; | 235 | struct cpuidle_state *new_state = next_valid_state(dev, state); |
| 156 | 236 | ||
| 157 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { | 237 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { |
| 158 | BUG_ON(!dev->safe_state); | 238 | BUG_ON(!dev->safe_state); |
| @@ -165,6 +245,50 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, | |||
| 165 | 245 | ||
| 166 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | 246 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
| 167 | 247 | ||
| 248 | /** | ||
| 249 | * omap3_cpuidle_update_states - Update the cpuidle states. | ||
| 250 | * | ||
| 251 | * Currently, this function toggles the validity of idle states based upon | ||
| 252 | * the flag 'enable_off_mode'. When the flag is set all states are valid. | ||
| 253 | * Else, states leading to OFF state set to be invalid. | ||
| 254 | */ | ||
| 255 | void omap3_cpuidle_update_states(void) | ||
| 256 | { | ||
| 257 | int i; | ||
| 258 | |||
| 259 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { | ||
| 260 | struct omap3_processor_cx *cx = &omap3_power_states[i]; | ||
| 261 | |||
| 262 | if (enable_off_mode) { | ||
| 263 | cx->valid = 1; | ||
| 264 | } else { | ||
| 265 | if ((cx->mpu_state == PWRDM_POWER_OFF) || | ||
| 266 | (cx->core_state == PWRDM_POWER_OFF)) | ||
| 267 | cx->valid = 0; | ||
| 268 | } | ||
| 269 | } | ||
| 270 | } | ||
| 271 | |||
| 272 | void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) | ||
| 273 | { | ||
| 274 | int i; | ||
| 275 | |||
| 276 | if (!cpuidle_board_params) | ||
| 277 | return; | ||
| 278 | |||
| 279 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { | ||
| 280 | cpuidle_params_table[i].valid = | ||
| 281 | cpuidle_board_params[i].valid; | ||
| 282 | cpuidle_params_table[i].sleep_latency = | ||
| 283 | cpuidle_board_params[i].sleep_latency; | ||
| 284 | cpuidle_params_table[i].wake_latency = | ||
| 285 | cpuidle_board_params[i].wake_latency; | ||
| 286 | cpuidle_params_table[i].threshold = | ||
| 287 | cpuidle_board_params[i].threshold; | ||
| 288 | } | ||
| 289 | return; | ||
| 290 | } | ||
| 291 | |||
| 168 | /* omap3_init_power_states - Initialises the OMAP3 specific C states. | 292 | /* omap3_init_power_states - Initialises the OMAP3 specific C states. |
| 169 | * | 293 | * |
| 170 | * Below is the desciption of each C state. | 294 | * Below is the desciption of each C state. |
| @@ -179,75 +303,103 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | |||
| 179 | void omap_init_power_states(void) | 303 | void omap_init_power_states(void) |
| 180 | { | 304 | { |
| 181 | /* C1 . MPU WFI + Core active */ | 305 | /* C1 . MPU WFI + Core active */ |
| 182 | omap3_power_states[OMAP3_STATE_C1].valid = 1; | 306 | omap3_power_states[OMAP3_STATE_C1].valid = |
| 307 | cpuidle_params_table[OMAP3_STATE_C1].valid; | ||
| 183 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; | 308 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; |
| 184 | omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2; | 309 | omap3_power_states[OMAP3_STATE_C1].sleep_latency = |
| 185 | omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2; | 310 | cpuidle_params_table[OMAP3_STATE_C1].sleep_latency; |
| 186 | omap3_power_states[OMAP3_STATE_C1].threshold = 5; | 311 | omap3_power_states[OMAP3_STATE_C1].wakeup_latency = |
| 312 | cpuidle_params_table[OMAP3_STATE_C1].wake_latency; | ||
| 313 | omap3_power_states[OMAP3_STATE_C1].threshold = | ||
| 314 | cpuidle_params_table[OMAP3_STATE_C1].threshold; | ||
| 187 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; | 315 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; |
| 188 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; | 316 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; |
| 189 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; | 317 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; |
| 190 | 318 | ||
| 191 | /* C2 . MPU WFI + Core inactive */ | 319 | /* C2 . MPU WFI + Core inactive */ |
| 192 | omap3_power_states[OMAP3_STATE_C2].valid = 1; | 320 | omap3_power_states[OMAP3_STATE_C2].valid = |
| 321 | cpuidle_params_table[OMAP3_STATE_C2].valid; | ||
| 193 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; | 322 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; |
| 194 | omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10; | 323 | omap3_power_states[OMAP3_STATE_C2].sleep_latency = |
| 195 | omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10; | 324 | cpuidle_params_table[OMAP3_STATE_C2].sleep_latency; |
| 196 | omap3_power_states[OMAP3_STATE_C2].threshold = 30; | 325 | omap3_power_states[OMAP3_STATE_C2].wakeup_latency = |
| 326 | cpuidle_params_table[OMAP3_STATE_C2].wake_latency; | ||
| 327 | omap3_power_states[OMAP3_STATE_C2].threshold = | ||
| 328 | cpuidle_params_table[OMAP3_STATE_C2].threshold; | ||
| 197 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; | 329 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; |
| 198 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; | 330 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; |
| 199 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; | 331 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; |
| 200 | 332 | ||
| 201 | /* C3 . MPU CSWR + Core inactive */ | 333 | /* C3 . MPU CSWR + Core inactive */ |
| 202 | omap3_power_states[OMAP3_STATE_C3].valid = 1; | 334 | omap3_power_states[OMAP3_STATE_C3].valid = |
| 335 | cpuidle_params_table[OMAP3_STATE_C3].valid; | ||
| 203 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; | 336 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; |
| 204 | omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50; | 337 | omap3_power_states[OMAP3_STATE_C3].sleep_latency = |
| 205 | omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50; | 338 | cpuidle_params_table[OMAP3_STATE_C3].sleep_latency; |
| 206 | omap3_power_states[OMAP3_STATE_C3].threshold = 300; | 339 | omap3_power_states[OMAP3_STATE_C3].wakeup_latency = |
| 340 | cpuidle_params_table[OMAP3_STATE_C3].wake_latency; | ||
| 341 | omap3_power_states[OMAP3_STATE_C3].threshold = | ||
| 342 | cpuidle_params_table[OMAP3_STATE_C3].threshold; | ||
| 207 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; | 343 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; |
| 208 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; | 344 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; |
| 209 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | | 345 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | |
| 210 | CPUIDLE_FLAG_CHECK_BM; | 346 | CPUIDLE_FLAG_CHECK_BM; |
| 211 | 347 | ||
| 212 | /* C4 . MPU OFF + Core inactive */ | 348 | /* C4 . MPU OFF + Core inactive */ |
| 213 | omap3_power_states[OMAP3_STATE_C4].valid = 1; | 349 | omap3_power_states[OMAP3_STATE_C4].valid = |
| 350 | cpuidle_params_table[OMAP3_STATE_C4].valid; | ||
| 214 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; | 351 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; |
| 215 | omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500; | 352 | omap3_power_states[OMAP3_STATE_C4].sleep_latency = |
| 216 | omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800; | 353 | cpuidle_params_table[OMAP3_STATE_C4].sleep_latency; |
| 217 | omap3_power_states[OMAP3_STATE_C4].threshold = 4000; | 354 | omap3_power_states[OMAP3_STATE_C4].wakeup_latency = |
| 355 | cpuidle_params_table[OMAP3_STATE_C4].wake_latency; | ||
| 356 | omap3_power_states[OMAP3_STATE_C4].threshold = | ||
| 357 | cpuidle_params_table[OMAP3_STATE_C4].threshold; | ||
| 218 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; | 358 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; |
| 219 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; | 359 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; |
| 220 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | | 360 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | |
| 221 | CPUIDLE_FLAG_CHECK_BM; | 361 | CPUIDLE_FLAG_CHECK_BM; |
| 222 | 362 | ||
| 223 | /* C5 . MPU CSWR + Core CSWR*/ | 363 | /* C5 . MPU CSWR + Core CSWR*/ |
| 224 | omap3_power_states[OMAP3_STATE_C5].valid = 1; | 364 | omap3_power_states[OMAP3_STATE_C5].valid = |
| 365 | cpuidle_params_table[OMAP3_STATE_C5].valid; | ||
| 225 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; | 366 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; |
| 226 | omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500; | 367 | omap3_power_states[OMAP3_STATE_C5].sleep_latency = |
| 227 | omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500; | 368 | cpuidle_params_table[OMAP3_STATE_C5].sleep_latency; |
| 228 | omap3_power_states[OMAP3_STATE_C5].threshold = 12000; | 369 | omap3_power_states[OMAP3_STATE_C5].wakeup_latency = |
| 370 | cpuidle_params_table[OMAP3_STATE_C5].wake_latency; | ||
| 371 | omap3_power_states[OMAP3_STATE_C5].threshold = | ||
| 372 | cpuidle_params_table[OMAP3_STATE_C5].threshold; | ||
| 229 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; | 373 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; |
| 230 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; | 374 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; |
| 231 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | | 375 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | |
| 232 | CPUIDLE_FLAG_CHECK_BM; | 376 | CPUIDLE_FLAG_CHECK_BM; |
| 233 | 377 | ||
| 234 | /* C6 . MPU OFF + Core CSWR */ | 378 | /* C6 . MPU OFF + Core CSWR */ |
| 235 | omap3_power_states[OMAP3_STATE_C6].valid = 1; | 379 | omap3_power_states[OMAP3_STATE_C6].valid = |
| 380 | cpuidle_params_table[OMAP3_STATE_C6].valid; | ||
| 236 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; | 381 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; |
| 237 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000; | 382 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = |
| 238 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500; | 383 | cpuidle_params_table[OMAP3_STATE_C6].sleep_latency; |
| 239 | omap3_power_states[OMAP3_STATE_C6].threshold = 15000; | 384 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = |
| 385 | cpuidle_params_table[OMAP3_STATE_C6].wake_latency; | ||
| 386 | omap3_power_states[OMAP3_STATE_C6].threshold = | ||
| 387 | cpuidle_params_table[OMAP3_STATE_C6].threshold; | ||
| 240 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; | 388 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; |
| 241 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; | 389 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; |
| 242 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | | 390 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | |
| 243 | CPUIDLE_FLAG_CHECK_BM; | 391 | CPUIDLE_FLAG_CHECK_BM; |
| 244 | 392 | ||
| 245 | /* C7 . MPU OFF + Core OFF */ | 393 | /* C7 . MPU OFF + Core OFF */ |
| 246 | omap3_power_states[OMAP3_STATE_C7].valid = 1; | 394 | omap3_power_states[OMAP3_STATE_C7].valid = |
| 395 | cpuidle_params_table[OMAP3_STATE_C7].valid; | ||
| 247 | omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; | 396 | omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; |
| 248 | omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000; | 397 | omap3_power_states[OMAP3_STATE_C7].sleep_latency = |
| 249 | omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000; | 398 | cpuidle_params_table[OMAP3_STATE_C7].sleep_latency; |
| 250 | omap3_power_states[OMAP3_STATE_C7].threshold = 300000; | 399 | omap3_power_states[OMAP3_STATE_C7].wakeup_latency = |
| 400 | cpuidle_params_table[OMAP3_STATE_C7].wake_latency; | ||
| 401 | omap3_power_states[OMAP3_STATE_C7].threshold = | ||
| 402 | cpuidle_params_table[OMAP3_STATE_C7].threshold; | ||
| 251 | omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; | 403 | omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; |
| 252 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; | 404 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; |
| 253 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | | 405 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | |
| @@ -302,6 +454,8 @@ int __init omap3_idle_init(void) | |||
| 302 | return -EINVAL; | 454 | return -EINVAL; |
| 303 | dev->state_count = count; | 455 | dev->state_count = count; |
| 304 | 456 | ||
| 457 | omap3_cpuidle_update_states(); | ||
| 458 | |||
| 305 | if (cpuidle_register_device(dev)) { | 459 | if (cpuidle_register_device(dev)) { |
| 306 | printk(KERN_ERR "%s: CPUidle register device failed\n", | 460 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
| 307 | __func__); | 461 | __func__); |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 18ad93160abb..23e4d7733610 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -141,7 +141,7 @@ static inline void omap_init_camera(void) | |||
| 141 | #define MBOX_REG_SIZE 0x120 | 141 | #define MBOX_REG_SIZE 0x120 |
| 142 | 142 | ||
| 143 | #ifdef CONFIG_ARCH_OMAP2 | 143 | #ifdef CONFIG_ARCH_OMAP2 |
| 144 | static struct resource omap_mbox_resources[] = { | 144 | static struct resource omap2_mbox_resources[] = { |
| 145 | { | 145 | { |
| 146 | .start = OMAP24XX_MAILBOX_BASE, | 146 | .start = OMAP24XX_MAILBOX_BASE, |
| 147 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | 147 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, |
| @@ -156,10 +156,14 @@ static struct resource omap_mbox_resources[] = { | |||
| 156 | .flags = IORESOURCE_IRQ, | 156 | .flags = IORESOURCE_IRQ, |
| 157 | }, | 157 | }, |
| 158 | }; | 158 | }; |
| 159 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); | ||
| 160 | #else | ||
| 161 | #define omap2_mbox_resources NULL | ||
| 162 | #define omap2_mbox_resources_sz 0 | ||
| 159 | #endif | 163 | #endif |
| 160 | 164 | ||
| 161 | #ifdef CONFIG_ARCH_OMAP3 | 165 | #ifdef CONFIG_ARCH_OMAP3 |
| 162 | static struct resource omap_mbox_resources[] = { | 166 | static struct resource omap3_mbox_resources[] = { |
| 163 | { | 167 | { |
| 164 | .start = OMAP34XX_MAILBOX_BASE, | 168 | .start = OMAP34XX_MAILBOX_BASE, |
| 165 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | 169 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, |
| @@ -170,12 +174,16 @@ static struct resource omap_mbox_resources[] = { | |||
| 170 | .flags = IORESOURCE_IRQ, | 174 | .flags = IORESOURCE_IRQ, |
| 171 | }, | 175 | }, |
| 172 | }; | 176 | }; |
| 177 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); | ||
| 178 | #else | ||
| 179 | #define omap3_mbox_resources NULL | ||
| 180 | #define omap3_mbox_resources_sz 0 | ||
| 173 | #endif | 181 | #endif |
| 174 | 182 | ||
| 175 | #ifdef CONFIG_ARCH_OMAP4 | 183 | #ifdef CONFIG_ARCH_OMAP4 |
| 176 | 184 | ||
| 177 | #define OMAP4_MBOX_REG_SIZE 0x130 | 185 | #define OMAP4_MBOX_REG_SIZE 0x130 |
| 178 | static struct resource omap_mbox_resources[] = { | 186 | static struct resource omap4_mbox_resources[] = { |
| 179 | { | 187 | { |
| 180 | .start = OMAP44XX_MAILBOX_BASE, | 188 | .start = OMAP44XX_MAILBOX_BASE, |
| 181 | .end = OMAP44XX_MAILBOX_BASE + | 189 | .end = OMAP44XX_MAILBOX_BASE + |
| @@ -183,10 +191,14 @@ static struct resource omap_mbox_resources[] = { | |||
| 183 | .flags = IORESOURCE_MEM, | 191 | .flags = IORESOURCE_MEM, |
| 184 | }, | 192 | }, |
| 185 | { | 193 | { |
| 186 | .start = INT_44XX_MAIL_U0_MPU, | 194 | .start = OMAP44XX_IRQ_MAIL_U0, |
| 187 | .flags = IORESOURCE_IRQ, | 195 | .flags = IORESOURCE_IRQ, |
| 188 | }, | 196 | }, |
| 189 | }; | 197 | }; |
| 198 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); | ||
| 199 | #else | ||
| 200 | #define omap4_mbox_resources NULL | ||
| 201 | #define omap4_mbox_resources_sz 0 | ||
| 190 | #endif | 202 | #endif |
| 191 | 203 | ||
| 192 | static struct platform_device mbox_device = { | 204 | static struct platform_device mbox_device = { |
| @@ -196,9 +208,15 @@ static struct platform_device mbox_device = { | |||
| 196 | 208 | ||
| 197 | static inline void omap_init_mbox(void) | 209 | static inline void omap_init_mbox(void) |
| 198 | { | 210 | { |
| 199 | if (cpu_is_omap2420() || cpu_is_omap3430() || cpu_is_omap44xx()) { | 211 | if (cpu_is_omap24xx()) { |
| 200 | mbox_device.num_resources = ARRAY_SIZE(omap_mbox_resources); | 212 | mbox_device.resource = omap2_mbox_resources; |
| 201 | mbox_device.resource = omap_mbox_resources; | 213 | mbox_device.num_resources = omap2_mbox_resources_sz; |
| 214 | } else if (cpu_is_omap34xx()) { | ||
| 215 | mbox_device.resource = omap3_mbox_resources; | ||
| 216 | mbox_device.num_resources = omap3_mbox_resources_sz; | ||
| 217 | } else if (cpu_is_omap44xx()) { | ||
| 218 | mbox_device.resource = omap4_mbox_resources; | ||
| 219 | mbox_device.num_resources = omap4_mbox_resources_sz; | ||
| 202 | } else { | 220 | } else { |
| 203 | pr_err("%s: platform not supported\n", __func__); | 221 | pr_err("%s: platform not supported\n", __func__); |
| 204 | return; | 222 | return; |
| @@ -492,7 +510,12 @@ static struct platform_device dummy_pdev = { | |||
| 492 | **/ | 510 | **/ |
| 493 | static void __init omap_hsmmc_reset(void) | 511 | static void __init omap_hsmmc_reset(void) |
| 494 | { | 512 | { |
| 495 | u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : | 513 | u32 i, nr_controllers; |
| 514 | |||
| 515 | if (cpu_is_omap242x()) | ||
| 516 | return; | ||
| 517 | |||
| 518 | nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : | ||
| 496 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); | 519 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); |
| 497 | 520 | ||
| 498 | for (i = 0; i < nr_controllers; i++) { | 521 | for (i = 0; i < nr_controllers; i++) { |
| @@ -697,13 +720,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |||
| 697 | if (!cpu_is_omap44xx()) | 720 | if (!cpu_is_omap44xx()) |
| 698 | return; | 721 | return; |
| 699 | base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; | 722 | base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; |
| 700 | irq = INT_44XX_MMC4_IRQ; | 723 | irq = OMAP44XX_IRQ_MMC4; |
| 701 | break; | 724 | break; |
| 702 | case 4: | 725 | case 4: |
| 703 | if (!cpu_is_omap44xx()) | 726 | if (!cpu_is_omap44xx()) |
| 704 | return; | 727 | return; |
| 705 | base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; | 728 | base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; |
| 706 | irq = INT_44XX_MMC5_IRQ; | 729 | irq = OMAP44XX_IRQ_MMC4; |
| 707 | break; | 730 | break; |
| 708 | default: | 731 | default: |
| 709 | continue; | 732 | continue; |
| @@ -715,7 +738,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |||
| 715 | } else if (cpu_is_omap44xx()) { | 738 | } else if (cpu_is_omap44xx()) { |
| 716 | if (i < 3) { | 739 | if (i < 3) { |
| 717 | base += OMAP4_MMC_REG_OFFSET; | 740 | base += OMAP4_MMC_REG_OFFSET; |
| 718 | irq += IRQ_GIC_START; | 741 | irq += OMAP44XX_IRQ_GIC_START; |
| 719 | } | 742 | } |
| 720 | size = OMAP4_HSMMC_SIZE; | 743 | size = OMAP4_HSMMC_SIZE; |
| 721 | name = "mmci-omap-hs"; | 744 | name = "mmci-omap-hs"; |
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll3xxx.c index f6055b493294..b32ccd954a1b 100644 --- a/arch/arm/mach-omap2/dpll.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
| @@ -1,11 +1,14 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP3/4 - specific DPLL control functions | 2 | * OMAP3/4 - specific DPLL control functions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009 Nokia Corporation | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * Testing and integration fixes by Jouni Högander | 8 | * Testing and integration fixes by Jouni Högander |
| 9 | * | ||
| 10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | ||
| 11 | * Menon | ||
| 9 | * | 12 | * |
| 10 | * Parts of this code are based on code written by | 13 | * Parts of this code are based on code written by |
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | 14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu |
| @@ -15,7 +18,6 @@ | |||
| 15 | * published by the Free Software Foundation. | 18 | * published by the Free Software Foundation. |
| 16 | */ | 19 | */ |
| 17 | 20 | ||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
| 20 | #include <linux/device.h> | 22 | #include <linux/device.h> |
| 21 | #include <linux/list.h> | 23 | #include <linux/list.h> |
| @@ -23,13 +25,10 @@ | |||
| 23 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
| 25 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 26 | #include <linux/limits.h> | ||
| 27 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 28 | 29 | ||
| 29 | #include <plat/cpu.h> | 30 | #include <plat/cpu.h> |
| 30 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
| 31 | #include <plat/sram.h> | ||
| 32 | #include <asm/div64.h> | ||
| 33 | #include <asm/clkdev.h> | 32 | #include <asm/clkdev.h> |
| 34 | 33 | ||
| 35 | #include "clock.h" | 34 | #include "clock.h" |
| @@ -44,17 +43,7 @@ | |||
| 44 | 43 | ||
| 45 | #define MAX_DPLL_WAIT_TRIES 1000000 | 44 | #define MAX_DPLL_WAIT_TRIES 1000000 |
| 46 | 45 | ||
| 47 | 46 | /* Private functions */ | |
| 48 | /** | ||
| 49 | * omap3_dpll_recalc - recalculate DPLL rate | ||
| 50 | * @clk: DPLL struct clk | ||
| 51 | * | ||
| 52 | * Recalculate and propagate the DPLL rate. | ||
| 53 | */ | ||
| 54 | unsigned long omap3_dpll_recalc(struct clk *clk) | ||
| 55 | { | ||
| 56 | return omap2_get_dpll_rate(clk); | ||
| 57 | } | ||
| 58 | 47 | ||
| 59 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | 48 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ |
| 60 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | 49 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) |
| @@ -136,8 +125,6 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | |||
| 136 | return f; | 125 | return f; |
| 137 | } | 126 | } |
| 138 | 127 | ||
| 139 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | ||
| 140 | |||
| 141 | /* | 128 | /* |
| 142 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | 129 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness |
| 143 | * @clk: pointer to a DPLL struct clk | 130 | * @clk: pointer to a DPLL struct clk |
| @@ -238,6 +225,122 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
| 238 | } | 225 | } |
| 239 | 226 | ||
| 240 | /** | 227 | /** |
| 228 | * lookup_dco_sddiv - Set j-type DPLL4 compensation variables | ||
| 229 | * @clk: pointer to a DPLL struct clk | ||
| 230 | * @dco: digital control oscillator selector | ||
| 231 | * @sd_div: target sigma-delta divider | ||
| 232 | * @m: DPLL multiplier to set | ||
| 233 | * @n: DPLL divider to set | ||
| 234 | * | ||
| 235 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | ||
| 236 | * | ||
| 237 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | ||
| 238 | * out in non-multi-OMAP builds for those chips? | ||
| 239 | */ | ||
| 240 | static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, | ||
| 241 | u8 n) | ||
| 242 | { | ||
| 243 | unsigned long fint, clkinp, sd; /* watch out for overflow */ | ||
| 244 | int mod1, mod2; | ||
| 245 | |||
| 246 | clkinp = clk->parent->rate; | ||
| 247 | fint = (clkinp / n) * m; | ||
| 248 | |||
| 249 | if (fint < 1000000000) | ||
| 250 | *dco = 2; | ||
| 251 | else | ||
| 252 | *dco = 4; | ||
| 253 | /* | ||
| 254 | * target sigma-delta to near 250MHz | ||
| 255 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | ||
| 256 | */ | ||
| 257 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | ||
| 258 | mod1 = (clkinp * m) % (250 * n); | ||
| 259 | sd = (clkinp * m) / (250 * n); | ||
| 260 | mod2 = sd % 10; | ||
| 261 | sd /= 10; | ||
| 262 | |||
| 263 | if (mod1 || mod2) | ||
| 264 | sd++; | ||
| 265 | *sd_div = sd; | ||
| 266 | } | ||
| 267 | |||
| 268 | /* | ||
| 269 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | ||
| 270 | * @clk: struct clk * of DPLL to set | ||
| 271 | * @m: DPLL multiplier to set | ||
| 272 | * @n: DPLL divider to set | ||
| 273 | * @freqsel: FREQSEL value to set | ||
| 274 | * | ||
| 275 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | ||
| 276 | * lock.. Returns -EINVAL upon error, or 0 upon success. | ||
| 277 | */ | ||
| 278 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | ||
| 279 | { | ||
| 280 | struct dpll_data *dd = clk->dpll_data; | ||
| 281 | u32 v; | ||
| 282 | |||
| 283 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | ||
| 284 | _omap3_noncore_dpll_bypass(clk); | ||
| 285 | |||
| 286 | /* | ||
| 287 | * Set jitter correction. No jitter correction for OMAP4 and 3630 | ||
| 288 | * since freqsel field is no longer present | ||
| 289 | */ | ||
| 290 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | ||
| 291 | v = __raw_readl(dd->control_reg); | ||
| 292 | v &= ~dd->freqsel_mask; | ||
| 293 | v |= freqsel << __ffs(dd->freqsel_mask); | ||
| 294 | __raw_writel(v, dd->control_reg); | ||
| 295 | } | ||
| 296 | |||
| 297 | /* Set DPLL multiplier, divider */ | ||
| 298 | v = __raw_readl(dd->mult_div1_reg); | ||
| 299 | v &= ~(dd->mult_mask | dd->div1_mask); | ||
| 300 | v |= m << __ffs(dd->mult_mask); | ||
| 301 | v |= (n - 1) << __ffs(dd->div1_mask); | ||
| 302 | |||
| 303 | /* | ||
| 304 | * XXX This code is not needed for 3430/AM35XX; can it be optimized | ||
| 305 | * out in non-multi-OMAP builds for those chips? | ||
| 306 | */ | ||
| 307 | if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) { | ||
| 308 | u8 dco, sd_div; | ||
| 309 | lookup_dco_sddiv(clk, &dco, &sd_div, m, n); | ||
| 310 | /* XXX This probably will need revision for OMAP4 */ | ||
| 311 | v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK | ||
| 312 | | OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | ||
| 313 | v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK); | ||
| 314 | v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | ||
| 315 | } | ||
| 316 | |||
| 317 | __raw_writel(v, dd->mult_div1_reg); | ||
| 318 | |||
| 319 | /* We let the clock framework set the other output dividers later */ | ||
| 320 | |||
| 321 | /* REVISIT: Set ramp-up delay? */ | ||
| 322 | |||
| 323 | _omap3_noncore_dpll_lock(clk); | ||
| 324 | |||
| 325 | return 0; | ||
| 326 | } | ||
| 327 | |||
| 328 | /* Public functions */ | ||
| 329 | |||
| 330 | /** | ||
| 331 | * omap3_dpll_recalc - recalculate DPLL rate | ||
| 332 | * @clk: DPLL struct clk | ||
| 333 | * | ||
| 334 | * Recalculate and propagate the DPLL rate. | ||
| 335 | */ | ||
| 336 | unsigned long omap3_dpll_recalc(struct clk *clk) | ||
| 337 | { | ||
| 338 | return omap2_get_dpll_rate(clk); | ||
| 339 | } | ||
| 340 | |||
| 341 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | ||
| 342 | |||
| 343 | /** | ||
| 241 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | 344 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode |
| 242 | * @clk: pointer to a DPLL struct clk | 345 | * @clk: pointer to a DPLL struct clk |
| 243 | * | 346 | * |
| @@ -292,48 +395,6 @@ void omap3_noncore_dpll_disable(struct clk *clk) | |||
| 292 | 395 | ||
| 293 | /* Non-CORE DPLL rate set code */ | 396 | /* Non-CORE DPLL rate set code */ |
| 294 | 397 | ||
| 295 | /* | ||
| 296 | * omap3_noncore_dpll_program - set non-core DPLL M,N values directly | ||
| 297 | * @clk: struct clk * of DPLL to set | ||
| 298 | * @m: DPLL multiplier to set | ||
| 299 | * @n: DPLL divider to set | ||
| 300 | * @freqsel: FREQSEL value to set | ||
| 301 | * | ||
| 302 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | ||
| 303 | * lock.. Returns -EINVAL upon error, or 0 upon success. | ||
| 304 | */ | ||
| 305 | int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | ||
| 306 | { | ||
| 307 | struct dpll_data *dd = clk->dpll_data; | ||
| 308 | u32 v; | ||
| 309 | |||
| 310 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | ||
| 311 | _omap3_noncore_dpll_bypass(clk); | ||
| 312 | |||
| 313 | /* Set jitter correction */ | ||
| 314 | if (!cpu_is_omap44xx()) { | ||
| 315 | v = __raw_readl(dd->control_reg); | ||
| 316 | v &= ~dd->freqsel_mask; | ||
| 317 | v |= freqsel << __ffs(dd->freqsel_mask); | ||
| 318 | __raw_writel(v, dd->control_reg); | ||
| 319 | } | ||
| 320 | |||
| 321 | /* Set DPLL multiplier, divider */ | ||
| 322 | v = __raw_readl(dd->mult_div1_reg); | ||
| 323 | v &= ~(dd->mult_mask | dd->div1_mask); | ||
| 324 | v |= m << __ffs(dd->mult_mask); | ||
| 325 | v |= (n - 1) << __ffs(dd->div1_mask); | ||
| 326 | __raw_writel(v, dd->mult_div1_reg); | ||
| 327 | |||
| 328 | /* We let the clock framework set the other output dividers later */ | ||
| 329 | |||
| 330 | /* REVISIT: Set ramp-up delay? */ | ||
| 331 | |||
| 332 | _omap3_noncore_dpll_lock(clk); | ||
| 333 | |||
| 334 | return 0; | ||
| 335 | } | ||
| 336 | |||
| 337 | /** | 398 | /** |
| 338 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | 399 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate |
| 339 | * @clk: struct clk * of DPLL to set | 400 | * @clk: struct clk * of DPLL to set |
| @@ -384,8 +445,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |||
| 384 | if (dd->last_rounded_rate == 0) | 445 | if (dd->last_rounded_rate == 0) |
| 385 | return -EINVAL; | 446 | return -EINVAL; |
| 386 | 447 | ||
| 387 | /* No freqsel on OMAP4 */ | 448 | /* No freqsel on OMAP4 and OMAP3630 */ |
| 388 | if (!cpu_is_omap44xx()) { | 449 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { |
| 389 | freqsel = _omap3_dpll_compute_freqsel(clk, | 450 | freqsel = _omap3_dpll_compute_freqsel(clk, |
| 390 | dd->last_rounded_n); | 451 | dd->last_rounded_n); |
| 391 | if (!freqsel) | 452 | if (!freqsel) |
| @@ -530,7 +591,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |||
| 530 | 591 | ||
| 531 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | 592 | v = __raw_readl(dd->control_reg) & dd->enable_mask; |
| 532 | v >>= __ffs(dd->enable_mask); | 593 | v >>= __ffs(dd->enable_mask); |
| 533 | if (v != OMAP3XXX_EN_DPLL_LOCKED) | 594 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
| 534 | rate = clk->parent->rate; | 595 | rate = clk->parent->rate; |
| 535 | else | 596 | else |
| 536 | rate = clk->parent->rate * 2; | 597 | rate = clk->parent->rate * 2; |
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index ec0d984a26fc..9c442e290ccb 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c | |||
| @@ -56,6 +56,9 @@ static struct amba_device omap3_etm_device = { | |||
| 56 | 56 | ||
| 57 | static int __init emu_init(void) | 57 | static int __init emu_init(void) |
| 58 | { | 58 | { |
| 59 | if (!cpu_is_omap34xx()) | ||
| 60 | return -ENODEV; | ||
| 61 | |||
| 59 | amba_device_register(&omap3_etb_device, &iomem_resource); | 62 | amba_device_register(&omap3_etb_device, &iomem_resource); |
| 60 | amba_device_register(&omap3_etm_device, &iomem_resource); | 63 | amba_device_register(&omap3_etm_device, &iomem_resource); |
| 61 | 64 | ||
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c new file mode 100644 index 000000000000..64d74f05abbe --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -0,0 +1,139 @@ | |||
| 1 | /* | ||
| 2 | * gpmc-nand.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments | ||
| 5 | * Vimal Singh <vimalsingh@ti.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | |||
| 16 | #include <asm/mach/flash.h> | ||
| 17 | |||
| 18 | #include <plat/nand.h> | ||
| 19 | #include <plat/board.h> | ||
| 20 | #include <plat/gpmc.h> | ||
| 21 | |||
| 22 | #define WR_RD_PIN_MONITORING 0x00600000 | ||
| 23 | |||
| 24 | static struct omap_nand_platform_data *gpmc_nand_data; | ||
| 25 | |||
| 26 | static struct resource gpmc_nand_resource = { | ||
| 27 | .flags = IORESOURCE_MEM, | ||
| 28 | }; | ||
| 29 | |||
| 30 | static struct platform_device gpmc_nand_device = { | ||
| 31 | .name = "omap2-nand", | ||
| 32 | .id = 0, | ||
| 33 | .num_resources = 1, | ||
| 34 | .resource = &gpmc_nand_resource, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static int omap2_nand_gpmc_retime(void) | ||
| 38 | { | ||
| 39 | struct gpmc_timings t; | ||
| 40 | int err; | ||
| 41 | |||
| 42 | memset(&t, 0, sizeof(t)); | ||
| 43 | t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk); | ||
| 44 | t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); | ||
| 45 | t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); | ||
| 46 | |||
| 47 | /* Read */ | ||
| 48 | t.adv_rd_off = gpmc_round_ns_to_ticks( | ||
| 49 | gpmc_nand_data->gpmc_t->adv_rd_off); | ||
| 50 | t.oe_on = t.adv_on; | ||
| 51 | t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access); | ||
| 52 | t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off); | ||
| 53 | t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off); | ||
| 54 | t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle); | ||
| 55 | |||
| 56 | /* Write */ | ||
| 57 | t.adv_wr_off = gpmc_round_ns_to_ticks( | ||
| 58 | gpmc_nand_data->gpmc_t->adv_wr_off); | ||
| 59 | t.we_on = t.oe_on; | ||
| 60 | if (cpu_is_omap34xx()) { | ||
| 61 | t.wr_data_mux_bus = gpmc_round_ns_to_ticks( | ||
| 62 | gpmc_nand_data->gpmc_t->wr_data_mux_bus); | ||
| 63 | t.wr_access = gpmc_round_ns_to_ticks( | ||
| 64 | gpmc_nand_data->gpmc_t->wr_access); | ||
| 65 | } | ||
| 66 | t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off); | ||
| 67 | t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); | ||
| 68 | t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); | ||
| 69 | |||
| 70 | /* Configure GPMC */ | ||
| 71 | gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, | ||
| 72 | GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | | ||
| 73 | GPMC_CONFIG1_DEVICETYPE_NAND); | ||
| 74 | |||
| 75 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); | ||
| 76 | if (err) | ||
| 77 | return err; | ||
| 78 | |||
| 79 | return 0; | ||
| 80 | } | ||
| 81 | |||
| 82 | static int gpmc_nand_setup(void) | ||
| 83 | { | ||
| 84 | struct device *dev = &gpmc_nand_device.dev; | ||
| 85 | |||
| 86 | /* Set timings in GPMC */ | ||
| 87 | if (omap2_nand_gpmc_retime() < 0) { | ||
| 88 | dev_err(dev, "Unable to set gpmc timings\n"); | ||
| 89 | return -EINVAL; | ||
| 90 | } | ||
| 91 | |||
| 92 | return 0; | ||
| 93 | } | ||
| 94 | |||
| 95 | int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) | ||
| 96 | { | ||
| 97 | unsigned int val; | ||
| 98 | int err = 0; | ||
| 99 | struct device *dev = &gpmc_nand_device.dev; | ||
| 100 | |||
| 101 | gpmc_nand_data = _nand_data; | ||
| 102 | gpmc_nand_data->nand_setup = gpmc_nand_setup; | ||
| 103 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; | ||
| 104 | |||
| 105 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | ||
| 106 | &gpmc_nand_data->phys_base); | ||
| 107 | if (err < 0) { | ||
| 108 | dev_err(dev, "Cannot request GPMC CS\n"); | ||
| 109 | return err; | ||
| 110 | } | ||
| 111 | |||
| 112 | err = gpmc_nand_setup(); | ||
| 113 | if (err < 0) { | ||
| 114 | dev_err(dev, "NAND platform setup failed: %d\n", err); | ||
| 115 | return err; | ||
| 116 | } | ||
| 117 | |||
| 118 | /* Enable RD PIN Monitoring Reg */ | ||
| 119 | if (gpmc_nand_data->dev_ready) { | ||
| 120 | val = gpmc_cs_read_reg(gpmc_nand_data->cs, | ||
| 121 | GPMC_CS_CONFIG1); | ||
| 122 | val |= WR_RD_PIN_MONITORING; | ||
| 123 | gpmc_cs_write_reg(gpmc_nand_data->cs, | ||
| 124 | GPMC_CS_CONFIG1, val); | ||
| 125 | } | ||
| 126 | |||
| 127 | err = platform_device_register(&gpmc_nand_device); | ||
| 128 | if (err < 0) { | ||
| 129 | dev_err(dev, "Unable to register NAND device\n"); | ||
| 130 | goto out_free_cs; | ||
| 131 | } | ||
| 132 | |||
| 133 | return 0; | ||
| 134 | |||
| 135 | out_free_cs: | ||
| 136 | gpmc_cs_free(gpmc_nand_data->cs); | ||
| 137 | |||
| 138 | return err; | ||
| 139 | } | ||
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 7027cdc1ba49..5bc3ca03551c 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -552,9 +552,10 @@ void __init gpmc_init(void) | |||
| 552 | #ifdef CONFIG_ARCH_OMAP3 | 552 | #ifdef CONFIG_ARCH_OMAP3 |
| 553 | static struct omap3_gpmc_regs gpmc_context; | 553 | static struct omap3_gpmc_regs gpmc_context; |
| 554 | 554 | ||
| 555 | void omap3_gpmc_save_context() | 555 | void omap3_gpmc_save_context(void) |
| 556 | { | 556 | { |
| 557 | int i; | 557 | int i; |
| 558 | |||
| 558 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); | 559 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
| 559 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | 560 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); |
| 560 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | 561 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); |
| @@ -583,9 +584,10 @@ void omap3_gpmc_save_context() | |||
| 583 | } | 584 | } |
| 584 | } | 585 | } |
| 585 | 586 | ||
| 586 | void omap3_gpmc_restore_context() | 587 | void omap3_gpmc_restore_context(void) |
| 587 | { | 588 | { |
| 588 | int i; | 589 | int i; |
| 590 | |||
| 589 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); | 591 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
| 590 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | 592 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); |
| 591 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | 593 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); |
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c new file mode 100644 index 000000000000..9ad229594b46 --- /dev/null +++ b/arch/arm/mach-omap2/hsmmc.c | |||
| @@ -0,0 +1,266 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/hsmmc.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2008 Texas Instruments | ||
| 5 | * Copyright (C) 2008 Nokia Corporation | ||
| 6 | * Author: Texas Instruments | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/slab.h> | ||
| 14 | #include <linux/string.h> | ||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <plat/control.h> | ||
| 18 | #include <plat/mmc.h> | ||
| 19 | #include <plat/omap-pm.h> | ||
| 20 | |||
| 21 | #include "hsmmc.h" | ||
| 22 | |||
| 23 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | ||
| 24 | |||
| 25 | static u16 control_pbias_offset; | ||
| 26 | static u16 control_devconf1_offset; | ||
| 27 | |||
| 28 | #define HSMMC_NAME_LEN 9 | ||
| 29 | |||
| 30 | static struct hsmmc_controller { | ||
| 31 | char name[HSMMC_NAME_LEN + 1]; | ||
| 32 | } hsmmc[OMAP34XX_NR_MMC]; | ||
| 33 | |||
| 34 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | ||
| 35 | |||
| 36 | static int hsmmc_get_context_loss(struct device *dev) | ||
| 37 | { | ||
| 38 | return omap_pm_get_dev_context_loss_count(dev); | ||
| 39 | } | ||
| 40 | |||
| 41 | #else | ||
| 42 | #define hsmmc_get_context_loss NULL | ||
| 43 | #endif | ||
| 44 | |||
| 45 | static void hsmmc1_before_set_reg(struct device *dev, int slot, | ||
| 46 | int power_on, int vdd) | ||
| 47 | { | ||
| 48 | u32 reg, prog_io; | ||
| 49 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 50 | |||
| 51 | if (mmc->slots[0].remux) | ||
| 52 | mmc->slots[0].remux(dev, slot, power_on); | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | ||
| 56 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both | ||
| 57 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | ||
| 58 | * | ||
| 59 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | ||
| 60 | * is most naturally TWL VSIM; those pins also use PBIAS. | ||
| 61 | * | ||
| 62 | * FIXME handle VMMC1A as needed ... | ||
| 63 | */ | ||
| 64 | if (power_on) { | ||
| 65 | if (cpu_is_omap2430()) { | ||
| 66 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | ||
| 67 | if ((1 << vdd) >= MMC_VDD_30_31) | ||
| 68 | reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; | ||
| 69 | else | ||
| 70 | reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; | ||
| 71 | omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); | ||
| 72 | } | ||
| 73 | |||
| 74 | if (mmc->slots[0].internal_clock) { | ||
| 75 | reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 76 | reg |= OMAP2_MMCSDIO1ADPCLKISEL; | ||
| 77 | omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); | ||
| 78 | } | ||
| 79 | |||
| 80 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 81 | if (cpu_is_omap3630()) { | ||
| 82 | /* Set MMC I/O to 52Mhz */ | ||
| 83 | prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | ||
| 84 | prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; | ||
| 85 | omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); | ||
| 86 | } else { | ||
| 87 | reg |= OMAP2_PBIASSPEEDCTRL0; | ||
| 88 | } | ||
| 89 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | ||
| 90 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 91 | } else { | ||
| 92 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 93 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | ||
| 94 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 95 | } | ||
| 96 | } | ||
| 97 | |||
| 98 | static void hsmmc1_after_set_reg(struct device *dev, int slot, | ||
| 99 | int power_on, int vdd) | ||
| 100 | { | ||
| 101 | u32 reg; | ||
| 102 | |||
| 103 | /* 100ms delay required for PBIAS configuration */ | ||
| 104 | msleep(100); | ||
| 105 | |||
| 106 | if (power_on) { | ||
| 107 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 108 | reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); | ||
| 109 | if ((1 << vdd) <= MMC_VDD_165_195) | ||
| 110 | reg &= ~OMAP2_PBIASLITEVMODE0; | ||
| 111 | else | ||
| 112 | reg |= OMAP2_PBIASLITEVMODE0; | ||
| 113 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 114 | } else { | ||
| 115 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 116 | reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | | ||
| 117 | OMAP2_PBIASLITEVMODE0); | ||
| 118 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 119 | } | ||
| 120 | } | ||
| 121 | |||
| 122 | static void hsmmc23_before_set_reg(struct device *dev, int slot, | ||
| 123 | int power_on, int vdd) | ||
| 124 | { | ||
| 125 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 126 | |||
| 127 | if (mmc->slots[0].remux) | ||
| 128 | mmc->slots[0].remux(dev, slot, power_on); | ||
| 129 | |||
| 130 | if (power_on) { | ||
| 131 | /* Only MMC2 supports a CLKIN */ | ||
| 132 | if (mmc->slots[0].internal_clock) { | ||
| 133 | u32 reg; | ||
| 134 | |||
| 135 | reg = omap_ctrl_readl(control_devconf1_offset); | ||
| 136 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; | ||
| 137 | omap_ctrl_writel(reg, control_devconf1_offset); | ||
| 138 | } | ||
| 139 | } | ||
| 140 | } | ||
| 141 | |||
| 142 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; | ||
| 143 | |||
| 144 | void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) | ||
| 145 | { | ||
| 146 | struct omap2_hsmmc_info *c; | ||
| 147 | int nr_hsmmc = ARRAY_SIZE(hsmmc_data); | ||
| 148 | int i; | ||
| 149 | |||
| 150 | if (cpu_is_omap2430()) { | ||
| 151 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | ||
| 152 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | ||
| 153 | } else { | ||
| 154 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | ||
| 155 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | ||
| 156 | } | ||
| 157 | |||
| 158 | for (c = controllers; c->mmc; c++) { | ||
| 159 | struct hsmmc_controller *hc = hsmmc + c->mmc - 1; | ||
| 160 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | ||
| 161 | |||
| 162 | if (!c->mmc || c->mmc > nr_hsmmc) { | ||
| 163 | pr_debug("MMC%d: no such controller\n", c->mmc); | ||
| 164 | continue; | ||
| 165 | } | ||
| 166 | if (mmc) { | ||
| 167 | pr_debug("MMC%d: already configured\n", c->mmc); | ||
| 168 | continue; | ||
| 169 | } | ||
| 170 | |||
| 171 | mmc = kzalloc(sizeof(struct omap_mmc_platform_data), | ||
| 172 | GFP_KERNEL); | ||
| 173 | if (!mmc) { | ||
| 174 | pr_err("Cannot allocate memory for mmc device!\n"); | ||
| 175 | goto done; | ||
| 176 | } | ||
| 177 | |||
| 178 | if (c->name) | ||
| 179 | strncpy(hc->name, c->name, HSMMC_NAME_LEN); | ||
| 180 | else | ||
| 181 | snprintf(hc->name, ARRAY_SIZE(hc->name), | ||
| 182 | "mmc%islot%i", c->mmc, 1); | ||
| 183 | mmc->slots[0].name = hc->name; | ||
| 184 | mmc->nr_slots = 1; | ||
| 185 | mmc->slots[0].wires = c->wires; | ||
| 186 | mmc->slots[0].internal_clock = !c->ext_clock; | ||
| 187 | mmc->dma_mask = 0xffffffff; | ||
| 188 | |||
| 189 | mmc->get_context_loss_count = hsmmc_get_context_loss; | ||
| 190 | |||
| 191 | mmc->slots[0].switch_pin = c->gpio_cd; | ||
| 192 | mmc->slots[0].gpio_wp = c->gpio_wp; | ||
| 193 | |||
| 194 | mmc->slots[0].remux = c->remux; | ||
| 195 | |||
| 196 | if (c->cover_only) | ||
| 197 | mmc->slots[0].cover = 1; | ||
| 198 | |||
| 199 | if (c->nonremovable) | ||
| 200 | mmc->slots[0].nonremovable = 1; | ||
| 201 | |||
| 202 | if (c->power_saving) | ||
| 203 | mmc->slots[0].power_saving = 1; | ||
| 204 | |||
| 205 | if (c->no_off) | ||
| 206 | mmc->slots[0].no_off = 1; | ||
| 207 | |||
| 208 | if (c->vcc_aux_disable_is_sleep) | ||
| 209 | mmc->slots[0].vcc_aux_disable_is_sleep = 1; | ||
| 210 | |||
| 211 | /* NOTE: MMC slots should have a Vcc regulator set up. | ||
| 212 | * This may be from a TWL4030-family chip, another | ||
| 213 | * controllable regulator, or a fixed supply. | ||
| 214 | * | ||
| 215 | * temporary HACK: ocr_mask instead of fixed supply | ||
| 216 | */ | ||
| 217 | mmc->slots[0].ocr_mask = c->ocr_mask; | ||
| 218 | |||
| 219 | switch (c->mmc) { | ||
| 220 | case 1: | ||
| 221 | /* on-chip level shifting via PBIAS0/PBIAS1 */ | ||
| 222 | mmc->slots[0].before_set_reg = hsmmc1_before_set_reg; | ||
| 223 | mmc->slots[0].after_set_reg = hsmmc1_after_set_reg; | ||
| 224 | |||
| 225 | /* Omap3630 HSMMC1 supports only 4-bit */ | ||
| 226 | if (cpu_is_omap3630() && c->wires > 4) { | ||
| 227 | c->wires = 4; | ||
| 228 | mmc->slots[0].wires = c->wires; | ||
| 229 | } | ||
| 230 | break; | ||
| 231 | case 2: | ||
| 232 | if (c->ext_clock) | ||
| 233 | c->transceiver = 1; | ||
| 234 | if (c->transceiver && c->wires > 4) | ||
| 235 | c->wires = 4; | ||
| 236 | /* FALLTHROUGH */ | ||
| 237 | case 3: | ||
| 238 | /* off-chip level shifting, or none */ | ||
| 239 | mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; | ||
| 240 | mmc->slots[0].after_set_reg = NULL; | ||
| 241 | break; | ||
| 242 | default: | ||
| 243 | pr_err("MMC%d configuration not supported!\n", c->mmc); | ||
| 244 | kfree(mmc); | ||
| 245 | continue; | ||
| 246 | } | ||
| 247 | hsmmc_data[c->mmc - 1] = mmc; | ||
| 248 | } | ||
| 249 | |||
| 250 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); | ||
| 251 | |||
| 252 | /* pass the device nodes back to board setup code */ | ||
| 253 | for (c = controllers; c->mmc; c++) { | ||
| 254 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | ||
| 255 | |||
| 256 | if (!c->mmc || c->mmc > nr_hsmmc) | ||
| 257 | continue; | ||
| 258 | c->dev = mmc->dev; | ||
| 259 | } | ||
| 260 | |||
| 261 | done: | ||
| 262 | for (i = 0; i < nr_hsmmc; i++) | ||
| 263 | kfree(hsmmc_data[i]); | ||
| 264 | } | ||
| 265 | |||
| 266 | #endif | ||
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/hsmmc.h index a47e68563fb6..36f0ba8d89e2 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.h +++ b/arch/arm/mach-omap2/hsmmc.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | struct twl4030_hsmmc_info { | 9 | struct omap2_hsmmc_info { |
| 10 | u8 mmc; /* controller 1/2/3 */ | 10 | u8 mmc; /* controller 1/2/3 */ |
| 11 | u8 wires; /* 1/4/8 wires */ | 11 | u8 wires; /* 1/4/8 wires */ |
| 12 | bool transceiver; /* MMC-2 option */ | 12 | bool transceiver; /* MMC-2 option */ |
| @@ -14,22 +14,24 @@ struct twl4030_hsmmc_info { | |||
| 14 | bool cover_only; /* No card detect - just cover switch */ | 14 | bool cover_only; /* No card detect - just cover switch */ |
| 15 | bool nonremovable; /* Nonremovable e.g. eMMC */ | 15 | bool nonremovable; /* Nonremovable e.g. eMMC */ |
| 16 | bool power_saving; /* Try to sleep or power off when possible */ | 16 | bool power_saving; /* Try to sleep or power off when possible */ |
| 17 | bool no_off; /* power_saving and power is not to go off */ | ||
| 18 | bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */ | ||
| 17 | int gpio_cd; /* or -EINVAL */ | 19 | int gpio_cd; /* or -EINVAL */ |
| 18 | int gpio_wp; /* or -EINVAL */ | 20 | int gpio_wp; /* or -EINVAL */ |
| 19 | char *name; /* or NULL for default */ | 21 | char *name; /* or NULL for default */ |
| 20 | struct device *dev; /* returned: pointer to mmc adapter */ | 22 | struct device *dev; /* returned: pointer to mmc adapter */ |
| 21 | int ocr_mask; /* temporary HACK */ | 23 | int ocr_mask; /* temporary HACK */ |
| 24 | /* Remux (pad configuation) when powering on/off */ | ||
| 25 | void (*remux)(struct device *dev, int slot, int power_on); | ||
| 22 | }; | 26 | }; |
| 23 | 27 | ||
| 24 | #if defined(CONFIG_REGULATOR) && \ | 28 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
| 25 | (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ | ||
| 26 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) | ||
| 27 | 29 | ||
| 28 | void twl4030_mmc_init(struct twl4030_hsmmc_info *); | 30 | void omap2_hsmmc_init(struct omap2_hsmmc_info *); |
| 29 | 31 | ||
| 30 | #else | 32 | #else |
| 31 | 33 | ||
| 32 | static inline void twl4030_mmc_init(struct twl4030_hsmmc_info *info) | 34 | static inline void omap2_hsmmc_init(struct omap2_hsmmc_info *info) |
| 33 | { | 35 | { |
| 34 | } | 36 | } |
| 35 | 37 | ||
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index 789ca8c02f0c..7951ae1447ee 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c | |||
| @@ -25,9 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include "mux.h" | 26 | #include "mux.h" |
| 27 | 27 | ||
| 28 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | 28 | void __init omap2_i2c_mux_pins(int bus_id) |
| 29 | struct i2c_board_info const *info, | ||
| 30 | unsigned len) | ||
| 31 | { | 29 | { |
| 32 | if (cpu_is_omap24xx()) { | 30 | if (cpu_is_omap24xx()) { |
| 33 | const int omap24xx_pins[][2] = { | 31 | const int omap24xx_pins[][2] = { |
| @@ -51,6 +49,4 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 51 | sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); | 49 | sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); |
| 52 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); | 50 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); |
| 53 | } | 51 | } |
| 54 | |||
| 55 | return omap_plat_register_i2c_bus(bus_id, clkrate, info, len); | ||
| 56 | } | 52 | } |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 3d65c50bd017..37b8a1a4adf8 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -57,6 +57,8 @@ int omap_type(void) | |||
| 57 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); | 57 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
| 58 | } else if (cpu_is_omap34xx()) { | 58 | } else if (cpu_is_omap34xx()) { |
| 59 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); | 59 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
| 60 | } else if (cpu_is_omap44xx()) { | ||
| 61 | val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); | ||
| 60 | } else { | 62 | } else { |
| 61 | pr_err("Cannot detect omap type!\n"); | 63 | pr_err("Cannot detect omap type!\n"); |
| 62 | goto out; | 64 | goto out; |
| @@ -175,6 +177,8 @@ void __init omap3_check_features(void) | |||
| 175 | OMAP3_CHECK_FEATURE(status, SGX); | 177 | OMAP3_CHECK_FEATURE(status, SGX); |
| 176 | OMAP3_CHECK_FEATURE(status, NEON); | 178 | OMAP3_CHECK_FEATURE(status, NEON); |
| 177 | OMAP3_CHECK_FEATURE(status, ISP); | 179 | OMAP3_CHECK_FEATURE(status, ISP); |
| 180 | if (cpu_is_omap3630()) | ||
| 181 | omap3_features |= OMAP3_HAS_192MHZ_CLK; | ||
| 178 | 182 | ||
| 179 | /* | 183 | /* |
| 180 | * TODO: Get additional info (where applicable) | 184 | * TODO: Get additional info (where applicable) |
| @@ -281,6 +285,7 @@ void __init omap4_check_revision(void) | |||
| 281 | 285 | ||
| 282 | if ((hawkeye == 0xb852) && (rev == 0x0)) { | 286 | if ((hawkeye == 0xb852) && (rev == 0x0)) { |
| 283 | omap_revision = OMAP4430_REV_ES1_0; | 287 | omap_revision = OMAP4430_REV_ES1_0; |
| 288 | omap_chip.oc |= CHIP_IS_OMAP4430ES1; | ||
| 284 | pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); | 289 | pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); |
| 285 | return; | 290 | return; |
| 286 | } | 291 | } |
| @@ -358,6 +363,7 @@ void __init omap3_cpuinfo(void) | |||
| 358 | OMAP3_SHOW_FEATURE(sgx); | 363 | OMAP3_SHOW_FEATURE(sgx); |
| 359 | OMAP3_SHOW_FEATURE(neon); | 364 | OMAP3_SHOW_FEATURE(neon); |
| 360 | OMAP3_SHOW_FEATURE(isp); | 365 | OMAP3_SHOW_FEATURE(isp); |
| 366 | OMAP3_SHOW_FEATURE(192mhz_clk); | ||
| 361 | 367 | ||
| 362 | printk(")\n"); | 368 | printk(")\n"); |
| 363 | } | 369 | } |
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h new file mode 100644 index 000000000000..a705f946fc46 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/am35xx.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /*: | ||
| 2 | * Address mappings and base address for AM35XX specific interconnects | ||
| 3 | * and peripherals. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2009 Texas Instruments | ||
| 6 | * | ||
| 7 | * Author: Sriramakrishnan <srk@ti.com> | ||
| 8 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | #ifndef __ASM_ARCH_AM35XX_H | ||
| 15 | #define __ASM_ARCH_AM35XX_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Base addresses | ||
| 19 | * Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules | ||
| 20 | */ | ||
| 21 | #define AM35XX_IPSS_EMAC_BASE 0x5C000000 | ||
| 22 | #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 | ||
| 23 | #define AM35XX_IPSS_HECC_BASE 0x5C050000 | ||
| 24 | #define AM35XX_IPSS_VPFE_BASE 0x5C060000 | ||
| 25 | |||
| 26 | #endif /* __ASM_ARCH_AM35XX_H */ | ||
diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-sdp.h new file mode 100644 index 000000000000..465169c0908a --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/board-sdp.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * board-sdp.h | ||
| 3 | * | ||
| 4 | * Information structures for SDP-specific board config data | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 Nokia Corporation | ||
| 7 | * Copyright (C) 2009 Texas Instruments | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | #include <linux/mtd/mtd.h> | ||
| 14 | #include <linux/mtd/partitions.h> | ||
| 15 | |||
| 16 | struct flash_partitions { | ||
| 17 | struct mtd_partition *parts; | ||
| 18 | int nr_parts; | ||
| 19 | }; | ||
| 20 | |||
| 21 | extern void sdp_flash_init(struct flash_partitions []); | ||
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 86979d7bd871..4a63a2ea484d 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S | |||
| @@ -11,32 +11,107 @@ | |||
| 11 | * | 11 | * |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/serial_reg.h> | ||
| 15 | |||
| 16 | #include <plat/serial.h> | ||
| 17 | |||
| 18 | #define UART_OFFSET(addr) ((addr) & 0x00ffffff) | ||
| 19 | |||
| 20 | .pushsection .data | ||
| 21 | omap_uart_phys: .word 0 | ||
| 22 | omap_uart_virt: .word 0 | ||
| 23 | omap_uart_lsr: .word 0 | ||
| 24 | .popsection | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Note that this code won't work if the bootloader passes | ||
| 28 | * a wrong machine ID number in r1. To debug, just hardcode | ||
| 29 | * the desired UART phys and virt addresses temporarily into | ||
| 30 | * the omap_uart_phys and omap_uart_virt above. | ||
| 31 | */ | ||
| 14 | .macro addruart, rx, tmp | 32 | .macro addruart, rx, tmp |
| 33 | |||
| 34 | /* Use omap_uart_phys/virt if already configured */ | ||
| 35 | 10: mrc p15, 0, \rx, c1, c0 | ||
| 36 | tst \rx, #1 @ MMU enabled? | ||
| 37 | ldreq \rx, =omap_uart_phys @ physical base address | ||
| 38 | ldrne \rx, =omap_uart_virt @ virtual base address | ||
| 39 | ldr \rx, [\rx, #0] | ||
| 40 | cmp \rx, #0 @ is port configured? | ||
| 41 | bne 99f @ already configured | ||
| 42 | |||
| 43 | /* Check UART1 scratchpad register for uart to use */ | ||
| 15 | mrc p15, 0, \rx, c1, c0 | 44 | mrc p15, 0, \rx, c1, c0 |
| 16 | tst \rx, #1 @ MMU enabled? | 45 | tst \rx, #1 @ MMU enabled? |
| 17 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 18 | moveq \rx, #0x48000000 @ physical base address | 46 | moveq \rx, #0x48000000 @ physical base address |
| 19 | movne \rx, #0xfa000000 @ virtual base | 47 | movne \rx, #0xfa000000 @ virtual base |
| 20 | orr \rx, \rx, #0x0006a000 | 48 | orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4 |
| 21 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 | 49 | ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad |
| 22 | add \rx, \rx, #0x00002000 @ UART 2 | 50 | |
| 23 | #endif | 51 | /* Select the UART to use based on the UART1 scratchpad value */ |
| 24 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | 52 | cmp \rx, #0 @ no port configured? |
| 25 | add \rx, \rx, #0x00004000 @ UART 3 | 53 | beq 21f @ if none, try to use UART1 |
| 26 | #endif | 54 | cmp \rx, #OMAP2UART1 @ OMAP2/3/4UART1 |
| 27 | 55 | beq 21f @ configure OMAP2/3/4UART1 | |
| 28 | #elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | 56 | cmp \rx, #OMAP2UART2 @ OMAP2/3/4UART2 |
| 29 | moveq \rx, #0x48000000 @ physical base address | 57 | beq 22f @ configure OMAP2/3/4UART2 |
| 30 | movne \rx, #0xfa000000 @ virtual base | 58 | cmp \rx, #OMAP2UART3 @ only on 24xx |
| 31 | orr \rx, \rx, #0x0006a000 | 59 | beq 23f @ configure OMAP2UART3 |
| 32 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 | 60 | cmp \rx, #OMAP3UART3 @ only on 34xx |
| 33 | add \rx, \rx, #0x00002000 @ UART 2 | 61 | beq 33f @ configure OMAP3UART3 |
| 34 | #endif | 62 | cmp \rx, #OMAP4UART3 @ only on 44xx |
| 35 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | 63 | beq 43f @ configure OMAP4UART3 |
| 36 | add \rx, \rx, #0x00fb0000 @ UART 3 | 64 | cmp \rx, #OMAP3UART4 @ only on 36xx |
| 37 | add \rx, \rx, #0x00006000 | 65 | beq 34f @ configure OMAP3UART4 |
| 38 | #endif | 66 | cmp \rx, #OMAP4UART4 @ only on 44xx |
| 39 | #endif | 67 | beq 44f @ configure OMAP4UART4 |
| 68 | cmp \rx, #ZOOM_UART @ only on zoom2/3 | ||
| 69 | beq 95f @ configure ZOOM_UART | ||
| 70 | |||
| 71 | /* Configure the UART offset from the phys/virt base */ | ||
| 72 | 21: mov \rx, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4 | ||
| 73 | b 98f | ||
| 74 | 22: mov \rx, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4 | ||
| 75 | b 98f | ||
| 76 | 23: mov \rx, #UART_OFFSET(OMAP2_UART3_BASE) | ||
| 77 | b 98f | ||
| 78 | 33: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE) | ||
| 79 | add \rx, \rx, #0x00fb0000 | ||
| 80 | add \rx, \rx, #0x00006000 @ OMAP3_UART3_BASE | ||
| 81 | b 98f | ||
| 82 | 34: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE) | ||
| 83 | add \rx, \rx, #0x00fb0000 | ||
| 84 | add \rx, \rx, #0x00028000 @ OMAP3_UART4_BASE | ||
| 85 | b 98f | ||
| 86 | 43: mov \rx, #UART_OFFSET(OMAP4_UART3_BASE) | ||
| 87 | b 98f | ||
| 88 | 44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) | ||
| 89 | b 98f | ||
| 90 | 95: mov \rx, #ZOOM_UART_BASE | ||
| 91 | ldr \tmp, =omap_uart_phys | ||
| 92 | str \rx, [\tmp, #0] | ||
| 93 | mov \rx, #ZOOM_UART_VIRT | ||
| 94 | ldr \tmp, =omap_uart_virt | ||
| 95 | str \rx, [\tmp, #0] | ||
| 96 | mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) | ||
| 97 | ldr \tmp, =omap_uart_lsr | ||
| 98 | str \rx, [\tmp, #0] | ||
| 99 | b 10b | ||
| 100 | |||
| 101 | /* Store both phys and virt address for the uart */ | ||
| 102 | 98: add \rx, \rx, #0x48000000 @ phys base | ||
| 103 | ldr \tmp, =omap_uart_phys | ||
| 104 | str \rx, [\tmp, #0] | ||
| 105 | sub \rx, \rx, #0x48000000 @ phys base | ||
| 106 | add \rx, \rx, #0xfa000000 @ virt base | ||
| 107 | ldr \tmp, =omap_uart_virt | ||
| 108 | str \rx, [\tmp, #0] | ||
| 109 | mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) | ||
| 110 | ldr \tmp, =omap_uart_lsr | ||
| 111 | str \rx, [\tmp, #0] | ||
| 112 | |||
| 113 | b 10b | ||
| 114 | 99: | ||
| 40 | .endm | 115 | .endm |
| 41 | 116 | ||
| 42 | .macro senduart,rd,rx | 117 | .macro senduart,rd,rx |
| @@ -44,15 +119,12 @@ | |||
| 44 | .endm | 119 | .endm |
| 45 | 120 | ||
| 46 | .macro busyuart,rd,rx | 121 | .macro busyuart,rd,rx |
| 47 | 1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends | 122 | 1001: ldr \rd, =omap_uart_lsr |
| 48 | and \rd, \rd, #0x60 | 123 | ldr \rd, [\rd, #0] |
| 49 | teq \rd, #0x60 | 124 | ldrb \rd, [\rx, \rd] |
| 50 | beq 1002f | 125 | and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
| 51 | ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only | 126 | teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
| 52 | and \rd, \rd, #0x60 | ||
| 53 | teq \rd, #0x60 | ||
| 54 | bne 1001b | 127 | bne 1001b |
| 55 | 1002: | ||
| 56 | .endm | 128 | .endm |
| 57 | 129 | ||
| 58 | .macro waituart,rd,rx | 130 | .macro waituart,rd,rx |
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index c7f1720bf282..ff25c7e4e606 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S | |||
| @@ -17,46 +17,134 @@ | |||
| 17 | 17 | ||
| 18 | #include <plat/omap24xx.h> | 18 | #include <plat/omap24xx.h> |
| 19 | #include <plat/omap34xx.h> | 19 | #include <plat/omap34xx.h> |
| 20 | |||
| 21 | /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ | ||
| 22 | #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) | ||
| 23 | #define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) | ||
| 24 | #elif defined(CONFIG_ARCH_OMAP34XX) | ||
| 25 | #define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | ||
| 26 | #endif | ||
| 27 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 28 | #include <plat/omap44xx.h> | 20 | #include <plat/omap44xx.h> |
| 29 | #endif | 21 | |
| 30 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ | 22 | #include <plat/multi.h> |
| 31 | #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ | 23 | |
| 24 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) | ||
| 25 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | ||
| 26 | #define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | ||
| 27 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ | ||
| 28 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ | ||
| 32 | 29 | ||
| 33 | .macro disable_fiq | 30 | .macro disable_fiq |
| 34 | .endm | 31 | .endm |
| 35 | 32 | ||
| 36 | .macro get_irqnr_preamble, base, tmp | 33 | .macro arch_ret_to_user, tmp1, tmp2 |
| 37 | .endm | 34 | .endm |
| 38 | 35 | ||
| 39 | .macro arch_ret_to_user, tmp1, tmp2 | 36 | /* |
| 37 | * Unoptimized irq functions for multi-omap2, 3 and 4 | ||
| 38 | */ | ||
| 39 | |||
| 40 | #ifdef MULTI_OMAP2 | ||
| 41 | .pushsection .data | ||
| 42 | omap_irq_base: .word 0 | ||
| 43 | .popsection | ||
| 44 | |||
| 45 | /* Configure the interrupt base on the first interrupt */ | ||
| 46 | .macro get_irqnr_preamble, base, tmp | ||
| 47 | 9: | ||
| 48 | ldr \base, =omap_irq_base @ irq base address | ||
| 49 | ldr \base, [\base, #0] @ irq base value | ||
| 50 | cmp \base, #0 @ already configured? | ||
| 51 | bne 9997f @ nothing to do | ||
| 52 | |||
| 53 | mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision | ||
| 54 | and \tmp, \tmp, #0x000f0000 @ only check architecture | ||
| 55 | cmp \tmp, #0x00060000 @ is v6? | ||
| 56 | beq 2400f @ found v6 so it's omap24xx | ||
| 57 | mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision | ||
| 58 | and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9 | ||
| 59 | cmp \tmp, #0x00000080 @ cortex A-8? | ||
| 60 | beq 3400f @ found A-8 so it's omap34xx | ||
| 61 | cmp \tmp, #0x00000090 @ cortex A-9? | ||
| 62 | beq 4400f @ found A-9 so it's omap44xx | ||
| 63 | 2400: ldr \base, =OMAP2_IRQ_BASE | ||
| 64 | ldr \tmp, =omap_irq_base | ||
| 65 | str \base, [\tmp, #0] | ||
| 66 | b 9b | ||
| 67 | 3400: ldr \base, =OMAP3_IRQ_BASE | ||
| 68 | ldr \tmp, =omap_irq_base | ||
| 69 | str \base, [\tmp, #0] | ||
| 70 | b 9b | ||
| 71 | 4400: ldr \base, =OMAP4_IRQ_BASE | ||
| 72 | ldr \tmp, =omap_irq_base | ||
| 73 | str \base, [\tmp, #0] | ||
| 74 | b 9b | ||
| 75 | 9997: | ||
| 40 | .endm | 76 | .endm |
| 41 | 77 | ||
| 42 | #ifndef CONFIG_ARCH_OMAP4 | 78 | /* Check the pending interrupts. Note that base already set */ |
| 43 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 79 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 44 | ldr \base, =OMAP2_VA_IC_BASE | 80 | tst \base, #0x100 @ gic address? |
| 81 | bne 4401f @ found gic | ||
| 82 | |||
| 83 | /* Handle omap2 and omap3 */ | ||
| 45 | ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ | 84 | ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ |
| 46 | cmp \irqnr, #0x0 | 85 | cmp \irqnr, #0x0 |
| 47 | bne 2222f | 86 | bne 9998f |
| 48 | ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ | 87 | ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ |
| 49 | cmp \irqnr, #0x0 | 88 | cmp \irqnr, #0x0 |
| 50 | bne 2222f | 89 | bne 9998f |
| 51 | ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ | 90 | ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ |
| 52 | cmp \irqnr, #0x0 | 91 | cmp \irqnr, #0x0 |
| 53 | 2222: | 92 | 9998: |
| 54 | ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] | 93 | ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] |
| 55 | and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ | 94 | and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ |
| 95 | b 9999f | ||
| 56 | 96 | ||
| 97 | /* Handle omap4 */ | ||
| 98 | 4401: ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
| 99 | ldr \tmp, =1021 | ||
| 100 | bic \irqnr, \irqstat, #0x1c00 | ||
| 101 | cmp \irqnr, #29 | ||
| 102 | cmpcc \irqnr, \irqnr | ||
| 103 | cmpne \irqnr, \tmp | ||
| 104 | cmpcs \irqnr, \irqnr | ||
| 105 | 9999: | ||
| 57 | .endm | 106 | .endm |
| 107 | |||
| 108 | |||
| 109 | #else /* MULTI_OMAP2 */ | ||
| 110 | |||
| 111 | |||
| 112 | /* | ||
| 113 | * Optimized irq functions for omap2, 3 and 4 | ||
| 114 | */ | ||
| 115 | |||
| 116 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 117 | .macro get_irqnr_preamble, base, tmp | ||
| 118 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 119 | ldr \base, =OMAP2_IRQ_BASE | ||
| 58 | #else | 120 | #else |
| 59 | #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | 121 | ldr \base, =OMAP3_IRQ_BASE |
| 122 | #endif | ||
| 123 | .endm | ||
| 124 | |||
| 125 | /* Check the pending interrupts. Note that base already set */ | ||
| 126 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 127 | ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ | ||
| 128 | cmp \irqnr, #0x0 | ||
| 129 | bne 9999f | ||
| 130 | ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ | ||
| 131 | cmp \irqnr, #0x0 | ||
| 132 | bne 9999f | ||
| 133 | ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ | ||
| 134 | cmp \irqnr, #0x0 | ||
| 135 | 9999: | ||
| 136 | ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] | ||
| 137 | and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ | ||
| 138 | |||
| 139 | .endm | ||
| 140 | #endif | ||
| 141 | |||
| 142 | |||
| 143 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 144 | |||
| 145 | .macro get_irqnr_preamble, base, tmp | ||
| 146 | ldr \base, =OMAP4_IRQ_BASE | ||
| 147 | .endm | ||
| 60 | 148 | ||
| 61 | /* | 149 | /* |
| 62 | * The interrupt numbering scheme is defined in the | 150 | * The interrupt numbering scheme is defined in the |
| @@ -78,7 +166,6 @@ | |||
| 78 | * valid range for an IRQ (30-1020 inclusive). | 166 | * valid range for an IRQ (30-1020 inclusive). |
| 79 | */ | 167 | */ |
| 80 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 168 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 81 | ldr \base, =OMAP44XX_VA_GIC_CPU_BASE | ||
| 82 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | 169 | ldr \irqstat, [\base, #GIC_CPU_INTACK] |
| 83 | 170 | ||
| 84 | ldr \tmp, =1021 | 171 | ldr \tmp, =1021 |
| @@ -119,6 +206,7 @@ | |||
| 119 | cmp \tmp, #0 | 206 | cmp \tmp, #0 |
| 120 | .endm | 207 | .endm |
| 121 | #endif | 208 | #endif |
| 209 | #endif /* MULTI_OMAP2 */ | ||
| 122 | 210 | ||
| 123 | .macro irq_prio_table | 211 | .macro irq_prio_table |
| 124 | .endm | 212 | .endm |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5a7996402c53..402e8f0d0f21 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -35,7 +35,9 @@ | |||
| 35 | #include <plat/serial.h> | 35 | #include <plat/serial.h> |
| 36 | #include <plat/vram.h> | 36 | #include <plat/vram.h> |
| 37 | 37 | ||
| 38 | #include "clock.h" | 38 | #include "clock2xxx.h" |
| 39 | #include "clock3xxx.h" | ||
| 40 | #include "clock44xx.h" | ||
| 39 | 41 | ||
| 40 | #include <plat/omap-pm.h> | 42 | #include <plat/omap-pm.h> |
| 41 | #include <plat/powerdomain.h> | 43 | #include <plat/powerdomain.h> |
| @@ -44,16 +46,13 @@ | |||
| 44 | #include <plat/clockdomain.h> | 46 | #include <plat/clockdomain.h> |
| 45 | #include "clockdomains.h" | 47 | #include "clockdomains.h" |
| 46 | #include <plat/omap_hwmod.h> | 48 | #include <plat/omap_hwmod.h> |
| 47 | #include "omap_hwmod_2420.h" | ||
| 48 | #include "omap_hwmod_2430.h" | ||
| 49 | #include "omap_hwmod_34xx.h" | ||
| 50 | 49 | ||
| 51 | /* | 50 | /* |
| 52 | * The machine specific code may provide the extra mapping besides the | 51 | * The machine specific code may provide the extra mapping besides the |
| 53 | * default mapping provided here. | 52 | * default mapping provided here. |
| 54 | */ | 53 | */ |
| 55 | 54 | ||
| 56 | #ifdef CONFIG_ARCH_OMAP24XX | 55 | #ifdef CONFIG_ARCH_OMAP2 |
| 57 | static struct map_desc omap24xx_io_desc[] __initdata = { | 56 | static struct map_desc omap24xx_io_desc[] __initdata = { |
| 58 | { | 57 | { |
| 59 | .virtual = L3_24XX_VIRT, | 58 | .virtual = L3_24XX_VIRT, |
| @@ -123,7 +122,7 @@ static struct map_desc omap243x_io_desc[] __initdata = { | |||
| 123 | #endif | 122 | #endif |
| 124 | #endif | 123 | #endif |
| 125 | 124 | ||
| 126 | #ifdef CONFIG_ARCH_OMAP34XX | 125 | #ifdef CONFIG_ARCH_OMAP3 |
| 127 | static struct map_desc omap34xx_io_desc[] __initdata = { | 126 | static struct map_desc omap34xx_io_desc[] __initdata = { |
| 128 | { | 127 | { |
| 129 | .virtual = L3_34XX_VIRT, | 128 | .virtual = L3_34XX_VIRT, |
| @@ -138,12 +137,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = { | |||
| 138 | .type = MT_DEVICE | 137 | .type = MT_DEVICE |
| 139 | }, | 138 | }, |
| 140 | { | 139 | { |
| 141 | .virtual = L4_WK_34XX_VIRT, | ||
| 142 | .pfn = __phys_to_pfn(L4_WK_34XX_PHYS), | ||
| 143 | .length = L4_WK_34XX_SIZE, | ||
| 144 | .type = MT_DEVICE | ||
| 145 | }, | ||
| 146 | { | ||
| 147 | .virtual = OMAP34XX_GPMC_VIRT, | 140 | .virtual = OMAP34XX_GPMC_VIRT, |
| 148 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | 141 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), |
| 149 | .length = OMAP34XX_GPMC_SIZE, | 142 | .length = OMAP34XX_GPMC_SIZE, |
| @@ -190,12 +183,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = { | |||
| 190 | .type = MT_DEVICE, | 183 | .type = MT_DEVICE, |
| 191 | }, | 184 | }, |
| 192 | { | 185 | { |
| 193 | .virtual = L4_WK_44XX_VIRT, | ||
| 194 | .pfn = __phys_to_pfn(L4_WK_44XX_PHYS), | ||
| 195 | .length = L4_WK_44XX_SIZE, | ||
| 196 | .type = MT_DEVICE, | ||
| 197 | }, | ||
| 198 | { | ||
| 199 | .virtual = OMAP44XX_GPMC_VIRT, | 186 | .virtual = OMAP44XX_GPMC_VIRT, |
| 200 | .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), | 187 | .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), |
| 201 | .length = OMAP44XX_GPMC_SIZE, | 188 | .length = OMAP44XX_GPMC_SIZE, |
| @@ -234,37 +221,54 @@ static struct map_desc omap44xx_io_desc[] __initdata = { | |||
| 234 | }; | 221 | }; |
| 235 | #endif | 222 | #endif |
| 236 | 223 | ||
| 237 | void __init omap2_map_common_io(void) | 224 | static void __init _omap2_map_common_io(void) |
| 225 | { | ||
| 226 | /* Normally devicemaps_init() would flush caches and tlb after | ||
| 227 | * mdesc->map_io(), but we must also do it here because of the CPU | ||
| 228 | * revision check below. | ||
| 229 | */ | ||
| 230 | local_flush_tlb_all(); | ||
| 231 | flush_cache_all(); | ||
| 232 | |||
| 233 | omap2_check_revision(); | ||
| 234 | omap_sram_init(); | ||
| 235 | omapfb_reserve_sdram(); | ||
| 236 | omap_vram_reserve_sdram(); | ||
| 237 | } | ||
| 238 | |||
| 239 | #ifdef CONFIG_ARCH_OMAP2420 | ||
| 240 | void __init omap242x_map_common_io() | ||
| 238 | { | 241 | { |
| 239 | #if defined(CONFIG_ARCH_OMAP2420) | ||
| 240 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); | 242 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
| 241 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | 243 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); |
| 244 | _omap2_map_common_io(); | ||
| 245 | } | ||
| 242 | #endif | 246 | #endif |
| 243 | 247 | ||
| 244 | #if defined(CONFIG_ARCH_OMAP2430) | 248 | #ifdef CONFIG_ARCH_OMAP2430 |
| 249 | void __init omap243x_map_common_io() | ||
| 250 | { | ||
| 245 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); | 251 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
| 246 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | 252 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); |
| 253 | _omap2_map_common_io(); | ||
| 254 | } | ||
| 247 | #endif | 255 | #endif |
| 248 | 256 | ||
| 249 | #if defined(CONFIG_ARCH_OMAP34XX) | 257 | #ifdef CONFIG_ARCH_OMAP3 |
| 258 | void __init omap34xx_map_common_io() | ||
| 259 | { | ||
| 250 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); | 260 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
| 261 | _omap2_map_common_io(); | ||
| 262 | } | ||
| 251 | #endif | 263 | #endif |
| 252 | 264 | ||
| 253 | #if defined(CONFIG_ARCH_OMAP4) | 265 | #ifdef CONFIG_ARCH_OMAP4 |
| 266 | void __init omap44xx_map_common_io() | ||
| 267 | { | ||
| 254 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); | 268 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
| 255 | #endif | 269 | _omap2_map_common_io(); |
| 256 | /* Normally devicemaps_init() would flush caches and tlb after | ||
| 257 | * mdesc->map_io(), but we must also do it here because of the CPU | ||
| 258 | * revision check below. | ||
| 259 | */ | ||
| 260 | local_flush_tlb_all(); | ||
| 261 | flush_cache_all(); | ||
| 262 | |||
| 263 | omap2_check_revision(); | ||
| 264 | omap_sram_init(); | ||
| 265 | omapfb_reserve_sdram(); | ||
| 266 | omap_vram_reserve_sdram(); | ||
| 267 | } | 270 | } |
| 271 | #endif | ||
| 268 | 272 | ||
| 269 | /* | 273 | /* |
| 270 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | 274 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters |
| @@ -303,24 +307,31 @@ static int __init _omap2_init_reprogram_sdrc(void) | |||
| 303 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | 307 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, |
| 304 | struct omap_sdrc_params *sdrc_cs1) | 308 | struct omap_sdrc_params *sdrc_cs1) |
| 305 | { | 309 | { |
| 306 | struct omap_hwmod **hwmods = NULL; | 310 | pwrdm_init(powerdomains_omap); |
| 311 | clkdm_init(clockdomains_omap, clkdm_autodeps); | ||
| 312 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ | ||
| 313 | if (cpu_is_omap242x()) | ||
| 314 | omap2420_hwmod_init(); | ||
| 315 | else if (cpu_is_omap243x()) | ||
| 316 | omap2430_hwmod_init(); | ||
| 317 | else if (cpu_is_omap34xx()) | ||
| 318 | omap3xxx_hwmod_init(); | ||
| 319 | omap2_mux_init(); | ||
| 320 | /* The OPP tables have to be registered before a clk init */ | ||
| 321 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | ||
| 322 | #endif | ||
| 307 | 323 | ||
| 308 | if (cpu_is_omap2420()) | 324 | if (cpu_is_omap2420()) |
| 309 | hwmods = omap2420_hwmods; | 325 | omap2420_clk_init(); |
| 310 | else if (cpu_is_omap2430()) | 326 | else if (cpu_is_omap2430()) |
| 311 | hwmods = omap2430_hwmods; | 327 | omap2430_clk_init(); |
| 312 | else if (cpu_is_omap34xx()) | 328 | else if (cpu_is_omap34xx()) |
| 313 | hwmods = omap34xx_hwmods; | 329 | omap3xxx_clk_init(); |
| 330 | else if (cpu_is_omap44xx()) | ||
| 331 | omap4xxx_clk_init(); | ||
| 332 | else | ||
| 333 | pr_err("Could not init clock framework - unknown CPU\n"); | ||
| 314 | 334 | ||
| 315 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ | ||
| 316 | /* The OPP tables have to be registered before a clk init */ | ||
| 317 | omap_hwmod_init(hwmods); | ||
| 318 | omap2_mux_init(); | ||
| 319 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | ||
| 320 | pwrdm_init(powerdomains_omap); | ||
| 321 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); | ||
| 322 | #endif | ||
| 323 | omap2_clk_init(); | ||
| 324 | omap_serial_early_init(); | 335 | omap_serial_early_init(); |
| 325 | #ifndef CONFIG_ARCH_OMAP4 | 336 | #ifndef CONFIG_ARCH_OMAP4 |
| 326 | omap_hwmod_late_init(); | 337 | omap_hwmod_late_init(); |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 281ab6342448..52a981cb8fdd 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -40,6 +40,9 @@ | |||
| 40 | #define AUTOIDLE (1 << 0) | 40 | #define AUTOIDLE (1 << 0) |
| 41 | #define SOFTRESET (1 << 1) | 41 | #define SOFTRESET (1 << 1) |
| 42 | #define SMARTIDLE (2 << 3) | 42 | #define SMARTIDLE (2 << 3) |
| 43 | #define OMAP4_SOFTRESET (1 << 0) | ||
| 44 | #define OMAP4_NOIDLE (1 << 2) | ||
| 45 | #define OMAP4_SMARTIDLE (2 << 2) | ||
| 43 | 46 | ||
| 44 | /* SYSSTATUS: register bit definition */ | 47 | /* SYSSTATUS: register bit definition */ |
| 45 | #define RESETDONE (1 << 0) | 48 | #define RESETDONE (1 << 0) |
| @@ -93,29 +96,47 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) | |||
| 93 | 96 | ||
| 94 | mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); | 97 | mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); |
| 95 | if (IS_ERR(mbox_ick_handle)) { | 98 | if (IS_ERR(mbox_ick_handle)) { |
| 96 | printk(KERN_ERR "Could not get mailboxes_ick: %d\n", | 99 | printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", |
| 97 | PTR_ERR(mbox_ick_handle)); | 100 | PTR_ERR(mbox_ick_handle)); |
| 98 | return PTR_ERR(mbox_ick_handle); | 101 | return PTR_ERR(mbox_ick_handle); |
| 99 | } | 102 | } |
| 100 | clk_enable(mbox_ick_handle); | 103 | clk_enable(mbox_ick_handle); |
| 101 | 104 | ||
| 102 | mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG); | 105 | if (cpu_is_omap44xx()) { |
| 103 | timeout = jiffies + msecs_to_jiffies(20); | 106 | mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG); |
| 104 | do { | 107 | timeout = jiffies + msecs_to_jiffies(20); |
| 105 | l = mbox_read_reg(MAILBOX_SYSSTATUS); | 108 | do { |
| 106 | if (l & RESETDONE) | 109 | l = mbox_read_reg(MAILBOX_SYSCONFIG); |
| 107 | break; | 110 | if (!(l & OMAP4_SOFTRESET)) |
| 108 | } while (!time_after(jiffies, timeout)); | 111 | break; |
| 109 | 112 | } while (!time_after(jiffies, timeout)); | |
| 110 | if (!(l & RESETDONE)) { | 113 | |
| 111 | pr_err("Can't take mmu out of reset\n"); | 114 | if (l & OMAP4_SOFTRESET) { |
| 112 | return -ENODEV; | 115 | pr_err("Can't take mailbox out of reset\n"); |
| 116 | return -ENODEV; | ||
| 117 | } | ||
| 118 | } else { | ||
| 119 | mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG); | ||
| 120 | timeout = jiffies + msecs_to_jiffies(20); | ||
| 121 | do { | ||
| 122 | l = mbox_read_reg(MAILBOX_SYSSTATUS); | ||
| 123 | if (l & RESETDONE) | ||
| 124 | break; | ||
| 125 | } while (!time_after(jiffies, timeout)); | ||
| 126 | |||
| 127 | if (!(l & RESETDONE)) { | ||
| 128 | pr_err("Can't take mailbox out of reset\n"); | ||
| 129 | return -ENODEV; | ||
| 130 | } | ||
| 113 | } | 131 | } |
| 114 | 132 | ||
| 115 | l = mbox_read_reg(MAILBOX_REVISION); | 133 | l = mbox_read_reg(MAILBOX_REVISION); |
| 116 | pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); | 134 | pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); |
| 117 | 135 | ||
| 118 | l = SMARTIDLE | AUTOIDLE; | 136 | if (cpu_is_omap44xx()) |
| 137 | l = OMAP4_SMARTIDLE; | ||
| 138 | else | ||
| 139 | l = SMARTIDLE | AUTOIDLE; | ||
| 119 | mbox_write_reg(l, MAILBOX_SYSCONFIG); | 140 | mbox_write_reg(l, MAILBOX_SYSCONFIG); |
| 120 | 141 | ||
| 121 | omap2_mbox_enable_irq(mbox, IRQ_RX); | 142 | omap2_mbox_enable_irq(mbox, IRQ_RX); |
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index baa451733850..be8fce395a58 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -65,9 +65,11 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 65 | }, | 65 | }, |
| 66 | }; | 66 | }; |
| 67 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) | 67 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
| 68 | #define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) | ||
| 68 | #else | 69 | #else |
| 69 | #define omap2420_mcbsp_pdata NULL | 70 | #define omap2420_mcbsp_pdata NULL |
| 70 | #define OMAP2420_MCBSP_PDATA_SZ 0 | 71 | #define OMAP2420_MCBSP_PDATA_SZ 0 |
| 72 | #define OMAP2420_MCBSP_REG_NUM 0 | ||
| 71 | #endif | 73 | #endif |
| 72 | 74 | ||
| 73 | #ifdef CONFIG_ARCH_OMAP2430 | 75 | #ifdef CONFIG_ARCH_OMAP2430 |
| @@ -114,12 +116,14 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 114 | }, | 116 | }, |
| 115 | }; | 117 | }; |
| 116 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) | 118 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) |
| 119 | #define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) | ||
| 117 | #else | 120 | #else |
| 118 | #define omap2430_mcbsp_pdata NULL | 121 | #define omap2430_mcbsp_pdata NULL |
| 119 | #define OMAP2430_MCBSP_PDATA_SZ 0 | 122 | #define OMAP2430_MCBSP_PDATA_SZ 0 |
| 123 | #define OMAP2430_MCBSP_REG_NUM 0 | ||
| 120 | #endif | 124 | #endif |
| 121 | 125 | ||
| 122 | #ifdef CONFIG_ARCH_OMAP34XX | 126 | #ifdef CONFIG_ARCH_OMAP3 |
| 123 | static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | 127 | static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { |
| 124 | { | 128 | { |
| 125 | .phys_base = OMAP34XX_MCBSP1_BASE, | 129 | .phys_base = OMAP34XX_MCBSP1_BASE, |
| @@ -132,6 +136,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 132 | }, | 136 | }, |
| 133 | { | 137 | { |
| 134 | .phys_base = OMAP34XX_MCBSP2_BASE, | 138 | .phys_base = OMAP34XX_MCBSP2_BASE, |
| 139 | .phys_base_st = OMAP34XX_MCBSP2_ST_BASE, | ||
| 135 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, | 140 | .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, |
| 136 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, | 141 | .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, |
| 137 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 142 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| @@ -141,6 +146,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 141 | }, | 146 | }, |
| 142 | { | 147 | { |
| 143 | .phys_base = OMAP34XX_MCBSP3_BASE, | 148 | .phys_base = OMAP34XX_MCBSP3_BASE, |
| 149 | .phys_base_st = OMAP34XX_MCBSP3_ST_BASE, | ||
| 144 | .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, | 150 | .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, |
| 145 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, | 151 | .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, |
| 146 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 152 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| @@ -168,9 +174,11 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 168 | }, | 174 | }, |
| 169 | }; | 175 | }; |
| 170 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) | 176 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) |
| 177 | #define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) | ||
| 171 | #else | 178 | #else |
| 172 | #define omap34xx_mcbsp_pdata NULL | 179 | #define omap34xx_mcbsp_pdata NULL |
| 173 | #define OMAP34XX_MCBSP_PDATA_SZ 0 | 180 | #define OMAP34XX_MCBSP_PDATA_SZ 0 |
| 181 | #define OMAP34XX_MCBSP_REG_NUM 0 | ||
| 174 | #endif | 182 | #endif |
| 175 | 183 | ||
| 176 | static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { | 184 | static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { |
| @@ -208,17 +216,23 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { | |||
| 208 | }, | 216 | }, |
| 209 | }; | 217 | }; |
| 210 | #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) | 218 | #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) |
| 219 | #define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) | ||
| 211 | 220 | ||
| 212 | static int __init omap2_mcbsp_init(void) | 221 | static int __init omap2_mcbsp_init(void) |
| 213 | { | 222 | { |
| 214 | if (cpu_is_omap2420()) | 223 | if (cpu_is_omap2420()) { |
| 215 | omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; | 224 | omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; |
| 216 | if (cpu_is_omap2430()) | 225 | omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); |
| 226 | } else if (cpu_is_omap2430()) { | ||
| 217 | omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; | 227 | omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; |
| 218 | if (cpu_is_omap34xx()) | 228 | omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); |
| 229 | } else if (cpu_is_omap34xx()) { | ||
| 219 | omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; | 230 | omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; |
| 220 | if (cpu_is_omap44xx()) | 231 | omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); |
| 232 | } else if (cpu_is_omap44xx()) { | ||
| 221 | omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; | 233 | omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; |
| 234 | omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); | ||
| 235 | } | ||
| 222 | 236 | ||
| 223 | mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), | 237 | mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), |
| 224 | GFP_KERNEL); | 238 | GFP_KERNEL); |
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c deleted file mode 100644 index 8afe9dd3f150..000000000000 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ /dev/null | |||
| @@ -1,542 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/mmc-twl4030.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2008 Texas Instruments | ||
| 5 | * Copyright (C) 2008 Nokia Corporation | ||
| 6 | * Author: Texas Instruments | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #include <linux/err.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/delay.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | #include <linux/mmc/host.h> | ||
| 20 | #include <linux/regulator/consumer.h> | ||
| 21 | |||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <plat/control.h> | ||
| 24 | #include <plat/mmc.h> | ||
| 25 | #include <plat/board.h> | ||
| 26 | |||
| 27 | #include "mmc-twl4030.h" | ||
| 28 | |||
| 29 | |||
| 30 | #if defined(CONFIG_REGULATOR) && \ | ||
| 31 | (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) | ||
| 32 | |||
| 33 | static u16 control_pbias_offset; | ||
| 34 | static u16 control_devconf1_offset; | ||
| 35 | |||
| 36 | #define HSMMC_NAME_LEN 9 | ||
| 37 | |||
| 38 | static struct twl_mmc_controller { | ||
| 39 | struct omap_mmc_platform_data *mmc; | ||
| 40 | /* Vcc == configured supply | ||
| 41 | * Vcc_alt == optional | ||
| 42 | * - MMC1, supply for DAT4..DAT7 | ||
| 43 | * - MMC2/MMC2, external level shifter voltage supply, for | ||
| 44 | * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) | ||
| 45 | */ | ||
| 46 | struct regulator *vcc; | ||
| 47 | struct regulator *vcc_aux; | ||
| 48 | char name[HSMMC_NAME_LEN + 1]; | ||
| 49 | } hsmmc[OMAP34XX_NR_MMC]; | ||
| 50 | |||
| 51 | static int twl_mmc_card_detect(int irq) | ||
| 52 | { | ||
| 53 | unsigned i; | ||
| 54 | |||
| 55 | for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { | ||
| 56 | struct omap_mmc_platform_data *mmc; | ||
| 57 | |||
| 58 | mmc = hsmmc[i].mmc; | ||
| 59 | if (!mmc) | ||
| 60 | continue; | ||
| 61 | if (irq != mmc->slots[0].card_detect_irq) | ||
| 62 | continue; | ||
| 63 | |||
| 64 | /* NOTE: assumes card detect signal is active-low */ | ||
| 65 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | ||
| 66 | } | ||
| 67 | return -ENOSYS; | ||
| 68 | } | ||
| 69 | |||
| 70 | static int twl_mmc_get_ro(struct device *dev, int slot) | ||
| 71 | { | ||
| 72 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 73 | |||
| 74 | /* NOTE: assumes write protect signal is active-high */ | ||
| 75 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | ||
| 76 | } | ||
| 77 | |||
| 78 | static int twl_mmc_get_cover_state(struct device *dev, int slot) | ||
| 79 | { | ||
| 80 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 81 | |||
| 82 | /* NOTE: assumes card detect signal is active-low */ | ||
| 83 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | ||
| 84 | } | ||
| 85 | |||
| 86 | /* | ||
| 87 | * MMC Slot Initialization. | ||
| 88 | */ | ||
| 89 | static int twl_mmc_late_init(struct device *dev) | ||
| 90 | { | ||
| 91 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 92 | int ret = 0; | ||
| 93 | int i; | ||
| 94 | |||
| 95 | /* MMC/SD/SDIO doesn't require a card detect switch */ | ||
| 96 | if (gpio_is_valid(mmc->slots[0].switch_pin)) { | ||
| 97 | ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); | ||
| 98 | if (ret) | ||
| 99 | goto done; | ||
| 100 | ret = gpio_direction_input(mmc->slots[0].switch_pin); | ||
| 101 | if (ret) | ||
| 102 | goto err; | ||
| 103 | } | ||
| 104 | |||
| 105 | /* require at least main regulator */ | ||
| 106 | for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { | ||
| 107 | if (hsmmc[i].name == mmc->slots[0].name) { | ||
| 108 | struct regulator *reg; | ||
| 109 | |||
| 110 | hsmmc[i].mmc = mmc; | ||
| 111 | |||
| 112 | reg = regulator_get(dev, "vmmc"); | ||
| 113 | if (IS_ERR(reg)) { | ||
| 114 | dev_dbg(dev, "vmmc regulator missing\n"); | ||
| 115 | /* HACK: until fixed.c regulator is usable, | ||
| 116 | * we don't require a main regulator | ||
| 117 | * for MMC2 or MMC3 | ||
| 118 | */ | ||
| 119 | if (i != 0) | ||
| 120 | break; | ||
| 121 | ret = PTR_ERR(reg); | ||
| 122 | hsmmc[i].vcc = NULL; | ||
| 123 | goto err; | ||
| 124 | } | ||
| 125 | hsmmc[i].vcc = reg; | ||
| 126 | mmc->slots[0].ocr_mask = mmc_regulator_get_ocrmask(reg); | ||
| 127 | |||
| 128 | /* allow an aux regulator */ | ||
| 129 | reg = regulator_get(dev, "vmmc_aux"); | ||
| 130 | hsmmc[i].vcc_aux = IS_ERR(reg) ? NULL : reg; | ||
| 131 | |||
| 132 | /* UGLY HACK: workaround regulator framework bugs. | ||
| 133 | * When the bootloader leaves a supply active, it's | ||
| 134 | * initialized with zero usecount ... and we can't | ||
| 135 | * disable it without first enabling it. Until the | ||
| 136 | * framework is fixed, we need a workaround like this | ||
| 137 | * (which is safe for MMC, but not in general). | ||
| 138 | */ | ||
| 139 | if (regulator_is_enabled(hsmmc[i].vcc) > 0) { | ||
| 140 | regulator_enable(hsmmc[i].vcc); | ||
| 141 | regulator_disable(hsmmc[i].vcc); | ||
| 142 | } | ||
| 143 | if (hsmmc[i].vcc_aux) { | ||
| 144 | if (regulator_is_enabled(reg) > 0) { | ||
| 145 | regulator_enable(reg); | ||
| 146 | regulator_disable(reg); | ||
| 147 | } | ||
| 148 | } | ||
| 149 | |||
| 150 | break; | ||
| 151 | } | ||
| 152 | } | ||
| 153 | |||
| 154 | return 0; | ||
| 155 | |||
| 156 | err: | ||
| 157 | gpio_free(mmc->slots[0].switch_pin); | ||
| 158 | done: | ||
| 159 | mmc->slots[0].card_detect_irq = 0; | ||
| 160 | mmc->slots[0].card_detect = NULL; | ||
| 161 | |||
| 162 | dev_err(dev, "err %d configuring card detect\n", ret); | ||
| 163 | return ret; | ||
| 164 | } | ||
| 165 | |||
| 166 | static void twl_mmc_cleanup(struct device *dev) | ||
| 167 | { | ||
| 168 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 169 | int i; | ||
| 170 | |||
| 171 | gpio_free(mmc->slots[0].switch_pin); | ||
| 172 | for(i = 0; i < ARRAY_SIZE(hsmmc); i++) { | ||
| 173 | regulator_put(hsmmc[i].vcc); | ||
| 174 | regulator_put(hsmmc[i].vcc_aux); | ||
| 175 | } | ||
| 176 | } | ||
| 177 | |||
| 178 | #ifdef CONFIG_PM | ||
| 179 | |||
| 180 | static int twl_mmc_suspend(struct device *dev, int slot) | ||
| 181 | { | ||
| 182 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 183 | |||
| 184 | disable_irq(mmc->slots[0].card_detect_irq); | ||
| 185 | return 0; | ||
| 186 | } | ||
| 187 | |||
| 188 | static int twl_mmc_resume(struct device *dev, int slot) | ||
| 189 | { | ||
| 190 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 191 | |||
| 192 | enable_irq(mmc->slots[0].card_detect_irq); | ||
| 193 | return 0; | ||
| 194 | } | ||
| 195 | |||
| 196 | #else | ||
| 197 | #define twl_mmc_suspend NULL | ||
| 198 | #define twl_mmc_resume NULL | ||
| 199 | #endif | ||
| 200 | |||
| 201 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | ||
| 202 | |||
| 203 | static int twl4030_mmc_get_context_loss(struct device *dev) | ||
| 204 | { | ||
| 205 | /* FIXME: PM DPS not implemented yet */ | ||
| 206 | return 0; | ||
| 207 | } | ||
| 208 | |||
| 209 | #else | ||
| 210 | #define twl4030_mmc_get_context_loss NULL | ||
| 211 | #endif | ||
| 212 | |||
| 213 | static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, | ||
| 214 | int vdd) | ||
| 215 | { | ||
| 216 | u32 reg, prog_io; | ||
| 217 | int ret = 0; | ||
| 218 | struct twl_mmc_controller *c = &hsmmc[0]; | ||
| 219 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 220 | |||
| 221 | /* | ||
| 222 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | ||
| 223 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both | ||
| 224 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | ||
| 225 | * | ||
| 226 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | ||
| 227 | * is most naturally TWL VSIM; those pins also use PBIAS. | ||
| 228 | * | ||
| 229 | * FIXME handle VMMC1A as needed ... | ||
| 230 | */ | ||
| 231 | if (power_on) { | ||
| 232 | if (cpu_is_omap2430()) { | ||
| 233 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | ||
| 234 | if ((1 << vdd) >= MMC_VDD_30_31) | ||
| 235 | reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; | ||
| 236 | else | ||
| 237 | reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; | ||
| 238 | omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); | ||
| 239 | } | ||
| 240 | |||
| 241 | if (mmc->slots[0].internal_clock) { | ||
| 242 | reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 243 | reg |= OMAP2_MMCSDIO1ADPCLKISEL; | ||
| 244 | omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); | ||
| 245 | } | ||
| 246 | |||
| 247 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 248 | if (cpu_is_omap3630()) { | ||
| 249 | /* Set MMC I/O to 52Mhz */ | ||
| 250 | prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | ||
| 251 | prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; | ||
| 252 | omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); | ||
| 253 | } else { | ||
| 254 | reg |= OMAP2_PBIASSPEEDCTRL0; | ||
| 255 | } | ||
| 256 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | ||
| 257 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 258 | |||
| 259 | ret = mmc_regulator_set_ocr(c->vcc, vdd); | ||
| 260 | |||
| 261 | /* 100ms delay required for PBIAS configuration */ | ||
| 262 | msleep(100); | ||
| 263 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 264 | reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); | ||
| 265 | if ((1 << vdd) <= MMC_VDD_165_195) | ||
| 266 | reg &= ~OMAP2_PBIASLITEVMODE0; | ||
| 267 | else | ||
| 268 | reg |= OMAP2_PBIASLITEVMODE0; | ||
| 269 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 270 | } else { | ||
| 271 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 272 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | ||
| 273 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 274 | |||
| 275 | ret = mmc_regulator_set_ocr(c->vcc, 0); | ||
| 276 | |||
| 277 | /* 100ms delay required for PBIAS configuration */ | ||
| 278 | msleep(100); | ||
| 279 | reg = omap_ctrl_readl(control_pbias_offset); | ||
| 280 | reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | | ||
| 281 | OMAP2_PBIASLITEVMODE0); | ||
| 282 | omap_ctrl_writel(reg, control_pbias_offset); | ||
| 283 | } | ||
| 284 | |||
| 285 | return ret; | ||
| 286 | } | ||
| 287 | |||
| 288 | static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd) | ||
| 289 | { | ||
| 290 | int ret = 0; | ||
| 291 | struct twl_mmc_controller *c = NULL; | ||
| 292 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 293 | int i; | ||
| 294 | |||
| 295 | for (i = 1; i < ARRAY_SIZE(hsmmc); i++) { | ||
| 296 | if (mmc == hsmmc[i].mmc) { | ||
| 297 | c = &hsmmc[i]; | ||
| 298 | break; | ||
| 299 | } | ||
| 300 | } | ||
| 301 | |||
| 302 | if (c == NULL) | ||
| 303 | return -ENODEV; | ||
| 304 | |||
| 305 | /* If we don't see a Vcc regulator, assume it's a fixed | ||
| 306 | * voltage always-on regulator. | ||
| 307 | */ | ||
| 308 | if (!c->vcc) | ||
| 309 | return 0; | ||
| 310 | |||
| 311 | /* | ||
| 312 | * Assume Vcc regulator is used only to power the card ... OMAP | ||
| 313 | * VDDS is used to power the pins, optionally with a transceiver to | ||
| 314 | * support cards using voltages other than VDDS (1.8V nominal). When a | ||
| 315 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | ||
| 316 | * | ||
| 317 | * In some cases this regulator won't support enable/disable; | ||
| 318 | * e.g. it's a fixed rail for a WLAN chip. | ||
| 319 | * | ||
| 320 | * In other cases vcc_aux switches interface power. Example, for | ||
| 321 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | ||
| 322 | * chips/cards need an interface voltage rail too. | ||
| 323 | */ | ||
| 324 | if (power_on) { | ||
| 325 | /* only MMC2 supports a CLKIN */ | ||
| 326 | if (mmc->slots[0].internal_clock) { | ||
| 327 | u32 reg; | ||
| 328 | |||
| 329 | reg = omap_ctrl_readl(control_devconf1_offset); | ||
| 330 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; | ||
| 331 | omap_ctrl_writel(reg, control_devconf1_offset); | ||
| 332 | } | ||
| 333 | ret = mmc_regulator_set_ocr(c->vcc, vdd); | ||
| 334 | /* enable interface voltage rail, if needed */ | ||
| 335 | if (ret == 0 && c->vcc_aux) { | ||
| 336 | ret = regulator_enable(c->vcc_aux); | ||
| 337 | if (ret < 0) | ||
| 338 | ret = mmc_regulator_set_ocr(c->vcc, 0); | ||
| 339 | } | ||
| 340 | } else { | ||
| 341 | if (c->vcc_aux && (ret = regulator_is_enabled(c->vcc_aux)) > 0) | ||
| 342 | ret = regulator_disable(c->vcc_aux); | ||
| 343 | if (ret == 0) | ||
| 344 | ret = mmc_regulator_set_ocr(c->vcc, 0); | ||
| 345 | } | ||
| 346 | |||
| 347 | return ret; | ||
| 348 | } | ||
| 349 | |||
| 350 | static int twl_mmc1_set_sleep(struct device *dev, int slot, int sleep, int vdd, | ||
| 351 | int cardsleep) | ||
| 352 | { | ||
| 353 | struct twl_mmc_controller *c = &hsmmc[0]; | ||
| 354 | int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; | ||
| 355 | |||
| 356 | return regulator_set_mode(c->vcc, mode); | ||
| 357 | } | ||
| 358 | |||
| 359 | static int twl_mmc23_set_sleep(struct device *dev, int slot, int sleep, int vdd, | ||
| 360 | int cardsleep) | ||
| 361 | { | ||
| 362 | struct twl_mmc_controller *c = NULL; | ||
| 363 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 364 | int i, err, mode; | ||
| 365 | |||
| 366 | for (i = 1; i < ARRAY_SIZE(hsmmc); i++) { | ||
| 367 | if (mmc == hsmmc[i].mmc) { | ||
| 368 | c = &hsmmc[i]; | ||
| 369 | break; | ||
| 370 | } | ||
| 371 | } | ||
| 372 | |||
| 373 | if (c == NULL) | ||
| 374 | return -ENODEV; | ||
| 375 | |||
| 376 | /* | ||
| 377 | * If we don't see a Vcc regulator, assume it's a fixed | ||
| 378 | * voltage always-on regulator. | ||
| 379 | */ | ||
| 380 | if (!c->vcc) | ||
| 381 | return 0; | ||
| 382 | |||
| 383 | mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; | ||
| 384 | |||
| 385 | if (!c->vcc_aux) | ||
| 386 | return regulator_set_mode(c->vcc, mode); | ||
| 387 | |||
| 388 | if (cardsleep) { | ||
| 389 | /* VCC can be turned off if card is asleep */ | ||
| 390 | struct regulator *vcc_aux = c->vcc_aux; | ||
| 391 | |||
| 392 | c->vcc_aux = NULL; | ||
| 393 | if (sleep) | ||
| 394 | err = twl_mmc23_set_power(dev, slot, 0, 0); | ||
| 395 | else | ||
| 396 | err = twl_mmc23_set_power(dev, slot, 1, vdd); | ||
| 397 | c->vcc_aux = vcc_aux; | ||
| 398 | } else | ||
| 399 | err = regulator_set_mode(c->vcc, mode); | ||
| 400 | if (err) | ||
| 401 | return err; | ||
| 402 | return regulator_set_mode(c->vcc_aux, mode); | ||
| 403 | } | ||
| 404 | |||
| 405 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; | ||
| 406 | |||
| 407 | void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | ||
| 408 | { | ||
| 409 | struct twl4030_hsmmc_info *c; | ||
| 410 | int nr_hsmmc = ARRAY_SIZE(hsmmc_data); | ||
| 411 | int i; | ||
| 412 | |||
| 413 | if (cpu_is_omap2430()) { | ||
| 414 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | ||
| 415 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | ||
| 416 | nr_hsmmc = 2; | ||
| 417 | } else { | ||
| 418 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | ||
| 419 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | ||
| 420 | } | ||
| 421 | |||
| 422 | for (c = controllers; c->mmc; c++) { | ||
| 423 | struct twl_mmc_controller *twl = hsmmc + c->mmc - 1; | ||
| 424 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | ||
| 425 | |||
| 426 | if (!c->mmc || c->mmc > nr_hsmmc) { | ||
| 427 | pr_debug("MMC%d: no such controller\n", c->mmc); | ||
| 428 | continue; | ||
| 429 | } | ||
| 430 | if (mmc) { | ||
| 431 | pr_debug("MMC%d: already configured\n", c->mmc); | ||
| 432 | continue; | ||
| 433 | } | ||
| 434 | |||
| 435 | mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); | ||
| 436 | if (!mmc) { | ||
| 437 | pr_err("Cannot allocate memory for mmc device!\n"); | ||
| 438 | goto done; | ||
| 439 | } | ||
| 440 | |||
| 441 | if (c->name) | ||
| 442 | strncpy(twl->name, c->name, HSMMC_NAME_LEN); | ||
| 443 | else | ||
| 444 | snprintf(twl->name, ARRAY_SIZE(twl->name), | ||
| 445 | "mmc%islot%i", c->mmc, 1); | ||
| 446 | mmc->slots[0].name = twl->name; | ||
| 447 | mmc->nr_slots = 1; | ||
| 448 | mmc->slots[0].wires = c->wires; | ||
| 449 | mmc->slots[0].internal_clock = !c->ext_clock; | ||
| 450 | mmc->dma_mask = 0xffffffff; | ||
| 451 | mmc->init = twl_mmc_late_init; | ||
| 452 | |||
| 453 | /* note: twl4030 card detect GPIOs can disable VMMCx ... */ | ||
| 454 | if (gpio_is_valid(c->gpio_cd)) { | ||
| 455 | mmc->cleanup = twl_mmc_cleanup; | ||
| 456 | mmc->suspend = twl_mmc_suspend; | ||
| 457 | mmc->resume = twl_mmc_resume; | ||
| 458 | |||
| 459 | mmc->slots[0].switch_pin = c->gpio_cd; | ||
| 460 | mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); | ||
| 461 | if (c->cover_only) | ||
| 462 | mmc->slots[0].get_cover_state = twl_mmc_get_cover_state; | ||
| 463 | else | ||
| 464 | mmc->slots[0].card_detect = twl_mmc_card_detect; | ||
| 465 | } else | ||
| 466 | mmc->slots[0].switch_pin = -EINVAL; | ||
| 467 | |||
| 468 | mmc->get_context_loss_count = | ||
| 469 | twl4030_mmc_get_context_loss; | ||
| 470 | |||
| 471 | /* write protect normally uses an OMAP gpio */ | ||
| 472 | if (gpio_is_valid(c->gpio_wp)) { | ||
| 473 | gpio_request(c->gpio_wp, "mmc_wp"); | ||
| 474 | gpio_direction_input(c->gpio_wp); | ||
| 475 | |||
| 476 | mmc->slots[0].gpio_wp = c->gpio_wp; | ||
| 477 | mmc->slots[0].get_ro = twl_mmc_get_ro; | ||
| 478 | } else | ||
| 479 | mmc->slots[0].gpio_wp = -EINVAL; | ||
| 480 | |||
| 481 | if (c->nonremovable) | ||
| 482 | mmc->slots[0].nonremovable = 1; | ||
| 483 | |||
| 484 | if (c->power_saving) | ||
| 485 | mmc->slots[0].power_saving = 1; | ||
| 486 | |||
| 487 | /* NOTE: MMC slots should have a Vcc regulator set up. | ||
| 488 | * This may be from a TWL4030-family chip, another | ||
| 489 | * controllable regulator, or a fixed supply. | ||
| 490 | * | ||
| 491 | * temporary HACK: ocr_mask instead of fixed supply | ||
| 492 | */ | ||
| 493 | mmc->slots[0].ocr_mask = c->ocr_mask; | ||
| 494 | |||
| 495 | switch (c->mmc) { | ||
| 496 | case 1: | ||
| 497 | /* on-chip level shifting via PBIAS0/PBIAS1 */ | ||
| 498 | mmc->slots[0].set_power = twl_mmc1_set_power; | ||
| 499 | mmc->slots[0].set_sleep = twl_mmc1_set_sleep; | ||
| 500 | |||
| 501 | /* Omap3630 HSMMC1 supports only 4-bit */ | ||
| 502 | if (cpu_is_omap3630() && c->wires > 4) { | ||
| 503 | c->wires = 4; | ||
| 504 | mmc->slots[0].wires = c->wires; | ||
| 505 | } | ||
| 506 | break; | ||
| 507 | case 2: | ||
| 508 | if (c->ext_clock) | ||
| 509 | c->transceiver = 1; | ||
| 510 | if (c->transceiver && c->wires > 4) | ||
| 511 | c->wires = 4; | ||
| 512 | /* FALLTHROUGH */ | ||
| 513 | case 3: | ||
| 514 | /* off-chip level shifting, or none */ | ||
| 515 | mmc->slots[0].set_power = twl_mmc23_set_power; | ||
| 516 | mmc->slots[0].set_sleep = twl_mmc23_set_sleep; | ||
| 517 | break; | ||
| 518 | default: | ||
| 519 | pr_err("MMC%d configuration not supported!\n", c->mmc); | ||
| 520 | kfree(mmc); | ||
| 521 | continue; | ||
| 522 | } | ||
| 523 | hsmmc_data[c->mmc - 1] = mmc; | ||
| 524 | } | ||
| 525 | |||
| 526 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); | ||
| 527 | |||
| 528 | /* pass the device nodes back to board setup code */ | ||
| 529 | for (c = controllers; c->mmc; c++) { | ||
| 530 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | ||
| 531 | |||
| 532 | if (!c->mmc || c->mmc > nr_hsmmc) | ||
| 533 | continue; | ||
| 534 | c->dev = mmc->dev; | ||
| 535 | } | ||
| 536 | |||
| 537 | done: | ||
| 538 | for (i = 0; i < nr_hsmmc; i++) | ||
| 539 | kfree(hsmmc_data[i]); | ||
| 540 | } | ||
| 541 | |||
| 542 | #endif | ||
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 5fef73f4743d..b4ca84ee0a95 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
| @@ -75,7 +75,7 @@ void omap_mux_write_array(struct omap_board_mux *board_mux) | |||
| 75 | } | 75 | } |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) | 78 | #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX) |
| 79 | 79 | ||
| 80 | static struct omap_mux_cfg arch_mux_cfg; | 80 | static struct omap_mux_cfg arch_mux_cfg; |
| 81 | 81 | ||
| @@ -369,7 +369,7 @@ int __init omap2_mux_init(void) | |||
| 369 | 369 | ||
| 370 | /*----------------------------------------------------------------------------*/ | 370 | /*----------------------------------------------------------------------------*/ |
| 371 | 371 | ||
| 372 | #ifdef CONFIG_ARCH_OMAP34XX | 372 | #ifdef CONFIG_ARCH_OMAP3 |
| 373 | static LIST_HEAD(muxmodes); | 373 | static LIST_HEAD(muxmodes); |
| 374 | static DEFINE_MUTEX(muxmode_mutex); | 374 | static DEFINE_MUTEX(muxmode_mutex); |
| 375 | 375 | ||
| @@ -983,6 +983,38 @@ static void __init omap_mux_init_list(struct omap_mux *superset) | |||
| 983 | } | 983 | } |
| 984 | } | 984 | } |
| 985 | 985 | ||
| 986 | #ifdef CONFIG_OMAP_MUX | ||
| 987 | |||
| 988 | static void omap_mux_init_package(struct omap_mux *superset, | ||
| 989 | struct omap_mux *package_subset, | ||
| 990 | struct omap_ball *package_balls) | ||
| 991 | { | ||
| 992 | if (package_subset) | ||
| 993 | omap_mux_package_fixup(package_subset, superset); | ||
| 994 | if (package_balls) | ||
| 995 | omap_mux_package_init_balls(package_balls, superset); | ||
| 996 | } | ||
| 997 | |||
| 998 | static void omap_mux_init_signals(struct omap_board_mux *board_mux) | ||
| 999 | { | ||
| 1000 | omap_mux_set_cmdline_signals(); | ||
| 1001 | omap_mux_write_array(board_mux); | ||
| 1002 | } | ||
| 1003 | |||
| 1004 | #else | ||
| 1005 | |||
| 1006 | static void omap_mux_init_package(struct omap_mux *superset, | ||
| 1007 | struct omap_mux *package_subset, | ||
| 1008 | struct omap_ball *package_balls) | ||
| 1009 | { | ||
| 1010 | } | ||
| 1011 | |||
| 1012 | static void omap_mux_init_signals(struct omap_board_mux *board_mux) | ||
| 1013 | { | ||
| 1014 | } | ||
| 1015 | |||
| 1016 | #endif | ||
| 1017 | |||
| 986 | int __init omap_mux_init(u32 mux_pbase, u32 mux_size, | 1018 | int __init omap_mux_init(u32 mux_pbase, u32 mux_size, |
| 987 | struct omap_mux *superset, | 1019 | struct omap_mux *superset, |
| 988 | struct omap_mux *package_subset, | 1020 | struct omap_mux *package_subset, |
| @@ -999,22 +1031,12 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, | |||
| 999 | return -ENODEV; | 1031 | return -ENODEV; |
| 1000 | } | 1032 | } |
| 1001 | 1033 | ||
| 1002 | #ifdef CONFIG_OMAP_MUX | 1034 | omap_mux_init_package(superset, package_subset, package_balls); |
| 1003 | if (package_subset) | ||
| 1004 | omap_mux_package_fixup(package_subset, superset); | ||
| 1005 | if (package_balls) | ||
| 1006 | omap_mux_package_init_balls(package_balls, superset); | ||
| 1007 | #endif | ||
| 1008 | |||
| 1009 | omap_mux_init_list(superset); | 1035 | omap_mux_init_list(superset); |
| 1010 | 1036 | omap_mux_init_signals(board_mux); | |
| 1011 | #ifdef CONFIG_OMAP_MUX | ||
| 1012 | omap_mux_set_cmdline_signals(); | ||
| 1013 | omap_mux_write_array(board_mux); | ||
| 1014 | #endif | ||
| 1015 | 1037 | ||
| 1016 | return 0; | 1038 | return 0; |
| 1017 | } | 1039 | } |
| 1018 | 1040 | ||
| 1019 | #endif /* CONFIG_ARCH_OMAP34XX */ | 1041 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 1020 | 1042 | ||
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index f8c2e7a8f063..480abc56e605 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h | |||
| @@ -102,7 +102,7 @@ struct omap_board_mux { | |||
| 102 | u16 value; | 102 | u16 value; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX) | 105 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3) |
| 106 | 106 | ||
| 107 | /** | 107 | /** |
| 108 | * omap_mux_init_gpio - initialize a signal based on the GPIO number | 108 | * omap_mux_init_gpio - initialize a signal based on the GPIO number |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 478ae585ca39..c6649472ce0d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -84,17 +84,16 @@ static u8 inited; | |||
| 84 | */ | 84 | */ |
| 85 | static int _update_sysc_cache(struct omap_hwmod *oh) | 85 | static int _update_sysc_cache(struct omap_hwmod *oh) |
| 86 | { | 86 | { |
| 87 | if (!oh->sysconfig) { | 87 | if (!oh->class->sysc) { |
| 88 | WARN(!oh->sysconfig, "omap_hwmod: %s: cannot read " | 88 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); |
| 89 | "OCP_SYSCONFIG: not defined on hwmod\n", oh->name); | ||
| 90 | return -EINVAL; | 89 | return -EINVAL; |
| 91 | } | 90 | } |
| 92 | 91 | ||
| 93 | /* XXX ensure module interface clock is up */ | 92 | /* XXX ensure module interface clock is up */ |
| 94 | 93 | ||
| 95 | oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); | 94 | oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); |
| 96 | 95 | ||
| 97 | if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE)) | 96 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
| 98 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; | 97 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
| 99 | 98 | ||
| 100 | return 0; | 99 | return 0; |
| @@ -105,14 +104,13 @@ static int _update_sysc_cache(struct omap_hwmod *oh) | |||
| 105 | * @v: OCP_SYSCONFIG value to write | 104 | * @v: OCP_SYSCONFIG value to write |
| 106 | * @oh: struct omap_hwmod * | 105 | * @oh: struct omap_hwmod * |
| 107 | * | 106 | * |
| 108 | * Write @v into the module OCP_SYSCONFIG register, if it has one. No | 107 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
| 109 | * return value. | 108 | * one. No return value. |
| 110 | */ | 109 | */ |
| 111 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | 110 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) |
| 112 | { | 111 | { |
| 113 | if (!oh->sysconfig) { | 112 | if (!oh->class->sysc) { |
| 114 | WARN(!oh->sysconfig, "omap_hwmod: %s: cannot write " | 113 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); |
| 115 | "OCP_SYSCONFIG: not defined on hwmod\n", oh->name); | ||
| 116 | return; | 114 | return; |
| 117 | } | 115 | } |
| 118 | 116 | ||
| @@ -120,7 +118,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |||
| 120 | 118 | ||
| 121 | if (oh->_sysc_cache != v) { | 119 | if (oh->_sysc_cache != v) { |
| 122 | oh->_sysc_cache = v; | 120 | oh->_sysc_cache = v; |
| 123 | omap_hwmod_writel(v, oh, oh->sysconfig->sysc_offs); | 121 | omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs); |
| 124 | } | 122 | } |
| 125 | } | 123 | } |
| 126 | 124 | ||
| @@ -137,12 +135,23 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |||
| 137 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | 135 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, |
| 138 | u32 *v) | 136 | u32 *v) |
| 139 | { | 137 | { |
| 140 | if (!oh->sysconfig || | 138 | u32 mstandby_mask; |
| 141 | !(oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)) | 139 | u8 mstandby_shift; |
| 140 | |||
| 141 | if (!oh->class->sysc || | ||
| 142 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | ||
| 143 | return -EINVAL; | ||
| 144 | |||
| 145 | if (!oh->class->sysc->sysc_fields) { | ||
| 146 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
| 142 | return -EINVAL; | 147 | return -EINVAL; |
| 148 | } | ||
| 149 | |||
| 150 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; | ||
| 151 | mstandby_mask = (0x3 << mstandby_shift); | ||
| 143 | 152 | ||
| 144 | *v &= ~SYSC_MIDLEMODE_MASK; | 153 | *v &= ~mstandby_mask; |
| 145 | *v |= __ffs(standbymode) << SYSC_MIDLEMODE_SHIFT; | 154 | *v |= __ffs(standbymode) << mstandby_shift; |
| 146 | 155 | ||
| 147 | return 0; | 156 | return 0; |
| 148 | } | 157 | } |
| @@ -159,12 +168,23 @@ static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |||
| 159 | */ | 168 | */ |
| 160 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | 169 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) |
| 161 | { | 170 | { |
| 162 | if (!oh->sysconfig || | 171 | u32 sidle_mask; |
| 163 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE)) | 172 | u8 sidle_shift; |
| 173 | |||
| 174 | if (!oh->class->sysc || | ||
| 175 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | ||
| 176 | return -EINVAL; | ||
| 177 | |||
| 178 | if (!oh->class->sysc->sysc_fields) { | ||
| 179 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
| 164 | return -EINVAL; | 180 | return -EINVAL; |
| 181 | } | ||
| 165 | 182 | ||
| 166 | *v &= ~SYSC_SIDLEMODE_MASK; | 183 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
| 167 | *v |= __ffs(idlemode) << SYSC_SIDLEMODE_SHIFT; | 184 | sidle_mask = (0x3 << sidle_shift); |
| 185 | |||
| 186 | *v &= ~sidle_mask; | ||
| 187 | *v |= __ffs(idlemode) << sidle_shift; | ||
| 168 | 188 | ||
| 169 | return 0; | 189 | return 0; |
| 170 | } | 190 | } |
| @@ -182,12 +202,23 @@ static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |||
| 182 | */ | 202 | */ |
| 183 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | 203 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) |
| 184 | { | 204 | { |
| 185 | if (!oh->sysconfig || | 205 | u32 clkact_mask; |
| 186 | !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | 206 | u8 clkact_shift; |
| 207 | |||
| 208 | if (!oh->class->sysc || | ||
| 209 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | ||
| 187 | return -EINVAL; | 210 | return -EINVAL; |
| 188 | 211 | ||
| 189 | *v &= ~SYSC_CLOCKACTIVITY_MASK; | 212 | if (!oh->class->sysc->sysc_fields) { |
| 190 | *v |= clockact << SYSC_CLOCKACTIVITY_SHIFT; | 213 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); |
| 214 | return -EINVAL; | ||
| 215 | } | ||
| 216 | |||
| 217 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; | ||
| 218 | clkact_mask = (0x3 << clkact_shift); | ||
| 219 | |||
| 220 | *v &= ~clkact_mask; | ||
| 221 | *v |= clockact << clkact_shift; | ||
| 191 | 222 | ||
| 192 | return 0; | 223 | return 0; |
| 193 | } | 224 | } |
| @@ -202,11 +233,20 @@ static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |||
| 202 | */ | 233 | */ |
| 203 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | 234 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) |
| 204 | { | 235 | { |
| 205 | if (!oh->sysconfig || | 236 | u32 softrst_mask; |
| 206 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET)) | 237 | |
| 238 | if (!oh->class->sysc || | ||
| 239 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | ||
| 207 | return -EINVAL; | 240 | return -EINVAL; |
| 208 | 241 | ||
| 209 | *v |= SYSC_SOFTRESET_MASK; | 242 | if (!oh->class->sysc->sysc_fields) { |
| 243 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
| 244 | return -EINVAL; | ||
| 245 | } | ||
| 246 | |||
| 247 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | ||
| 248 | |||
| 249 | *v |= softrst_mask; | ||
| 210 | 250 | ||
| 211 | return 0; | 251 | return 0; |
| 212 | } | 252 | } |
| @@ -227,12 +267,23 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |||
| 227 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | 267 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, |
| 228 | u32 *v) | 268 | u32 *v) |
| 229 | { | 269 | { |
| 230 | if (!oh->sysconfig || | 270 | u32 autoidle_mask; |
| 231 | !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)) | 271 | u8 autoidle_shift; |
| 272 | |||
| 273 | if (!oh->class->sysc || | ||
| 274 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | ||
| 232 | return -EINVAL; | 275 | return -EINVAL; |
| 233 | 276 | ||
| 234 | *v &= ~SYSC_AUTOIDLE_MASK; | 277 | if (!oh->class->sysc->sysc_fields) { |
| 235 | *v |= autoidle << SYSC_AUTOIDLE_SHIFT; | 278 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); |
| 279 | return -EINVAL; | ||
| 280 | } | ||
| 281 | |||
| 282 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; | ||
| 283 | autoidle_mask = (0x3 << autoidle_shift); | ||
| 284 | |||
| 285 | *v &= ~autoidle_mask; | ||
| 286 | *v |= autoidle << autoidle_shift; | ||
| 236 | 287 | ||
| 237 | return 0; | 288 | return 0; |
| 238 | } | 289 | } |
| @@ -246,14 +297,21 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |||
| 246 | */ | 297 | */ |
| 247 | static int _enable_wakeup(struct omap_hwmod *oh) | 298 | static int _enable_wakeup(struct omap_hwmod *oh) |
| 248 | { | 299 | { |
| 249 | u32 v; | 300 | u32 v, wakeup_mask; |
| 250 | 301 | ||
| 251 | if (!oh->sysconfig || | 302 | if (!oh->class->sysc || |
| 252 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 303 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
| 253 | return -EINVAL; | 304 | return -EINVAL; |
| 254 | 305 | ||
| 306 | if (!oh->class->sysc->sysc_fields) { | ||
| 307 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
| 308 | return -EINVAL; | ||
| 309 | } | ||
| 310 | |||
| 311 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | ||
| 312 | |||
| 255 | v = oh->_sysc_cache; | 313 | v = oh->_sysc_cache; |
| 256 | v |= SYSC_ENAWAKEUP_MASK; | 314 | v |= wakeup_mask; |
| 257 | _write_sysconfig(v, oh); | 315 | _write_sysconfig(v, oh); |
| 258 | 316 | ||
| 259 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 317 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
| @@ -272,14 +330,21 @@ static int _enable_wakeup(struct omap_hwmod *oh) | |||
| 272 | */ | 330 | */ |
| 273 | static int _disable_wakeup(struct omap_hwmod *oh) | 331 | static int _disable_wakeup(struct omap_hwmod *oh) |
| 274 | { | 332 | { |
| 275 | u32 v; | 333 | u32 v, wakeup_mask; |
| 276 | 334 | ||
| 277 | if (!oh->sysconfig || | 335 | if (!oh->class->sysc || |
| 278 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 336 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
| 279 | return -EINVAL; | 337 | return -EINVAL; |
| 280 | 338 | ||
| 339 | if (!oh->class->sysc->sysc_fields) { | ||
| 340 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
| 341 | return -EINVAL; | ||
| 342 | } | ||
| 343 | |||
| 344 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | ||
| 345 | |||
| 281 | v = oh->_sysc_cache; | 346 | v = oh->_sysc_cache; |
| 282 | v &= ~SYSC_ENAWAKEUP_MASK; | 347 | v &= ~wakeup_mask; |
| 283 | _write_sysconfig(v, oh); | 348 | _write_sysconfig(v, oh); |
| 284 | 349 | ||
| 285 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 350 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
| @@ -299,15 +364,14 @@ static int _disable_wakeup(struct omap_hwmod *oh) | |||
| 299 | * be accessed by the IVA, there should be a sleepdep between the IVA | 364 | * be accessed by the IVA, there should be a sleepdep between the IVA |
| 300 | * initiator and the module). Only applies to modules in smart-idle | 365 | * initiator and the module). Only applies to modules in smart-idle |
| 301 | * mode. Returns -EINVAL upon error or passes along | 366 | * mode. Returns -EINVAL upon error or passes along |
| 302 | * pwrdm_add_sleepdep() value upon success. | 367 | * clkdm_add_sleepdep() value upon success. |
| 303 | */ | 368 | */ |
| 304 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | 369 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) |
| 305 | { | 370 | { |
| 306 | if (!oh->_clk) | 371 | if (!oh->_clk) |
| 307 | return -EINVAL; | 372 | return -EINVAL; |
| 308 | 373 | ||
| 309 | return pwrdm_add_sleepdep(oh->_clk->clkdm->pwrdm.ptr, | 374 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
| 310 | init_oh->_clk->clkdm->pwrdm.ptr); | ||
| 311 | } | 375 | } |
| 312 | 376 | ||
| 313 | /** | 377 | /** |
| @@ -320,15 +384,14 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |||
| 320 | * be accessed by the IVA, there should be no sleepdep between the IVA | 384 | * be accessed by the IVA, there should be no sleepdep between the IVA |
| 321 | * initiator and the module). Only applies to modules in smart-idle | 385 | * initiator and the module). Only applies to modules in smart-idle |
| 322 | * mode. Returns -EINVAL upon error or passes along | 386 | * mode. Returns -EINVAL upon error or passes along |
| 323 | * pwrdm_add_sleepdep() value upon success. | 387 | * clkdm_del_sleepdep() value upon success. |
| 324 | */ | 388 | */ |
| 325 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | 389 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) |
| 326 | { | 390 | { |
| 327 | if (!oh->_clk) | 391 | if (!oh->_clk) |
| 328 | return -EINVAL; | 392 | return -EINVAL; |
| 329 | 393 | ||
| 330 | return pwrdm_del_sleepdep(oh->_clk->clkdm->pwrdm.ptr, | 394 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
| 331 | init_oh->_clk->clkdm->pwrdm.ptr); | ||
| 332 | } | 395 | } |
| 333 | 396 | ||
| 334 | /** | 397 | /** |
| @@ -344,18 +407,18 @@ static int _init_main_clk(struct omap_hwmod *oh) | |||
| 344 | struct clk *c; | 407 | struct clk *c; |
| 345 | int ret = 0; | 408 | int ret = 0; |
| 346 | 409 | ||
| 347 | if (!oh->clkdev_con_id) | 410 | if (!oh->main_clk) |
| 348 | return 0; | 411 | return 0; |
| 349 | 412 | ||
| 350 | c = clk_get_sys(oh->clkdev_dev_id, oh->clkdev_con_id); | 413 | c = omap_clk_get_by_name(oh->main_clk); |
| 351 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s.%s\n", | 414 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s\n", |
| 352 | oh->name, oh->clkdev_dev_id, oh->clkdev_con_id); | 415 | oh->name, oh->main_clk); |
| 353 | if (IS_ERR(c)) | 416 | if (IS_ERR(c)) |
| 354 | ret = -EINVAL; | 417 | ret = -EINVAL; |
| 355 | oh->_clk = c; | 418 | oh->_clk = c; |
| 356 | 419 | ||
| 357 | WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", | 420 | WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", |
| 358 | oh->clkdev_con_id, c->name); | 421 | oh->main_clk, c->name); |
| 359 | 422 | ||
| 360 | return ret; | 423 | return ret; |
| 361 | } | 424 | } |
| @@ -378,13 +441,12 @@ static int _init_interface_clks(struct omap_hwmod *oh) | |||
| 378 | return 0; | 441 | return 0; |
| 379 | 442 | ||
| 380 | for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { | 443 | for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { |
| 381 | if (!os->clkdev_con_id) | 444 | if (!os->clk) |
| 382 | continue; | 445 | continue; |
| 383 | 446 | ||
| 384 | c = clk_get_sys(os->clkdev_dev_id, os->clkdev_con_id); | 447 | c = omap_clk_get_by_name(os->clk); |
| 385 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " | 448 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " |
| 386 | "interface_clk %s.%s\n", oh->name, | 449 | "interface_clk %s\n", oh->name, os->clk); |
| 387 | os->clkdev_dev_id, os->clkdev_con_id); | ||
| 388 | if (IS_ERR(c)) | 450 | if (IS_ERR(c)) |
| 389 | ret = -EINVAL; | 451 | ret = -EINVAL; |
| 390 | os->_clk = c; | 452 | os->_clk = c; |
| @@ -408,10 +470,9 @@ static int _init_opt_clks(struct omap_hwmod *oh) | |||
| 408 | int ret = 0; | 470 | int ret = 0; |
| 409 | 471 | ||
| 410 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | 472 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { |
| 411 | c = clk_get_sys(oc->clkdev_dev_id, oc->clkdev_con_id); | 473 | c = omap_clk_get_by_name(oc->clk); |
| 412 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " | 474 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " |
| 413 | "%s.%s\n", oh->name, oc->clkdev_dev_id, | 475 | "%s\n", oh->name, oc->clk); |
| 414 | oc->clkdev_con_id); | ||
| 415 | if (IS_ERR(c)) | 476 | if (IS_ERR(c)) |
| 416 | ret = -EINVAL; | 477 | ret = -EINVAL; |
| 417 | oc->_clk = c; | 478 | oc->_clk = c; |
| @@ -568,27 +629,28 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |||
| 568 | */ | 629 | */ |
| 569 | static void _sysc_enable(struct omap_hwmod *oh) | 630 | static void _sysc_enable(struct omap_hwmod *oh) |
| 570 | { | 631 | { |
| 571 | u8 idlemode; | 632 | u8 idlemode, sf; |
| 572 | u32 v; | 633 | u32 v; |
| 573 | 634 | ||
| 574 | if (!oh->sysconfig) | 635 | if (!oh->class->sysc) |
| 575 | return; | 636 | return; |
| 576 | 637 | ||
| 577 | v = oh->_sysc_cache; | 638 | v = oh->_sysc_cache; |
| 639 | sf = oh->class->sysc->sysc_flags; | ||
| 578 | 640 | ||
| 579 | if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) { | 641 | if (sf & SYSC_HAS_SIDLEMODE) { |
| 580 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 642 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
| 581 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | 643 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; |
| 582 | _set_slave_idlemode(oh, idlemode, &v); | 644 | _set_slave_idlemode(oh, idlemode, &v); |
| 583 | } | 645 | } |
| 584 | 646 | ||
| 585 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) { | 647 | if (sf & SYSC_HAS_MIDLEMODE) { |
| 586 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? | 648 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
| 587 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | 649 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; |
| 588 | _set_master_standbymode(oh, idlemode, &v); | 650 | _set_master_standbymode(oh, idlemode, &v); |
| 589 | } | 651 | } |
| 590 | 652 | ||
| 591 | if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) { | 653 | if (sf & SYSC_HAS_AUTOIDLE) { |
| 592 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | 654 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? |
| 593 | 0 : 1; | 655 | 0 : 1; |
| 594 | _set_module_autoidle(oh, idlemode, &v); | 656 | _set_module_autoidle(oh, idlemode, &v); |
| @@ -601,9 +663,9 @@ static void _sysc_enable(struct omap_hwmod *oh) | |||
| 601 | * calling into this code. But this must wait until the | 663 | * calling into this code. But this must wait until the |
| 602 | * clock structures are tagged with omap_hwmod entries | 664 | * clock structures are tagged with omap_hwmod entries |
| 603 | */ | 665 | */ |
| 604 | if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && | 666 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
| 605 | oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) | 667 | (sf & SYSC_HAS_CLOCKACTIVITY)) |
| 606 | _set_clockactivity(oh, oh->sysconfig->clockact, &v); | 668 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); |
| 607 | 669 | ||
| 608 | _write_sysconfig(v, oh); | 670 | _write_sysconfig(v, oh); |
| 609 | } | 671 | } |
| @@ -619,21 +681,22 @@ static void _sysc_enable(struct omap_hwmod *oh) | |||
| 619 | */ | 681 | */ |
| 620 | static void _sysc_idle(struct omap_hwmod *oh) | 682 | static void _sysc_idle(struct omap_hwmod *oh) |
| 621 | { | 683 | { |
| 622 | u8 idlemode; | 684 | u8 idlemode, sf; |
| 623 | u32 v; | 685 | u32 v; |
| 624 | 686 | ||
| 625 | if (!oh->sysconfig) | 687 | if (!oh->class->sysc) |
| 626 | return; | 688 | return; |
| 627 | 689 | ||
| 628 | v = oh->_sysc_cache; | 690 | v = oh->_sysc_cache; |
| 691 | sf = oh->class->sysc->sysc_flags; | ||
| 629 | 692 | ||
| 630 | if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) { | 693 | if (sf & SYSC_HAS_SIDLEMODE) { |
| 631 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 694 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
| 632 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | 695 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; |
| 633 | _set_slave_idlemode(oh, idlemode, &v); | 696 | _set_slave_idlemode(oh, idlemode, &v); |
| 634 | } | 697 | } |
| 635 | 698 | ||
| 636 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) { | 699 | if (sf & SYSC_HAS_MIDLEMODE) { |
| 637 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? | 700 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
| 638 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | 701 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; |
| 639 | _set_master_standbymode(oh, idlemode, &v); | 702 | _set_master_standbymode(oh, idlemode, &v); |
| @@ -652,19 +715,21 @@ static void _sysc_idle(struct omap_hwmod *oh) | |||
| 652 | static void _sysc_shutdown(struct omap_hwmod *oh) | 715 | static void _sysc_shutdown(struct omap_hwmod *oh) |
| 653 | { | 716 | { |
| 654 | u32 v; | 717 | u32 v; |
| 718 | u8 sf; | ||
| 655 | 719 | ||
| 656 | if (!oh->sysconfig) | 720 | if (!oh->class->sysc) |
| 657 | return; | 721 | return; |
| 658 | 722 | ||
| 659 | v = oh->_sysc_cache; | 723 | v = oh->_sysc_cache; |
| 724 | sf = oh->class->sysc->sysc_flags; | ||
| 660 | 725 | ||
| 661 | if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) | 726 | if (sf & SYSC_HAS_SIDLEMODE) |
| 662 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); | 727 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
| 663 | 728 | ||
| 664 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) | 729 | if (sf & SYSC_HAS_MIDLEMODE) |
| 665 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); | 730 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
| 666 | 731 | ||
| 667 | if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) | 732 | if (sf & SYSC_HAS_AUTOIDLE) |
| 668 | _set_module_autoidle(oh, 1, &v); | 733 | _set_module_autoidle(oh, 1, &v); |
| 669 | 734 | ||
| 670 | _write_sysconfig(v, oh); | 735 | _write_sysconfig(v, oh); |
| @@ -781,9 +846,9 @@ static int _reset(struct omap_hwmod *oh) | |||
| 781 | u32 r, v; | 846 | u32 r, v; |
| 782 | int c = 0; | 847 | int c = 0; |
| 783 | 848 | ||
| 784 | if (!oh->sysconfig || | 849 | if (!oh->class->sysc || |
| 785 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || | 850 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || |
| 786 | (oh->sysconfig->sysc_flags & SYSS_MISSING)) | 851 | (oh->class->sysc->sysc_flags & SYSS_MISSING)) |
| 787 | return -EINVAL; | 852 | return -EINVAL; |
| 788 | 853 | ||
| 789 | /* clocks must be on for this operation */ | 854 | /* clocks must be on for this operation */ |
| @@ -801,7 +866,7 @@ static int _reset(struct omap_hwmod *oh) | |||
| 801 | return r; | 866 | return r; |
| 802 | _write_sysconfig(v, oh); | 867 | _write_sysconfig(v, oh); |
| 803 | 868 | ||
| 804 | omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & | 869 | omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & |
| 805 | SYSS_RESETDONE_MASK), | 870 | SYSS_RESETDONE_MASK), |
| 806 | MAX_MODULE_RESET_WAIT, c); | 871 | MAX_MODULE_RESET_WAIT, c); |
| 807 | 872 | ||
| @@ -847,7 +912,7 @@ static int _enable(struct omap_hwmod *oh) | |||
| 847 | _add_initiator_dep(oh, mpu_oh); | 912 | _add_initiator_dep(oh, mpu_oh); |
| 848 | _enable_clocks(oh); | 913 | _enable_clocks(oh); |
| 849 | 914 | ||
| 850 | if (oh->sysconfig) { | 915 | if (oh->class->sysc) { |
| 851 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | 916 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) |
| 852 | _update_sysc_cache(oh); | 917 | _update_sysc_cache(oh); |
| 853 | _sysc_enable(oh); | 918 | _sysc_enable(oh); |
| @@ -878,7 +943,7 @@ static int _idle(struct omap_hwmod *oh) | |||
| 878 | 943 | ||
| 879 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | 944 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
| 880 | 945 | ||
| 881 | if (oh->sysconfig) | 946 | if (oh->class->sysc) |
| 882 | _sysc_idle(oh); | 947 | _sysc_idle(oh); |
| 883 | _del_initiator_dep(oh, mpu_oh); | 948 | _del_initiator_dep(oh, mpu_oh); |
| 884 | _disable_clocks(oh); | 949 | _disable_clocks(oh); |
| @@ -908,7 +973,7 @@ static int _shutdown(struct omap_hwmod *oh) | |||
| 908 | 973 | ||
| 909 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | 974 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
| 910 | 975 | ||
| 911 | if (oh->sysconfig) | 976 | if (oh->class->sysc) |
| 912 | _sysc_shutdown(oh); | 977 | _sysc_shutdown(oh); |
| 913 | _del_initiator_dep(oh, mpu_oh); | 978 | _del_initiator_dep(oh, mpu_oh); |
| 914 | /* XXX what about the other system initiators here? DMA, tesla, d2d */ | 979 | /* XXX what about the other system initiators here? DMA, tesla, d2d */ |
| @@ -968,7 +1033,7 @@ static int _setup(struct omap_hwmod *oh) | |||
| 968 | * _enable() function should be split to avoid the | 1033 | * _enable() function should be split to avoid the |
| 969 | * rewrite of the OCP_SYSCONFIG register. | 1034 | * rewrite of the OCP_SYSCONFIG register. |
| 970 | */ | 1035 | */ |
| 971 | if (oh->sysconfig) { | 1036 | if (oh->class->sysc) { |
| 972 | _update_sysc_cache(oh); | 1037 | _update_sysc_cache(oh); |
| 973 | _sysc_enable(oh); | 1038 | _sysc_enable(oh); |
| 974 | } | 1039 | } |
| @@ -994,13 +1059,33 @@ void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |||
| 994 | __raw_writel(v, oh->_rt_va + reg_offs); | 1059 | __raw_writel(v, oh->_rt_va + reg_offs); |
| 995 | } | 1060 | } |
| 996 | 1061 | ||
| 1062 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | ||
| 1063 | { | ||
| 1064 | u32 v; | ||
| 1065 | int retval = 0; | ||
| 1066 | |||
| 1067 | if (!oh) | ||
| 1068 | return -EINVAL; | ||
| 1069 | |||
| 1070 | v = oh->_sysc_cache; | ||
| 1071 | |||
| 1072 | retval = _set_slave_idlemode(oh, idlemode, &v); | ||
| 1073 | if (!retval) | ||
| 1074 | _write_sysconfig(v, oh); | ||
| 1075 | |||
| 1076 | return retval; | ||
| 1077 | } | ||
| 1078 | |||
| 997 | /** | 1079 | /** |
| 998 | * omap_hwmod_register - register a struct omap_hwmod | 1080 | * omap_hwmod_register - register a struct omap_hwmod |
| 999 | * @oh: struct omap_hwmod * | 1081 | * @oh: struct omap_hwmod * |
| 1000 | * | 1082 | * |
| 1001 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod already | 1083 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
| 1002 | * has been registered by the same name; -EINVAL if the omap_hwmod is in the | 1084 | * already has been registered by the same name; -EINVAL if the |
| 1003 | * wrong state, or 0 on success. | 1085 | * omap_hwmod is in the wrong state, if @oh is NULL, if the |
| 1086 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | ||
| 1087 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | ||
| 1088 | * success. | ||
| 1004 | * | 1089 | * |
| 1005 | * XXX The data should be copied into bootmem, so the original data | 1090 | * XXX The data should be copied into bootmem, so the original data |
| 1006 | * should be marked __initdata and freed after init. This would allow | 1091 | * should be marked __initdata and freed after init. This would allow |
| @@ -1012,7 +1097,8 @@ int omap_hwmod_register(struct omap_hwmod *oh) | |||
| 1012 | { | 1097 | { |
| 1013 | int ret, ms_id; | 1098 | int ret, ms_id; |
| 1014 | 1099 | ||
| 1015 | if (!oh || (oh->_state != _HWMOD_STATE_UNKNOWN)) | 1100 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
| 1101 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | ||
| 1016 | return -EINVAL; | 1102 | return -EINVAL; |
| 1017 | 1103 | ||
| 1018 | mutex_lock(&omap_hwmod_mutex); | 1104 | mutex_lock(&omap_hwmod_mutex); |
| @@ -1285,7 +1371,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |||
| 1285 | { | 1371 | { |
| 1286 | BUG_ON(!oh); | 1372 | BUG_ON(!oh); |
| 1287 | 1373 | ||
| 1288 | if (!oh->sysconfig || !oh->sysconfig->sysc_flags) { | 1374 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
| 1289 | WARN(1, "omap_device: %s: OCP barrier impossible due to " | 1375 | WARN(1, "omap_device: %s: OCP barrier impossible due to " |
| 1290 | "device configuration\n", oh->name); | 1376 | "device configuration\n", oh->name); |
| 1291 | return; | 1377 | return; |
| @@ -1295,7 +1381,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |||
| 1295 | * Forces posted writes to complete on the OCP thread handling | 1381 | * Forces posted writes to complete on the OCP thread handling |
| 1296 | * register writes | 1382 | * register writes |
| 1297 | */ | 1383 | */ |
| 1298 | omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); | 1384 | omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); |
| 1299 | } | 1385 | } |
| 1300 | 1386 | ||
| 1301 | /** | 1387 | /** |
| @@ -1488,8 +1574,8 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |||
| 1488 | */ | 1574 | */ |
| 1489 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | 1575 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) |
| 1490 | { | 1576 | { |
| 1491 | if (!oh->sysconfig || | 1577 | if (!oh->class->sysc || |
| 1492 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 1578 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
| 1493 | return -EINVAL; | 1579 | return -EINVAL; |
| 1494 | 1580 | ||
| 1495 | mutex_lock(&omap_hwmod_mutex); | 1581 | mutex_lock(&omap_hwmod_mutex); |
| @@ -1513,8 +1599,8 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |||
| 1513 | */ | 1599 | */ |
| 1514 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | 1600 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) |
| 1515 | { | 1601 | { |
| 1516 | if (!oh->sysconfig || | 1602 | if (!oh->class->sysc || |
| 1517 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 1603 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
| 1518 | return -EINVAL; | 1604 | return -EINVAL; |
| 1519 | 1605 | ||
| 1520 | mutex_lock(&omap_hwmod_mutex); | 1606 | mutex_lock(&omap_hwmod_mutex); |
| @@ -1523,3 +1609,52 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |||
| 1523 | 1609 | ||
| 1524 | return 0; | 1610 | return 0; |
| 1525 | } | 1611 | } |
| 1612 | |||
| 1613 | /** | ||
| 1614 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | ||
| 1615 | * @classname: struct omap_hwmod_class name to search for | ||
| 1616 | * @fn: callback function pointer to call for each hwmod in class @classname | ||
| 1617 | * @user: arbitrary context data to pass to the callback function | ||
| 1618 | * | ||
| 1619 | * For each omap_hwmod of class @classname, call @fn. Takes | ||
| 1620 | * omap_hwmod_mutex to prevent the hwmod list from changing during the | ||
| 1621 | * iteration. If the callback function returns something other than | ||
| 1622 | * zero, the iterator is terminated, and the callback function's return | ||
| 1623 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | ||
| 1624 | * if @classname or @fn are NULL, or passes back the error code from @fn. | ||
| 1625 | */ | ||
| 1626 | int omap_hwmod_for_each_by_class(const char *classname, | ||
| 1627 | int (*fn)(struct omap_hwmod *oh, | ||
| 1628 | void *user), | ||
| 1629 | void *user) | ||
| 1630 | { | ||
| 1631 | struct omap_hwmod *temp_oh; | ||
| 1632 | int ret = 0; | ||
| 1633 | |||
| 1634 | if (!classname || !fn) | ||
| 1635 | return -EINVAL; | ||
| 1636 | |||
| 1637 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | ||
| 1638 | __func__, classname); | ||
| 1639 | |||
| 1640 | mutex_lock(&omap_hwmod_mutex); | ||
| 1641 | |||
| 1642 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | ||
| 1643 | if (!strcmp(temp_oh->class->name, classname)) { | ||
| 1644 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | ||
| 1645 | __func__, temp_oh->name); | ||
| 1646 | ret = (*fn)(temp_oh, user); | ||
| 1647 | if (ret) | ||
| 1648 | break; | ||
| 1649 | } | ||
| 1650 | } | ||
| 1651 | |||
| 1652 | mutex_unlock(&omap_hwmod_mutex); | ||
| 1653 | |||
| 1654 | if (ret) | ||
| 1655 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | ||
| 1656 | __func__, ret); | ||
| 1657 | |||
| 1658 | return ret; | ||
| 1659 | } | ||
| 1660 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a9ca1b99a301..eb7ee2453b24 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420.h +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap_hwmod_2420.h - hardware modules present on the OMAP2420 chips | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
| 5 | * Paul Walmsley | 5 | * Paul Walmsley |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| @@ -9,20 +9,26 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | * | 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? | 11 | * XXX handle crossbar/shared link difference for L3? |
| 12 | * | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
| 13 | */ | 13 | */ |
| 14 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H | ||
| 15 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H | ||
| 16 | |||
| 17 | #ifdef CONFIG_ARCH_OMAP2420 | ||
| 18 | |||
| 19 | #include <plat/omap_hwmod.h> | 14 | #include <plat/omap_hwmod.h> |
| 20 | #include <mach/irqs.h> | 15 | #include <mach/irqs.h> |
| 21 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
| 22 | #include <plat/dma.h> | 17 | #include <plat/dma.h> |
| 23 | 18 | ||
| 19 | #include "omap_hwmod_common_data.h" | ||
| 20 | |||
| 24 | #include "prm-regbits-24xx.h" | 21 | #include "prm-regbits-24xx.h" |
| 25 | 22 | ||
| 23 | /* | ||
| 24 | * OMAP2420 hardware module integration data | ||
| 25 | * | ||
| 26 | * ALl of the data in this section should be autogeneratable from the | ||
| 27 | * TI hardware database or other technical documentation. Data that | ||
| 28 | * is driver-specific or driver-kernel integration-specific belongs | ||
| 29 | * elsewhere. | ||
| 30 | */ | ||
| 31 | |||
| 26 | static struct omap_hwmod omap2420_mpu_hwmod; | 32 | static struct omap_hwmod omap2420_mpu_hwmod; |
| 27 | static struct omap_hwmod omap2420_l3_hwmod; | 33 | static struct omap_hwmod omap2420_l3_hwmod; |
| 28 | static struct omap_hwmod omap2420_l4_core_hwmod; | 34 | static struct omap_hwmod omap2420_l4_core_hwmod; |
| @@ -54,6 +60,7 @@ static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = { | |||
| 54 | /* L3 */ | 60 | /* L3 */ |
| 55 | static struct omap_hwmod omap2420_l3_hwmod = { | 61 | static struct omap_hwmod omap2420_l3_hwmod = { |
| 56 | .name = "l3_hwmod", | 62 | .name = "l3_hwmod", |
| 63 | .class = &l3_hwmod_class, | ||
| 57 | .masters = omap2420_l3_masters, | 64 | .masters = omap2420_l3_masters, |
| 58 | .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), | 65 | .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), |
| 59 | .slaves = omap2420_l3_slaves, | 66 | .slaves = omap2420_l3_slaves, |
| @@ -83,6 +90,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { | |||
| 83 | /* L4 CORE */ | 90 | /* L4 CORE */ |
| 84 | static struct omap_hwmod omap2420_l4_core_hwmod = { | 91 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
| 85 | .name = "l4_core_hwmod", | 92 | .name = "l4_core_hwmod", |
| 93 | .class = &l4_hwmod_class, | ||
| 86 | .masters = omap2420_l4_core_masters, | 94 | .masters = omap2420_l4_core_masters, |
| 87 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), | 95 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 88 | .slaves = omap2420_l4_core_slaves, | 96 | .slaves = omap2420_l4_core_slaves, |
| @@ -102,6 +110,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { | |||
| 102 | /* L4 WKUP */ | 110 | /* L4 WKUP */ |
| 103 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { | 111 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
| 104 | .name = "l4_wkup_hwmod", | 112 | .name = "l4_wkup_hwmod", |
| 113 | .class = &l4_hwmod_class, | ||
| 105 | .masters = omap2420_l4_wkup_masters, | 114 | .masters = omap2420_l4_wkup_masters, |
| 106 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), | 115 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 107 | .slaves = omap2420_l4_wkup_slaves, | 116 | .slaves = omap2420_l4_wkup_slaves, |
| @@ -117,8 +126,8 @@ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { | |||
| 117 | /* MPU */ | 126 | /* MPU */ |
| 118 | static struct omap_hwmod omap2420_mpu_hwmod = { | 127 | static struct omap_hwmod omap2420_mpu_hwmod = { |
| 119 | .name = "mpu_hwmod", | 128 | .name = "mpu_hwmod", |
| 120 | .clkdev_dev_id = NULL, | 129 | .class = &mpu_hwmod_class, |
| 121 | .clkdev_con_id = "mpu_ck", | 130 | .main_clk = "mpu_ck", |
| 122 | .masters = omap2420_mpu_masters, | 131 | .masters = omap2420_mpu_masters, |
| 123 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), | 132 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 124 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -132,10 +141,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { | |||
| 132 | NULL, | 141 | NULL, |
| 133 | }; | 142 | }; |
| 134 | 143 | ||
| 135 | #else | 144 | int __init omap2420_hwmod_init(void) |
| 136 | # define omap2420_hwmods 0 | 145 | { |
| 137 | #endif | 146 | return omap_hwmod_init(omap2420_hwmods); |
| 138 | 147 | } | |
| 139 | #endif | ||
| 140 | 148 | ||
| 141 | 149 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 59a208bea6c2..241bd8230729 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430.h +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap_hwmod_2430.h - hardware modules present on the OMAP2430 chips | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
| 5 | * Paul Walmsley | 5 | * Paul Walmsley |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| @@ -9,20 +9,26 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | * | 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? | 11 | * XXX handle crossbar/shared link difference for L3? |
| 12 | * | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
| 13 | */ | 13 | */ |
| 14 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H | ||
| 15 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H | ||
| 16 | |||
| 17 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 18 | |||
| 19 | #include <plat/omap_hwmod.h> | 14 | #include <plat/omap_hwmod.h> |
| 20 | #include <mach/irqs.h> | 15 | #include <mach/irqs.h> |
| 21 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
| 22 | #include <plat/dma.h> | 17 | #include <plat/dma.h> |
| 23 | 18 | ||
| 19 | #include "omap_hwmod_common_data.h" | ||
| 20 | |||
| 24 | #include "prm-regbits-24xx.h" | 21 | #include "prm-regbits-24xx.h" |
| 25 | 22 | ||
| 23 | /* | ||
| 24 | * OMAP2430 hardware module integration data | ||
| 25 | * | ||
| 26 | * ALl of the data in this section should be autogeneratable from the | ||
| 27 | * TI hardware database or other technical documentation. Data that | ||
| 28 | * is driver-specific or driver-kernel integration-specific belongs | ||
| 29 | * elsewhere. | ||
| 30 | */ | ||
| 31 | |||
| 26 | static struct omap_hwmod omap2430_mpu_hwmod; | 32 | static struct omap_hwmod omap2430_mpu_hwmod; |
| 27 | static struct omap_hwmod omap2430_l3_hwmod; | 33 | static struct omap_hwmod omap2430_l3_hwmod; |
| 28 | static struct omap_hwmod omap2430_l4_core_hwmod; | 34 | static struct omap_hwmod omap2430_l4_core_hwmod; |
| @@ -54,6 +60,7 @@ static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = { | |||
| 54 | /* L3 */ | 60 | /* L3 */ |
| 55 | static struct omap_hwmod omap2430_l3_hwmod = { | 61 | static struct omap_hwmod omap2430_l3_hwmod = { |
| 56 | .name = "l3_hwmod", | 62 | .name = "l3_hwmod", |
| 63 | .class = &l3_hwmod_class, | ||
| 57 | .masters = omap2430_l3_masters, | 64 | .masters = omap2430_l3_masters, |
| 58 | .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), | 65 | .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), |
| 59 | .slaves = omap2430_l3_slaves, | 66 | .slaves = omap2430_l3_slaves, |
| @@ -85,6 +92,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |||
| 85 | /* L4 CORE */ | 92 | /* L4 CORE */ |
| 86 | static struct omap_hwmod omap2430_l4_core_hwmod = { | 93 | static struct omap_hwmod omap2430_l4_core_hwmod = { |
| 87 | .name = "l4_core_hwmod", | 94 | .name = "l4_core_hwmod", |
| 95 | .class = &l4_hwmod_class, | ||
| 88 | .masters = omap2430_l4_core_masters, | 96 | .masters = omap2430_l4_core_masters, |
| 89 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | 97 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), |
| 90 | .slaves = omap2430_l4_core_slaves, | 98 | .slaves = omap2430_l4_core_slaves, |
| @@ -104,6 +112,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |||
| 104 | /* L4 WKUP */ | 112 | /* L4 WKUP */ |
| 105 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | 113 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { |
| 106 | .name = "l4_wkup_hwmod", | 114 | .name = "l4_wkup_hwmod", |
| 115 | .class = &l4_hwmod_class, | ||
| 107 | .masters = omap2430_l4_wkup_masters, | 116 | .masters = omap2430_l4_wkup_masters, |
| 108 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | 117 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), |
| 109 | .slaves = omap2430_l4_wkup_slaves, | 118 | .slaves = omap2430_l4_wkup_slaves, |
| @@ -119,8 +128,8 @@ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |||
| 119 | /* MPU */ | 128 | /* MPU */ |
| 120 | static struct omap_hwmod omap2430_mpu_hwmod = { | 129 | static struct omap_hwmod omap2430_mpu_hwmod = { |
| 121 | .name = "mpu_hwmod", | 130 | .name = "mpu_hwmod", |
| 122 | .clkdev_dev_id = NULL, | 131 | .class = &mpu_hwmod_class, |
| 123 | .clkdev_con_id = "mpu_ck", | 132 | .main_clk = "mpu_ck", |
| 124 | .masters = omap2430_mpu_masters, | 133 | .masters = omap2430_mpu_masters, |
| 125 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | 134 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), |
| 126 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -134,10 +143,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { | |||
| 134 | NULL, | 143 | NULL, |
| 135 | }; | 144 | }; |
| 136 | 145 | ||
| 137 | #else | 146 | int __init omap2430_hwmod_init(void) |
| 138 | # define omap2430_hwmods 0 | 147 | { |
| 139 | #endif | 148 | return omap_hwmod_init(omap2430_hwmods); |
| 140 | 149 | } | |
| 141 | #endif | ||
| 142 | 150 | ||
| 143 | 151 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h deleted file mode 100644 index b6076b9c364e..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_34xx.h +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H | ||
| 13 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H | ||
| 14 | |||
| 15 | #ifdef CONFIG_ARCH_OMAP34XX | ||
| 16 | |||
| 17 | #include <plat/omap_hwmod.h> | ||
| 18 | #include <mach/irqs.h> | ||
| 19 | #include <plat/cpu.h> | ||
| 20 | #include <plat/dma.h> | ||
| 21 | |||
| 22 | #include "prm-regbits-34xx.h" | ||
| 23 | |||
| 24 | static struct omap_hwmod omap34xx_mpu_hwmod; | ||
| 25 | static struct omap_hwmod omap34xx_l3_hwmod; | ||
| 26 | static struct omap_hwmod omap34xx_l4_core_hwmod; | ||
| 27 | static struct omap_hwmod omap34xx_l4_per_hwmod; | ||
| 28 | |||
| 29 | /* L3 -> L4_CORE interface */ | ||
| 30 | static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = { | ||
| 31 | .master = &omap34xx_l3_hwmod, | ||
| 32 | .slave = &omap34xx_l4_core_hwmod, | ||
| 33 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* L3 -> L4_PER interface */ | ||
| 37 | static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = { | ||
| 38 | .master = &omap34xx_l3_hwmod, | ||
| 39 | .slave = &omap34xx_l4_per_hwmod, | ||
| 40 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 41 | }; | ||
| 42 | |||
| 43 | /* MPU -> L3 interface */ | ||
| 44 | static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = { | ||
| 45 | .master = &omap34xx_mpu_hwmod, | ||
| 46 | .slave = &omap34xx_l3_hwmod, | ||
| 47 | .user = OCP_USER_MPU, | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* Slave interfaces on the L3 interconnect */ | ||
| 51 | static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = { | ||
| 52 | &omap34xx_mpu__l3, | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* Master interfaces on the L3 interconnect */ | ||
| 56 | static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = { | ||
| 57 | &omap34xx_l3__l4_core, | ||
| 58 | &omap34xx_l3__l4_per, | ||
| 59 | }; | ||
| 60 | |||
| 61 | /* L3 */ | ||
| 62 | static struct omap_hwmod omap34xx_l3_hwmod = { | ||
| 63 | .name = "l3_hwmod", | ||
| 64 | .masters = omap34xx_l3_masters, | ||
| 65 | .masters_cnt = ARRAY_SIZE(omap34xx_l3_masters), | ||
| 66 | .slaves = omap34xx_l3_slaves, | ||
| 67 | .slaves_cnt = ARRAY_SIZE(omap34xx_l3_slaves), | ||
| 68 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct omap_hwmod omap34xx_l4_wkup_hwmod; | ||
| 72 | |||
| 73 | /* L4_CORE -> L4_WKUP interface */ | ||
| 74 | static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = { | ||
| 75 | .master = &omap34xx_l4_core_hwmod, | ||
| 76 | .slave = &omap34xx_l4_wkup_hwmod, | ||
| 77 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 78 | }; | ||
| 79 | |||
| 80 | /* Slave interfaces on the L4_CORE interconnect */ | ||
| 81 | static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = { | ||
| 82 | &omap34xx_l3__l4_core, | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* Master interfaces on the L4_CORE interconnect */ | ||
| 86 | static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = { | ||
| 87 | &omap34xx_l4_core__l4_wkup, | ||
| 88 | }; | ||
| 89 | |||
| 90 | /* L4 CORE */ | ||
| 91 | static struct omap_hwmod omap34xx_l4_core_hwmod = { | ||
| 92 | .name = "l4_core_hwmod", | ||
| 93 | .masters = omap34xx_l4_core_masters, | ||
| 94 | .masters_cnt = ARRAY_SIZE(omap34xx_l4_core_masters), | ||
| 95 | .slaves = omap34xx_l4_core_slaves, | ||
| 96 | .slaves_cnt = ARRAY_SIZE(omap34xx_l4_core_slaves), | ||
| 97 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 98 | }; | ||
| 99 | |||
| 100 | /* Slave interfaces on the L4_PER interconnect */ | ||
| 101 | static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = { | ||
| 102 | &omap34xx_l3__l4_per, | ||
| 103 | }; | ||
| 104 | |||
| 105 | /* Master interfaces on the L4_PER interconnect */ | ||
| 106 | static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = { | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* L4 PER */ | ||
| 110 | static struct omap_hwmod omap34xx_l4_per_hwmod = { | ||
| 111 | .name = "l4_per_hwmod", | ||
| 112 | .masters = omap34xx_l4_per_masters, | ||
| 113 | .masters_cnt = ARRAY_SIZE(omap34xx_l4_per_masters), | ||
| 114 | .slaves = omap34xx_l4_per_slaves, | ||
| 115 | .slaves_cnt = ARRAY_SIZE(omap34xx_l4_per_slaves), | ||
| 116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 117 | }; | ||
| 118 | |||
| 119 | /* Slave interfaces on the L4_WKUP interconnect */ | ||
| 120 | static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = { | ||
| 121 | &omap34xx_l4_core__l4_wkup, | ||
| 122 | }; | ||
| 123 | |||
| 124 | /* Master interfaces on the L4_WKUP interconnect */ | ||
| 125 | static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = { | ||
| 126 | }; | ||
| 127 | |||
| 128 | /* L4 WKUP */ | ||
| 129 | static struct omap_hwmod omap34xx_l4_wkup_hwmod = { | ||
| 130 | .name = "l4_wkup_hwmod", | ||
| 131 | .masters = omap34xx_l4_wkup_masters, | ||
| 132 | .masters_cnt = ARRAY_SIZE(omap34xx_l4_wkup_masters), | ||
| 133 | .slaves = omap34xx_l4_wkup_slaves, | ||
| 134 | .slaves_cnt = ARRAY_SIZE(omap34xx_l4_wkup_slaves), | ||
| 135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 136 | }; | ||
| 137 | |||
| 138 | /* Master interfaces on the MPU device */ | ||
| 139 | static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = { | ||
| 140 | &omap34xx_mpu__l3, | ||
| 141 | }; | ||
| 142 | |||
| 143 | /* MPU */ | ||
| 144 | static struct omap_hwmod omap34xx_mpu_hwmod = { | ||
| 145 | .name = "mpu_hwmod", | ||
| 146 | .clkdev_dev_id = NULL, | ||
| 147 | .clkdev_con_id = "arm_fck", | ||
| 148 | .masters = omap34xx_mpu_masters, | ||
| 149 | .masters_cnt = ARRAY_SIZE(omap34xx_mpu_masters), | ||
| 150 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 151 | }; | ||
| 152 | |||
| 153 | static __initdata struct omap_hwmod *omap34xx_hwmods[] = { | ||
| 154 | &omap34xx_l3_hwmod, | ||
| 155 | &omap34xx_l4_core_hwmod, | ||
| 156 | &omap34xx_l4_per_hwmod, | ||
| 157 | &omap34xx_l4_wkup_hwmod, | ||
| 158 | &omap34xx_mpu_hwmod, | ||
| 159 | NULL, | ||
| 160 | }; | ||
| 161 | |||
| 162 | #else | ||
| 163 | # define omap34xx_hwmods 0 | ||
| 164 | #endif | ||
| 165 | |||
| 166 | #endif | ||
| 167 | |||
| 168 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c new file mode 100644 index 000000000000..ed6084004260 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | /* | ||
| 2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * The data in this file should be completely autogeneratable from | ||
| 12 | * the TI hardware database or other technical documentation. | ||
| 13 | * | ||
| 14 | * XXX these should be marked initdata for multi-OMAP kernels | ||
| 15 | */ | ||
| 16 | #include <plat/omap_hwmod.h> | ||
| 17 | #include <mach/irqs.h> | ||
| 18 | #include <plat/cpu.h> | ||
| 19 | #include <plat/dma.h> | ||
| 20 | |||
| 21 | #include "omap_hwmod_common_data.h" | ||
| 22 | |||
| 23 | #include "prm-regbits-34xx.h" | ||
| 24 | |||
| 25 | /* | ||
| 26 | * OMAP3xxx hardware module integration data | ||
| 27 | * | ||
| 28 | * ALl of the data in this section should be autogeneratable from the | ||
| 29 | * TI hardware database or other technical documentation. Data that | ||
| 30 | * is driver-specific or driver-kernel integration-specific belongs | ||
| 31 | * elsewhere. | ||
| 32 | */ | ||
| 33 | |||
| 34 | static struct omap_hwmod omap3xxx_mpu_hwmod; | ||
| 35 | static struct omap_hwmod omap3xxx_l3_hwmod; | ||
| 36 | static struct omap_hwmod omap3xxx_l4_core_hwmod; | ||
| 37 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | ||
| 38 | |||
| 39 | /* L3 -> L4_CORE interface */ | ||
| 40 | static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = { | ||
| 41 | .master = &omap3xxx_l3_hwmod, | ||
| 42 | .slave = &omap3xxx_l4_core_hwmod, | ||
| 43 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 44 | }; | ||
| 45 | |||
| 46 | /* L3 -> L4_PER interface */ | ||
| 47 | static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = { | ||
| 48 | .master = &omap3xxx_l3_hwmod, | ||
| 49 | .slave = &omap3xxx_l4_per_hwmod, | ||
| 50 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* MPU -> L3 interface */ | ||
| 54 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = { | ||
| 55 | .master = &omap3xxx_mpu_hwmod, | ||
| 56 | .slave = &omap3xxx_l3_hwmod, | ||
| 57 | .user = OCP_USER_MPU, | ||
| 58 | }; | ||
| 59 | |||
| 60 | /* Slave interfaces on the L3 interconnect */ | ||
| 61 | static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = { | ||
| 62 | &omap3xxx_mpu__l3, | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* Master interfaces on the L3 interconnect */ | ||
| 66 | static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = { | ||
| 67 | &omap3xxx_l3__l4_core, | ||
| 68 | &omap3xxx_l3__l4_per, | ||
| 69 | }; | ||
| 70 | |||
| 71 | /* L3 */ | ||
| 72 | static struct omap_hwmod omap3xxx_l3_hwmod = { | ||
| 73 | .name = "l3_hwmod", | ||
| 74 | .class = &l3_hwmod_class, | ||
| 75 | .masters = omap3xxx_l3_masters, | ||
| 76 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters), | ||
| 77 | .slaves = omap3xxx_l3_slaves, | ||
| 78 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves), | ||
| 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | ||
| 83 | |||
| 84 | /* L4_CORE -> L4_WKUP interface */ | ||
| 85 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | ||
| 86 | .master = &omap3xxx_l4_core_hwmod, | ||
| 87 | .slave = &omap3xxx_l4_wkup_hwmod, | ||
| 88 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 89 | }; | ||
| 90 | |||
| 91 | /* Slave interfaces on the L4_CORE interconnect */ | ||
| 92 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | ||
| 93 | &omap3xxx_l3__l4_core, | ||
| 94 | }; | ||
| 95 | |||
| 96 | /* Master interfaces on the L4_CORE interconnect */ | ||
| 97 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { | ||
| 98 | &omap3xxx_l4_core__l4_wkup, | ||
| 99 | }; | ||
| 100 | |||
| 101 | /* L4 CORE */ | ||
| 102 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | ||
| 103 | .name = "l4_core_hwmod", | ||
| 104 | .class = &l4_hwmod_class, | ||
| 105 | .masters = omap3xxx_l4_core_masters, | ||
| 106 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), | ||
| 107 | .slaves = omap3xxx_l4_core_slaves, | ||
| 108 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | ||
| 109 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* Slave interfaces on the L4_PER interconnect */ | ||
| 113 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | ||
| 114 | &omap3xxx_l3__l4_per, | ||
| 115 | }; | ||
| 116 | |||
| 117 | /* Master interfaces on the L4_PER interconnect */ | ||
| 118 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* L4 PER */ | ||
| 122 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | ||
| 123 | .name = "l4_per_hwmod", | ||
| 124 | .class = &l4_hwmod_class, | ||
| 125 | .masters = omap3xxx_l4_per_masters, | ||
| 126 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), | ||
| 127 | .slaves = omap3xxx_l4_per_slaves, | ||
| 128 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | ||
| 129 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 130 | }; | ||
| 131 | |||
| 132 | /* Slave interfaces on the L4_WKUP interconnect */ | ||
| 133 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { | ||
| 134 | &omap3xxx_l4_core__l4_wkup, | ||
| 135 | }; | ||
| 136 | |||
| 137 | /* Master interfaces on the L4_WKUP interconnect */ | ||
| 138 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { | ||
| 139 | }; | ||
| 140 | |||
| 141 | /* L4 WKUP */ | ||
| 142 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | ||
| 143 | .name = "l4_wkup_hwmod", | ||
| 144 | .class = &l4_hwmod_class, | ||
| 145 | .masters = omap3xxx_l4_wkup_masters, | ||
| 146 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), | ||
| 147 | .slaves = omap3xxx_l4_wkup_slaves, | ||
| 148 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | ||
| 149 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 150 | }; | ||
| 151 | |||
| 152 | /* Master interfaces on the MPU device */ | ||
| 153 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | ||
| 154 | &omap3xxx_mpu__l3, | ||
| 155 | }; | ||
| 156 | |||
| 157 | /* MPU */ | ||
| 158 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | ||
| 159 | .name = "mpu_hwmod", | ||
| 160 | .class = &mpu_hwmod_class, | ||
| 161 | .main_clk = "arm_fck", | ||
| 162 | .masters = omap3xxx_mpu_masters, | ||
| 163 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), | ||
| 164 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 165 | }; | ||
| 166 | |||
| 167 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { | ||
| 168 | &omap3xxx_l3_hwmod, | ||
| 169 | &omap3xxx_l4_core_hwmod, | ||
| 170 | &omap3xxx_l4_per_hwmod, | ||
| 171 | &omap3xxx_l4_wkup_hwmod, | ||
| 172 | &omap3xxx_mpu_hwmod, | ||
| 173 | NULL, | ||
| 174 | }; | ||
| 175 | |||
| 176 | int __init omap3xxx_hwmod_init(void) | ||
| 177 | { | ||
| 178 | return omap_hwmod_init(omap3xxx_hwmods); | ||
| 179 | } | ||
| 180 | |||
| 181 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c new file mode 100644 index 000000000000..1e80b914fa1a --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * omap_hwmod common data structures | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Thara Gopinath <thara@ti.com> | ||
| 6 | * Benoît Cousson | ||
| 7 | * | ||
| 8 | * Copyright (C) 2010 Nokia Corporation | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * This data/structures are to be used while defining OMAP on-chip module | ||
| 16 | * data and their integration with other OMAP modules and Linux. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <plat/omap_hwmod.h> | ||
| 20 | |||
| 21 | #include "omap_hwmod_common_data.h" | ||
| 22 | |||
| 23 | /** | ||
| 24 | * struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme. | ||
| 25 | * | ||
| 26 | * To be used by hwmod structure to specify the sysconfig offsets | ||
| 27 | * if the device ip is compliant with the original PRCM protocol | ||
| 28 | * defined for OMAP2420. | ||
| 29 | */ | ||
| 30 | struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = { | ||
| 31 | .midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT, | ||
| 32 | .clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT, | ||
| 33 | .sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT, | ||
| 34 | .enwkup_shift = SYSC_TYPE1_ENAWAKEUP_SHIFT, | ||
| 35 | .srst_shift = SYSC_TYPE1_SOFTRESET_SHIFT, | ||
| 36 | .autoidle_shift = SYSC_TYPE1_AUTOIDLE_SHIFT, | ||
| 37 | }; | ||
| 38 | |||
| 39 | /** | ||
| 40 | * struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme. | ||
| 41 | * | ||
| 42 | * To be used by hwmod structure to specify the sysconfig offsets if the | ||
| 43 | * device ip is compliant with the new PRCM protocol defined for new | ||
| 44 | * OMAP4 IPs. | ||
| 45 | */ | ||
| 46 | struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { | ||
| 47 | .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT, | ||
| 48 | .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT, | ||
| 49 | .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, | ||
| 50 | }; | ||
| 51 | |||
| 52 | |||
| 53 | /* | ||
| 54 | * omap_hwmod class data | ||
| 55 | */ | ||
| 56 | |||
| 57 | struct omap_hwmod_class l3_hwmod_class = { | ||
| 58 | .name = "l3" | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct omap_hwmod_class l4_hwmod_class = { | ||
| 62 | .name = "l4" | ||
| 63 | }; | ||
| 64 | |||
| 65 | struct omap_hwmod_class mpu_hwmod_class = { | ||
| 66 | .name = "mpu" | ||
| 67 | }; | ||
| 68 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h new file mode 100644 index 000000000000..3645a28c7c27 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 8 | * Benoît Cousson | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H | ||
| 15 | #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H | ||
| 16 | |||
| 17 | #include <plat/omap_hwmod.h> | ||
| 18 | |||
| 19 | /* OMAP hwmod classes - forward declarations */ | ||
| 20 | extern struct omap_hwmod_class l3_hwmod_class; | ||
| 21 | extern struct omap_hwmod_class l4_hwmod_class; | ||
| 22 | extern struct omap_hwmod_class mpu_hwmod_class; | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h index ed6df04e2f29..38b730550506 100644 --- a/arch/arm/mach-omap2/opp2xxx.h +++ b/arch/arm/mach-omap2/opp2xxx.h | |||
| @@ -417,7 +417,12 @@ struct prcm_config { | |||
| 417 | 417 | ||
| 418 | 418 | ||
| 419 | extern const struct prcm_config omap2420_rate_table[]; | 419 | extern const struct prcm_config omap2420_rate_table[]; |
| 420 | |||
| 421 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 420 | extern const struct prcm_config omap2430_rate_table[]; | 422 | extern const struct prcm_config omap2430_rate_table[]; |
| 423 | #else | ||
| 424 | #define omap2430_rate_table NULL | ||
| 425 | #endif | ||
| 421 | extern const struct prcm_config *rate_table; | 426 | extern const struct prcm_config *rate_table; |
| 422 | extern const struct prcm_config *curr_prcm_set; | 427 | extern const struct prcm_config *curr_prcm_set; |
| 423 | 428 | ||
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a0866268aa41..c18f7f2f19bc 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
| @@ -67,9 +67,9 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) | |||
| 67 | #if 0 | 67 | #if 0 |
| 68 | /* MPU */ | 68 | /* MPU */ |
| 69 | DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); | 69 | DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); |
| 70 | DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); | 70 | DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL); |
| 71 | DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); | 71 | DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL); |
| 72 | DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); | 72 | DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST); |
| 73 | DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); | 73 | DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); |
| 74 | #endif | 74 | #endif |
| 75 | #if 0 | 75 | #if 0 |
| @@ -93,7 +93,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) | |||
| 93 | DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); | 93 | DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); |
| 94 | DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); | 94 | DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); |
| 95 | DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); | 95 | DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); |
| 96 | DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); | 96 | DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST); |
| 97 | #endif | 97 | #endif |
| 98 | #if 0 | 98 | #if 0 |
| 99 | /* DSP */ | 99 | /* DSP */ |
| @@ -103,11 +103,11 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) | |||
| 103 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); | 103 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); |
| 104 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); | 104 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); |
| 105 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); | 105 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); |
| 106 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); | 106 | DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL); |
| 107 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); | 107 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL); |
| 108 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); | 108 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST); |
| 109 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); | 109 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL); |
| 110 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); | 110 | DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST); |
| 111 | } | 111 | } |
| 112 | #endif | 112 | #endif |
| 113 | } else { | 113 | } else { |
| @@ -385,6 +385,11 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user) | |||
| 385 | seq_printf(s, ",%s:%d", pwrdm_state_names[i], | 385 | seq_printf(s, ",%s:%d", pwrdm_state_names[i], |
| 386 | pwrdm->state_counter[i]); | 386 | pwrdm->state_counter[i]); |
| 387 | 387 | ||
| 388 | seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter); | ||
| 389 | for (i = 0; i < pwrdm->banks; i++) | ||
| 390 | seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1, | ||
| 391 | pwrdm->ret_mem_off_counter[i]); | ||
| 392 | |||
| 388 | seq_printf(s, "\n"); | 393 | seq_printf(s, "\n"); |
| 389 | 394 | ||
| 390 | return 0; | 395 | return 0; |
| @@ -577,7 +582,7 @@ static int __init pm_dbg_init(void) | |||
| 577 | (void) debugfs_create_file("time", S_IRUGO, | 582 | (void) debugfs_create_file("time", S_IRUGO, |
| 578 | d, (void *)DEBUG_FILE_TIMERS, &debug_fops); | 583 | d, (void *)DEBUG_FILE_TIMERS, &debug_fops); |
| 579 | 584 | ||
| 580 | pwrdm_for_each_nolock(pwrdms_setup, (void *)d); | 585 | pwrdm_for_each(pwrdms_setup, (void *)d); |
| 581 | 586 | ||
| 582 | pm_dbg_dir = debugfs_create_dir("registers", d); | 587 | pm_dbg_dir = debugfs_create_dir("registers", d); |
| 583 | if (IS_ERR(pm_dbg_dir)) | 588 | if (IS_ERR(pm_dbg_dir)) |
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 7a9c2d004511..bd6466a2b039 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h | |||
| @@ -23,6 +23,22 @@ extern int omap3_can_sleep(void); | |||
| 23 | extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); | 23 | extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); |
| 24 | extern int omap3_idle_init(void); | 24 | extern int omap3_idle_init(void); |
| 25 | 25 | ||
| 26 | struct cpuidle_params { | ||
| 27 | u8 valid; | ||
| 28 | u32 sleep_latency; | ||
| 29 | u32 wake_latency; | ||
| 30 | u32 threshold; | ||
| 31 | }; | ||
| 32 | |||
| 33 | #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE) | ||
| 34 | extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params); | ||
| 35 | #else | ||
| 36 | static | ||
| 37 | inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) | ||
| 38 | { | ||
| 39 | } | ||
| 40 | #endif | ||
| 41 | |||
| 26 | extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); | 42 | extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); |
| 27 | extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); | 43 | extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); |
| 28 | 44 | ||
| @@ -37,6 +53,10 @@ extern int omap2_pm_debug; | |||
| 37 | #define omap2_pm_debug 0 | 53 | #define omap2_pm_debug 0 |
| 38 | #endif | 54 | #endif |
| 39 | 55 | ||
| 56 | #if defined(CONFIG_CPU_IDLE) | ||
| 57 | extern void omap3_cpuidle_update_states(void); | ||
| 58 | #endif | ||
| 59 | |||
| 40 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | 60 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
| 41 | extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); | 61 | extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); |
| 42 | extern int pm_dbg_regset_save(int reg_set); | 62 | extern int pm_dbg_regset_save(int reg_set); |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index cba05b9f041f..374299ea7ade 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
| @@ -57,11 +57,8 @@ static void (*omap2_sram_idle)(void); | |||
| 57 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, | 57 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
| 58 | void __iomem *sdrc_power); | 58 | void __iomem *sdrc_power); |
| 59 | 59 | ||
| 60 | static struct powerdomain *mpu_pwrdm; | 60 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
| 61 | static struct powerdomain *core_pwrdm; | 61 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; |
| 62 | |||
| 63 | static struct clockdomain *dsp_clkdm; | ||
| 64 | static struct clockdomain *gfx_clkdm; | ||
| 65 | 62 | ||
| 66 | static struct clk *osc_ck, *emul_ck; | 63 | static struct clk *osc_ck, *emul_ck; |
| 67 | 64 | ||
| @@ -219,11 +216,12 @@ static void omap2_enter_mpu_retention(void) | |||
| 219 | /* Try to enter MPU retention */ | 216 | /* Try to enter MPU retention */ |
| 220 | prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | | 217 | prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | |
| 221 | OMAP_LOGICRETSTATE, | 218 | OMAP_LOGICRETSTATE, |
| 222 | MPU_MOD, PM_PWSTCTRL); | 219 | MPU_MOD, OMAP2_PM_PWSTCTRL); |
| 223 | } else { | 220 | } else { |
| 224 | /* Block MPU retention */ | 221 | /* Block MPU retention */ |
| 225 | 222 | ||
| 226 | prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); | 223 | prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, |
| 224 | OMAP2_PM_PWSTCTRL); | ||
| 227 | only_idle = 1; | 225 | only_idle = 1; |
| 228 | } | 226 | } |
| 229 | 227 | ||
| @@ -333,9 +331,17 @@ static struct platform_suspend_ops omap_pm_ops = { | |||
| 333 | .valid = suspend_valid_only_mem, | 331 | .valid = suspend_valid_only_mem, |
| 334 | }; | 332 | }; |
| 335 | 333 | ||
| 336 | static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused) | 334 | /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ |
| 335 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | ||
| 337 | { | 336 | { |
| 338 | omap2_clkdm_allow_idle(clkdm); | 337 | clkdm_clear_all_wkdeps(clkdm); |
| 338 | clkdm_clear_all_sleepdeps(clkdm); | ||
| 339 | |||
| 340 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | ||
| 341 | omap2_clkdm_allow_idle(clkdm); | ||
| 342 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | ||
| 343 | atomic_read(&clkdm->usecount) == 0) | ||
| 344 | omap2_clkdm_sleep(clkdm); | ||
| 339 | return 0; | 345 | return 0; |
| 340 | } | 346 | } |
| 341 | 347 | ||
| @@ -348,14 +354,6 @@ static void __init prcm_setup_regs(void) | |||
| 348 | prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, | 354 | prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, |
| 349 | OMAP2_PRCM_SYSCONFIG_OFFSET); | 355 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
| 350 | 356 | ||
| 351 | /* Set all domain wakeup dependencies */ | ||
| 352 | prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP); | ||
| 353 | prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP); | ||
| 354 | prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); | ||
| 355 | prm_write_mod_reg(0, CORE_MOD, PM_WKDEP); | ||
| 356 | if (cpu_is_omap2430()) | ||
| 357 | prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP); | ||
| 358 | |||
| 359 | /* | 357 | /* |
| 360 | * Set CORE powerdomain memory banks to retain their contents | 358 | * Set CORE powerdomain memory banks to retain their contents |
| 361 | * during RETENTION | 359 | * during RETENTION |
| @@ -384,8 +382,12 @@ static void __init prcm_setup_regs(void) | |||
| 384 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | 382 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); |
| 385 | omap2_clkdm_sleep(gfx_clkdm); | 383 | omap2_clkdm_sleep(gfx_clkdm); |
| 386 | 384 | ||
| 387 | /* Enable clockdomain hardware-supervised control for all clkdms */ | 385 | /* |
| 388 | clkdm_for_each(_pm_clkdm_enable_hwsup, NULL); | 386 | * Clear clockdomain wakeup dependencies and enable |
| 387 | * hardware-supervised idle for all clkdms | ||
| 388 | */ | ||
| 389 | clkdm_for_each(clkdms_setup, NULL); | ||
| 390 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); | ||
| 389 | 391 | ||
| 390 | /* Enable clock autoidle for all domains */ | 392 | /* Enable clock autoidle for all domains */ |
| 391 | cm_write_mod_reg(OMAP24XX_AUTO_CAM | | 393 | cm_write_mod_reg(OMAP24XX_AUTO_CAM | |
| @@ -481,7 +483,7 @@ static int __init omap2_pm_init(void) | |||
| 481 | l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); | 483 | l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
| 482 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | 484 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
| 483 | 485 | ||
| 484 | /* Look up important powerdomains, clockdomains */ | 486 | /* Look up important powerdomains */ |
| 485 | 487 | ||
| 486 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | 488 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
| 487 | if (!mpu_pwrdm) | 489 | if (!mpu_pwrdm) |
| @@ -491,9 +493,19 @@ static int __init omap2_pm_init(void) | |||
| 491 | if (!core_pwrdm) | 493 | if (!core_pwrdm) |
| 492 | pr_err("PM: core_pwrdm not found\n"); | 494 | pr_err("PM: core_pwrdm not found\n"); |
| 493 | 495 | ||
| 496 | /* Look up important clockdomains */ | ||
| 497 | |||
| 498 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | ||
| 499 | if (!mpu_clkdm) | ||
| 500 | pr_err("PM: mpu_clkdm not found\n"); | ||
| 501 | |||
| 502 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | ||
| 503 | if (!wkup_clkdm) | ||
| 504 | pr_err("PM: wkup_clkdm not found\n"); | ||
| 505 | |||
| 494 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); | 506 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
| 495 | if (!dsp_clkdm) | 507 | if (!dsp_clkdm) |
| 496 | pr_err("PM: mpu_clkdm not found\n"); | 508 | pr_err("PM: dsp_clkdm not found\n"); |
| 497 | 509 | ||
| 498 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); | 510 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); |
| 499 | if (!gfx_clkdm) | 511 | if (!gfx_clkdm) |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 910a7acf542d..fee2efb172e7 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
| @@ -685,10 +685,10 @@ static void __init omap3_iva_idle(void) | |||
| 685 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | | 685 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | |
| 686 | OMAP3430_RST2_IVA2 | | 686 | OMAP3430_RST2_IVA2 | |
| 687 | OMAP3430_RST3_IVA2, | 687 | OMAP3430_RST3_IVA2, |
| 688 | OMAP3430_IVA2_MOD, RM_RSTCTRL); | 688 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
| 689 | 689 | ||
| 690 | /* Enable IVA2 clock */ | 690 | /* Enable IVA2 clock */ |
| 691 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, | 691 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
| 692 | OMAP3430_IVA2_MOD, CM_FCLKEN); | 692 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 693 | 693 | ||
| 694 | /* Set IVA2 boot mode to 'idle' */ | 694 | /* Set IVA2 boot mode to 'idle' */ |
| @@ -696,7 +696,7 @@ static void __init omap3_iva_idle(void) | |||
| 696 | OMAP343X_CONTROL_IVA2_BOOTMOD); | 696 | OMAP343X_CONTROL_IVA2_BOOTMOD); |
| 697 | 697 | ||
| 698 | /* Un-reset IVA2 */ | 698 | /* Un-reset IVA2 */ |
| 699 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); | 699 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
| 700 | 700 | ||
| 701 | /* Disable IVA2 clock */ | 701 | /* Disable IVA2 clock */ |
| 702 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | 702 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
| @@ -705,7 +705,7 @@ static void __init omap3_iva_idle(void) | |||
| 705 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | | 705 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | |
| 706 | OMAP3430_RST2_IVA2 | | 706 | OMAP3430_RST2_IVA2 | |
| 707 | OMAP3430_RST3_IVA2, | 707 | OMAP3430_RST3_IVA2, |
| 708 | OMAP3430_IVA2_MOD, RM_RSTCTRL); | 708 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
| 709 | } | 709 | } |
| 710 | 710 | ||
| 711 | static void __init omap3_d2d_idle(void) | 711 | static void __init omap3_d2d_idle(void) |
| @@ -728,8 +728,8 @@ static void __init omap3_d2d_idle(void) | |||
| 728 | /* reset modem */ | 728 | /* reset modem */ |
| 729 | prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | | 729 | prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | |
| 730 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, | 730 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, |
| 731 | CORE_MOD, RM_RSTCTRL); | 731 | CORE_MOD, OMAP2_RM_RSTCTRL); |
| 732 | prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); | 732 | prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
| 733 | } | 733 | } |
| 734 | 734 | ||
| 735 | static void __init prcm_setup_regs(void) | 735 | static void __init prcm_setup_regs(void) |
| @@ -916,13 +916,13 @@ static void __init prcm_setup_regs(void) | |||
| 916 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | 916 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); |
| 917 | 917 | ||
| 918 | /* Clear any pending 'reset' flags */ | 918 | /* Clear any pending 'reset' flags */ |
| 919 | prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); | 919 | prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
| 920 | prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); | 920 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); |
| 921 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); | 921 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); |
| 922 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); | 922 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); |
| 923 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); | 923 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); |
| 924 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); | 924 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); |
| 925 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); | 925 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); |
| 926 | 926 | ||
| 927 | /* Clear any pending PRCM interrupts */ | 927 | /* Clear any pending PRCM interrupts */ |
| 928 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 928 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| @@ -941,6 +941,10 @@ void omap3_pm_off_mode_enable(int enable) | |||
| 941 | else | 941 | else |
| 942 | state = PWRDM_POWER_RET; | 942 | state = PWRDM_POWER_RET; |
| 943 | 943 | ||
| 944 | #ifdef CONFIG_CPU_IDLE | ||
| 945 | omap3_cpuidle_update_states(); | ||
| 946 | #endif | ||
| 947 | |||
| 944 | list_for_each_entry(pwrst, &pwrst_list, node) { | 948 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 945 | pwrst->next_state = state; | 949 | pwrst->next_state = state; |
| 946 | set_pwrdm_state(pwrst->pwrdm, state); | 950 | set_pwrdm_state(pwrst->pwrdm, state); |
| @@ -998,6 +1002,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |||
| 998 | */ | 1002 | */ |
| 999 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | 1003 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
| 1000 | { | 1004 | { |
| 1005 | clkdm_clear_all_wkdeps(clkdm); | ||
| 1006 | clkdm_clear_all_sleepdeps(clkdm); | ||
| 1007 | |||
| 1001 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | 1008 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) |
| 1002 | omap2_clkdm_allow_idle(clkdm); | 1009 | omap2_clkdm_allow_idle(clkdm); |
| 1003 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | 1010 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
| @@ -1018,6 +1025,7 @@ void omap_push_sram_idle(void) | |||
| 1018 | static int __init omap3_pm_init(void) | 1025 | static int __init omap3_pm_init(void) |
| 1019 | { | 1026 | { |
| 1020 | struct power_state *pwrst, *tmp; | 1027 | struct power_state *pwrst, *tmp; |
| 1028 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; | ||
| 1021 | int ret; | 1029 | int ret; |
| 1022 | 1030 | ||
| 1023 | if (!cpu_is_omap34xx()) | 1031 | if (!cpu_is_omap34xx()) |
| @@ -1057,6 +1065,11 @@ static int __init omap3_pm_init(void) | |||
| 1057 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | 1065 | core_pwrdm = pwrdm_lookup("core_pwrdm"); |
| 1058 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); | 1066 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
| 1059 | 1067 | ||
| 1068 | neon_clkdm = clkdm_lookup("neon_clkdm"); | ||
| 1069 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | ||
| 1070 | per_clkdm = clkdm_lookup("per_clkdm"); | ||
| 1071 | core_clkdm = clkdm_lookup("core_clkdm"); | ||
| 1072 | |||
| 1060 | omap_push_sram_idle(); | 1073 | omap_push_sram_idle(); |
| 1061 | #ifdef CONFIG_SUSPEND | 1074 | #ifdef CONFIG_SUSPEND |
| 1062 | suspend_set_ops(&omap_pm_ops); | 1075 | suspend_set_ops(&omap_pm_ops); |
| @@ -1065,14 +1078,14 @@ static int __init omap3_pm_init(void) | |||
| 1065 | pm_idle = omap3_pm_idle; | 1078 | pm_idle = omap3_pm_idle; |
| 1066 | omap3_idle_init(); | 1079 | omap3_idle_init(); |
| 1067 | 1080 | ||
| 1068 | pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); | 1081 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
| 1069 | /* | 1082 | /* |
| 1070 | * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for | 1083 | * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for |
| 1071 | * IO-pad wakeup. Otherwise it will unnecessarily waste power | 1084 | * IO-pad wakeup. Otherwise it will unnecessarily waste power |
| 1072 | * waking up PER with every CORE wakeup - see | 1085 | * waking up PER with every CORE wakeup - see |
| 1073 | * http://marc.info/?l=linux-omap&m=121852150710062&w=2 | 1086 | * http://marc.info/?l=linux-omap&m=121852150710062&w=2 |
| 1074 | */ | 1087 | */ |
| 1075 | pwrdm_add_wkdep(per_pwrdm, core_pwrdm); | 1088 | clkdm_add_wkdep(per_clkdm, core_clkdm); |
| 1076 | 1089 | ||
| 1077 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | 1090 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
| 1078 | omap3_secure_ram_storage = | 1091 | omap3_secure_ram_storage = |
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 26b3f3ee82a3..9a0fb385622b 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
| @@ -2,10 +2,12 @@ | |||
| 2 | * OMAP powerdomain control | 2 | * OMAP powerdomain control |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2008 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * | 8 | * |
| 9 | * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> | ||
| 10 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
| @@ -26,12 +28,15 @@ | |||
| 26 | 28 | ||
| 27 | #include "cm.h" | 29 | #include "cm.h" |
| 28 | #include "cm-regbits-34xx.h" | 30 | #include "cm-regbits-34xx.h" |
| 31 | #include "cm-regbits-44xx.h" | ||
| 29 | #include "prm.h" | 32 | #include "prm.h" |
| 30 | #include "prm-regbits-34xx.h" | 33 | #include "prm-regbits-34xx.h" |
| 34 | #include "prm-regbits-44xx.h" | ||
| 31 | 35 | ||
| 32 | #include <plat/cpu.h> | 36 | #include <plat/cpu.h> |
| 33 | #include <plat/powerdomain.h> | 37 | #include <plat/powerdomain.h> |
| 34 | #include <plat/clockdomain.h> | 38 | #include <plat/clockdomain.h> |
| 39 | #include <plat/prcm.h> | ||
| 35 | 40 | ||
| 36 | #include "pm.h" | 41 | #include "pm.h" |
| 37 | 42 | ||
| @@ -40,28 +45,42 @@ enum { | |||
| 40 | PWRDM_STATE_PREV, | 45 | PWRDM_STATE_PREV, |
| 41 | }; | 46 | }; |
| 42 | 47 | ||
| 43 | /* pwrdm_list contains all registered struct powerdomains */ | 48 | /* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */ |
| 44 | static LIST_HEAD(pwrdm_list); | 49 | static u16 pwrstctrl_reg_offs; |
| 45 | 50 | ||
| 46 | /* | 51 | /* Variable holding value of the CPU dependent PWRSTST Register Offset */ |
| 47 | * pwrdm_rwlock protects pwrdm_list add and del ops - also reused to | 52 | static u16 pwrstst_reg_offs; |
| 48 | * protect pwrdm_clkdms[] during clkdm add/del ops | ||
| 49 | */ | ||
| 50 | static DEFINE_RWLOCK(pwrdm_rwlock); | ||
| 51 | 53 | ||
| 54 | /* OMAP3 and OMAP4 specific register bit initialisations | ||
| 55 | * Notice that the names here are not according to each power | ||
| 56 | * domain but the bit mapping used applies to all of them | ||
| 57 | */ | ||
| 52 | 58 | ||
| 53 | /* Private functions */ | 59 | /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ |
| 54 | 60 | #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK | |
| 55 | static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | 61 | #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK |
| 56 | { | 62 | #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK |
| 57 | u32 v; | 63 | #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK |
| 64 | #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK | ||
| 65 | |||
| 66 | /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ | ||
| 67 | #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE | ||
| 68 | #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE | ||
| 69 | #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE | ||
| 70 | #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE | ||
| 71 | #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK | ||
| 72 | |||
| 73 | /* OMAP3 and OMAP4 Memory Status bits */ | ||
| 74 | #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK | ||
| 75 | #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK | ||
| 76 | #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK | ||
| 77 | #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK | ||
| 78 | #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK | ||
| 58 | 79 | ||
| 59 | v = prm_read_mod_reg(domain, idx); | 80 | /* pwrdm_list contains all registered struct powerdomains */ |
| 60 | v &= mask; | 81 | static LIST_HEAD(pwrdm_list); |
| 61 | v >>= __ffs(mask); | ||
| 62 | 82 | ||
| 63 | return v; | 83 | /* Private functions */ |
| 64 | } | ||
| 65 | 84 | ||
| 66 | static struct powerdomain *_pwrdm_lookup(const char *name) | 85 | static struct powerdomain *_pwrdm_lookup(const char *name) |
| 67 | { | 86 | { |
| @@ -79,32 +98,63 @@ static struct powerdomain *_pwrdm_lookup(const char *name) | |||
| 79 | return pwrdm; | 98 | return pwrdm; |
| 80 | } | 99 | } |
| 81 | 100 | ||
| 82 | /* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */ | 101 | /** |
| 83 | static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm, | 102 | * _pwrdm_register - register a powerdomain |
| 84 | struct pwrdm_dep *deps) | 103 | * @pwrdm: struct powerdomain * to register |
| 104 | * | ||
| 105 | * Adds a powerdomain to the internal powerdomain list. Returns | ||
| 106 | * -EINVAL if given a null pointer, -EEXIST if a powerdomain is | ||
| 107 | * already registered by the provided name, or 0 upon success. | ||
| 108 | */ | ||
| 109 | static int _pwrdm_register(struct powerdomain *pwrdm) | ||
| 85 | { | 110 | { |
| 86 | struct pwrdm_dep *pd; | 111 | int i; |
| 112 | |||
| 113 | if (!pwrdm) | ||
| 114 | return -EINVAL; | ||
| 115 | |||
| 116 | if (!omap_chip_is(pwrdm->omap_chip)) | ||
| 117 | return -EINVAL; | ||
| 87 | 118 | ||
| 88 | if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip)) | 119 | if (_pwrdm_lookup(pwrdm->name)) |
| 89 | return ERR_PTR(-EINVAL); | 120 | return -EEXIST; |
| 90 | 121 | ||
| 91 | for (pd = deps; pd->pwrdm_name; pd++) { | 122 | list_add(&pwrdm->node, &pwrdm_list); |
| 92 | 123 | ||
| 93 | if (!omap_chip_is(pd->omap_chip)) | 124 | /* Initialize the powerdomain's state counter */ |
| 94 | continue; | 125 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) |
| 126 | pwrdm->state_counter[i] = 0; | ||
| 95 | 127 | ||
| 96 | if (!pd->pwrdm && pd->pwrdm_name) | 128 | pwrdm->ret_logic_off_counter = 0; |
| 97 | pd->pwrdm = pwrdm_lookup(pd->pwrdm_name); | 129 | for (i = 0; i < pwrdm->banks; i++) |
| 130 | pwrdm->ret_mem_off_counter[i] = 0; | ||
| 98 | 131 | ||
| 99 | if (pd->pwrdm == pwrdm) | 132 | pwrdm_wait_transition(pwrdm); |
| 100 | break; | 133 | pwrdm->state = pwrdm_read_pwrst(pwrdm); |
| 134 | pwrdm->state_counter[pwrdm->state] = 1; | ||
| 101 | 135 | ||
| 102 | } | 136 | pr_debug("powerdomain: registered %s\n", pwrdm->name); |
| 103 | 137 | ||
| 104 | if (!pd->pwrdm_name) | 138 | return 0; |
| 105 | return ERR_PTR(-ENOENT); | 139 | } |
| 106 | 140 | ||
| 107 | return pd->pwrdm; | 141 | static void _update_logic_membank_counters(struct powerdomain *pwrdm) |
| 142 | { | ||
| 143 | int i; | ||
| 144 | u8 prev_logic_pwrst, prev_mem_pwrst; | ||
| 145 | |||
| 146 | prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm); | ||
| 147 | if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) && | ||
| 148 | (prev_logic_pwrst == PWRDM_POWER_OFF)) | ||
| 149 | pwrdm->ret_logic_off_counter++; | ||
| 150 | |||
| 151 | for (i = 0; i < pwrdm->banks; i++) { | ||
| 152 | prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i); | ||
| 153 | |||
| 154 | if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) && | ||
| 155 | (prev_mem_pwrst == PWRDM_POWER_OFF)) | ||
| 156 | pwrdm->ret_mem_off_counter[i]++; | ||
| 157 | } | ||
| 108 | } | 158 | } |
| 109 | 159 | ||
| 110 | static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) | 160 | static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) |
| @@ -126,6 +176,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) | |||
| 126 | prev = pwrdm_read_prev_pwrst(pwrdm); | 176 | prev = pwrdm_read_prev_pwrst(pwrdm); |
| 127 | if (pwrdm->state != prev) | 177 | if (pwrdm->state != prev) |
| 128 | pwrdm->state_counter[prev]++; | 178 | pwrdm->state_counter[prev]++; |
| 179 | if (prev == PWRDM_POWER_RET) | ||
| 180 | _update_logic_membank_counters(pwrdm); | ||
| 129 | break; | 181 | break; |
| 130 | default: | 182 | default: |
| 131 | return -EINVAL; | 183 | return -EINVAL; |
| @@ -154,134 +206,71 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) | |||
| 154 | return 0; | 206 | return 0; |
| 155 | } | 207 | } |
| 156 | 208 | ||
| 157 | static __init void _pwrdm_setup(struct powerdomain *pwrdm) | ||
| 158 | { | ||
| 159 | int i; | ||
| 160 | |||
| 161 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) | ||
| 162 | pwrdm->state_counter[i] = 0; | ||
| 163 | |||
| 164 | pwrdm_wait_transition(pwrdm); | ||
| 165 | pwrdm->state = pwrdm_read_pwrst(pwrdm); | ||
| 166 | pwrdm->state_counter[pwrdm->state] = 1; | ||
| 167 | |||
| 168 | } | ||
| 169 | |||
| 170 | /* Public functions */ | 209 | /* Public functions */ |
| 171 | 210 | ||
| 172 | /** | 211 | /** |
| 173 | * pwrdm_init - set up the powerdomain layer | 212 | * pwrdm_init - set up the powerdomain layer |
| 213 | * @pwrdm_list: array of struct powerdomain pointers to register | ||
| 174 | * | 214 | * |
| 175 | * Loop through the list of powerdomains, registering all that are | 215 | * Loop through the array of powerdomains @pwrdm_list, registering all |
| 176 | * available on the current CPU. If pwrdm_list is supplied and not | 216 | * that are available on the current CPU. If pwrdm_list is supplied |
| 177 | * null, all of the referenced powerdomains will be registered. No | 217 | * and not null, all of the referenced powerdomains will be |
| 178 | * return value. | 218 | * registered. No return value. XXX pwrdm_list is not really a |
| 219 | * "list"; it is an array. Rename appropriately. | ||
| 179 | */ | 220 | */ |
| 180 | void pwrdm_init(struct powerdomain **pwrdm_list) | 221 | void pwrdm_init(struct powerdomain **pwrdm_list) |
| 181 | { | 222 | { |
| 182 | struct powerdomain **p = NULL; | 223 | struct powerdomain **p = NULL; |
| 183 | 224 | ||
| 184 | if (pwrdm_list) { | 225 | if (cpu_is_omap24xx() | cpu_is_omap34xx()) { |
| 185 | for (p = pwrdm_list; *p; p++) { | 226 | pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; |
| 186 | pwrdm_register(*p); | 227 | pwrstst_reg_offs = OMAP2_PM_PWSTST; |
| 187 | _pwrdm_setup(*p); | 228 | } else if (cpu_is_omap44xx()) { |
| 188 | } | 229 | pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL; |
| 230 | pwrstst_reg_offs = OMAP4_PM_PWSTST; | ||
| 231 | } else { | ||
| 232 | printk(KERN_ERR "Power Domain struct not supported for " \ | ||
| 233 | "this CPU\n"); | ||
| 234 | return; | ||
| 189 | } | 235 | } |
| 190 | } | ||
| 191 | |||
| 192 | /** | ||
| 193 | * pwrdm_register - register a powerdomain | ||
| 194 | * @pwrdm: struct powerdomain * to register | ||
| 195 | * | ||
| 196 | * Adds a powerdomain to the internal powerdomain list. Returns | ||
| 197 | * -EINVAL if given a null pointer, -EEXIST if a powerdomain is | ||
| 198 | * already registered by the provided name, or 0 upon success. | ||
| 199 | */ | ||
| 200 | int pwrdm_register(struct powerdomain *pwrdm) | ||
| 201 | { | ||
| 202 | unsigned long flags; | ||
| 203 | int ret = -EINVAL; | ||
| 204 | |||
| 205 | if (!pwrdm) | ||
| 206 | return -EINVAL; | ||
| 207 | 236 | ||
| 208 | if (!omap_chip_is(pwrdm->omap_chip)) | 237 | if (pwrdm_list) { |
| 209 | return -EINVAL; | 238 | for (p = pwrdm_list; *p; p++) |
| 210 | 239 | _pwrdm_register(*p); | |
| 211 | write_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 212 | if (_pwrdm_lookup(pwrdm->name)) { | ||
| 213 | ret = -EEXIST; | ||
| 214 | goto pr_unlock; | ||
| 215 | } | 240 | } |
| 216 | |||
| 217 | list_add(&pwrdm->node, &pwrdm_list); | ||
| 218 | |||
| 219 | pr_debug("powerdomain: registered %s\n", pwrdm->name); | ||
| 220 | ret = 0; | ||
| 221 | |||
| 222 | pr_unlock: | ||
| 223 | write_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 224 | |||
| 225 | return ret; | ||
| 226 | } | ||
| 227 | |||
| 228 | /** | ||
| 229 | * pwrdm_unregister - unregister a powerdomain | ||
| 230 | * @pwrdm: struct powerdomain * to unregister | ||
| 231 | * | ||
| 232 | * Removes a powerdomain from the internal powerdomain list. Returns | ||
| 233 | * -EINVAL if pwrdm argument is NULL. | ||
| 234 | */ | ||
| 235 | int pwrdm_unregister(struct powerdomain *pwrdm) | ||
| 236 | { | ||
| 237 | unsigned long flags; | ||
| 238 | |||
| 239 | if (!pwrdm) | ||
| 240 | return -EINVAL; | ||
| 241 | |||
| 242 | write_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 243 | list_del(&pwrdm->node); | ||
| 244 | write_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 245 | |||
| 246 | pr_debug("powerdomain: unregistered %s\n", pwrdm->name); | ||
| 247 | |||
| 248 | return 0; | ||
| 249 | } | 241 | } |
| 250 | 242 | ||
| 251 | /** | 243 | /** |
| 252 | * pwrdm_lookup - look up a powerdomain by name, return a pointer | 244 | * pwrdm_lookup - look up a powerdomain by name, return a pointer |
| 253 | * @name: name of powerdomain | 245 | * @name: name of powerdomain |
| 254 | * | 246 | * |
| 255 | * Find a registered powerdomain by its name. Returns a pointer to the | 247 | * Find a registered powerdomain by its name @name. Returns a pointer |
| 256 | * struct powerdomain if found, or NULL otherwise. | 248 | * to the struct powerdomain if found, or NULL otherwise. |
| 257 | */ | 249 | */ |
| 258 | struct powerdomain *pwrdm_lookup(const char *name) | 250 | struct powerdomain *pwrdm_lookup(const char *name) |
| 259 | { | 251 | { |
| 260 | struct powerdomain *pwrdm; | 252 | struct powerdomain *pwrdm; |
| 261 | unsigned long flags; | ||
| 262 | 253 | ||
| 263 | if (!name) | 254 | if (!name) |
| 264 | return NULL; | 255 | return NULL; |
| 265 | 256 | ||
| 266 | read_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 267 | pwrdm = _pwrdm_lookup(name); | 257 | pwrdm = _pwrdm_lookup(name); |
| 268 | read_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 269 | 258 | ||
| 270 | return pwrdm; | 259 | return pwrdm; |
| 271 | } | 260 | } |
| 272 | 261 | ||
| 273 | /** | 262 | /** |
| 274 | * pwrdm_for_each_nolock - call function on each registered clockdomain | 263 | * pwrdm_for_each - call function on each registered clockdomain |
| 275 | * @fn: callback function * | 264 | * @fn: callback function * |
| 276 | * | 265 | * |
| 277 | * Call the supplied function for each registered powerdomain. The | 266 | * Call the supplied function @fn for each registered powerdomain. |
| 278 | * callback function can return anything but 0 to bail out early from | 267 | * The callback function @fn can return anything but 0 to bail out |
| 279 | * the iterator. Returns the last return value of the callback function, which | 268 | * early from the iterator. Returns the last return value of the |
| 280 | * should be 0 for success or anything else to indicate failure; or -EINVAL if | 269 | * callback function, which should be 0 for success or anything else |
| 281 | * the function pointer is null. | 270 | * to indicate failure; or -EINVAL if the function pointer is null. |
| 282 | */ | 271 | */ |
| 283 | int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), | 272 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
| 284 | void *user) | 273 | void *user) |
| 285 | { | 274 | { |
| 286 | struct powerdomain *temp_pwrdm; | 275 | struct powerdomain *temp_pwrdm; |
| 287 | int ret = 0; | 276 | int ret = 0; |
| @@ -299,40 +288,17 @@ int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), | |||
| 299 | } | 288 | } |
| 300 | 289 | ||
| 301 | /** | 290 | /** |
| 302 | * pwrdm_for_each - call function on each registered clockdomain | ||
| 303 | * @fn: callback function * | ||
| 304 | * | ||
| 305 | * This function is the same as 'pwrdm_for_each_nolock()', but keeps the | ||
| 306 | * &pwrdm_rwlock locked for reading, so no powerdomain structure manipulation | ||
| 307 | * functions should be called from the callback, although hardware powerdomain | ||
| 308 | * control functions are fine. | ||
| 309 | */ | ||
| 310 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), | ||
| 311 | void *user) | ||
| 312 | { | ||
| 313 | unsigned long flags; | ||
| 314 | int ret; | ||
| 315 | |||
| 316 | read_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 317 | ret = pwrdm_for_each_nolock(fn, user); | ||
| 318 | read_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 319 | |||
| 320 | return ret; | ||
| 321 | } | ||
| 322 | |||
| 323 | /** | ||
| 324 | * pwrdm_add_clkdm - add a clockdomain to a powerdomain | 291 | * pwrdm_add_clkdm - add a clockdomain to a powerdomain |
| 325 | * @pwrdm: struct powerdomain * to add the clockdomain to | 292 | * @pwrdm: struct powerdomain * to add the clockdomain to |
| 326 | * @clkdm: struct clockdomain * to associate with a powerdomain | 293 | * @clkdm: struct clockdomain * to associate with a powerdomain |
| 327 | * | 294 | * |
| 328 | * Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'. This | 295 | * Associate the clockdomain @clkdm with a powerdomain @pwrdm. This |
| 329 | * enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if | 296 | * enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if |
| 330 | * presented with invalid pointers; -ENOMEM if memory could not be allocated; | 297 | * presented with invalid pointers; -ENOMEM if memory could not be allocated; |
| 331 | * or 0 upon success. | 298 | * or 0 upon success. |
| 332 | */ | 299 | */ |
| 333 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | 300 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) |
| 334 | { | 301 | { |
| 335 | unsigned long flags; | ||
| 336 | int i; | 302 | int i; |
| 337 | int ret = -EINVAL; | 303 | int ret = -EINVAL; |
| 338 | 304 | ||
| @@ -342,8 +308,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | |||
| 342 | pr_debug("powerdomain: associating clockdomain %s with powerdomain " | 308 | pr_debug("powerdomain: associating clockdomain %s with powerdomain " |
| 343 | "%s\n", clkdm->name, pwrdm->name); | 309 | "%s\n", clkdm->name, pwrdm->name); |
| 344 | 310 | ||
| 345 | write_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 346 | |||
| 347 | for (i = 0; i < PWRDM_MAX_CLKDMS; i++) { | 311 | for (i = 0; i < PWRDM_MAX_CLKDMS; i++) { |
| 348 | if (!pwrdm->pwrdm_clkdms[i]) | 312 | if (!pwrdm->pwrdm_clkdms[i]) |
| 349 | break; | 313 | break; |
| @@ -368,8 +332,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | |||
| 368 | ret = 0; | 332 | ret = 0; |
| 369 | 333 | ||
| 370 | pac_exit: | 334 | pac_exit: |
| 371 | write_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 372 | |||
| 373 | return ret; | 335 | return ret; |
| 374 | } | 336 | } |
| 375 | 337 | ||
| @@ -378,14 +340,13 @@ pac_exit: | |||
| 378 | * @pwrdm: struct powerdomain * to add the clockdomain to | 340 | * @pwrdm: struct powerdomain * to add the clockdomain to |
| 379 | * @clkdm: struct clockdomain * to associate with a powerdomain | 341 | * @clkdm: struct clockdomain * to associate with a powerdomain |
| 380 | * | 342 | * |
| 381 | * Dissociate the clockdomain 'clkdm' from the powerdomain | 343 | * Dissociate the clockdomain @clkdm from the powerdomain |
| 382 | * 'pwrdm'. Returns -EINVAL if presented with invalid pointers; | 344 | * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT |
| 383 | * -ENOENT if the clkdm was not associated with the powerdomain, or 0 | 345 | * if @clkdm was not associated with the powerdomain, or 0 upon |
| 384 | * upon success. | 346 | * success. |
| 385 | */ | 347 | */ |
| 386 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | 348 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) |
| 387 | { | 349 | { |
| 388 | unsigned long flags; | ||
| 389 | int ret = -EINVAL; | 350 | int ret = -EINVAL; |
| 390 | int i; | 351 | int i; |
| 391 | 352 | ||
| @@ -395,8 +356,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | |||
| 395 | pr_debug("powerdomain: dissociating clockdomain %s from powerdomain " | 356 | pr_debug("powerdomain: dissociating clockdomain %s from powerdomain " |
| 396 | "%s\n", clkdm->name, pwrdm->name); | 357 | "%s\n", clkdm->name, pwrdm->name); |
| 397 | 358 | ||
| 398 | write_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 399 | |||
| 400 | for (i = 0; i < PWRDM_MAX_CLKDMS; i++) | 359 | for (i = 0; i < PWRDM_MAX_CLKDMS; i++) |
| 401 | if (pwrdm->pwrdm_clkdms[i] == clkdm) | 360 | if (pwrdm->pwrdm_clkdms[i] == clkdm) |
| 402 | break; | 361 | break; |
| @@ -413,8 +372,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | |||
| 413 | ret = 0; | 372 | ret = 0; |
| 414 | 373 | ||
| 415 | pdc_exit: | 374 | pdc_exit: |
| 416 | write_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 417 | |||
| 418 | return ret; | 375 | return ret; |
| 419 | } | 376 | } |
| 420 | 377 | ||
| @@ -423,259 +380,34 @@ pdc_exit: | |||
| 423 | * @pwrdm: struct powerdomain * to iterate over | 380 | * @pwrdm: struct powerdomain * to iterate over |
| 424 | * @fn: callback function * | 381 | * @fn: callback function * |
| 425 | * | 382 | * |
| 426 | * Call the supplied function for each clockdomain in the powerdomain | 383 | * Call the supplied function @fn for each clockdomain in the powerdomain |
| 427 | * 'pwrdm'. The callback function can return anything but 0 to bail | 384 | * @pwrdm. The callback function can return anything but 0 to bail |
| 428 | * out early from the iterator. The callback function is called with | 385 | * out early from the iterator. Returns -EINVAL if presented with |
| 429 | * the pwrdm_rwlock held for reading, so no powerdomain structure | 386 | * invalid pointers; or passes along the last return value of the |
| 430 | * manipulation functions should be called from the callback, although | 387 | * callback function, which should be 0 for success or anything else |
| 431 | * hardware powerdomain control functions are fine. Returns -EINVAL | 388 | * to indicate failure. |
| 432 | * if presented with invalid pointers; or passes along the last return | ||
| 433 | * value of the callback function, which should be 0 for success or | ||
| 434 | * anything else to indicate failure. | ||
| 435 | */ | 389 | */ |
| 436 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | 390 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, |
| 437 | int (*fn)(struct powerdomain *pwrdm, | 391 | int (*fn)(struct powerdomain *pwrdm, |
| 438 | struct clockdomain *clkdm)) | 392 | struct clockdomain *clkdm)) |
| 439 | { | 393 | { |
| 440 | unsigned long flags; | ||
| 441 | int ret = 0; | 394 | int ret = 0; |
| 442 | int i; | 395 | int i; |
| 443 | 396 | ||
| 444 | if (!fn) | 397 | if (!fn) |
| 445 | return -EINVAL; | 398 | return -EINVAL; |
| 446 | 399 | ||
| 447 | read_lock_irqsave(&pwrdm_rwlock, flags); | ||
| 448 | |||
| 449 | for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) | 400 | for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) |
| 450 | ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); | 401 | ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); |
| 451 | 402 | ||
| 452 | read_unlock_irqrestore(&pwrdm_rwlock, flags); | ||
| 453 | |||
| 454 | return ret; | 403 | return ret; |
| 455 | } | 404 | } |
| 456 | 405 | ||
| 457 | |||
| 458 | /** | ||
| 459 | * pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1 | ||
| 460 | * @pwrdm1: wake this struct powerdomain * up (dependent) | ||
| 461 | * @pwrdm2: when this struct powerdomain * wakes up (source) | ||
| 462 | * | ||
| 463 | * When the powerdomain represented by pwrdm2 wakes up (due to an | ||
| 464 | * interrupt), wake up pwrdm1. Implemented in hardware on the OMAP, | ||
| 465 | * this feature is designed to reduce wakeup latency of the dependent | ||
| 466 | * powerdomain. Returns -EINVAL if presented with invalid powerdomain | ||
| 467 | * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or | ||
| 468 | * 0 upon success. | ||
| 469 | */ | ||
| 470 | int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | ||
| 471 | { | ||
| 472 | struct powerdomain *p; | ||
| 473 | |||
| 474 | if (!pwrdm1) | ||
| 475 | return -EINVAL; | ||
| 476 | |||
| 477 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs); | ||
| 478 | if (IS_ERR(p)) { | ||
| 479 | pr_debug("powerdomain: hardware cannot set/clear wake up of " | ||
| 480 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); | ||
| 481 | return PTR_ERR(p); | ||
| 482 | } | ||
| 483 | |||
| 484 | pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n", | ||
| 485 | pwrdm1->name, pwrdm2->name); | ||
| 486 | |||
| 487 | prm_set_mod_reg_bits((1 << pwrdm2->dep_bit), | ||
| 488 | pwrdm1->prcm_offs, PM_WKDEP); | ||
| 489 | |||
| 490 | return 0; | ||
| 491 | } | ||
| 492 | |||
| 493 | /** | ||
| 494 | * pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1 | ||
| 495 | * @pwrdm1: wake this struct powerdomain * up (dependent) | ||
| 496 | * @pwrdm2: when this struct powerdomain * wakes up (source) | ||
| 497 | * | ||
| 498 | * Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2 | ||
| 499 | * wakes up. Returns -EINVAL if presented with invalid powerdomain | ||
| 500 | * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or | ||
| 501 | * 0 upon success. | ||
| 502 | */ | ||
| 503 | int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | ||
| 504 | { | ||
| 505 | struct powerdomain *p; | ||
| 506 | |||
| 507 | if (!pwrdm1) | ||
| 508 | return -EINVAL; | ||
| 509 | |||
| 510 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs); | ||
| 511 | if (IS_ERR(p)) { | ||
| 512 | pr_debug("powerdomain: hardware cannot set/clear wake up of " | ||
| 513 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); | ||
| 514 | return PTR_ERR(p); | ||
| 515 | } | ||
| 516 | |||
| 517 | pr_debug("powerdomain: hardware will no longer wake up %s after %s " | ||
| 518 | "wakes up\n", pwrdm1->name, pwrdm2->name); | ||
| 519 | |||
| 520 | prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit), | ||
| 521 | pwrdm1->prcm_offs, PM_WKDEP); | ||
| 522 | |||
| 523 | return 0; | ||
| 524 | } | ||
| 525 | |||
| 526 | /** | ||
| 527 | * pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1 | ||
| 528 | * @pwrdm1: wake this struct powerdomain * up (dependent) | ||
| 529 | * @pwrdm2: when this struct powerdomain * wakes up (source) | ||
| 530 | * | ||
| 531 | * Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be | ||
| 532 | * awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL | ||
| 533 | * if either powerdomain pointer is invalid; or -ENOENT if the hardware | ||
| 534 | * is incapable. | ||
| 535 | * | ||
| 536 | * REVISIT: Currently this function only represents software-controllable | ||
| 537 | * wakeup dependencies. Wakeup dependencies fixed in hardware are not | ||
| 538 | * yet handled here. | ||
| 539 | */ | ||
| 540 | int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | ||
| 541 | { | ||
| 542 | struct powerdomain *p; | ||
| 543 | |||
| 544 | if (!pwrdm1) | ||
| 545 | return -EINVAL; | ||
| 546 | |||
| 547 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs); | ||
| 548 | if (IS_ERR(p)) { | ||
| 549 | pr_debug("powerdomain: hardware cannot set/clear wake up of " | ||
| 550 | "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); | ||
| 551 | return PTR_ERR(p); | ||
| 552 | } | ||
| 553 | |||
| 554 | return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP, | ||
| 555 | (1 << pwrdm2->dep_bit)); | ||
| 556 | } | ||
| 557 | |||
| 558 | /** | ||
| 559 | * pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1 | ||
| 560 | * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent) | ||
| 561 | * @pwrdm2: when this struct powerdomain * is active (source) | ||
| 562 | * | ||
| 563 | * Prevent pwrdm1 from automatically going inactive (and then to | ||
| 564 | * retention or off) if pwrdm2 is still active. Returns -EINVAL if | ||
| 565 | * presented with invalid powerdomain pointers or called on a machine | ||
| 566 | * that does not support software-configurable hardware sleep dependencies, | ||
| 567 | * -ENOENT if the specified dependency cannot be set in hardware, or | ||
| 568 | * 0 upon success. | ||
| 569 | */ | ||
| 570 | int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | ||
| 571 | { | ||
| 572 | struct powerdomain *p; | ||
| 573 | |||
| 574 | if (!cpu_is_omap34xx()) | ||
| 575 | return -EINVAL; | ||
| 576 | |||
| 577 | if (!pwrdm1) | ||
| 578 | return -EINVAL; | ||
| 579 | |||
| 580 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); | ||
| 581 | if (IS_ERR(p)) { | ||
| 582 | pr_debug("powerdomain: hardware cannot set/clear sleep " | ||
| 583 | "dependency affecting %s from %s\n", pwrdm1->name, | ||
| 584 | pwrdm2->name); | ||
| 585 | return PTR_ERR(p); | ||
| 586 | } | ||
| 587 | |||
| 588 | pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n", | ||
| 589 | pwrdm1->name, pwrdm2->name); | ||
| 590 | |||
| 591 | cm_set_mod_reg_bits((1 << pwrdm2->dep_bit), | ||
| 592 | pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP); | ||
| 593 | |||
| 594 | return 0; | ||
| 595 | } | ||
| 596 | |||
| 597 | /** | ||
| 598 | * pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1 | ||
| 599 | * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent) | ||
| 600 | * @pwrdm2: when this struct powerdomain * is active (source) | ||
| 601 | * | ||
| 602 | * Allow pwrdm1 to automatically go inactive (and then to retention or | ||
| 603 | * off), independent of the activity state of pwrdm2. Returns -EINVAL | ||
| 604 | * if presented with invalid powerdomain pointers or called on a machine | ||
| 605 | * that does not support software-configurable hardware sleep dependencies, | ||
| 606 | * -ENOENT if the specified dependency cannot be cleared in hardware, or | ||
| 607 | * 0 upon success. | ||
| 608 | */ | ||
| 609 | int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | ||
| 610 | { | ||
| 611 | struct powerdomain *p; | ||
| 612 | |||
| 613 | if (!cpu_is_omap34xx()) | ||
| 614 | return -EINVAL; | ||
| 615 | |||
| 616 | if (!pwrdm1) | ||
| 617 | return -EINVAL; | ||
| 618 | |||
| 619 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); | ||
| 620 | if (IS_ERR(p)) { | ||
| 621 | pr_debug("powerdomain: hardware cannot set/clear sleep " | ||
| 622 | "dependency affecting %s from %s\n", pwrdm1->name, | ||
| 623 | pwrdm2->name); | ||
| 624 | return PTR_ERR(p); | ||
| 625 | } | ||
| 626 | |||
| 627 | pr_debug("powerdomain: will no longer prevent %s from sleeping if " | ||
| 628 | "%s is active\n", pwrdm1->name, pwrdm2->name); | ||
| 629 | |||
| 630 | cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit), | ||
| 631 | pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP); | ||
| 632 | |||
| 633 | return 0; | ||
| 634 | } | ||
| 635 | |||
| 636 | /** | ||
| 637 | * pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1 | ||
| 638 | * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent) | ||
| 639 | * @pwrdm2: when this struct powerdomain * is active (source) | ||
| 640 | * | ||
| 641 | * Return 1 if a hardware sleep dependency exists wherein pwrdm1 will | ||
| 642 | * not be allowed to automatically go inactive if pwrdm2 is active; | ||
| 643 | * 0 if pwrdm1's automatic power state inactivity transition is independent | ||
| 644 | * of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called | ||
| 645 | * on a machine that does not support software-configurable hardware sleep | ||
| 646 | * dependencies; or -ENOENT if the hardware is incapable. | ||
| 647 | * | ||
| 648 | * REVISIT: Currently this function only represents software-controllable | ||
| 649 | * sleep dependencies. Sleep dependencies fixed in hardware are not | ||
| 650 | * yet handled here. | ||
| 651 | */ | ||
| 652 | int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) | ||
| 653 | { | ||
| 654 | struct powerdomain *p; | ||
| 655 | |||
| 656 | if (!cpu_is_omap34xx()) | ||
| 657 | return -EINVAL; | ||
| 658 | |||
| 659 | if (!pwrdm1) | ||
| 660 | return -EINVAL; | ||
| 661 | |||
| 662 | p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); | ||
| 663 | if (IS_ERR(p)) { | ||
| 664 | pr_debug("powerdomain: hardware cannot set/clear sleep " | ||
| 665 | "dependency affecting %s from %s\n", pwrdm1->name, | ||
| 666 | pwrdm2->name); | ||
| 667 | return PTR_ERR(p); | ||
| 668 | } | ||
| 669 | |||
| 670 | return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP, | ||
| 671 | (1 << pwrdm2->dep_bit)); | ||
| 672 | } | ||
| 673 | |||
| 674 | /** | 406 | /** |
| 675 | * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain | 407 | * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain |
| 676 | * @pwrdm: struct powerdomain * | 408 | * @pwrdm: struct powerdomain * |
| 677 | * | 409 | * |
| 678 | * Return the number of controllable memory banks in powerdomain pwrdm, | 410 | * Return the number of controllable memory banks in powerdomain @pwrdm, |
| 679 | * starting with 1. Returns -EINVAL if the powerdomain pointer is null. | 411 | * starting with 1. Returns -EINVAL if the powerdomain pointer is null. |
| 680 | */ | 412 | */ |
| 681 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) | 413 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) |
| @@ -691,7 +423,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) | |||
| 691 | * @pwrdm: struct powerdomain * to set | 423 | * @pwrdm: struct powerdomain * to set |
| 692 | * @pwrst: one of the PWRDM_POWER_* macros | 424 | * @pwrst: one of the PWRDM_POWER_* macros |
| 693 | * | 425 | * |
| 694 | * Set the powerdomain pwrdm's next power state to pwrst. The powerdomain | 426 | * Set the powerdomain @pwrdm's next power state to @pwrst. The powerdomain |
| 695 | * may not enter this state immediately if the preconditions for this state | 427 | * may not enter this state immediately if the preconditions for this state |
| 696 | * have not been satisfied. Returns -EINVAL if the powerdomain pointer is | 428 | * have not been satisfied. Returns -EINVAL if the powerdomain pointer is |
| 697 | * null or if the power state is invalid for the powerdomin, or returns 0 | 429 | * null or if the power state is invalid for the powerdomin, or returns 0 |
| @@ -710,7 +442,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 710 | 442 | ||
| 711 | prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | 443 | prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, |
| 712 | (pwrst << OMAP_POWERSTATE_SHIFT), | 444 | (pwrst << OMAP_POWERSTATE_SHIFT), |
| 713 | pwrdm->prcm_offs, PM_PWSTCTRL); | 445 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
| 714 | 446 | ||
| 715 | return 0; | 447 | return 0; |
| 716 | } | 448 | } |
| @@ -719,7 +451,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 719 | * pwrdm_read_next_pwrst - get next powerdomain power state | 451 | * pwrdm_read_next_pwrst - get next powerdomain power state |
| 720 | * @pwrdm: struct powerdomain * to get power state | 452 | * @pwrdm: struct powerdomain * to get power state |
| 721 | * | 453 | * |
| 722 | * Return the powerdomain pwrdm's next power state. Returns -EINVAL | 454 | * Return the powerdomain @pwrdm's next power state. Returns -EINVAL |
| 723 | * if the powerdomain pointer is null or returns the next power state | 455 | * if the powerdomain pointer is null or returns the next power state |
| 724 | * upon success. | 456 | * upon success. |
| 725 | */ | 457 | */ |
| @@ -728,15 +460,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | |||
| 728 | if (!pwrdm) | 460 | if (!pwrdm) |
| 729 | return -EINVAL; | 461 | return -EINVAL; |
| 730 | 462 | ||
| 731 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL, | 463 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 732 | OMAP_POWERSTATE_MASK); | 464 | pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK); |
| 733 | } | 465 | } |
| 734 | 466 | ||
| 735 | /** | 467 | /** |
| 736 | * pwrdm_read_pwrst - get current powerdomain power state | 468 | * pwrdm_read_pwrst - get current powerdomain power state |
| 737 | * @pwrdm: struct powerdomain * to get power state | 469 | * @pwrdm: struct powerdomain * to get power state |
| 738 | * | 470 | * |
| 739 | * Return the powerdomain pwrdm's current power state. Returns -EINVAL | 471 | * Return the powerdomain @pwrdm's current power state. Returns -EINVAL |
| 740 | * if the powerdomain pointer is null or returns the current power state | 472 | * if the powerdomain pointer is null or returns the current power state |
| 741 | * upon success. | 473 | * upon success. |
| 742 | */ | 474 | */ |
| @@ -745,15 +477,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) | |||
| 745 | if (!pwrdm) | 477 | if (!pwrdm) |
| 746 | return -EINVAL; | 478 | return -EINVAL; |
| 747 | 479 | ||
| 748 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, | 480 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 749 | OMAP_POWERSTATEST_MASK); | 481 | pwrstst_reg_offs, OMAP_POWERSTATEST_MASK); |
| 750 | } | 482 | } |
| 751 | 483 | ||
| 752 | /** | 484 | /** |
| 753 | * pwrdm_read_prev_pwrst - get previous powerdomain power state | 485 | * pwrdm_read_prev_pwrst - get previous powerdomain power state |
| 754 | * @pwrdm: struct powerdomain * to get previous power state | 486 | * @pwrdm: struct powerdomain * to get previous power state |
| 755 | * | 487 | * |
| 756 | * Return the powerdomain pwrdm's previous power state. Returns -EINVAL | 488 | * Return the powerdomain @pwrdm's previous power state. Returns -EINVAL |
| 757 | * if the powerdomain pointer is null or returns the previous power state | 489 | * if the powerdomain pointer is null or returns the previous power state |
| 758 | * upon success. | 490 | * upon success. |
| 759 | */ | 491 | */ |
| @@ -771,11 +503,11 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | |||
| 771 | * @pwrdm: struct powerdomain * to set | 503 | * @pwrdm: struct powerdomain * to set |
| 772 | * @pwrst: one of the PWRDM_POWER_* macros | 504 | * @pwrst: one of the PWRDM_POWER_* macros |
| 773 | * | 505 | * |
| 774 | * Set the next power state that the logic portion of the powerdomain | 506 | * Set the next power state @pwrst that the logic portion of the |
| 775 | * pwrdm will enter when the powerdomain enters retention. This will | 507 | * powerdomain @pwrdm will enter when the powerdomain enters retention. |
| 776 | * be either RETENTION or OFF, if supported. Returns -EINVAL if the | 508 | * This will be either RETENTION or OFF, if supported. Returns |
| 777 | * powerdomain pointer is null or the target power state is not not | 509 | * -EINVAL if the powerdomain pointer is null or the target power |
| 778 | * supported, or returns 0 upon success. | 510 | * state is not not supported, or returns 0 upon success. |
| 779 | */ | 511 | */ |
| 780 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | 512 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) |
| 781 | { | 513 | { |
| @@ -796,7 +528,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 796 | */ | 528 | */ |
| 797 | prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, | 529 | prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, |
| 798 | (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), | 530 | (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), |
| 799 | pwrdm->prcm_offs, PM_PWSTCTRL); | 531 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
| 800 | 532 | ||
| 801 | return 0; | 533 | return 0; |
| 802 | } | 534 | } |
| @@ -807,13 +539,14 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 807 | * @bank: memory bank number to set (0-3) | 539 | * @bank: memory bank number to set (0-3) |
| 808 | * @pwrst: one of the PWRDM_POWER_* macros | 540 | * @pwrst: one of the PWRDM_POWER_* macros |
| 809 | * | 541 | * |
| 810 | * Set the next power state that memory bank x of the powerdomain | 542 | * Set the next power state @pwrst that memory bank @bank of the |
| 811 | * pwrdm will enter when the powerdomain enters the ON state. Bank | 543 | * powerdomain @pwrdm will enter when the powerdomain enters the ON |
| 812 | * will be a number from 0 to 3, and represents different types of | 544 | * state. @bank will be a number from 0 to 3, and represents different |
| 813 | * memory, depending on the powerdomain. Returns -EINVAL if the | 545 | * types of memory, depending on the powerdomain. Returns -EINVAL if |
| 814 | * powerdomain pointer is null or the target power state is not not | 546 | * the powerdomain pointer is null or the target power state is not |
| 815 | * supported for this memory bank, -EEXIST if the target memory bank | 547 | * not supported for this memory bank, -EEXIST if the target memory |
| 816 | * does not exist or is not controllable, or returns 0 upon success. | 548 | * bank does not exist or is not controllable, or returns 0 upon |
| 549 | * success. | ||
| 817 | */ | 550 | */ |
| 818 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | 551 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) |
| 819 | { | 552 | { |
| @@ -839,16 +572,19 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 839 | */ | 572 | */ |
| 840 | switch (bank) { | 573 | switch (bank) { |
| 841 | case 0: | 574 | case 0: |
| 842 | m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK; | 575 | m = OMAP_MEM0_ONSTATE_MASK; |
| 843 | break; | 576 | break; |
| 844 | case 1: | 577 | case 1: |
| 845 | m = OMAP3430_L1FLATMEMONSTATE_MASK; | 578 | m = OMAP_MEM1_ONSTATE_MASK; |
| 846 | break; | 579 | break; |
| 847 | case 2: | 580 | case 2: |
| 848 | m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK; | 581 | m = OMAP_MEM2_ONSTATE_MASK; |
| 849 | break; | 582 | break; |
| 850 | case 3: | 583 | case 3: |
| 851 | m = OMAP3430_L2FLATMEMONSTATE_MASK; | 584 | m = OMAP_MEM3_ONSTATE_MASK; |
| 585 | break; | ||
| 586 | case 4: | ||
| 587 | m = OMAP_MEM4_ONSTATE_MASK; | ||
| 852 | break; | 588 | break; |
| 853 | default: | 589 | default: |
| 854 | WARN_ON(1); /* should never happen */ | 590 | WARN_ON(1); /* should never happen */ |
| @@ -856,7 +592,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 856 | } | 592 | } |
| 857 | 593 | ||
| 858 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), | 594 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), |
| 859 | pwrdm->prcm_offs, PM_PWSTCTRL); | 595 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
| 860 | 596 | ||
| 861 | return 0; | 597 | return 0; |
| 862 | } | 598 | } |
| @@ -867,14 +603,15 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 867 | * @bank: memory bank number to set (0-3) | 603 | * @bank: memory bank number to set (0-3) |
| 868 | * @pwrst: one of the PWRDM_POWER_* macros | 604 | * @pwrst: one of the PWRDM_POWER_* macros |
| 869 | * | 605 | * |
| 870 | * Set the next power state that memory bank x of the powerdomain | 606 | * Set the next power state @pwrst that memory bank @bank of the |
| 871 | * pwrdm will enter when the powerdomain enters the RETENTION state. | 607 | * powerdomain @pwrdm will enter when the powerdomain enters the |
| 872 | * Bank will be a number from 0 to 3, and represents different types | 608 | * RETENTION state. Bank will be a number from 0 to 3, and represents |
| 873 | * of memory, depending on the powerdomain. pwrst will be either | 609 | * different types of memory, depending on the powerdomain. @pwrst |
| 874 | * RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain | 610 | * will be either RETENTION or OFF, if supported. Returns -EINVAL if |
| 875 | * pointer is null or the target power state is not not supported for | 611 | * the powerdomain pointer is null or the target power state is not |
| 876 | * this memory bank, -EEXIST if the target memory bank does not exist | 612 | * not supported for this memory bank, -EEXIST if the target memory |
| 877 | * or is not controllable, or returns 0 upon success. | 613 | * bank does not exist or is not controllable, or returns 0 upon |
| 614 | * success. | ||
| 878 | */ | 615 | */ |
| 879 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | 616 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) |
| 880 | { | 617 | { |
| @@ -900,16 +637,19 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 900 | */ | 637 | */ |
| 901 | switch (bank) { | 638 | switch (bank) { |
| 902 | case 0: | 639 | case 0: |
| 903 | m = OMAP3430_SHAREDL1CACHEFLATRETSTATE; | 640 | m = OMAP_MEM0_RETSTATE_MASK; |
| 904 | break; | 641 | break; |
| 905 | case 1: | 642 | case 1: |
| 906 | m = OMAP3430_L1FLATMEMRETSTATE; | 643 | m = OMAP_MEM1_RETSTATE_MASK; |
| 907 | break; | 644 | break; |
| 908 | case 2: | 645 | case 2: |
| 909 | m = OMAP3430_SHAREDL2CACHEFLATRETSTATE; | 646 | m = OMAP_MEM2_RETSTATE_MASK; |
| 910 | break; | 647 | break; |
| 911 | case 3: | 648 | case 3: |
| 912 | m = OMAP3430_L2FLATMEMRETSTATE; | 649 | m = OMAP_MEM3_RETSTATE_MASK; |
| 650 | break; | ||
| 651 | case 4: | ||
| 652 | m = OMAP_MEM4_RETSTATE_MASK; | ||
| 913 | break; | 653 | break; |
| 914 | default: | 654 | default: |
| 915 | WARN_ON(1); /* should never happen */ | 655 | WARN_ON(1); /* should never happen */ |
| @@ -917,7 +657,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 917 | } | 657 | } |
| 918 | 658 | ||
| 919 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | 659 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, |
| 920 | PM_PWSTCTRL); | 660 | pwrstctrl_reg_offs); |
| 921 | 661 | ||
| 922 | return 0; | 662 | return 0; |
| 923 | } | 663 | } |
| @@ -926,27 +666,27 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 926 | * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state | 666 | * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state |
| 927 | * @pwrdm: struct powerdomain * to get current logic retention power state | 667 | * @pwrdm: struct powerdomain * to get current logic retention power state |
| 928 | * | 668 | * |
| 929 | * Return the current power state that the logic portion of | 669 | * Return the power state that the logic portion of powerdomain @pwrdm |
| 930 | * powerdomain pwrdm will enter | 670 | * will enter when the powerdomain enters retention. Returns -EINVAL |
| 931 | * Returns -EINVAL if the powerdomain pointer is null or returns the | 671 | * if the powerdomain pointer is null or returns the logic retention |
| 932 | * current logic retention power state upon success. | 672 | * power state upon success. |
| 933 | */ | 673 | */ |
| 934 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | 674 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) |
| 935 | { | 675 | { |
| 936 | if (!pwrdm) | 676 | if (!pwrdm) |
| 937 | return -EINVAL; | 677 | return -EINVAL; |
| 938 | 678 | ||
| 939 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, | 679 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 940 | OMAP3430_LOGICSTATEST); | 680 | pwrstst_reg_offs, OMAP3430_LOGICSTATEST); |
| 941 | } | 681 | } |
| 942 | 682 | ||
| 943 | /** | 683 | /** |
| 944 | * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state | 684 | * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state |
| 945 | * @pwrdm: struct powerdomain * to get previous logic power state | 685 | * @pwrdm: struct powerdomain * to get previous logic power state |
| 946 | * | 686 | * |
| 947 | * Return the powerdomain pwrdm's logic power state. Returns -EINVAL | 687 | * Return the powerdomain @pwrdm's previous logic power state. Returns |
| 948 | * if the powerdomain pointer is null or returns the previous logic | 688 | * -EINVAL if the powerdomain pointer is null or returns the previous |
| 949 | * power state upon success. | 689 | * logic power state upon success. |
| 950 | */ | 690 | */ |
| 951 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | 691 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) |
| 952 | { | 692 | { |
| @@ -964,12 +704,35 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | |||
| 964 | } | 704 | } |
| 965 | 705 | ||
| 966 | /** | 706 | /** |
| 707 | * pwrdm_read_logic_retst - get next powerdomain logic power state | ||
| 708 | * @pwrdm: struct powerdomain * to get next logic power state | ||
| 709 | * | ||
| 710 | * Return the powerdomain pwrdm's logic power state. Returns -EINVAL | ||
| 711 | * if the powerdomain pointer is null or returns the next logic | ||
| 712 | * power state upon success. | ||
| 713 | */ | ||
| 714 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
| 715 | { | ||
| 716 | if (!pwrdm) | ||
| 717 | return -EINVAL; | ||
| 718 | |||
| 719 | /* | ||
| 720 | * The register bit names below may not correspond to the | ||
| 721 | * actual names of the bits in each powerdomain's register, | ||
| 722 | * but the type of value returned is the same for each | ||
| 723 | * powerdomain. | ||
| 724 | */ | ||
| 725 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, | ||
| 726 | OMAP3430_LOGICSTATEST); | ||
| 727 | } | ||
| 728 | |||
| 729 | /** | ||
| 967 | * pwrdm_read_mem_pwrst - get current memory bank power state | 730 | * pwrdm_read_mem_pwrst - get current memory bank power state |
| 968 | * @pwrdm: struct powerdomain * to get current memory bank power state | 731 | * @pwrdm: struct powerdomain * to get current memory bank power state |
| 969 | * @bank: memory bank number (0-3) | 732 | * @bank: memory bank number (0-3) |
| 970 | * | 733 | * |
| 971 | * Return the powerdomain pwrdm's current memory power state for bank | 734 | * Return the powerdomain @pwrdm's current memory power state for bank |
| 972 | * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if | 735 | * @bank. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if |
| 973 | * the target memory bank does not exist or is not controllable, or | 736 | * the target memory bank does not exist or is not controllable, or |
| 974 | * returns the current memory power state upon success. | 737 | * returns the current memory power state upon success. |
| 975 | */ | 738 | */ |
| @@ -994,23 +757,27 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
| 994 | */ | 757 | */ |
| 995 | switch (bank) { | 758 | switch (bank) { |
| 996 | case 0: | 759 | case 0: |
| 997 | m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK; | 760 | m = OMAP_MEM0_STATEST_MASK; |
| 998 | break; | 761 | break; |
| 999 | case 1: | 762 | case 1: |
| 1000 | m = OMAP3430_L1FLATMEMSTATEST_MASK; | 763 | m = OMAP_MEM1_STATEST_MASK; |
| 1001 | break; | 764 | break; |
| 1002 | case 2: | 765 | case 2: |
| 1003 | m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK; | 766 | m = OMAP_MEM2_STATEST_MASK; |
| 1004 | break; | 767 | break; |
| 1005 | case 3: | 768 | case 3: |
| 1006 | m = OMAP3430_L2FLATMEMSTATEST_MASK; | 769 | m = OMAP_MEM3_STATEST_MASK; |
| 770 | break; | ||
| 771 | case 4: | ||
| 772 | m = OMAP_MEM4_STATEST_MASK; | ||
| 1007 | break; | 773 | break; |
| 1008 | default: | 774 | default: |
| 1009 | WARN_ON(1); /* should never happen */ | 775 | WARN_ON(1); /* should never happen */ |
| 1010 | return -EEXIST; | 776 | return -EEXIST; |
| 1011 | } | 777 | } |
| 1012 | 778 | ||
| 1013 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m); | 779 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 780 | pwrstst_reg_offs, m); | ||
| 1014 | } | 781 | } |
| 1015 | 782 | ||
| 1016 | /** | 783 | /** |
| @@ -1018,10 +785,11 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
| 1018 | * @pwrdm: struct powerdomain * to get previous memory bank power state | 785 | * @pwrdm: struct powerdomain * to get previous memory bank power state |
| 1019 | * @bank: memory bank number (0-3) | 786 | * @bank: memory bank number (0-3) |
| 1020 | * | 787 | * |
| 1021 | * Return the powerdomain pwrdm's previous memory power state for bank | 788 | * Return the powerdomain @pwrdm's previous memory power state for |
| 1022 | * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if | 789 | * bank @bank. Returns -EINVAL if the powerdomain pointer is null, |
| 1023 | * the target memory bank does not exist or is not controllable, or | 790 | * -EEXIST if the target memory bank does not exist or is not |
| 1024 | * returns the previous memory power state upon success. | 791 | * controllable, or returns the previous memory power state upon |
| 792 | * success. | ||
| 1025 | */ | 793 | */ |
| 1026 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | 794 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) |
| 1027 | { | 795 | { |
| @@ -1065,13 +833,63 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
| 1065 | } | 833 | } |
| 1066 | 834 | ||
| 1067 | /** | 835 | /** |
| 836 | * pwrdm_read_mem_retst - get next memory bank power state | ||
| 837 | * @pwrdm: struct powerdomain * to get mext memory bank power state | ||
| 838 | * @bank: memory bank number (0-3) | ||
| 839 | * | ||
| 840 | * Return the powerdomain pwrdm's next memory power state for bank | ||
| 841 | * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if | ||
| 842 | * the target memory bank does not exist or is not controllable, or | ||
| 843 | * returns the next memory power state upon success. | ||
| 844 | */ | ||
| 845 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
| 846 | { | ||
| 847 | u32 m; | ||
| 848 | |||
| 849 | if (!pwrdm) | ||
| 850 | return -EINVAL; | ||
| 851 | |||
| 852 | if (pwrdm->banks < (bank + 1)) | ||
| 853 | return -EEXIST; | ||
| 854 | |||
| 855 | /* | ||
| 856 | * The register bit names below may not correspond to the | ||
| 857 | * actual names of the bits in each powerdomain's register, | ||
| 858 | * but the type of value returned is the same for each | ||
| 859 | * powerdomain. | ||
| 860 | */ | ||
| 861 | switch (bank) { | ||
| 862 | case 0: | ||
| 863 | m = OMAP_MEM0_RETSTATE_MASK; | ||
| 864 | break; | ||
| 865 | case 1: | ||
| 866 | m = OMAP_MEM1_RETSTATE_MASK; | ||
| 867 | break; | ||
| 868 | case 2: | ||
| 869 | m = OMAP_MEM2_RETSTATE_MASK; | ||
| 870 | break; | ||
| 871 | case 3: | ||
| 872 | m = OMAP_MEM3_RETSTATE_MASK; | ||
| 873 | break; | ||
| 874 | case 4: | ||
| 875 | m = OMAP_MEM4_RETSTATE_MASK; | ||
| 876 | default: | ||
| 877 | WARN_ON(1); /* should never happen */ | ||
| 878 | return -EEXIST; | ||
| 879 | } | ||
| 880 | |||
| 881 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 882 | pwrstctrl_reg_offs, m); | ||
| 883 | } | ||
| 884 | |||
| 885 | /** | ||
| 1068 | * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm | 886 | * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm |
| 1069 | * @pwrdm: struct powerdomain * to clear | 887 | * @pwrdm: struct powerdomain * to clear |
| 1070 | * | 888 | * |
| 1071 | * Clear the powerdomain's previous power state register. Clears the | 889 | * Clear the powerdomain's previous power state register @pwrdm. |
| 1072 | * entire register, including logic and memory bank previous power states. | 890 | * Clears the entire register, including logic and memory bank |
| 1073 | * Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon | 891 | * previous power states. Returns -EINVAL if the powerdomain pointer |
| 1074 | * success. | 892 | * is null, or returns 0 upon success. |
| 1075 | */ | 893 | */ |
| 1076 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | 894 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) |
| 1077 | { | 895 | { |
| @@ -1096,11 +914,11 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | |||
| 1096 | * @pwrdm: struct powerdomain * | 914 | * @pwrdm: struct powerdomain * |
| 1097 | * | 915 | * |
| 1098 | * Enable automatic context save-and-restore upon power state change | 916 | * Enable automatic context save-and-restore upon power state change |
| 1099 | * for some devices in a powerdomain. Warning: this only affects a | 917 | * for some devices in the powerdomain @pwrdm. Warning: this only |
| 1100 | * subset of devices in a powerdomain; check the TRM closely. Returns | 918 | * affects a subset of devices in a powerdomain; check the TRM |
| 1101 | * -EINVAL if the powerdomain pointer is null or if the powerdomain | 919 | * closely. Returns -EINVAL if the powerdomain pointer is null or if |
| 1102 | * does not support automatic save-and-restore, or returns 0 upon | 920 | * the powerdomain does not support automatic save-and-restore, or |
| 1103 | * success. | 921 | * returns 0 upon success. |
| 1104 | */ | 922 | */ |
| 1105 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | 923 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) |
| 1106 | { | 924 | { |
| @@ -1114,7 +932,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | |||
| 1114 | pwrdm->name); | 932 | pwrdm->name); |
| 1115 | 933 | ||
| 1116 | prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, | 934 | prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
| 1117 | pwrdm->prcm_offs, PM_PWSTCTRL); | 935 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
| 1118 | 936 | ||
| 1119 | return 0; | 937 | return 0; |
| 1120 | } | 938 | } |
| @@ -1124,11 +942,11 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | |||
| 1124 | * @pwrdm: struct powerdomain * | 942 | * @pwrdm: struct powerdomain * |
| 1125 | * | 943 | * |
| 1126 | * Disable automatic context save-and-restore upon power state change | 944 | * Disable automatic context save-and-restore upon power state change |
| 1127 | * for some devices in a powerdomain. Warning: this only affects a | 945 | * for some devices in the powerdomain @pwrdm. Warning: this only |
| 1128 | * subset of devices in a powerdomain; check the TRM closely. Returns | 946 | * affects a subset of devices in a powerdomain; check the TRM |
| 1129 | * -EINVAL if the powerdomain pointer is null or if the powerdomain | 947 | * closely. Returns -EINVAL if the powerdomain pointer is null or if |
| 1130 | * does not support automatic save-and-restore, or returns 0 upon | 948 | * the powerdomain does not support automatic save-and-restore, or |
| 1131 | * success. | 949 | * returns 0 upon success. |
| 1132 | */ | 950 | */ |
| 1133 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | 951 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) |
| 1134 | { | 952 | { |
| @@ -1142,7 +960,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | |||
| 1142 | pwrdm->name); | 960 | pwrdm->name); |
| 1143 | 961 | ||
| 1144 | prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, | 962 | prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, |
| 1145 | pwrdm->prcm_offs, PM_PWSTCTRL); | 963 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
| 1146 | 964 | ||
| 1147 | return 0; | 965 | return 0; |
| 1148 | } | 966 | } |
| @@ -1151,7 +969,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | |||
| 1151 | * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR | 969 | * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR |
| 1152 | * @pwrdm: struct powerdomain * | 970 | * @pwrdm: struct powerdomain * |
| 1153 | * | 971 | * |
| 1154 | * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore | 972 | * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore |
| 1155 | * for some devices, or 0 if it does not. | 973 | * for some devices, or 0 if it does not. |
| 1156 | */ | 974 | */ |
| 1157 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) | 975 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) |
| @@ -1163,7 +981,7 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) | |||
| 1163 | * pwrdm_wait_transition - wait for powerdomain power transition to finish | 981 | * pwrdm_wait_transition - wait for powerdomain power transition to finish |
| 1164 | * @pwrdm: struct powerdomain * to wait for | 982 | * @pwrdm: struct powerdomain * to wait for |
| 1165 | * | 983 | * |
| 1166 | * If the powerdomain pwrdm is in the process of a state transition, | 984 | * If the powerdomain @pwrdm is in the process of a state transition, |
| 1167 | * spin until it completes the power transition, or until an iteration | 985 | * spin until it completes the power transition, or until an iteration |
| 1168 | * bailout value is reached. Returns -EINVAL if the powerdomain | 986 | * bailout value is reached. Returns -EINVAL if the powerdomain |
| 1169 | * pointer is null, -EAGAIN if the bailout value was reached, or | 987 | * pointer is null, -EAGAIN if the bailout value was reached, or |
| @@ -1183,10 +1001,10 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) | |||
| 1183 | */ | 1001 | */ |
| 1184 | 1002 | ||
| 1185 | /* XXX Is this udelay() value meaningful? */ | 1003 | /* XXX Is this udelay() value meaningful? */ |
| 1186 | while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) & | 1004 | while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & |
| 1187 | OMAP_INTRANSITION) && | 1005 | OMAP_INTRANSITION) && |
| 1188 | (c++ < PWRDM_TRANSITION_BAILOUT)) | 1006 | (c++ < PWRDM_TRANSITION_BAILOUT)) |
| 1189 | udelay(1); | 1007 | udelay(1); |
| 1190 | 1008 | ||
| 1191 | if (c > PWRDM_TRANSITION_BAILOUT) { | 1009 | if (c > PWRDM_TRANSITION_BAILOUT) { |
| 1192 | printk(KERN_ERR "powerdomain: waited too long for " | 1010 | printk(KERN_ERR "powerdomain: waited too long for " |
| @@ -1213,12 +1031,6 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm) | |||
| 1213 | 1031 | ||
| 1214 | return -EINVAL; | 1032 | return -EINVAL; |
| 1215 | } | 1033 | } |
| 1216 | int pwrdm_clk_state_switch(struct clk *clk) | ||
| 1217 | { | ||
| 1218 | if (clk != NULL && clk->clkdm != NULL) | ||
| 1219 | return pwrdm_clkdm_state_switch(clk->clkdm); | ||
| 1220 | return -EINVAL; | ||
| 1221 | } | ||
| 1222 | 1034 | ||
| 1223 | int pwrdm_pre_transition(void) | 1035 | int pwrdm_pre_transition(void) |
| 1224 | { | 1036 | { |
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 057b2e3e2c35..105cbcaefd3b 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP2/3 common powerdomain definitions | 2 | * OMAP2/3 common powerdomain definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-8 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-8 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * Debugging and integration fixes by Jouni Högander | 8 | * Debugging and integration fixes by Jouni Högander |
| @@ -12,26 +12,21 @@ | |||
| 12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | /* | ||
| 16 | * To Do List | ||
| 17 | * -> Move the Sleep/Wakeup dependencies from Power Domain framework to | ||
| 18 | * Clock Domain Framework | ||
| 19 | */ | ||
| 20 | |||
| 15 | #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS | 21 | #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS |
| 16 | #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS | 22 | #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS |
| 17 | 23 | ||
| 18 | /* | 24 | /* |
| 19 | * This file contains all of the powerdomains that have some element | 25 | * This file contains all of the powerdomains that have some element |
| 20 | * of software control for the OMAP24xx and OMAP34XX chips. | 26 | * of software control for the OMAP24xx and OMAP34xx chips. |
| 21 | * | ||
| 22 | * A few notes: | ||
| 23 | * | 27 | * |
| 24 | * This is not an exhaustive listing of powerdomains on the chips; only | 28 | * This is not an exhaustive listing of powerdomains on the chips; only |
| 25 | * powerdomains that can be controlled in software. | 29 | * powerdomains that can be controlled in software. |
| 26 | * | ||
| 27 | * A useful validation rule for struct powerdomain: | ||
| 28 | * Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array | ||
| 29 | * must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really | ||
| 30 | * just software-controllable dependencies. Non-software-controllable | ||
| 31 | * dependencies do exist, but they are not encoded below (yet). | ||
| 32 | * | ||
| 33 | * 24xx does not support programmable sleep dependencies (SLEEPDEP) | ||
| 34 | * | ||
| 35 | */ | 30 | */ |
| 36 | 31 | ||
| 37 | /* | 32 | /* |
| @@ -41,26 +36,17 @@ | |||
| 41 | * | 36 | * |
| 42 | * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its | 37 | * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its |
| 43 | * powerdomain is called the "DSP power domain." On the 2430, the | 38 | * powerdomain is called the "DSP power domain." On the 2430, the |
| 44 | * on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its | 39 | * on-board DSP is a 'C64 DSP, now called (along with its hardware |
| 45 | * powerdomain is still called the "DSP power domain." On the 3430, | 40 | * accelerators) the IVA2 or IVA2.1. Its powerdomain is still called |
| 46 | * the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but | 41 | * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the |
| 47 | * its powerdomain is now called the "IVA2 power domain." | 42 | * 2430, also known as the IVA2; but its powerdomain is now called the |
| 43 | * "IVA2 power domain." | ||
| 48 | * | 44 | * |
| 49 | * The 2420 also has something called the IVA, which is a separate ARM | 45 | * The 2420 also has something called the IVA, which is a separate ARM |
| 50 | * core, and has nothing to do with the DSP/IVA2. | 46 | * core, and has nothing to do with the DSP/IVA2. |
| 51 | * | 47 | * |
| 52 | * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM | 48 | * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM |
| 53 | * address offset is different between the C55 and C64 DSPs. | 49 | * address offset is different between the C55 and C64 DSPs. |
| 54 | * | ||
| 55 | * The overly-specific dep_bit names are due to a bit name collision | ||
| 56 | * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift | ||
| 57 | * value are the same for all powerdomains: 2 | ||
| 58 | */ | ||
| 59 | |||
| 60 | /* | ||
| 61 | * XXX should dep_bit be a mask, so we can test to see if it is 0 as a | ||
| 62 | * sanity check? | ||
| 63 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE | ||
| 64 | */ | 50 | */ |
| 65 | 51 | ||
| 66 | #include <plat/powerdomain.h> | 52 | #include <plat/powerdomain.h> |
| @@ -68,69 +54,23 @@ | |||
| 68 | #include "prcm-common.h" | 54 | #include "prcm-common.h" |
| 69 | #include "prm.h" | 55 | #include "prm.h" |
| 70 | #include "cm.h" | 56 | #include "cm.h" |
| 71 | |||
| 72 | /* OMAP2/3-common powerdomains and wakeup dependencies */ | ||
| 73 | |||
| 74 | /* | ||
| 75 | * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP | ||
| 76 | * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE | ||
| 77 | * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE | ||
| 78 | */ | ||
| 79 | static struct pwrdm_dep gfx_sgx_wkdeps[] = { | ||
| 80 | { | ||
| 81 | .pwrdm_name = "core_pwrdm", | ||
| 82 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 83 | }, | ||
| 84 | { | ||
| 85 | .pwrdm_name = "iva2_pwrdm", | ||
| 86 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 87 | }, | ||
| 88 | { | ||
| 89 | .pwrdm_name = "mpu_pwrdm", | ||
| 90 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | ||
| 91 | CHIP_IS_OMAP3430) | ||
| 92 | }, | ||
| 93 | { | ||
| 94 | .pwrdm_name = "wkup_pwrdm", | ||
| 95 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | ||
| 96 | CHIP_IS_OMAP3430) | ||
| 97 | }, | ||
| 98 | { NULL }, | ||
| 99 | }; | ||
| 100 | |||
| 101 | /* | ||
| 102 | * 3430: CM_SLEEPDEP_CAM: MPU | ||
| 103 | * 3430ES1: CM_SLEEPDEP_GFX: MPU | ||
| 104 | * 3430ES2: CM_SLEEPDEP_SGX: MPU | ||
| 105 | */ | ||
| 106 | static struct pwrdm_dep cam_gfx_sleepdeps[] = { | ||
| 107 | { | ||
| 108 | .pwrdm_name = "mpu_pwrdm", | ||
| 109 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 110 | }, | ||
| 111 | { NULL }, | ||
| 112 | }; | ||
| 113 | |||
| 114 | |||
| 115 | #include "powerdomains24xx.h" | 57 | #include "powerdomains24xx.h" |
| 116 | #include "powerdomains34xx.h" | 58 | #include "powerdomains34xx.h" |
| 59 | #include "powerdomains44xx.h" | ||
| 117 | 60 | ||
| 61 | /* OMAP2/3-common powerdomains */ | ||
| 118 | 62 | ||
| 119 | /* | 63 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 120 | * OMAP2/3 common powerdomains | ||
| 121 | */ | ||
| 122 | 64 | ||
| 123 | /* | 65 | /* |
| 124 | * The GFX powerdomain is not present on 3430ES2, but currently we do not | 66 | * The GFX powerdomain is not present on 3430ES2, but currently we do not |
| 125 | * have a macro to filter it out at compile-time. | 67 | * have a macro to filter it out at compile-time. |
| 126 | */ | 68 | */ |
| 127 | static struct powerdomain gfx_pwrdm = { | 69 | static struct powerdomain gfx_omap2_pwrdm = { |
| 128 | .name = "gfx_pwrdm", | 70 | .name = "gfx_pwrdm", |
| 129 | .prcm_offs = GFX_MOD, | 71 | .prcm_offs = GFX_MOD, |
| 130 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | 72 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | |
| 131 | CHIP_IS_OMAP3430ES1), | 73 | CHIP_IS_OMAP3430ES1), |
| 132 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
| 133 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
| 134 | .pwrsts = PWRSTS_OFF_RET_ON, | 74 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 135 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 75 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 136 | .banks = 1, | 76 | .banks = 1, |
| @@ -142,22 +82,24 @@ static struct powerdomain gfx_pwrdm = { | |||
| 142 | }, | 82 | }, |
| 143 | }; | 83 | }; |
| 144 | 84 | ||
| 145 | static struct powerdomain wkup_pwrdm = { | 85 | static struct powerdomain wkup_omap2_pwrdm = { |
| 146 | .name = "wkup_pwrdm", | 86 | .name = "wkup_pwrdm", |
| 147 | .prcm_offs = WKUP_MOD, | 87 | .prcm_offs = WKUP_MOD, |
| 148 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 88 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 149 | .dep_bit = OMAP_EN_WKUP_SHIFT, | ||
| 150 | }; | 89 | }; |
| 151 | 90 | ||
| 91 | #endif | ||
| 152 | 92 | ||
| 153 | 93 | ||
| 154 | /* As powerdomains are added or removed above, this list must also be changed */ | 94 | /* As powerdomains are added or removed above, this list must also be changed */ |
| 155 | static struct powerdomain *powerdomains_omap[] __initdata = { | 95 | static struct powerdomain *powerdomains_omap[] __initdata = { |
| 156 | 96 | ||
| 157 | &gfx_pwrdm, | 97 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 158 | &wkup_pwrdm, | 98 | &wkup_omap2_pwrdm, |
| 99 | &gfx_omap2_pwrdm, | ||
| 100 | #endif | ||
| 159 | 101 | ||
| 160 | #ifdef CONFIG_ARCH_OMAP24XX | 102 | #ifdef CONFIG_ARCH_OMAP2 |
| 161 | &dsp_pwrdm, | 103 | &dsp_pwrdm, |
| 162 | &mpu_24xx_pwrdm, | 104 | &mpu_24xx_pwrdm, |
| 163 | &core_24xx_pwrdm, | 105 | &core_24xx_pwrdm, |
| @@ -167,12 +109,12 @@ static struct powerdomain *powerdomains_omap[] __initdata = { | |||
| 167 | &mdm_pwrdm, | 109 | &mdm_pwrdm, |
| 168 | #endif | 110 | #endif |
| 169 | 111 | ||
| 170 | #ifdef CONFIG_ARCH_OMAP34XX | 112 | #ifdef CONFIG_ARCH_OMAP3 |
| 171 | &iva2_pwrdm, | 113 | &iva2_pwrdm, |
| 172 | &mpu_34xx_pwrdm, | 114 | &mpu_3xxx_pwrdm, |
| 173 | &neon_pwrdm, | 115 | &neon_pwrdm, |
| 174 | &core_34xx_pre_es3_1_pwrdm, | 116 | &core_3xxx_pre_es3_1_pwrdm, |
| 175 | &core_34xx_es3_1_pwrdm, | 117 | &core_3xxx_es3_1_pwrdm, |
| 176 | &cam_pwrdm, | 118 | &cam_pwrdm, |
| 177 | &dss_pwrdm, | 119 | &dss_pwrdm, |
| 178 | &per_pwrdm, | 120 | &per_pwrdm, |
| @@ -186,6 +128,24 @@ static struct powerdomain *powerdomains_omap[] __initdata = { | |||
| 186 | &dpll5_pwrdm, | 128 | &dpll5_pwrdm, |
| 187 | #endif | 129 | #endif |
| 188 | 130 | ||
| 131 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 132 | &core_44xx_pwrdm, | ||
| 133 | &gfx_44xx_pwrdm, | ||
| 134 | &abe_44xx_pwrdm, | ||
| 135 | &dss_44xx_pwrdm, | ||
| 136 | &tesla_44xx_pwrdm, | ||
| 137 | &wkup_44xx_pwrdm, | ||
| 138 | &cpu0_44xx_pwrdm, | ||
| 139 | &cpu1_44xx_pwrdm, | ||
| 140 | &emu_44xx_pwrdm, | ||
| 141 | &mpu_44xx_pwrdm, | ||
| 142 | &ivahd_44xx_pwrdm, | ||
| 143 | &cam_44xx_pwrdm, | ||
| 144 | &l3init_44xx_pwrdm, | ||
| 145 | &l4per_44xx_pwrdm, | ||
| 146 | &always_on_core_44xx_pwrdm, | ||
| 147 | &cefuse_44xx_pwrdm, | ||
| 148 | #endif | ||
| 189 | NULL | 149 | NULL |
| 190 | }; | 150 | }; |
| 191 | 151 | ||
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h index bd249a495aa9..775093add9b6 100644 --- a/arch/arm/mach-omap2/powerdomains24xx.h +++ b/arch/arm/mach-omap2/powerdomains24xx.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * OMAP24XX powerdomain definitions | 2 | * OMAP24XX powerdomain definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2008 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * Debugging and integration fixes by Jouni Högander | 8 | * Debugging and integration fixes by Jouni Högander |
| @@ -30,83 +30,7 @@ | |||
| 30 | 30 | ||
| 31 | /* 24XX powerdomains and dependencies */ | 31 | /* 24XX powerdomains and dependencies */ |
| 32 | 32 | ||
| 33 | #ifdef CONFIG_ARCH_OMAP24XX | 33 | #ifdef CONFIG_ARCH_OMAP2 |
| 34 | |||
| 35 | |||
| 36 | /* Wakeup dependency source arrays */ | ||
| 37 | |||
| 38 | /* | ||
| 39 | * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP | ||
| 40 | * 2430 PM_WKDEP_MDM: same as above | ||
| 41 | */ | ||
| 42 | static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = { | ||
| 43 | { | ||
| 44 | .pwrdm_name = "core_pwrdm", | ||
| 45 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 46 | }, | ||
| 47 | { | ||
| 48 | .pwrdm_name = "mpu_pwrdm", | ||
| 49 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 50 | }, | ||
| 51 | { | ||
| 52 | .pwrdm_name = "wkup_pwrdm", | ||
| 53 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 54 | }, | ||
| 55 | { NULL }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | /* | ||
| 59 | * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP | ||
| 60 | * 2430 adds MDM | ||
| 61 | */ | ||
| 62 | static struct pwrdm_dep mpu_24xx_wkdeps[] = { | ||
| 63 | { | ||
| 64 | .pwrdm_name = "core_pwrdm", | ||
| 65 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 66 | }, | ||
| 67 | { | ||
| 68 | .pwrdm_name = "dsp_pwrdm", | ||
| 69 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 70 | }, | ||
| 71 | { | ||
| 72 | .pwrdm_name = "wkup_pwrdm", | ||
| 73 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 74 | }, | ||
| 75 | { | ||
| 76 | .pwrdm_name = "mdm_pwrdm", | ||
| 77 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | ||
| 78 | }, | ||
| 79 | { NULL }, | ||
| 80 | }; | ||
| 81 | |||
| 82 | /* | ||
| 83 | * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP | ||
| 84 | * 2430 adds MDM | ||
| 85 | */ | ||
| 86 | static struct pwrdm_dep core_24xx_wkdeps[] = { | ||
| 87 | { | ||
| 88 | .pwrdm_name = "dsp_pwrdm", | ||
| 89 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 90 | }, | ||
| 91 | { | ||
| 92 | .pwrdm_name = "gfx_pwrdm", | ||
| 93 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .pwrdm_name = "mpu_pwrdm", | ||
| 97 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 98 | }, | ||
| 99 | { | ||
| 100 | .pwrdm_name = "wkup_pwrdm", | ||
| 101 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | ||
| 102 | }, | ||
| 103 | { | ||
| 104 | .pwrdm_name = "mdm_pwrdm", | ||
| 105 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | ||
| 106 | }, | ||
| 107 | { NULL }, | ||
| 108 | }; | ||
| 109 | |||
| 110 | 34 | ||
| 111 | /* Powerdomains */ | 35 | /* Powerdomains */ |
| 112 | 36 | ||
| @@ -114,8 +38,6 @@ static struct powerdomain dsp_pwrdm = { | |||
| 114 | .name = "dsp_pwrdm", | 38 | .name = "dsp_pwrdm", |
| 115 | .prcm_offs = OMAP24XX_DSP_MOD, | 39 | .prcm_offs = OMAP24XX_DSP_MOD, |
| 116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 40 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| 117 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, | ||
| 118 | .wkdep_srcs = dsp_mdm_24xx_wkdeps, | ||
| 119 | .pwrsts = PWRSTS_OFF_RET_ON, | 41 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 120 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 42 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 121 | .banks = 1, | 43 | .banks = 1, |
| @@ -131,8 +53,6 @@ static struct powerdomain mpu_24xx_pwrdm = { | |||
| 131 | .name = "mpu_pwrdm", | 53 | .name = "mpu_pwrdm", |
| 132 | .prcm_offs = MPU_MOD, | 54 | .prcm_offs = MPU_MOD, |
| 133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 55 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| 134 | .dep_bit = OMAP24XX_EN_MPU_SHIFT, | ||
| 135 | .wkdep_srcs = mpu_24xx_wkdeps, | ||
| 136 | .pwrsts = PWRSTS_OFF_RET_ON, | 56 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 137 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 57 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 138 | .banks = 1, | 58 | .banks = 1, |
| @@ -148,9 +68,7 @@ static struct powerdomain core_24xx_pwrdm = { | |||
| 148 | .name = "core_pwrdm", | 68 | .name = "core_pwrdm", |
| 149 | .prcm_offs = CORE_MOD, | 69 | .prcm_offs = CORE_MOD, |
| 150 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 70 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| 151 | .wkdep_srcs = core_24xx_wkdeps, | ||
| 152 | .pwrsts = PWRSTS_OFF_RET_ON, | 71 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 153 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, | ||
| 154 | .banks = 3, | 72 | .banks = 3, |
| 155 | .pwrsts_mem_ret = { | 73 | .pwrsts_mem_ret = { |
| 156 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 74 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
| @@ -164,7 +82,7 @@ static struct powerdomain core_24xx_pwrdm = { | |||
| 164 | }, | 82 | }, |
| 165 | }; | 83 | }; |
| 166 | 84 | ||
| 167 | #endif /* CONFIG_ARCH_OMAP24XX */ | 85 | #endif /* CONFIG_ARCH_OMAP2 */ |
| 168 | 86 | ||
| 169 | 87 | ||
| 170 | 88 | ||
| @@ -176,13 +94,10 @@ static struct powerdomain core_24xx_pwrdm = { | |||
| 176 | 94 | ||
| 177 | /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ | 95 | /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ |
| 178 | 96 | ||
| 179 | /* Another case of bit name collisions between several registers: EN_MDM */ | ||
| 180 | static struct powerdomain mdm_pwrdm = { | 97 | static struct powerdomain mdm_pwrdm = { |
| 181 | .name = "mdm_pwrdm", | 98 | .name = "mdm_pwrdm", |
| 182 | .prcm_offs = OMAP2430_MDM_MOD, | 99 | .prcm_offs = OMAP2430_MDM_MOD, |
| 183 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 184 | .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, | ||
| 185 | .wkdep_srcs = dsp_mdm_24xx_wkdeps, | ||
| 186 | .pwrsts = PWRSTS_OFF_RET_ON, | 101 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 187 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 102 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 188 | .banks = 1, | 103 | .banks = 1, |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 588f7e07d0ea..bd87112beea8 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP34XX powerdomain definitions | 2 | * OMAP3 powerdomain definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2008 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * Debugging and integration fixes by Jouni Högander | 8 | * Debugging and integration fixes by Jouni Högander |
| @@ -32,128 +32,7 @@ | |||
| 32 | * 34XX-specific powerdomains, dependencies | 32 | * 34XX-specific powerdomains, dependencies |
| 33 | */ | 33 | */ |
| 34 | 34 | ||
| 35 | #ifdef CONFIG_ARCH_OMAP34XX | 35 | #ifdef CONFIG_ARCH_OMAP3 |
| 36 | |||
| 37 | /* | ||
| 38 | * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP | ||
| 39 | * (USBHOST is ES2 only) | ||
| 40 | */ | ||
| 41 | static struct pwrdm_dep per_usbhost_wkdeps[] = { | ||
| 42 | { | ||
| 43 | .pwrdm_name = "core_pwrdm", | ||
| 44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 45 | }, | ||
| 46 | { | ||
| 47 | .pwrdm_name = "iva2_pwrdm", | ||
| 48 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 49 | }, | ||
| 50 | { | ||
| 51 | .pwrdm_name = "mpu_pwrdm", | ||
| 52 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 53 | }, | ||
| 54 | { | ||
| 55 | .pwrdm_name = "wkup_pwrdm", | ||
| 56 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 57 | }, | ||
| 58 | { NULL }, | ||
| 59 | }; | ||
| 60 | |||
| 61 | /* | ||
| 62 | * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER | ||
| 63 | */ | ||
| 64 | static struct pwrdm_dep mpu_34xx_wkdeps[] = { | ||
| 65 | { | ||
| 66 | .pwrdm_name = "core_pwrdm", | ||
| 67 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 68 | }, | ||
| 69 | { | ||
| 70 | .pwrdm_name = "iva2_pwrdm", | ||
| 71 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 72 | }, | ||
| 73 | { | ||
| 74 | .pwrdm_name = "dss_pwrdm", | ||
| 75 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 76 | }, | ||
| 77 | { | ||
| 78 | .pwrdm_name = "per_pwrdm", | ||
| 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 80 | }, | ||
| 81 | { NULL }, | ||
| 82 | }; | ||
| 83 | |||
| 84 | /* | ||
| 85 | * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER | ||
| 86 | */ | ||
| 87 | static struct pwrdm_dep iva2_wkdeps[] = { | ||
| 88 | { | ||
| 89 | .pwrdm_name = "core_pwrdm", | ||
| 90 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 91 | }, | ||
| 92 | { | ||
| 93 | .pwrdm_name = "mpu_pwrdm", | ||
| 94 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 95 | }, | ||
| 96 | { | ||
| 97 | .pwrdm_name = "wkup_pwrdm", | ||
| 98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 99 | }, | ||
| 100 | { | ||
| 101 | .pwrdm_name = "dss_pwrdm", | ||
| 102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 103 | }, | ||
| 104 | { | ||
| 105 | .pwrdm_name = "per_pwrdm", | ||
| 106 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 107 | }, | ||
| 108 | { NULL }, | ||
| 109 | }; | ||
| 110 | |||
| 111 | |||
| 112 | /* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */ | ||
| 113 | static struct pwrdm_dep cam_dss_wkdeps[] = { | ||
| 114 | { | ||
| 115 | .pwrdm_name = "iva2_pwrdm", | ||
| 116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 117 | }, | ||
| 118 | { | ||
| 119 | .pwrdm_name = "mpu_pwrdm", | ||
| 120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 121 | }, | ||
| 122 | { | ||
| 123 | .pwrdm_name = "wkup_pwrdm", | ||
| 124 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 125 | }, | ||
| 126 | { NULL }, | ||
| 127 | }; | ||
| 128 | |||
| 129 | /* 3430: PM_WKDEP_NEON: MPU */ | ||
| 130 | static struct pwrdm_dep neon_wkdeps[] = { | ||
| 131 | { | ||
| 132 | .pwrdm_name = "mpu_pwrdm", | ||
| 133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 134 | }, | ||
| 135 | { NULL }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | |||
| 139 | /* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */ | ||
| 140 | |||
| 141 | /* | ||
| 142 | * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA | ||
| 143 | * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA | ||
| 144 | */ | ||
| 145 | static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = { | ||
| 146 | { | ||
| 147 | .pwrdm_name = "mpu_pwrdm", | ||
| 148 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 149 | }, | ||
| 150 | { | ||
| 151 | .pwrdm_name = "iva2_pwrdm", | ||
| 152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 153 | }, | ||
| 154 | { NULL }, | ||
| 155 | }; | ||
| 156 | |||
| 157 | 36 | ||
| 158 | /* | 37 | /* |
| 159 | * Powerdomains | 38 | * Powerdomains |
| @@ -163,8 +42,6 @@ static struct powerdomain iva2_pwrdm = { | |||
| 163 | .name = "iva2_pwrdm", | 42 | .name = "iva2_pwrdm", |
| 164 | .prcm_offs = OMAP3430_IVA2_MOD, | 43 | .prcm_offs = OMAP3430_IVA2_MOD, |
| 165 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 166 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, | ||
| 167 | .wkdep_srcs = iva2_wkdeps, | ||
| 168 | .pwrsts = PWRSTS_OFF_RET_ON, | 45 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 169 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 46 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 170 | .banks = 4, | 47 | .banks = 4, |
| @@ -182,12 +59,10 @@ static struct powerdomain iva2_pwrdm = { | |||
| 182 | }, | 59 | }, |
| 183 | }; | 60 | }; |
| 184 | 61 | ||
| 185 | static struct powerdomain mpu_34xx_pwrdm = { | 62 | static struct powerdomain mpu_3xxx_pwrdm = { |
| 186 | .name = "mpu_pwrdm", | 63 | .name = "mpu_pwrdm", |
| 187 | .prcm_offs = MPU_MOD, | 64 | .prcm_offs = MPU_MOD, |
| 188 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 65 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 189 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | ||
| 190 | .wkdep_srcs = mpu_34xx_wkdeps, | ||
| 191 | .pwrsts = PWRSTS_OFF_RET_ON, | 66 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 192 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 67 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 193 | .flags = PWRDM_HAS_MPU_QUIRK, | 68 | .flags = PWRDM_HAS_MPU_QUIRK, |
| @@ -200,15 +75,14 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
| 200 | }, | 75 | }, |
| 201 | }; | 76 | }; |
| 202 | 77 | ||
| 203 | /* No wkdeps or sleepdeps for 34xx core apparently */ | 78 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { |
| 204 | static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | ||
| 205 | .name = "core_pwrdm", | 79 | .name = "core_pwrdm", |
| 206 | .prcm_offs = CORE_MOD, | 80 | .prcm_offs = CORE_MOD, |
| 207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | 81 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | |
| 208 | CHIP_IS_OMAP3430ES2 | | 82 | CHIP_IS_OMAP3430ES2 | |
| 209 | CHIP_IS_OMAP3430ES3_0), | 83 | CHIP_IS_OMAP3430ES3_0), |
| 210 | .pwrsts = PWRSTS_OFF_RET_ON, | 84 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 211 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 85 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 212 | .banks = 2, | 86 | .banks = 2, |
| 213 | .pwrsts_mem_ret = { | 87 | .pwrsts_mem_ret = { |
| 214 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 88 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
| @@ -220,13 +94,12 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | |||
| 220 | }, | 94 | }, |
| 221 | }; | 95 | }; |
| 222 | 96 | ||
| 223 | /* No wkdeps or sleepdeps for 34xx core apparently */ | 97 | static struct powerdomain core_3xxx_es3_1_pwrdm = { |
| 224 | static struct powerdomain core_34xx_es3_1_pwrdm = { | ||
| 225 | .name = "core_pwrdm", | 98 | .name = "core_pwrdm", |
| 226 | .prcm_offs = CORE_MOD, | 99 | .prcm_offs = CORE_MOD, |
| 227 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), |
| 228 | .pwrsts = PWRSTS_OFF_RET_ON, | 101 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 229 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 102 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 230 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 103 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
| 231 | .banks = 2, | 104 | .banks = 2, |
| 232 | .pwrsts_mem_ret = { | 105 | .pwrsts_mem_ret = { |
| @@ -239,14 +112,10 @@ static struct powerdomain core_34xx_es3_1_pwrdm = { | |||
| 239 | }, | 112 | }, |
| 240 | }; | 113 | }; |
| 241 | 114 | ||
| 242 | /* Another case of bit name collisions between several registers: EN_DSS */ | ||
| 243 | static struct powerdomain dss_pwrdm = { | 115 | static struct powerdomain dss_pwrdm = { |
| 244 | .name = "dss_pwrdm", | 116 | .name = "dss_pwrdm", |
| 245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 117 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 246 | .prcm_offs = OMAP3430_DSS_MOD, | 118 | .prcm_offs = OMAP3430_DSS_MOD, |
| 247 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | ||
| 248 | .wkdep_srcs = cam_dss_wkdeps, | ||
| 249 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
| 250 | .pwrsts = PWRSTS_OFF_RET_ON, | 119 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 251 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 120 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 252 | .banks = 1, | 121 | .banks = 1, |
| @@ -267,8 +136,6 @@ static struct powerdomain sgx_pwrdm = { | |||
| 267 | .name = "sgx_pwrdm", | 136 | .name = "sgx_pwrdm", |
| 268 | .prcm_offs = OMAP3430ES2_SGX_MOD, | 137 | .prcm_offs = OMAP3430ES2_SGX_MOD, |
| 269 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 138 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 270 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
| 271 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
| 272 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ | 139 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ |
| 273 | .pwrsts = PWRSTS_OFF_ON, | 140 | .pwrsts = PWRSTS_OFF_ON, |
| 274 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 141 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| @@ -285,8 +152,6 @@ static struct powerdomain cam_pwrdm = { | |||
| 285 | .name = "cam_pwrdm", | 152 | .name = "cam_pwrdm", |
| 286 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 287 | .prcm_offs = OMAP3430_CAM_MOD, | 154 | .prcm_offs = OMAP3430_CAM_MOD, |
| 288 | .wkdep_srcs = cam_dss_wkdeps, | ||
| 289 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
| 290 | .pwrsts = PWRSTS_OFF_RET_ON, | 155 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 291 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 156 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 292 | .banks = 1, | 157 | .banks = 1, |
| @@ -302,9 +167,6 @@ static struct powerdomain per_pwrdm = { | |||
| 302 | .name = "per_pwrdm", | 167 | .name = "per_pwrdm", |
| 303 | .prcm_offs = OMAP3430_PER_MOD, | 168 | .prcm_offs = OMAP3430_PER_MOD, |
| 304 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 305 | .dep_bit = OMAP3430_EN_PER_SHIFT, | ||
| 306 | .wkdep_srcs = per_usbhost_wkdeps, | ||
| 307 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
| 308 | .pwrsts = PWRSTS_OFF_RET_ON, | 170 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 309 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 171 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 310 | .banks = 1, | 172 | .banks = 1, |
| @@ -326,7 +188,6 @@ static struct powerdomain neon_pwrdm = { | |||
| 326 | .name = "neon_pwrdm", | 188 | .name = "neon_pwrdm", |
| 327 | .prcm_offs = OMAP3430_NEON_MOD, | 189 | .prcm_offs = OMAP3430_NEON_MOD, |
| 328 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 190 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 329 | .wkdep_srcs = neon_wkdeps, | ||
| 330 | .pwrsts = PWRSTS_OFF_RET_ON, | 191 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 331 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 192 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 332 | }; | 193 | }; |
| @@ -335,8 +196,6 @@ static struct powerdomain usbhost_pwrdm = { | |||
| 335 | .name = "usbhost_pwrdm", | 196 | .name = "usbhost_pwrdm", |
| 336 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 197 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
| 337 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 198 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 338 | .wkdep_srcs = per_usbhost_wkdeps, | ||
| 339 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
| 340 | .pwrsts = PWRSTS_OFF_RET_ON, | 199 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 341 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 200 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 342 | /* | 201 | /* |
| @@ -386,7 +245,7 @@ static struct powerdomain dpll5_pwrdm = { | |||
| 386 | }; | 245 | }; |
| 387 | 246 | ||
| 388 | 247 | ||
| 389 | #endif /* CONFIG_ARCH_OMAP34XX */ | 248 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 390 | 249 | ||
| 391 | 250 | ||
| 392 | #endif | 251 | #endif |
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h new file mode 100644 index 000000000000..c1015147d579 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains44xx.h | |||
| @@ -0,0 +1,310 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Power domains framework | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2009 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Abhijit Pagare (abhijitpagare@ti.com) | ||
| 8 | * Benoit Cousson (b-cousson@ti.com) | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This file is automatically generated from the OMAP hardware databases. | ||
| 12 | * We respectfully ask that any modifications to this file be coordinated | ||
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 14 | * authors above to ensure that the autogeneration scripts are kept | ||
| 15 | * up-to-date with the file contents. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or modify | ||
| 18 | * it under the terms of the GNU General Public License version 2 as | ||
| 19 | * published by the Free Software Foundation. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H | ||
| 23 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H | ||
| 24 | |||
| 25 | #include <plat/powerdomain.h> | ||
| 26 | |||
| 27 | #include "prcm-common.h" | ||
| 28 | #include "cm.h" | ||
| 29 | #include "cm-regbits-44xx.h" | ||
| 30 | #include "prm.h" | ||
| 31 | #include "prm-regbits-44xx.h" | ||
| 32 | |||
| 33 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 34 | |||
| 35 | /* core_44xx_pwrdm: CORE power domain */ | ||
| 36 | static struct powerdomain core_44xx_pwrdm = { | ||
| 37 | .name = "core_pwrdm", | ||
| 38 | .prcm_offs = OMAP4430_PRM_CORE_MOD, | ||
| 39 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 40 | .pwrsts = PWRSTS_RET_ON, | ||
| 41 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 42 | .banks = 5, | ||
| 43 | .pwrsts_mem_ret = { | ||
| 44 | [0] = PWRDM_POWER_OFF, /* core_nret_bank */ | ||
| 45 | [1] = PWRSTS_OFF_RET, /* core_ocmram */ | ||
| 46 | [2] = PWRDM_POWER_RET, /* core_other_bank */ | ||
| 47 | [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ | ||
| 48 | [4] = PWRSTS_OFF_RET, /* ducati_unicache */ | ||
| 49 | }, | ||
| 50 | .pwrsts_mem_on = { | ||
| 51 | [0] = PWRDM_POWER_ON, /* core_nret_bank */ | ||
| 52 | [1] = PWRSTS_OFF_RET, /* core_ocmram */ | ||
| 53 | [2] = PWRDM_POWER_ON, /* core_other_bank */ | ||
| 54 | [3] = PWRDM_POWER_ON, /* ducati_l2ram */ | ||
| 55 | [4] = PWRDM_POWER_ON, /* ducati_unicache */ | ||
| 56 | }, | ||
| 57 | }; | ||
| 58 | |||
| 59 | /* gfx_44xx_pwrdm: 3D accelerator power domain */ | ||
| 60 | static struct powerdomain gfx_44xx_pwrdm = { | ||
| 61 | .name = "gfx_pwrdm", | ||
| 62 | .prcm_offs = OMAP4430_PRM_GFX_MOD, | ||
| 63 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 64 | .pwrsts = PWRSTS_OFF_ON, | ||
| 65 | .banks = 1, | ||
| 66 | .pwrsts_mem_ret = { | ||
| 67 | [0] = PWRDM_POWER_OFF, /* gfx_mem */ | ||
| 68 | }, | ||
| 69 | .pwrsts_mem_on = { | ||
| 70 | [0] = PWRDM_POWER_ON, /* gfx_mem */ | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | /* abe_44xx_pwrdm: Audio back end power domain */ | ||
| 75 | static struct powerdomain abe_44xx_pwrdm = { | ||
| 76 | .name = "abe_pwrdm", | ||
| 77 | .prcm_offs = OMAP4430_PRM_ABE_MOD, | ||
| 78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 79 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 80 | .pwrsts_logic_ret = PWRDM_POWER_OFF, | ||
| 81 | .banks = 2, | ||
| 82 | .pwrsts_mem_ret = { | ||
| 83 | [0] = PWRDM_POWER_RET, /* aessmem */ | ||
| 84 | [1] = PWRDM_POWER_OFF, /* periphmem */ | ||
| 85 | }, | ||
| 86 | .pwrsts_mem_on = { | ||
| 87 | [0] = PWRDM_POWER_ON, /* aessmem */ | ||
| 88 | [1] = PWRDM_POWER_ON, /* periphmem */ | ||
| 89 | }, | ||
| 90 | }; | ||
| 91 | |||
| 92 | /* dss_44xx_pwrdm: Display subsystem power domain */ | ||
| 93 | static struct powerdomain dss_44xx_pwrdm = { | ||
| 94 | .name = "dss_pwrdm", | ||
| 95 | .prcm_offs = OMAP4430_PRM_DSS_MOD, | ||
| 96 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 97 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 98 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 99 | .banks = 1, | ||
| 100 | .pwrsts_mem_ret = { | ||
| 101 | [0] = PWRDM_POWER_OFF, /* dss_mem */ | ||
| 102 | }, | ||
| 103 | .pwrsts_mem_on = { | ||
| 104 | [0] = PWRDM_POWER_ON, /* dss_mem */ | ||
| 105 | }, | ||
| 106 | }; | ||
| 107 | |||
| 108 | /* tesla_44xx_pwrdm: Tesla processor power domain */ | ||
| 109 | static struct powerdomain tesla_44xx_pwrdm = { | ||
| 110 | .name = "tesla_pwrdm", | ||
| 111 | .prcm_offs = OMAP4430_PRM_TESLA_MOD, | ||
| 112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 113 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 114 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 115 | .banks = 3, | ||
| 116 | .pwrsts_mem_ret = { | ||
| 117 | [0] = PWRDM_POWER_RET, /* tesla_edma */ | ||
| 118 | [1] = PWRSTS_OFF_RET, /* tesla_l1 */ | ||
| 119 | [2] = PWRSTS_OFF_RET, /* tesla_l2 */ | ||
| 120 | }, | ||
| 121 | .pwrsts_mem_on = { | ||
| 122 | [0] = PWRDM_POWER_ON, /* tesla_edma */ | ||
| 123 | [1] = PWRDM_POWER_ON, /* tesla_l1 */ | ||
| 124 | [2] = PWRDM_POWER_ON, /* tesla_l2 */ | ||
| 125 | }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | /* wkup_44xx_pwrdm: Wake-up power domain */ | ||
| 129 | static struct powerdomain wkup_44xx_pwrdm = { | ||
| 130 | .name = "wkup_pwrdm", | ||
| 131 | .prcm_offs = OMAP4430_PRM_WKUP_MOD, | ||
| 132 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 133 | .pwrsts = PWRDM_POWER_ON, | ||
| 134 | .banks = 1, | ||
| 135 | .pwrsts_mem_ret = { | ||
| 136 | [0] = PWRDM_POWER_OFF, /* wkup_bank */ | ||
| 137 | }, | ||
| 138 | .pwrsts_mem_on = { | ||
| 139 | [0] = PWRDM_POWER_ON, /* wkup_bank */ | ||
| 140 | }, | ||
| 141 | }; | ||
| 142 | |||
| 143 | /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ | ||
| 144 | static struct powerdomain cpu0_44xx_pwrdm = { | ||
| 145 | .name = "cpu0_pwrdm", | ||
| 146 | .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, | ||
| 147 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 148 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 149 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 150 | .banks = 1, | ||
| 151 | .pwrsts_mem_ret = { | ||
| 152 | [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ | ||
| 153 | }, | ||
| 154 | .pwrsts_mem_on = { | ||
| 155 | [0] = PWRDM_POWER_ON, /* cpu0_l1 */ | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ | ||
| 160 | static struct powerdomain cpu1_44xx_pwrdm = { | ||
| 161 | .name = "cpu1_pwrdm", | ||
| 162 | .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, | ||
| 163 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 164 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 165 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 166 | .banks = 1, | ||
| 167 | .pwrsts_mem_ret = { | ||
| 168 | [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ | ||
| 169 | }, | ||
| 170 | .pwrsts_mem_on = { | ||
| 171 | [0] = PWRDM_POWER_ON, /* cpu1_l1 */ | ||
| 172 | }, | ||
| 173 | }; | ||
| 174 | |||
| 175 | /* emu_44xx_pwrdm: Emulation power domain */ | ||
| 176 | static struct powerdomain emu_44xx_pwrdm = { | ||
| 177 | .name = "emu_pwrdm", | ||
| 178 | .prcm_offs = OMAP4430_PRM_EMU_MOD, | ||
| 179 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 180 | .pwrsts = PWRSTS_OFF_ON, | ||
| 181 | .banks = 1, | ||
| 182 | .pwrsts_mem_ret = { | ||
| 183 | [0] = PWRDM_POWER_OFF, /* emu_bank */ | ||
| 184 | }, | ||
| 185 | .pwrsts_mem_on = { | ||
| 186 | [0] = PWRDM_POWER_ON, /* emu_bank */ | ||
| 187 | }, | ||
| 188 | }; | ||
| 189 | |||
| 190 | /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ | ||
| 191 | static struct powerdomain mpu_44xx_pwrdm = { | ||
| 192 | .name = "mpu_pwrdm", | ||
| 193 | .prcm_offs = OMAP4430_PRM_MPU_MOD, | ||
| 194 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 195 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 196 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 197 | .banks = 3, | ||
| 198 | .pwrsts_mem_ret = { | ||
| 199 | [0] = PWRSTS_OFF_RET, /* mpu_l1 */ | ||
| 200 | [1] = PWRSTS_OFF_RET, /* mpu_l2 */ | ||
| 201 | [2] = PWRDM_POWER_RET, /* mpu_ram */ | ||
| 202 | }, | ||
| 203 | .pwrsts_mem_on = { | ||
| 204 | [0] = PWRDM_POWER_ON, /* mpu_l1 */ | ||
| 205 | [1] = PWRDM_POWER_ON, /* mpu_l2 */ | ||
| 206 | [2] = PWRDM_POWER_ON, /* mpu_ram */ | ||
| 207 | }, | ||
| 208 | }; | ||
| 209 | |||
| 210 | /* ivahd_44xx_pwrdm: IVA-HD power domain */ | ||
| 211 | static struct powerdomain ivahd_44xx_pwrdm = { | ||
| 212 | .name = "ivahd_pwrdm", | ||
| 213 | .prcm_offs = OMAP4430_PRM_IVAHD_MOD, | ||
| 214 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 215 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 216 | .pwrsts_logic_ret = PWRDM_POWER_OFF, | ||
| 217 | .banks = 4, | ||
| 218 | .pwrsts_mem_ret = { | ||
| 219 | [0] = PWRDM_POWER_OFF, /* hwa_mem */ | ||
| 220 | [1] = PWRSTS_OFF_RET, /* sl2_mem */ | ||
| 221 | [2] = PWRSTS_OFF_RET, /* tcm1_mem */ | ||
| 222 | [3] = PWRSTS_OFF_RET, /* tcm2_mem */ | ||
| 223 | }, | ||
| 224 | .pwrsts_mem_on = { | ||
| 225 | [0] = PWRDM_POWER_ON, /* hwa_mem */ | ||
| 226 | [1] = PWRDM_POWER_ON, /* sl2_mem */ | ||
| 227 | [2] = PWRDM_POWER_ON, /* tcm1_mem */ | ||
| 228 | [3] = PWRDM_POWER_ON, /* tcm2_mem */ | ||
| 229 | }, | ||
| 230 | }; | ||
| 231 | |||
| 232 | /* cam_44xx_pwrdm: Camera subsystem power domain */ | ||
| 233 | static struct powerdomain cam_44xx_pwrdm = { | ||
| 234 | .name = "cam_pwrdm", | ||
| 235 | .prcm_offs = OMAP4430_PRM_CAM_MOD, | ||
| 236 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 237 | .pwrsts = PWRSTS_OFF_ON, | ||
| 238 | .banks = 1, | ||
| 239 | .pwrsts_mem_ret = { | ||
| 240 | [0] = PWRDM_POWER_OFF, /* cam_mem */ | ||
| 241 | }, | ||
| 242 | .pwrsts_mem_on = { | ||
| 243 | [0] = PWRDM_POWER_ON, /* cam_mem */ | ||
| 244 | }, | ||
| 245 | }; | ||
| 246 | |||
| 247 | /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ | ||
| 248 | static struct powerdomain l3init_44xx_pwrdm = { | ||
| 249 | .name = "l3init_pwrdm", | ||
| 250 | .prcm_offs = OMAP4430_PRM_L3INIT_MOD, | ||
| 251 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 252 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 253 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 254 | .banks = 1, | ||
| 255 | .pwrsts_mem_ret = { | ||
| 256 | [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ | ||
| 257 | }, | ||
| 258 | .pwrsts_mem_on = { | ||
| 259 | [0] = PWRDM_POWER_ON, /* l3init_bank1 */ | ||
| 260 | }, | ||
| 261 | }; | ||
| 262 | |||
| 263 | /* l4per_44xx_pwrdm: Target peripherals power domain */ | ||
| 264 | static struct powerdomain l4per_44xx_pwrdm = { | ||
| 265 | .name = "l4per_pwrdm", | ||
| 266 | .prcm_offs = OMAP4430_PRM_L4PER_MOD, | ||
| 267 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 268 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 269 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 270 | .banks = 2, | ||
| 271 | .pwrsts_mem_ret = { | ||
| 272 | [0] = PWRDM_POWER_OFF, /* nonretained_bank */ | ||
| 273 | [1] = PWRDM_POWER_RET, /* retained_bank */ | ||
| 274 | }, | ||
| 275 | .pwrsts_mem_on = { | ||
| 276 | [0] = PWRDM_POWER_ON, /* nonretained_bank */ | ||
| 277 | [1] = PWRDM_POWER_ON, /* retained_bank */ | ||
| 278 | }, | ||
| 279 | }; | ||
| 280 | |||
| 281 | /* | ||
| 282 | * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage | ||
| 283 | * domain | ||
| 284 | */ | ||
| 285 | static struct powerdomain always_on_core_44xx_pwrdm = { | ||
| 286 | .name = "always_on_core_pwrdm", | ||
| 287 | .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, | ||
| 288 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 289 | .pwrsts = PWRDM_POWER_ON, | ||
| 290 | }; | ||
| 291 | |||
| 292 | /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ | ||
| 293 | static struct powerdomain cefuse_44xx_pwrdm = { | ||
| 294 | .name = "cefuse_pwrdm", | ||
| 295 | .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, | ||
| 296 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 297 | .pwrsts = PWRSTS_OFF_ON, | ||
| 298 | }; | ||
| 299 | |||
| 300 | /* | ||
| 301 | * The following power domains are not under SW control | ||
| 302 | * | ||
| 303 | * always_on_iva | ||
| 304 | * always_on_mpu | ||
| 305 | * stdefuse | ||
| 306 | */ | ||
| 307 | |||
| 308 | #endif | ||
| 309 | |||
| 310 | #endif | ||
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 61ac2a418bd0..90f603d434c6 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -119,6 +119,15 @@ | |||
| 119 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 | 119 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 |
| 120 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 | 120 | #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 |
| 121 | 121 | ||
| 122 | /* Base Addresses for the OMAP4 */ | ||
| 123 | |||
| 124 | #define OMAP4430_CM1_BASE 0x4a004000 | ||
| 125 | #define OMAP4430_CM2_BASE 0x4a008000 | ||
| 126 | #define OMAP4430_PRM_BASE 0x4a306000 | ||
| 127 | #define OMAP4430_SCRM_BASE 0x4a30a000 | ||
| 128 | #define OMAP4430_CHIRONSS_BASE 0x48243000 | ||
| 129 | |||
| 130 | |||
| 122 | /* 24XX register bits shared between CM & PRM registers */ | 131 | /* 24XX register bits shared between CM & PRM registers */ |
| 123 | 132 | ||
| 124 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | 133 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ |
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index cf466ea1dffc..81872aacb801 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | * Rajendra Nayak <rnayak@ti.com> | 11 | * Rajendra Nayak <rnayak@ti.com> |
| 12 | * | 12 | * |
| 13 | * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. | 13 | * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. |
| 14 | * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com> | ||
| 14 | * | 15 | * |
| 15 | * This program is free software; you can redistribute it and/or modify | 16 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License version 2 as | 17 | * it under the terms of the GNU General Public License version 2 as |
| @@ -28,6 +29,7 @@ | |||
| 28 | #include <plat/control.h> | 29 | #include <plat/control.h> |
| 29 | 30 | ||
| 30 | #include "clock.h" | 31 | #include "clock.h" |
| 32 | #include "clock2xxx.h" | ||
| 31 | #include "cm.h" | 33 | #include "cm.h" |
| 32 | #include "prm.h" | 34 | #include "prm.h" |
| 33 | #include "prm-regbits-24xx.h" | 35 | #include "prm-regbits-24xx.h" |
| @@ -121,19 +123,25 @@ struct omap3_prcm_regs prcm_context; | |||
| 121 | u32 omap_prcm_get_reset_sources(void) | 123 | u32 omap_prcm_get_reset_sources(void) |
| 122 | { | 124 | { |
| 123 | /* XXX This presumably needs modification for 34XX */ | 125 | /* XXX This presumably needs modification for 34XX */ |
| 124 | return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; | 126 | if (cpu_is_omap24xx() | cpu_is_omap34xx()) |
| 127 | return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; | ||
| 128 | if (cpu_is_omap44xx()) | ||
| 129 | return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; | ||
| 130 | |||
| 131 | return 0; | ||
| 125 | } | 132 | } |
| 126 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); | 133 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); |
| 127 | 134 | ||
| 128 | /* Resets clock rates and reboots the system. Only called from system.h */ | 135 | /* Resets clock rates and reboots the system. Only called from system.h */ |
| 129 | void omap_prcm_arch_reset(char mode) | 136 | void omap_prcm_arch_reset(char mode) |
| 130 | { | 137 | { |
| 131 | s16 prcm_offs; | 138 | s16 prcm_offs = 0; |
| 132 | omap2_clk_prepare_for_reboot(); | 139 | |
| 140 | if (cpu_is_omap24xx()) { | ||
| 141 | omap2xxx_clk_prepare_for_reboot(); | ||
| 133 | 142 | ||
| 134 | if (cpu_is_omap24xx()) | ||
| 135 | prcm_offs = WKUP_MOD; | 143 | prcm_offs = WKUP_MOD; |
| 136 | else if (cpu_is_omap34xx()) { | 144 | } else if (cpu_is_omap34xx()) { |
| 137 | u32 l; | 145 | u32 l; |
| 138 | 146 | ||
| 139 | prcm_offs = OMAP3430_GR_MOD; | 147 | prcm_offs = OMAP3430_GR_MOD; |
| @@ -144,10 +152,17 @@ void omap_prcm_arch_reset(char mode) | |||
| 144 | * cf. OMAP34xx TRM, Initialization / Software Booting | 152 | * cf. OMAP34xx TRM, Initialization / Software Booting |
| 145 | * Configuration. */ | 153 | * Configuration. */ |
| 146 | omap_writel(l, OMAP343X_SCRATCHPAD + 4); | 154 | omap_writel(l, OMAP343X_SCRATCHPAD + 4); |
| 147 | } else | 155 | } else if (cpu_is_omap44xx()) |
| 156 | prcm_offs = OMAP4430_PRM_DEVICE_MOD; | ||
| 157 | else | ||
| 148 | WARN_ON(1); | 158 | WARN_ON(1); |
| 149 | 159 | ||
| 150 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); | 160 | if (cpu_is_omap24xx() | cpu_is_omap34xx()) |
| 161 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, | ||
| 162 | OMAP2_RM_RSTCTRL); | ||
| 163 | if (cpu_is_omap44xx()) | ||
| 164 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, | ||
| 165 | OMAP4_RM_RSTCTRL); | ||
| 151 | } | 166 | } |
| 152 | 167 | ||
| 153 | static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) | 168 | static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) |
| @@ -188,6 +203,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
| 188 | return v; | 203 | return v; |
| 189 | } | 204 | } |
| 190 | 205 | ||
| 206 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | ||
| 207 | u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | ||
| 208 | { | ||
| 209 | u32 v; | ||
| 210 | |||
| 211 | v = prm_read_mod_reg(domain, idx); | ||
| 212 | v &= mask; | ||
| 213 | v >>= __ffs(mask); | ||
| 214 | |||
| 215 | return v; | ||
| 216 | } | ||
| 217 | |||
| 191 | /* Read a register in a CM module */ | 218 | /* Read a register in a CM module */ |
| 192 | u32 cm_read_mod_reg(s16 module, u16 idx) | 219 | u32 cm_read_mod_reg(s16 module, u16 idx) |
| 193 | { | 220 | { |
| @@ -217,26 +244,22 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
| 217 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness | 244 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness |
| 218 | * @reg: physical address of module IDLEST register | 245 | * @reg: physical address of module IDLEST register |
| 219 | * @mask: value to mask against to determine if the module is active | 246 | * @mask: value to mask against to determine if the module is active |
| 247 | * @idlest: idle state indicator (0 or 1) for the clock | ||
| 220 | * @name: name of the clock (for printk) | 248 | * @name: name of the clock (for printk) |
| 221 | * | 249 | * |
| 222 | * Returns 1 if the module indicated readiness in time, or 0 if it | 250 | * Returns 1 if the module indicated readiness in time, or 0 if it |
| 223 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. | 251 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. |
| 224 | */ | 252 | */ |
| 225 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) | 253 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
| 254 | const char *name) | ||
| 226 | { | 255 | { |
| 227 | int i = 0; | 256 | int i = 0; |
| 228 | int ena = 0; | 257 | int ena = 0; |
| 229 | 258 | ||
| 230 | /* | 259 | if (idlest) |
| 231 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | ||
| 232 | * 34xx reverses this, just to keep us on our toes | ||
| 233 | */ | ||
| 234 | if (cpu_is_omap24xx()) | ||
| 235 | ena = mask; | ||
| 236 | else if (cpu_is_omap34xx()) | ||
| 237 | ena = 0; | 260 | ena = 0; |
| 238 | else | 261 | else |
| 239 | BUG(); | 262 | ena = mask; |
| 240 | 263 | ||
| 241 | /* Wait for lock */ | 264 | /* Wait for lock */ |
| 242 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), | 265 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), |
| @@ -254,9 +277,19 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) | |||
| 254 | 277 | ||
| 255 | void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) | 278 | void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) |
| 256 | { | 279 | { |
| 257 | prm_base = omap2_globals->prm; | 280 | /* Static mapping, never released */ |
| 258 | cm_base = omap2_globals->cm; | 281 | if (omap2_globals->prm) { |
| 259 | cm2_base = omap2_globals->cm2; | 282 | prm_base = ioremap(omap2_globals->prm, SZ_8K); |
| 283 | WARN_ON(!prm_base); | ||
| 284 | } | ||
| 285 | if (omap2_globals->cm) { | ||
| 286 | cm_base = ioremap(omap2_globals->cm, SZ_8K); | ||
| 287 | WARN_ON(!cm_base); | ||
| 288 | } | ||
| 289 | if (omap2_globals->cm2) { | ||
| 290 | cm2_base = ioremap(omap2_globals->cm2, SZ_8K); | ||
| 291 | WARN_ON(!cm2_base); | ||
| 292 | } | ||
| 260 | } | 293 | } |
| 261 | 294 | ||
| 262 | #ifdef CONFIG_ARCH_OMAP3 | 295 | #ifdef CONFIG_ARCH_OMAP3 |
| @@ -280,7 +313,7 @@ void omap3_prcm_save_context(void) | |||
| 280 | prcm_context.emu_cm_clksel = | 313 | prcm_context.emu_cm_clksel = |
| 281 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | 314 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); |
| 282 | prcm_context.emu_cm_clkstctrl = | 315 | prcm_context.emu_cm_clkstctrl = |
| 283 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL); | 316 | cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); |
| 284 | prcm_context.pll_cm_autoidle2 = | 317 | prcm_context.pll_cm_autoidle2 = |
| 285 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | 318 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); |
| 286 | prcm_context.pll_cm_clksel4 = | 319 | prcm_context.pll_cm_clksel4 = |
| @@ -333,23 +366,25 @@ void omap3_prcm_save_context(void) | |||
| 333 | prcm_context.mpu_cm_autoidle2 = | 366 | prcm_context.mpu_cm_autoidle2 = |
| 334 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | 367 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); |
| 335 | prcm_context.iva2_cm_clkstctrl = | 368 | prcm_context.iva2_cm_clkstctrl = |
| 336 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); | 369 | cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); |
| 337 | prcm_context.mpu_cm_clkstctrl = | 370 | prcm_context.mpu_cm_clkstctrl = |
| 338 | cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL); | 371 | cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); |
| 339 | prcm_context.core_cm_clkstctrl = | 372 | prcm_context.core_cm_clkstctrl = |
| 340 | cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL); | 373 | cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); |
| 341 | prcm_context.sgx_cm_clkstctrl = | 374 | prcm_context.sgx_cm_clkstctrl = |
| 342 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL); | 375 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, |
| 376 | OMAP2_CM_CLKSTCTRL); | ||
| 343 | prcm_context.dss_cm_clkstctrl = | 377 | prcm_context.dss_cm_clkstctrl = |
| 344 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL); | 378 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); |
| 345 | prcm_context.cam_cm_clkstctrl = | 379 | prcm_context.cam_cm_clkstctrl = |
| 346 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL); | 380 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); |
| 347 | prcm_context.per_cm_clkstctrl = | 381 | prcm_context.per_cm_clkstctrl = |
| 348 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL); | 382 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); |
| 349 | prcm_context.neon_cm_clkstctrl = | 383 | prcm_context.neon_cm_clkstctrl = |
| 350 | cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL); | 384 | cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); |
| 351 | prcm_context.usbhost_cm_clkstctrl = | 385 | prcm_context.usbhost_cm_clkstctrl = |
| 352 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); | 386 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
| 387 | OMAP2_CM_CLKSTCTRL); | ||
| 353 | prcm_context.core_cm_autoidle1 = | 388 | prcm_context.core_cm_autoidle1 = |
| 354 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | 389 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); |
| 355 | prcm_context.core_cm_autoidle2 = | 390 | prcm_context.core_cm_autoidle2 = |
| @@ -432,7 +467,7 @@ void omap3_prcm_restore_context(void) | |||
| 432 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | 467 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, |
| 433 | CM_CLKSEL1); | 468 | CM_CLKSEL1); |
| 434 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | 469 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, |
| 435 | CM_CLKSTCTRL); | 470 | OMAP2_CM_CLKSTCTRL); |
| 436 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, | 471 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, |
| 437 | CM_AUTOIDLE2); | 472 | CM_AUTOIDLE2); |
| 438 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, | 473 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, |
| @@ -478,22 +513,23 @@ void omap3_prcm_restore_context(void) | |||
| 478 | CM_AUTOIDLE2); | 513 | CM_AUTOIDLE2); |
| 479 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); | 514 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); |
| 480 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | 515 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, |
| 481 | CM_CLKSTCTRL); | 516 | OMAP2_CM_CLKSTCTRL); |
| 482 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); | 517 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, |
| 518 | OMAP2_CM_CLKSTCTRL); | ||
| 483 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, | 519 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, |
| 484 | CM_CLKSTCTRL); | 520 | OMAP2_CM_CLKSTCTRL); |
| 485 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | 521 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, |
| 486 | CM_CLKSTCTRL); | 522 | OMAP2_CM_CLKSTCTRL); |
| 487 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | 523 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, |
| 488 | CM_CLKSTCTRL); | 524 | OMAP2_CM_CLKSTCTRL); |
| 489 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | 525 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, |
| 490 | CM_CLKSTCTRL); | 526 | OMAP2_CM_CLKSTCTRL); |
| 491 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | 527 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, |
| 492 | CM_CLKSTCTRL); | 528 | OMAP2_CM_CLKSTCTRL); |
| 493 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | 529 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, |
| 494 | CM_CLKSTCTRL); | 530 | OMAP2_CM_CLKSTCTRL); |
| 495 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, | 531 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, |
| 496 | OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); | 532 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); |
| 497 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, | 533 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, |
| 498 | CM_AUTOIDLE1); | 534 | CM_AUTOIDLE1); |
| 499 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, | 535 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, |
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 301c810fb269..597be4a2b9ff 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
| @@ -29,412 +29,412 @@ | |||
| 29 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 29 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 30 | * PRM_LDO_SRAM_MPU_SETUP | 30 | * PRM_LDO_SRAM_MPU_SETUP |
| 31 | */ | 31 | */ |
| 32 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT (1 << 1) | 32 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 |
| 33 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) | 33 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) |
| 34 | 34 | ||
| 35 | /* | 35 | /* |
| 36 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 36 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 37 | * PRM_LDO_SRAM_MPU_SETUP | 37 | * PRM_LDO_SRAM_MPU_SETUP |
| 38 | */ | 38 | */ |
| 39 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT (1 << 2) | 39 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 |
| 40 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) | 40 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) |
| 41 | 41 | ||
| 42 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 42 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 43 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT (1 << 31) | 43 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 |
| 44 | #define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) | 44 | #define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) |
| 45 | 45 | ||
| 46 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 46 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 47 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT (1 << 31) | 47 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 |
| 48 | #define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) | 48 | #define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) |
| 49 | 49 | ||
| 50 | /* Used by PRM_IRQENABLE_MPU_2 */ | 50 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 51 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT (1 << 7) | 51 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 |
| 52 | #define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) | 52 | #define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) |
| 53 | 53 | ||
| 54 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 54 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 55 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT (1 << 7) | 55 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 |
| 56 | #define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) | 56 | #define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) |
| 57 | 57 | ||
| 58 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 58 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 59 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT (1 << 2) | 59 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 |
| 60 | #define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) | 60 | #define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) |
| 61 | 61 | ||
| 62 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 62 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 63 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT (1 << 1) | 63 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 |
| 64 | #define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) | 64 | #define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) |
| 65 | 65 | ||
| 66 | /* Used by PM_ABE_PWRSTCTRL */ | 66 | /* Used by PM_ABE_PWRSTCTRL */ |
| 67 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT (1 << 16) | 67 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 |
| 68 | #define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) | 68 | #define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) |
| 69 | 69 | ||
| 70 | /* Used by PM_ABE_PWRSTCTRL */ | 70 | /* Used by PM_ABE_PWRSTCTRL */ |
| 71 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT (1 << 8) | 71 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 |
| 72 | #define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) | 72 | #define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) |
| 73 | 73 | ||
| 74 | /* Used by PM_ABE_PWRSTST */ | 74 | /* Used by PM_ABE_PWRSTST */ |
| 75 | #define OMAP4430_AESSMEM_STATEST_SHIFT (1 << 4) | 75 | #define OMAP4430_AESSMEM_STATEST_SHIFT 4 |
| 76 | #define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) | 76 | #define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) |
| 77 | 77 | ||
| 78 | /* | 78 | /* |
| 79 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 79 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 80 | * PRM_LDO_SRAM_MPU_SETUP | 80 | * PRM_LDO_SRAM_MPU_SETUP |
| 81 | */ | 81 | */ |
| 82 | #define OMAP4430_AIPOFF_SHIFT (1 << 8) | 82 | #define OMAP4430_AIPOFF_SHIFT 8 |
| 83 | #define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) | 83 | #define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) |
| 84 | 84 | ||
| 85 | /* Used by PRM_VOLTCTRL */ | 85 | /* Used by PRM_VOLTCTRL */ |
| 86 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT (1 << 0) | 86 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 |
| 87 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) | 87 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) |
| 88 | 88 | ||
| 89 | /* Used by PRM_VOLTCTRL */ | 89 | /* Used by PRM_VOLTCTRL */ |
| 90 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT (1 << 4) | 90 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 |
| 91 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) | 91 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) |
| 92 | 92 | ||
| 93 | /* Used by PRM_VOLTCTRL */ | 93 | /* Used by PRM_VOLTCTRL */ |
| 94 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT (1 << 2) | 94 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 |
| 95 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) | 95 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) |
| 96 | 96 | ||
| 97 | /* Used by PM_CAM_PWRSTCTRL */ | 97 | /* Used by PM_CAM_PWRSTCTRL */ |
| 98 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT (1 << 16) | 98 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 |
| 99 | #define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) | 99 | #define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) |
| 100 | 100 | ||
| 101 | /* Used by PM_CAM_PWRSTST */ | 101 | /* Used by PM_CAM_PWRSTST */ |
| 102 | #define OMAP4430_CAM_MEM_STATEST_SHIFT (1 << 4) | 102 | #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 |
| 103 | #define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) | 103 | #define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) |
| 104 | 104 | ||
| 105 | /* Used by PRM_CLKREQCTRL */ | 105 | /* Used by PRM_CLKREQCTRL */ |
| 106 | #define OMAP4430_CLKREQ_COND_SHIFT (1 << 0) | 106 | #define OMAP4430_CLKREQ_COND_SHIFT 0 |
| 107 | #define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) | 107 | #define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) |
| 108 | 108 | ||
| 109 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | 109 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ |
| 110 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT (1 << 0) | 110 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 |
| 111 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) | 111 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) |
| 112 | 112 | ||
| 113 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | 113 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ |
| 114 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT (1 << 8) | 114 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 |
| 115 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) | 115 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) |
| 116 | 116 | ||
| 117 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | 117 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ |
| 118 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT (1 << 16) | 118 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 |
| 119 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) | 119 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) |
| 120 | 120 | ||
| 121 | /* Used by PRM_VC_CFG_CHANNEL */ | 121 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 122 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT (1 << 4) | 122 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 |
| 123 | #define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) | 123 | #define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) |
| 124 | 124 | ||
| 125 | /* Used by PRM_VC_CFG_CHANNEL */ | 125 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 126 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT (1 << 12) | 126 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 |
| 127 | #define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) | 127 | #define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) |
| 128 | 128 | ||
| 129 | /* Used by PRM_VC_CFG_CHANNEL */ | 129 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 130 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT (1 << 17) | 130 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 |
| 131 | #define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) | 131 | #define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) |
| 132 | 132 | ||
| 133 | /* Used by PM_CORE_PWRSTCTRL */ | 133 | /* Used by PM_CORE_PWRSTCTRL */ |
| 134 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT (1 << 18) | 134 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 |
| 135 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) | 135 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) |
| 136 | 136 | ||
| 137 | /* Used by PM_CORE_PWRSTCTRL */ | 137 | /* Used by PM_CORE_PWRSTCTRL */ |
| 138 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT (1 << 9) | 138 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 |
| 139 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) | 139 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) |
| 140 | 140 | ||
| 141 | /* Used by PM_CORE_PWRSTST */ | 141 | /* Used by PM_CORE_PWRSTST */ |
| 142 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT (1 << 6) | 142 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 |
| 143 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) | 143 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) |
| 144 | 144 | ||
| 145 | /* Used by PM_CORE_PWRSTCTRL */ | 145 | /* Used by PM_CORE_PWRSTCTRL */ |
| 146 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT (1 << 16) | 146 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 |
| 147 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) | 147 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) |
| 148 | 148 | ||
| 149 | /* Used by PM_CORE_PWRSTCTRL */ | 149 | /* Used by PM_CORE_PWRSTCTRL */ |
| 150 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT (1 << 8) | 150 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 |
| 151 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) | 151 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) |
| 152 | 152 | ||
| 153 | /* Used by PM_CORE_PWRSTST */ | 153 | /* Used by PM_CORE_PWRSTST */ |
| 154 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT (1 << 4) | 154 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 |
| 155 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) | 155 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) |
| 156 | 156 | ||
| 157 | /* Used by PRM_VC_VAL_BYPASS */ | 157 | /* Used by PRM_VC_VAL_BYPASS */ |
| 158 | #define OMAP4430_DATA_SHIFT (1 << 16) | 158 | #define OMAP4430_DATA_SHIFT 16 |
| 159 | #define OMAP4430_DATA_MASK BITFIELD(16, 23) | 159 | #define OMAP4430_DATA_MASK BITFIELD(16, 23) |
| 160 | 160 | ||
| 161 | /* Used by PRM_DEVICE_OFF_CTRL */ | 161 | /* Used by PRM_DEVICE_OFF_CTRL */ |
| 162 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT (1 << 0) | 162 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 |
| 163 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) | 163 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) |
| 164 | 164 | ||
| 165 | /* Used by PRM_VC_CFG_I2C_MODE */ | 165 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 166 | #define OMAP4430_DFILTEREN_SHIFT (1 << 6) | 166 | #define OMAP4430_DFILTEREN_SHIFT 6 |
| 167 | #define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) | 167 | #define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) |
| 168 | 168 | ||
| 169 | /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | 169 | /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ |
| 170 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT (1 << 4) | 170 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 |
| 171 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) | 171 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) |
| 172 | 172 | ||
| 173 | /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | 173 | /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ |
| 174 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT (1 << 4) | 174 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 |
| 175 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) | 175 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) |
| 176 | 176 | ||
| 177 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 177 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 178 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT (1 << 0) | 178 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 |
| 179 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) | 179 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) |
| 180 | 180 | ||
| 181 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 181 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 182 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT (1 << 0) | 182 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 |
| 183 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) | 183 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) |
| 184 | 184 | ||
| 185 | /* Used by PRM_IRQENABLE_MPU */ | 185 | /* Used by PRM_IRQENABLE_MPU */ |
| 186 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT (1 << 6) | 186 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 |
| 187 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) | 187 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) |
| 188 | 188 | ||
| 189 | /* Used by PRM_IRQSTATUS_MPU */ | 189 | /* Used by PRM_IRQSTATUS_MPU */ |
| 190 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT (1 << 6) | 190 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 |
| 191 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) | 191 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) |
| 192 | 192 | ||
| 193 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | 193 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ |
| 194 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT (1 << 2) | 194 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 |
| 195 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) | 195 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) |
| 196 | 196 | ||
| 197 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | 197 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ |
| 198 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT (1 << 2) | 198 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 |
| 199 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) | 199 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) |
| 200 | 200 | ||
| 201 | /* Used by PRM_IRQENABLE_MPU */ | 201 | /* Used by PRM_IRQENABLE_MPU */ |
| 202 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT (1 << 1) | 202 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 |
| 203 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) | 203 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) |
| 204 | 204 | ||
| 205 | /* Used by PRM_IRQSTATUS_MPU */ | 205 | /* Used by PRM_IRQSTATUS_MPU */ |
| 206 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT (1 << 1) | 206 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 |
| 207 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) | 207 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) |
| 208 | 208 | ||
| 209 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 209 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 210 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT (1 << 3) | 210 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 |
| 211 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) | 211 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) |
| 212 | 212 | ||
| 213 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 213 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 214 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT (1 << 3) | 214 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 |
| 215 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) | 215 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) |
| 216 | 216 | ||
| 217 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 217 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 218 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT (1 << 7) | 218 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 |
| 219 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) | 219 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) |
| 220 | 220 | ||
| 221 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 221 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 222 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT (1 << 7) | 222 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 |
| 223 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) | 223 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) |
| 224 | 224 | ||
| 225 | /* Used by PRM_IRQENABLE_MPU */ | 225 | /* Used by PRM_IRQENABLE_MPU */ |
| 226 | #define OMAP4430_DPLL_USB_RECAL_EN_SHIFT (1 << 5) | 226 | #define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 |
| 227 | #define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) | 227 | #define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) |
| 228 | 228 | ||
| 229 | /* Used by PRM_IRQSTATUS_MPU */ | 229 | /* Used by PRM_IRQSTATUS_MPU */ |
| 230 | #define OMAP4430_DPLL_USB_RECAL_ST_SHIFT (1 << 5) | 230 | #define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 |
| 231 | #define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) | 231 | #define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) |
| 232 | 232 | ||
| 233 | /* Used by PM_DSS_PWRSTCTRL */ | 233 | /* Used by PM_DSS_PWRSTCTRL */ |
| 234 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT (1 << 16) | 234 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 |
| 235 | #define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) | 235 | #define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) |
| 236 | 236 | ||
| 237 | /* Used by PM_DSS_PWRSTCTRL */ | 237 | /* Used by PM_DSS_PWRSTCTRL */ |
| 238 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT (1 << 8) | 238 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 |
| 239 | #define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) | 239 | #define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) |
| 240 | 240 | ||
| 241 | /* Used by PM_DSS_PWRSTST */ | 241 | /* Used by PM_DSS_PWRSTST */ |
| 242 | #define OMAP4430_DSS_MEM_STATEST_SHIFT (1 << 4) | 242 | #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 |
| 243 | #define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) | 243 | #define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) |
| 244 | 244 | ||
| 245 | /* Used by PM_CORE_PWRSTCTRL */ | 245 | /* Used by PM_CORE_PWRSTCTRL */ |
| 246 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT (1 << 20) | 246 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 |
| 247 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) | 247 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) |
| 248 | 248 | ||
| 249 | /* Used by PM_CORE_PWRSTCTRL */ | 249 | /* Used by PM_CORE_PWRSTCTRL */ |
| 250 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT (1 << 10) | 250 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 |
| 251 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) | 251 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) |
| 252 | 252 | ||
| 253 | /* Used by PM_CORE_PWRSTST */ | 253 | /* Used by PM_CORE_PWRSTST */ |
| 254 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT (1 << 8) | 254 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 |
| 255 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) | 255 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) |
| 256 | 256 | ||
| 257 | /* Used by PM_CORE_PWRSTCTRL */ | 257 | /* Used by PM_CORE_PWRSTCTRL */ |
| 258 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT (1 << 22) | 258 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 |
| 259 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) | 259 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) |
| 260 | 260 | ||
| 261 | /* Used by PM_CORE_PWRSTCTRL */ | 261 | /* Used by PM_CORE_PWRSTCTRL */ |
| 262 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT (1 << 11) | 262 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 |
| 263 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) | 263 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) |
| 264 | 264 | ||
| 265 | /* Used by PM_CORE_PWRSTST */ | 265 | /* Used by PM_CORE_PWRSTST */ |
| 266 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT (1 << 10) | 266 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 |
| 267 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) | 267 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) |
| 268 | 268 | ||
| 269 | /* Used by RM_MPU_RSTST */ | 269 | /* Used by RM_MPU_RSTST */ |
| 270 | #define OMAP4430_EMULATION_RST_SHIFT (1 << 0) | 270 | #define OMAP4430_EMULATION_RST_SHIFT 0 |
| 271 | #define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) | 271 | #define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) |
| 272 | 272 | ||
| 273 | /* Used by RM_DUCATI_RSTST */ | 273 | /* Used by RM_DUCATI_RSTST */ |
| 274 | #define OMAP4430_EMULATION_RST1ST_SHIFT (1 << 3) | 274 | #define OMAP4430_EMULATION_RST1ST_SHIFT 3 |
| 275 | #define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) | 275 | #define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) |
| 276 | 276 | ||
| 277 | /* Used by RM_DUCATI_RSTST */ | 277 | /* Used by RM_DUCATI_RSTST */ |
| 278 | #define OMAP4430_EMULATION_RST2ST_SHIFT (1 << 4) | 278 | #define OMAP4430_EMULATION_RST2ST_SHIFT 4 |
| 279 | #define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) | 279 | #define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) |
| 280 | 280 | ||
| 281 | /* Used by RM_IVAHD_RSTST */ | 281 | /* Used by RM_IVAHD_RSTST */ |
| 282 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT (1 << 3) | 282 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 |
| 283 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) | 283 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) |
| 284 | 284 | ||
| 285 | /* Used by RM_IVAHD_RSTST */ | 285 | /* Used by RM_IVAHD_RSTST */ |
| 286 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT (1 << 4) | 286 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 |
| 287 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) | 287 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) |
| 288 | 288 | ||
| 289 | /* Used by PM_EMU_PWRSTCTRL */ | 289 | /* Used by PM_EMU_PWRSTCTRL */ |
| 290 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT (1 << 16) | 290 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 |
| 291 | #define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) | 291 | #define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) |
| 292 | 292 | ||
| 293 | /* Used by PM_EMU_PWRSTST */ | 293 | /* Used by PM_EMU_PWRSTST */ |
| 294 | #define OMAP4430_EMU_BANK_STATEST_SHIFT (1 << 4) | 294 | #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 |
| 295 | #define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) | 295 | #define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) |
| 296 | 296 | ||
| 297 | /* | 297 | /* |
| 298 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 298 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 299 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | 299 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP |
| 300 | */ | 300 | */ |
| 301 | #define OMAP4430_ENABLE_RTA_EXPORT_SHIFT (1 << 0) | 301 | #define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 |
| 302 | #define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) | 302 | #define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) |
| 303 | 303 | ||
| 304 | /* | 304 | /* |
| 305 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 305 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 306 | * PRM_LDO_SRAM_MPU_SETUP | 306 | * PRM_LDO_SRAM_MPU_SETUP |
| 307 | */ | 307 | */ |
| 308 | #define OMAP4430_ENFUNC1_SHIFT (1 << 3) | 308 | #define OMAP4430_ENFUNC1_SHIFT 3 |
| 309 | #define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) | 309 | #define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) |
| 310 | 310 | ||
| 311 | /* | 311 | /* |
| 312 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 312 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 313 | * PRM_LDO_SRAM_MPU_SETUP | 313 | * PRM_LDO_SRAM_MPU_SETUP |
| 314 | */ | 314 | */ |
| 315 | #define OMAP4430_ENFUNC3_SHIFT (1 << 5) | 315 | #define OMAP4430_ENFUNC3_SHIFT 5 |
| 316 | #define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) | 316 | #define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) |
| 317 | 317 | ||
| 318 | /* | 318 | /* |
| 319 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 319 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 320 | * PRM_LDO_SRAM_MPU_SETUP | 320 | * PRM_LDO_SRAM_MPU_SETUP |
| 321 | */ | 321 | */ |
| 322 | #define OMAP4430_ENFUNC4_SHIFT (1 << 6) | 322 | #define OMAP4430_ENFUNC4_SHIFT 6 |
| 323 | #define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) | 323 | #define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) |
| 324 | 324 | ||
| 325 | /* | 325 | /* |
| 326 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 326 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 327 | * PRM_LDO_SRAM_MPU_SETUP | 327 | * PRM_LDO_SRAM_MPU_SETUP |
| 328 | */ | 328 | */ |
| 329 | #define OMAP4430_ENFUNC5_SHIFT (1 << 7) | 329 | #define OMAP4430_ENFUNC5_SHIFT 7 |
| 330 | #define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) | 330 | #define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) |
| 331 | 331 | ||
| 332 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 332 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 333 | #define OMAP4430_ERRORGAIN_SHIFT (1 << 16) | 333 | #define OMAP4430_ERRORGAIN_SHIFT 16 |
| 334 | #define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) | 334 | #define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) |
| 335 | 335 | ||
| 336 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 336 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 337 | #define OMAP4430_ERROROFFSET_SHIFT (1 << 24) | 337 | #define OMAP4430_ERROROFFSET_SHIFT 24 |
| 338 | #define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) | 338 | #define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) |
| 339 | 339 | ||
| 340 | /* Used by PRM_RSTST */ | 340 | /* Used by PRM_RSTST */ |
| 341 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT (1 << 5) | 341 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
| 342 | #define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) | 342 | #define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) |
| 343 | 343 | ||
| 344 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 344 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 345 | #define OMAP4430_FORCEUPDATE_SHIFT (1 << 1) | 345 | #define OMAP4430_FORCEUPDATE_SHIFT 1 |
| 346 | #define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) | 346 | #define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) |
| 347 | 347 | ||
| 348 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | 348 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ |
| 349 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT (1 << 8) | 349 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 |
| 350 | #define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) | 350 | #define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) |
| 351 | 351 | ||
| 352 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ | 352 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ |
| 353 | #define OMAP4430_FORCEWKUP_EN_SHIFT (1 << 10) | 353 | #define OMAP4430_FORCEWKUP_EN_SHIFT 10 |
| 354 | #define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) | 354 | #define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) |
| 355 | 355 | ||
| 356 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ | 356 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ |
| 357 | #define OMAP4430_FORCEWKUP_ST_SHIFT (1 << 10) | 357 | #define OMAP4430_FORCEWKUP_ST_SHIFT 10 |
| 358 | #define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) | 358 | #define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) |
| 359 | 359 | ||
| 360 | /* Used by PM_GFX_PWRSTCTRL */ | 360 | /* Used by PM_GFX_PWRSTCTRL */ |
| 361 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT (1 << 16) | 361 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 |
| 362 | #define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) | 362 | #define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) |
| 363 | 363 | ||
| 364 | /* Used by PM_GFX_PWRSTST */ | 364 | /* Used by PM_GFX_PWRSTST */ |
| 365 | #define OMAP4430_GFX_MEM_STATEST_SHIFT (1 << 4) | 365 | #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 |
| 366 | #define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) | 366 | #define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) |
| 367 | 367 | ||
| 368 | /* Used by PRM_RSTST */ | 368 | /* Used by PRM_RSTST */ |
| 369 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT (1 << 0) | 369 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
| 370 | #define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) | 370 | #define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) |
| 371 | 371 | ||
| 372 | /* Used by PRM_RSTST */ | 372 | /* Used by PRM_RSTST */ |
| 373 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT (1 << 1) | 373 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 374 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) | 374 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) |
| 375 | 375 | ||
| 376 | /* Used by PRM_IO_PMCTRL */ | 376 | /* Used by PRM_IO_PMCTRL */ |
| 377 | #define OMAP4430_GLOBAL_WUEN_SHIFT (1 << 16) | 377 | #define OMAP4430_GLOBAL_WUEN_SHIFT 16 |
| 378 | #define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) | 378 | #define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) |
| 379 | 379 | ||
| 380 | /* Used by PRM_VC_CFG_I2C_MODE */ | 380 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 381 | #define OMAP4430_HSMCODE_SHIFT (1 << 0) | 381 | #define OMAP4430_HSMCODE_SHIFT 0 |
| 382 | #define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) | 382 | #define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) |
| 383 | 383 | ||
| 384 | /* Used by PRM_VC_CFG_I2C_MODE */ | 384 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 385 | #define OMAP4430_HSMODEEN_SHIFT (1 << 3) | 385 | #define OMAP4430_HSMODEEN_SHIFT 3 |
| 386 | #define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) | 386 | #define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) |
| 387 | 387 | ||
| 388 | /* Used by PRM_VC_CFG_I2C_CLK */ | 388 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 389 | #define OMAP4430_HSSCLH_SHIFT (1 << 16) | 389 | #define OMAP4430_HSSCLH_SHIFT 16 |
| 390 | #define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) | 390 | #define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) |
| 391 | 391 | ||
| 392 | /* Used by PRM_VC_CFG_I2C_CLK */ | 392 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 393 | #define OMAP4430_HSSCLL_SHIFT (1 << 24) | 393 | #define OMAP4430_HSSCLL_SHIFT 24 |
| 394 | #define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) | 394 | #define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) |
| 395 | 395 | ||
| 396 | /* Used by PM_IVAHD_PWRSTCTRL */ | 396 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 397 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT (1 << 16) | 397 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 |
| 398 | #define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) | 398 | #define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) |
| 399 | 399 | ||
| 400 | /* Used by PM_IVAHD_PWRSTCTRL */ | 400 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 401 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT (1 << 8) | 401 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 |
| 402 | #define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) | 402 | #define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) |
| 403 | 403 | ||
| 404 | /* Used by PM_IVAHD_PWRSTST */ | 404 | /* Used by PM_IVAHD_PWRSTST */ |
| 405 | #define OMAP4430_HWA_MEM_STATEST_SHIFT (1 << 4) | 405 | #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 |
| 406 | #define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) | 406 | #define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) |
| 407 | 407 | ||
| 408 | /* Used by RM_MPU_RSTST */ | 408 | /* Used by RM_MPU_RSTST */ |
| 409 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT (1 << 1) | 409 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 |
| 410 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) | 410 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) |
| 411 | 411 | ||
| 412 | /* Used by RM_DUCATI_RSTST */ | 412 | /* Used by RM_DUCATI_RSTST */ |
| 413 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT (1 << 5) | 413 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 |
| 414 | #define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) | 414 | #define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) |
| 415 | 415 | ||
| 416 | /* Used by RM_DUCATI_RSTST */ | 416 | /* Used by RM_DUCATI_RSTST */ |
| 417 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT (1 << 6) | 417 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 |
| 418 | #define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) | 418 | #define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) |
| 419 | 419 | ||
| 420 | /* Used by RM_IVAHD_RSTST */ | 420 | /* Used by RM_IVAHD_RSTST */ |
| 421 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT (1 << 5) | 421 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 |
| 422 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) | 422 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) |
| 423 | 423 | ||
| 424 | /* Used by RM_IVAHD_RSTST */ | 424 | /* Used by RM_IVAHD_RSTST */ |
| 425 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT (1 << 6) | 425 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 |
| 426 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) | 426 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) |
| 427 | 427 | ||
| 428 | /* Used by PRM_RSTST */ | 428 | /* Used by PRM_RSTST */ |
| 429 | #define OMAP4430_ICEPICK_RST_SHIFT (1 << 9) | 429 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
| 430 | #define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) | 430 | #define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) |
| 431 | 431 | ||
| 432 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 432 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 433 | #define OMAP4430_INITVDD_SHIFT (1 << 2) | 433 | #define OMAP4430_INITVDD_SHIFT 2 |
| 434 | #define OMAP4430_INITVDD_MASK BITFIELD(2, 2) | 434 | #define OMAP4430_INITVDD_MASK BITFIELD(2, 2) |
| 435 | 435 | ||
| 436 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 436 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 437 | #define OMAP4430_INITVOLTAGE_SHIFT (1 << 8) | 437 | #define OMAP4430_INITVOLTAGE_SHIFT 8 |
| 438 | #define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) | 438 | #define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) |
| 439 | 439 | ||
| 440 | /* | 440 | /* |
| @@ -442,47 +442,47 @@ | |||
| 442 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | 442 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, |
| 443 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | 443 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST |
| 444 | */ | 444 | */ |
| 445 | #define OMAP4430_INTRANSITION_SHIFT (1 << 20) | 445 | #define OMAP4430_INTRANSITION_SHIFT 20 |
| 446 | #define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) | 446 | #define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) |
| 447 | 447 | ||
| 448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 449 | #define OMAP4430_IO_EN_SHIFT (1 << 9) | 449 | #define OMAP4430_IO_EN_SHIFT 9 |
| 450 | #define OMAP4430_IO_EN_MASK BITFIELD(9, 9) | 450 | #define OMAP4430_IO_EN_MASK BITFIELD(9, 9) |
| 451 | 451 | ||
| 452 | /* Used by PRM_IO_PMCTRL */ | 452 | /* Used by PRM_IO_PMCTRL */ |
| 453 | #define OMAP4430_IO_ON_STATUS_SHIFT (1 << 5) | 453 | #define OMAP4430_IO_ON_STATUS_SHIFT 5 |
| 454 | #define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) | 454 | #define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) |
| 455 | 455 | ||
| 456 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 456 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 457 | #define OMAP4430_IO_ST_SHIFT (1 << 9) | 457 | #define OMAP4430_IO_ST_SHIFT 9 |
| 458 | #define OMAP4430_IO_ST_MASK BITFIELD(9, 9) | 458 | #define OMAP4430_IO_ST_MASK BITFIELD(9, 9) |
| 459 | 459 | ||
| 460 | /* Used by PRM_IO_PMCTRL */ | 460 | /* Used by PRM_IO_PMCTRL */ |
| 461 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT (1 << 0) | 461 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 |
| 462 | #define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) | 462 | #define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) |
| 463 | 463 | ||
| 464 | /* Used by PRM_IO_PMCTRL */ | 464 | /* Used by PRM_IO_PMCTRL */ |
| 465 | #define OMAP4430_ISOCLK_STATUS_SHIFT (1 << 1) | 465 | #define OMAP4430_ISOCLK_STATUS_SHIFT 1 |
| 466 | #define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) | 466 | #define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) |
| 467 | 467 | ||
| 468 | /* Used by PRM_IO_PMCTRL */ | 468 | /* Used by PRM_IO_PMCTRL */ |
| 469 | #define OMAP4430_ISOOVR_EXTEND_SHIFT (1 << 4) | 469 | #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 |
| 470 | #define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) | 470 | #define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) |
| 471 | 471 | ||
| 472 | /* Used by PRM_IO_COUNT */ | 472 | /* Used by PRM_IO_COUNT */ |
| 473 | #define OMAP4430_ISO_2_ON_TIME_SHIFT (1 << 0) | 473 | #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 |
| 474 | #define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) | 474 | #define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) |
| 475 | 475 | ||
| 476 | /* Used by PM_L3INIT_PWRSTCTRL */ | 476 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 477 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT (1 << 16) | 477 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 |
| 478 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) | 478 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) |
| 479 | 479 | ||
| 480 | /* Used by PM_L3INIT_PWRSTCTRL */ | 480 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 481 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT (1 << 8) | 481 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 |
| 482 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) | 482 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) |
| 483 | 483 | ||
| 484 | /* Used by PM_L3INIT_PWRSTST */ | 484 | /* Used by PM_L3INIT_PWRSTST */ |
| 485 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT (1 << 4) | 485 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 |
| 486 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) | 486 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) |
| 487 | 487 | ||
| 488 | /* | 488 | /* |
| @@ -490,7 +490,7 @@ | |||
| 490 | * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, | 490 | * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, |
| 491 | * PM_IVAHD_PWRSTCTRL | 491 | * PM_IVAHD_PWRSTCTRL |
| 492 | */ | 492 | */ |
| 493 | #define OMAP4430_LOGICRETSTATE_SHIFT (1 << 2) | 493 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
| 494 | #define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) | 494 | #define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) |
| 495 | 495 | ||
| 496 | /* | 496 | /* |
| @@ -498,7 +498,7 @@ | |||
| 498 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | 498 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, |
| 499 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | 499 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST |
| 500 | */ | 500 | */ |
| 501 | #define OMAP4430_LOGICSTATEST_SHIFT (1 << 2) | 501 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
| 502 | #define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) | 502 | #define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) |
| 503 | 503 | ||
| 504 | /* | 504 | /* |
| @@ -537,7 +537,7 @@ | |||
| 537 | * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, | 537 | * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, |
| 538 | * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT | 538 | * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT |
| 539 | */ | 539 | */ |
| 540 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT (1 << 0) | 540 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 |
| 541 | #define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) | 541 | #define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) |
| 542 | 542 | ||
| 543 | /* | 543 | /* |
| @@ -558,58 +558,58 @@ | |||
| 558 | * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, | 558 | * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, |
| 559 | * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT | 559 | * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT |
| 560 | */ | 560 | */ |
| 561 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT (1 << 1) | 561 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 |
| 562 | #define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) | 562 | #define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) |
| 563 | 563 | ||
| 564 | /* Used by RM_ABE_AESS_CONTEXT */ | 564 | /* Used by RM_ABE_AESS_CONTEXT */ |
| 565 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT (1 << 8) | 565 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 |
| 566 | #define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) | 566 | #define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) |
| 567 | 567 | ||
| 568 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | 568 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ |
| 569 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT (1 << 8) | 569 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 |
| 570 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) | 570 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) |
| 571 | 571 | ||
| 572 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ | 572 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ |
| 573 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT (1 << 8) | 573 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 |
| 574 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) | 574 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) |
| 575 | 575 | ||
| 576 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ | 576 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ |
| 577 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT (1 << 9) | 577 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 |
| 578 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) | 578 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) |
| 579 | 579 | ||
| 580 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ | 580 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ |
| 581 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT (1 << 8) | 581 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 |
| 582 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) | 582 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) |
| 583 | 583 | ||
| 584 | /* | 584 | /* |
| 585 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, | 585 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, |
| 586 | * RM_SDMA_SDMA_CONTEXT | 586 | * RM_SDMA_SDMA_CONTEXT |
| 587 | */ | 587 | */ |
| 588 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT (1 << 8) | 588 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 |
| 589 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) | 589 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) |
| 590 | 590 | ||
| 591 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ | 591 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ |
| 592 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT (1 << 8) | 592 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 |
| 593 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) | 593 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) |
| 594 | 594 | ||
| 595 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | 595 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ |
| 596 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT (1 << 9) | 596 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 |
| 597 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) | 597 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) |
| 598 | 598 | ||
| 599 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | 599 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ |
| 600 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT (1 << 8) | 600 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 |
| 601 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) | 601 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) |
| 602 | 602 | ||
| 603 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | 603 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ |
| 604 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT (1 << 8) | 604 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 |
| 605 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) | 605 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) |
| 606 | 606 | ||
| 607 | /* Used by RM_GFX_GFX_CONTEXT */ | 607 | /* Used by RM_GFX_GFX_CONTEXT */ |
| 608 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT (1 << 8) | 608 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 |
| 609 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) | 609 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) |
| 610 | 610 | ||
| 611 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | 611 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ |
| 612 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT (1 << 10) | 612 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 |
| 613 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) | 613 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) |
| 614 | 614 | ||
| 615 | /* | 615 | /* |
| @@ -619,19 +619,19 @@ | |||
| 619 | * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | 619 | * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, |
| 620 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT | 620 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT |
| 621 | */ | 621 | */ |
| 622 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT (1 << 8) | 622 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 |
| 623 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) | 623 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) |
| 624 | 624 | ||
| 625 | /* Used by RM_MPU_MPU_CONTEXT */ | 625 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 626 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT (1 << 8) | 626 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 |
| 627 | #define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) | 627 | #define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) |
| 628 | 628 | ||
| 629 | /* Used by RM_MPU_MPU_CONTEXT */ | 629 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 630 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT (1 << 9) | 630 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 |
| 631 | #define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) | 631 | #define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) |
| 632 | 632 | ||
| 633 | /* Used by RM_MPU_MPU_CONTEXT */ | 633 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 634 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT (1 << 10) | 634 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 |
| 635 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) | 635 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) |
| 636 | 636 | ||
| 637 | /* | 637 | /* |
| @@ -639,14 +639,14 @@ | |||
| 639 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | 639 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, |
| 640 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT | 640 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT |
| 641 | */ | 641 | */ |
| 642 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT (1 << 8) | 642 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 |
| 643 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) | 643 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) |
| 644 | 644 | ||
| 645 | /* | 645 | /* |
| 646 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | 646 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, |
| 647 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT | 647 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT |
| 648 | */ | 648 | */ |
| 649 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT (1 << 8) | 649 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 |
| 650 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) | 650 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) |
| 651 | 651 | ||
| 652 | /* | 652 | /* |
| @@ -654,35 +654,35 @@ | |||
| 654 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | 654 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, |
| 655 | * RM_L4SEC_CRYPTODMA_CONTEXT | 655 | * RM_L4SEC_CRYPTODMA_CONTEXT |
| 656 | */ | 656 | */ |
| 657 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT (1 << 8) | 657 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 |
| 658 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) | 658 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) |
| 659 | 659 | ||
| 660 | /* Used by RM_IVAHD_SL2_CONTEXT */ | 660 | /* Used by RM_IVAHD_SL2_CONTEXT */ |
| 661 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT (1 << 8) | 661 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 |
| 662 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) | 662 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) |
| 663 | 663 | ||
| 664 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | 664 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ |
| 665 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT (1 << 8) | 665 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 |
| 666 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) | 666 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) |
| 667 | 667 | ||
| 668 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | 668 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ |
| 669 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT (1 << 9) | 669 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 |
| 670 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) | 670 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) |
| 671 | 671 | ||
| 672 | /* Used by RM_TESLA_TESLA_CONTEXT */ | 672 | /* Used by RM_TESLA_TESLA_CONTEXT */ |
| 673 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT (1 << 10) | 673 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 |
| 674 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) | 674 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) |
| 675 | 675 | ||
| 676 | /* Used by RM_TESLA_TESLA_CONTEXT */ | 676 | /* Used by RM_TESLA_TESLA_CONTEXT */ |
| 677 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT (1 << 8) | 677 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 |
| 678 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) | 678 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) |
| 679 | 679 | ||
| 680 | /* Used by RM_TESLA_TESLA_CONTEXT */ | 680 | /* Used by RM_TESLA_TESLA_CONTEXT */ |
| 681 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT (1 << 9) | 681 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 |
| 682 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) | 682 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) |
| 683 | 683 | ||
| 684 | /* Used by RM_WKUP_SARRAM_CONTEXT */ | 684 | /* Used by RM_WKUP_SARRAM_CONTEXT */ |
| 685 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT (1 << 8) | 685 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 |
| 686 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) | 686 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) |
| 687 | 687 | ||
| 688 | /* | 688 | /* |
| @@ -690,164 +690,164 @@ | |||
| 690 | * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | 690 | * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, |
| 691 | * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL | 691 | * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL |
| 692 | */ | 692 | */ |
| 693 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT (1 << 4) | 693 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
| 694 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) | 694 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) |
| 695 | 695 | ||
| 696 | /* Used by PM_CORE_PWRSTCTRL */ | 696 | /* Used by PM_CORE_PWRSTCTRL */ |
| 697 | #define OMAP4430_MEMORYCHANGE_SHIFT (1 << 3) | 697 | #define OMAP4430_MEMORYCHANGE_SHIFT 3 |
| 698 | #define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) | 698 | #define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) |
| 699 | 699 | ||
| 700 | /* Used by PRM_MODEM_IF_CTRL */ | 700 | /* Used by PRM_MODEM_IF_CTRL */ |
| 701 | #define OMAP4430_MODEM_READY_SHIFT (1 << 1) | 701 | #define OMAP4430_MODEM_READY_SHIFT 1 |
| 702 | #define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) | 702 | #define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) |
| 703 | 703 | ||
| 704 | /* Used by PRM_MODEM_IF_CTRL */ | 704 | /* Used by PRM_MODEM_IF_CTRL */ |
| 705 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT (1 << 9) | 705 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 |
| 706 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) | 706 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) |
| 707 | 707 | ||
| 708 | /* Used by PRM_MODEM_IF_CTRL */ | 708 | /* Used by PRM_MODEM_IF_CTRL */ |
| 709 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT (1 << 16) | 709 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 |
| 710 | #define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) | 710 | #define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) |
| 711 | 711 | ||
| 712 | /* Used by PRM_MODEM_IF_CTRL */ | 712 | /* Used by PRM_MODEM_IF_CTRL */ |
| 713 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT (1 << 8) | 713 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 |
| 714 | #define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) | 714 | #define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) |
| 715 | 715 | ||
| 716 | /* Used by PM_MPU_PWRSTCTRL */ | 716 | /* Used by PM_MPU_PWRSTCTRL */ |
| 717 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT (1 << 16) | 717 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 |
| 718 | #define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) | 718 | #define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) |
| 719 | 719 | ||
| 720 | /* Used by PM_MPU_PWRSTCTRL */ | 720 | /* Used by PM_MPU_PWRSTCTRL */ |
| 721 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT (1 << 8) | 721 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 |
| 722 | #define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) | 722 | #define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) |
| 723 | 723 | ||
| 724 | /* Used by PM_MPU_PWRSTST */ | 724 | /* Used by PM_MPU_PWRSTST */ |
| 725 | #define OMAP4430_MPU_L1_STATEST_SHIFT (1 << 4) | 725 | #define OMAP4430_MPU_L1_STATEST_SHIFT 4 |
| 726 | #define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) | 726 | #define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) |
| 727 | 727 | ||
| 728 | /* Used by PM_MPU_PWRSTCTRL */ | 728 | /* Used by PM_MPU_PWRSTCTRL */ |
| 729 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT (1 << 18) | 729 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 |
| 730 | #define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) | 730 | #define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) |
| 731 | 731 | ||
| 732 | /* Used by PM_MPU_PWRSTCTRL */ | 732 | /* Used by PM_MPU_PWRSTCTRL */ |
| 733 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT (1 << 9) | 733 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 |
| 734 | #define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) | 734 | #define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) |
| 735 | 735 | ||
| 736 | /* Used by PM_MPU_PWRSTST */ | 736 | /* Used by PM_MPU_PWRSTST */ |
| 737 | #define OMAP4430_MPU_L2_STATEST_SHIFT (1 << 6) | 737 | #define OMAP4430_MPU_L2_STATEST_SHIFT 6 |
| 738 | #define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) | 738 | #define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) |
| 739 | 739 | ||
| 740 | /* Used by PM_MPU_PWRSTCTRL */ | 740 | /* Used by PM_MPU_PWRSTCTRL */ |
| 741 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT (1 << 20) | 741 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 |
| 742 | #define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) | 742 | #define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) |
| 743 | 743 | ||
| 744 | /* Used by PM_MPU_PWRSTCTRL */ | 744 | /* Used by PM_MPU_PWRSTCTRL */ |
| 745 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT (1 << 10) | 745 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 |
| 746 | #define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) | 746 | #define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) |
| 747 | 747 | ||
| 748 | /* Used by PM_MPU_PWRSTST */ | 748 | /* Used by PM_MPU_PWRSTST */ |
| 749 | #define OMAP4430_MPU_RAM_STATEST_SHIFT (1 << 8) | 749 | #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 |
| 750 | #define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) | 750 | #define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) |
| 751 | 751 | ||
| 752 | /* Used by PRM_RSTST */ | 752 | /* Used by PRM_RSTST */ |
| 753 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT (1 << 2) | 753 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
| 754 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) | 754 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) |
| 755 | 755 | ||
| 756 | /* Used by PRM_RSTST */ | 756 | /* Used by PRM_RSTST */ |
| 757 | #define OMAP4430_MPU_WDT_RST_SHIFT (1 << 3) | 757 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
| 758 | #define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) | 758 | #define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) |
| 759 | 759 | ||
| 760 | /* Used by PM_L4PER_PWRSTCTRL */ | 760 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 761 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT (1 << 18) | 761 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 |
| 762 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) | 762 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) |
| 763 | 763 | ||
| 764 | /* Used by PM_L4PER_PWRSTCTRL */ | 764 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 765 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT (1 << 9) | 765 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 |
| 766 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) | 766 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) |
| 767 | 767 | ||
| 768 | /* Used by PM_L4PER_PWRSTST */ | 768 | /* Used by PM_L4PER_PWRSTST */ |
| 769 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT (1 << 6) | 769 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 |
| 770 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) | 770 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) |
| 771 | 771 | ||
| 772 | /* Used by PM_CORE_PWRSTCTRL */ | 772 | /* Used by PM_CORE_PWRSTCTRL */ |
| 773 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT (1 << 24) | 773 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 |
| 774 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) | 774 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) |
| 775 | 775 | ||
| 776 | /* Used by PM_CORE_PWRSTCTRL */ | 776 | /* Used by PM_CORE_PWRSTCTRL */ |
| 777 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT (1 << 12) | 777 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 |
| 778 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) | 778 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) |
| 779 | 779 | ||
| 780 | /* Used by PM_CORE_PWRSTST */ | 780 | /* Used by PM_CORE_PWRSTST */ |
| 781 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT (1 << 12) | 781 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 |
| 782 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) | 782 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) |
| 783 | 783 | ||
| 784 | /* | 784 | /* |
| 785 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 785 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 786 | * PRM_VC_VAL_CMD_VDD_MPU_L | 786 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 787 | */ | 787 | */ |
| 788 | #define OMAP4430_OFF_SHIFT (1 << 0) | 788 | #define OMAP4430_OFF_SHIFT 0 |
| 789 | #define OMAP4430_OFF_MASK BITFIELD(0, 7) | 789 | #define OMAP4430_OFF_MASK BITFIELD(0, 7) |
| 790 | 790 | ||
| 791 | /* Used by PRM_LDO_BANDGAP_CTRL */ | 791 | /* Used by PRM_LDO_BANDGAP_CTRL */ |
| 792 | #define OMAP4430_OFF_ENABLE_SHIFT (1 << 0) | 792 | #define OMAP4430_OFF_ENABLE_SHIFT 0 |
| 793 | #define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) | 793 | #define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) |
| 794 | 794 | ||
| 795 | /* | 795 | /* |
| 796 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 796 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 797 | * PRM_VC_VAL_CMD_VDD_MPU_L | 797 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 798 | */ | 798 | */ |
| 799 | #define OMAP4430_ON_SHIFT (1 << 24) | 799 | #define OMAP4430_ON_SHIFT 24 |
| 800 | #define OMAP4430_ON_MASK BITFIELD(24, 31) | 800 | #define OMAP4430_ON_MASK BITFIELD(24, 31) |
| 801 | 801 | ||
| 802 | /* | 802 | /* |
| 803 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 803 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 804 | * PRM_VC_VAL_CMD_VDD_MPU_L | 804 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 805 | */ | 805 | */ |
| 806 | #define OMAP4430_ONLP_SHIFT (1 << 16) | 806 | #define OMAP4430_ONLP_SHIFT 16 |
| 807 | #define OMAP4430_ONLP_MASK BITFIELD(16, 23) | 807 | #define OMAP4430_ONLP_MASK BITFIELD(16, 23) |
| 808 | 808 | ||
| 809 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 809 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 810 | #define OMAP4430_OPP_CHANGE_SHIFT (1 << 2) | 810 | #define OMAP4430_OPP_CHANGE_SHIFT 2 |
| 811 | #define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) | 811 | #define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) |
| 812 | 812 | ||
| 813 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 813 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 814 | #define OMAP4430_OPP_SEL_SHIFT (1 << 0) | 814 | #define OMAP4430_OPP_SEL_SHIFT 0 |
| 815 | #define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) | 815 | #define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) |
| 816 | 816 | ||
| 817 | /* Used by PRM_SRAM_COUNT */ | 817 | /* Used by PRM_SRAM_COUNT */ |
| 818 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT (1 << 0) | 818 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 |
| 819 | #define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) | 819 | #define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) |
| 820 | 820 | ||
| 821 | /* Used by PRM_PSCON_COUNT */ | 821 | /* Used by PRM_PSCON_COUNT */ |
| 822 | #define OMAP4430_PCHARGE_TIME_SHIFT (1 << 0) | 822 | #define OMAP4430_PCHARGE_TIME_SHIFT 0 |
| 823 | #define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) | 823 | #define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) |
| 824 | 824 | ||
| 825 | /* Used by PM_ABE_PWRSTCTRL */ | 825 | /* Used by PM_ABE_PWRSTCTRL */ |
| 826 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT (1 << 20) | 826 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 |
| 827 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) | 827 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) |
| 828 | 828 | ||
| 829 | /* Used by PM_ABE_PWRSTCTRL */ | 829 | /* Used by PM_ABE_PWRSTCTRL */ |
| 830 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT (1 << 10) | 830 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 |
| 831 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) | 831 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) |
| 832 | 832 | ||
| 833 | /* Used by PM_ABE_PWRSTST */ | 833 | /* Used by PM_ABE_PWRSTST */ |
| 834 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT (1 << 8) | 834 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 |
| 835 | #define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) | 835 | #define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) |
| 836 | 836 | ||
| 837 | /* Used by PRM_PHASE1_CNDP */ | 837 | /* Used by PRM_PHASE1_CNDP */ |
| 838 | #define OMAP4430_PHASE1_CNDP_SHIFT (1 << 0) | 838 | #define OMAP4430_PHASE1_CNDP_SHIFT 0 |
| 839 | #define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) | 839 | #define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) |
| 840 | 840 | ||
| 841 | /* Used by PRM_PHASE2A_CNDP */ | 841 | /* Used by PRM_PHASE2A_CNDP */ |
| 842 | #define OMAP4430_PHASE2A_CNDP_SHIFT (1 << 0) | 842 | #define OMAP4430_PHASE2A_CNDP_SHIFT 0 |
| 843 | #define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) | 843 | #define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) |
| 844 | 844 | ||
| 845 | /* Used by PRM_PHASE2B_CNDP */ | 845 | /* Used by PRM_PHASE2B_CNDP */ |
| 846 | #define OMAP4430_PHASE2B_CNDP_SHIFT (1 << 0) | 846 | #define OMAP4430_PHASE2B_CNDP_SHIFT 0 |
| 847 | #define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) | 847 | #define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) |
| 848 | 848 | ||
| 849 | /* Used by PRM_PSCON_COUNT */ | 849 | /* Used by PRM_PSCON_COUNT */ |
| 850 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT (1 << 8) | 850 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 |
| 851 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) | 851 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) |
| 852 | 852 | ||
| 853 | /* | 853 | /* |
| @@ -856,7 +856,7 @@ | |||
| 856 | * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | 856 | * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, |
| 857 | * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL | 857 | * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL |
| 858 | */ | 858 | */ |
| 859 | #define OMAP4430_POWERSTATE_SHIFT (1 << 0) | 859 | #define OMAP4430_POWERSTATE_SHIFT 0 |
| 860 | #define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) | 860 | #define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) |
| 861 | 861 | ||
| 862 | /* | 862 | /* |
| @@ -864,35 +864,35 @@ | |||
| 864 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | 864 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, |
| 865 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | 865 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST |
| 866 | */ | 866 | */ |
| 867 | #define OMAP4430_POWERSTATEST_SHIFT (1 << 0) | 867 | #define OMAP4430_POWERSTATEST_SHIFT 0 |
| 868 | #define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) | 868 | #define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) |
| 869 | 869 | ||
| 870 | /* Used by PRM_PWRREQCTRL */ | 870 | /* Used by PRM_PWRREQCTRL */ |
| 871 | #define OMAP4430_PWRREQ_COND_SHIFT (1 << 0) | 871 | #define OMAP4430_PWRREQ_COND_SHIFT 0 |
| 872 | #define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) | 872 | #define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) |
| 873 | 873 | ||
| 874 | /* Used by PRM_VC_CFG_CHANNEL */ | 874 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 875 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT (1 << 3) | 875 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 |
| 876 | #define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) | 876 | #define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) |
| 877 | 877 | ||
| 878 | /* Used by PRM_VC_CFG_CHANNEL */ | 878 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 879 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT (1 << 11) | 879 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 |
| 880 | #define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) | 880 | #define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) |
| 881 | 881 | ||
| 882 | /* Used by PRM_VC_CFG_CHANNEL */ | 882 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 883 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT (1 << 20) | 883 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 |
| 884 | #define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) | 884 | #define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) |
| 885 | 885 | ||
| 886 | /* Used by PRM_VC_CFG_CHANNEL */ | 886 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 887 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT (1 << 2) | 887 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 |
| 888 | #define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) | 888 | #define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) |
| 889 | 889 | ||
| 890 | /* Used by PRM_VC_CFG_CHANNEL */ | 890 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 891 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT (1 << 10) | 891 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 |
| 892 | #define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) | 892 | #define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) |
| 893 | 893 | ||
| 894 | /* Used by PRM_VC_CFG_CHANNEL */ | 894 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 895 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT (1 << 19) | 895 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 |
| 896 | #define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) | 896 | #define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) |
| 897 | 897 | ||
| 898 | /* | 898 | /* |
| @@ -900,7 +900,7 @@ | |||
| 900 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | 900 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 901 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 901 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 902 | */ | 902 | */ |
| 903 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT (1 << 16) | 903 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
| 904 | #define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) | 904 | #define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) |
| 905 | 905 | ||
| 906 | /* | 906 | /* |
| @@ -908,7 +908,7 @@ | |||
| 908 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | 908 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 909 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 909 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 910 | */ | 910 | */ |
| 911 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT (1 << 24) | 911 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 |
| 912 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) | 912 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) |
| 913 | 913 | ||
| 914 | /* | 914 | /* |
| @@ -916,7 +916,7 @@ | |||
| 916 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | 916 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 917 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 917 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 918 | */ | 918 | */ |
| 919 | #define OMAP4430_RAMP_UP_COUNT_SHIFT (1 << 0) | 919 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
| 920 | #define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) | 920 | #define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) |
| 921 | 921 | ||
| 922 | /* | 922 | /* |
| @@ -924,1282 +924,1282 @@ | |||
| 924 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | 924 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 925 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 925 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 926 | */ | 926 | */ |
| 927 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT (1 << 8) | 927 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
| 928 | #define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) | 928 | #define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) |
| 929 | 929 | ||
| 930 | /* Used by PRM_VC_CFG_CHANNEL */ | 930 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 931 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT (1 << 1) | 931 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 |
| 932 | #define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) | 932 | #define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) |
| 933 | 933 | ||
| 934 | /* Used by PRM_VC_CFG_CHANNEL */ | 934 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 935 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT (1 << 9) | 935 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 |
| 936 | #define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) | 936 | #define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) |
| 937 | 937 | ||
| 938 | /* Used by PRM_VC_CFG_CHANNEL */ | 938 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 939 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT (1 << 18) | 939 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 |
| 940 | #define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) | 940 | #define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) |
| 941 | 941 | ||
| 942 | /* Used by PRM_VC_VAL_BYPASS */ | 942 | /* Used by PRM_VC_VAL_BYPASS */ |
| 943 | #define OMAP4430_REGADDR_SHIFT (1 << 8) | 943 | #define OMAP4430_REGADDR_SHIFT 8 |
| 944 | #define OMAP4430_REGADDR_MASK BITFIELD(8, 15) | 944 | #define OMAP4430_REGADDR_MASK BITFIELD(8, 15) |
| 945 | 945 | ||
| 946 | /* | 946 | /* |
| 947 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 947 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 948 | * PRM_VC_VAL_CMD_VDD_MPU_L | 948 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 949 | */ | 949 | */ |
| 950 | #define OMAP4430_RET_SHIFT (1 << 8) | 950 | #define OMAP4430_RET_SHIFT 8 |
| 951 | #define OMAP4430_RET_MASK BITFIELD(8, 15) | 951 | #define OMAP4430_RET_MASK BITFIELD(8, 15) |
| 952 | 952 | ||
| 953 | /* Used by PM_L4PER_PWRSTCTRL */ | 953 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 954 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT (1 << 16) | 954 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 |
| 955 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) | 955 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) |
| 956 | 956 | ||
| 957 | /* Used by PM_L4PER_PWRSTCTRL */ | 957 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 958 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT (1 << 8) | 958 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 |
| 959 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) | 959 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) |
| 960 | 960 | ||
| 961 | /* Used by PM_L4PER_PWRSTST */ | 961 | /* Used by PM_L4PER_PWRSTST */ |
| 962 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT (1 << 4) | 962 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 |
| 963 | #define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) | 963 | #define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) |
| 964 | 964 | ||
| 965 | /* | 965 | /* |
| 966 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | 966 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, |
| 967 | * PRM_LDO_SRAM_MPU_CTRL | 967 | * PRM_LDO_SRAM_MPU_CTRL |
| 968 | */ | 968 | */ |
| 969 | #define OMAP4430_RETMODE_ENABLE_SHIFT (1 << 0) | 969 | #define OMAP4430_RETMODE_ENABLE_SHIFT 0 |
| 970 | #define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) | 970 | #define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) |
| 971 | 971 | ||
| 972 | /* Used by REVISION_PRM */ | 972 | /* Used by REVISION_PRM */ |
| 973 | #define OMAP4430_REV_SHIFT (1 << 0) | 973 | #define OMAP4430_REV_SHIFT 0 |
| 974 | #define OMAP4430_REV_MASK BITFIELD(0, 7) | 974 | #define OMAP4430_REV_MASK BITFIELD(0, 7) |
| 975 | 975 | ||
| 976 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ | 976 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ |
| 977 | #define OMAP4430_RST1_SHIFT (1 << 0) | 977 | #define OMAP4430_RST1_SHIFT 0 |
| 978 | #define OMAP4430_RST1_MASK BITFIELD(0, 0) | 978 | #define OMAP4430_RST1_MASK BITFIELD(0, 0) |
| 979 | 979 | ||
| 980 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ | 980 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ |
| 981 | #define OMAP4430_RST1ST_SHIFT (1 << 0) | 981 | #define OMAP4430_RST1ST_SHIFT 0 |
| 982 | #define OMAP4430_RST1ST_MASK BITFIELD(0, 0) | 982 | #define OMAP4430_RST1ST_MASK BITFIELD(0, 0) |
| 983 | 983 | ||
| 984 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ | 984 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ |
| 985 | #define OMAP4430_RST2_SHIFT (1 << 1) | 985 | #define OMAP4430_RST2_SHIFT 1 |
| 986 | #define OMAP4430_RST2_MASK BITFIELD(1, 1) | 986 | #define OMAP4430_RST2_MASK BITFIELD(1, 1) |
| 987 | 987 | ||
| 988 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ | 988 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ |
| 989 | #define OMAP4430_RST2ST_SHIFT (1 << 1) | 989 | #define OMAP4430_RST2ST_SHIFT 1 |
| 990 | #define OMAP4430_RST2ST_MASK BITFIELD(1, 1) | 990 | #define OMAP4430_RST2ST_MASK BITFIELD(1, 1) |
| 991 | 991 | ||
| 992 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ | 992 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ |
| 993 | #define OMAP4430_RST3_SHIFT (1 << 2) | 993 | #define OMAP4430_RST3_SHIFT 2 |
| 994 | #define OMAP4430_RST3_MASK BITFIELD(2, 2) | 994 | #define OMAP4430_RST3_MASK BITFIELD(2, 2) |
| 995 | 995 | ||
| 996 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ | 996 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ |
| 997 | #define OMAP4430_RST3ST_SHIFT (1 << 2) | 997 | #define OMAP4430_RST3ST_SHIFT 2 |
| 998 | #define OMAP4430_RST3ST_MASK BITFIELD(2, 2) | 998 | #define OMAP4430_RST3ST_MASK BITFIELD(2, 2) |
| 999 | 999 | ||
| 1000 | /* Used by PRM_RSTTIME */ | 1000 | /* Used by PRM_RSTTIME */ |
| 1001 | #define OMAP4430_RSTTIME1_SHIFT (1 << 0) | 1001 | #define OMAP4430_RSTTIME1_SHIFT 0 |
| 1002 | #define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) | 1002 | #define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) |
| 1003 | 1003 | ||
| 1004 | /* Used by PRM_RSTTIME */ | 1004 | /* Used by PRM_RSTTIME */ |
| 1005 | #define OMAP4430_RSTTIME2_SHIFT (1 << 10) | 1005 | #define OMAP4430_RSTTIME2_SHIFT 10 |
| 1006 | #define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) | 1006 | #define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) |
| 1007 | 1007 | ||
| 1008 | /* Used by PRM_RSTCTRL */ | 1008 | /* Used by PRM_RSTCTRL */ |
| 1009 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT (1 << 1) | 1009 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 |
| 1010 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) | 1010 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) |
| 1011 | 1011 | ||
| 1012 | /* Used by PRM_RSTCTRL */ | 1012 | /* Used by PRM_RSTCTRL */ |
| 1013 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT (1 << 0) | 1013 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 |
| 1014 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) | 1014 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) |
| 1015 | 1015 | ||
| 1016 | /* Used by PRM_VC_CFG_CHANNEL */ | 1016 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 1017 | #define OMAP4430_SA_VDD_CORE_L_SHIFT (1 << 0) | 1017 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
| 1018 | #define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) | 1018 | #define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) |
| 1019 | 1019 | ||
| 1020 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ | 1020 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ |
| 1021 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT (1 << 0) | 1021 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 |
| 1022 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) | 1022 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) |
| 1023 | 1023 | ||
| 1024 | /* Used by PRM_VC_CFG_CHANNEL */ | 1024 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 1025 | #define OMAP4430_SA_VDD_IVA_L_SHIFT (1 << 8) | 1025 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
| 1026 | #define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) | 1026 | #define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) |
| 1027 | 1027 | ||
| 1028 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ | 1028 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ |
| 1029 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT (1 << 8) | 1029 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 |
| 1030 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) | 1030 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) |
| 1031 | 1031 | ||
| 1032 | /* Used by PRM_VC_CFG_CHANNEL */ | 1032 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 1033 | #define OMAP4430_SA_VDD_MPU_L_SHIFT (1 << 16) | 1033 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
| 1034 | #define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) | 1034 | #define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) |
| 1035 | 1035 | ||
| 1036 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ | 1036 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ |
| 1037 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT (1 << 16) | 1037 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 |
| 1038 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) | 1038 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) |
| 1039 | 1039 | ||
| 1040 | /* Used by PRM_VC_CFG_I2C_CLK */ | 1040 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 1041 | #define OMAP4430_SCLH_SHIFT (1 << 0) | 1041 | #define OMAP4430_SCLH_SHIFT 0 |
| 1042 | #define OMAP4430_SCLH_MASK BITFIELD(0, 7) | 1042 | #define OMAP4430_SCLH_MASK BITFIELD(0, 7) |
| 1043 | 1043 | ||
| 1044 | /* Used by PRM_VC_CFG_I2C_CLK */ | 1044 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 1045 | #define OMAP4430_SCLL_SHIFT (1 << 8) | 1045 | #define OMAP4430_SCLL_SHIFT 8 |
| 1046 | #define OMAP4430_SCLL_MASK BITFIELD(8, 15) | 1046 | #define OMAP4430_SCLL_MASK BITFIELD(8, 15) |
| 1047 | 1047 | ||
| 1048 | /* Used by PRM_RSTST */ | 1048 | /* Used by PRM_RSTST */ |
| 1049 | #define OMAP4430_SECURE_WDT_RST_SHIFT (1 << 4) | 1049 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
| 1050 | #define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) | 1050 | #define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) |
| 1051 | 1051 | ||
| 1052 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1052 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1053 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT (1 << 18) | 1053 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 |
| 1054 | #define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) | 1054 | #define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) |
| 1055 | 1055 | ||
| 1056 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1056 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1057 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT (1 << 9) | 1057 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 |
| 1058 | #define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) | 1058 | #define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) |
| 1059 | 1059 | ||
| 1060 | /* Used by PM_IVAHD_PWRSTST */ | 1060 | /* Used by PM_IVAHD_PWRSTST */ |
| 1061 | #define OMAP4430_SL2_MEM_STATEST_SHIFT (1 << 6) | 1061 | #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 |
| 1062 | #define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) | 1062 | #define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) |
| 1063 | 1063 | ||
| 1064 | /* Used by PRM_VC_VAL_BYPASS */ | 1064 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1065 | #define OMAP4430_SLAVEADDR_SHIFT (1 << 0) | 1065 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
| 1066 | #define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) | 1066 | #define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) |
| 1067 | 1067 | ||
| 1068 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 1068 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 1069 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT (1 << 3) | 1069 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 |
| 1070 | #define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) | 1070 | #define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) |
| 1071 | 1071 | ||
| 1072 | /* Used by PRM_SRAM_COUNT */ | 1072 | /* Used by PRM_SRAM_COUNT */ |
| 1073 | #define OMAP4430_SLPCNT_VALUE_SHIFT (1 << 16) | 1073 | #define OMAP4430_SLPCNT_VALUE_SHIFT 16 |
| 1074 | #define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) | 1074 | #define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) |
| 1075 | 1075 | ||
| 1076 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | 1076 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ |
| 1077 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT (1 << 8) | 1077 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
| 1078 | #define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) | 1078 | #define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) |
| 1079 | 1079 | ||
| 1080 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | 1080 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ |
| 1081 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT (1 << 8) | 1081 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
| 1082 | #define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) | 1082 | #define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) |
| 1083 | 1083 | ||
| 1084 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 1084 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 1085 | #define OMAP4430_SR2EN_SHIFT (1 << 0) | 1085 | #define OMAP4430_SR2EN_SHIFT 0 |
| 1086 | #define OMAP4430_SR2EN_MASK BITFIELD(0, 0) | 1086 | #define OMAP4430_SR2EN_MASK BITFIELD(0, 0) |
| 1087 | 1087 | ||
| 1088 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 1088 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 1089 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT (1 << 6) | 1089 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 |
| 1090 | #define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) | 1090 | #define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) |
| 1091 | 1091 | ||
| 1092 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 1092 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 1093 | #define OMAP4430_SR2_STATUS_SHIFT (1 << 3) | 1093 | #define OMAP4430_SR2_STATUS_SHIFT 3 |
| 1094 | #define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) | 1094 | #define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) |
| 1095 | 1095 | ||
| 1096 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 1096 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 1097 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT (1 << 8) | 1097 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 |
| 1098 | #define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) | 1098 | #define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) |
| 1099 | 1099 | ||
| 1100 | /* | 1100 | /* |
| 1101 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | 1101 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, |
| 1102 | * PRM_LDO_SRAM_MPU_CTRL | 1102 | * PRM_LDO_SRAM_MPU_CTRL |
| 1103 | */ | 1103 | */ |
| 1104 | #define OMAP4430_SRAMLDO_STATUS_SHIFT (1 << 8) | 1104 | #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 |
| 1105 | #define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) | 1105 | #define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) |
| 1106 | 1106 | ||
| 1107 | /* | 1107 | /* |
| 1108 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | 1108 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, |
| 1109 | * PRM_LDO_SRAM_MPU_CTRL | 1109 | * PRM_LDO_SRAM_MPU_CTRL |
| 1110 | */ | 1110 | */ |
| 1111 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT (1 << 9) | 1111 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 |
| 1112 | #define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) | 1112 | #define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) |
| 1113 | 1113 | ||
| 1114 | /* Used by PRM_VC_CFG_I2C_MODE */ | 1114 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 1115 | #define OMAP4430_SRMODEEN_SHIFT (1 << 4) | 1115 | #define OMAP4430_SRMODEEN_SHIFT 4 |
| 1116 | #define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) | 1116 | #define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) |
| 1117 | 1117 | ||
| 1118 | /* Used by PRM_VOLTSETUP_WARMRESET */ | 1118 | /* Used by PRM_VOLTSETUP_WARMRESET */ |
| 1119 | #define OMAP4430_STABLE_COUNT_SHIFT (1 << 0) | 1119 | #define OMAP4430_STABLE_COUNT_SHIFT 0 |
| 1120 | #define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) | 1120 | #define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) |
| 1121 | 1121 | ||
| 1122 | /* Used by PRM_VOLTSETUP_WARMRESET */ | 1122 | /* Used by PRM_VOLTSETUP_WARMRESET */ |
| 1123 | #define OMAP4430_STABLE_PRESCAL_SHIFT (1 << 8) | 1123 | #define OMAP4430_STABLE_PRESCAL_SHIFT 8 |
| 1124 | #define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) | 1124 | #define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) |
| 1125 | 1125 | ||
| 1126 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1126 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1127 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT (1 << 20) | 1127 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 |
| 1128 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) | 1128 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) |
| 1129 | 1129 | ||
| 1130 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1130 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1131 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT (1 << 10) | 1131 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 |
| 1132 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) | 1132 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) |
| 1133 | 1133 | ||
| 1134 | /* Used by PM_IVAHD_PWRSTST */ | 1134 | /* Used by PM_IVAHD_PWRSTST */ |
| 1135 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT (1 << 8) | 1135 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 |
| 1136 | #define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) | 1136 | #define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) |
| 1137 | 1137 | ||
| 1138 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1138 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1139 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT (1 << 22) | 1139 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 |
| 1140 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) | 1140 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) |
| 1141 | 1141 | ||
| 1142 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1142 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1143 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT (1 << 11) | 1143 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 |
| 1144 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) | 1144 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) |
| 1145 | 1145 | ||
| 1146 | /* Used by PM_IVAHD_PWRSTST */ | 1146 | /* Used by PM_IVAHD_PWRSTST */ |
| 1147 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT (1 << 10) | 1147 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 |
| 1148 | #define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) | 1148 | #define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) |
| 1149 | 1149 | ||
| 1150 | /* Used by RM_TESLA_RSTST */ | 1150 | /* Used by RM_TESLA_RSTST */ |
| 1151 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT (1 << 2) | 1151 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 |
| 1152 | #define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) | 1152 | #define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) |
| 1153 | 1153 | ||
| 1154 | /* Used by RM_TESLA_RSTST */ | 1154 | /* Used by RM_TESLA_RSTST */ |
| 1155 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT (1 << 3) | 1155 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 |
| 1156 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) | 1156 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) |
| 1157 | 1157 | ||
| 1158 | /* Used by PM_TESLA_PWRSTCTRL */ | 1158 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1159 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT (1 << 20) | 1159 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 |
| 1160 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) | 1160 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) |
| 1161 | 1161 | ||
| 1162 | /* Used by PM_TESLA_PWRSTCTRL */ | 1162 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1163 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT (1 << 10) | 1163 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 |
| 1164 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) | 1164 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) |
| 1165 | 1165 | ||
| 1166 | /* Used by PM_TESLA_PWRSTST */ | 1166 | /* Used by PM_TESLA_PWRSTST */ |
| 1167 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT (1 << 8) | 1167 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 |
| 1168 | #define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) | 1168 | #define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) |
| 1169 | 1169 | ||
| 1170 | /* Used by PM_TESLA_PWRSTCTRL */ | 1170 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1171 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT (1 << 16) | 1171 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 |
| 1172 | #define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) | 1172 | #define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) |
| 1173 | 1173 | ||
| 1174 | /* Used by PM_TESLA_PWRSTCTRL */ | 1174 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1175 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT (1 << 8) | 1175 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 |
| 1176 | #define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) | 1176 | #define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) |
| 1177 | 1177 | ||
| 1178 | /* Used by PM_TESLA_PWRSTST */ | 1178 | /* Used by PM_TESLA_PWRSTST */ |
| 1179 | #define OMAP4430_TESLA_L1_STATEST_SHIFT (1 << 4) | 1179 | #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 |
| 1180 | #define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) | 1180 | #define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) |
| 1181 | 1181 | ||
| 1182 | /* Used by PM_TESLA_PWRSTCTRL */ | 1182 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1183 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT (1 << 18) | 1183 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 |
| 1184 | #define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) | 1184 | #define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) |
| 1185 | 1185 | ||
| 1186 | /* Used by PM_TESLA_PWRSTCTRL */ | 1186 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1187 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT (1 << 9) | 1187 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 |
| 1188 | #define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) | 1188 | #define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) |
| 1189 | 1189 | ||
| 1190 | /* Used by PM_TESLA_PWRSTST */ | 1190 | /* Used by PM_TESLA_PWRSTST */ |
| 1191 | #define OMAP4430_TESLA_L2_STATEST_SHIFT (1 << 6) | 1191 | #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 |
| 1192 | #define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) | 1192 | #define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) |
| 1193 | 1193 | ||
| 1194 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | 1194 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1195 | #define OMAP4430_TIMEOUT_SHIFT (1 << 0) | 1195 | #define OMAP4430_TIMEOUT_SHIFT 0 |
| 1196 | #define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) | 1196 | #define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) |
| 1197 | 1197 | ||
| 1198 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 1198 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 1199 | #define OMAP4430_TIMEOUTEN_SHIFT (1 << 3) | 1199 | #define OMAP4430_TIMEOUTEN_SHIFT 3 |
| 1200 | #define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) | 1200 | #define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) |
| 1201 | 1201 | ||
| 1202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1203 | #define OMAP4430_TRANSITION_EN_SHIFT (1 << 8) | 1203 | #define OMAP4430_TRANSITION_EN_SHIFT 8 |
| 1204 | #define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) | 1204 | #define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) |
| 1205 | 1205 | ||
| 1206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1207 | #define OMAP4430_TRANSITION_ST_SHIFT (1 << 8) | 1207 | #define OMAP4430_TRANSITION_ST_SHIFT 8 |
| 1208 | #define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) | 1208 | #define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) |
| 1209 | 1209 | ||
| 1210 | /* Used by PRM_VC_VAL_BYPASS */ | 1210 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1211 | #define OMAP4430_VALID_SHIFT (1 << 24) | 1211 | #define OMAP4430_VALID_SHIFT 24 |
| 1212 | #define OMAP4430_VALID_MASK BITFIELD(24, 24) | 1212 | #define OMAP4430_VALID_MASK BITFIELD(24, 24) |
| 1213 | 1213 | ||
| 1214 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1214 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1215 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT (1 << 14) | 1215 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 |
| 1216 | #define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) | 1216 | #define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) |
| 1217 | 1217 | ||
| 1218 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1218 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1219 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT (1 << 14) | 1219 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 |
| 1220 | #define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) | 1220 | #define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) |
| 1221 | 1221 | ||
| 1222 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1222 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1223 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT (1 << 30) | 1223 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 |
| 1224 | #define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) | 1224 | #define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) |
| 1225 | 1225 | ||
| 1226 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1226 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1227 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT (1 << 30) | 1227 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 |
| 1228 | #define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) | 1228 | #define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) |
| 1229 | 1229 | ||
| 1230 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1230 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1231 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT (1 << 6) | 1231 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 |
| 1232 | #define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) | 1232 | #define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) |
| 1233 | 1233 | ||
| 1234 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1234 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1235 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT (1 << 6) | 1235 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 |
| 1236 | #define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) | 1236 | #define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) |
| 1237 | 1237 | ||
| 1238 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1238 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1239 | #define OMAP4430_VC_RAERR_EN_SHIFT (1 << 12) | 1239 | #define OMAP4430_VC_RAERR_EN_SHIFT 12 |
| 1240 | #define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) | 1240 | #define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) |
| 1241 | 1241 | ||
| 1242 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1242 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1243 | #define OMAP4430_VC_RAERR_ST_SHIFT (1 << 12) | 1243 | #define OMAP4430_VC_RAERR_ST_SHIFT 12 |
| 1244 | #define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) | 1244 | #define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) |
| 1245 | 1245 | ||
| 1246 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1246 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1247 | #define OMAP4430_VC_SAERR_EN_SHIFT (1 << 11) | 1247 | #define OMAP4430_VC_SAERR_EN_SHIFT 11 |
| 1248 | #define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) | 1248 | #define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) |
| 1249 | 1249 | ||
| 1250 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1250 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1251 | #define OMAP4430_VC_SAERR_ST_SHIFT (1 << 11) | 1251 | #define OMAP4430_VC_SAERR_ST_SHIFT 11 |
| 1252 | #define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) | 1252 | #define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) |
| 1253 | 1253 | ||
| 1254 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1254 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1255 | #define OMAP4430_VC_TOERR_EN_SHIFT (1 << 13) | 1255 | #define OMAP4430_VC_TOERR_EN_SHIFT 13 |
| 1256 | #define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) | 1256 | #define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) |
| 1257 | 1257 | ||
| 1258 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1258 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1259 | #define OMAP4430_VC_TOERR_ST_SHIFT (1 << 13) | 1259 | #define OMAP4430_VC_TOERR_ST_SHIFT 13 |
| 1260 | #define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) | 1260 | #define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) |
| 1261 | 1261 | ||
| 1262 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | 1262 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1263 | #define OMAP4430_VDDMAX_SHIFT (1 << 24) | 1263 | #define OMAP4430_VDDMAX_SHIFT 24 |
| 1264 | #define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) | 1264 | #define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) |
| 1265 | 1265 | ||
| 1266 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | 1266 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1267 | #define OMAP4430_VDDMIN_SHIFT (1 << 16) | 1267 | #define OMAP4430_VDDMIN_SHIFT 16 |
| 1268 | #define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) | 1268 | #define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) |
| 1269 | 1269 | ||
| 1270 | /* Used by PRM_VOLTCTRL */ | 1270 | /* Used by PRM_VOLTCTRL */ |
| 1271 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT (1 << 12) | 1271 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 |
| 1272 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) | 1272 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) |
| 1273 | 1273 | ||
| 1274 | /* Used by PRM_RSTST */ | 1274 | /* Used by PRM_RSTST */ |
| 1275 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT (1 << 8) | 1275 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
| 1276 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) | 1276 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) |
| 1277 | 1277 | ||
| 1278 | /* Used by PRM_VOLTCTRL */ | 1278 | /* Used by PRM_VOLTCTRL */ |
| 1279 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT (1 << 14) | 1279 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 |
| 1280 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) | 1280 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) |
| 1281 | 1281 | ||
| 1282 | /* Used by PRM_VOLTCTRL */ | 1282 | /* Used by PRM_VOLTCTRL */ |
| 1283 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT (1 << 9) | 1283 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 |
| 1284 | #define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) | 1284 | #define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) |
| 1285 | 1285 | ||
| 1286 | /* Used by PRM_RSTST */ | 1286 | /* Used by PRM_RSTST */ |
| 1287 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT (1 << 7) | 1287 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
| 1288 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) | 1288 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) |
| 1289 | 1289 | ||
| 1290 | /* Used by PRM_VOLTCTRL */ | 1290 | /* Used by PRM_VOLTCTRL */ |
| 1291 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT (1 << 13) | 1291 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 |
| 1292 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) | 1292 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) |
| 1293 | 1293 | ||
| 1294 | /* Used by PRM_VOLTCTRL */ | 1294 | /* Used by PRM_VOLTCTRL */ |
| 1295 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT (1 << 8) | 1295 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 |
| 1296 | #define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) | 1296 | #define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) |
| 1297 | 1297 | ||
| 1298 | /* Used by PRM_RSTST */ | 1298 | /* Used by PRM_RSTST */ |
| 1299 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT (1 << 6) | 1299 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
| 1300 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) | 1300 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) |
| 1301 | 1301 | ||
| 1302 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | 1302 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ |
| 1303 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT (1 << 0) | 1303 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 |
| 1304 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) | 1304 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) |
| 1305 | 1305 | ||
| 1306 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | 1306 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ |
| 1307 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT (1 << 8) | 1307 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 |
| 1308 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) | 1308 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) |
| 1309 | 1309 | ||
| 1310 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | 1310 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ |
| 1311 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT (1 << 16) | 1311 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 |
| 1312 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) | 1312 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) |
| 1313 | 1313 | ||
| 1314 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 1314 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 1315 | #define OMAP4430_VPENABLE_SHIFT (1 << 0) | 1315 | #define OMAP4430_VPENABLE_SHIFT 0 |
| 1316 | #define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) | 1316 | #define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) |
| 1317 | 1317 | ||
| 1318 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ | 1318 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ |
| 1319 | #define OMAP4430_VPINIDLE_SHIFT (1 << 0) | 1319 | #define OMAP4430_VPINIDLE_SHIFT 0 |
| 1320 | #define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) | 1320 | #define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) |
| 1321 | 1321 | ||
| 1322 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | 1322 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ |
| 1323 | #define OMAP4430_VPVOLTAGE_SHIFT (1 << 0) | 1323 | #define OMAP4430_VPVOLTAGE_SHIFT 0 |
| 1324 | #define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) | 1324 | #define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) |
| 1325 | 1325 | ||
| 1326 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1326 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1327 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT (1 << 20) | 1327 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 |
| 1328 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) | 1328 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) |
| 1329 | 1329 | ||
| 1330 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1330 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1331 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT (1 << 20) | 1331 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 |
| 1332 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) | 1332 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) |
| 1333 | 1333 | ||
| 1334 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1334 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1335 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT (1 << 18) | 1335 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 |
| 1336 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) | 1336 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) |
| 1337 | 1337 | ||
| 1338 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1338 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1339 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT (1 << 18) | 1339 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 |
| 1340 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) | 1340 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) |
| 1341 | 1341 | ||
| 1342 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1342 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1343 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT (1 << 17) | 1343 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 |
| 1344 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) | 1344 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) |
| 1345 | 1345 | ||
| 1346 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1346 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1347 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT (1 << 17) | 1347 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 |
| 1348 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) | 1348 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) |
| 1349 | 1349 | ||
| 1350 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1350 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1351 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT (1 << 19) | 1351 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 |
| 1352 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) | 1352 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) |
| 1353 | 1353 | ||
| 1354 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1354 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1355 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT (1 << 19) | 1355 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 |
| 1356 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) | 1356 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) |
| 1357 | 1357 | ||
| 1358 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1358 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1359 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT (1 << 16) | 1359 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 |
| 1360 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) | 1360 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) |
| 1361 | 1361 | ||
| 1362 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1362 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1363 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT (1 << 16) | 1363 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 |
| 1364 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) | 1364 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) |
| 1365 | 1365 | ||
| 1366 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1366 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1367 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT (1 << 21) | 1367 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 |
| 1368 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) | 1368 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) |
| 1369 | 1369 | ||
| 1370 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1370 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1371 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT (1 << 21) | 1371 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 |
| 1372 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) | 1372 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) |
| 1373 | 1373 | ||
| 1374 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1374 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1375 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT (1 << 28) | 1375 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 |
| 1376 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) | 1376 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) |
| 1377 | 1377 | ||
| 1378 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1378 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1379 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT (1 << 28) | 1379 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 |
| 1380 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) | 1380 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) |
| 1381 | 1381 | ||
| 1382 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1382 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1383 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT (1 << 26) | 1383 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 |
| 1384 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) | 1384 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) |
| 1385 | 1385 | ||
| 1386 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1386 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1387 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT (1 << 26) | 1387 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 |
| 1388 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) | 1388 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) |
| 1389 | 1389 | ||
| 1390 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1390 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1391 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT (1 << 25) | 1391 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 |
| 1392 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) | 1392 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) |
| 1393 | 1393 | ||
| 1394 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1394 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1395 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT (1 << 25) | 1395 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 |
| 1396 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) | 1396 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) |
| 1397 | 1397 | ||
| 1398 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1398 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1399 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT (1 << 27) | 1399 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 |
| 1400 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) | 1400 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) |
| 1401 | 1401 | ||
| 1402 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1402 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1403 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT (1 << 27) | 1403 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 |
| 1404 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) | 1404 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) |
| 1405 | 1405 | ||
| 1406 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1406 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1407 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT (1 << 24) | 1407 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 |
| 1408 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) | 1408 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) |
| 1409 | 1409 | ||
| 1410 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1410 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1411 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT (1 << 24) | 1411 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 |
| 1412 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) | 1412 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) |
| 1413 | 1413 | ||
| 1414 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1414 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1415 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT (1 << 29) | 1415 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 |
| 1416 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) | 1416 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) |
| 1417 | 1417 | ||
| 1418 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1418 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1419 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT (1 << 29) | 1419 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 |
| 1420 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) | 1420 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) |
| 1421 | 1421 | ||
| 1422 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1422 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1423 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT (1 << 4) | 1423 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 |
| 1424 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) | 1424 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) |
| 1425 | 1425 | ||
| 1426 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1426 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1427 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT (1 << 4) | 1427 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 |
| 1428 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) | 1428 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) |
| 1429 | 1429 | ||
| 1430 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1430 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1431 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT (1 << 2) | 1431 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 |
| 1432 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) | 1432 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) |
| 1433 | 1433 | ||
| 1434 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1434 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1435 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT (1 << 2) | 1435 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 |
| 1436 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) | 1436 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) |
| 1437 | 1437 | ||
| 1438 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1438 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1439 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT (1 << 1) | 1439 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 |
| 1440 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) | 1440 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) |
| 1441 | 1441 | ||
| 1442 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1442 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1443 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT (1 << 1) | 1443 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 |
| 1444 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) | 1444 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) |
| 1445 | 1445 | ||
| 1446 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1446 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1447 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT (1 << 3) | 1447 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 |
| 1448 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) | 1448 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) |
| 1449 | 1449 | ||
| 1450 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1450 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1451 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT (1 << 3) | 1451 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 |
| 1452 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) | 1452 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) |
| 1453 | 1453 | ||
| 1454 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1454 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1455 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT (1 << 0) | 1455 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 |
| 1456 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) | 1456 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) |
| 1457 | 1457 | ||
| 1458 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1458 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1459 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT (1 << 0) | 1459 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 |
| 1460 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) | 1460 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) |
| 1461 | 1461 | ||
| 1462 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1462 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1463 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT (1 << 5) | 1463 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 |
| 1464 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) | 1464 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) |
| 1465 | 1465 | ||
| 1466 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1466 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1467 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT (1 << 5) | 1467 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 |
| 1468 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) | 1468 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) |
| 1469 | 1469 | ||
| 1470 | /* Used by PRM_SRAM_COUNT */ | 1470 | /* Used by PRM_SRAM_COUNT */ |
| 1471 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT (1 << 8) | 1471 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 |
| 1472 | #define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) | 1472 | #define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) |
| 1473 | 1473 | ||
| 1474 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | 1474 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ |
| 1475 | #define OMAP4430_VSTEPMAX_SHIFT (1 << 0) | 1475 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
| 1476 | #define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) | 1476 | #define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) |
| 1477 | 1477 | ||
| 1478 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | 1478 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ |
| 1479 | #define OMAP4430_VSTEPMIN_SHIFT (1 << 0) | 1479 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
| 1480 | #define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) | 1480 | #define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) |
| 1481 | 1481 | ||
| 1482 | /* Used by PRM_MODEM_IF_CTRL */ | 1482 | /* Used by PRM_MODEM_IF_CTRL */ |
| 1483 | #define OMAP4430_WAKE_MODEM_SHIFT (1 << 0) | 1483 | #define OMAP4430_WAKE_MODEM_SHIFT 0 |
| 1484 | #define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) | 1484 | #define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) |
| 1485 | 1485 | ||
| 1486 | /* Used by PM_DSS_DSS_WKDEP */ | 1486 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1487 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT (1 << 1) | 1487 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 |
| 1488 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) | 1488 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) |
| 1489 | 1489 | ||
| 1490 | /* Used by PM_DSS_DSS_WKDEP */ | 1490 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1491 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT (1 << 0) | 1491 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 |
| 1492 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) | 1492 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) |
| 1493 | 1493 | ||
| 1494 | /* Used by PM_DSS_DSS_WKDEP */ | 1494 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1495 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT (1 << 3) | 1495 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 |
| 1496 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) | 1496 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) |
| 1497 | 1497 | ||
| 1498 | /* Used by PM_DSS_DSS_WKDEP */ | 1498 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1499 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT (1 << 2) | 1499 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 |
| 1500 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) | 1500 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) |
| 1501 | 1501 | ||
| 1502 | /* Used by PM_ABE_DMIC_WKDEP */ | 1502 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1503 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT (1 << 7) | 1503 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 |
| 1504 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) | 1504 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1505 | 1505 | ||
| 1506 | /* Used by PM_ABE_DMIC_WKDEP */ | 1506 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1507 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT (1 << 6) | 1507 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 |
| 1508 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) | 1508 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) |
| 1509 | 1509 | ||
| 1510 | /* Used by PM_ABE_DMIC_WKDEP */ | 1510 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1511 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT (1 << 0) | 1511 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 |
| 1512 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) | 1512 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1513 | 1513 | ||
| 1514 | /* Used by PM_ABE_DMIC_WKDEP */ | 1514 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1515 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT (1 << 2) | 1515 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 |
| 1516 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) | 1516 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 1517 | 1517 | ||
| 1518 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ | 1518 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ |
| 1519 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT (1 << 0) | 1519 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 |
| 1520 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) | 1520 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) |
| 1521 | 1521 | ||
| 1522 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | 1522 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ |
| 1523 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT (1 << 1) | 1523 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 |
| 1524 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) | 1524 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) |
| 1525 | 1525 | ||
| 1526 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | 1526 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ |
| 1527 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT (1 << 0) | 1527 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 |
| 1528 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) | 1528 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) |
| 1529 | 1529 | ||
| 1530 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ | 1530 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ |
| 1531 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT (1 << 0) | 1531 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 |
| 1532 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) | 1532 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) |
| 1533 | 1533 | ||
| 1534 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | 1534 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ |
| 1535 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT (1 << 1) | 1535 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 |
| 1536 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) | 1536 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) |
| 1537 | 1537 | ||
| 1538 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | 1538 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ |
| 1539 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT (1 << 0) | 1539 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 |
| 1540 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) | 1540 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) |
| 1541 | 1541 | ||
| 1542 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | 1542 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ |
| 1543 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT (1 << 1) | 1543 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 |
| 1544 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) | 1544 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) |
| 1545 | 1545 | ||
| 1546 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | 1546 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ |
| 1547 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT (1 << 0) | 1547 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 |
| 1548 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) | 1548 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) |
| 1549 | 1549 | ||
| 1550 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | 1550 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ |
| 1551 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT (1 << 1) | 1551 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 |
| 1552 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) | 1552 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) |
| 1553 | 1553 | ||
| 1554 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | 1554 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ |
| 1555 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT (1 << 0) | 1555 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 |
| 1556 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) | 1556 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) |
| 1557 | 1557 | ||
| 1558 | /* Used by PM_DSS_DSS_WKDEP */ | 1558 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1559 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT (1 << 5) | 1559 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 |
| 1560 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) | 1560 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) |
| 1561 | 1561 | ||
| 1562 | /* Used by PM_DSS_DSS_WKDEP */ | 1562 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1563 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT (1 << 4) | 1563 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 |
| 1564 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) | 1564 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) |
| 1565 | 1565 | ||
| 1566 | /* Used by PM_DSS_DSS_WKDEP */ | 1566 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1567 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT (1 << 7) | 1567 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 |
| 1568 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) | 1568 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) |
| 1569 | 1569 | ||
| 1570 | /* Used by PM_DSS_DSS_WKDEP */ | 1570 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1571 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT (1 << 6) | 1571 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 |
| 1572 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) | 1572 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) |
| 1573 | 1573 | ||
| 1574 | /* Used by PM_DSS_DSS_WKDEP */ | 1574 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1575 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT (1 << 9) | 1575 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 |
| 1576 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) | 1576 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) |
| 1577 | 1577 | ||
| 1578 | /* Used by PM_DSS_DSS_WKDEP */ | 1578 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1579 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT (1 << 8) | 1579 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 |
| 1580 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) | 1580 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) |
| 1581 | 1581 | ||
| 1582 | /* Used by PM_DSS_DSS_WKDEP */ | 1582 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1583 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT (1 << 11) | 1583 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 |
| 1584 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) | 1584 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) |
| 1585 | 1585 | ||
| 1586 | /* Used by PM_DSS_DSS_WKDEP */ | 1586 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1587 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT (1 << 10) | 1587 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 |
| 1588 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) | 1588 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) |
| 1589 | 1589 | ||
| 1590 | /* Used by PM_WKUP_GPIO1_WKDEP */ | 1590 | /* Used by PM_WKUP_GPIO1_WKDEP */ |
| 1591 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT (1 << 1) | 1591 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 |
| 1592 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) | 1592 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) |
| 1593 | 1593 | ||
| 1594 | /* Used by PM_WKUP_GPIO1_WKDEP */ | 1594 | /* Used by PM_WKUP_GPIO1_WKDEP */ |
| 1595 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT (1 << 0) | 1595 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 |
| 1596 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) | 1596 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) |
| 1597 | 1597 | ||
| 1598 | /* Used by PM_WKUP_GPIO1_WKDEP */ | 1598 | /* Used by PM_WKUP_GPIO1_WKDEP */ |
| 1599 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT (1 << 6) | 1599 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 |
| 1600 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1600 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) |
| 1601 | 1601 | ||
| 1602 | /* Used by PM_L4PER_GPIO2_WKDEP */ | 1602 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 1603 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT (1 << 1) | 1603 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 |
| 1604 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) | 1604 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) |
| 1605 | 1605 | ||
| 1606 | /* Used by PM_L4PER_GPIO2_WKDEP */ | 1606 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 1607 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT (1 << 0) | 1607 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 |
| 1608 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) | 1608 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) |
| 1609 | 1609 | ||
| 1610 | /* Used by PM_L4PER_GPIO2_WKDEP */ | 1610 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 1611 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT (1 << 6) | 1611 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 |
| 1612 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1612 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) |
| 1613 | 1613 | ||
| 1614 | /* Used by PM_L4PER_GPIO3_WKDEP */ | 1614 | /* Used by PM_L4PER_GPIO3_WKDEP */ |
| 1615 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT (1 << 0) | 1615 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 |
| 1616 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) | 1616 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) |
| 1617 | 1617 | ||
| 1618 | /* Used by PM_L4PER_GPIO3_WKDEP */ | 1618 | /* Used by PM_L4PER_GPIO3_WKDEP */ |
| 1619 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT (1 << 6) | 1619 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 |
| 1620 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1620 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) |
| 1621 | 1621 | ||
| 1622 | /* Used by PM_L4PER_GPIO4_WKDEP */ | 1622 | /* Used by PM_L4PER_GPIO4_WKDEP */ |
| 1623 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT (1 << 0) | 1623 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 |
| 1624 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) | 1624 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) |
| 1625 | 1625 | ||
| 1626 | /* Used by PM_L4PER_GPIO4_WKDEP */ | 1626 | /* Used by PM_L4PER_GPIO4_WKDEP */ |
| 1627 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT (1 << 6) | 1627 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 |
| 1628 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1628 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) |
| 1629 | 1629 | ||
| 1630 | /* Used by PM_L4PER_GPIO5_WKDEP */ | 1630 | /* Used by PM_L4PER_GPIO5_WKDEP */ |
| 1631 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT (1 << 0) | 1631 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 |
| 1632 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) | 1632 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) |
| 1633 | 1633 | ||
| 1634 | /* Used by PM_L4PER_GPIO5_WKDEP */ | 1634 | /* Used by PM_L4PER_GPIO5_WKDEP */ |
| 1635 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT (1 << 6) | 1635 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 |
| 1636 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1636 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) |
| 1637 | 1637 | ||
| 1638 | /* Used by PM_L4PER_GPIO6_WKDEP */ | 1638 | /* Used by PM_L4PER_GPIO6_WKDEP */ |
| 1639 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT (1 << 0) | 1639 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 |
| 1640 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) | 1640 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) |
| 1641 | 1641 | ||
| 1642 | /* Used by PM_L4PER_GPIO6_WKDEP */ | 1642 | /* Used by PM_L4PER_GPIO6_WKDEP */ |
| 1643 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT (1 << 6) | 1643 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 |
| 1644 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1644 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) |
| 1645 | 1645 | ||
| 1646 | /* Used by PM_DSS_DSS_WKDEP */ | 1646 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1647 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT (1 << 19) | 1647 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 |
| 1648 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) | 1648 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) |
| 1649 | 1649 | ||
| 1650 | /* Used by PM_DSS_DSS_WKDEP */ | 1650 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1651 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT (1 << 13) | 1651 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 |
| 1652 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) | 1652 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) |
| 1653 | 1653 | ||
| 1654 | /* Used by PM_DSS_DSS_WKDEP */ | 1654 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1655 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT (1 << 12) | 1655 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 |
| 1656 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) | 1656 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) |
| 1657 | 1657 | ||
| 1658 | /* Used by PM_DSS_DSS_WKDEP */ | 1658 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1659 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT (1 << 14) | 1659 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 |
| 1660 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) | 1660 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) |
| 1661 | 1661 | ||
| 1662 | /* Used by PM_L4PER_HECC1_WKDEP */ | 1662 | /* Used by PM_L4PER_HECC1_WKDEP */ |
| 1663 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT (1 << 0) | 1663 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 |
| 1664 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) | 1664 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) |
| 1665 | 1665 | ||
| 1666 | /* Used by PM_L4PER_HECC2_WKDEP */ | 1666 | /* Used by PM_L4PER_HECC2_WKDEP */ |
| 1667 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT (1 << 0) | 1667 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 |
| 1668 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) | 1668 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) |
| 1669 | 1669 | ||
| 1670 | /* Used by PM_L3INIT_HSI_WKDEP */ | 1670 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 1671 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT (1 << 6) | 1671 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 |
| 1672 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) | 1672 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) |
| 1673 | 1673 | ||
| 1674 | /* Used by PM_L3INIT_HSI_WKDEP */ | 1674 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 1675 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT (1 << 1) | 1675 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 |
| 1676 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) | 1676 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) |
| 1677 | 1677 | ||
| 1678 | /* Used by PM_L3INIT_HSI_WKDEP */ | 1678 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 1679 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT (1 << 0) | 1679 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 |
| 1680 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) | 1680 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) |
| 1681 | 1681 | ||
| 1682 | /* Used by PM_L4PER_I2C1_WKDEP */ | 1682 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 1683 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT (1 << 7) | 1683 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 |
| 1684 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) | 1684 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1685 | 1685 | ||
| 1686 | /* Used by PM_L4PER_I2C1_WKDEP */ | 1686 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 1687 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT (1 << 1) | 1687 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 |
| 1688 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1688 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) |
| 1689 | 1689 | ||
| 1690 | /* Used by PM_L4PER_I2C1_WKDEP */ | 1690 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 1691 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT (1 << 0) | 1691 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 |
| 1692 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) | 1692 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1693 | 1693 | ||
| 1694 | /* Used by PM_L4PER_I2C2_WKDEP */ | 1694 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 1695 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT (1 << 7) | 1695 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 |
| 1696 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) | 1696 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1697 | 1697 | ||
| 1698 | /* Used by PM_L4PER_I2C2_WKDEP */ | 1698 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 1699 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT (1 << 1) | 1699 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 |
| 1700 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1700 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) |
| 1701 | 1701 | ||
| 1702 | /* Used by PM_L4PER_I2C2_WKDEP */ | 1702 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 1703 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT (1 << 0) | 1703 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 |
| 1704 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) | 1704 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1705 | 1705 | ||
| 1706 | /* Used by PM_L4PER_I2C3_WKDEP */ | 1706 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 1707 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT (1 << 7) | 1707 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 |
| 1708 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) | 1708 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1709 | 1709 | ||
| 1710 | /* Used by PM_L4PER_I2C3_WKDEP */ | 1710 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 1711 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT (1 << 1) | 1711 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 |
| 1712 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1712 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) |
| 1713 | 1713 | ||
| 1714 | /* Used by PM_L4PER_I2C3_WKDEP */ | 1714 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 1715 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT (1 << 0) | 1715 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 |
| 1716 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) | 1716 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1717 | 1717 | ||
| 1718 | /* Used by PM_L4PER_I2C4_WKDEP */ | 1718 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 1719 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT (1 << 7) | 1719 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 |
| 1720 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) | 1720 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1721 | 1721 | ||
| 1722 | /* Used by PM_L4PER_I2C4_WKDEP */ | 1722 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 1723 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT (1 << 1) | 1723 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 |
| 1724 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1724 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) |
| 1725 | 1725 | ||
| 1726 | /* Used by PM_L4PER_I2C4_WKDEP */ | 1726 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 1727 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT (1 << 0) | 1727 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 |
| 1728 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) | 1728 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1729 | 1729 | ||
| 1730 | /* Used by PM_L4PER_I2C5_WKDEP */ | 1730 | /* Used by PM_L4PER_I2C5_WKDEP */ |
| 1731 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT (1 << 7) | 1731 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 |
| 1732 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) | 1732 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1733 | 1733 | ||
| 1734 | /* Used by PM_L4PER_I2C5_WKDEP */ | 1734 | /* Used by PM_L4PER_I2C5_WKDEP */ |
| 1735 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT (1 << 0) | 1735 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 |
| 1736 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) | 1736 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1737 | 1737 | ||
| 1738 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ | 1738 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ |
| 1739 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT (1 << 0) | 1739 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 |
| 1740 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) | 1740 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) |
| 1741 | 1741 | ||
| 1742 | /* Used by PM_ABE_MCASP_WKDEP */ | 1742 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1743 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT (1 << 7) | 1743 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 |
| 1744 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) | 1744 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1745 | 1745 | ||
| 1746 | /* Used by PM_ABE_MCASP_WKDEP */ | 1746 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1747 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT (1 << 6) | 1747 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 |
| 1748 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) | 1748 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) |
| 1749 | 1749 | ||
| 1750 | /* Used by PM_ABE_MCASP_WKDEP */ | 1750 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1751 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT (1 << 0) | 1751 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 |
| 1752 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) | 1752 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1753 | 1753 | ||
| 1754 | /* Used by PM_ABE_MCASP_WKDEP */ | 1754 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1755 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT (1 << 2) | 1755 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 |
| 1756 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) | 1756 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 1757 | 1757 | ||
| 1758 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1758 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1759 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT (1 << 7) | 1759 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 |
| 1760 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) | 1760 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1761 | 1761 | ||
| 1762 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1762 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1763 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT (1 << 6) | 1763 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 |
| 1764 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) | 1764 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) |
| 1765 | 1765 | ||
| 1766 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1766 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1767 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT (1 << 0) | 1767 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 |
| 1768 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) | 1768 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1769 | 1769 | ||
| 1770 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1770 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1771 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT (1 << 2) | 1771 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 |
| 1772 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) | 1772 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 1773 | 1773 | ||
| 1774 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1774 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1775 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT (1 << 7) | 1775 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 |
| 1776 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) | 1776 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1777 | 1777 | ||
| 1778 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1778 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1779 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT (1 << 6) | 1779 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 |
| 1780 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) | 1780 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) |
| 1781 | 1781 | ||
| 1782 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1782 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1783 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT (1 << 0) | 1783 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 |
| 1784 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) | 1784 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1785 | 1785 | ||
| 1786 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1786 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1787 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT (1 << 2) | 1787 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 |
| 1788 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) | 1788 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 1789 | 1789 | ||
| 1790 | /* Used by PM_ABE_MCBSP1_WKDEP */ | 1790 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 1791 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT (1 << 0) | 1791 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 |
| 1792 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) | 1792 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) |
| 1793 | 1793 | ||
| 1794 | /* Used by PM_ABE_MCBSP1_WKDEP */ | 1794 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 1795 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT (1 << 3) | 1795 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 |
| 1796 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) | 1796 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) |
| 1797 | 1797 | ||
| 1798 | /* Used by PM_ABE_MCBSP1_WKDEP */ | 1798 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 1799 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT (1 << 2) | 1799 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 |
| 1800 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) | 1800 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) |
| 1801 | 1801 | ||
| 1802 | /* Used by PM_ABE_MCBSP2_WKDEP */ | 1802 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 1803 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT (1 << 0) | 1803 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 |
| 1804 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) | 1804 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) |
| 1805 | 1805 | ||
| 1806 | /* Used by PM_ABE_MCBSP2_WKDEP */ | 1806 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 1807 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT (1 << 3) | 1807 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 |
| 1808 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) | 1808 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) |
| 1809 | 1809 | ||
| 1810 | /* Used by PM_ABE_MCBSP2_WKDEP */ | 1810 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 1811 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT (1 << 2) | 1811 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 |
| 1812 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) | 1812 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) |
| 1813 | 1813 | ||
| 1814 | /* Used by PM_ABE_MCBSP3_WKDEP */ | 1814 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 1815 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT (1 << 0) | 1815 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 |
| 1816 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) | 1816 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) |
| 1817 | 1817 | ||
| 1818 | /* Used by PM_ABE_MCBSP3_WKDEP */ | 1818 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 1819 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT (1 << 3) | 1819 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 |
| 1820 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) | 1820 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) |
| 1821 | 1821 | ||
| 1822 | /* Used by PM_ABE_MCBSP3_WKDEP */ | 1822 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 1823 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT (1 << 2) | 1823 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 |
| 1824 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) | 1824 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) |
| 1825 | 1825 | ||
| 1826 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | 1826 | /* Used by PM_L4PER_MCBSP4_WKDEP */ |
| 1827 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT (1 << 0) | 1827 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 |
| 1828 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) | 1828 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) |
| 1829 | 1829 | ||
| 1830 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | 1830 | /* Used by PM_L4PER_MCBSP4_WKDEP */ |
| 1831 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT (1 << 3) | 1831 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 |
| 1832 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) | 1832 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) |
| 1833 | 1833 | ||
| 1834 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | 1834 | /* Used by PM_L4PER_MCBSP4_WKDEP */ |
| 1835 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT (1 << 2) | 1835 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 |
| 1836 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) | 1836 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) |
| 1837 | 1837 | ||
| 1838 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1838 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1839 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT (1 << 1) | 1839 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 |
| 1840 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) | 1840 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) |
| 1841 | 1841 | ||
| 1842 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1842 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1843 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT (1 << 0) | 1843 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 |
| 1844 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) | 1844 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) |
| 1845 | 1845 | ||
| 1846 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1846 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1847 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT (1 << 3) | 1847 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 |
| 1848 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) | 1848 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) |
| 1849 | 1849 | ||
| 1850 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1850 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1851 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT (1 << 2) | 1851 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 |
| 1852 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) | 1852 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) |
| 1853 | 1853 | ||
| 1854 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | 1854 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 1855 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT (1 << 1) | 1855 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 |
| 1856 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) | 1856 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) |
| 1857 | 1857 | ||
| 1858 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | 1858 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 1859 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT (1 << 0) | 1859 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 |
| 1860 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) | 1860 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) |
| 1861 | 1861 | ||
| 1862 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | 1862 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 1863 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT (1 << 3) | 1863 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 |
| 1864 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) | 1864 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) |
| 1865 | 1865 | ||
| 1866 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | 1866 | /* Used by PM_L4PER_MCSPI3_WKDEP */ |
| 1867 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT (1 << 0) | 1867 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 |
| 1868 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) | 1868 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) |
| 1869 | 1869 | ||
| 1870 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | 1870 | /* Used by PM_L4PER_MCSPI3_WKDEP */ |
| 1871 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT (1 << 3) | 1871 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 |
| 1872 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) | 1872 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) |
| 1873 | 1873 | ||
| 1874 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | 1874 | /* Used by PM_L4PER_MCSPI4_WKDEP */ |
| 1875 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT (1 << 0) | 1875 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 |
| 1876 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) | 1876 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) |
| 1877 | 1877 | ||
| 1878 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | 1878 | /* Used by PM_L4PER_MCSPI4_WKDEP */ |
| 1879 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT (1 << 3) | 1879 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 |
| 1880 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) | 1880 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) |
| 1881 | 1881 | ||
| 1882 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1882 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1883 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT (1 << 1) | 1883 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 |
| 1884 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) | 1884 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) |
| 1885 | 1885 | ||
| 1886 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1886 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1887 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT (1 << 0) | 1887 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 |
| 1888 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) | 1888 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) |
| 1889 | 1889 | ||
| 1890 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1890 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1891 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT (1 << 3) | 1891 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 |
| 1892 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) | 1892 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) |
| 1893 | 1893 | ||
| 1894 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1894 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1895 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT (1 << 2) | 1895 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 |
| 1896 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) | 1896 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) |
| 1897 | 1897 | ||
| 1898 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 1898 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1899 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT (1 << 1) | 1899 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 |
| 1900 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) | 1900 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) |
| 1901 | 1901 | ||
| 1902 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 1902 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1903 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT (1 << 0) | 1903 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 |
| 1904 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) | 1904 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) |
| 1905 | 1905 | ||
| 1906 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 1906 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1907 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT (1 << 3) | 1907 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 |
| 1908 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) | 1908 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) |
| 1909 | 1909 | ||
| 1910 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 1910 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1911 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT (1 << 2) | 1911 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 |
| 1912 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) | 1912 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) |
| 1913 | 1913 | ||
| 1914 | /* Used by PM_L3INIT_MMC6_WKDEP */ | 1914 | /* Used by PM_L3INIT_MMC6_WKDEP */ |
| 1915 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT (1 << 1) | 1915 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 |
| 1916 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) | 1916 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) |
| 1917 | 1917 | ||
| 1918 | /* Used by PM_L3INIT_MMC6_WKDEP */ | 1918 | /* Used by PM_L3INIT_MMC6_WKDEP */ |
| 1919 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT (1 << 0) | 1919 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 |
| 1920 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) | 1920 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) |
| 1921 | 1921 | ||
| 1922 | /* Used by PM_L3INIT_MMC6_WKDEP */ | 1922 | /* Used by PM_L3INIT_MMC6_WKDEP */ |
| 1923 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT (1 << 2) | 1923 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 |
| 1924 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) | 1924 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) |
| 1925 | 1925 | ||
| 1926 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | 1926 | /* Used by PM_L4PER_MMCSD3_WKDEP */ |
| 1927 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT (1 << 1) | 1927 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 |
| 1928 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) | 1928 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) |
| 1929 | 1929 | ||
| 1930 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | 1930 | /* Used by PM_L4PER_MMCSD3_WKDEP */ |
| 1931 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT (1 << 0) | 1931 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 |
| 1932 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) | 1932 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) |
| 1933 | 1933 | ||
| 1934 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | 1934 | /* Used by PM_L4PER_MMCSD3_WKDEP */ |
| 1935 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT (1 << 3) | 1935 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 |
| 1936 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) | 1936 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) |
| 1937 | 1937 | ||
| 1938 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | 1938 | /* Used by PM_L4PER_MMCSD4_WKDEP */ |
| 1939 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT (1 << 1) | 1939 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 |
| 1940 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) | 1940 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) |
| 1941 | 1941 | ||
| 1942 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | 1942 | /* Used by PM_L4PER_MMCSD4_WKDEP */ |
| 1943 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT (1 << 0) | 1943 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 |
| 1944 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) | 1944 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) |
| 1945 | 1945 | ||
| 1946 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | 1946 | /* Used by PM_L4PER_MMCSD4_WKDEP */ |
| 1947 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT (1 << 3) | 1947 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 |
| 1948 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) | 1948 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) |
| 1949 | 1949 | ||
| 1950 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | 1950 | /* Used by PM_L4PER_MMCSD5_WKDEP */ |
| 1951 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT (1 << 1) | 1951 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 |
| 1952 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) | 1952 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) |
| 1953 | 1953 | ||
| 1954 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | 1954 | /* Used by PM_L4PER_MMCSD5_WKDEP */ |
| 1955 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT (1 << 0) | 1955 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 |
| 1956 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) | 1956 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) |
| 1957 | 1957 | ||
| 1958 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | 1958 | /* Used by PM_L4PER_MMCSD5_WKDEP */ |
| 1959 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT (1 << 3) | 1959 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 |
| 1960 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) | 1960 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) |
| 1961 | 1961 | ||
| 1962 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | 1962 | /* Used by PM_L3INIT_PCIESS_WKDEP */ |
| 1963 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT (1 << 0) | 1963 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 |
| 1964 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) | 1964 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) |
| 1965 | 1965 | ||
| 1966 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | 1966 | /* Used by PM_L3INIT_PCIESS_WKDEP */ |
| 1967 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT (1 << 2) | 1967 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 |
| 1968 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) | 1968 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) |
| 1969 | 1969 | ||
| 1970 | /* Used by PM_ABE_PDM_WKDEP */ | 1970 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1971 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT (1 << 7) | 1971 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 |
| 1972 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) | 1972 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) |
| 1973 | 1973 | ||
| 1974 | /* Used by PM_ABE_PDM_WKDEP */ | 1974 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1975 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT (1 << 6) | 1975 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 |
| 1976 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) | 1976 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) |
| 1977 | 1977 | ||
| 1978 | /* Used by PM_ABE_PDM_WKDEP */ | 1978 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1979 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT (1 << 0) | 1979 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 |
| 1980 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) | 1980 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) |
| 1981 | 1981 | ||
| 1982 | /* Used by PM_ABE_PDM_WKDEP */ | 1982 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1983 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT (1 << 2) | 1983 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 |
| 1984 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) | 1984 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 1985 | 1985 | ||
| 1986 | /* Used by PM_WKUP_RTC_WKDEP */ | 1986 | /* Used by PM_WKUP_RTC_WKDEP */ |
| 1987 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT (1 << 0) | 1987 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 |
| 1988 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) | 1988 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) |
| 1989 | 1989 | ||
| 1990 | /* Used by PM_L3INIT_SATA_WKDEP */ | 1990 | /* Used by PM_L3INIT_SATA_WKDEP */ |
| 1991 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT (1 << 0) | 1991 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 |
| 1992 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) | 1992 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) |
| 1993 | 1993 | ||
| 1994 | /* Used by PM_L3INIT_SATA_WKDEP */ | 1994 | /* Used by PM_L3INIT_SATA_WKDEP */ |
| 1995 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT (1 << 2) | 1995 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 |
| 1996 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) | 1996 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) |
| 1997 | 1997 | ||
| 1998 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 1998 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 1999 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT (1 << 7) | 1999 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 |
| 2000 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) | 2000 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) |
| 2001 | 2001 | ||
| 2002 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2002 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 2003 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT (1 << 6) | 2003 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 |
| 2004 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) | 2004 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) |
| 2005 | 2005 | ||
| 2006 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2006 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 2007 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT (1 << 0) | 2007 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 |
| 2008 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) | 2008 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) |
| 2009 | 2009 | ||
| 2010 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2010 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 2011 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT (1 << 2) | 2011 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 |
| 2012 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) | 2012 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 2013 | 2013 | ||
| 2014 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2014 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2015 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT (1 << 7) | 2015 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 |
| 2016 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) | 2016 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) |
| 2017 | 2017 | ||
| 2018 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2018 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2019 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT (1 << 6) | 2019 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 |
| 2020 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) | 2020 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) |
| 2021 | 2021 | ||
| 2022 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2022 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2023 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT (1 << 0) | 2023 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 |
| 2024 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) | 2024 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) |
| 2025 | 2025 | ||
| 2026 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2026 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2027 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT (1 << 2) | 2027 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 |
| 2028 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) | 2028 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) |
| 2029 | 2029 | ||
| 2030 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | 2030 | /* Used by PM_ALWON_SR_CORE_WKDEP */ |
| 2031 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT (1 << 1) | 2031 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 |
| 2032 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) | 2032 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) |
| 2033 | 2033 | ||
| 2034 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | 2034 | /* Used by PM_ALWON_SR_CORE_WKDEP */ |
| 2035 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT (1 << 0) | 2035 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 |
| 2036 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) | 2036 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) |
| 2037 | 2037 | ||
| 2038 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | 2038 | /* Used by PM_ALWON_SR_IVA_WKDEP */ |
| 2039 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT (1 << 1) | 2039 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 |
| 2040 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) | 2040 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) |
| 2041 | 2041 | ||
| 2042 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | 2042 | /* Used by PM_ALWON_SR_IVA_WKDEP */ |
| 2043 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT (1 << 0) | 2043 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 |
| 2044 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) | 2044 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) |
| 2045 | 2045 | ||
| 2046 | /* Used by PM_ALWON_SR_MPU_WKDEP */ | 2046 | /* Used by PM_ALWON_SR_MPU_WKDEP */ |
| 2047 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT (1 << 0) | 2047 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 |
| 2048 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) | 2048 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) |
| 2049 | 2049 | ||
| 2050 | /* Used by PM_WKUP_TIMER12_WKDEP */ | 2050 | /* Used by PM_WKUP_TIMER12_WKDEP */ |
| 2051 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT (1 << 0) | 2051 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 |
| 2052 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) | 2052 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) |
| 2053 | 2053 | ||
| 2054 | /* Used by PM_WKUP_TIMER1_WKDEP */ | 2054 | /* Used by PM_WKUP_TIMER1_WKDEP */ |
| 2055 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT (1 << 0) | 2055 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 |
| 2056 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) | 2056 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) |
| 2057 | 2057 | ||
| 2058 | /* Used by PM_ABE_TIMER5_WKDEP */ | 2058 | /* Used by PM_ABE_TIMER5_WKDEP */ |
| 2059 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT (1 << 0) | 2059 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 |
| 2060 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) | 2060 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) |
| 2061 | 2061 | ||
| 2062 | /* Used by PM_ABE_TIMER5_WKDEP */ | 2062 | /* Used by PM_ABE_TIMER5_WKDEP */ |
| 2063 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT (1 << 2) | 2063 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 |
| 2064 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) | 2064 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) |
| 2065 | 2065 | ||
| 2066 | /* Used by PM_ABE_TIMER6_WKDEP */ | 2066 | /* Used by PM_ABE_TIMER6_WKDEP */ |
| 2067 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT (1 << 0) | 2067 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 |
| 2068 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) | 2068 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) |
| 2069 | 2069 | ||
| 2070 | /* Used by PM_ABE_TIMER6_WKDEP */ | 2070 | /* Used by PM_ABE_TIMER6_WKDEP */ |
| 2071 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT (1 << 2) | 2071 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 |
| 2072 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) | 2072 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) |
| 2073 | 2073 | ||
| 2074 | /* Used by PM_ABE_TIMER7_WKDEP */ | 2074 | /* Used by PM_ABE_TIMER7_WKDEP */ |
| 2075 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT (1 << 0) | 2075 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 |
| 2076 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) | 2076 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) |
| 2077 | 2077 | ||
| 2078 | /* Used by PM_ABE_TIMER7_WKDEP */ | 2078 | /* Used by PM_ABE_TIMER7_WKDEP */ |
| 2079 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT (1 << 2) | 2079 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 |
| 2080 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) | 2080 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) |
| 2081 | 2081 | ||
| 2082 | /* Used by PM_ABE_TIMER8_WKDEP */ | 2082 | /* Used by PM_ABE_TIMER8_WKDEP */ |
| 2083 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT (1 << 0) | 2083 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 |
| 2084 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) | 2084 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) |
| 2085 | 2085 | ||
| 2086 | /* Used by PM_ABE_TIMER8_WKDEP */ | 2086 | /* Used by PM_ABE_TIMER8_WKDEP */ |
| 2087 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT (1 << 2) | 2087 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 |
| 2088 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) | 2088 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) |
| 2089 | 2089 | ||
| 2090 | /* Used by PM_L4PER_UART1_WKDEP */ | 2090 | /* Used by PM_L4PER_UART1_WKDEP */ |
| 2091 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT (1 << 0) | 2091 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 |
| 2092 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) | 2092 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) |
| 2093 | 2093 | ||
| 2094 | /* Used by PM_L4PER_UART1_WKDEP */ | 2094 | /* Used by PM_L4PER_UART1_WKDEP */ |
| 2095 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT (1 << 3) | 2095 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 |
| 2096 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) | 2096 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) |
| 2097 | 2097 | ||
| 2098 | /* Used by PM_L4PER_UART2_WKDEP */ | 2098 | /* Used by PM_L4PER_UART2_WKDEP */ |
| 2099 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT (1 << 0) | 2099 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 |
| 2100 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) | 2100 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) |
| 2101 | 2101 | ||
| 2102 | /* Used by PM_L4PER_UART2_WKDEP */ | 2102 | /* Used by PM_L4PER_UART2_WKDEP */ |
| 2103 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT (1 << 3) | 2103 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 |
| 2104 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) | 2104 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) |
| 2105 | 2105 | ||
| 2106 | /* Used by PM_L4PER_UART3_WKDEP */ | 2106 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2107 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT (1 << 1) | 2107 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 |
| 2108 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) | 2108 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) |
| 2109 | 2109 | ||
| 2110 | /* Used by PM_L4PER_UART3_WKDEP */ | 2110 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2111 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT (1 << 0) | 2111 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 |
| 2112 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) | 2112 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) |
| 2113 | 2113 | ||
| 2114 | /* Used by PM_L4PER_UART3_WKDEP */ | 2114 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2115 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT (1 << 3) | 2115 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 |
| 2116 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) | 2116 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) |
| 2117 | 2117 | ||
| 2118 | /* Used by PM_L4PER_UART3_WKDEP */ | 2118 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2119 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT (1 << 2) | 2119 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 |
| 2120 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) | 2120 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) |
| 2121 | 2121 | ||
| 2122 | /* Used by PM_L4PER_UART4_WKDEP */ | 2122 | /* Used by PM_L4PER_UART4_WKDEP */ |
| 2123 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT (1 << 0) | 2123 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 |
| 2124 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) | 2124 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) |
| 2125 | 2125 | ||
| 2126 | /* Used by PM_L4PER_UART4_WKDEP */ | 2126 | /* Used by PM_L4PER_UART4_WKDEP */ |
| 2127 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT (1 << 3) | 2127 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 |
| 2128 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) | 2128 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) |
| 2129 | 2129 | ||
| 2130 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | 2130 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ |
| 2131 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT (1 << 1) | 2131 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 |
| 2132 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) | 2132 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) |
| 2133 | 2133 | ||
| 2134 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | 2134 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ |
| 2135 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT (1 << 0) | 2135 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 |
| 2136 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) | 2136 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) |
| 2137 | 2137 | ||
| 2138 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | 2138 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ |
| 2139 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT (1 << 1) | 2139 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 |
| 2140 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) | 2140 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) |
| 2141 | 2141 | ||
| 2142 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | 2142 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ |
| 2143 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT (1 << 1) | 2143 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 |
| 2144 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) | 2144 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) |
| 2145 | 2145 | ||
| 2146 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | 2146 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ |
| 2147 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT (1 << 0) | 2147 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 |
| 2148 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) | 2148 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) |
| 2149 | 2149 | ||
| 2150 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | 2150 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ |
| 2151 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT (1 << 0) | 2151 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 |
| 2152 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) | 2152 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) |
| 2153 | 2153 | ||
| 2154 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | 2154 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ |
| 2155 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT (1 << 1) | 2155 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 |
| 2156 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) | 2156 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) |
| 2157 | 2157 | ||
| 2158 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | 2158 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ |
| 2159 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT (1 << 0) | 2159 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 |
| 2160 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) | 2160 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) |
| 2161 | 2161 | ||
| 2162 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | 2162 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ |
| 2163 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT (1 << 1) | 2163 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 |
| 2164 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) | 2164 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) |
| 2165 | 2165 | ||
| 2166 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | 2166 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ |
| 2167 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT (1 << 0) | 2167 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 |
| 2168 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) | 2168 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) |
| 2169 | 2169 | ||
| 2170 | /* Used by PM_WKUP_USIM_WKDEP */ | 2170 | /* Used by PM_WKUP_USIM_WKDEP */ |
| 2171 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT (1 << 0) | 2171 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 |
| 2172 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) | 2172 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) |
| 2173 | 2173 | ||
| 2174 | /* Used by PM_WKUP_USIM_WKDEP */ | 2174 | /* Used by PM_WKUP_USIM_WKDEP */ |
| 2175 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT (1 << 3) | 2175 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 |
| 2176 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) | 2176 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) |
| 2177 | 2177 | ||
| 2178 | /* Used by PM_WKUP_WDT2_WKDEP */ | 2178 | /* Used by PM_WKUP_WDT2_WKDEP */ |
| 2179 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT (1 << 1) | 2179 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 |
| 2180 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) | 2180 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) |
| 2181 | 2181 | ||
| 2182 | /* Used by PM_WKUP_WDT2_WKDEP */ | 2182 | /* Used by PM_WKUP_WDT2_WKDEP */ |
| 2183 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT (1 << 0) | 2183 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 |
| 2184 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) | 2184 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) |
| 2185 | 2185 | ||
| 2186 | /* Used by PM_ABE_WDT3_WKDEP */ | 2186 | /* Used by PM_ABE_WDT3_WKDEP */ |
| 2187 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT (1 << 0) | 2187 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 |
| 2188 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) | 2188 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) |
| 2189 | 2189 | ||
| 2190 | /* Used by PM_L3INIT_HSI_WKDEP */ | 2190 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 2191 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT (1 << 8) | 2191 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 |
| 2192 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) | 2192 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) |
| 2193 | 2193 | ||
| 2194 | /* Used by PM_L3INIT_XHPI_WKDEP */ | 2194 | /* Used by PM_L3INIT_XHPI_WKDEP */ |
| 2195 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT (1 << 1) | 2195 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 |
| 2196 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) | 2196 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) |
| 2197 | 2197 | ||
| 2198 | /* Used by PRM_IO_PMCTRL */ | 2198 | /* Used by PRM_IO_PMCTRL */ |
| 2199 | #define OMAP4430_WUCLK_CTRL_SHIFT (1 << 8) | 2199 | #define OMAP4430_WUCLK_CTRL_SHIFT 8 |
| 2200 | #define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) | 2200 | #define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) |
| 2201 | 2201 | ||
| 2202 | /* Used by PRM_IO_PMCTRL */ | 2202 | /* Used by PRM_IO_PMCTRL */ |
| 2203 | #define OMAP4430_WUCLK_STATUS_SHIFT (1 << 9) | 2203 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
| 2204 | #define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) | 2204 | #define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) |
| 2205 | #endif | 2205 | #endif |
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 40f006285163..5fba2aa8932c 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h | |||
| @@ -179,9 +179,11 @@ | |||
| 179 | 179 | ||
| 180 | /* Registers appearing on both 24xx and 34xx */ | 180 | /* Registers appearing on both 24xx and 34xx */ |
| 181 | 181 | ||
| 182 | #define RM_RSTCTRL 0x0050 | 182 | #define OMAP2_RM_RSTCTRL 0x0050 |
| 183 | #define RM_RSTTIME 0x0054 | 183 | #define OMAP2_RM_RSTTIME 0x0054 |
| 184 | #define RM_RSTST 0x0058 | 184 | #define OMAP2_RM_RSTST 0x0058 |
| 185 | #define OMAP2_PM_PWSTCTRL 0x00e0 | ||
| 186 | #define OMAP2_PM_PWSTST 0x00e4 | ||
| 185 | 187 | ||
| 186 | #define PM_WKEN 0x00a0 | 188 | #define PM_WKEN 0x00a0 |
| 187 | #define PM_WKEN1 PM_WKEN | 189 | #define PM_WKEN1 PM_WKEN |
| @@ -191,8 +193,6 @@ | |||
| 191 | #define PM_EVGENCTRL 0x00d4 | 193 | #define PM_EVGENCTRL 0x00d4 |
| 192 | #define PM_EVGENONTIM 0x00d8 | 194 | #define PM_EVGENONTIM 0x00d8 |
| 193 | #define PM_EVGENOFFTIM 0x00dc | 195 | #define PM_EVGENOFFTIM 0x00dc |
| 194 | #define PM_PWSTCTRL 0x00e0 | ||
| 195 | #define PM_PWSTST 0x00e4 | ||
| 196 | 196 | ||
| 197 | /* Omap2 specific registers */ | 197 | /* Omap2 specific registers */ |
| 198 | #define OMAP24XX_PM_WKEN2 0x00a4 | 198 | #define OMAP24XX_PM_WKEN2 0x00a4 |
| @@ -220,6 +220,13 @@ | |||
| 220 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 | 220 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 |
| 221 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | 221 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc |
| 222 | 222 | ||
| 223 | /* Omap4 specific registers */ | ||
| 224 | #define OMAP4_RM_RSTCTRL 0x0000 | ||
| 225 | #define OMAP4_RM_RSTTIME 0x0004 | ||
| 226 | #define OMAP4_RM_RSTST 0x0008 | ||
| 227 | #define OMAP4_PM_PWSTCTRL 0x0000 | ||
| 228 | #define OMAP4_PM_PWSTST 0x0004 | ||
| 229 | |||
| 223 | 230 | ||
| 224 | #ifndef __ASSEMBLER__ | 231 | #ifndef __ASSEMBLER__ |
| 225 | 232 | ||
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h new file mode 100644 index 000000000000..cd4352917022 --- /dev/null +++ b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * SDRC register values for the Numonyx M65KXXXXAM | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Integration Software and Electronic Engineering. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM | ||
| 12 | #define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM | ||
| 13 | |||
| 14 | #include <plat/sdrc.h> | ||
| 15 | |||
| 16 | /* Numonyx M65KXXXXAM */ | ||
| 17 | static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = { | ||
| 18 | [0] = { | ||
| 19 | .rate = 200000000, | ||
| 20 | .actim_ctrla = 0xe321d4c6, | ||
| 21 | .actim_ctrlb = 0x00022328, | ||
| 22 | .rfr_ctrl = 0x0005e601, | ||
| 23 | .mr = 0x00000032, | ||
| 24 | }, | ||
| 25 | [1] = { | ||
| 26 | .rate = 166000000, | ||
| 27 | .actim_ctrla = 0xba9dc485, | ||
| 28 | .actim_ctrlb = 0x00022321, | ||
| 29 | .rfr_ctrl = 0x0004dc01, | ||
| 30 | .mr = 0x00000032, | ||
| 31 | }, | ||
| 32 | [2] = { | ||
| 33 | .rate = 133000000, | ||
| 34 | .actim_ctrla = 0x9a19b485, | ||
| 35 | .actim_ctrlb = 0x0002231b, | ||
| 36 | .rfr_ctrl = 0x0003de01, | ||
| 37 | .mr = 0x00000032, | ||
| 38 | }, | ||
| 39 | [3] = { | ||
| 40 | .rate = 83000000, | ||
| 41 | .actim_ctrla = 0x594ca242, | ||
| 42 | .actim_ctrlb = 0x00022310, | ||
| 43 | .rfr_ctrl = 0x00025501, | ||
| 44 | .mr = 0x00000032, | ||
| 45 | }, | ||
| 46 | [4] = { | ||
| 47 | .rate = 0 | ||
| 48 | }, | ||
| 49 | }; | ||
| 50 | |||
| 51 | #endif | ||
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index cbfbd142e946..4c65f5628b39 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c | |||
| @@ -119,8 +119,15 @@ int omap2_sdrc_get_params(unsigned long r, | |||
| 119 | 119 | ||
| 120 | void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) | 120 | void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) |
| 121 | { | 121 | { |
| 122 | omap2_sdrc_base = omap2_globals->sdrc; | 122 | /* Static mapping, never released */ |
| 123 | omap2_sms_base = omap2_globals->sms; | 123 | if (omap2_globals->sdrc) { |
| 124 | omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K); | ||
| 125 | WARN_ON(!omap2_sdrc_base); | ||
| 126 | } | ||
| 127 | if (omap2_globals->sms) { | ||
| 128 | omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K); | ||
| 129 | WARN_ON(!omap2_sms_base); | ||
| 130 | } | ||
| 124 | } | 131 | } |
| 125 | 132 | ||
| 126 | /** | 133 | /** |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index e10a02df6e1d..b79bc8926cc9 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/serial_reg.h> | 23 | #include <linux/serial_reg.h> |
| 24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | #include <linux/delay.h> | ||
| 26 | 27 | ||
| 27 | #include <plat/common.h> | 28 | #include <plat/common.h> |
| 28 | #include <plat/board.h> | 29 | #include <plat/board.h> |
| @@ -80,7 +81,6 @@ static LIST_HEAD(uart_list); | |||
| 80 | 81 | ||
| 81 | static struct plat_serial8250_port serial_platform_data0[] = { | 82 | static struct plat_serial8250_port serial_platform_data0[] = { |
| 82 | { | 83 | { |
| 83 | .mapbase = OMAP_UART1_BASE, | ||
| 84 | .irq = 72, | 84 | .irq = 72, |
| 85 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
| 86 | .iotype = UPIO_MEM, | 86 | .iotype = UPIO_MEM, |
| @@ -93,7 +93,6 @@ static struct plat_serial8250_port serial_platform_data0[] = { | |||
| 93 | 93 | ||
| 94 | static struct plat_serial8250_port serial_platform_data1[] = { | 94 | static struct plat_serial8250_port serial_platform_data1[] = { |
| 95 | { | 95 | { |
| 96 | .mapbase = OMAP_UART2_BASE, | ||
| 97 | .irq = 73, | 96 | .irq = 73, |
| 98 | .flags = UPF_BOOT_AUTOCONF, | 97 | .flags = UPF_BOOT_AUTOCONF, |
| 99 | .iotype = UPIO_MEM, | 98 | .iotype = UPIO_MEM, |
| @@ -106,7 +105,6 @@ static struct plat_serial8250_port serial_platform_data1[] = { | |||
| 106 | 105 | ||
| 107 | static struct plat_serial8250_port serial_platform_data2[] = { | 106 | static struct plat_serial8250_port serial_platform_data2[] = { |
| 108 | { | 107 | { |
| 109 | .mapbase = OMAP_UART3_BASE, | ||
| 110 | .irq = 74, | 108 | .irq = 74, |
| 111 | .flags = UPF_BOOT_AUTOCONF, | 109 | .flags = UPF_BOOT_AUTOCONF, |
| 112 | .iotype = UPIO_MEM, | 110 | .iotype = UPIO_MEM, |
| @@ -117,10 +115,9 @@ static struct plat_serial8250_port serial_platform_data2[] = { | |||
| 117 | } | 115 | } |
| 118 | }; | 116 | }; |
| 119 | 117 | ||
| 120 | #ifdef CONFIG_ARCH_OMAP4 | 118 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
| 121 | static struct plat_serial8250_port serial_platform_data3[] = { | 119 | static struct plat_serial8250_port serial_platform_data3[] = { |
| 122 | { | 120 | { |
| 123 | .mapbase = OMAP_UART4_BASE, | ||
| 124 | .irq = 70, | 121 | .irq = 70, |
| 125 | .flags = UPF_BOOT_AUTOCONF, | 122 | .flags = UPF_BOOT_AUTOCONF, |
| 126 | .iotype = UPIO_MEM, | 123 | .iotype = UPIO_MEM, |
| @@ -130,7 +127,26 @@ static struct plat_serial8250_port serial_platform_data3[] = { | |||
| 130 | .flags = 0 | 127 | .flags = 0 |
| 131 | } | 128 | } |
| 132 | }; | 129 | }; |
| 130 | |||
| 131 | static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) | ||
| 132 | { | ||
| 133 | serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; | ||
| 134 | } | ||
| 135 | #else | ||
| 136 | static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) | ||
| 137 | { | ||
| 138 | } | ||
| 133 | #endif | 139 | #endif |
| 140 | |||
| 141 | void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) | ||
| 142 | { | ||
| 143 | serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; | ||
| 144 | serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; | ||
| 145 | serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; | ||
| 146 | if (cpu_is_omap3630() || cpu_is_omap44xx()) | ||
| 147 | omap2_set_globals_uart4(omap2_globals); | ||
| 148 | } | ||
| 149 | |||
| 134 | static inline unsigned int __serial_read_reg(struct uart_port *up, | 150 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
| 135 | int offset) | 151 | int offset) |
| 136 | { | 152 | { |
| @@ -145,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, | |||
| 145 | return (unsigned int)__raw_readb(up->membase + offset); | 161 | return (unsigned int)__raw_readb(up->membase + offset); |
| 146 | } | 162 | } |
| 147 | 163 | ||
| 164 | static inline void __serial_write_reg(struct uart_port *up, int offset, | ||
| 165 | int value) | ||
| 166 | { | ||
| 167 | offset <<= up->regshift; | ||
| 168 | __raw_writeb(value, up->membase + offset); | ||
| 169 | } | ||
| 170 | |||
| 148 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, | 171 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, |
| 149 | int value) | 172 | int value) |
| 150 | { | 173 | { |
| @@ -574,7 +597,7 @@ static struct omap_uart_state omap_uart[] = { | |||
| 574 | }, | 597 | }, |
| 575 | }, | 598 | }, |
| 576 | }, | 599 | }, |
| 577 | #ifdef CONFIG_ARCH_OMAP4 | 600 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
| 578 | { | 601 | { |
| 579 | .pdev = { | 602 | .pdev = { |
| 580 | .name = "serial8250", | 603 | .name = "serial8250", |
| @@ -605,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset) | |||
| 605 | return __serial_read_reg(up, offset); | 628 | return __serial_read_reg(up, offset); |
| 606 | } | 629 | } |
| 607 | 630 | ||
| 631 | static void serial_out_override(struct uart_port *up, int offset, int value) | ||
| 632 | { | ||
| 633 | unsigned int status, tmout = 10000; | ||
| 634 | |||
| 635 | status = __serial_read_reg(up, UART_LSR); | ||
| 636 | while (!(status & UART_LSR_THRE)) { | ||
| 637 | /* Wait up to 10ms for the character(s) to be sent. */ | ||
| 638 | if (--tmout == 0) | ||
| 639 | break; | ||
| 640 | udelay(1); | ||
| 641 | status = __serial_read_reg(up, UART_LSR); | ||
| 642 | } | ||
| 643 | __serial_write_reg(up, offset, value); | ||
| 644 | } | ||
| 608 | void __init omap_serial_early_init(void) | 645 | void __init omap_serial_early_init(void) |
| 609 | { | 646 | { |
| 610 | int i; | 647 | int i; |
| @@ -701,15 +738,19 @@ void __init omap_serial_init_port(int port) | |||
| 701 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); | 738 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); |
| 702 | } | 739 | } |
| 703 | 740 | ||
| 704 | /* omap44xx: Never read empty UART fifo | 741 | /* |
| 705 | * omap3xxx: Never read empty UART fifo on UARTs | 742 | * omap44xx: Never read empty UART fifo |
| 706 | * with IP rev >=0x52 | 743 | * omap3xxx: Never read empty UART fifo on UARTs |
| 707 | */ | 744 | * with IP rev >=0x52 |
| 708 | if (cpu_is_omap44xx()) | 745 | */ |
| 709 | uart->p->serial_in = serial_in_override; | 746 | if (cpu_is_omap44xx()) { |
| 710 | else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) | 747 | uart->p->serial_in = serial_in_override; |
| 711 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) | 748 | uart->p->serial_out = serial_out_override; |
| 712 | uart->p->serial_in = serial_in_override; | 749 | } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) |
| 750 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { | ||
| 751 | uart->p->serial_in = serial_in_override; | ||
| 752 | uart->p->serial_out = serial_out_override; | ||
| 753 | } | ||
| 713 | } | 754 | } |
| 714 | 755 | ||
| 715 | /** | 756 | /** |
| @@ -721,8 +762,13 @@ void __init omap_serial_init_port(int port) | |||
| 721 | */ | 762 | */ |
| 722 | void __init omap_serial_init(void) | 763 | void __init omap_serial_init(void) |
| 723 | { | 764 | { |
| 724 | int i; | 765 | int i, nr_ports; |
| 766 | |||
| 767 | if (!(cpu_is_omap3630() || cpu_is_omap4430())) | ||
| 768 | nr_ports = 3; | ||
| 769 | else | ||
| 770 | nr_ports = ARRAY_SIZE(omap_uart); | ||
| 725 | 771 | ||
| 726 | for (i = 0; i < ARRAY_SIZE(omap_uart); i++) | 772 | for (i = 0; i < nr_ports; i++) |
| 727 | omap_serial_init_port(i); | 773 | omap_serial_init_port(i); |
| 728 | } | 774 | } |
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index c3626ea48143..d522cd70bf53 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S | |||
| @@ -33,12 +33,14 @@ | |||
| 33 | #include "prm.h" | 33 | #include "prm.h" |
| 34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
| 35 | 35 | ||
| 36 | #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c | ||
| 37 | |||
| 36 | #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ | 38 | #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ |
| 37 | OMAP3430_PM_PREPWSTST) | 39 | OMAP3430_PM_PREPWSTST) |
| 38 | #define PM_PREPWSTST_CORE_P 0x48306AE8 | 40 | #define PM_PREPWSTST_CORE_P 0x48306AE8 |
| 39 | #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ | 41 | #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ |
| 40 | OMAP3430_PM_PREPWSTST) | 42 | OMAP3430_PM_PREPWSTST) |
| 41 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL | 43 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL |
| 42 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) | 44 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) |
| 43 | #define SRAM_BASE_P 0x40200000 | 45 | #define SRAM_BASE_P 0x40200000 |
| 44 | #define CONTROL_STAT 0x480022F0 | 46 | #define CONTROL_STAT 0x480022F0 |
| @@ -57,6 +59,37 @@ | |||
| 57 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) | 59 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
| 58 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) | 60 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 59 | 61 | ||
| 62 | .text | ||
| 63 | /* Function to aquire the semaphore in scratchpad */ | ||
| 64 | ENTRY(lock_scratchpad_sem) | ||
| 65 | stmfd sp!, {lr} @ save registers on stack | ||
| 66 | wait_sem: | ||
| 67 | mov r0,#1 | ||
| 68 | ldr r1, sdrc_scratchpad_sem | ||
| 69 | wait_loop: | ||
| 70 | ldr r2, [r1] @ load the lock value | ||
| 71 | cmp r2, r0 @ is the lock free ? | ||
| 72 | beq wait_loop @ not free... | ||
| 73 | swp r2, r0, [r1] @ semaphore free so lock it and proceed | ||
| 74 | cmp r2, r0 @ did we succeed ? | ||
| 75 | beq wait_sem @ no - try again | ||
| 76 | ldmfd sp!, {pc} @ restore regs and return | ||
| 77 | sdrc_scratchpad_sem: | ||
| 78 | .word SDRC_SCRATCHPAD_SEM_V | ||
| 79 | ENTRY(lock_scratchpad_sem_sz) | ||
| 80 | .word . - lock_scratchpad_sem | ||
| 81 | |||
| 82 | .text | ||
| 83 | /* Function to release the scratchpad semaphore */ | ||
| 84 | ENTRY(unlock_scratchpad_sem) | ||
| 85 | stmfd sp!, {lr} @ save registers on stack | ||
| 86 | ldr r3, sdrc_scratchpad_sem | ||
| 87 | mov r2,#0 | ||
| 88 | str r2,[r3] | ||
| 89 | ldmfd sp!, {pc} @ restore regs and return | ||
| 90 | ENTRY(unlock_scratchpad_sem_sz) | ||
| 91 | .word . - unlock_scratchpad_sem | ||
| 92 | |||
| 60 | .text | 93 | .text |
| 61 | /* Function call to get the restore pointer for resume from OFF */ | 94 | /* Function call to get the restore pointer for resume from OFF */ |
| 62 | ENTRY(get_restore_pointer) | 95 | ENTRY(get_restore_pointer) |
| @@ -251,6 +284,21 @@ restore: | |||
| 251 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | 284 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier |
| 252 | .word 0xE1600071 @ call SMI monitor (smi #1) | 285 | .word 0xE1600071 @ call SMI monitor (smi #1) |
| 253 | 286 | ||
| 287 | #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE | ||
| 288 | /* Restore L2 aux control register */ | ||
| 289 | @ set service ID for PPA | ||
| 290 | mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID | ||
| 291 | mov r12, r0 @ copy service ID in r12 | ||
| 292 | mov r1, #0 @ set task ID for ROM code in r1 | ||
| 293 | mov r2, #4 @ set some flags in r2, r6 | ||
| 294 | mov r6, #0xff | ||
| 295 | ldr r4, scratchpad_base | ||
| 296 | ldr r3, [r4, #0xBC] | ||
| 297 | adds r3, r3, #8 @ r3 points to parameters | ||
| 298 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | ||
| 299 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | ||
| 300 | .word 0xE1600071 @ call SMI monitor (smi #1) | ||
| 301 | #endif | ||
| 254 | b logic_l1_restore | 302 | b logic_l1_restore |
| 255 | l2_inv_api_params: | 303 | l2_inv_api_params: |
| 256 | .word 0x1, 0x00 | 304 | .word 0x1, 0x00 |
| @@ -264,6 +312,11 @@ smi: .word 0xE1600070 @ Call SMI monitor (smieq) | |||
| 264 | ldr r0, [r3,#4] | 312 | ldr r0, [r3,#4] |
| 265 | mov r12, #0x3 | 313 | mov r12, #0x3 |
| 266 | .word 0xE1600070 @ Call SMI monitor (smieq) | 314 | .word 0xE1600070 @ Call SMI monitor (smieq) |
| 315 | ldr r4, scratchpad_base | ||
| 316 | ldr r3, [r4,#0xBC] | ||
| 317 | ldr r0, [r3,#12] | ||
| 318 | mov r12, #0x2 | ||
| 319 | .word 0xE1600070 @ Call SMI monitor (smieq) | ||
| 267 | logic_l1_restore: | 320 | logic_l1_restore: |
| 268 | mov r1, #0 | 321 | mov r1, #0 |
| 269 | /* Invalidate all instruction caches to PoU | 322 | /* Invalidate all instruction caches to PoU |
| @@ -272,7 +325,7 @@ logic_l1_restore: | |||
| 272 | 325 | ||
| 273 | ldr r4, scratchpad_base | 326 | ldr r4, scratchpad_base |
| 274 | ldr r3, [r4,#0xBC] | 327 | ldr r3, [r4,#0xBC] |
| 275 | adds r3, r3, #8 | 328 | adds r3, r3, #16 |
| 276 | ldmia r3!, {r4-r6} | 329 | ldmia r3!, {r4-r6} |
| 277 | mov sp, r4 | 330 | mov sp, r4 |
| 278 | msr spsr_cxsf, r5 | 331 | msr spsr_cxsf, r5 |
| @@ -391,7 +444,9 @@ save_context_wfi: | |||
| 391 | mov r8, r0 /* Store SDRAM address in r8 */ | 444 | mov r8, r0 /* Store SDRAM address in r8 */ |
| 392 | mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register | 445 | mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register |
| 393 | mov r4, #0x1 @ Number of parameters for restore call | 446 | mov r4, #0x1 @ Number of parameters for restore call |
| 394 | stmia r8!, {r4-r5} | 447 | stmia r8!, {r4-r5} @ Push parameters for restore call |
| 448 | mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register | ||
| 449 | stmia r8!, {r4-r5} @ Push parameters for restore call | ||
| 395 | /* Check what that target sleep state is:stored in r1*/ | 450 | /* Check what that target sleep state is:stored in r1*/ |
| 396 | /* 1 - Only L1 and logic lost */ | 451 | /* 1 - Only L1 and logic lost */ |
| 397 | /* 2 - Only L2 lost */ | 452 | /* 2 - Only L2 lost */ |
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index cd04deaa88c5..74fbed8491f2 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c | |||
| @@ -85,8 +85,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |||
| 85 | case CLOCK_EVT_MODE_PERIODIC: | 85 | case CLOCK_EVT_MODE_PERIODIC: |
| 86 | period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; | 86 | period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; |
| 87 | period -= 1; | 87 | period -= 1; |
| 88 | if (cpu_is_omap44xx()) | ||
| 89 | period = 0xff; /* FIXME: */ | ||
| 90 | omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); | 88 | omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); |
| 91 | break; | 89 | break; |
| 92 | case CLOCK_EVT_MODE_ONESHOT: | 90 | case CLOCK_EVT_MODE_ONESHOT: |
| @@ -150,9 +148,6 @@ static void __init omap2_gp_clockevent_init(void) | |||
| 150 | "timer-gp: omap_dm_timer_set_source() failed\n"); | 148 | "timer-gp: omap_dm_timer_set_source() failed\n"); |
| 151 | 149 | ||
| 152 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); | 150 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); |
| 153 | if (cpu_is_omap44xx()) | ||
| 154 | /* Assuming 32kHz clk is driving GPT1 */ | ||
| 155 | tick_rate = 32768; /* FIXME: */ | ||
| 156 | 151 | ||
| 157 | pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", | 152 | pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", |
| 158 | gptimer_id, tick_rate); | 153 | gptimer_id, tick_rate); |
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c index c1a650a9910f..954682e64399 100644 --- a/arch/arm/mach-omap2/timer-mpu.c +++ b/arch/arm/mach-omap2/timer-mpu.c | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | */ | 28 | */ |
| 29 | void __cpuinit local_timer_setup(struct clock_event_device *evt) | 29 | void __cpuinit local_timer_setup(struct clock_event_device *evt) |
| 30 | { | 30 | { |
| 31 | evt->irq = INT_44XX_LOCALTIMER_IRQ; | 31 | evt->irq = OMAP44XX_IRQ_LOCALTIMER; |
| 32 | twd_timer_setup(evt); | 32 | twd_timer_setup(evt); |
| 33 | } | 33 | } |
| 34 | 34 | ||
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index a80441dd19b8..6d41fa7b2ce8 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -47,70 +47,11 @@ static struct resource musb_resources[] = { | |||
| 47 | }, | 47 | }, |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | static int clk_on; | ||
| 51 | |||
| 52 | static int musb_set_clock(struct clk *clk, int state) | ||
| 53 | { | ||
| 54 | if (state) { | ||
| 55 | if (clk_on > 0) | ||
| 56 | return -ENODEV; | ||
| 57 | |||
| 58 | clk_enable(clk); | ||
| 59 | clk_on = 1; | ||
| 60 | } else { | ||
| 61 | if (clk_on == 0) | ||
| 62 | return -ENODEV; | ||
| 63 | |||
| 64 | clk_disable(clk); | ||
| 65 | clk_on = 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | static struct musb_hdrc_eps_bits musb_eps[] = { | ||
| 72 | { "ep1_tx", 10, }, | ||
| 73 | { "ep1_rx", 10, }, | ||
| 74 | { "ep2_tx", 9, }, | ||
| 75 | { "ep2_rx", 9, }, | ||
| 76 | { "ep3_tx", 3, }, | ||
| 77 | { "ep3_rx", 3, }, | ||
| 78 | { "ep4_tx", 3, }, | ||
| 79 | { "ep4_rx", 3, }, | ||
| 80 | { "ep5_tx", 3, }, | ||
| 81 | { "ep5_rx", 3, }, | ||
| 82 | { "ep6_tx", 3, }, | ||
| 83 | { "ep6_rx", 3, }, | ||
| 84 | { "ep7_tx", 3, }, | ||
| 85 | { "ep7_rx", 3, }, | ||
| 86 | { "ep8_tx", 2, }, | ||
| 87 | { "ep8_rx", 2, }, | ||
| 88 | { "ep9_tx", 2, }, | ||
| 89 | { "ep9_rx", 2, }, | ||
| 90 | { "ep10_tx", 2, }, | ||
| 91 | { "ep10_rx", 2, }, | ||
| 92 | { "ep11_tx", 2, }, | ||
| 93 | { "ep11_rx", 2, }, | ||
| 94 | { "ep12_tx", 2, }, | ||
| 95 | { "ep12_rx", 2, }, | ||
| 96 | { "ep13_tx", 2, }, | ||
| 97 | { "ep13_rx", 2, }, | ||
| 98 | { "ep14_tx", 2, }, | ||
| 99 | { "ep14_rx", 2, }, | ||
| 100 | { "ep15_tx", 2, }, | ||
| 101 | { "ep15_rx", 2, }, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct musb_hdrc_config musb_config = { | 50 | static struct musb_hdrc_config musb_config = { |
| 105 | .multipoint = 1, | 51 | .multipoint = 1, |
| 106 | .dyn_fifo = 1, | 52 | .dyn_fifo = 1, |
| 107 | .soft_con = 1, | ||
| 108 | .dma = 1, | ||
| 109 | .num_eps = 16, | 53 | .num_eps = 16, |
| 110 | .dma_channels = 7, | ||
| 111 | .dma_req_chan = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), | ||
| 112 | .ram_bits = 12, | 54 | .ram_bits = 12, |
| 113 | .eps_bits = musb_eps, | ||
| 114 | }; | 55 | }; |
| 115 | 56 | ||
| 116 | static struct musb_hdrc_platform_data musb_plat = { | 57 | static struct musb_hdrc_platform_data musb_plat = { |
| @@ -122,7 +63,6 @@ static struct musb_hdrc_platform_data musb_plat = { | |||
| 122 | .mode = MUSB_PERIPHERAL, | 63 | .mode = MUSB_PERIPHERAL, |
| 123 | #endif | 64 | #endif |
| 124 | /* .clock is set dynamically */ | 65 | /* .clock is set dynamically */ |
| 125 | .set_clock = musb_set_clock, | ||
| 126 | .config = &musb_config, | 66 | .config = &musb_config, |
| 127 | 67 | ||
| 128 | /* REVISIT charge pump on TWL4030 can supply up to | 68 | /* REVISIT charge pump on TWL4030 can supply up to |
| @@ -146,28 +86,34 @@ static struct platform_device musb_device = { | |||
| 146 | .resource = musb_resources, | 86 | .resource = musb_resources, |
| 147 | }; | 87 | }; |
| 148 | 88 | ||
| 149 | void __init usb_musb_init(void) | 89 | void __init usb_musb_init(struct omap_musb_board_data *board_data) |
| 150 | { | 90 | { |
| 151 | if (cpu_is_omap243x()) | 91 | if (cpu_is_omap243x()) { |
| 152 | musb_resources[0].start = OMAP243X_HS_BASE; | 92 | musb_resources[0].start = OMAP243X_HS_BASE; |
| 153 | else | 93 | } else if (cpu_is_omap34xx()) { |
| 154 | musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; | 94 | musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; |
| 155 | musb_resources[0].end = musb_resources[0].start + SZ_8K - 1; | 95 | } else if (cpu_is_omap44xx()) { |
| 96 | musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; | ||
| 97 | musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; | ||
| 98 | musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; | ||
| 99 | } | ||
| 100 | musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; | ||
| 156 | 101 | ||
| 157 | /* | 102 | /* |
| 158 | * REVISIT: This line can be removed once all the platforms using | 103 | * REVISIT: This line can be removed once all the platforms using |
| 159 | * musb_core.c have been converted to use use clkdev. | 104 | * musb_core.c have been converted to use use clkdev. |
| 160 | */ | 105 | */ |
| 161 | musb_plat.clock = "ick"; | 106 | musb_plat.clock = "ick"; |
| 107 | musb_plat.board_data = board_data; | ||
| 108 | musb_plat.power = board_data->power >> 1; | ||
| 109 | musb_plat.mode = board_data->mode; | ||
| 162 | 110 | ||
| 163 | if (platform_device_register(&musb_device) < 0) { | 111 | if (platform_device_register(&musb_device) < 0) |
| 164 | printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); | 112 | printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); |
| 165 | return; | ||
| 166 | } | ||
| 167 | } | 113 | } |
| 168 | 114 | ||
| 169 | #else | 115 | #else |
| 170 | void __init usb_musb_init(void) | 116 | void __init usb_musb_init(struct omap_musb_board_data *board_data) |
| 171 | { | 117 | { |
| 172 | } | 118 | } |
| 173 | #endif /* CONFIG_USB_MUSB_SOC */ | 119 | #endif /* CONFIG_USB_MUSB_SOC */ |
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 2e3eec660864..6da796ef82bd 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -7,28 +7,37 @@ config ARCH_OMAP_OTG | |||
| 7 | 7 | ||
| 8 | choice | 8 | choice |
| 9 | prompt "OMAP System Type" | 9 | prompt "OMAP System Type" |
| 10 | default ARCH_OMAP1 | 10 | default ARCH_OMAP2PLUS |
| 11 | 11 | ||
| 12 | config ARCH_OMAP1 | 12 | config ARCH_OMAP1 |
| 13 | bool "TI OMAP1" | 13 | bool "TI OMAP1" |
| 14 | select COMMON_CLKDEV | 14 | select COMMON_CLKDEV |
| 15 | help | ||
| 16 | "Systems based on omap7xx, omap15xx or omap16xx" | ||
| 17 | |||
| 18 | config ARCH_OMAP2PLUS | ||
| 19 | bool "TI OMAP2/3/4" | ||
| 20 | select COMMON_CLKDEV | ||
| 21 | help | ||
| 22 | "Systems based on omap24xx, omap34xx or omap44xx" | ||
| 15 | 23 | ||
| 16 | config ARCH_OMAP2 | 24 | config ARCH_OMAP2 |
| 17 | bool "TI OMAP2" | 25 | bool "TI OMAP2" |
| 26 | depends on ARCH_OMAP2PLUS | ||
| 18 | select CPU_V6 | 27 | select CPU_V6 |
| 19 | select COMMON_CLKDEV | ||
| 20 | 28 | ||
| 21 | config ARCH_OMAP3 | 29 | config ARCH_OMAP3 |
| 22 | bool "TI OMAP3" | 30 | bool "TI OMAP3" |
| 31 | depends on ARCH_OMAP2PLUS | ||
| 23 | select CPU_V7 | 32 | select CPU_V7 |
| 24 | select COMMON_CLKDEV | 33 | select USB_ARCH_HAS_EHCI |
| 25 | select ARM_L1_CACHE_SHIFT_6 | 34 | select ARM_L1_CACHE_SHIFT_6 |
| 26 | 35 | ||
| 27 | config ARCH_OMAP4 | 36 | config ARCH_OMAP4 |
| 28 | bool "TI OMAP4" | 37 | bool "TI OMAP4" |
| 38 | depends on ARCH_OMAP2PLUS | ||
| 29 | select CPU_V7 | 39 | select CPU_V7 |
| 30 | select ARM_GIC | 40 | select ARM_GIC |
| 31 | select COMMON_CLKDEV | ||
| 32 | 41 | ||
| 33 | endchoice | 42 | endchoice |
| 34 | 43 | ||
| @@ -117,7 +126,7 @@ config OMAP_MPU_TIMER | |||
| 117 | 126 | ||
| 118 | config OMAP_32K_TIMER | 127 | config OMAP_32K_TIMER |
| 119 | bool "Use 32KHz timer" | 128 | bool "Use 32KHz timer" |
| 120 | depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4 | 129 | depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS |
| 121 | help | 130 | help |
| 122 | Select this option if you want to enable the OMAP 32KHz timer. | 131 | Select this option if you want to enable the OMAP 32KHz timer. |
| 123 | This timer saves power compared to the OMAP_MPU_TIMER, and has | 132 | This timer saves power compared to the OMAP_MPU_TIMER, and has |
| @@ -127,6 +136,23 @@ config OMAP_32K_TIMER | |||
| 127 | 136 | ||
| 128 | endchoice | 137 | endchoice |
| 129 | 138 | ||
| 139 | config OMAP3_L2_AUX_SECURE_SAVE_RESTORE | ||
| 140 | bool "OMAP3 HS/EMU save and restore for L2 AUX control register" | ||
| 141 | depends on ARCH_OMAP3 && PM | ||
| 142 | default n | ||
| 143 | help | ||
| 144 | Without this option, L2 Auxiliary control register contents are | ||
| 145 | lost during off-mode entry on HS/EMU devices. This feature | ||
| 146 | requires support from PPA / boot-loader in HS/EMU devices, which | ||
| 147 | currently does not exist by default. | ||
| 148 | |||
| 149 | config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID | ||
| 150 | int "Service ID for the support routine to set L2 AUX control" | ||
| 151 | depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE | ||
| 152 | default 43 | ||
| 153 | help | ||
| 154 | PPA routine service ID for setting L2 auxiliary control register. | ||
| 155 | |||
| 130 | config OMAP_32K_TIMER_HZ | 156 | config OMAP_32K_TIMER_HZ |
| 131 | int "Kernel internal timer frequency for 32KHz timer" | 157 | int "Kernel internal timer frequency for 32KHz timer" |
| 132 | range 32 1024 | 158 | range 32 1024 |
| @@ -138,29 +164,10 @@ config OMAP_32K_TIMER_HZ | |||
| 138 | 164 | ||
| 139 | config OMAP_DM_TIMER | 165 | config OMAP_DM_TIMER |
| 140 | bool "Use dual-mode timer" | 166 | bool "Use dual-mode timer" |
| 141 | depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4 | 167 | depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS |
| 142 | help | 168 | help |
| 143 | Select this option if you want to use OMAP Dual-Mode timers. | 169 | Select this option if you want to use OMAP Dual-Mode timers. |
| 144 | 170 | ||
| 145 | choice | ||
| 146 | prompt "Low-level debug console UART" | ||
| 147 | depends on ARCH_OMAP | ||
| 148 | default OMAP_LL_DEBUG_NONE | ||
| 149 | |||
| 150 | config OMAP_LL_DEBUG_UART1 | ||
| 151 | bool "UART1" | ||
| 152 | |||
| 153 | config OMAP_LL_DEBUG_UART2 | ||
| 154 | bool "UART2" | ||
| 155 | |||
| 156 | config OMAP_LL_DEBUG_UART3 | ||
| 157 | bool "UART3" | ||
| 158 | |||
| 159 | config OMAP_LL_DEBUG_NONE | ||
| 160 | bool "None" | ||
| 161 | |||
| 162 | endchoice | ||
| 163 | |||
| 164 | config OMAP_SERIAL_WAKE | 171 | config OMAP_SERIAL_WAKE |
| 165 | bool "Enable wake-up events for serial ports" | 172 | bool "Enable wake-up events for serial ports" |
| 166 | depends on ARCH_OMAP1 && OMAP_MUX | 173 | depends on ARCH_OMAP1 && OMAP_MUX |
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 4becbdd1935c..5261a0923691 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
| @@ -173,7 +173,7 @@ EXPORT_SYMBOL(clk_get_parent); | |||
| 173 | * OMAP specific clock functions shared between omap1 and omap2 | 173 | * OMAP specific clock functions shared between omap1 and omap2 |
| 174 | *-------------------------------------------------------------------------*/ | 174 | *-------------------------------------------------------------------------*/ |
| 175 | 175 | ||
| 176 | unsigned int __initdata mpurate; | 176 | int __initdata mpurate; |
| 177 | 177 | ||
| 178 | /* | 178 | /* |
| 179 | * By default we use the rate set by the bootloader. | 179 | * By default we use the rate set by the bootloader. |
| @@ -199,6 +199,17 @@ unsigned long followparent_recalc(struct clk *clk) | |||
| 199 | return clk->parent->rate; | 199 | return clk->parent->rate; |
| 200 | } | 200 | } |
| 201 | 201 | ||
| 202 | /* | ||
| 203 | * Used for clocks that have the same value as the parent clock, | ||
| 204 | * divided by some factor | ||
| 205 | */ | ||
| 206 | unsigned long omap_fixed_divisor_recalc(struct clk *clk) | ||
| 207 | { | ||
| 208 | WARN_ON(!clk->fixed_div); | ||
| 209 | |||
| 210 | return clk->parent->rate / clk->fixed_div; | ||
| 211 | } | ||
| 212 | |||
| 202 | void clk_reparent(struct clk *child, struct clk *parent) | 213 | void clk_reparent(struct clk *child, struct clk *parent) |
| 203 | { | 214 | { |
| 204 | list_del_init(&child->sibling); | 215 | list_del_init(&child->sibling); |
| @@ -302,6 +313,33 @@ void clk_enable_init_clocks(void) | |||
| 302 | } | 313 | } |
| 303 | } | 314 | } |
| 304 | 315 | ||
| 316 | /** | ||
| 317 | * omap_clk_get_by_name - locate OMAP struct clk by its name | ||
| 318 | * @name: name of the struct clk to locate | ||
| 319 | * | ||
| 320 | * Locate an OMAP struct clk by its name. Assumes that struct clk | ||
| 321 | * names are unique. Returns NULL if not found or a pointer to the | ||
| 322 | * struct clk if found. | ||
| 323 | */ | ||
| 324 | struct clk *omap_clk_get_by_name(const char *name) | ||
| 325 | { | ||
| 326 | struct clk *c; | ||
| 327 | struct clk *ret = NULL; | ||
| 328 | |||
| 329 | mutex_lock(&clocks_mutex); | ||
| 330 | |||
| 331 | list_for_each_entry(c, &clocks, node) { | ||
| 332 | if (!strcmp(c->name, name)) { | ||
| 333 | ret = c; | ||
| 334 | break; | ||
| 335 | } | ||
| 336 | } | ||
| 337 | |||
| 338 | mutex_unlock(&clocks_mutex); | ||
| 339 | |||
| 340 | return ret; | ||
| 341 | } | ||
| 342 | |||
| 305 | /* | 343 | /* |
| 306 | * Low level helpers | 344 | * Low level helpers |
| 307 | */ | 345 | */ |
| @@ -319,6 +357,16 @@ const struct clkops clkops_null = { | |||
| 319 | .disable = clkll_disable_null, | 357 | .disable = clkll_disable_null, |
| 320 | }; | 358 | }; |
| 321 | 359 | ||
| 360 | /* | ||
| 361 | * Dummy clock | ||
| 362 | * | ||
| 363 | * Used for clock aliases that are needed on some OMAPs, but not others | ||
| 364 | */ | ||
| 365 | struct clk dummy_ck = { | ||
| 366 | .name = "dummy", | ||
| 367 | .ops = &clkops_null, | ||
| 368 | }; | ||
| 369 | |||
| 322 | #ifdef CONFIG_CPU_FREQ | 370 | #ifdef CONFIG_CPU_FREQ |
| 323 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | 371 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) |
| 324 | { | 372 | { |
| @@ -397,8 +445,6 @@ static int clk_debugfs_register_one(struct clk *c) | |||
| 397 | char *p = s; | 445 | char *p = s; |
| 398 | 446 | ||
| 399 | p += sprintf(p, "%s", c->name); | 447 | p += sprintf(p, "%s", c->name); |
| 400 | if (c->id != 0) | ||
| 401 | sprintf(p, ":%d", c->id); | ||
| 402 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | 448 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); |
| 403 | if (!d) | 449 | if (!d) |
| 404 | return -ENOMEM; | 450 | return -ENOMEM; |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index dddc0273bc8b..088c1a03b946 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <plat/control.h> | 34 | #include <plat/control.h> |
| 35 | #include <plat/mux.h> | 35 | #include <plat/mux.h> |
| 36 | #include <plat/fpga.h> | 36 | #include <plat/fpga.h> |
| 37 | #include <plat/serial.h> | ||
| 37 | 38 | ||
| 38 | #include <plat/clock.h> | 39 | #include <plat/clock.h> |
| 39 | 40 | ||
| @@ -126,7 +127,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs) | |||
| 126 | #define omap2430_32k_read NULL | 127 | #define omap2430_32k_read NULL |
| 127 | #endif | 128 | #endif |
| 128 | 129 | ||
| 129 | #ifdef CONFIG_ARCH_OMAP34XX | 130 | #ifdef CONFIG_ARCH_OMAP3 |
| 130 | static cycle_t omap34xx_32k_read(struct clocksource *cs) | 131 | static cycle_t omap34xx_32k_read(struct clocksource *cs) |
| 131 | { | 132 | { |
| 132 | return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10); | 133 | return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10); |
| @@ -245,6 +246,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals) | |||
| 245 | omap2_set_globals_sdrc(omap2_globals); | 246 | omap2_set_globals_sdrc(omap2_globals); |
| 246 | omap2_set_globals_control(omap2_globals); | 247 | omap2_set_globals_control(omap2_globals); |
| 247 | omap2_set_globals_prcm(omap2_globals); | 248 | omap2_set_globals_prcm(omap2_globals); |
| 249 | omap2_set_globals_uart(omap2_globals); | ||
| 248 | } | 250 | } |
| 249 | 251 | ||
| 250 | #endif | 252 | #endif |
| @@ -254,11 +256,14 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals) | |||
| 254 | static struct omap_globals omap242x_globals = { | 256 | static struct omap_globals omap242x_globals = { |
| 255 | .class = OMAP242X_CLASS, | 257 | .class = OMAP242X_CLASS, |
| 256 | .tap = OMAP2_L4_IO_ADDRESS(0x48014000), | 258 | .tap = OMAP2_L4_IO_ADDRESS(0x48014000), |
| 257 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | 259 | .sdrc = OMAP2420_SDRC_BASE, |
| 258 | .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE), | 260 | .sms = OMAP2420_SMS_BASE, |
| 259 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE), | 261 | .ctrl = OMAP2420_CTRL_BASE, |
| 260 | .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE), | 262 | .prm = OMAP2420_PRM_BASE, |
| 261 | .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), | 263 | .cm = OMAP2420_CM_BASE, |
| 264 | .uart1_phys = OMAP2_UART1_BASE, | ||
| 265 | .uart2_phys = OMAP2_UART2_BASE, | ||
| 266 | .uart3_phys = OMAP2_UART3_BASE, | ||
| 262 | }; | 267 | }; |
| 263 | 268 | ||
| 264 | void __init omap2_set_globals_242x(void) | 269 | void __init omap2_set_globals_242x(void) |
| @@ -272,11 +277,14 @@ void __init omap2_set_globals_242x(void) | |||
| 272 | static struct omap_globals omap243x_globals = { | 277 | static struct omap_globals omap243x_globals = { |
| 273 | .class = OMAP243X_CLASS, | 278 | .class = OMAP243X_CLASS, |
| 274 | .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), | 279 | .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), |
| 275 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | 280 | .sdrc = OMAP243X_SDRC_BASE, |
| 276 | .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE), | 281 | .sms = OMAP243X_SMS_BASE, |
| 277 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), | 282 | .ctrl = OMAP243X_CTRL_BASE, |
| 278 | .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE), | 283 | .prm = OMAP2430_PRM_BASE, |
| 279 | .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), | 284 | .cm = OMAP2430_CM_BASE, |
| 285 | .uart1_phys = OMAP2_UART1_BASE, | ||
| 286 | .uart2_phys = OMAP2_UART2_BASE, | ||
| 287 | .uart3_phys = OMAP2_UART3_BASE, | ||
| 280 | }; | 288 | }; |
| 281 | 289 | ||
| 282 | void __init omap2_set_globals_243x(void) | 290 | void __init omap2_set_globals_243x(void) |
| @@ -285,21 +293,31 @@ void __init omap2_set_globals_243x(void) | |||
| 285 | } | 293 | } |
| 286 | #endif | 294 | #endif |
| 287 | 295 | ||
| 288 | #if defined(CONFIG_ARCH_OMAP3430) | 296 | #if defined(CONFIG_ARCH_OMAP3) |
| 289 | 297 | ||
| 290 | static struct omap_globals omap343x_globals = { | 298 | static struct omap_globals omap3_globals = { |
| 291 | .class = OMAP343X_CLASS, | 299 | .class = OMAP343X_CLASS, |
| 292 | .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), | 300 | .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), |
| 293 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | 301 | .sdrc = OMAP343X_SDRC_BASE, |
| 294 | .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE), | 302 | .sms = OMAP343X_SMS_BASE, |
| 295 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), | 303 | .ctrl = OMAP343X_CTRL_BASE, |
| 296 | .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE), | 304 | .prm = OMAP3430_PRM_BASE, |
| 297 | .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), | 305 | .cm = OMAP3430_CM_BASE, |
| 306 | .uart1_phys = OMAP3_UART1_BASE, | ||
| 307 | .uart2_phys = OMAP3_UART2_BASE, | ||
| 308 | .uart3_phys = OMAP3_UART3_BASE, | ||
| 298 | }; | 309 | }; |
| 299 | 310 | ||
| 300 | void __init omap2_set_globals_343x(void) | 311 | void __init omap2_set_globals_343x(void) |
| 301 | { | 312 | { |
| 302 | __omap2_set_globals(&omap343x_globals); | 313 | __omap2_set_globals(&omap3_globals); |
| 314 | } | ||
| 315 | |||
| 316 | void __init omap2_set_globals_36xx(void) | ||
| 317 | { | ||
| 318 | omap3_globals.uart4_phys = OMAP3_UART4_BASE; | ||
| 319 | |||
| 320 | __omap2_set_globals(&omap3_globals); | ||
| 303 | } | 321 | } |
| 304 | #endif | 322 | #endif |
| 305 | 323 | ||
| @@ -307,10 +325,14 @@ void __init omap2_set_globals_343x(void) | |||
| 307 | static struct omap_globals omap4_globals = { | 325 | static struct omap_globals omap4_globals = { |
| 308 | .class = OMAP443X_CLASS, | 326 | .class = OMAP443X_CLASS, |
| 309 | .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), | 327 | .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), |
| 310 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), | 328 | .ctrl = OMAP443X_CTRL_BASE, |
| 311 | .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), | 329 | .prm = OMAP4430_PRM_BASE, |
| 312 | .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | 330 | .cm = OMAP4430_CM_BASE, |
| 313 | .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), | 331 | .cm2 = OMAP4430_CM2_BASE, |
| 332 | .uart1_phys = OMAP4_UART1_BASE, | ||
| 333 | .uart2_phys = OMAP4_UART2_BASE, | ||
| 334 | .uart3_phys = OMAP4_UART3_BASE, | ||
| 335 | .uart4_phys = OMAP4_UART4_BASE, | ||
| 314 | }; | 336 | }; |
| 315 | 337 | ||
| 316 | void __init omap2_set_globals_443x(void) | 338 | void __init omap2_set_globals_443x(void) |
| @@ -318,6 +340,7 @@ void __init omap2_set_globals_443x(void) | |||
| 318 | omap2_set_globals_tap(&omap4_globals); | 340 | omap2_set_globals_tap(&omap4_globals); |
| 319 | omap2_set_globals_control(&omap4_globals); | 341 | omap2_set_globals_control(&omap4_globals); |
| 320 | omap2_set_globals_prcm(&omap4_globals); | 342 | omap2_set_globals_prcm(&omap4_globals); |
| 343 | omap2_set_globals_uart(&omap4_globals); | ||
| 321 | } | 344 | } |
| 322 | #endif | 345 | #endif |
| 323 | 346 | ||
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 30b5db73017a..4a4cd8774aaa 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <plat/menelaus.h> | 28 | #include <plat/menelaus.h> |
| 29 | #include <plat/mcbsp.h> | 29 | #include <plat/mcbsp.h> |
| 30 | #include <plat/dsp_common.h> | 30 | #include <plat/dsp_common.h> |
| 31 | #include <plat/omap44xx.h> | ||
| 31 | 32 | ||
| 32 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) | 33 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) |
| 33 | 34 | ||
| @@ -192,6 +193,41 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, | |||
| 192 | 193 | ||
| 193 | /*-------------------------------------------------------------------------*/ | 194 | /*-------------------------------------------------------------------------*/ |
| 194 | 195 | ||
| 196 | #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ | ||
| 197 | defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) | ||
| 198 | |||
| 199 | static struct resource mcpdm_resources[] = { | ||
| 200 | { | ||
| 201 | .name = "mcpdm_mem", | ||
| 202 | .start = OMAP44XX_MCPDM_BASE, | ||
| 203 | .end = OMAP44XX_MCPDM_BASE + SZ_4K, | ||
| 204 | .flags = IORESOURCE_MEM, | ||
| 205 | }, | ||
| 206 | { | ||
| 207 | .name = "mcpdm_irq", | ||
| 208 | .start = OMAP44XX_IRQ_MCPDM, | ||
| 209 | .end = OMAP44XX_IRQ_MCPDM, | ||
| 210 | .flags = IORESOURCE_IRQ, | ||
| 211 | }, | ||
| 212 | }; | ||
| 213 | |||
| 214 | static struct platform_device omap_mcpdm_device = { | ||
| 215 | .name = "omap-mcpdm", | ||
| 216 | .id = -1, | ||
| 217 | .num_resources = ARRAY_SIZE(mcpdm_resources), | ||
| 218 | .resource = mcpdm_resources, | ||
| 219 | }; | ||
| 220 | |||
| 221 | static void omap_init_mcpdm(void) | ||
| 222 | { | ||
| 223 | (void) platform_device_register(&omap_mcpdm_device); | ||
| 224 | } | ||
| 225 | #else | ||
| 226 | static inline void omap_init_mcpdm(void) {} | ||
| 227 | #endif | ||
| 228 | |||
| 229 | /*-------------------------------------------------------------------------*/ | ||
| 230 | |||
| 195 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ | 231 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
| 196 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | 232 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
| 197 | 233 | ||
| @@ -244,7 +280,7 @@ fail: | |||
| 244 | 280 | ||
| 245 | #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) | 281 | #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) |
| 246 | 282 | ||
| 247 | #ifdef CONFIG_ARCH_OMAP24XX | 283 | #ifdef CONFIG_ARCH_OMAP2 |
| 248 | #define OMAP_RNG_BASE 0x480A0000 | 284 | #define OMAP_RNG_BASE 0x480A0000 |
| 249 | #else | 285 | #else |
| 250 | #define OMAP_RNG_BASE 0xfffe5000 | 286 | #define OMAP_RNG_BASE 0xfffe5000 |
| @@ -385,6 +421,7 @@ static int __init omap_init_devices(void) | |||
| 385 | omap_init_dsp(); | 421 | omap_init_dsp(); |
| 386 | omap_init_kp(); | 422 | omap_init_kp(); |
| 387 | omap_init_rng(); | 423 | omap_init_rng(); |
| 424 | omap_init_mcpdm(); | ||
| 388 | omap_init_uwire(); | 425 | omap_init_uwire(); |
| 389 | omap_init_wdt(); | 426 | omap_init_wdt(); |
| 390 | return 0; | 427 | return 0; |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 728c64204184..2ab224c8e16c 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -1870,8 +1870,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) | |||
| 1870 | #define omap1_dma_irq_handler NULL | 1870 | #define omap1_dma_irq_handler NULL |
| 1871 | #endif | 1871 | #endif |
| 1872 | 1872 | ||
| 1873 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 1873 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 1874 | defined(CONFIG_ARCH_OMAP4) | ||
| 1875 | 1874 | ||
| 1876 | static int omap2_dma_handle_ch(int ch) | 1875 | static int omap2_dma_handle_ch(int ch) |
| 1877 | { | 1876 | { |
| @@ -2133,13 +2132,13 @@ static int __init omap_init_dma(void) | |||
| 2133 | if (cpu_class_is_omap2()) { | 2132 | if (cpu_class_is_omap2()) { |
| 2134 | int irq; | 2133 | int irq; |
| 2135 | if (cpu_is_omap44xx()) | 2134 | if (cpu_is_omap44xx()) |
| 2136 | irq = INT_44XX_SDMA_IRQ0; | 2135 | irq = OMAP44XX_IRQ_SDMA_0; |
| 2137 | else | 2136 | else |
| 2138 | irq = INT_24XX_SDMA_IRQ0; | 2137 | irq = INT_24XX_SDMA_IRQ0; |
| 2139 | setup_irq(irq, &omap24xx_dma_irq); | 2138 | setup_irq(irq, &omap24xx_dma_irq); |
| 2140 | } | 2139 | } |
| 2141 | 2140 | ||
| 2142 | if (cpu_is_omap34xx()) { | 2141 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
| 2143 | /* Enable smartidle idlemodes and autoidle */ | 2142 | /* Enable smartidle idlemodes and autoidle */ |
| 2144 | u32 v = dma_read(OCP_SYSCONFIG); | 2143 | u32 v = dma_read(OCP_SYSCONFIG); |
| 2145 | v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | | 2144 | v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | |
| @@ -2150,7 +2149,8 @@ static int __init omap_init_dma(void) | |||
| 2150 | DMA_SYSCONFIG_AUTOIDLE); | 2149 | DMA_SYSCONFIG_AUTOIDLE); |
| 2151 | dma_write(v , OCP_SYSCONFIG); | 2150 | dma_write(v , OCP_SYSCONFIG); |
| 2152 | /* reserve dma channels 0 and 1 in high security devices */ | 2151 | /* reserve dma channels 0 and 1 in high security devices */ |
| 2153 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | 2152 | if (cpu_is_omap34xx() && |
| 2153 | (omap_type() != OMAP2_DEVICE_TYPE_GP)) { | ||
| 2154 | printk(KERN_INFO "Reserving DMA channels 0 and 1 for " | 2154 | printk(KERN_INFO "Reserving DMA channels 0 and 1 for " |
| 2155 | "HS ROM code\n"); | 2155 | "HS ROM code\n"); |
| 2156 | dma_chan[0].dev_id = 0; | 2156 | dma_chan[0].dev_id = 0; |
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 08ccf8922520..4d99dfbc8bef 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
| @@ -153,8 +153,7 @@ | |||
| 153 | struct omap_dm_timer { | 153 | struct omap_dm_timer { |
| 154 | unsigned long phys_base; | 154 | unsigned long phys_base; |
| 155 | int irq; | 155 | int irq; |
| 156 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 156 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 157 | defined(CONFIG_ARCH_OMAP4) | ||
| 158 | struct clk *iclk, *fclk; | 157 | struct clk *iclk, *fclk; |
| 159 | #endif | 158 | #endif |
| 160 | void __iomem *io_base; | 159 | void __iomem *io_base; |
| @@ -163,20 +162,9 @@ struct omap_dm_timer { | |||
| 163 | unsigned posted:1; | 162 | unsigned posted:1; |
| 164 | }; | 163 | }; |
| 165 | 164 | ||
| 166 | #ifdef CONFIG_ARCH_OMAP1 | 165 | static int dm_timer_count; |
| 167 | |||
| 168 | #define omap_dm_clk_enable(x) | ||
| 169 | #define omap_dm_clk_disable(x) | ||
| 170 | #define omap2_dm_timers NULL | ||
| 171 | #define omap2_dm_source_names NULL | ||
| 172 | #define omap2_dm_source_clocks NULL | ||
| 173 | #define omap3_dm_timers NULL | ||
| 174 | #define omap3_dm_source_names NULL | ||
| 175 | #define omap3_dm_source_clocks NULL | ||
| 176 | #define omap4_dm_timers NULL | ||
| 177 | #define omap4_dm_source_names NULL | ||
| 178 | #define omap4_dm_source_clocks NULL | ||
| 179 | 166 | ||
| 167 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 180 | static struct omap_dm_timer omap1_dm_timers[] = { | 168 | static struct omap_dm_timer omap1_dm_timers[] = { |
| 181 | { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, | 169 | { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, |
| 182 | { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, | 170 | { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, |
| @@ -188,20 +176,14 @@ static struct omap_dm_timer omap1_dm_timers[] = { | |||
| 188 | { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, | 176 | { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, |
| 189 | }; | 177 | }; |
| 190 | 178 | ||
| 191 | static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); | 179 | static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers); |
| 192 | |||
| 193 | #elif defined(CONFIG_ARCH_OMAP2) | ||
| 194 | 180 | ||
| 195 | #define omap_dm_clk_enable(x) clk_enable(x) | 181 | #else |
| 196 | #define omap_dm_clk_disable(x) clk_disable(x) | ||
| 197 | #define omap1_dm_timers NULL | 182 | #define omap1_dm_timers NULL |
| 198 | #define omap3_dm_timers NULL | 183 | #define omap1_dm_timer_count 0 |
| 199 | #define omap3_dm_source_names NULL | 184 | #endif /* CONFIG_ARCH_OMAP1 */ |
| 200 | #define omap3_dm_source_clocks NULL | ||
| 201 | #define omap4_dm_timers NULL | ||
| 202 | #define omap4_dm_source_names NULL | ||
| 203 | #define omap4_dm_source_clocks NULL | ||
| 204 | 185 | ||
| 186 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 205 | static struct omap_dm_timer omap2_dm_timers[] = { | 187 | static struct omap_dm_timer omap2_dm_timers[] = { |
| 206 | { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, | 188 | { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, |
| 207 | { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, | 189 | { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, |
| @@ -225,20 +207,16 @@ static const char *omap2_dm_source_names[] __initdata = { | |||
| 225 | }; | 207 | }; |
| 226 | 208 | ||
| 227 | static struct clk *omap2_dm_source_clocks[3]; | 209 | static struct clk *omap2_dm_source_clocks[3]; |
| 228 | static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); | 210 | static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers); |
| 229 | 211 | ||
| 230 | #elif defined(CONFIG_ARCH_OMAP3) | 212 | #else |
| 231 | |||
| 232 | #define omap_dm_clk_enable(x) clk_enable(x) | ||
| 233 | #define omap_dm_clk_disable(x) clk_disable(x) | ||
| 234 | #define omap1_dm_timers NULL | ||
| 235 | #define omap2_dm_timers NULL | 213 | #define omap2_dm_timers NULL |
| 214 | #define omap2_dm_timer_count 0 | ||
| 236 | #define omap2_dm_source_names NULL | 215 | #define omap2_dm_source_names NULL |
| 237 | #define omap2_dm_source_clocks NULL | 216 | #define omap2_dm_source_clocks NULL |
| 238 | #define omap4_dm_timers NULL | 217 | #endif /* CONFIG_ARCH_OMAP2 */ |
| 239 | #define omap4_dm_source_names NULL | ||
| 240 | #define omap4_dm_source_clocks NULL | ||
| 241 | 218 | ||
| 219 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 242 | static struct omap_dm_timer omap3_dm_timers[] = { | 220 | static struct omap_dm_timer omap3_dm_timers[] = { |
| 243 | { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, | 221 | { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, |
| 244 | { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, | 222 | { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, |
| @@ -261,33 +239,29 @@ static const char *omap3_dm_source_names[] __initdata = { | |||
| 261 | }; | 239 | }; |
| 262 | 240 | ||
| 263 | static struct clk *omap3_dm_source_clocks[2]; | 241 | static struct clk *omap3_dm_source_clocks[2]; |
| 264 | static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); | 242 | static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers); |
| 265 | |||
| 266 | #elif defined(CONFIG_ARCH_OMAP4) | ||
| 267 | 243 | ||
| 268 | #define omap_dm_clk_enable(x) clk_enable(x) | 244 | #else |
| 269 | #define omap_dm_clk_disable(x) clk_disable(x) | ||
| 270 | #define omap1_dm_timers NULL | ||
| 271 | #define omap2_dm_timers NULL | ||
| 272 | #define omap2_dm_source_names NULL | ||
| 273 | #define omap2_dm_source_clocks NULL | ||
| 274 | #define omap3_dm_timers NULL | 245 | #define omap3_dm_timers NULL |
| 246 | #define omap3_dm_timer_count 0 | ||
| 275 | #define omap3_dm_source_names NULL | 247 | #define omap3_dm_source_names NULL |
| 276 | #define omap3_dm_source_clocks NULL | 248 | #define omap3_dm_source_clocks NULL |
| 249 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
| 277 | 250 | ||
| 251 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 278 | static struct omap_dm_timer omap4_dm_timers[] = { | 252 | static struct omap_dm_timer omap4_dm_timers[] = { |
| 279 | { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 }, | 253 | { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 }, |
| 280 | { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 }, | 254 | { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 }, |
| 281 | { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 }, | 255 | { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 }, |
| 282 | { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 }, | 256 | { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 }, |
| 283 | { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 }, | 257 | { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 }, |
| 284 | { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 }, | 258 | { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 }, |
| 285 | { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 }, | 259 | { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 }, |
| 286 | { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 }, | 260 | { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 }, |
| 287 | { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 }, | 261 | { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 }, |
| 288 | { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 }, | 262 | { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 }, |
| 289 | { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 }, | 263 | { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 }, |
| 290 | { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 }, | 264 | { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, |
| 291 | }; | 265 | }; |
| 292 | static const char *omap4_dm_source_names[] __initdata = { | 266 | static const char *omap4_dm_source_names[] __initdata = { |
| 293 | "sys_ck", | 267 | "sys_ck", |
| @@ -295,13 +269,14 @@ static const char *omap4_dm_source_names[] __initdata = { | |||
| 295 | NULL | 269 | NULL |
| 296 | }; | 270 | }; |
| 297 | static struct clk *omap4_dm_source_clocks[2]; | 271 | static struct clk *omap4_dm_source_clocks[2]; |
| 298 | static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers); | 272 | static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers); |
| 299 | 273 | ||
| 300 | #else | 274 | #else |
| 301 | 275 | #define omap4_dm_timers NULL | |
| 302 | #error OMAP architecture not supported! | 276 | #define omap4_dm_timer_count 0 |
| 303 | 277 | #define omap4_dm_source_names NULL | |
| 304 | #endif | 278 | #define omap4_dm_source_clocks NULL |
| 279 | #endif /* CONFIG_ARCH_OMAP4 */ | ||
| 305 | 280 | ||
| 306 | static struct omap_dm_timer *dm_timers; | 281 | static struct omap_dm_timer *dm_timers; |
| 307 | static const char **dm_source_names; | 282 | static const char **dm_source_names; |
| @@ -450,8 +425,12 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer) | |||
| 450 | if (timer->enabled) | 425 | if (timer->enabled) |
| 451 | return; | 426 | return; |
| 452 | 427 | ||
| 453 | omap_dm_clk_enable(timer->fclk); | 428 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 454 | omap_dm_clk_enable(timer->iclk); | 429 | if (cpu_class_is_omap2()) { |
| 430 | clk_enable(timer->fclk); | ||
| 431 | clk_enable(timer->iclk); | ||
| 432 | } | ||
| 433 | #endif | ||
| 455 | 434 | ||
| 456 | timer->enabled = 1; | 435 | timer->enabled = 1; |
| 457 | } | 436 | } |
| @@ -462,8 +441,12 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer) | |||
| 462 | if (!timer->enabled) | 441 | if (!timer->enabled) |
| 463 | return; | 442 | return; |
| 464 | 443 | ||
| 465 | omap_dm_clk_disable(timer->iclk); | 444 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 466 | omap_dm_clk_disable(timer->fclk); | 445 | if (cpu_class_is_omap2()) { |
| 446 | clk_disable(timer->iclk); | ||
| 447 | clk_disable(timer->fclk); | ||
| 448 | } | ||
| 449 | #endif | ||
| 467 | 450 | ||
| 468 | timer->enabled = 0; | 451 | timer->enabled = 0; |
| 469 | } | 452 | } |
| @@ -506,8 +489,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |||
| 506 | } | 489 | } |
| 507 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); | 490 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
| 508 | 491 | ||
| 509 | #elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 492 | #else |
| 510 | defined(CONFIG_ARCH_OMAP4) | ||
| 511 | 493 | ||
| 512 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | 494 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
| 513 | { | 495 | { |
| @@ -551,8 +533,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) | |||
| 551 | if (l & OMAP_TIMER_CTRL_ST) { | 533 | if (l & OMAP_TIMER_CTRL_ST) { |
| 552 | l &= ~0x1; | 534 | l &= ~0x1; |
| 553 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 535 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 554 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 536 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 555 | defined(CONFIG_ARCH_OMAP4) | ||
| 556 | /* Readback to make sure write has completed */ | 537 | /* Readback to make sure write has completed */ |
| 557 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | 538 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
| 558 | /* | 539 | /* |
| @@ -764,17 +745,21 @@ int __init omap_dm_timer_init(void) | |||
| 764 | 745 | ||
| 765 | if (cpu_class_is_omap1()) { | 746 | if (cpu_class_is_omap1()) { |
| 766 | dm_timers = omap1_dm_timers; | 747 | dm_timers = omap1_dm_timers; |
| 748 | dm_timer_count = omap1_dm_timer_count; | ||
| 767 | map_size = SZ_2K; | 749 | map_size = SZ_2K; |
| 768 | } else if (cpu_is_omap24xx()) { | 750 | } else if (cpu_is_omap24xx()) { |
| 769 | dm_timers = omap2_dm_timers; | 751 | dm_timers = omap2_dm_timers; |
| 752 | dm_timer_count = omap2_dm_timer_count; | ||
| 770 | dm_source_names = omap2_dm_source_names; | 753 | dm_source_names = omap2_dm_source_names; |
| 771 | dm_source_clocks = omap2_dm_source_clocks; | 754 | dm_source_clocks = omap2_dm_source_clocks; |
| 772 | } else if (cpu_is_omap34xx()) { | 755 | } else if (cpu_is_omap34xx()) { |
| 773 | dm_timers = omap3_dm_timers; | 756 | dm_timers = omap3_dm_timers; |
| 757 | dm_timer_count = omap3_dm_timer_count; | ||
| 774 | dm_source_names = omap3_dm_source_names; | 758 | dm_source_names = omap3_dm_source_names; |
| 775 | dm_source_clocks = omap3_dm_source_clocks; | 759 | dm_source_clocks = omap3_dm_source_clocks; |
| 776 | } else if (cpu_is_omap44xx()) { | 760 | } else if (cpu_is_omap44xx()) { |
| 777 | dm_timers = omap4_dm_timers; | 761 | dm_timers = omap4_dm_timers; |
| 762 | dm_timer_count = omap4_dm_timer_count; | ||
| 778 | dm_source_names = omap4_dm_source_names; | 763 | dm_source_names = omap4_dm_source_names; |
| 779 | dm_source_clocks = omap4_dm_source_clocks; | 764 | dm_source_clocks = omap4_dm_source_clocks; |
| 780 | } | 765 | } |
| @@ -793,8 +778,7 @@ int __init omap_dm_timer_init(void) | |||
| 793 | timer->io_base = ioremap(timer->phys_base, map_size); | 778 | timer->io_base = ioremap(timer->phys_base, map_size); |
| 794 | BUG_ON(!timer->io_base); | 779 | BUG_ON(!timer->io_base); |
| 795 | 780 | ||
| 796 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 781 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 797 | defined(CONFIG_ARCH_OMAP4) | ||
| 798 | if (cpu_class_is_omap2()) { | 782 | if (cpu_class_is_omap2()) { |
| 799 | char clk_name[16]; | 783 | char clk_name[16]; |
| 800 | sprintf(clk_name, "gpt%d_ick", i + 1); | 784 | sprintf(clk_name, "gpt%d_ick", i + 1); |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d2422c766cca..337199ed3479 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
| @@ -177,13 +177,11 @@ struct gpio_bank { | |||
| 177 | u16 irq; | 177 | u16 irq; |
| 178 | u16 virtual_irq_start; | 178 | u16 virtual_irq_start; |
| 179 | int method; | 179 | int method; |
| 180 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ | 180 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
| 181 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | ||
| 182 | u32 suspend_wakeup; | 181 | u32 suspend_wakeup; |
| 183 | u32 saved_wakeup; | 182 | u32 saved_wakeup; |
| 184 | #endif | 183 | #endif |
| 185 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 184 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 186 | defined(CONFIG_ARCH_OMAP4) | ||
| 187 | u32 non_wakeup_gpios; | 185 | u32 non_wakeup_gpios; |
| 188 | u32 enabled_non_wakeup_gpios; | 186 | u32 enabled_non_wakeup_gpios; |
| 189 | 187 | ||
| @@ -204,6 +202,7 @@ struct gpio_bank { | |||
| 204 | #define METHOD_GPIO_1610 2 | 202 | #define METHOD_GPIO_1610 2 |
| 205 | #define METHOD_GPIO_7XX 3 | 203 | #define METHOD_GPIO_7XX 3 |
| 206 | #define METHOD_GPIO_24XX 5 | 204 | #define METHOD_GPIO_24XX 5 |
| 205 | #define METHOD_GPIO_44XX 6 | ||
| 207 | 206 | ||
| 208 | #ifdef CONFIG_ARCH_OMAP16XX | 207 | #ifdef CONFIG_ARCH_OMAP16XX |
| 209 | static struct gpio_bank gpio_bank_1610[5] = { | 208 | static struct gpio_bank gpio_bank_1610[5] = { |
| @@ -248,7 +247,7 @@ static struct gpio_bank gpio_bank_7xx[7] = { | |||
| 248 | }; | 247 | }; |
| 249 | #endif | 248 | #endif |
| 250 | 249 | ||
| 251 | #ifdef CONFIG_ARCH_OMAP24XX | 250 | #ifdef CONFIG_ARCH_OMAP2 |
| 252 | 251 | ||
| 253 | static struct gpio_bank gpio_bank_242x[4] = { | 252 | static struct gpio_bank gpio_bank_242x[4] = { |
| 254 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, | 253 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
| @@ -276,7 +275,7 @@ static struct gpio_bank gpio_bank_243x[5] = { | |||
| 276 | 275 | ||
| 277 | #endif | 276 | #endif |
| 278 | 277 | ||
| 279 | #ifdef CONFIG_ARCH_OMAP34XX | 278 | #ifdef CONFIG_ARCH_OMAP3 |
| 280 | static struct gpio_bank gpio_bank_34xx[6] = { | 279 | static struct gpio_bank gpio_bank_34xx[6] = { |
| 281 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, | 280 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
| 282 | METHOD_GPIO_24XX }, | 281 | METHOD_GPIO_24XX }, |
| @@ -313,18 +312,18 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; | |||
| 313 | 312 | ||
| 314 | #ifdef CONFIG_ARCH_OMAP4 | 313 | #ifdef CONFIG_ARCH_OMAP4 |
| 315 | static struct gpio_bank gpio_bank_44xx[6] = { | 314 | static struct gpio_bank gpio_bank_44xx[6] = { |
| 316 | { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, | 315 | { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, |
| 317 | METHOD_GPIO_24XX }, | 316 | METHOD_GPIO_44XX }, |
| 318 | { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, | 317 | { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, |
| 319 | METHOD_GPIO_24XX }, | 318 | METHOD_GPIO_44XX }, |
| 320 | { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, | 319 | { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, |
| 321 | METHOD_GPIO_24XX }, | 320 | METHOD_GPIO_44XX }, |
| 322 | { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, | 321 | { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, |
| 323 | METHOD_GPIO_24XX }, | 322 | METHOD_GPIO_44XX }, |
| 324 | { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, | 323 | { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, |
| 325 | METHOD_GPIO_24XX }, | 324 | METHOD_GPIO_44XX }, |
| 326 | { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, | 325 | { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, |
| 327 | METHOD_GPIO_24XX }, | 326 | METHOD_GPIO_44XX }, |
| 328 | }; | 327 | }; |
| 329 | 328 | ||
| 330 | #endif | 329 | #endif |
| @@ -426,13 +425,13 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |||
| 426 | reg += OMAP7XX_GPIO_DIR_CONTROL; | 425 | reg += OMAP7XX_GPIO_DIR_CONTROL; |
| 427 | break; | 426 | break; |
| 428 | #endif | 427 | #endif |
| 429 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 428 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 430 | case METHOD_GPIO_24XX: | 429 | case METHOD_GPIO_24XX: |
| 431 | reg += OMAP24XX_GPIO_OE; | 430 | reg += OMAP24XX_GPIO_OE; |
| 432 | break; | 431 | break; |
| 433 | #endif | 432 | #endif |
| 434 | #if defined(CONFIG_ARCH_OMAP4) | 433 | #if defined(CONFIG_ARCH_OMAP4) |
| 435 | case METHOD_GPIO_24XX: | 434 | case METHOD_GPIO_44XX: |
| 436 | reg += OMAP4_GPIO_OE; | 435 | reg += OMAP4_GPIO_OE; |
| 437 | break; | 436 | break; |
| 438 | #endif | 437 | #endif |
| @@ -493,7 +492,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |||
| 493 | l &= ~(1 << gpio); | 492 | l &= ~(1 << gpio); |
| 494 | break; | 493 | break; |
| 495 | #endif | 494 | #endif |
| 496 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 495 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 497 | case METHOD_GPIO_24XX: | 496 | case METHOD_GPIO_24XX: |
| 498 | if (enable) | 497 | if (enable) |
| 499 | reg += OMAP24XX_GPIO_SETDATAOUT; | 498 | reg += OMAP24XX_GPIO_SETDATAOUT; |
| @@ -503,7 +502,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |||
| 503 | break; | 502 | break; |
| 504 | #endif | 503 | #endif |
| 505 | #ifdef CONFIG_ARCH_OMAP4 | 504 | #ifdef CONFIG_ARCH_OMAP4 |
| 506 | case METHOD_GPIO_24XX: | 505 | case METHOD_GPIO_44XX: |
| 507 | if (enable) | 506 | if (enable) |
| 508 | reg += OMAP4_GPIO_SETDATAOUT; | 507 | reg += OMAP4_GPIO_SETDATAOUT; |
| 509 | else | 508 | else |
| @@ -546,13 +545,13 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio) | |||
| 546 | reg += OMAP7XX_GPIO_DATA_INPUT; | 545 | reg += OMAP7XX_GPIO_DATA_INPUT; |
| 547 | break; | 546 | break; |
| 548 | #endif | 547 | #endif |
| 549 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 548 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 550 | case METHOD_GPIO_24XX: | 549 | case METHOD_GPIO_24XX: |
| 551 | reg += OMAP24XX_GPIO_DATAIN; | 550 | reg += OMAP24XX_GPIO_DATAIN; |
| 552 | break; | 551 | break; |
| 553 | #endif | 552 | #endif |
| 554 | #ifdef CONFIG_ARCH_OMAP4 | 553 | #ifdef CONFIG_ARCH_OMAP4 |
| 555 | case METHOD_GPIO_24XX: | 554 | case METHOD_GPIO_44XX: |
| 556 | reg += OMAP4_GPIO_DATAIN; | 555 | reg += OMAP4_GPIO_DATAIN; |
| 557 | break; | 556 | break; |
| 558 | #endif | 557 | #endif |
| @@ -592,9 +591,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) | |||
| 592 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | 591 | reg += OMAP7XX_GPIO_DATA_OUTPUT; |
| 593 | break; | 592 | break; |
| 594 | #endif | 593 | #endif |
| 595 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 594 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 596 | defined(CONFIG_ARCH_OMAP4) | ||
| 597 | case METHOD_GPIO_24XX: | 595 | case METHOD_GPIO_24XX: |
| 596 | case METHOD_GPIO_44XX: | ||
| 598 | reg += OMAP24XX_GPIO_DATAOUT; | 597 | reg += OMAP24XX_GPIO_DATAOUT; |
| 599 | break; | 598 | break; |
| 600 | #endif | 599 | #endif |
| @@ -625,11 +624,12 @@ void omap_set_gpio_debounce(int gpio, int enable) | |||
| 625 | 624 | ||
| 626 | bank = get_gpio_bank(gpio); | 625 | bank = get_gpio_bank(gpio); |
| 627 | reg = bank->base; | 626 | reg = bank->base; |
| 628 | #ifdef CONFIG_ARCH_OMAP4 | 627 | |
| 629 | reg += OMAP4_GPIO_DEBOUNCENABLE; | 628 | if (cpu_is_omap44xx()) |
| 630 | #else | 629 | reg += OMAP4_GPIO_DEBOUNCENABLE; |
| 631 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | 630 | else |
| 632 | #endif | 631 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; |
| 632 | |||
| 633 | if (!(bank->mod_usage & l)) { | 633 | if (!(bank->mod_usage & l)) { |
| 634 | printk(KERN_ERR "GPIO %d not requested\n", gpio); | 634 | printk(KERN_ERR "GPIO %d not requested\n", gpio); |
| 635 | return; | 635 | return; |
| @@ -675,17 +675,17 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time) | |||
| 675 | } | 675 | } |
| 676 | 676 | ||
| 677 | enc_time &= 0xff; | 677 | enc_time &= 0xff; |
| 678 | #ifdef CONFIG_ARCH_OMAP4 | 678 | |
| 679 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | 679 | if (cpu_is_omap44xx()) |
| 680 | #else | 680 | reg += OMAP4_GPIO_DEBOUNCINGTIME; |
| 681 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | 681 | else |
| 682 | #endif | 682 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; |
| 683 | |||
| 683 | __raw_writel(enc_time, reg); | 684 | __raw_writel(enc_time, reg); |
| 684 | } | 685 | } |
| 685 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | 686 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); |
| 686 | 687 | ||
| 687 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 688 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 688 | defined(CONFIG_ARCH_OMAP4) | ||
| 689 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, | 689 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
| 690 | int trigger) | 690 | int trigger) |
| 691 | { | 691 | { |
| @@ -856,9 +856,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
| 856 | goto bad; | 856 | goto bad; |
| 857 | break; | 857 | break; |
| 858 | #endif | 858 | #endif |
| 859 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 859 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 860 | defined(CONFIG_ARCH_OMAP4) | ||
| 861 | case METHOD_GPIO_24XX: | 860 | case METHOD_GPIO_24XX: |
| 861 | case METHOD_GPIO_44XX: | ||
| 862 | set_24xx_gpio_triggering(bank, gpio, trigger); | 862 | set_24xx_gpio_triggering(bank, gpio, trigger); |
| 863 | break; | 863 | break; |
| 864 | #endif | 864 | #endif |
| @@ -937,13 +937,13 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
| 937 | reg += OMAP7XX_GPIO_INT_STATUS; | 937 | reg += OMAP7XX_GPIO_INT_STATUS; |
| 938 | break; | 938 | break; |
| 939 | #endif | 939 | #endif |
| 940 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 940 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 941 | case METHOD_GPIO_24XX: | 941 | case METHOD_GPIO_24XX: |
| 942 | reg += OMAP24XX_GPIO_IRQSTATUS1; | 942 | reg += OMAP24XX_GPIO_IRQSTATUS1; |
| 943 | break; | 943 | break; |
| 944 | #endif | 944 | #endif |
| 945 | #if defined(CONFIG_ARCH_OMAP4) | 945 | #if defined(CONFIG_ARCH_OMAP4) |
| 946 | case METHOD_GPIO_24XX: | 946 | case METHOD_GPIO_44XX: |
| 947 | reg += OMAP4_GPIO_IRQSTATUS0; | 947 | reg += OMAP4_GPIO_IRQSTATUS0; |
| 948 | break; | 948 | break; |
| 949 | #endif | 949 | #endif |
| @@ -954,12 +954,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
| 954 | __raw_writel(gpio_mask, reg); | 954 | __raw_writel(gpio_mask, reg); |
| 955 | 955 | ||
| 956 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | 956 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ |
| 957 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 957 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
| 958 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | 958 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; |
| 959 | #endif | 959 | else if (cpu_is_omap44xx()) |
| 960 | #if defined(CONFIG_ARCH_OMAP4) | 960 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; |
| 961 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | 961 | |
| 962 | #endif | ||
| 963 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | 962 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
| 964 | __raw_writel(gpio_mask, reg); | 963 | __raw_writel(gpio_mask, reg); |
| 965 | 964 | ||
| @@ -1008,14 +1007,14 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | |||
| 1008 | inv = 1; | 1007 | inv = 1; |
| 1009 | break; | 1008 | break; |
| 1010 | #endif | 1009 | #endif |
| 1011 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1010 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 1012 | case METHOD_GPIO_24XX: | 1011 | case METHOD_GPIO_24XX: |
| 1013 | reg += OMAP24XX_GPIO_IRQENABLE1; | 1012 | reg += OMAP24XX_GPIO_IRQENABLE1; |
| 1014 | mask = 0xffffffff; | 1013 | mask = 0xffffffff; |
| 1015 | break; | 1014 | break; |
| 1016 | #endif | 1015 | #endif |
| 1017 | #if defined(CONFIG_ARCH_OMAP4) | 1016 | #if defined(CONFIG_ARCH_OMAP4) |
| 1018 | case METHOD_GPIO_24XX: | 1017 | case METHOD_GPIO_44XX: |
| 1019 | reg += OMAP4_GPIO_IRQSTATUSSET0; | 1018 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
| 1020 | mask = 0xffffffff; | 1019 | mask = 0xffffffff; |
| 1021 | break; | 1020 | break; |
| @@ -1077,7 +1076,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab | |||
| 1077 | l |= gpio_mask; | 1076 | l |= gpio_mask; |
| 1078 | break; | 1077 | break; |
| 1079 | #endif | 1078 | #endif |
| 1080 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1079 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 1081 | case METHOD_GPIO_24XX: | 1080 | case METHOD_GPIO_24XX: |
| 1082 | if (enable) | 1081 | if (enable) |
| 1083 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | 1082 | reg += OMAP24XX_GPIO_SETIRQENABLE1; |
| @@ -1087,7 +1086,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab | |||
| 1087 | break; | 1086 | break; |
| 1088 | #endif | 1087 | #endif |
| 1089 | #ifdef CONFIG_ARCH_OMAP4 | 1088 | #ifdef CONFIG_ARCH_OMAP4 |
| 1090 | case METHOD_GPIO_24XX: | 1089 | case METHOD_GPIO_44XX: |
| 1091 | if (enable) | 1090 | if (enable) |
| 1092 | reg += OMAP4_GPIO_IRQSTATUSSET0; | 1091 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
| 1093 | else | 1092 | else |
| @@ -1131,9 +1130,9 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |||
| 1131 | spin_unlock_irqrestore(&bank->lock, flags); | 1130 | spin_unlock_irqrestore(&bank->lock, flags); |
| 1132 | return 0; | 1131 | return 0; |
| 1133 | #endif | 1132 | #endif |
| 1134 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 1133 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 1135 | defined(CONFIG_ARCH_OMAP4) | ||
| 1136 | case METHOD_GPIO_24XX: | 1134 | case METHOD_GPIO_24XX: |
| 1135 | case METHOD_GPIO_44XX: | ||
| 1137 | if (bank->non_wakeup_gpios & (1 << gpio)) { | 1136 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
| 1138 | printk(KERN_ERR "Unable to modify wakeup on " | 1137 | printk(KERN_ERR "Unable to modify wakeup on " |
| 1139 | "non-wakeup GPIO%d\n", | 1138 | "non-wakeup GPIO%d\n", |
| @@ -1227,9 +1226,9 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
| 1227 | __raw_writel(1 << offset, reg); | 1226 | __raw_writel(1 << offset, reg); |
| 1228 | } | 1227 | } |
| 1229 | #endif | 1228 | #endif |
| 1230 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 1229 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 1231 | defined(CONFIG_ARCH_OMAP4) | 1230 | if ((bank->method == METHOD_GPIO_24XX) || |
| 1232 | if (bank->method == METHOD_GPIO_24XX) { | 1231 | (bank->method == METHOD_GPIO_44XX)) { |
| 1233 | /* Disable wake-up during idle for dynamic tick */ | 1232 | /* Disable wake-up during idle for dynamic tick */ |
| 1234 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | 1233 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
| 1235 | __raw_writel(1 << offset, reg); | 1234 | __raw_writel(1 << offset, reg); |
| @@ -1286,12 +1285,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 1286 | if (bank->method == METHOD_GPIO_7XX) | 1285 | if (bank->method == METHOD_GPIO_7XX) |
| 1287 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | 1286 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; |
| 1288 | #endif | 1287 | #endif |
| 1289 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1288 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 1290 | if (bank->method == METHOD_GPIO_24XX) | 1289 | if (bank->method == METHOD_GPIO_24XX) |
| 1291 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | 1290 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; |
| 1292 | #endif | 1291 | #endif |
| 1293 | #if defined(CONFIG_ARCH_OMAP4) | 1292 | #if defined(CONFIG_ARCH_OMAP4) |
| 1294 | if (bank->method == METHOD_GPIO_24XX) | 1293 | if (bank->method == METHOD_GPIO_44XX) |
| 1295 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; | 1294 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
| 1296 | #endif | 1295 | #endif |
| 1297 | while(1) { | 1296 | while(1) { |
| @@ -1571,6 +1570,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) | |||
| 1571 | reg += OMAP7XX_GPIO_DIR_CONTROL; | 1570 | reg += OMAP7XX_GPIO_DIR_CONTROL; |
| 1572 | break; | 1571 | break; |
| 1573 | case METHOD_GPIO_24XX: | 1572 | case METHOD_GPIO_24XX: |
| 1573 | case METHOD_GPIO_44XX: | ||
| 1574 | reg += OMAP24XX_GPIO_OE; | 1574 | reg += OMAP24XX_GPIO_OE; |
| 1575 | break; | 1575 | break; |
| 1576 | } | 1576 | } |
| @@ -1630,7 +1630,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset) | |||
| 1630 | /*---------------------------------------------------------------------*/ | 1630 | /*---------------------------------------------------------------------*/ |
| 1631 | 1631 | ||
| 1632 | static int initialized; | 1632 | static int initialized; |
| 1633 | #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)) | 1633 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) |
| 1634 | static struct clk * gpio_ick; | 1634 | static struct clk * gpio_ick; |
| 1635 | #endif | 1635 | #endif |
| 1636 | 1636 | ||
| @@ -1756,7 +1756,7 @@ static int __init _omap_gpio_init(void) | |||
| 1756 | bank_size = SZ_2K; | 1756 | bank_size = SZ_2K; |
| 1757 | } | 1757 | } |
| 1758 | #endif | 1758 | #endif |
| 1759 | #ifdef CONFIG_ARCH_OMAP24XX | 1759 | #ifdef CONFIG_ARCH_OMAP2 |
| 1760 | if (cpu_is_omap242x()) { | 1760 | if (cpu_is_omap242x()) { |
| 1761 | gpio_bank_count = 4; | 1761 | gpio_bank_count = 4; |
| 1762 | gpio_bank = gpio_bank_242x; | 1762 | gpio_bank = gpio_bank_242x; |
| @@ -1766,7 +1766,7 @@ static int __init _omap_gpio_init(void) | |||
| 1766 | gpio_bank = gpio_bank_243x; | 1766 | gpio_bank = gpio_bank_243x; |
| 1767 | } | 1767 | } |
| 1768 | #endif | 1768 | #endif |
| 1769 | #ifdef CONFIG_ARCH_OMAP34XX | 1769 | #ifdef CONFIG_ARCH_OMAP3 |
| 1770 | if (cpu_is_omap34xx()) { | 1770 | if (cpu_is_omap34xx()) { |
| 1771 | gpio_bank_count = OMAP34XX_NR_GPIOS; | 1771 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
| 1772 | gpio_bank = gpio_bank_34xx; | 1772 | gpio_bank = gpio_bank_34xx; |
| @@ -1809,30 +1809,42 @@ static int __init _omap_gpio_init(void) | |||
| 1809 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ | 1809 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ |
| 1810 | } | 1810 | } |
| 1811 | 1811 | ||
| 1812 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 1812 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 1813 | defined(CONFIG_ARCH_OMAP4) | 1813 | if ((bank->method == METHOD_GPIO_24XX) || |
| 1814 | if (bank->method == METHOD_GPIO_24XX) { | 1814 | (bank->method == METHOD_GPIO_44XX)) { |
| 1815 | static const u32 non_wakeup_gpios[] = { | 1815 | static const u32 non_wakeup_gpios[] = { |
| 1816 | 0xe203ffc0, 0x08700040 | 1816 | 0xe203ffc0, 0x08700040 |
| 1817 | }; | 1817 | }; |
| 1818 | if (cpu_is_omap44xx()) { | 1818 | |
| 1819 | __raw_writel(0xffffffff, bank->base + | 1819 | if (cpu_is_omap44xx()) { |
| 1820 | __raw_writel(0xffffffff, bank->base + | ||
| 1820 | OMAP4_GPIO_IRQSTATUSCLR0); | 1821 | OMAP4_GPIO_IRQSTATUSCLR0); |
| 1821 | __raw_writew(0x0015, bank->base + | 1822 | __raw_writew(0x0015, bank->base + |
| 1822 | OMAP4_GPIO_SYSCONFIG); | 1823 | OMAP4_GPIO_SYSCONFIG); |
| 1823 | __raw_writel(0x00000000, bank->base + | 1824 | __raw_writel(0x00000000, bank->base + |
| 1824 | OMAP4_GPIO_DEBOUNCENABLE); | 1825 | OMAP4_GPIO_DEBOUNCENABLE); |
| 1825 | /* Initialize interface clock ungated, module enabled */ | 1826 | /* |
| 1826 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | 1827 | * Initialize interface clock ungated, |
| 1827 | } else { | 1828 | * module enabled |
| 1828 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); | 1829 | */ |
| 1829 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | 1830 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); |
| 1830 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); | 1831 | } else { |
| 1831 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); | 1832 | __raw_writel(0x00000000, bank->base + |
| 1832 | 1833 | OMAP24XX_GPIO_IRQENABLE1); | |
| 1833 | /* Initialize interface clock ungated, module enabled */ | 1834 | __raw_writel(0xffffffff, bank->base + |
| 1834 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | 1835 | OMAP24XX_GPIO_IRQSTATUS1); |
| 1835 | } | 1836 | __raw_writew(0x0015, bank->base + |
| 1837 | OMAP24XX_GPIO_SYSCONFIG); | ||
| 1838 | __raw_writel(0x00000000, bank->base + | ||
| 1839 | OMAP24XX_GPIO_DEBOUNCE_EN); | ||
| 1840 | |||
| 1841 | /* | ||
| 1842 | * Initialize interface clock ungated, | ||
| 1843 | * module enabled | ||
| 1844 | */ | ||
| 1845 | __raw_writel(0, bank->base + | ||
| 1846 | OMAP24XX_GPIO_CTRL); | ||
| 1847 | } | ||
| 1836 | if (i < ARRAY_SIZE(non_wakeup_gpios)) | 1848 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
| 1837 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | 1849 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; |
| 1838 | gpio_count = 32; | 1850 | gpio_count = 32; |
| @@ -1903,8 +1915,7 @@ static int __init _omap_gpio_init(void) | |||
| 1903 | return 0; | 1915 | return 0; |
| 1904 | } | 1916 | } |
| 1905 | 1917 | ||
| 1906 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ | 1918 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
| 1907 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | ||
| 1908 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) | 1919 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
| 1909 | { | 1920 | { |
| 1910 | int i; | 1921 | int i; |
| @@ -1927,7 +1938,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) | |||
| 1927 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | 1938 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; |
| 1928 | break; | 1939 | break; |
| 1929 | #endif | 1940 | #endif |
| 1930 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1941 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 1931 | case METHOD_GPIO_24XX: | 1942 | case METHOD_GPIO_24XX: |
| 1932 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; | 1943 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
| 1933 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | 1944 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
| @@ -1935,7 +1946,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) | |||
| 1935 | break; | 1946 | break; |
| 1936 | #endif | 1947 | #endif |
| 1937 | #ifdef CONFIG_ARCH_OMAP4 | 1948 | #ifdef CONFIG_ARCH_OMAP4 |
| 1938 | case METHOD_GPIO_24XX: | 1949 | case METHOD_GPIO_44XX: |
| 1939 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; | 1950 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
| 1940 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | 1951 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
| 1941 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | 1952 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; |
| @@ -1975,14 +1986,14 @@ static int omap_gpio_resume(struct sys_device *dev) | |||
| 1975 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | 1986 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; |
| 1976 | break; | 1987 | break; |
| 1977 | #endif | 1988 | #endif |
| 1978 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1989 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 1979 | case METHOD_GPIO_24XX: | 1990 | case METHOD_GPIO_24XX: |
| 1980 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | 1991 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
| 1981 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | 1992 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; |
| 1982 | break; | 1993 | break; |
| 1983 | #endif | 1994 | #endif |
| 1984 | #ifdef CONFIG_ARCH_OMAP4 | 1995 | #ifdef CONFIG_ARCH_OMAP4 |
| 1985 | case METHOD_GPIO_24XX: | 1996 | case METHOD_GPIO_44XX: |
| 1986 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | 1997 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
| 1987 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | 1998 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; |
| 1988 | break; | 1999 | break; |
| @@ -2013,8 +2024,7 @@ static struct sys_device omap_gpio_device = { | |||
| 2013 | 2024 | ||
| 2014 | #endif | 2025 | #endif |
| 2015 | 2026 | ||
| 2016 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 2027 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 2017 | defined(CONFIG_ARCH_OMAP4) | ||
| 2018 | 2028 | ||
| 2019 | static int workaround_enabled; | 2029 | static int workaround_enabled; |
| 2020 | 2030 | ||
| @@ -2030,29 +2040,42 @@ void omap2_gpio_prepare_for_retention(void) | |||
| 2030 | 2040 | ||
| 2031 | if (!(bank->enabled_non_wakeup_gpios)) | 2041 | if (!(bank->enabled_non_wakeup_gpios)) |
| 2032 | continue; | 2042 | continue; |
| 2033 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 2043 | |
| 2034 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); | 2044 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 2035 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | 2045 | bank->saved_datain = __raw_readl(bank->base + |
| 2036 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | 2046 | OMAP24XX_GPIO_DATAIN); |
| 2037 | #endif | 2047 | l1 = __raw_readl(bank->base + |
| 2038 | #ifdef CONFIG_ARCH_OMAP4 | 2048 | OMAP24XX_GPIO_FALLINGDETECT); |
| 2039 | bank->saved_datain = __raw_readl(bank->base + | 2049 | l2 = __raw_readl(bank->base + |
| 2040 | OMAP4_GPIO_DATAIN); | 2050 | OMAP24XX_GPIO_RISINGDETECT); |
| 2041 | l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT); | 2051 | } |
| 2042 | l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT); | 2052 | |
| 2043 | #endif | 2053 | if (cpu_is_omap44xx()) { |
| 2054 | bank->saved_datain = __raw_readl(bank->base + | ||
| 2055 | OMAP4_GPIO_DATAIN); | ||
| 2056 | l1 = __raw_readl(bank->base + | ||
| 2057 | OMAP4_GPIO_FALLINGDETECT); | ||
| 2058 | l2 = __raw_readl(bank->base + | ||
| 2059 | OMAP4_GPIO_RISINGDETECT); | ||
| 2060 | } | ||
| 2061 | |||
| 2044 | bank->saved_fallingdetect = l1; | 2062 | bank->saved_fallingdetect = l1; |
| 2045 | bank->saved_risingdetect = l2; | 2063 | bank->saved_risingdetect = l2; |
| 2046 | l1 &= ~bank->enabled_non_wakeup_gpios; | 2064 | l1 &= ~bank->enabled_non_wakeup_gpios; |
| 2047 | l2 &= ~bank->enabled_non_wakeup_gpios; | 2065 | l2 &= ~bank->enabled_non_wakeup_gpios; |
| 2048 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 2066 | |
| 2049 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); | 2067 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 2050 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | 2068 | __raw_writel(l1, bank->base + |
| 2051 | #endif | 2069 | OMAP24XX_GPIO_FALLINGDETECT); |
| 2052 | #ifdef CONFIG_ARCH_OMAP4 | 2070 | __raw_writel(l2, bank->base + |
| 2053 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | 2071 | OMAP24XX_GPIO_RISINGDETECT); |
| 2054 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | 2072 | } |
| 2055 | #endif | 2073 | |
| 2074 | if (cpu_is_omap44xx()) { | ||
| 2075 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | ||
| 2076 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | ||
| 2077 | } | ||
| 2078 | |||
| 2056 | c++; | 2079 | c++; |
| 2057 | } | 2080 | } |
| 2058 | if (!c) { | 2081 | if (!c) { |
| @@ -2074,20 +2097,23 @@ void omap2_gpio_resume_after_retention(void) | |||
| 2074 | 2097 | ||
| 2075 | if (!(bank->enabled_non_wakeup_gpios)) | 2098 | if (!(bank->enabled_non_wakeup_gpios)) |
| 2076 | continue; | 2099 | continue; |
| 2077 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 2100 | |
| 2078 | __raw_writel(bank->saved_fallingdetect, | 2101 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 2102 | __raw_writel(bank->saved_fallingdetect, | ||
| 2079 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | 2103 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
| 2080 | __raw_writel(bank->saved_risingdetect, | 2104 | __raw_writel(bank->saved_risingdetect, |
| 2081 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | 2105 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
| 2082 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); | 2106 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
| 2083 | #endif | 2107 | } |
| 2084 | #ifdef CONFIG_ARCH_OMAP4 | 2108 | |
| 2085 | __raw_writel(bank->saved_fallingdetect, | 2109 | if (cpu_is_omap44xx()) { |
| 2110 | __raw_writel(bank->saved_fallingdetect, | ||
| 2086 | bank->base + OMAP4_GPIO_FALLINGDETECT); | 2111 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
| 2087 | __raw_writel(bank->saved_risingdetect, | 2112 | __raw_writel(bank->saved_risingdetect, |
| 2088 | bank->base + OMAP4_GPIO_RISINGDETECT); | 2113 | bank->base + OMAP4_GPIO_RISINGDETECT); |
| 2089 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); | 2114 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
| 2090 | #endif | 2115 | } |
| 2116 | |||
| 2091 | /* Check if any of the non-wakeup interrupt GPIOs have changed | 2117 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
| 2092 | * state. If so, generate an IRQ by software. This is | 2118 | * state. If so, generate an IRQ by software. This is |
| 2093 | * horribly racy, but it's the best we can do to work around | 2119 | * horribly racy, but it's the best we can do to work around |
| @@ -2113,30 +2139,36 @@ void omap2_gpio_resume_after_retention(void) | |||
| 2113 | 2139 | ||
| 2114 | if (gen) { | 2140 | if (gen) { |
| 2115 | u32 old0, old1; | 2141 | u32 old0, old1; |
| 2116 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 2142 | |
| 2117 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | 2143 | if (cpu_is_omap24xx() || cpu_is_omap44xx()) { |
| 2118 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | 2144 | old0 = __raw_readl(bank->base + |
| 2145 | OMAP24XX_GPIO_LEVELDETECT0); | ||
| 2146 | old1 = __raw_readl(bank->base + | ||
| 2147 | OMAP24XX_GPIO_LEVELDETECT1); | ||
| 2119 | __raw_writel(old0 | gen, bank->base + | 2148 | __raw_writel(old0 | gen, bank->base + |
| 2120 | OMAP24XX_GPIO_LEVELDETECT0); | 2149 | OMAP24XX_GPIO_LEVELDETECT0); |
| 2121 | __raw_writel(old1 | gen, bank->base + | 2150 | __raw_writel(old1 | gen, bank->base + |
| 2122 | OMAP24XX_GPIO_LEVELDETECT1); | 2151 | OMAP24XX_GPIO_LEVELDETECT1); |
| 2123 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | 2152 | __raw_writel(old0, bank->base + |
| 2124 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | 2153 | OMAP24XX_GPIO_LEVELDETECT0); |
| 2125 | #endif | 2154 | __raw_writel(old1, bank->base + |
| 2126 | #ifdef CONFIG_ARCH_OMAP4 | 2155 | OMAP24XX_GPIO_LEVELDETECT1); |
| 2127 | old0 = __raw_readl(bank->base + | 2156 | } |
| 2157 | |||
| 2158 | if (cpu_is_omap44xx()) { | ||
| 2159 | old0 = __raw_readl(bank->base + | ||
| 2128 | OMAP4_GPIO_LEVELDETECT0); | 2160 | OMAP4_GPIO_LEVELDETECT0); |
| 2129 | old1 = __raw_readl(bank->base + | 2161 | old1 = __raw_readl(bank->base + |
| 2130 | OMAP4_GPIO_LEVELDETECT1); | 2162 | OMAP4_GPIO_LEVELDETECT1); |
| 2131 | __raw_writel(old0 | l, bank->base + | 2163 | __raw_writel(old0 | l, bank->base + |
| 2132 | OMAP4_GPIO_LEVELDETECT0); | 2164 | OMAP4_GPIO_LEVELDETECT0); |
| 2133 | __raw_writel(old1 | l, bank->base + | 2165 | __raw_writel(old1 | l, bank->base + |
| 2134 | OMAP4_GPIO_LEVELDETECT1); | 2166 | OMAP4_GPIO_LEVELDETECT1); |
| 2135 | __raw_writel(old0, bank->base + | 2167 | __raw_writel(old0, bank->base + |
| 2136 | OMAP4_GPIO_LEVELDETECT0); | 2168 | OMAP4_GPIO_LEVELDETECT0); |
| 2137 | __raw_writel(old1, bank->base + | 2169 | __raw_writel(old1, bank->base + |
| 2138 | OMAP4_GPIO_LEVELDETECT1); | 2170 | OMAP4_GPIO_LEVELDETECT1); |
| 2139 | #endif | 2171 | } |
| 2140 | } | 2172 | } |
| 2141 | } | 2173 | } |
| 2142 | 2174 | ||
| @@ -2144,7 +2176,7 @@ void omap2_gpio_resume_after_retention(void) | |||
| 2144 | 2176 | ||
| 2145 | #endif | 2177 | #endif |
| 2146 | 2178 | ||
| 2147 | #ifdef CONFIG_ARCH_OMAP34XX | 2179 | #ifdef CONFIG_ARCH_OMAP3 |
| 2148 | /* save the registers of bank 2-6 */ | 2180 | /* save the registers of bank 2-6 */ |
| 2149 | void omap_gpio_save_context(void) | 2181 | void omap_gpio_save_context(void) |
| 2150 | { | 2182 | { |
| @@ -2240,8 +2272,7 @@ static int __init omap_gpio_sysinit(void) | |||
| 2240 | 2272 | ||
| 2241 | mpuio_init(); | 2273 | mpuio_init(); |
| 2242 | 2274 | ||
| 2243 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ | 2275 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
| 2244 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | ||
| 2245 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | 2276 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
| 2246 | if (ret == 0) { | 2277 | if (ret == 0) { |
| 2247 | ret = sysdev_class_register(&omap_gpio_sysclass); | 2278 | ret = sysdev_class_register(&omap_gpio_sysclass); |
| @@ -2300,8 +2331,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
| 2300 | /* FIXME for at least omap2, show pullup/pulldown state */ | 2331 | /* FIXME for at least omap2, show pullup/pulldown state */ |
| 2301 | 2332 | ||
| 2302 | irqstat = irq_desc[irq].status; | 2333 | irqstat = irq_desc[irq].status; |
| 2303 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ | 2334 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
| 2304 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | ||
| 2305 | if (is_in && ((bank->suspend_wakeup & mask) | 2335 | if (is_in && ((bank->suspend_wakeup & mask) |
| 2306 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | 2336 | || irqstat & IRQ_TYPE_SENSE_MASK)) { |
| 2307 | char *trigger = NULL; | 2337 | char *trigger = NULL; |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 33fff4ef382d..624e26298faa 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <linux/i2c.h> | 28 | #include <linux/i2c.h> |
| 29 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
| 30 | #include <plat/mux.h> | 30 | #include <plat/mux.h> |
| 31 | #include <plat/i2c.h> | ||
| 31 | 32 | ||
| 32 | #define OMAP_I2C_SIZE 0x3f | 33 | #define OMAP_I2C_SIZE 0x3f |
| 33 | #define OMAP1_I2C_BASE 0xfffb3800 | 34 | #define OMAP1_I2C_BASE 0xfffb3800 |
| @@ -50,10 +51,10 @@ static const char name[] = "i2c_omap"; | |||
| 50 | 51 | ||
| 51 | static struct resource i2c_resources[][2] = { | 52 | static struct resource i2c_resources[][2] = { |
| 52 | { I2C_RESOURCE_BUILDER(0, 0) }, | 53 | { I2C_RESOURCE_BUILDER(0, 0) }, |
| 53 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 54 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 54 | { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) }, | 55 | { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) }, |
| 55 | #endif | 56 | #endif |
| 56 | #if defined(CONFIG_ARCH_OMAP34XX) | 57 | #if defined(CONFIG_ARCH_OMAP3) |
| 57 | { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) }, | 58 | { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) }, |
| 58 | #endif | 59 | #endif |
| 59 | }; | 60 | }; |
| @@ -72,10 +73,10 @@ static struct resource i2c_resources[][2] = { | |||
| 72 | static u32 i2c_rate[ARRAY_SIZE(i2c_resources)]; | 73 | static u32 i2c_rate[ARRAY_SIZE(i2c_resources)]; |
| 73 | static struct platform_device omap_i2c_devices[] = { | 74 | static struct platform_device omap_i2c_devices[] = { |
| 74 | I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]), | 75 | I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]), |
| 75 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 76 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 76 | I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]), | 77 | I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]), |
| 77 | #endif | 78 | #endif |
| 78 | #if defined(CONFIG_ARCH_OMAP34XX) | 79 | #if defined(CONFIG_ARCH_OMAP3) |
| 79 | I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]), | 80 | I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]), |
| 80 | #endif | 81 | #endif |
| 81 | }; | 82 | }; |
| @@ -117,6 +118,11 @@ static int __init omap_i2c_add_bus(int bus_id) | |||
| 117 | res[1].start = irq; | 118 | res[1].start = irq; |
| 118 | } | 119 | } |
| 119 | 120 | ||
| 121 | if (cpu_class_is_omap1()) | ||
| 122 | omap1_i2c_mux_pins(bus_id); | ||
| 123 | if (cpu_class_is_omap2()) | ||
| 124 | omap2_i2c_mux_pins(bus_id); | ||
| 125 | |||
| 120 | return platform_device_register(pdev); | 126 | return platform_device_register(pdev); |
| 121 | } | 127 | } |
| 122 | 128 | ||
| @@ -169,7 +175,7 @@ out: | |||
| 169 | subsys_initcall(omap_register_i2c_bus_cmdline); | 175 | subsys_initcall(omap_register_i2c_bus_cmdline); |
| 170 | 176 | ||
| 171 | /** | 177 | /** |
| 172 | * omap_plat_register_i2c_bus - register I2C bus with device descriptors | 178 | * omap_register_i2c_bus - register I2C bus with device descriptors |
| 173 | * @bus_id: bus id counting from number 1 | 179 | * @bus_id: bus id counting from number 1 |
| 174 | * @clkrate: clock rate of the bus in kHz | 180 | * @clkrate: clock rate of the bus in kHz |
| 175 | * @info: pointer into I2C device descriptor table or NULL | 181 | * @info: pointer into I2C device descriptor table or NULL |
| @@ -177,7 +183,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline); | |||
| 177 | * | 183 | * |
| 178 | * Returns 0 on success or an error code. | 184 | * Returns 0 on success or an error code. |
| 179 | */ | 185 | */ |
| 180 | int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate, | 186 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, |
| 181 | struct i2c_board_info const *info, | 187 | struct i2c_board_info const *info, |
| 182 | unsigned len) | 188 | unsigned len) |
| 183 | { | 189 | { |
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 35b36caf5f91..bb937f3fabed 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h | |||
| @@ -25,17 +25,25 @@ struct omap_clk { | |||
| 25 | }, \ | 25 | }, \ |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | 28 | /* Platform flags for the clkdev-OMAP integration code */ | |
| 29 | #define CK_310 (1 << 0) | 29 | #define CK_310 (1 << 0) |
| 30 | #define CK_7XX (1 << 1) | 30 | #define CK_7XX (1 << 1) /* 7xx, 850 */ |
| 31 | #define CK_1510 (1 << 2) | 31 | #define CK_1510 (1 << 2) |
| 32 | #define CK_16XX (1 << 3) | 32 | #define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ |
| 33 | #define CK_243X (1 << 4) | 33 | #define CK_242X (1 << 4) |
| 34 | #define CK_242X (1 << 5) | 34 | #define CK_243X (1 << 5) |
| 35 | #define CK_343X (1 << 6) | 35 | #define CK_3XXX (1 << 6) /* OMAP3 + AM3 common clocks*/ |
| 36 | #define CK_3430ES1 (1 << 7) | 36 | #define CK_343X (1 << 7) /* OMAP34xx common clocks */ |
| 37 | #define CK_3430ES2 (1 << 8) | 37 | #define CK_3430ES1 (1 << 8) /* 34xxES1 only */ |
| 38 | #define CK_443X (1 << 9) | 38 | #define CK_3430ES2 (1 << 9) /* 34xxES2, ES3, non-Sitara 35xx only */ |
| 39 | #define CK_3505 (1 << 10) | ||
| 40 | #define CK_3517 (1 << 11) | ||
| 41 | #define CK_36XX (1 << 12) /* OMAP36xx/37xx-specific clocks */ | ||
| 42 | #define CK_443X (1 << 13) | ||
| 43 | |||
| 44 | #define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ | ||
| 45 | |||
| 46 | |||
| 39 | 47 | ||
| 40 | #endif | 48 | #endif |
| 41 | 49 | ||
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 94fe2a0ce40a..34f7fa9ad4c0 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/clock.h | 2 | * OMAP clock: data structure definitions, function prototypes, shared macros |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2004 - 2005 Nokia corporation | 4 | * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation |
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| @@ -22,12 +22,13 @@ struct clockdomain; | |||
| 22 | struct clkops { | 22 | struct clkops { |
| 23 | int (*enable)(struct clk *); | 23 | int (*enable)(struct clk *); |
| 24 | void (*disable)(struct clk *); | 24 | void (*disable)(struct clk *); |
| 25 | void (*find_idlest)(struct clk *, void __iomem **, u8 *); | 25 | void (*find_idlest)(struct clk *, void __iomem **, |
| 26 | void (*find_companion)(struct clk *, void __iomem **, u8 *); | 26 | u8 *, u8 *); |
| 27 | void (*find_companion)(struct clk *, void __iomem **, | ||
| 28 | u8 *); | ||
| 27 | }; | 29 | }; |
| 28 | 30 | ||
| 29 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 31 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 30 | defined(CONFIG_ARCH_OMAP4) | ||
| 31 | 32 | ||
| 32 | struct clksel_rate { | 33 | struct clksel_rate { |
| 33 | u32 val; | 34 | u32 val; |
| @@ -40,6 +41,50 @@ struct clksel { | |||
| 40 | const struct clksel_rate *rates; | 41 | const struct clksel_rate *rates; |
| 41 | }; | 42 | }; |
| 42 | 43 | ||
| 44 | /** | ||
| 45 | * struct dpll_data - DPLL registers and integration data | ||
| 46 | * @mult_div1_reg: register containing the DPLL M and N bitfields | ||
| 47 | * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg | ||
| 48 | * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg | ||
| 49 | * @clk_bypass: struct clk pointer to the clock's bypass clock input | ||
| 50 | * @clk_ref: struct clk pointer to the clock's reference clock input | ||
| 51 | * @control_reg: register containing the DPLL mode bitfield | ||
| 52 | * @enable_mask: mask of the DPLL mode bitfield in @control_reg | ||
| 53 | * @rate_tolerance: maximum variance allowed from target rate (in Hz) | ||
| 54 | * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() | ||
| 55 | * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() | ||
| 56 | * @max_multiplier: maximum valid non-bypass multiplier value (actual) | ||
| 57 | * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() | ||
| 58 | * @min_divider: minimum valid non-bypass divider value (actual) | ||
| 59 | * @max_divider: maximum valid non-bypass divider value (actual) | ||
| 60 | * @modes: possible values of @enable_mask | ||
| 61 | * @autoidle_reg: register containing the DPLL autoidle mode bitfield | ||
| 62 | * @idlest_reg: register containing the DPLL idle status bitfield | ||
| 63 | * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg | ||
| 64 | * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg | ||
| 65 | * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg | ||
| 66 | * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg | ||
| 67 | * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs | ||
| 68 | * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs | ||
| 69 | * @flags: DPLL type/features (see below) | ||
| 70 | * | ||
| 71 | * Possible values for @flags: | ||
| 72 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) | ||
| 73 | * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs) | ||
| 74 | |||
| 75 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. | ||
| 76 | * | ||
| 77 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically | ||
| 78 | * correct to only have one @clk_bypass pointer. | ||
| 79 | * | ||
| 80 | * XXX @rate_tolerance should probably be deprecated - currently there | ||
| 81 | * don't seem to be any usecases for DPLL rounding that is not exact. | ||
| 82 | * | ||
| 83 | * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, | ||
| 84 | * @last_rounded_n) should be separated from the runtime-fixed fields | ||
| 85 | * and placed into a differenct structure, so that the runtime-fixed data | ||
| 86 | * can be placed into read-only space. | ||
| 87 | */ | ||
| 43 | struct dpll_data { | 88 | struct dpll_data { |
| 44 | void __iomem *mult_div1_reg; | 89 | void __iomem *mult_div1_reg; |
| 45 | u32 mult_mask; | 90 | u32 mult_mask; |
| @@ -51,13 +96,12 @@ struct dpll_data { | |||
| 51 | unsigned int rate_tolerance; | 96 | unsigned int rate_tolerance; |
| 52 | unsigned long last_rounded_rate; | 97 | unsigned long last_rounded_rate; |
| 53 | u16 last_rounded_m; | 98 | u16 last_rounded_m; |
| 99 | u16 max_multiplier; | ||
| 54 | u8 last_rounded_n; | 100 | u8 last_rounded_n; |
| 55 | u8 min_divider; | 101 | u8 min_divider; |
| 56 | u8 max_divider; | 102 | u8 max_divider; |
| 57 | u32 max_tolerance; | ||
| 58 | u16 max_multiplier; | ||
| 59 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 60 | u8 modes; | 103 | u8 modes; |
| 104 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 61 | void __iomem *autoidle_reg; | 105 | void __iomem *autoidle_reg; |
| 62 | void __iomem *idlest_reg; | 106 | void __iomem *idlest_reg; |
| 63 | u32 autoidle_mask; | 107 | u32 autoidle_mask; |
| @@ -66,6 +110,7 @@ struct dpll_data { | |||
| 66 | u8 auto_recal_bit; | 110 | u8 auto_recal_bit; |
| 67 | u8 recal_en_bit; | 111 | u8 recal_en_bit; |
| 68 | u8 recal_st_bit; | 112 | u8 recal_st_bit; |
| 113 | u8 flags; | ||
| 69 | # endif | 114 | # endif |
| 70 | }; | 115 | }; |
| 71 | 116 | ||
| @@ -75,12 +120,10 @@ struct clk { | |||
| 75 | struct list_head node; | 120 | struct list_head node; |
| 76 | const struct clkops *ops; | 121 | const struct clkops *ops; |
| 77 | const char *name; | 122 | const char *name; |
| 78 | int id; | ||
| 79 | struct clk *parent; | 123 | struct clk *parent; |
| 80 | struct list_head children; | 124 | struct list_head children; |
| 81 | struct list_head sibling; /* node for children */ | 125 | struct list_head sibling; /* node for children */ |
| 82 | unsigned long rate; | 126 | unsigned long rate; |
| 83 | __u32 flags; | ||
| 84 | void __iomem *enable_reg; | 127 | void __iomem *enable_reg; |
| 85 | unsigned long (*recalc)(struct clk *); | 128 | unsigned long (*recalc)(struct clk *); |
| 86 | int (*set_rate)(struct clk *, unsigned long); | 129 | int (*set_rate)(struct clk *, unsigned long); |
| @@ -88,9 +131,9 @@ struct clk { | |||
| 88 | void (*init)(struct clk *); | 131 | void (*init)(struct clk *); |
| 89 | __u8 enable_bit; | 132 | __u8 enable_bit; |
| 90 | __s8 usecount; | 133 | __s8 usecount; |
| 91 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | ||
| 92 | defined(CONFIG_ARCH_OMAP4) | ||
| 93 | u8 fixed_div; | 134 | u8 fixed_div; |
| 135 | u8 flags; | ||
| 136 | #ifdef CONFIG_ARCH_OMAP2PLUS | ||
| 94 | void __iomem *clksel_reg; | 137 | void __iomem *clksel_reg; |
| 95 | u32 clksel_mask; | 138 | u32 clksel_mask; |
| 96 | const struct clksel *clksel; | 139 | const struct clksel *clksel; |
| @@ -123,7 +166,7 @@ struct clk_functions { | |||
| 123 | #endif | 166 | #endif |
| 124 | }; | 167 | }; |
| 125 | 168 | ||
| 126 | extern unsigned int mpurate; | 169 | extern int mpurate; |
| 127 | 170 | ||
| 128 | extern int clk_init(struct clk_functions *custom_clocks); | 171 | extern int clk_init(struct clk_functions *custom_clocks); |
| 129 | extern void clk_preinit(struct clk *clk); | 172 | extern void clk_preinit(struct clk *clk); |
| @@ -134,27 +177,23 @@ extern void propagate_rate(struct clk *clk); | |||
| 134 | extern void recalculate_root_clocks(void); | 177 | extern void recalculate_root_clocks(void); |
| 135 | extern unsigned long followparent_recalc(struct clk *clk); | 178 | extern unsigned long followparent_recalc(struct clk *clk); |
| 136 | extern void clk_enable_init_clocks(void); | 179 | extern void clk_enable_init_clocks(void); |
| 180 | unsigned long omap_fixed_divisor_recalc(struct clk *clk); | ||
| 137 | #ifdef CONFIG_CPU_FREQ | 181 | #ifdef CONFIG_CPU_FREQ |
| 138 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); | 182 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); |
| 139 | extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); | 183 | extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); |
| 140 | #endif | 184 | #endif |
| 185 | extern struct clk *omap_clk_get_by_name(const char *name); | ||
| 141 | 186 | ||
| 142 | extern const struct clkops clkops_null; | 187 | extern const struct clkops clkops_null; |
| 143 | 188 | ||
| 189 | extern struct clk dummy_ck; | ||
| 190 | |||
| 144 | /* Clock flags */ | 191 | /* Clock flags */ |
| 145 | /* bit 0 is free */ | 192 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
| 146 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ | 193 | #define CLOCK_IDLE_CONTROL (1 << 1) |
| 147 | /* bits 2-4 are free */ | 194 | #define CLOCK_NO_IDLE_PARENT (1 << 2) |
| 148 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ | 195 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
| 149 | #define CLOCK_IDLE_CONTROL (1 << 7) | 196 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
| 150 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | ||
| 151 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | ||
| 152 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | ||
| 153 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ | ||
| 154 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | ||
| 155 | #define CLOCK_IN_OMAP4430 (1 << 13) | ||
| 156 | #define ALWAYS_ENABLED (1 << 14) | ||
| 157 | /* bits 13-31 are currently free */ | ||
| 158 | 197 | ||
| 159 | /* Clksel_rate flags */ | 198 | /* Clksel_rate flags */ |
| 160 | #define DEFAULT_RATE (1 << 0) | 199 | #define DEFAULT_RATE (1 << 0) |
| @@ -162,7 +201,8 @@ extern const struct clkops clkops_null; | |||
| 162 | #define RATE_IN_243X (1 << 2) | 201 | #define RATE_IN_243X (1 << 2) |
| 163 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | 202 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ |
| 164 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | 203 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ |
| 165 | #define RATE_IN_4430 (1 << 5) | 204 | #define RATE_IN_36XX (1 << 5) |
| 205 | #define RATE_IN_4430 (1 << 6) | ||
| 166 | 206 | ||
| 167 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 207 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
| 168 | 208 | ||
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index eb734826e64e..ba0a6c07c0fe 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * OMAP2/3 clockdomain framework functions | 4 | * OMAP2/3 clockdomain framework functions |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. | 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2008 Nokia Corporation | 7 | * Copyright (C) 2008-2009 Nokia Corporation |
| 8 | * | 8 | * |
| 9 | * Written by Paul Walmsley | 9 | * Written by Paul Walmsley |
| 10 | * | 10 | * |
| @@ -40,65 +40,95 @@ | |||
| 40 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | 40 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 |
| 41 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | 41 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 |
| 42 | 42 | ||
| 43 | /* | 43 | /** |
| 44 | * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps | 44 | * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode |
| 45 | * and sleepdeps added when a powerdomain should stay active in hwsup mode; | 45 | * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only |
| 46 | * and conversely, removed when the powerdomain should be allowed to go | 46 | * @omap_chip: OMAP chip types that this autodep is valid on |
| 47 | * inactive in hwsup mode. | 47 | * |
| 48 | * A clockdomain that should have wkdeps and sleepdeps added when a | ||
| 49 | * clockdomain should stay active in hwsup mode; and conversely, | ||
| 50 | * removed when the clockdomain should be allowed to go inactive in | ||
| 51 | * hwsup mode. | ||
| 52 | * | ||
| 53 | * Autodeps are deprecated and should be removed after | ||
| 54 | * omap_hwmod-based fine-grained module idle control is added. | ||
| 48 | */ | 55 | */ |
| 49 | struct clkdm_pwrdm_autodep { | 56 | struct clkdm_autodep { |
| 50 | |||
| 51 | union { | 57 | union { |
| 52 | /* Name of the powerdomain to add a wkdep/sleepdep on */ | ||
| 53 | const char *name; | 58 | const char *name; |
| 54 | 59 | struct clockdomain *ptr; | |
| 55 | /* Powerdomain pointer (looked up at clkdm_init() time) */ | 60 | } clkdm; |
| 56 | struct powerdomain *ptr; | ||
| 57 | } pwrdm; | ||
| 58 | |||
| 59 | /* OMAP chip types that this clockdomain dep is valid on */ | ||
| 60 | const struct omap_chip_id omap_chip; | 61 | const struct omap_chip_id omap_chip; |
| 62 | }; | ||
| 61 | 63 | ||
| 64 | /** | ||
| 65 | * struct clkdm_dep - encode dependencies between clockdomains | ||
| 66 | * @clkdm_name: clockdomain name | ||
| 67 | * @clkdm: pointer to the struct clockdomain of @clkdm_name | ||
| 68 | * @omap_chip: OMAP chip types that this dependency is valid on | ||
| 69 | * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake | ||
| 70 | * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle | ||
| 71 | * | ||
| 72 | * Statically defined. @clkdm is resolved from @clkdm_name at runtime and | ||
| 73 | * should not be pre-initialized. | ||
| 74 | * | ||
| 75 | * XXX Should also include hardware (fixed) dependencies. | ||
| 76 | */ | ||
| 77 | struct clkdm_dep { | ||
| 78 | const char *clkdm_name; | ||
| 79 | struct clockdomain *clkdm; | ||
| 80 | atomic_t wkdep_usecount; | ||
| 81 | atomic_t sleepdep_usecount; | ||
| 82 | const struct omap_chip_id omap_chip; | ||
| 62 | }; | 83 | }; |
| 63 | 84 | ||
| 85 | /** | ||
| 86 | * struct clockdomain - OMAP clockdomain | ||
| 87 | * @name: clockdomain name | ||
| 88 | * @pwrdm: powerdomain containing this clockdomain | ||
| 89 | * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain | ||
| 90 | * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg | ||
| 91 | * @flags: Clockdomain capability flags | ||
| 92 | * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit | ||
| 93 | * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up | ||
| 94 | * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact | ||
| 95 | * @omap_chip: OMAP chip types that this clockdomain is valid on | ||
| 96 | * @usecount: Usecount tracking | ||
| 97 | * @node: list_head to link all clockdomains together | ||
| 98 | */ | ||
| 64 | struct clockdomain { | 99 | struct clockdomain { |
| 65 | |||
| 66 | /* Clockdomain name */ | ||
| 67 | const char *name; | 100 | const char *name; |
| 68 | |||
| 69 | union { | 101 | union { |
| 70 | /* Powerdomain enclosing this clockdomain */ | ||
| 71 | const char *name; | 102 | const char *name; |
| 72 | |||
| 73 | /* Powerdomain pointer assigned at clkdm_register() */ | ||
| 74 | struct powerdomain *ptr; | 103 | struct powerdomain *ptr; |
| 75 | } pwrdm; | 104 | } pwrdm; |
| 76 | 105 | void __iomem *clkstctrl_reg; | |
| 77 | /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ | ||
| 78 | const u16 clktrctrl_mask; | 106 | const u16 clktrctrl_mask; |
| 79 | |||
| 80 | /* Clockdomain capability flags */ | ||
| 81 | const u8 flags; | 107 | const u8 flags; |
| 82 | 108 | const u8 dep_bit; | |
| 83 | /* OMAP chip types that this clockdomain is valid on */ | 109 | struct clkdm_dep *wkdep_srcs; |
| 110 | struct clkdm_dep *sleepdep_srcs; | ||
| 84 | const struct omap_chip_id omap_chip; | 111 | const struct omap_chip_id omap_chip; |
| 85 | |||
| 86 | /* Usecount tracking */ | ||
| 87 | atomic_t usecount; | 112 | atomic_t usecount; |
| 88 | |||
| 89 | struct list_head node; | 113 | struct list_head node; |
| 90 | |||
| 91 | }; | 114 | }; |
| 92 | 115 | ||
| 93 | void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps); | 116 | void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); |
| 94 | int clkdm_register(struct clockdomain *clkdm); | ||
| 95 | int clkdm_unregister(struct clockdomain *clkdm); | ||
| 96 | struct clockdomain *clkdm_lookup(const char *name); | 117 | struct clockdomain *clkdm_lookup(const char *name); |
| 97 | 118 | ||
| 98 | int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), | 119 | int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), |
| 99 | void *user); | 120 | void *user); |
| 100 | struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); | 121 | struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); |
| 101 | 122 | ||
| 123 | int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); | ||
| 124 | int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); | ||
| 125 | int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); | ||
| 126 | int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); | ||
| 127 | int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); | ||
| 128 | int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); | ||
| 129 | int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); | ||
| 130 | int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); | ||
| 131 | |||
| 102 | void omap2_clkdm_allow_idle(struct clockdomain *clkdm); | 132 | void omap2_clkdm_allow_idle(struct clockdomain *clkdm); |
| 103 | void omap2_clkdm_deny_idle(struct clockdomain *clkdm); | 133 | void omap2_clkdm_deny_idle(struct clockdomain *clkdm); |
| 104 | 134 | ||
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 32c22272425d..7556e271942e 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h | |||
| @@ -37,21 +37,30 @@ extern void __iomem *gic_cpu_base_addr; | |||
| 37 | extern void omap_map_common_io(void); | 37 | extern void omap_map_common_io(void); |
| 38 | extern struct sys_timer omap_timer; | 38 | extern struct sys_timer omap_timer; |
| 39 | 39 | ||
| 40 | /* IO bases for various OMAP processors */ | 40 | /* |
| 41 | * IO bases for various OMAP processors | ||
| 42 | * Except the tap base, rest all the io bases | ||
| 43 | * listed are physical addresses. | ||
| 44 | */ | ||
| 41 | struct omap_globals { | 45 | struct omap_globals { |
| 42 | u32 class; /* OMAP class to detect */ | 46 | u32 class; /* OMAP class to detect */ |
| 43 | void __iomem *tap; /* Control module ID code */ | 47 | void __iomem *tap; /* Control module ID code */ |
| 44 | void __iomem *sdrc; /* SDRAM Controller */ | 48 | unsigned long sdrc; /* SDRAM Controller */ |
| 45 | void __iomem *sms; /* SDRAM Memory Scheduler */ | 49 | unsigned long sms; /* SDRAM Memory Scheduler */ |
| 46 | void __iomem *ctrl; /* System Control Module */ | 50 | unsigned long ctrl; /* System Control Module */ |
| 47 | void __iomem *prm; /* Power and Reset Management */ | 51 | unsigned long prm; /* Power and Reset Management */ |
| 48 | void __iomem *cm; /* Clock Management */ | 52 | unsigned long cm; /* Clock Management */ |
| 49 | void __iomem *cm2; | 53 | unsigned long cm2; |
| 54 | unsigned long uart1_phys; | ||
| 55 | unsigned long uart2_phys; | ||
| 56 | unsigned long uart3_phys; | ||
| 57 | unsigned long uart4_phys; | ||
| 50 | }; | 58 | }; |
| 51 | 59 | ||
| 52 | void omap2_set_globals_242x(void); | 60 | void omap2_set_globals_242x(void); |
| 53 | void omap2_set_globals_243x(void); | 61 | void omap2_set_globals_243x(void); |
| 54 | void omap2_set_globals_343x(void); | 62 | void omap2_set_globals_343x(void); |
| 63 | void omap2_set_globals_36xx(void); | ||
| 55 | void omap2_set_globals_443x(void); | 64 | void omap2_set_globals_443x(void); |
| 56 | 65 | ||
| 57 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | 66 | /* These get called from omap2_set_globals_xxxx(), do not call these */ |
| @@ -59,6 +68,7 @@ void omap2_set_globals_tap(struct omap_globals *); | |||
| 59 | void omap2_set_globals_sdrc(struct omap_globals *); | 68 | void omap2_set_globals_sdrc(struct omap_globals *); |
| 60 | void omap2_set_globals_control(struct omap_globals *); | 69 | void omap2_set_globals_control(struct omap_globals *); |
| 61 | void omap2_set_globals_prcm(struct omap_globals *); | 70 | void omap2_set_globals_prcm(struct omap_globals *); |
| 71 | void omap2_set_globals_uart(struct omap_globals *); | ||
| 62 | 72 | ||
| 63 | /** | 73 | /** |
| 64 | * omap_test_timeout - busy-loop, testing a condition | 74 | * omap_test_timeout - busy-loop, testing a condition |
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index a745d62fad0d..a56deee97676 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h | |||
| @@ -160,6 +160,14 @@ | |||
| 160 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) | 160 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) |
| 161 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) | 161 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) |
| 162 | 162 | ||
| 163 | /* AM35XX only CONTROL_GENERAL register offsets */ | ||
| 164 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) | ||
| 165 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) | ||
| 166 | #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) | ||
| 167 | #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) | ||
| 168 | #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) | ||
| 169 | #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) | ||
| 170 | #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) | ||
| 163 | 171 | ||
| 164 | /* 34xx PADCONF register offsets */ | 172 | /* 34xx PADCONF register offsets */ |
| 165 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ | 173 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ |
| @@ -196,6 +204,9 @@ | |||
| 196 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | 204 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 |
| 197 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 | 205 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 |
| 198 | 206 | ||
| 207 | /* 44xx control status register offset */ | ||
| 208 | #define OMAP44XX_CONTROL_STATUS 0x2c4 | ||
| 209 | |||
| 199 | /* | 210 | /* |
| 200 | * REVISIT: This list of registers is not comprehensive - there are more | 211 | * REVISIT: This list of registers is not comprehensive - there are more |
| 201 | * that should be added. | 212 | * that should be added. |
| @@ -257,6 +268,32 @@ | |||
| 257 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) | 268 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) |
| 258 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C | 269 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C |
| 259 | 270 | ||
| 271 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ | ||
| 272 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 | ||
| 273 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 | ||
| 274 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 | ||
| 275 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 | ||
| 276 | #define AM35XX_USBOTG_FCLK_SHIFT 8 | ||
| 277 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 | ||
| 278 | #define AM35XX_VPFE_FCLK_SHIFT 10 | ||
| 279 | |||
| 280 | /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ | ||
| 281 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) | ||
| 282 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) | ||
| 283 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) | ||
| 284 | #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) | ||
| 285 | #define AM35XX_USBOTGSS_INT_CLR BIT(4) | ||
| 286 | #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) | ||
| 287 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) | ||
| 288 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) | ||
| 289 | |||
| 290 | /*AM35XX CONTROL_IP_SW_RESET bits*/ | ||
| 291 | #define AM35XX_USBOTGSS_SW_RST BIT(0) | ||
| 292 | #define AM35XX_CPGMACSS_SW_RST BIT(1) | ||
| 293 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) | ||
| 294 | #define AM35XX_HECC_SW_RST BIT(3) | ||
| 295 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) | ||
| 296 | |||
| 260 | /* | 297 | /* |
| 261 | * CONTROL OMAP STATUS register to identify OMAP3 features | 298 | * CONTROL OMAP STATUS register to identify OMAP3 features |
| 262 | */ | 299 | */ |
| @@ -292,8 +329,7 @@ | |||
| 292 | 329 | ||
| 293 | 330 | ||
| 294 | #ifndef __ASSEMBLY__ | 331 | #ifndef __ASSEMBLY__ |
| 295 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 332 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 296 | defined(CONFIG_ARCH_OMAP4) | ||
| 297 | extern void __iomem *omap_ctrl_base_get(void); | 333 | extern void __iomem *omap_ctrl_base_get(void); |
| 298 | extern u8 omap_ctrl_readb(u16 offset); | 334 | extern u8 omap_ctrl_readb(u16 offset); |
| 299 | extern u16 omap_ctrl_readw(u16 offset); | 335 | extern u16 omap_ctrl_readw(u16 offset); |
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index a162f585b1e3..ed8786c41df2 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #define __ASM_ARCH_OMAP_CPU_H | 31 | #define __ASM_ARCH_OMAP_CPU_H |
| 32 | 32 | ||
| 33 | #include <linux/bitops.h> | 33 | #include <linux/bitops.h> |
| 34 | #include <plat/multi.h> | ||
| 34 | 35 | ||
| 35 | /* | 36 | /* |
| 36 | * Omap device type i.e. EMU/HS/TST/GP/BAD | 37 | * Omap device type i.e. EMU/HS/TST/GP/BAD |
| @@ -44,7 +45,7 @@ | |||
| 44 | int omap_type(void); | 45 | int omap_type(void); |
| 45 | 46 | ||
| 46 | struct omap_chip_id { | 47 | struct omap_chip_id { |
| 47 | u8 oc; | 48 | u16 oc; |
| 48 | u8 type; | 49 | u8 type; |
| 49 | }; | 50 | }; |
| 50 | 51 | ||
| @@ -76,75 +77,6 @@ unsigned int omap_rev(void); | |||
| 76 | #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) | 77 | #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) |
| 77 | 78 | ||
| 78 | /* | 79 | /* |
| 79 | * Test if multicore OMAP support is needed | ||
| 80 | */ | ||
| 81 | #undef MULTI_OMAP1 | ||
| 82 | #undef MULTI_OMAP2 | ||
| 83 | #undef OMAP_NAME | ||
| 84 | |||
| 85 | #ifdef CONFIG_ARCH_OMAP730 | ||
| 86 | # ifdef OMAP_NAME | ||
| 87 | # undef MULTI_OMAP1 | ||
| 88 | # define MULTI_OMAP1 | ||
| 89 | # else | ||
| 90 | # define OMAP_NAME omap730 | ||
| 91 | # endif | ||
| 92 | #endif | ||
| 93 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 94 | # ifdef OMAP_NAME | ||
| 95 | # undef MULTI_OMAP1 | ||
| 96 | # define MULTI_OMAP1 | ||
| 97 | # else | ||
| 98 | # define OMAP_NAME omap850 | ||
| 99 | # endif | ||
| 100 | #endif | ||
| 101 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 102 | # ifdef OMAP_NAME | ||
| 103 | # undef MULTI_OMAP1 | ||
| 104 | # define MULTI_OMAP1 | ||
| 105 | # else | ||
| 106 | # define OMAP_NAME omap1510 | ||
| 107 | # endif | ||
| 108 | #endif | ||
| 109 | #ifdef CONFIG_ARCH_OMAP16XX | ||
| 110 | # ifdef OMAP_NAME | ||
| 111 | # undef MULTI_OMAP1 | ||
| 112 | # define MULTI_OMAP1 | ||
| 113 | # else | ||
| 114 | # define OMAP_NAME omap16xx | ||
| 115 | # endif | ||
| 116 | #endif | ||
| 117 | #if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) | ||
| 118 | # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) | ||
| 119 | # error "OMAP1 and OMAP2 can't be selected at the same time" | ||
| 120 | # endif | ||
| 121 | #endif | ||
| 122 | #ifdef CONFIG_ARCH_OMAP2420 | ||
| 123 | # ifdef OMAP_NAME | ||
| 124 | # undef MULTI_OMAP2 | ||
| 125 | # define MULTI_OMAP2 | ||
| 126 | # else | ||
| 127 | # define OMAP_NAME omap2420 | ||
| 128 | # endif | ||
| 129 | #endif | ||
| 130 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 131 | # ifdef OMAP_NAME | ||
| 132 | # undef MULTI_OMAP2 | ||
| 133 | # define MULTI_OMAP2 | ||
| 134 | # else | ||
| 135 | # define OMAP_NAME omap2430 | ||
| 136 | # endif | ||
| 137 | #endif | ||
| 138 | #ifdef CONFIG_ARCH_OMAP3430 | ||
| 139 | # ifdef OMAP_NAME | ||
| 140 | # undef MULTI_OMAP2 | ||
| 141 | # define MULTI_OMAP2 | ||
| 142 | # else | ||
| 143 | # define OMAP_NAME omap3430 | ||
| 144 | # endif | ||
| 145 | #endif | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Macros to group OMAP into cpu classes. | 80 | * Macros to group OMAP into cpu classes. |
| 149 | * These can be used in most places. | 81 | * These can be used in most places. |
| 150 | * cpu_is_omap7xx(): True for OMAP730, OMAP850 | 82 | * cpu_is_omap7xx(): True for OMAP730, OMAP850 |
| @@ -154,6 +86,7 @@ unsigned int omap_rev(void); | |||
| 154 | * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 | 86 | * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 |
| 155 | * cpu_is_omap243x(): True for OMAP2430 | 87 | * cpu_is_omap243x(): True for OMAP2430 |
| 156 | * cpu_is_omap343x(): True for OMAP3430 | 88 | * cpu_is_omap343x(): True for OMAP3430 |
| 89 | * cpu_is_omap443x(): True for OMAP4430 | ||
| 157 | */ | 90 | */ |
| 158 | #define GET_OMAP_CLASS (omap_rev() & 0xff) | 91 | #define GET_OMAP_CLASS (omap_rev() & 0xff) |
| 159 | 92 | ||
| @@ -232,7 +165,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) | |||
| 232 | #endif | 165 | #endif |
| 233 | 166 | ||
| 234 | #if defined(MULTI_OMAP2) | 167 | #if defined(MULTI_OMAP2) |
| 235 | # if defined(CONFIG_ARCH_OMAP24XX) | 168 | # if defined(CONFIG_ARCH_OMAP2) |
| 236 | # undef cpu_is_omap24xx | 169 | # undef cpu_is_omap24xx |
| 237 | # undef cpu_is_omap242x | 170 | # undef cpu_is_omap242x |
| 238 | # undef cpu_is_omap243x | 171 | # undef cpu_is_omap243x |
| @@ -240,14 +173,14 @@ IS_OMAP_SUBCLASS(443x, 0x443) | |||
| 240 | # define cpu_is_omap242x() is_omap242x() | 173 | # define cpu_is_omap242x() is_omap242x() |
| 241 | # define cpu_is_omap243x() is_omap243x() | 174 | # define cpu_is_omap243x() is_omap243x() |
| 242 | # endif | 175 | # endif |
| 243 | # if defined(CONFIG_ARCH_OMAP34XX) | 176 | # if defined(CONFIG_ARCH_OMAP3) |
| 244 | # undef cpu_is_omap34xx | 177 | # undef cpu_is_omap34xx |
| 245 | # undef cpu_is_omap343x | 178 | # undef cpu_is_omap343x |
| 246 | # define cpu_is_omap34xx() is_omap34xx() | 179 | # define cpu_is_omap34xx() is_omap34xx() |
| 247 | # define cpu_is_omap343x() is_omap343x() | 180 | # define cpu_is_omap343x() is_omap343x() |
| 248 | # endif | 181 | # endif |
| 249 | #else | 182 | #else |
| 250 | # if defined(CONFIG_ARCH_OMAP24XX) | 183 | # if defined(CONFIG_ARCH_OMAP2) |
| 251 | # undef cpu_is_omap24xx | 184 | # undef cpu_is_omap24xx |
| 252 | # define cpu_is_omap24xx() 1 | 185 | # define cpu_is_omap24xx() 1 |
| 253 | # endif | 186 | # endif |
| @@ -259,7 +192,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) | |||
| 259 | # undef cpu_is_omap243x | 192 | # undef cpu_is_omap243x |
| 260 | # define cpu_is_omap243x() 1 | 193 | # define cpu_is_omap243x() 1 |
| 261 | # endif | 194 | # endif |
| 262 | # if defined(CONFIG_ARCH_OMAP34XX) | 195 | # if defined(CONFIG_ARCH_OMAP3) |
| 263 | # undef cpu_is_omap34xx | 196 | # undef cpu_is_omap34xx |
| 264 | # define cpu_is_omap34xx() 1 | 197 | # define cpu_is_omap34xx() 1 |
| 265 | # endif | 198 | # endif |
| @@ -286,6 +219,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) | |||
| 286 | * cpu_is_omap2423(): True for OMAP2423 | 219 | * cpu_is_omap2423(): True for OMAP2423 |
| 287 | * cpu_is_omap2430(): True for OMAP2430 | 220 | * cpu_is_omap2430(): True for OMAP2430 |
| 288 | * cpu_is_omap3430(): True for OMAP3430 | 221 | * cpu_is_omap3430(): True for OMAP3430 |
| 222 | * cpu_is_omap4430(): True for OMAP4430 | ||
| 289 | * cpu_is_omap3505(): True for OMAP3505 | 223 | * cpu_is_omap3505(): True for OMAP3505 |
| 290 | * cpu_is_omap3517(): True for OMAP3517 | 224 | * cpu_is_omap3517(): True for OMAP3517 |
| 291 | */ | 225 | */ |
| @@ -334,6 +268,7 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 334 | #define cpu_is_omap3505() 0 | 268 | #define cpu_is_omap3505() 0 |
| 335 | #define cpu_is_omap3517() 0 | 269 | #define cpu_is_omap3517() 0 |
| 336 | #define cpu_is_omap3430() 0 | 270 | #define cpu_is_omap3430() 0 |
| 271 | #define cpu_is_omap4430() 0 | ||
| 337 | #define cpu_is_omap3630() 0 | 272 | #define cpu_is_omap3630() 0 |
| 338 | 273 | ||
| 339 | /* | 274 | /* |
| @@ -371,7 +306,7 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 371 | # define cpu_is_omap1710() is_omap1710() | 306 | # define cpu_is_omap1710() is_omap1710() |
| 372 | #endif | 307 | #endif |
| 373 | 308 | ||
| 374 | #if defined(CONFIG_ARCH_OMAP24XX) | 309 | #if defined(CONFIG_ARCH_OMAP2) |
| 375 | # undef cpu_is_omap2420 | 310 | # undef cpu_is_omap2420 |
| 376 | # undef cpu_is_omap2422 | 311 | # undef cpu_is_omap2422 |
| 377 | # undef cpu_is_omap2423 | 312 | # undef cpu_is_omap2423 |
| @@ -382,7 +317,7 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 382 | # define cpu_is_omap2430() is_omap2430() | 317 | # define cpu_is_omap2430() is_omap2430() |
| 383 | #endif | 318 | #endif |
| 384 | 319 | ||
| 385 | #if defined(CONFIG_ARCH_OMAP34XX) | 320 | #if defined(CONFIG_ARCH_OMAP3) |
| 386 | # undef cpu_is_omap3430 | 321 | # undef cpu_is_omap3430 |
| 387 | # undef cpu_is_omap3503 | 322 | # undef cpu_is_omap3503 |
| 388 | # undef cpu_is_omap3515 | 323 | # undef cpu_is_omap3515 |
| @@ -471,9 +406,12 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 471 | #define CHIP_IS_OMAP3430ES3_0 (1 << 5) | 406 | #define CHIP_IS_OMAP3430ES3_0 (1 << 5) |
| 472 | #define CHIP_IS_OMAP3430ES3_1 (1 << 6) | 407 | #define CHIP_IS_OMAP3430ES3_1 (1 << 6) |
| 473 | #define CHIP_IS_OMAP3630ES1 (1 << 7) | 408 | #define CHIP_IS_OMAP3630ES1 (1 << 7) |
| 409 | #define CHIP_IS_OMAP4430ES1 (1 << 8) | ||
| 474 | 410 | ||
| 475 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | 411 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) |
| 476 | 412 | ||
| 413 | #define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) | ||
| 414 | |||
| 477 | /* | 415 | /* |
| 478 | * "GE" here represents "greater than or equal to" in terms of ES | 416 | * "GE" here represents "greater than or equal to" in terms of ES |
| 479 | * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 | 417 | * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 |
| @@ -501,6 +439,7 @@ extern u32 omap3_features; | |||
| 501 | #define OMAP3_HAS_SGX BIT(2) | 439 | #define OMAP3_HAS_SGX BIT(2) |
| 502 | #define OMAP3_HAS_NEON BIT(3) | 440 | #define OMAP3_HAS_NEON BIT(3) |
| 503 | #define OMAP3_HAS_ISP BIT(4) | 441 | #define OMAP3_HAS_ISP BIT(4) |
| 442 | #define OMAP3_HAS_192MHZ_CLK BIT(5) | ||
| 504 | 443 | ||
| 505 | #define OMAP3_HAS_FEATURE(feat,flag) \ | 444 | #define OMAP3_HAS_FEATURE(feat,flag) \ |
| 506 | static inline unsigned int omap3_has_ ##feat(void) \ | 445 | static inline unsigned int omap3_has_ ##feat(void) \ |
| @@ -513,5 +452,6 @@ OMAP3_HAS_FEATURE(sgx, SGX) | |||
| 513 | OMAP3_HAS_FEATURE(iva, IVA) | 452 | OMAP3_HAS_FEATURE(iva, IVA) |
| 514 | OMAP3_HAS_FEATURE(neon, NEON) | 453 | OMAP3_HAS_FEATURE(neon, NEON) |
| 515 | OMAP3_HAS_FEATURE(isp, ISP) | 454 | OMAP3_HAS_FEATURE(isp, ISP) |
| 455 | OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) | ||
| 516 | 456 | ||
| 517 | #endif | 457 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h new file mode 100644 index 000000000000..1f767cb2f38a --- /dev/null +++ b/arch/arm/plat-omap/include/plat/dma-44xx.h | |||
| @@ -0,0 +1,147 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 SDMA channel definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
| 8 | * Benoit Cousson (b-cousson@ti.com) | ||
| 9 | * Paul Walmsley (paul@pwsan.com) | ||
| 10 | * | ||
| 11 | * This file is automatically generated from the OMAP hardware databases. | ||
| 12 | * We respectfully ask that any modifications to this file be coordinated | ||
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 14 | * authors above to ensure that the autogeneration scripts are kept | ||
| 15 | * up-to-date with the file contents. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or modify | ||
| 18 | * it under the terms of the GNU General Public License version 2 as | ||
| 19 | * published by the Free Software Foundation. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H | ||
| 23 | #define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H | ||
| 24 | |||
| 25 | #define OMAP44XX_DMA_SYS_REQ0 2 | ||
| 26 | #define OMAP44XX_DMA_SYS_REQ1 3 | ||
| 27 | #define OMAP44XX_DMA_GPMC 4 | ||
| 28 | #define OMAP44XX_DMA_DSS_DISPC_REQ 6 | ||
| 29 | #define OMAP44XX_DMA_SYS_REQ2 7 | ||
| 30 | #define OMAP44XX_DMA_MCASP1_AXEVT 8 | ||
| 31 | #define OMAP44XX_DMA_ISS_REQ1 9 | ||
| 32 | #define OMAP44XX_DMA_ISS_REQ2 10 | ||
| 33 | #define OMAP44XX_DMA_MCASP1_AREVT 11 | ||
| 34 | #define OMAP44XX_DMA_ISS_REQ3 12 | ||
| 35 | #define OMAP44XX_DMA_ISS_REQ4 13 | ||
| 36 | #define OMAP44XX_DMA_DSS_RFBI_REQ 14 | ||
| 37 | #define OMAP44XX_DMA_SPI3_TX0 15 | ||
| 38 | #define OMAP44XX_DMA_SPI3_RX0 16 | ||
| 39 | #define OMAP44XX_DMA_MCBSP2_TX 17 | ||
| 40 | #define OMAP44XX_DMA_MCBSP2_RX 18 | ||
| 41 | #define OMAP44XX_DMA_MCBSP3_TX 19 | ||
| 42 | #define OMAP44XX_DMA_MCBSP3_RX 20 | ||
| 43 | #define OMAP44XX_DMA_C2C_SSCM_GPO0 21 | ||
| 44 | #define OMAP44XX_DMA_C2C_SSCM_GPO1 22 | ||
| 45 | #define OMAP44XX_DMA_SPI3_TX1 23 | ||
| 46 | #define OMAP44XX_DMA_SPI3_RX1 24 | ||
| 47 | #define OMAP44XX_DMA_I2C3_TX 25 | ||
| 48 | #define OMAP44XX_DMA_I2C3_RX 26 | ||
| 49 | #define OMAP44XX_DMA_I2C1_TX 27 | ||
| 50 | #define OMAP44XX_DMA_I2C1_RX 28 | ||
| 51 | #define OMAP44XX_DMA_I2C2_TX 29 | ||
| 52 | #define OMAP44XX_DMA_I2C2_RX 30 | ||
| 53 | #define OMAP44XX_DMA_MCBSP4_TX 31 | ||
| 54 | #define OMAP44XX_DMA_MCBSP4_RX 32 | ||
| 55 | #define OMAP44XX_DMA_MCBSP1_TX 33 | ||
| 56 | #define OMAP44XX_DMA_MCBSP1_RX 34 | ||
| 57 | #define OMAP44XX_DMA_SPI1_TX0 35 | ||
| 58 | #define OMAP44XX_DMA_SPI1_RX0 36 | ||
| 59 | #define OMAP44XX_DMA_SPI1_TX1 37 | ||
| 60 | #define OMAP44XX_DMA_SPI1_RX1 38 | ||
| 61 | #define OMAP44XX_DMA_SPI1_TX2 39 | ||
| 62 | #define OMAP44XX_DMA_SPI1_RX2 40 | ||
| 63 | #define OMAP44XX_DMA_SPI1_TX3 41 | ||
| 64 | #define OMAP44XX_DMA_SPI1_RX3 42 | ||
| 65 | #define OMAP44XX_DMA_SPI2_TX0 43 | ||
| 66 | #define OMAP44XX_DMA_SPI2_RX0 44 | ||
| 67 | #define OMAP44XX_DMA_SPI2_TX1 45 | ||
| 68 | #define OMAP44XX_DMA_SPI2_RX1 46 | ||
| 69 | #define OMAP44XX_DMA_MMC2_TX 47 | ||
| 70 | #define OMAP44XX_DMA_MMC2_RX 48 | ||
| 71 | #define OMAP44XX_DMA_UART1_TX 49 | ||
| 72 | #define OMAP44XX_DMA_UART1_RX 50 | ||
| 73 | #define OMAP44XX_DMA_UART2_TX 51 | ||
| 74 | #define OMAP44XX_DMA_UART2_RX 52 | ||
| 75 | #define OMAP44XX_DMA_UART3_TX 53 | ||
| 76 | #define OMAP44XX_DMA_UART3_RX 54 | ||
| 77 | #define OMAP44XX_DMA_UART4_TX 55 | ||
| 78 | #define OMAP44XX_DMA_UART4_RX 56 | ||
| 79 | #define OMAP44XX_DMA_MMC4_TX 57 | ||
| 80 | #define OMAP44XX_DMA_MMC4_RX 58 | ||
| 81 | #define OMAP44XX_DMA_MMC5_TX 59 | ||
| 82 | #define OMAP44XX_DMA_MMC5_RX 60 | ||
| 83 | #define OMAP44XX_DMA_MMC1_TX 61 | ||
| 84 | #define OMAP44XX_DMA_MMC1_RX 62 | ||
| 85 | #define OMAP44XX_DMA_SYS_REQ3 64 | ||
| 86 | #define OMAP44XX_DMA_MCPDM_UP 65 | ||
| 87 | #define OMAP44XX_DMA_MCPDM_DL 66 | ||
| 88 | #define OMAP44XX_DMA_DMIC_REQ 67 | ||
| 89 | #define OMAP44XX_DMA_C2C_SSCM_GPO2 68 | ||
| 90 | #define OMAP44XX_DMA_C2C_SSCM_GPO3 69 | ||
| 91 | #define OMAP44XX_DMA_SPI4_TX0 70 | ||
| 92 | #define OMAP44XX_DMA_SPI4_RX0 71 | ||
| 93 | #define OMAP44XX_DMA_DSS_DSI1_REQ0 72 | ||
| 94 | #define OMAP44XX_DMA_DSS_DSI1_REQ1 73 | ||
| 95 | #define OMAP44XX_DMA_DSS_DSI1_REQ2 74 | ||
| 96 | #define OMAP44XX_DMA_DSS_DSI1_REQ3 75 | ||
| 97 | #define OMAP44XX_DMA_DSS_HDMI_REQ 76 | ||
| 98 | #define OMAP44XX_DMA_MMC3_TX 77 | ||
| 99 | #define OMAP44XX_DMA_MMC3_RX 78 | ||
| 100 | #define OMAP44XX_DMA_USIM_TX 79 | ||
| 101 | #define OMAP44XX_DMA_USIM_RX 80 | ||
| 102 | #define OMAP44XX_DMA_DSS_DSI2_REQ0 81 | ||
| 103 | #define OMAP44XX_DMA_DSS_DSI2_REQ1 82 | ||
| 104 | #define OMAP44XX_DMA_DSS_DSI2_REQ2 83 | ||
| 105 | #define OMAP44XX_DMA_DSS_DSI2_REQ3 84 | ||
| 106 | #define OMAP44XX_DMA_SLIMBUS1_TX0 85 | ||
| 107 | #define OMAP44XX_DMA_SLIMBUS1_TX1 86 | ||
| 108 | #define OMAP44XX_DMA_SLIMBUS1_TX2 87 | ||
| 109 | #define OMAP44XX_DMA_SLIMBUS1_TX3 88 | ||
| 110 | #define OMAP44XX_DMA_SLIMBUS1_RX0 89 | ||
| 111 | #define OMAP44XX_DMA_SLIMBUS1_RX1 90 | ||
| 112 | #define OMAP44XX_DMA_SLIMBUS1_RX2 91 | ||
| 113 | #define OMAP44XX_DMA_SLIMBUS1_RX3 92 | ||
| 114 | #define OMAP44XX_DMA_SLIMBUS2_TX0 93 | ||
| 115 | #define OMAP44XX_DMA_SLIMBUS2_TX1 94 | ||
| 116 | #define OMAP44XX_DMA_SLIMBUS2_TX2 95 | ||
| 117 | #define OMAP44XX_DMA_SLIMBUS2_TX3 96 | ||
| 118 | #define OMAP44XX_DMA_SLIMBUS2_RX0 97 | ||
| 119 | #define OMAP44XX_DMA_SLIMBUS2_RX1 98 | ||
| 120 | #define OMAP44XX_DMA_SLIMBUS2_RX2 99 | ||
| 121 | #define OMAP44XX_DMA_SLIMBUS2_RX3 100 | ||
| 122 | #define OMAP44XX_DMA_ABE_REQ_0 101 | ||
| 123 | #define OMAP44XX_DMA_ABE_REQ_1 102 | ||
| 124 | #define OMAP44XX_DMA_ABE_REQ_2 103 | ||
| 125 | #define OMAP44XX_DMA_ABE_REQ_3 104 | ||
| 126 | #define OMAP44XX_DMA_ABE_REQ_4 105 | ||
| 127 | #define OMAP44XX_DMA_ABE_REQ_5 106 | ||
| 128 | #define OMAP44XX_DMA_ABE_REQ_6 107 | ||
| 129 | #define OMAP44XX_DMA_ABE_REQ_7 108 | ||
| 130 | #define OMAP44XX_DMA_AES1_P_CTX_IN_REQ 109 | ||
| 131 | #define OMAP44XX_DMA_AES1_P_DATA_IN_REQ 110 | ||
| 132 | #define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ 111 | ||
| 133 | #define OMAP44XX_DMA_AES2_P_CTX_IN_REQ 112 | ||
| 134 | #define OMAP44XX_DMA_AES2_P_DATA_IN_REQ 113 | ||
| 135 | #define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ 114 | ||
| 136 | #define OMAP44XX_DMA_DES_P_CTX_IN_REQ 115 | ||
| 137 | #define OMAP44XX_DMA_DES_P_DATA_IN_REQ 116 | ||
| 138 | #define OMAP44XX_DMA_DES_P_DATA_OUT_REQ 117 | ||
| 139 | #define OMAP44XX_DMA_SHA2_CTXIN_P 118 | ||
| 140 | #define OMAP44XX_DMA_SHA2_DIN_P 119 | ||
| 141 | #define OMAP44XX_DMA_SHA2_CTXOUT_P 120 | ||
| 142 | #define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ 121 | ||
| 143 | #define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ 122 | ||
| 144 | #define OMAP44XX_DMA_I2C4_TX 124 | ||
| 145 | #define OMAP44XX_DMA_I2C4_RX 125 | ||
| 146 | |||
| 147 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 4ede9e17a0be..02232ca2c37f 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
| @@ -21,6 +21,9 @@ | |||
| 21 | #ifndef __ASM_ARCH_DMA_H | 21 | #ifndef __ASM_ARCH_DMA_H |
| 22 | #define __ASM_ARCH_DMA_H | 22 | #define __ASM_ARCH_DMA_H |
| 23 | 23 | ||
| 24 | /* Move omap4 specific defines to dma-44xx.h */ | ||
| 25 | #include "dma-44xx.h" | ||
| 26 | |||
| 24 | /* Hardware registers for omap1 */ | 27 | /* Hardware registers for omap1 */ |
| 25 | #define OMAP1_DMA_BASE (0xfffed800) | 28 | #define OMAP1_DMA_BASE (0xfffed800) |
| 26 | 29 | ||
| @@ -316,89 +319,6 @@ | |||
| 316 | #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ | 319 | #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ |
| 317 | #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ | 320 | #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ |
| 318 | 321 | ||
| 319 | /* DMA request lines for 44xx */ | ||
| 320 | #define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */ | ||
| 321 | #define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */ | ||
| 322 | #define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */ | ||
| 323 | #define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */ | ||
| 324 | #define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */ | ||
| 325 | #define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */ | ||
| 326 | #define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */ | ||
| 327 | #define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ | ||
| 328 | #define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ | ||
| 329 | #define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */ | ||
| 330 | #define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */ | ||
| 331 | #define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */ | ||
| 332 | #define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */ | ||
| 333 | #define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ | ||
| 334 | #define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ | ||
| 335 | #define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */ | ||
| 336 | #define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */ | ||
| 337 | #define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */ | ||
| 338 | #define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */ | ||
| 339 | #define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */ | ||
| 340 | #define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */ | ||
| 341 | #define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */ | ||
| 342 | #define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */ | ||
| 343 | #define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */ | ||
| 344 | #define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */ | ||
| 345 | #define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ | ||
| 346 | #define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ | ||
| 347 | #define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ | ||
| 348 | #define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ | ||
| 349 | #define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ | ||
| 350 | #define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ | ||
| 351 | #define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ | ||
| 352 | #define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ | ||
| 353 | #define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ | ||
| 354 | #define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ | ||
| 355 | #define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ | ||
| 356 | #define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ | ||
| 357 | #define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */ | ||
| 358 | #define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */ | ||
| 359 | #define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */ | ||
| 360 | #define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */ | ||
| 361 | #define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */ | ||
| 362 | #define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */ | ||
| 363 | #define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */ | ||
| 364 | #define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */ | ||
| 365 | #define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */ | ||
| 366 | #define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */ | ||
| 367 | #define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */ | ||
| 368 | #define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */ | ||
| 369 | #define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */ | ||
| 370 | #define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */ | ||
| 371 | #define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */ | ||
| 372 | #define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */ | ||
| 373 | #define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */ | ||
| 374 | #define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */ | ||
| 375 | #define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */ | ||
| 376 | #define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ | ||
| 377 | #define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ | ||
| 378 | #define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */ | ||
| 379 | #define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */ | ||
| 380 | #define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */ | ||
| 381 | #define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */ | ||
| 382 | #define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */ | ||
| 383 | #define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */ | ||
| 384 | #define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */ | ||
| 385 | #define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */ | ||
| 386 | #define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */ | ||
| 387 | #define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */ | ||
| 388 | #define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */ | ||
| 389 | #define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */ | ||
| 390 | #define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */ | ||
| 391 | #define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */ | ||
| 392 | #define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */ | ||
| 393 | #define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */ | ||
| 394 | #define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */ | ||
| 395 | #define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */ | ||
| 396 | #define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */ | ||
| 397 | #define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */ | ||
| 398 | #define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */ | ||
| 399 | #define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */ | ||
| 400 | #define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */ | ||
| 401 | |||
| 402 | /*----------------------------------------------------------------------------*/ | 322 | /*----------------------------------------------------------------------------*/ |
| 403 | 323 | ||
| 404 | #define OMAP1_DMA_TOUT_IRQ (1 << 0) | 324 | #define OMAP1_DMA_TOUT_IRQ (1 << 0) |
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h new file mode 100644 index 000000000000..3e6327016b40 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/flash.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* | ||
| 2 | * Flash support for OMAP1 | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __OMAP_FLASH_H | ||
| 10 | #define __OMAP_FLASH_H | ||
| 11 | |||
| 12 | #include <linux/mtd/map.h> | ||
| 13 | |||
| 14 | extern void omap1_set_vpp(struct map_info *map, int enable); | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index e081338e0b23..145838a81ef6 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | 27 | ||
| 28 | #define GPMC_CONFIG 0x50 | 28 | #define GPMC_CONFIG 0x50 |
| 29 | #define GPMC_STATUS 0x54 | 29 | #define GPMC_STATUS 0x54 |
| 30 | #define GPMC_CS0_BASE 0x60 | ||
| 31 | #define GPMC_CS_SIZE 0x30 | ||
| 30 | 32 | ||
| 31 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | 33 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) |
| 32 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | 34 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) |
| @@ -110,6 +112,6 @@ extern void gpmc_prefetch_reset(void); | |||
| 110 | extern int gpmc_prefetch_status(void); | 112 | extern int gpmc_prefetch_status(void); |
| 111 | extern void omap3_gpmc_save_context(void); | 113 | extern void omap3_gpmc_save_context(void); |
| 112 | extern void omap3_gpmc_restore_context(void); | 114 | extern void omap3_gpmc_restore_context(void); |
| 113 | extern void __init gpmc_init(void); | 115 | extern void gpmc_init(void); |
| 114 | 116 | ||
| 115 | #endif | 117 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 585d9ca68b97..87f6bf2ea4fa 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h | |||
| @@ -34,6 +34,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 34 | } | 34 | } |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | int omap_plat_register_i2c_bus(int bus_id, u32 clkrate, | 37 | void __init omap1_i2c_mux_pins(int bus_id); |
| 38 | struct i2c_board_info const *info, | 38 | void __init omap2_i2c_mux_pins(int bus_id); |
| 39 | unsigned len); | ||
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index a3e7b471bcba..128b549c2796 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h | |||
| @@ -158,10 +158,6 @@ | |||
| 158 | * VPOM3430 was not working for Int controller | 158 | * VPOM3430 was not working for Int controller |
| 159 | */ | 159 | */ |
| 160 | 160 | ||
| 161 | #define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */ | ||
| 162 | #define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET) | ||
| 163 | #define L4_WK_34XX_SIZE SZ_1M | ||
| 164 | |||
| 165 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE | 161 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE |
| 166 | /* 0x49000000 --> 0xfb000000 */ | 162 | /* 0x49000000 --> 0xfb000000 */ |
| 167 | #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) | 163 | #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) |
| @@ -204,11 +200,6 @@ | |||
| 204 | #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) | 200 | #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
| 205 | #define L4_44XX_SIZE SZ_4M | 201 | #define L4_44XX_SIZE SZ_4M |
| 206 | 202 | ||
| 207 | |||
| 208 | #define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */ | ||
| 209 | #define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET) | ||
| 210 | #define L4_WK_44XX_SIZE SZ_1M | ||
| 211 | |||
| 212 | #define L4_PER_44XX_PHYS L4_PER_44XX_BASE | 203 | #define L4_PER_44XX_PHYS L4_PER_44XX_BASE |
| 213 | /* 0x48000000 --> 0xfa000000 */ | 204 | /* 0x48000000 --> 0xfa000000 */ |
| 214 | #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) | 205 | #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
| @@ -268,7 +259,38 @@ struct omap_sdrc_params; | |||
| 268 | extern void omap1_map_common_io(void); | 259 | extern void omap1_map_common_io(void); |
| 269 | extern void omap1_init_common_hw(void); | 260 | extern void omap1_init_common_hw(void); |
| 270 | 261 | ||
| 271 | extern void omap2_map_common_io(void); | 262 | #ifdef CONFIG_ARCH_OMAP2420 |
| 263 | extern void omap242x_map_common_io(void); | ||
| 264 | #else | ||
| 265 | static inline void omap242x_map_common_io(void) | ||
| 266 | { | ||
| 267 | } | ||
| 268 | #endif | ||
| 269 | |||
| 270 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 271 | extern void omap243x_map_common_io(void); | ||
| 272 | #else | ||
| 273 | static inline void omap243x_map_common_io(void) | ||
| 274 | { | ||
| 275 | } | ||
| 276 | #endif | ||
| 277 | |||
| 278 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 279 | extern void omap34xx_map_common_io(void); | ||
| 280 | #else | ||
| 281 | static inline void omap34xx_map_common_io(void) | ||
| 282 | { | ||
| 283 | } | ||
| 284 | #endif | ||
| 285 | |||
| 286 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 287 | extern void omap44xx_map_common_io(void); | ||
| 288 | #else | ||
| 289 | static inline void omap44xx_map_common_io(void) | ||
| 290 | { | ||
| 291 | } | ||
| 292 | #endif | ||
| 293 | |||
| 272 | extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | 294 | extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, |
| 273 | struct omap_sdrc_params *sdrc_cs1); | 295 | struct omap_sdrc_params *sdrc_cs1); |
| 274 | 296 | ||
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h new file mode 100644 index 000000000000..518322c80116 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/irqs-44xx.h | |||
| @@ -0,0 +1,144 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Interrupt lines definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
| 7 | * Benoit Cousson (b-cousson@ti.com) | ||
| 8 | * | ||
| 9 | * This file is automatically generated from the OMAP hardware databases. | ||
| 10 | * We respectfully ask that any modifications to this file be coordinated | ||
| 11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 12 | * authors above to ensure that the autogeneration scripts are kept | ||
| 13 | * up-to-date with the file contents. | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H | ||
| 21 | #define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H | ||
| 22 | |||
| 23 | /* OMAP44XX IRQs numbers definitions */ | ||
| 24 | #define OMAP44XX_IRQ_LOCALTIMER 29 | ||
| 25 | #define OMAP44XX_IRQ_LOCALWDT 30 | ||
| 26 | |||
| 27 | #define OMAP44XX_IRQ_GIC_START 32 | ||
| 28 | |||
| 29 | #define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START) | ||
| 30 | #define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START) | ||
| 31 | #define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START) | ||
| 32 | #define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START) | ||
| 33 | #define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START) | ||
| 34 | #define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START) | ||
| 35 | #define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START) | ||
| 36 | #define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START) | ||
| 37 | #define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START) | ||
| 38 | #define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START) | ||
| 39 | #define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START) | ||
| 40 | #define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START) | ||
| 41 | #define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START) | ||
| 42 | #define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START) | ||
| 43 | #define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START) | ||
| 44 | #define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START) | ||
| 45 | #define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START) | ||
| 46 | #define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START) | ||
| 47 | #define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START) | ||
| 48 | #define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START) | ||
| 49 | #define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START) | ||
| 50 | #define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START) | ||
| 51 | #define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START) | ||
| 52 | #define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START) | ||
| 53 | #define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START) | ||
| 54 | #define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START) | ||
| 55 | #define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START) | ||
| 56 | #define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START) | ||
| 57 | #define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START) | ||
| 58 | #define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START) | ||
| 59 | #define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START) | ||
| 60 | #define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START) | ||
| 61 | #define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START) | ||
| 62 | #define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START) | ||
| 63 | #define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START) | ||
| 64 | #define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START) | ||
| 65 | #define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START) | ||
| 66 | #define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START) | ||
| 67 | #define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START) | ||
| 68 | #define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START) | ||
| 69 | #define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START) | ||
| 70 | #define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START) | ||
| 71 | #define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START) | ||
| 72 | #define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START) | ||
| 73 | #define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START) | ||
| 74 | #define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START) | ||
| 75 | #define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START) | ||
| 76 | #define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START) | ||
| 77 | #define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START) | ||
| 78 | #define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START) | ||
| 79 | #define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START) | ||
| 80 | #define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START) | ||
| 81 | #define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START) | ||
| 82 | #define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START) | ||
| 83 | #define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START) | ||
| 84 | #define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START) | ||
| 85 | #define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START) | ||
| 86 | #define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START) | ||
| 87 | #define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START) | ||
| 88 | #define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START) | ||
| 89 | #define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START) | ||
| 90 | #define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START) | ||
| 91 | #define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START) | ||
| 92 | #define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START) | ||
| 93 | #define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START) | ||
| 94 | #define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START) | ||
| 95 | #define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START) | ||
| 96 | #define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START) | ||
| 97 | #define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START) | ||
| 98 | #define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START) | ||
| 99 | #define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START) | ||
| 100 | #define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START) | ||
| 101 | #define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START) | ||
| 102 | #define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START) | ||
| 103 | #define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START) | ||
| 104 | #define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START) | ||
| 105 | #define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START) | ||
| 106 | #define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START) | ||
| 107 | #define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START) | ||
| 108 | #define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START) | ||
| 109 | #define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START) | ||
| 110 | #define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START) | ||
| 111 | #define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START) | ||
| 112 | #define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START) | ||
| 113 | #define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START) | ||
| 114 | #define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START) | ||
| 115 | #define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START) | ||
| 116 | #define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START) | ||
| 117 | #define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START) | ||
| 118 | #define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START) | ||
| 119 | #define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START) | ||
| 120 | #define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START) | ||
| 121 | #define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START) | ||
| 122 | #define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START) | ||
| 123 | #define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START) | ||
| 124 | #define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START) | ||
| 125 | #define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START) | ||
| 126 | #define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START) | ||
| 127 | #define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START) | ||
| 128 | #define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START) | ||
| 129 | #define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START) | ||
| 130 | #define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START) | ||
| 131 | #define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START) | ||
| 132 | #define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START) | ||
| 133 | #define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START) | ||
| 134 | #define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START) | ||
| 135 | #define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START) | ||
| 136 | #define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START) | ||
| 137 | #define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START) | ||
| 138 | #define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START) | ||
| 139 | #define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START) | ||
| 140 | #define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START) | ||
| 141 | #define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START) | ||
| 142 | #define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START) | ||
| 143 | |||
| 144 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index c0ab7c80f72e..b65088a869e9 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h | |||
| @@ -28,6 +28,9 @@ | |||
| 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H | 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H |
| 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H | 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H |
| 30 | 30 | ||
| 31 | /* All OMAP4 specific defines are moved to irqs-44xx.h */ | ||
| 32 | #include "irqs-44xx.h" | ||
| 33 | |||
| 31 | /* | 34 | /* |
| 32 | * IRQ numbers for interrupt handler 1 | 35 | * IRQ numbers for interrupt handler 1 |
| 33 | * | 36 | * |
| @@ -344,95 +347,16 @@ | |||
| 344 | 347 | ||
| 345 | #define INT_34XX_BENCH_MPU_EMUL 3 | 348 | #define INT_34XX_BENCH_MPU_EMUL 3 |
| 346 | 349 | ||
| 347 | 350 | #define INT_35XX_HECC0_IRQ 24 | |
| 348 | #define IRQ_GIC_START 32 | 351 | #define INT_35XX_HECC1_IRQ 28 |
| 349 | #define INT_44XX_LOCALTIMER_IRQ 29 | 352 | #define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 |
| 350 | #define INT_44XX_LOCALWDT_IRQ 30 | 353 | #define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68 |
| 351 | 354 | #define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 | |
| 352 | #define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) | 355 | #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 |
| 353 | #define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) | 356 | #define INT_35XX_USBOTG_IRQ 71 |
| 354 | #define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) | 357 | #define INT_35XX_CCDC_VD0_IRQ 88 |
| 355 | #define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) | 358 | #define INT_35XX_CCDC_VD1_IRQ 92 |
| 356 | #define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) | 359 | #define INT_35XX_CCDC_VD2_IRQ 93 |
| 357 | #define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) | ||
| 358 | #define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) | ||
| 359 | #define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) | ||
| 360 | #define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) | ||
| 361 | #define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) | ||
| 362 | #define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) | ||
| 363 | #define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) | ||
| 364 | #define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) | ||
| 365 | #define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) | ||
| 366 | #define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) | ||
| 367 | #define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) | ||
| 368 | #define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) | ||
| 369 | #define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) | ||
| 370 | #define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) | ||
| 371 | #define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) | ||
| 372 | #define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) | ||
| 373 | #define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) | ||
| 374 | #define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) | ||
| 375 | #define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) | ||
| 376 | #define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) | ||
| 377 | #define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) | ||
| 378 | #define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) | ||
| 379 | #define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) | ||
| 380 | #define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) | ||
| 381 | #define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) | ||
| 382 | #define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) | ||
| 383 | #define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) | ||
| 384 | #define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) | ||
| 385 | #define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) | ||
| 386 | #define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) | ||
| 387 | #define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) | ||
| 388 | #define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) | ||
| 389 | #define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) | ||
| 390 | #define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) | ||
| 391 | #define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) | ||
| 392 | #define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) | ||
| 393 | #define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) | ||
| 394 | #define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) | ||
| 395 | #define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) | ||
| 396 | #define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) | ||
| 397 | #define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) | ||
| 398 | #define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) | ||
| 399 | #define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) | ||
| 400 | #define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) | ||
| 401 | #define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) | ||
| 402 | #define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) | ||
| 403 | |||
| 404 | #define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) | ||
| 405 | #define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) | ||
| 406 | #define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) | ||
| 407 | #define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) | ||
| 408 | #define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) | ||
| 409 | #define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) | ||
| 410 | #define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) | ||
| 411 | |||
| 412 | #define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) | ||
| 413 | #define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) | ||
| 414 | #define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) | ||
| 415 | #define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) | ||
| 416 | #define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) | ||
| 417 | #define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) | ||
| 418 | #define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) | ||
| 419 | #define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) | ||
| 420 | #define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) | ||
| 421 | #define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) | ||
| 422 | #define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) | ||
| 423 | #define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) | ||
| 424 | #define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) | ||
| 425 | #define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START) | ||
| 426 | #define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) | ||
| 427 | #define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) | ||
| 428 | #define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) | ||
| 429 | #define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) | ||
| 430 | #define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) | ||
| 431 | #define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) | ||
| 432 | #define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) | ||
| 433 | #define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) | ||
| 434 | #define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START) | ||
| 435 | |||
| 436 | 360 | ||
| 437 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and | 361 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and |
| 438 | * 16 MPUIO lines */ | 362 | * 16 MPUIO lines */ |
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 4f22e5bb7ff7..39748354ce45 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h | |||
| @@ -49,6 +49,9 @@ | |||
| 49 | 49 | ||
| 50 | #define OMAP34XX_MCBSP1_BASE 0x48074000 | 50 | #define OMAP34XX_MCBSP1_BASE 0x48074000 |
| 51 | #define OMAP34XX_MCBSP2_BASE 0x49022000 | 51 | #define OMAP34XX_MCBSP2_BASE 0x49022000 |
| 52 | #define OMAP34XX_MCBSP2_ST_BASE 0x49028000 | ||
| 53 | #define OMAP34XX_MCBSP3_BASE 0x49024000 | ||
| 54 | #define OMAP34XX_MCBSP3_ST_BASE 0x4902A000 | ||
| 52 | #define OMAP34XX_MCBSP3_BASE 0x49024000 | 55 | #define OMAP34XX_MCBSP3_BASE 0x49024000 |
| 53 | #define OMAP34XX_MCBSP4_BASE 0x49026000 | 56 | #define OMAP34XX_MCBSP4_BASE 0x49026000 |
| 54 | #define OMAP34XX_MCBSP5_BASE 0x48096000 | 57 | #define OMAP34XX_MCBSP5_BASE 0x48096000 |
| @@ -103,8 +106,7 @@ | |||
| 103 | #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX | 106 | #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX |
| 104 | #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX | 107 | #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX |
| 105 | 108 | ||
| 106 | #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 109 | #else |
| 107 | defined(CONFIG_ARCH_OMAP4) | ||
| 108 | 110 | ||
| 109 | #define OMAP_MCBSP_REG_DRR2 0x00 | 111 | #define OMAP_MCBSP_REG_DRR2 0x00 |
| 110 | #define OMAP_MCBSP_REG_DRR1 0x04 | 112 | #define OMAP_MCBSP_REG_DRR1 0x04 |
| @@ -147,6 +149,15 @@ | |||
| 147 | #define OMAP_MCBSP_REG_WAKEUPEN 0xA8 | 149 | #define OMAP_MCBSP_REG_WAKEUPEN 0xA8 |
| 148 | #define OMAP_MCBSP_REG_XCCR 0xAC | 150 | #define OMAP_MCBSP_REG_XCCR 0xAC |
| 149 | #define OMAP_MCBSP_REG_RCCR 0xB0 | 151 | #define OMAP_MCBSP_REG_RCCR 0xB0 |
| 152 | #define OMAP_MCBSP_REG_SSELCR 0xBC | ||
| 153 | |||
| 154 | #define OMAP_ST_REG_REV 0x00 | ||
| 155 | #define OMAP_ST_REG_SYSCONFIG 0x10 | ||
| 156 | #define OMAP_ST_REG_IRQSTATUS 0x18 | ||
| 157 | #define OMAP_ST_REG_IRQENABLE 0x1C | ||
| 158 | #define OMAP_ST_REG_SGAINCR 0x24 | ||
| 159 | #define OMAP_ST_REG_SFIRCR 0x28 | ||
| 160 | #define OMAP_ST_REG_SSELCR 0x2C | ||
| 150 | 161 | ||
| 151 | #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) | 162 | #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) |
| 152 | #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) | 163 | #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) |
| @@ -265,6 +276,24 @@ | |||
| 265 | #define ENAWAKEUP 0x0004 | 276 | #define ENAWAKEUP 0x0004 |
| 266 | #define SOFTRST 0x0002 | 277 | #define SOFTRST 0x0002 |
| 267 | 278 | ||
| 279 | /********************** McBSP SSELCR bit definitions ***********************/ | ||
| 280 | #define SIDETONEEN 0x0400 | ||
| 281 | |||
| 282 | /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/ | ||
| 283 | #define ST_AUTOIDLE 0x0001 | ||
| 284 | |||
| 285 | /********************** McBSP Sidetone SGAINCR bit definitions *************/ | ||
| 286 | #define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */ | ||
| 287 | #define ST_CH0GAIN(value) (value) /* Bits 0:15 */ | ||
| 288 | |||
| 289 | /********************** McBSP Sidetone SFIRCR bit definitions **************/ | ||
| 290 | #define ST_FIRCOEFF(value) (value) /* Bits 0:15 */ | ||
| 291 | |||
| 292 | /********************** McBSP Sidetone SSELCR bit definitions **************/ | ||
| 293 | #define ST_COEFFWRDONE 0x0004 | ||
| 294 | #define ST_COEFFWREN 0x0002 | ||
| 295 | #define ST_SIDETONEEN 0x0001 | ||
| 296 | |||
| 268 | /********************** McBSP DMA operating modes **************************/ | 297 | /********************** McBSP DMA operating modes **************************/ |
| 269 | #define MCBSP_DMA_MODE_ELEMENT 0 | 298 | #define MCBSP_DMA_MODE_ELEMENT 0 |
| 270 | #define MCBSP_DMA_MODE_THRESHOLD 1 | 299 | #define MCBSP_DMA_MODE_THRESHOLD 1 |
| @@ -374,11 +403,23 @@ struct omap_mcbsp_platform_data { | |||
| 374 | u8 dma_rx_sync, dma_tx_sync; | 403 | u8 dma_rx_sync, dma_tx_sync; |
| 375 | u16 rx_irq, tx_irq; | 404 | u16 rx_irq, tx_irq; |
| 376 | struct omap_mcbsp_ops *ops; | 405 | struct omap_mcbsp_ops *ops; |
| 377 | #ifdef CONFIG_ARCH_OMAP34XX | 406 | #ifdef CONFIG_ARCH_OMAP3 |
| 407 | /* Sidetone block for McBSP 2 and 3 */ | ||
| 408 | unsigned long phys_base_st; | ||
| 378 | u16 buffer_size; | 409 | u16 buffer_size; |
| 379 | #endif | 410 | #endif |
| 380 | }; | 411 | }; |
| 381 | 412 | ||
| 413 | struct omap_mcbsp_st_data { | ||
| 414 | void __iomem *io_base_st; | ||
| 415 | bool running; | ||
| 416 | bool enabled; | ||
| 417 | s16 taps[128]; /* Sidetone filter coefficients */ | ||
| 418 | int nr_taps; /* Number of filter coefficients in use */ | ||
| 419 | s16 ch0gain; | ||
| 420 | s16 ch1gain; | ||
| 421 | }; | ||
| 422 | |||
| 382 | struct omap_mcbsp { | 423 | struct omap_mcbsp { |
| 383 | struct device *dev; | 424 | struct device *dev; |
| 384 | unsigned long phys_base; | 425 | unsigned long phys_base; |
| @@ -410,20 +451,22 @@ struct omap_mcbsp { | |||
| 410 | struct omap_mcbsp_platform_data *pdata; | 451 | struct omap_mcbsp_platform_data *pdata; |
| 411 | struct clk *iclk; | 452 | struct clk *iclk; |
| 412 | struct clk *fclk; | 453 | struct clk *fclk; |
| 413 | #ifdef CONFIG_ARCH_OMAP34XX | 454 | #ifdef CONFIG_ARCH_OMAP3 |
| 455 | struct omap_mcbsp_st_data *st_data; | ||
| 414 | int dma_op_mode; | 456 | int dma_op_mode; |
| 415 | u16 max_tx_thres; | 457 | u16 max_tx_thres; |
| 416 | u16 max_rx_thres; | 458 | u16 max_rx_thres; |
| 417 | #endif | 459 | #endif |
| 460 | void *reg_cache; | ||
| 418 | }; | 461 | }; |
| 419 | extern struct omap_mcbsp **mcbsp_ptr; | 462 | extern struct omap_mcbsp **mcbsp_ptr; |
| 420 | extern int omap_mcbsp_count; | 463 | extern int omap_mcbsp_count, omap_mcbsp_cache_size; |
| 421 | 464 | ||
| 422 | int omap_mcbsp_init(void); | 465 | int omap_mcbsp_init(void); |
| 423 | void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, | 466 | void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, |
| 424 | int size); | 467 | int size); |
| 425 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); | 468 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); |
| 426 | #ifdef CONFIG_ARCH_OMAP34XX | 469 | #ifdef CONFIG_ARCH_OMAP3 |
| 427 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); | 470 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); |
| 428 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); | 471 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); |
| 429 | u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); | 472 | u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); |
| @@ -459,4 +502,21 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf); | |||
| 459 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf); | 502 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf); |
| 460 | int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); | 503 | int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); |
| 461 | 504 | ||
| 505 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 506 | /* Sidetone specific API */ | ||
| 507 | int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); | ||
| 508 | int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); | ||
| 509 | int omap_st_enable(unsigned int id); | ||
| 510 | int omap_st_disable(unsigned int id); | ||
| 511 | int omap_st_is_enabled(unsigned int id); | ||
| 512 | #else | ||
| 513 | static inline int omap_st_set_chgain(unsigned int id, int channel, | ||
| 514 | s16 chgain) { return 0; } | ||
| 515 | static inline int omap_st_get_chgain(unsigned int id, int channel, | ||
| 516 | s16 *chgain) { return 0; } | ||
| 517 | static inline int omap_st_enable(unsigned int id) { return 0; } | ||
| 518 | static inline int omap_st_disable(unsigned int id) { return 0; } | ||
| 519 | static inline int omap_st_is_enabled(unsigned int id) { return 0; } | ||
| 520 | #endif | ||
| 521 | |||
| 462 | #endif | 522 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h index 3325f7b49eaa..d5306bee44b2 100644 --- a/arch/arm/plat-omap/include/plat/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h | |||
| @@ -38,8 +38,7 @@ | |||
| 38 | */ | 38 | */ |
| 39 | #if defined(CONFIG_ARCH_OMAP1) | 39 | #if defined(CONFIG_ARCH_OMAP1) |
| 40 | #define PHYS_OFFSET UL(0x10000000) | 40 | #define PHYS_OFFSET UL(0x10000000) |
| 41 | #elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 41 | #else |
| 42 | defined(CONFIG_ARCH_OMAP4) | ||
| 43 | #define PHYS_OFFSET UL(0x80000000) | 42 | #define PHYS_OFFSET UL(0x80000000) |
| 44 | #endif | 43 | #endif |
| 45 | 44 | ||
diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h index 3122bf68c7ce..4a970ec62dd1 100644 --- a/arch/arm/plat-omap/include/plat/menelaus.h +++ b/arch/arm/plat-omap/include/plat/menelaus.h | |||
| @@ -40,7 +40,7 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); | |||
| 40 | 40 | ||
| 41 | extern int menelaus_set_regulator_sleep(int enable, u32 val); | 41 | extern int menelaus_set_regulator_sleep(int enable, u32 val); |
| 42 | 42 | ||
| 43 | #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) | 43 | #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS) |
| 44 | #define omap_has_menelaus() 1 | 44 | #define omap_has_menelaus() 1 |
| 45 | #else | 45 | #else |
| 46 | #define omap_has_menelaus() 0 | 46 | #define omap_has_menelaus() 0 |
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 29937137bf3e..a1bac07c89eb 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h | |||
| @@ -55,12 +55,12 @@ struct omap_mmc_platform_data { | |||
| 55 | unsigned int max_freq; | 55 | unsigned int max_freq; |
| 56 | 56 | ||
| 57 | /* switch the bus to a new slot */ | 57 | /* switch the bus to a new slot */ |
| 58 | int (* switch_slot)(struct device *dev, int slot); | 58 | int (*switch_slot)(struct device *dev, int slot); |
| 59 | /* initialize board-specific MMC functionality, can be NULL if | 59 | /* initialize board-specific MMC functionality, can be NULL if |
| 60 | * not supported */ | 60 | * not supported */ |
| 61 | int (* init)(struct device *dev); | 61 | int (*init)(struct device *dev); |
| 62 | void (* cleanup)(struct device *dev); | 62 | void (*cleanup)(struct device *dev); |
| 63 | void (* shutdown)(struct device *dev); | 63 | void (*shutdown)(struct device *dev); |
| 64 | 64 | ||
| 65 | /* To handle board related suspend/resume functionality for MMC */ | 65 | /* To handle board related suspend/resume functionality for MMC */ |
| 66 | int (*suspend)(struct device *dev, int slot); | 66 | int (*suspend)(struct device *dev, int slot); |
| @@ -96,14 +96,28 @@ struct omap_mmc_platform_data { | |||
| 96 | /* Try to sleep or power off when possible */ | 96 | /* Try to sleep or power off when possible */ |
| 97 | unsigned power_saving:1; | 97 | unsigned power_saving:1; |
| 98 | 98 | ||
| 99 | /* If using power_saving and the MMC power is not to go off */ | ||
| 100 | unsigned no_off:1; | ||
| 101 | |||
| 102 | /* Regulator off remapped to sleep */ | ||
| 103 | unsigned vcc_aux_disable_is_sleep:1; | ||
| 104 | |||
| 99 | int switch_pin; /* gpio (card detect) */ | 105 | int switch_pin; /* gpio (card detect) */ |
| 100 | int gpio_wp; /* gpio (write protect) */ | 106 | int gpio_wp; /* gpio (write protect) */ |
| 101 | 107 | ||
| 102 | int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); | 108 | int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); |
| 103 | int (* set_power)(struct device *dev, int slot, int power_on, int vdd); | 109 | int (*set_power)(struct device *dev, int slot, |
| 104 | int (* get_ro)(struct device *dev, int slot); | 110 | int power_on, int vdd); |
| 111 | int (*get_ro)(struct device *dev, int slot); | ||
| 105 | int (*set_sleep)(struct device *dev, int slot, int sleep, | 112 | int (*set_sleep)(struct device *dev, int slot, int sleep, |
| 106 | int vdd, int cardsleep); | 113 | int vdd, int cardsleep); |
| 114 | void (*remux)(struct device *dev, int slot, int power_on); | ||
| 115 | /* Call back before enabling / disabling regulators */ | ||
| 116 | void (*before_set_reg)(struct device *dev, int slot, | ||
| 117 | int power_on, int vdd); | ||
| 118 | /* Call back after enabling / disabling regulators */ | ||
| 119 | void (*after_set_reg)(struct device *dev, int slot, | ||
| 120 | int power_on, int vdd); | ||
| 107 | 121 | ||
| 108 | /* return MMC cover switch state, can be NULL if not supported. | 122 | /* return MMC cover switch state, can be NULL if not supported. |
| 109 | * | 123 | * |
| @@ -111,14 +125,14 @@ struct omap_mmc_platform_data { | |||
| 111 | * 0 - closed | 125 | * 0 - closed |
| 112 | * 1 - open | 126 | * 1 - open |
| 113 | */ | 127 | */ |
| 114 | int (* get_cover_state)(struct device *dev, int slot); | 128 | int (*get_cover_state)(struct device *dev, int slot); |
| 115 | 129 | ||
| 116 | const char *name; | 130 | const char *name; |
| 117 | u32 ocr_mask; | 131 | u32 ocr_mask; |
| 118 | 132 | ||
| 119 | /* Card detection IRQs */ | 133 | /* Card detection IRQs */ |
| 120 | int card_detect_irq; | 134 | int card_detect_irq; |
| 121 | int (* card_detect)(int irq); | 135 | int (*card_detect)(struct device *dev, int slot); |
| 122 | 136 | ||
| 123 | unsigned int ban_openended:1; | 137 | unsigned int ban_openended:1; |
| 124 | 138 | ||
| @@ -126,7 +140,8 @@ struct omap_mmc_platform_data { | |||
| 126 | }; | 140 | }; |
| 127 | 141 | ||
| 128 | /* called from board-specific card detection service routine */ | 142 | /* called from board-specific card detection service routine */ |
| 129 | extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); | 143 | extern void omap_mmc_notify_cover_event(struct device *dev, int slot, |
| 144 | int is_closed); | ||
| 130 | 145 | ||
| 131 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ | 146 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
| 132 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | 147 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h new file mode 100644 index 000000000000..f235d32cd942 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/multi.h | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * Support for compiling in multiple OMAP processors | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __PLAT_OMAP_MULTI_H | ||
| 23 | #define __PLAT_OMAP_MULTI_H | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Test if multicore OMAP support is needed | ||
| 27 | */ | ||
| 28 | #undef MULTI_OMAP1 | ||
| 29 | #undef MULTI_OMAP2 | ||
| 30 | #undef OMAP_NAME | ||
| 31 | |||
| 32 | #ifdef CONFIG_ARCH_OMAP730 | ||
| 33 | # ifdef OMAP_NAME | ||
| 34 | # undef MULTI_OMAP1 | ||
| 35 | # define MULTI_OMAP1 | ||
| 36 | # else | ||
| 37 | # define OMAP_NAME omap730 | ||
| 38 | # endif | ||
| 39 | #endif | ||
| 40 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 41 | # ifdef OMAP_NAME | ||
| 42 | # undef MULTI_OMAP1 | ||
| 43 | # define MULTI_OMAP1 | ||
| 44 | # else | ||
| 45 | # define OMAP_NAME omap850 | ||
| 46 | # endif | ||
| 47 | #endif | ||
| 48 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 49 | # ifdef OMAP_NAME | ||
| 50 | # undef MULTI_OMAP1 | ||
| 51 | # define MULTI_OMAP1 | ||
| 52 | # else | ||
| 53 | # define OMAP_NAME omap1510 | ||
| 54 | # endif | ||
| 55 | #endif | ||
| 56 | #ifdef CONFIG_ARCH_OMAP16XX | ||
| 57 | # ifdef OMAP_NAME | ||
| 58 | # undef MULTI_OMAP1 | ||
| 59 | # define MULTI_OMAP1 | ||
| 60 | # else | ||
| 61 | # define OMAP_NAME omap16xx | ||
| 62 | # endif | ||
| 63 | #endif | ||
| 64 | #if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) | ||
| 65 | # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) | ||
| 66 | # error "OMAP1 and OMAP2 can't be selected at the same time" | ||
| 67 | # endif | ||
| 68 | #endif | ||
| 69 | #ifdef CONFIG_ARCH_OMAP2420 | ||
| 70 | # ifdef OMAP_NAME | ||
| 71 | # undef MULTI_OMAP2 | ||
| 72 | # define MULTI_OMAP2 | ||
| 73 | # else | ||
| 74 | # define OMAP_NAME omap2420 | ||
| 75 | # endif | ||
| 76 | #endif | ||
| 77 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 78 | # ifdef OMAP_NAME | ||
| 79 | # undef MULTI_OMAP2 | ||
| 80 | # define MULTI_OMAP2 | ||
| 81 | # else | ||
| 82 | # define OMAP_NAME omap2430 | ||
| 83 | # endif | ||
| 84 | #endif | ||
| 85 | #ifdef CONFIG_ARCH_OMAP3430 | ||
| 86 | # ifdef OMAP_NAME | ||
| 87 | # undef MULTI_OMAP2 | ||
| 88 | # define MULTI_OMAP2 | ||
| 89 | # else | ||
| 90 | # define OMAP_NAME omap3430 | ||
| 91 | # endif | ||
| 92 | #endif | ||
| 93 | |||
| 94 | #endif /* __PLAT_OMAP_MULTI_H */ | ||
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index 692c90e89ac3..c7472a28ce24 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h | |||
| @@ -135,7 +135,7 @@ struct pin_config { | |||
| 135 | const unsigned int mux_reg; | 135 | const unsigned int mux_reg; |
| 136 | unsigned char debug; | 136 | unsigned char debug; |
| 137 | 137 | ||
| 138 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) | 138 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) |
| 139 | const unsigned char mask_offset; | 139 | const unsigned char mask_offset; |
| 140 | const unsigned char mask; | 140 | const unsigned char mask; |
| 141 | 141 | ||
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 631a7bed1eef..6ba88d2630d9 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h | |||
| @@ -15,10 +15,18 @@ struct omap_nand_platform_data { | |||
| 15 | int cs; | 15 | int cs; |
| 16 | int gpio_irq; | 16 | int gpio_irq; |
| 17 | struct mtd_partition *parts; | 17 | struct mtd_partition *parts; |
| 18 | struct gpmc_timings *gpmc_t; | ||
| 18 | int nr_parts; | 19 | int nr_parts; |
| 19 | int (*nand_setup)(void __iomem *); | 20 | int (*nand_setup)(void); |
| 20 | int (*dev_ready)(struct omap_nand_platform_data *); | 21 | int (*dev_ready)(struct omap_nand_platform_data *); |
| 21 | int dma_channel; | 22 | int dma_channel; |
| 23 | unsigned long phys_base; | ||
| 22 | void __iomem *gpmc_cs_baseaddr; | 24 | void __iomem *gpmc_cs_baseaddr; |
| 23 | void __iomem *gpmc_baseaddr; | 25 | void __iomem *gpmc_baseaddr; |
| 26 | int devsize; | ||
| 24 | }; | 27 | }; |
| 28 | |||
| 29 | /* size (4 KiB) for IO mapping */ | ||
| 30 | #define NAND_IO_SIZE SZ_4K | ||
| 31 | |||
| 32 | extern int gpmc_nand_init(struct omap_nand_platform_data *d); | ||
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h index 7560b4d583a3..e69e1d857b45 100644 --- a/arch/arm/plat-omap/include/plat/omap16xx.h +++ b/arch/arm/plat-omap/include/plat/omap16xx.h | |||
| @@ -125,43 +125,43 @@ | |||
| 125 | #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) | 125 | #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) |
| 126 | 126 | ||
| 127 | /* UART3 Registers Mapping through MPU bus */ | 127 | /* UART3 Registers Mapping through MPU bus */ |
| 128 | #define UART3_RHR (OMAP_UART3_BASE + 0) | 128 | #define UART3_RHR (OMAP1_UART3_BASE + 0) |
| 129 | #define UART3_THR (OMAP_UART3_BASE + 0) | 129 | #define UART3_THR (OMAP1_UART3_BASE + 0) |
| 130 | #define UART3_DLL (OMAP_UART3_BASE + 0) | 130 | #define UART3_DLL (OMAP1_UART3_BASE + 0) |
| 131 | #define UART3_IER (OMAP_UART3_BASE + 4) | 131 | #define UART3_IER (OMAP1_UART3_BASE + 4) |
| 132 | #define UART3_DLH (OMAP_UART3_BASE + 4) | 132 | #define UART3_DLH (OMAP1_UART3_BASE + 4) |
| 133 | #define UART3_IIR (OMAP_UART3_BASE + 8) | 133 | #define UART3_IIR (OMAP1_UART3_BASE + 8) |
| 134 | #define UART3_FCR (OMAP_UART3_BASE + 8) | 134 | #define UART3_FCR (OMAP1_UART3_BASE + 8) |
| 135 | #define UART3_EFR (OMAP_UART3_BASE + 8) | 135 | #define UART3_EFR (OMAP1_UART3_BASE + 8) |
| 136 | #define UART3_LCR (OMAP_UART3_BASE + 0x0C) | 136 | #define UART3_LCR (OMAP1_UART3_BASE + 0x0C) |
| 137 | #define UART3_MCR (OMAP_UART3_BASE + 0x10) | 137 | #define UART3_MCR (OMAP1_UART3_BASE + 0x10) |
| 138 | #define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10) | 138 | #define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10) |
| 139 | #define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14) | 139 | #define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14) |
| 140 | #define UART3_LSR (OMAP_UART3_BASE + 0x14) | 140 | #define UART3_LSR (OMAP1_UART3_BASE + 0x14) |
| 141 | #define UART3_TCR (OMAP_UART3_BASE + 0x18) | 141 | #define UART3_TCR (OMAP1_UART3_BASE + 0x18) |
| 142 | #define UART3_MSR (OMAP_UART3_BASE + 0x18) | 142 | #define UART3_MSR (OMAP1_UART3_BASE + 0x18) |
| 143 | #define UART3_XOFF1 (OMAP_UART3_BASE + 0x18) | 143 | #define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18) |
| 144 | #define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C) | 144 | #define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C) |
| 145 | #define UART3_SPR (OMAP_UART3_BASE + 0x1C) | 145 | #define UART3_SPR (OMAP1_UART3_BASE + 0x1C) |
| 146 | #define UART3_TLR (OMAP_UART3_BASE + 0x1C) | 146 | #define UART3_TLR (OMAP1_UART3_BASE + 0x1C) |
| 147 | #define UART3_MDR1 (OMAP_UART3_BASE + 0x20) | 147 | #define UART3_MDR1 (OMAP1_UART3_BASE + 0x20) |
| 148 | #define UART3_MDR2 (OMAP_UART3_BASE + 0x24) | 148 | #define UART3_MDR2 (OMAP1_UART3_BASE + 0x24) |
| 149 | #define UART3_SFLSR (OMAP_UART3_BASE + 0x28) | 149 | #define UART3_SFLSR (OMAP1_UART3_BASE + 0x28) |
| 150 | #define UART3_TXFLL (OMAP_UART3_BASE + 0x28) | 150 | #define UART3_TXFLL (OMAP1_UART3_BASE + 0x28) |
| 151 | #define UART3_RESUME (OMAP_UART3_BASE + 0x2C) | 151 | #define UART3_RESUME (OMAP1_UART3_BASE + 0x2C) |
| 152 | #define UART3_TXFLH (OMAP_UART3_BASE + 0x2C) | 152 | #define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C) |
| 153 | #define UART3_SFREGL (OMAP_UART3_BASE + 0x30) | 153 | #define UART3_SFREGL (OMAP1_UART3_BASE + 0x30) |
| 154 | #define UART3_RXFLL (OMAP_UART3_BASE + 0x30) | 154 | #define UART3_RXFLL (OMAP1_UART3_BASE + 0x30) |
| 155 | #define UART3_SFREGH (OMAP_UART3_BASE + 0x34) | 155 | #define UART3_SFREGH (OMAP1_UART3_BASE + 0x34) |
| 156 | #define UART3_RXFLH (OMAP_UART3_BASE + 0x34) | 156 | #define UART3_RXFLH (OMAP1_UART3_BASE + 0x34) |
| 157 | #define UART3_BLR (OMAP_UART3_BASE + 0x38) | 157 | #define UART3_BLR (OMAP1_UART3_BASE + 0x38) |
| 158 | #define UART3_ACREG (OMAP_UART3_BASE + 0x3C) | 158 | #define UART3_ACREG (OMAP1_UART3_BASE + 0x3C) |
| 159 | #define UART3_DIV16 (OMAP_UART3_BASE + 0x3C) | 159 | #define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C) |
| 160 | #define UART3_SCR (OMAP_UART3_BASE + 0x40) | 160 | #define UART3_SCR (OMAP1_UART3_BASE + 0x40) |
| 161 | #define UART3_SSR (OMAP_UART3_BASE + 0x44) | 161 | #define UART3_SSR (OMAP1_UART3_BASE + 0x44) |
| 162 | #define UART3_EBLR (OMAP_UART3_BASE + 0x48) | 162 | #define UART3_EBLR (OMAP1_UART3_BASE + 0x48) |
| 163 | #define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C) | 163 | #define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C) |
| 164 | #define UART3_MVR (OMAP_UART3_BASE + 0x50) | 164 | #define UART3_MVR (OMAP1_UART3_BASE + 0x50) |
| 165 | 165 | ||
| 166 | /* | 166 | /* |
| 167 | * --------------------------------------------------------------------------- | 167 | * --------------------------------------------------------------------------- |
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 696edfc145a6..7055672a8c68 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h | |||
| @@ -23,8 +23,8 @@ | |||
| 23 | * | 23 | * |
| 24 | */ | 24 | */ |
| 25 | 25 | ||
| 26 | #ifndef __ASM_ARCH_OMAP24XX_H | 26 | #ifndef __ASM_ARCH_OMAP2_H |
| 27 | #define __ASM_ARCH_OMAP24XX_H | 27 | #define __ASM_ARCH_OMAP2_H |
| 28 | 28 | ||
| 29 | /* | 29 | /* |
| 30 | * Please place only base defines here and put the rest in device | 30 | * Please place only base defines here and put the rest in device |
| @@ -85,5 +85,5 @@ | |||
| 85 | #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) | 85 | #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) |
| 86 | #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) | 86 | #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) |
| 87 | 87 | ||
| 88 | #endif /* __ASM_ARCH_OMAP24XX_H */ | 88 | #endif /* __ASM_ARCH_OMAP2_H */ |
| 89 | 89 | ||
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 077f05979f86..2845fdc658b0 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h | |||
| @@ -21,8 +21,8 @@ | |||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ | 22 | */ |
| 23 | 23 | ||
| 24 | #ifndef __ASM_ARCH_OMAP34XX_H | 24 | #ifndef __ASM_ARCH_OMAP3_H |
| 25 | #define __ASM_ARCH_OMAP34XX_H | 25 | #define __ASM_ARCH_OMAP3_H |
| 26 | 26 | ||
| 27 | /* | 27 | /* |
| 28 | * Please place only base defines here and put the rest in device | 28 | * Please place only base defines here and put the rest in device |
| @@ -82,5 +82,5 @@ | |||
| 82 | 82 | ||
| 83 | #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) | 83 | #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) |
| 84 | 84 | ||
| 85 | #endif /* __ASM_ARCH_OMAP34XX_H */ | 85 | #endif /* __ASM_ARCH_OMAP3_H */ |
| 86 | 86 | ||
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index c7d628ecb467..2302474a3748 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h | |||
| @@ -42,8 +42,11 @@ | |||
| 42 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 | 42 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 |
| 43 | #define OMAP44XX_L2CACHE_BASE 0x48242000 | 43 | #define OMAP44XX_L2CACHE_BASE 0x48242000 |
| 44 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 | 44 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 |
| 45 | #define OMAP44XX_MCPDM_BASE 0x40132000 | ||
| 46 | #define OMAP44XX_MCPDM_L3_BASE 0x49032000 | ||
| 45 | 47 | ||
| 46 | #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) | 48 | #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) |
| 49 | #define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) | ||
| 47 | 50 | ||
| 48 | #endif /* __ASM_ARCH_OMAP44XX_H */ | 51 | #endif /* __ASM_ARCH_OMAP44XX_H */ |
| 49 | 52 | ||
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index dc1fac1d805c..3694b622c4ac 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h | |||
| @@ -62,6 +62,7 @@ | |||
| 62 | * | 62 | * |
| 63 | */ | 63 | */ |
| 64 | struct omap_device { | 64 | struct omap_device { |
| 65 | u32 magic; | ||
| 65 | struct platform_device pdev; | 66 | struct platform_device pdev; |
| 66 | struct omap_hwmod **hwmods; | 67 | struct omap_hwmod **hwmods; |
| 67 | struct omap_device_pm_latency *pm_lats; | 68 | struct omap_device_pm_latency *pm_lats; |
| @@ -81,6 +82,7 @@ int omap_device_shutdown(struct platform_device *pdev); | |||
| 81 | 82 | ||
| 82 | /* Core code interface */ | 83 | /* Core code interface */ |
| 83 | 84 | ||
| 85 | bool omap_device_is_valid(struct omap_device *od); | ||
| 84 | int omap_device_count_resources(struct omap_device *od); | 86 | int omap_device_count_resources(struct omap_device *od); |
| 85 | int omap_device_fill_resources(struct omap_device *od, struct resource *res); | 87 | int omap_device_fill_resources(struct omap_device *od, struct resource *res); |
| 86 | 88 | ||
| @@ -88,15 +90,16 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
| 88 | struct omap_hwmod *oh, void *pdata, | 90 | struct omap_hwmod *oh, void *pdata, |
| 89 | int pdata_len, | 91 | int pdata_len, |
| 90 | struct omap_device_pm_latency *pm_lats, | 92 | struct omap_device_pm_latency *pm_lats, |
| 91 | int pm_lats_cnt); | 93 | int pm_lats_cnt, int is_early_device); |
| 92 | 94 | ||
| 93 | struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | 95 | struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, |
| 94 | struct omap_hwmod **oh, int oh_cnt, | 96 | struct omap_hwmod **oh, int oh_cnt, |
| 95 | void *pdata, int pdata_len, | 97 | void *pdata, int pdata_len, |
| 96 | struct omap_device_pm_latency *pm_lats, | 98 | struct omap_device_pm_latency *pm_lats, |
| 97 | int pm_lats_cnt); | 99 | int pm_lats_cnt, int is_early_device); |
| 98 | 100 | ||
| 99 | int omap_device_register(struct omap_device *od); | 101 | int omap_device_register(struct omap_device *od); |
| 102 | int omap_early_device_register(struct omap_device *od); | ||
| 100 | 103 | ||
| 101 | /* OMAP PM interface */ | 104 | /* OMAP PM interface */ |
| 102 | int omap_device_align_pm_lat(struct platform_device *pdev, | 105 | int omap_device_align_pm_lat(struct platform_device *pdev, |
| @@ -131,11 +134,15 @@ int omap_device_enable_clocks(struct omap_device *od); | |||
| 131 | */ | 134 | */ |
| 132 | struct omap_device_pm_latency { | 135 | struct omap_device_pm_latency { |
| 133 | u32 deactivate_lat; | 136 | u32 deactivate_lat; |
| 137 | u32 deactivate_lat_worst; | ||
| 134 | int (*deactivate_func)(struct omap_device *od); | 138 | int (*deactivate_func)(struct omap_device *od); |
| 135 | u32 activate_lat; | 139 | u32 activate_lat; |
| 140 | u32 activate_lat_worst; | ||
| 136 | int (*activate_func)(struct omap_device *od); | 141 | int (*activate_func)(struct omap_device *od); |
| 142 | u32 flags; | ||
| 137 | }; | 143 | }; |
| 138 | 144 | ||
| 145 | #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) | ||
| 139 | 146 | ||
| 140 | /* Get omap_device pointer from platform_device pointer */ | 147 | /* Get omap_device pointer from platform_device pointer */ |
| 141 | #define to_omap_device(x) container_of((x), struct omap_device, pdev) | 148 | #define to_omap_device(x) container_of((x), struct omap_device, pdev) |
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 33933256a226..440b4164f2f6 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Paul Walmsley | 5 | * Paul Walmsley |
| 6 | * | 6 | * |
| 7 | * Created in collaboration with (alphabetical order): Benoit Cousson, | 7 | * Created in collaboration with (alphabetical order): Benoît Cousson, |
| 8 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari | 8 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari |
| 9 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff | 9 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff |
| 10 | * | 10 | * |
| @@ -33,25 +33,42 @@ | |||
| 33 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | 33 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H |
| 34 | 34 | ||
| 35 | #include <linux/kernel.h> | 35 | #include <linux/kernel.h> |
| 36 | #include <linux/list.h> | ||
| 36 | #include <linux/ioport.h> | 37 | #include <linux/ioport.h> |
| 37 | |||
| 38 | #include <plat/cpu.h> | 38 | #include <plat/cpu.h> |
| 39 | 39 | ||
| 40 | struct omap_device; | 40 | struct omap_device; |
| 41 | 41 | ||
| 42 | /* OCP SYSCONFIG bit shifts/masks */ | 42 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; |
| 43 | #define SYSC_MIDLEMODE_SHIFT 12 | 43 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; |
| 44 | #define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) | 44 | |
| 45 | #define SYSC_CLOCKACTIVITY_SHIFT 8 | 45 | /* |
| 46 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) | 46 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant |
| 47 | #define SYSC_SIDLEMODE_SHIFT 3 | 47 | * with the original PRCM protocol defined for OMAP2420 |
| 48 | #define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) | 48 | */ |
| 49 | #define SYSC_ENAWAKEUP_SHIFT 2 | 49 | #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 |
| 50 | #define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | 50 | #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) |
| 51 | #define SYSC_SOFTRESET_SHIFT 1 | 51 | #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 |
| 52 | #define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | 52 | #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) |
| 53 | #define SYSC_AUTOIDLE_SHIFT 0 | 53 | #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 |
| 54 | #define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | 54 | #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) |
| 55 | #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 | ||
| 56 | #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | ||
| 57 | #define SYSC_TYPE1_SOFTRESET_SHIFT 1 | ||
| 58 | #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | ||
| 59 | #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 | ||
| 60 | #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | ||
| 61 | |||
| 62 | /* | ||
| 63 | * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant | ||
| 64 | * with the new PRCM protocol defined for new OMAP4 IPs. | ||
| 65 | */ | ||
| 66 | #define SYSC_TYPE2_SOFTRESET_SHIFT 0 | ||
| 67 | #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) | ||
| 68 | #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 | ||
| 69 | #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) | ||
| 70 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 | ||
| 71 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) | ||
| 55 | 72 | ||
| 56 | /* OCP SYSSTATUS bit shifts/masks */ | 73 | /* OCP SYSSTATUS bit shifts/masks */ |
| 57 | #define SYSS_RESETDONE_SHIFT 0 | 74 | #define SYSS_RESETDONE_SHIFT 0 |
| @@ -62,7 +79,6 @@ struct omap_device; | |||
| 62 | #define HWMOD_IDLEMODE_NO (1 << 1) | 79 | #define HWMOD_IDLEMODE_NO (1 << 1) |
| 63 | #define HWMOD_IDLEMODE_SMART (1 << 2) | 80 | #define HWMOD_IDLEMODE_SMART (1 << 2) |
| 64 | 81 | ||
| 65 | |||
| 66 | /** | 82 | /** |
| 67 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod | 83 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod |
| 68 | * @name: name of the IRQ channel (module local name) | 84 | * @name: name of the IRQ channel (module local name) |
| @@ -94,8 +110,7 @@ struct omap_hwmod_dma_info { | |||
| 94 | /** | 110 | /** |
| 95 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod | 111 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod |
| 96 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() | 112 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() |
| 97 | * @clkdev_dev_id: opt clock: clkdev dev_id string | 113 | * @clk: opt clock: OMAP clock name |
| 98 | * @clkdev_con_id: opt clock: clkdev con_id string | ||
| 99 | * @_clk: pointer to the struct clk (filled in at runtime) | 114 | * @_clk: pointer to the struct clk (filled in at runtime) |
| 100 | * | 115 | * |
| 101 | * The module's interface clock and main functional clock should not | 116 | * The module's interface clock and main functional clock should not |
| @@ -103,8 +118,7 @@ struct omap_hwmod_dma_info { | |||
| 103 | */ | 118 | */ |
| 104 | struct omap_hwmod_opt_clk { | 119 | struct omap_hwmod_opt_clk { |
| 105 | const char *role; | 120 | const char *role; |
| 106 | const char *clkdev_dev_id; | 121 | const char *clk; |
| 107 | const char *clkdev_con_id; | ||
| 108 | struct clk *_clk; | 122 | struct clk *_clk; |
| 109 | }; | 123 | }; |
| 110 | 124 | ||
| @@ -171,8 +185,7 @@ struct omap_hwmod_addr_space { | |||
| 171 | * @master: struct omap_hwmod that initiates OCP transactions on this link | 185 | * @master: struct omap_hwmod that initiates OCP transactions on this link |
| 172 | * @slave: struct omap_hwmod that responds to OCP transactions on this link | 186 | * @slave: struct omap_hwmod that responds to OCP transactions on this link |
| 173 | * @addr: address space associated with this link | 187 | * @addr: address space associated with this link |
| 174 | * @clkdev_dev_id: interface clock: clkdev dev_id string | 188 | * @clk: interface clock: OMAP clock name |
| 175 | * @clkdev_con_id: interface clock: clkdev con_id string | ||
| 176 | * @_clk: pointer to the interface struct clk (filled in at runtime) | 189 | * @_clk: pointer to the interface struct clk (filled in at runtime) |
| 177 | * @fw: interface firewall data | 190 | * @fw: interface firewall data |
| 178 | * @addr_cnt: ARRAY_SIZE(@addr) | 191 | * @addr_cnt: ARRAY_SIZE(@addr) |
| @@ -191,8 +204,7 @@ struct omap_hwmod_ocp_if { | |||
| 191 | struct omap_hwmod *master; | 204 | struct omap_hwmod *master; |
| 192 | struct omap_hwmod *slave; | 205 | struct omap_hwmod *slave; |
| 193 | struct omap_hwmod_addr_space *addr; | 206 | struct omap_hwmod_addr_space *addr; |
| 194 | const char *clkdev_dev_id; | 207 | const char *clk; |
| 195 | const char *clkdev_con_id; | ||
| 196 | struct clk *_clk; | 208 | struct clk *_clk; |
| 197 | union { | 209 | union { |
| 198 | struct omap_hwmod_omap2_firewall omap2; | 210 | struct omap_hwmod_omap2_firewall omap2; |
| @@ -236,7 +248,25 @@ struct omap_hwmod_ocp_if { | |||
| 236 | #define CLOCKACT_TEST_NONE 0x3 | 248 | #define CLOCKACT_TEST_NONE 0x3 |
| 237 | 249 | ||
| 238 | /** | 250 | /** |
| 239 | * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data | 251 | * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. |
| 252 | * @midle_shift: Offset of the midle bit | ||
| 253 | * @clkact_shift: Offset of the clockactivity bit | ||
| 254 | * @sidle_shift: Offset of the sidle bit | ||
| 255 | * @enwkup_shift: Offset of the enawakeup bit | ||
| 256 | * @srst_shift: Offset of the softreset bit | ||
| 257 | * @autoidle_shift: Offset of the autoidle bit | ||
| 258 | */ | ||
| 259 | struct omap_hwmod_sysc_fields { | ||
| 260 | u8 midle_shift; | ||
| 261 | u8 clkact_shift; | ||
| 262 | u8 sidle_shift; | ||
| 263 | u8 enwkup_shift; | ||
| 264 | u8 srst_shift; | ||
| 265 | u8 autoidle_shift; | ||
| 266 | }; | ||
| 267 | |||
| 268 | /** | ||
| 269 | * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data | ||
| 240 | * @rev_offs: IP block revision register offset (from module base addr) | 270 | * @rev_offs: IP block revision register offset (from module base addr) |
| 241 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) | 271 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) |
| 242 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) | 272 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) |
| @@ -252,14 +282,22 @@ struct omap_hwmod_ocp_if { | |||
| 252 | * been associated with the clocks marked in @clockact. This field is | 282 | * been associated with the clocks marked in @clockact. This field is |
| 253 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) | 283 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) |
| 254 | * | 284 | * |
| 285 | * @sysc_fields: structure containing the offset positions of various bits in | ||
| 286 | * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or | ||
| 287 | * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on | ||
| 288 | * whether the device ip is compliant with the original PRCM protocol | ||
| 289 | * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. | ||
| 290 | * If the device follows a different scheme for the sysconfig register , | ||
| 291 | * then this field has to be populated with the correct offset structure. | ||
| 255 | */ | 292 | */ |
| 256 | struct omap_hwmod_sysconfig { | 293 | struct omap_hwmod_class_sysconfig { |
| 257 | u16 rev_offs; | 294 | u16 rev_offs; |
| 258 | u16 sysc_offs; | 295 | u16 sysc_offs; |
| 259 | u16 syss_offs; | 296 | u16 syss_offs; |
| 260 | u8 idlemodes; | 297 | u8 idlemodes; |
| 261 | u8 sysc_flags; | 298 | u8 sysc_flags; |
| 262 | u8 clockact; | 299 | u8 clockact; |
| 300 | struct omap_hwmod_sysc_fields *sysc_fields; | ||
| 263 | }; | 301 | }; |
| 264 | 302 | ||
| 265 | /** | 303 | /** |
| @@ -352,19 +390,33 @@ struct omap_hwmod_omap4_prcm { | |||
| 352 | #define _HWMOD_STATE_DISABLED 6 | 390 | #define _HWMOD_STATE_DISABLED 6 |
| 353 | 391 | ||
| 354 | /** | 392 | /** |
| 393 | * struct omap_hwmod_class - the type of an IP block | ||
| 394 | * @name: name of the hwmod_class | ||
| 395 | * @sysc: device SYSCONFIG/SYSSTATUS register data | ||
| 396 | * @rev: revision of the IP class | ||
| 397 | * | ||
| 398 | * Represent the class of a OMAP hardware "modules" (e.g. timer, | ||
| 399 | * smartreflex, gpio, uart...) | ||
| 400 | */ | ||
| 401 | struct omap_hwmod_class { | ||
| 402 | const char *name; | ||
| 403 | struct omap_hwmod_class_sysconfig *sysc; | ||
| 404 | u32 rev; | ||
| 405 | }; | ||
| 406 | |||
| 407 | /** | ||
| 355 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) | 408 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) |
| 356 | * @name: name of the hwmod | 409 | * @name: name of the hwmod |
| 410 | * @class: struct omap_hwmod_class * to the class of this hwmod | ||
| 357 | * @od: struct omap_device currently associated with this hwmod (internal use) | 411 | * @od: struct omap_device currently associated with this hwmod (internal use) |
| 358 | * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) | 412 | * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) |
| 359 | * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) | 413 | * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) |
| 360 | * @prcm: PRCM data pertaining to this hwmod | 414 | * @prcm: PRCM data pertaining to this hwmod |
| 361 | * @clkdev_dev_id: main clock: clkdev dev_id string | 415 | * @main_clk: main clock: OMAP clock name |
| 362 | * @clkdev_con_id: main clock: clkdev con_id string | ||
| 363 | * @_clk: pointer to the main struct clk (filled in at runtime) | 416 | * @_clk: pointer to the main struct clk (filled in at runtime) |
| 364 | * @opt_clks: other device clocks that drivers can request (0..*) | 417 | * @opt_clks: other device clocks that drivers can request (0..*) |
| 365 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on | 418 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on |
| 366 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on | 419 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on |
| 367 | * @sysconfig: device SYSCONFIG/SYSSTATUS register data | ||
| 368 | * @dev_attr: arbitrary device attributes that can be passed to the driver | 420 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
| 369 | * @_sysc_cache: internal-use hwmod flags | 421 | * @_sysc_cache: internal-use hwmod flags |
| 370 | * @_rt_va: cached register target start address (internal use) | 422 | * @_rt_va: cached register target start address (internal use) |
| @@ -383,16 +435,17 @@ struct omap_hwmod_omap4_prcm { | |||
| 383 | * @omap_chip: OMAP chips this hwmod is present on | 435 | * @omap_chip: OMAP chips this hwmod is present on |
| 384 | * @node: list node for hwmod list (internal use) | 436 | * @node: list node for hwmod list (internal use) |
| 385 | * | 437 | * |
| 386 | * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main | 438 | * @main_clk refers to this module's "main clock," which for our |
| 387 | * clock," which for our purposes is defined as "the functional clock needed | 439 | * purposes is defined as "the functional clock needed for register |
| 388 | * for register accesses to complete." Modules may not have a main clock if | 440 | * accesses to complete." Modules may not have a main clock if the |
| 389 | * the interface clock also serves as a main clock. | 441 | * interface clock also serves as a main clock. |
| 390 | * | 442 | * |
| 391 | * Parameter names beginning with an underscore are managed internally by | 443 | * Parameter names beginning with an underscore are managed internally by |
| 392 | * the omap_hwmod code and should not be set during initialization. | 444 | * the omap_hwmod code and should not be set during initialization. |
| 393 | */ | 445 | */ |
| 394 | struct omap_hwmod { | 446 | struct omap_hwmod { |
| 395 | const char *name; | 447 | const char *name; |
| 448 | struct omap_hwmod_class *class; | ||
| 396 | struct omap_device *od; | 449 | struct omap_device *od; |
| 397 | struct omap_hwmod_irq_info *mpu_irqs; | 450 | struct omap_hwmod_irq_info *mpu_irqs; |
| 398 | struct omap_hwmod_dma_info *sdma_chs; | 451 | struct omap_hwmod_dma_info *sdma_chs; |
| @@ -400,13 +453,11 @@ struct omap_hwmod { | |||
| 400 | struct omap_hwmod_omap2_prcm omap2; | 453 | struct omap_hwmod_omap2_prcm omap2; |
| 401 | struct omap_hwmod_omap4_prcm omap4; | 454 | struct omap_hwmod_omap4_prcm omap4; |
| 402 | } prcm; | 455 | } prcm; |
| 403 | const char *clkdev_dev_id; | 456 | const char *main_clk; |
| 404 | const char *clkdev_con_id; | ||
| 405 | struct clk *_clk; | 457 | struct clk *_clk; |
| 406 | struct omap_hwmod_opt_clk *opt_clks; | 458 | struct omap_hwmod_opt_clk *opt_clks; |
| 407 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ | 459 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ |
| 408 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ | 460 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ |
| 409 | struct omap_hwmod_sysconfig *sysconfig; | ||
| 410 | void *dev_attr; | 461 | void *dev_attr; |
| 411 | u32 _sysc_cache; | 462 | u32 _sysc_cache; |
| 412 | void __iomem *_rt_va; | 463 | void __iomem *_rt_va; |
| @@ -441,6 +492,8 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh); | |||
| 441 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh); | 492 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh); |
| 442 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh); | 493 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh); |
| 443 | 494 | ||
| 495 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); | ||
| 496 | |||
| 444 | int omap_hwmod_reset(struct omap_hwmod *oh); | 497 | int omap_hwmod_reset(struct omap_hwmod *oh); |
| 445 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); | 498 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); |
| 446 | 499 | ||
| @@ -465,4 +518,17 @@ int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); | |||
| 465 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); | 518 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); |
| 466 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); | 519 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); |
| 467 | 520 | ||
| 521 | int omap_hwmod_for_each_by_class(const char *classname, | ||
| 522 | int (*fn)(struct omap_hwmod *oh, | ||
| 523 | void *user), | ||
| 524 | void *user); | ||
| 525 | |||
| 526 | /* | ||
| 527 | * Chip variant-specific hwmod init routines - XXX should be converted | ||
| 528 | * to use initcalls once the initial boot ordering is straightened out | ||
| 529 | */ | ||
| 530 | extern int omap2420_hwmod_init(void); | ||
| 531 | extern int omap2430_hwmod_init(void); | ||
| 532 | extern int omap3xxx_hwmod_init(void); | ||
| 533 | |||
| 468 | #endif | 534 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 0b960051eaed..d82b2c00d4f1 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP2/3 powerdomain control | 2 | * OMAP2/3 powerdomain control |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-8 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-8 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
| 8 | * | 8 | * |
| @@ -37,6 +37,9 @@ | |||
| 37 | #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ | 37 | #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ |
| 38 | (1 << PWRDM_POWER_RET)) | 38 | (1 << PWRDM_POWER_RET)) |
| 39 | 39 | ||
| 40 | #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ | ||
| 41 | (1 << PWRDM_POWER_ON)) | ||
| 42 | |||
| 40 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) | 43 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) |
| 41 | 44 | ||
| 42 | 45 | ||
| @@ -48,16 +51,16 @@ | |||
| 48 | */ | 51 | */ |
| 49 | 52 | ||
| 50 | /* | 53 | /* |
| 51 | * Number of memory banks that are power-controllable. On OMAP3430, the | 54 | * Number of memory banks that are power-controllable. On OMAP4430, the |
| 52 | * maximum is 4. | 55 | * maximum is 5. |
| 53 | */ | 56 | */ |
| 54 | #define PWRDM_MAX_MEM_BANKS 4 | 57 | #define PWRDM_MAX_MEM_BANKS 5 |
| 55 | 58 | ||
| 56 | /* | 59 | /* |
| 57 | * Maximum number of clockdomains that can be associated with a powerdomain. | 60 | * Maximum number of clockdomains that can be associated with a powerdomain. |
| 58 | * CORE powerdomain on OMAP3 is the worst case | 61 | * CORE powerdomain on OMAP4 is the worst case |
| 59 | */ | 62 | */ |
| 60 | #define PWRDM_MAX_CLKDMS 4 | 63 | #define PWRDM_MAX_CLKDMS 9 |
| 61 | 64 | ||
| 62 | /* XXX A completely arbitrary number. What is reasonable here? */ | 65 | /* XXX A completely arbitrary number. What is reasonable here? */ |
| 63 | #define PWRDM_TRANSITION_BAILOUT 100000 | 66 | #define PWRDM_TRANSITION_BAILOUT 100000 |
| @@ -65,65 +68,40 @@ | |||
| 65 | struct clockdomain; | 68 | struct clockdomain; |
| 66 | struct powerdomain; | 69 | struct powerdomain; |
| 67 | 70 | ||
| 68 | /* Encodes dependencies between powerdomains - statically defined */ | 71 | /** |
| 69 | struct pwrdm_dep { | 72 | * struct powerdomain - OMAP powerdomain |
| 70 | 73 | * @name: Powerdomain name | |
| 71 | /* Powerdomain name */ | 74 | * @omap_chip: represents the OMAP chip types containing this pwrdm |
| 72 | const char *pwrdm_name; | 75 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE |
| 73 | 76 | * @pwrsts: Possible powerdomain power states | |
| 74 | /* Powerdomain pointer - resolved by the powerdomain code */ | 77 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION |
| 75 | struct powerdomain *pwrdm; | 78 | * @flags: Powerdomain flags |
| 76 | 79 | * @banks: Number of software-controllable memory banks in this powerdomain | |
| 77 | /* Flags to mark OMAP chip restrictions, etc. */ | 80 | * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION |
| 78 | const struct omap_chip_id omap_chip; | 81 | * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON |
| 79 | 82 | * @pwrdm_clkdms: Clockdomains in this powerdomain | |
| 80 | }; | 83 | * @node: list_head linking all powerdomains |
| 81 | 84 | * @state: | |
| 85 | * @state_counter: | ||
| 86 | * @timer: | ||
| 87 | * @state_timer: | ||
| 88 | */ | ||
| 82 | struct powerdomain { | 89 | struct powerdomain { |
| 83 | |||
| 84 | /* Powerdomain name */ | ||
| 85 | const char *name; | 90 | const char *name; |
| 86 | |||
| 87 | /* the address offset from CM_BASE/PRM_BASE */ | ||
| 88 | const s16 prcm_offs; | ||
| 89 | |||
| 90 | /* Used to represent the OMAP chip types containing this pwrdm */ | ||
| 91 | const struct omap_chip_id omap_chip; | 91 | const struct omap_chip_id omap_chip; |
| 92 | 92 | const s16 prcm_offs; | |
| 93 | /* Powerdomains that can be told to wake this powerdomain up */ | ||
| 94 | struct pwrdm_dep *wkdep_srcs; | ||
| 95 | |||
| 96 | /* Powerdomains that can be told to keep this pwrdm from inactivity */ | ||
| 97 | struct pwrdm_dep *sleepdep_srcs; | ||
| 98 | |||
| 99 | /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ | ||
| 100 | const u8 dep_bit; | ||
| 101 | |||
| 102 | /* Possible powerdomain power states */ | ||
| 103 | const u8 pwrsts; | 93 | const u8 pwrsts; |
| 104 | |||
| 105 | /* Possible logic power states when pwrdm in RETENTION */ | ||
| 106 | const u8 pwrsts_logic_ret; | 94 | const u8 pwrsts_logic_ret; |
| 107 | |||
| 108 | /* Powerdomain flags */ | ||
| 109 | const u8 flags; | 95 | const u8 flags; |
| 110 | |||
| 111 | /* Number of software-controllable memory banks in this powerdomain */ | ||
| 112 | const u8 banks; | 96 | const u8 banks; |
| 113 | |||
| 114 | /* Possible memory bank pwrstates when pwrdm in RETENTION */ | ||
| 115 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; | 97 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; |
| 116 | |||
| 117 | /* Possible memory bank pwrstates when pwrdm is ON */ | ||
| 118 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; | 98 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; |
| 119 | |||
| 120 | /* Clockdomains in this powerdomain */ | ||
| 121 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; | 99 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; |
| 122 | |||
| 123 | struct list_head node; | 100 | struct list_head node; |
| 124 | |||
| 125 | int state; | 101 | int state; |
| 126 | unsigned state_counter[PWRDM_MAX_PWRSTS]; | 102 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
| 103 | unsigned ret_logic_off_counter; | ||
| 104 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | ||
| 127 | 105 | ||
| 128 | #ifdef CONFIG_PM_DEBUG | 106 | #ifdef CONFIG_PM_DEBUG |
| 129 | s64 timer; | 107 | s64 timer; |
| @@ -134,8 +112,6 @@ struct powerdomain { | |||
| 134 | 112 | ||
| 135 | void pwrdm_init(struct powerdomain **pwrdm_list); | 113 | void pwrdm_init(struct powerdomain **pwrdm_list); |
| 136 | 114 | ||
| 137 | int pwrdm_register(struct powerdomain *pwrdm); | ||
| 138 | int pwrdm_unregister(struct powerdomain *pwrdm); | ||
| 139 | struct powerdomain *pwrdm_lookup(const char *name); | 115 | struct powerdomain *pwrdm_lookup(const char *name); |
| 140 | 116 | ||
| 141 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), | 117 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
| @@ -149,13 +125,6 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | |||
| 149 | int (*fn)(struct powerdomain *pwrdm, | 125 | int (*fn)(struct powerdomain *pwrdm, |
| 150 | struct clockdomain *clkdm)); | 126 | struct clockdomain *clkdm)); |
| 151 | 127 | ||
| 152 | int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | ||
| 153 | int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | ||
| 154 | int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | ||
| 155 | int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | ||
| 156 | int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | ||
| 157 | int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | ||
| 158 | |||
| 159 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); | 128 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); |
| 160 | 129 | ||
| 161 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | 130 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); |
| @@ -170,8 +139,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |||
| 170 | 139 | ||
| 171 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); | 140 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); |
| 172 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); | 141 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); |
| 142 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm); | ||
| 173 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | 143 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
| 174 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | 144 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
| 145 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); | ||
| 175 | 146 | ||
| 176 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); | 147 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
| 177 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); | 148 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); |
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index e63e94e18975..d6a0e27d5a7f 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h | |||
| @@ -25,7 +25,8 @@ | |||
| 25 | 25 | ||
| 26 | u32 omap_prcm_get_reset_sources(void); | 26 | u32 omap_prcm_get_reset_sources(void); |
| 27 | void omap_prcm_arch_reset(char mode); | 27 | void omap_prcm_arch_reset(char mode); |
| 28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); | 28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
| 29 | const char *name); | ||
| 29 | 30 | ||
| 30 | #define START_PADCONF_SAVE 0x2 | 31 | #define START_PADCONF_SAVE 0x2 |
| 31 | #define PADCONF_SAVE_DONE 0x1 | 32 | #define PADCONF_SAVE_DONE 0x1 |
| @@ -33,6 +34,14 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); | |||
| 33 | void omap3_prcm_save_context(void); | 34 | void omap3_prcm_save_context(void); |
| 34 | void omap3_prcm_restore_context(void); | 35 | void omap3_prcm_restore_context(void); |
| 35 | 36 | ||
| 37 | u32 prm_read_mod_reg(s16 module, u16 idx); | ||
| 38 | void prm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 39 | u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 40 | u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); | ||
| 41 | u32 cm_read_mod_reg(s16 module, u16 idx); | ||
| 42 | void cm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 43 | u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 44 | |||
| 36 | #endif | 45 | #endif |
| 37 | 46 | ||
| 38 | 47 | ||
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index f5a4a92393ef..83dce4c4f7e6 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h | |||
| @@ -15,37 +15,65 @@ | |||
| 15 | 15 | ||
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | 17 | ||
| 18 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 19 | /* OMAP1 serial ports */ | 18 | /* OMAP1 serial ports */ |
| 20 | #define OMAP_UART1_BASE 0xfffb0000 | 19 | #define OMAP1_UART1_BASE 0xfffb0000 |
| 21 | #define OMAP_UART2_BASE 0xfffb0800 | 20 | #define OMAP1_UART2_BASE 0xfffb0800 |
| 22 | #define OMAP_UART3_BASE 0xfffb9800 | 21 | #define OMAP1_UART3_BASE 0xfffb9800 |
| 23 | #elif defined(CONFIG_ARCH_OMAP2) | 22 | |
| 24 | /* OMAP2 serial ports */ | 23 | /* OMAP2 serial ports */ |
| 25 | #define OMAP_UART1_BASE 0x4806a000 | 24 | #define OMAP2_UART1_BASE 0x4806a000 |
| 26 | #define OMAP_UART2_BASE 0x4806c000 | 25 | #define OMAP2_UART2_BASE 0x4806c000 |
| 27 | #define OMAP_UART3_BASE 0x4806e000 | 26 | #define OMAP2_UART3_BASE 0x4806e000 |
| 28 | #elif defined(CONFIG_ARCH_OMAP3) | 27 | |
| 29 | /* OMAP3 serial ports */ | 28 | /* OMAP3 serial ports */ |
| 30 | #define OMAP_UART1_BASE 0x4806a000 | 29 | #define OMAP3_UART1_BASE OMAP2_UART1_BASE |
| 31 | #define OMAP_UART2_BASE 0x4806c000 | 30 | #define OMAP3_UART2_BASE OMAP2_UART2_BASE |
| 32 | #define OMAP_UART3_BASE 0x49020000 | 31 | #define OMAP3_UART3_BASE 0x49020000 |
| 33 | #elif defined(CONFIG_ARCH_OMAP4) | 32 | #define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ |
| 33 | |||
| 34 | /* OMAP4 serial ports */ | 34 | /* OMAP4 serial ports */ |
| 35 | #define OMAP_UART1_BASE 0x4806a000 | 35 | #define OMAP4_UART1_BASE OMAP2_UART1_BASE |
| 36 | #define OMAP_UART2_BASE 0x4806c000 | 36 | #define OMAP4_UART2_BASE OMAP2_UART2_BASE |
| 37 | #define OMAP_UART3_BASE 0x48020000 | 37 | #define OMAP4_UART3_BASE 0x48020000 |
| 38 | #define OMAP_UART4_BASE 0x4806e000 | 38 | #define OMAP4_UART4_BASE 0x4806e000 |
| 39 | #endif | 39 | |
| 40 | /* External port on Zoom2/3 */ | ||
| 41 | #define ZOOM_UART_BASE 0x10000000 | ||
| 42 | #define ZOOM_UART_VIRT 0xfb000000 | ||
| 43 | |||
| 44 | #define OMAP_PORT_SHIFT 2 | ||
| 45 | #define OMAP7XX_PORT_SHIFT 0 | ||
| 46 | #define ZOOM_PORT_SHIFT 1 | ||
| 40 | 47 | ||
| 41 | #define OMAP1510_BASE_BAUD (12000000/16) | 48 | #define OMAP1510_BASE_BAUD (12000000/16) |
| 42 | #define OMAP16XX_BASE_BAUD (48000000/16) | 49 | #define OMAP16XX_BASE_BAUD (48000000/16) |
| 43 | #define OMAP24XX_BASE_BAUD (48000000/16) | 50 | #define OMAP24XX_BASE_BAUD (48000000/16) |
| 44 | 51 | ||
| 52 | /* | ||
| 53 | * DEBUG_LL port encoding stored into the UART1 scratchpad register by | ||
| 54 | * decomp_setup in uncompress.h | ||
| 55 | */ | ||
| 56 | #define OMAP1UART1 11 | ||
| 57 | #define OMAP1UART2 12 | ||
| 58 | #define OMAP1UART3 13 | ||
| 59 | #define OMAP2UART1 21 | ||
| 60 | #define OMAP2UART2 22 | ||
| 61 | #define OMAP2UART3 23 | ||
| 62 | #define OMAP3UART1 OMAP2UART1 | ||
| 63 | #define OMAP3UART2 OMAP2UART2 | ||
| 64 | #define OMAP3UART3 33 | ||
| 65 | #define OMAP3UART4 34 /* Only on 36xx */ | ||
| 66 | #define OMAP4UART1 OMAP2UART1 | ||
| 67 | #define OMAP4UART2 OMAP2UART2 | ||
| 68 | #define OMAP4UART3 43 | ||
| 69 | #define OMAP4UART4 44 | ||
| 70 | #define ZOOM_UART 95 /* Only on zoom2/3 */ | ||
| 71 | |||
| 72 | /* This is only used by 8250.c for omap1510 */ | ||
| 45 | #define is_omap_port(pt) ({int __ret = 0; \ | 73 | #define is_omap_port(pt) ({int __ret = 0; \ |
| 46 | if ((pt)->port.mapbase == OMAP_UART1_BASE || \ | 74 | if ((pt)->port.mapbase == OMAP1_UART1_BASE || \ |
| 47 | (pt)->port.mapbase == OMAP_UART2_BASE || \ | 75 | (pt)->port.mapbase == OMAP1_UART2_BASE || \ |
| 48 | (pt)->port.mapbase == OMAP_UART3_BASE) \ | 76 | (pt)->port.mapbase == OMAP1_UART3_BASE) \ |
| 49 | __ret = 1; \ | 77 | __ret = 1; \ |
| 50 | __ret; \ | 78 | __ret; \ |
| 51 | }) | 79 | }) |
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 13c305d62127..81d9ec540fcf 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
| @@ -19,62 +19,38 @@ | |||
| 19 | 19 | ||
| 20 | #include <linux/types.h> | 20 | #include <linux/types.h> |
| 21 | #include <linux/serial_reg.h> | 21 | #include <linux/serial_reg.h> |
| 22 | |||
| 23 | #include <asm/mach-types.h> | ||
| 24 | |||
| 22 | #include <plat/serial.h> | 25 | #include <plat/serial.h> |
| 23 | 26 | ||
| 24 | unsigned int system_rev; | 27 | static volatile u8 *uart1_base; |
| 28 | static int uart1_shift; | ||
| 25 | 29 | ||
| 26 | #define UART_OMAP_MDR1 0x08 /* mode definition register */ | 30 | static volatile u8 *uart_base; |
| 27 | #define OMAP_ID_730 0x355F | 31 | static int uart_shift; |
| 28 | #define OMAP_ID_850 0x362C | ||
| 29 | #define ID_MASK 0x7fff | ||
| 30 | #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) | ||
| 31 | #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK | ||
| 32 | 32 | ||
| 33 | static void putc(int c) | 33 | /* |
| 34 | * Store the DEBUG_LL uart number into UART1 scratchpad register. | ||
| 35 | * See also debug-macro.S, and serial.c for related code. | ||
| 36 | * | ||
| 37 | * Please note that we currently assume that: | ||
| 38 | * - UART1 clocks are enabled for register access | ||
| 39 | * - UART1 scratchpad register can be used | ||
| 40 | */ | ||
| 41 | static void set_uart1_scratchpad(unsigned char port) | ||
| 34 | { | 42 | { |
| 35 | volatile u8 * uart = 0; | 43 | uart1_base[UART_SCR << uart1_shift] = port; |
| 36 | int shift = 2; | 44 | } |
| 37 | |||
| 38 | #ifdef CONFIG_MACH_OMAP_PALMTE | ||
| 39 | return; | ||
| 40 | #endif | ||
| 41 | |||
| 42 | #ifdef CONFIG_ARCH_OMAP | ||
| 43 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | ||
| 44 | uart = (volatile u8 *)(OMAP_UART3_BASE); | ||
| 45 | #elif defined(CONFIG_OMAP_LL_DEBUG_UART2) | ||
| 46 | uart = (volatile u8 *)(OMAP_UART2_BASE); | ||
| 47 | #elif defined(CONFIG_OMAP_LL_DEBUG_UART1) | ||
| 48 | uart = (volatile u8 *)(OMAP_UART1_BASE); | ||
| 49 | #elif defined(CONFIG_OMAP_LL_DEBUG_NONE) | ||
| 50 | return; | ||
| 51 | #else | ||
| 52 | return; | ||
| 53 | #endif | ||
| 54 | |||
| 55 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 56 | /* Determine which serial port to use */ | ||
| 57 | do { | ||
| 58 | /* MMU is not on, so cpu_is_omapXXXX() won't work here */ | ||
| 59 | unsigned int omap_id = omap_get_id(); | ||
| 60 | |||
| 61 | if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) | ||
| 62 | shift = 0; | ||
| 63 | 45 | ||
| 64 | if (check_port(uart, shift)) | 46 | static void putc(int c) |
| 65 | break; | 47 | { |
| 66 | /* Silent boot if no serial ports are enabled. */ | 48 | if (!uart_base) |
| 67 | return; | 49 | return; |
| 68 | } while (0); | ||
| 69 | #endif /* CONFIG_ARCH_OMAP1 */ | ||
| 70 | #endif | ||
| 71 | 50 | ||
| 72 | /* | 51 | while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) |
| 73 | * Now, xmit each character | ||
| 74 | */ | ||
| 75 | while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) | ||
| 76 | barrier(); | 52 | barrier(); |
| 77 | uart[UART_TX << shift] = c; | 53 | uart_base[UART_TX << uart_shift] = c; |
| 78 | } | 54 | } |
| 79 | 55 | ||
| 80 | static inline void flush(void) | 56 | static inline void flush(void) |
| @@ -82,7 +58,116 @@ static inline void flush(void) | |||
| 82 | } | 58 | } |
| 83 | 59 | ||
| 84 | /* | 60 | /* |
| 61 | * Macros to configure UART1 and debug UART | ||
| 62 | */ | ||
| 63 | #define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ | ||
| 64 | dbg_uart, dbg_shft, dbg_id) \ | ||
| 65 | if (machine_is_##mach()) { \ | ||
| 66 | uart1_base = (volatile u8 *)(uart1_phys); \ | ||
| 67 | uart1_shift = (uart1_shft); \ | ||
| 68 | uart_base = (volatile u8 *)(dbg_uart); \ | ||
| 69 | uart_shift = (dbg_shft); \ | ||
| 70 | port = (dbg_id); \ | ||
| 71 | set_uart1_scratchpad(port); \ | ||
| 72 | break; \ | ||
| 73 | } | ||
| 74 | |||
| 75 | #define DEBUG_LL_OMAP7XX(p, mach) \ | ||
| 76 | _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ | ||
| 77 | OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) | ||
| 78 | |||
| 79 | #define DEBUG_LL_OMAP1(p, mach) \ | ||
| 80 | _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ | ||
| 81 | OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) | ||
| 82 | |||
| 83 | #define DEBUG_LL_OMAP2(p, mach) \ | ||
| 84 | _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ | ||
| 85 | OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) | ||
| 86 | |||
| 87 | #define DEBUG_LL_OMAP3(p, mach) \ | ||
| 88 | _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ | ||
| 89 | OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) | ||
| 90 | |||
| 91 | #define DEBUG_LL_OMAP4(p, mach) \ | ||
| 92 | _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ | ||
| 93 | OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) | ||
| 94 | |||
| 95 | /* Zoom2/3 shift is different for UART1 and external port */ | ||
| 96 | #define DEBUG_LL_ZOOM(mach) \ | ||
| 97 | _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ | ||
| 98 | ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) | ||
| 99 | |||
| 100 | static inline void __arch_decomp_setup(unsigned long arch_id) | ||
| 101 | { | ||
| 102 | int port = 0; | ||
| 103 | |||
| 104 | /* | ||
| 105 | * Initialize the port based on the machine ID from the bootloader. | ||
| 106 | * Note that we're using macros here instead of switch statement | ||
| 107 | * as machine_is functions are optimized out for the boards that | ||
| 108 | * are not selected. | ||
| 109 | */ | ||
| 110 | do { | ||
| 111 | /* omap7xx/8xx based boards using UART1 with shift 0 */ | ||
| 112 | DEBUG_LL_OMAP7XX(1, herald); | ||
| 113 | DEBUG_LL_OMAP7XX(1, omap_perseus2); | ||
| 114 | |||
| 115 | /* omap15xx/16xx based boards using UART1 */ | ||
| 116 | DEBUG_LL_OMAP1(1, ams_delta); | ||
| 117 | DEBUG_LL_OMAP1(1, nokia770); | ||
| 118 | DEBUG_LL_OMAP1(1, omap_h2); | ||
| 119 | DEBUG_LL_OMAP1(1, omap_h3); | ||
| 120 | DEBUG_LL_OMAP1(1, omap_innovator); | ||
| 121 | DEBUG_LL_OMAP1(1, omap_osk); | ||
| 122 | DEBUG_LL_OMAP1(1, omap_palmte); | ||
| 123 | DEBUG_LL_OMAP1(1, omap_palmz71); | ||
| 124 | |||
| 125 | /* omap15xx/16xx based boards using UART2 */ | ||
| 126 | DEBUG_LL_OMAP1(2, omap_palmtt); | ||
| 127 | |||
| 128 | /* omap15xx/16xx based boards using UART3 */ | ||
| 129 | DEBUG_LL_OMAP1(3, sx1); | ||
| 130 | |||
| 131 | /* omap2 based boards using UART1 */ | ||
| 132 | DEBUG_LL_OMAP2(1, omap2evm); | ||
| 133 | DEBUG_LL_OMAP2(1, omap_2430sdp); | ||
| 134 | DEBUG_LL_OMAP2(1, omap_apollon); | ||
| 135 | DEBUG_LL_OMAP2(1, omap_h4); | ||
| 136 | |||
| 137 | /* omap2 based boards using UART3 */ | ||
| 138 | DEBUG_LL_OMAP2(3, nokia_n800); | ||
| 139 | DEBUG_LL_OMAP2(3, nokia_n810); | ||
| 140 | DEBUG_LL_OMAP2(3, nokia_n810_wimax); | ||
| 141 | |||
| 142 | /* omap3 based boards using UART1 */ | ||
| 143 | DEBUG_LL_OMAP2(1, omap3evm); | ||
| 144 | DEBUG_LL_OMAP3(1, omap_3430sdp); | ||
| 145 | DEBUG_LL_OMAP3(1, omap_3630sdp); | ||
| 146 | |||
| 147 | /* omap3 based boards using UART3 */ | ||
| 148 | DEBUG_LL_OMAP3(3, cm_t35); | ||
| 149 | DEBUG_LL_OMAP3(3, igep0020); | ||
| 150 | DEBUG_LL_OMAP3(3, nokia_rx51); | ||
| 151 | DEBUG_LL_OMAP3(3, omap3517evm); | ||
| 152 | DEBUG_LL_OMAP3(3, omap3_beagle); | ||
| 153 | DEBUG_LL_OMAP3(3, omap3_pandora); | ||
| 154 | DEBUG_LL_OMAP3(3, omap_ldp); | ||
| 155 | DEBUG_LL_OMAP3(3, overo); | ||
| 156 | DEBUG_LL_OMAP3(3, touchbook); | ||
| 157 | |||
| 158 | /* omap4 based boards using UART3 */ | ||
| 159 | DEBUG_LL_OMAP4(3, omap_4430sdp); | ||
| 160 | |||
| 161 | /* zoom2/3 external uart */ | ||
| 162 | DEBUG_LL_ZOOM(omap_zoom2); | ||
| 163 | DEBUG_LL_ZOOM(omap_zoom3); | ||
| 164 | |||
| 165 | } while (0); | ||
| 166 | } | ||
| 167 | |||
| 168 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) | ||
| 169 | |||
| 170 | /* | ||
| 85 | * nothing to do | 171 | * nothing to do |
| 86 | */ | 172 | */ |
| 87 | #define arch_decomp_setup() | ||
| 88 | #define arch_decomp_wdog() | 173 | #define arch_decomp_wdog() |
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 33a500eb2f93..288e29e1c06f 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
| @@ -3,6 +3,7 @@ | |||
| 3 | #ifndef __ASM_ARCH_OMAP_USB_H | 3 | #ifndef __ASM_ARCH_OMAP_USB_H |
| 4 | #define __ASM_ARCH_OMAP_USB_H | 4 | #define __ASM_ARCH_OMAP_USB_H |
| 5 | 5 | ||
| 6 | #include <linux/usb/musb.h> | ||
| 6 | #include <plat/board.h> | 7 | #include <plat/board.h> |
| 7 | 8 | ||
| 8 | #define OMAP3_HS_USB_PORTS 3 | 9 | #define OMAP3_HS_USB_PORTS 3 |
| @@ -42,7 +43,15 @@ struct ehci_hcd_omap_platform_data { | |||
| 42 | #define UDC_BASE OMAP2_UDC_BASE | 43 | #define UDC_BASE OMAP2_UDC_BASE |
| 43 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE | 44 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE |
| 44 | 45 | ||
| 45 | extern void usb_musb_init(void); | 46 | struct omap_musb_board_data { |
| 47 | u8 interface_type; | ||
| 48 | u8 mode; | ||
| 49 | u8 power; | ||
| 50 | }; | ||
| 51 | |||
| 52 | enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; | ||
| 53 | |||
| 54 | extern void usb_musb_init(struct omap_musb_board_data *board_data); | ||
| 46 | 55 | ||
| 47 | extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata); | 56 | extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata); |
| 48 | 57 | ||
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index 4cbd4fb3232c..b0078cf96281 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c | |||
| @@ -90,8 +90,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) | |||
| 90 | return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); | 90 | return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); |
| 91 | if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) | 91 | if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) |
| 92 | return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); | 92 | return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); |
| 93 | if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE)) | ||
| 94 | return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT); | ||
| 95 | if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE)) | 93 | if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE)) |
| 96 | return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT); | 94 | return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT); |
| 97 | if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE)) | 95 | if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE)) |
| @@ -110,8 +108,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) | |||
| 110 | return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT); | 108 | return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT); |
| 111 | if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE)) | 109 | if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE)) |
| 112 | return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT); | 110 | return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT); |
| 113 | if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE)) | ||
| 114 | return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); | ||
| 115 | if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) | 111 | if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) |
| 116 | return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); | 112 | return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); |
| 117 | if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE)) | 113 | if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE)) |
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 463d6386aff2..905ed832df56 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap iommu: tlb and pagetable primitives | 2 | * omap iommu: tlb and pagetable primitives |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008-2009 Nokia Corporation | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
| 5 | * | 5 | * |
| 6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | 6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, |
| 7 | * Paul Mundt and Toshihiro Kobayashi | 7 | * Paul Mundt and Toshihiro Kobayashi |
| @@ -646,7 +646,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) | |||
| 646 | if (*iopte & IOPTE_LARGE) { | 646 | if (*iopte & IOPTE_LARGE) { |
| 647 | nent *= 16; | 647 | nent *= 16; |
| 648 | /* rewind to the 1st entry */ | 648 | /* rewind to the 1st entry */ |
| 649 | iopte = (u32 *)((u32)iopte & IOLARGE_MASK); | 649 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
| 650 | } | 650 | } |
| 651 | bytes *= nent; | 651 | bytes *= nent; |
| 652 | memset(iopte, 0, nent * sizeof(*iopte)); | 652 | memset(iopte, 0, nent * sizeof(*iopte)); |
| @@ -667,7 +667,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) | |||
| 667 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { | 667 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
| 668 | nent *= 16; | 668 | nent *= 16; |
| 669 | /* rewind to the 1st entry */ | 669 | /* rewind to the 1st entry */ |
| 670 | iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK); | 670 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
| 671 | } | 671 | } |
| 672 | bytes *= nent; | 672 | bytes *= nent; |
| 673 | } | 673 | } |
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h index 37dac434c7a1..ab23b6a140fd 100644 --- a/arch/arm/plat-omap/iopgtable.h +++ b/arch/arm/plat-omap/iopgtable.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap iommu: pagetable definitions | 2 | * omap iommu: pagetable definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008-2009 Nokia Corporation | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
| 5 | * | 5 | * |
| 6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 7 | * | 7 | * |
| @@ -13,26 +13,52 @@ | |||
| 13 | #ifndef __PLAT_OMAP_IOMMU_H | 13 | #ifndef __PLAT_OMAP_IOMMU_H |
| 14 | #define __PLAT_OMAP_IOMMU_H | 14 | #define __PLAT_OMAP_IOMMU_H |
| 15 | 15 | ||
| 16 | /* | ||
| 17 | * "L2 table" address mask and size definitions. | ||
| 18 | */ | ||
| 16 | #define IOPGD_SHIFT 20 | 19 | #define IOPGD_SHIFT 20 |
| 17 | #define IOPGD_SIZE (1 << IOPGD_SHIFT) | 20 | #define IOPGD_SIZE (1UL << IOPGD_SHIFT) |
| 18 | #define IOPGD_MASK (~(IOPGD_SIZE - 1)) | 21 | #define IOPGD_MASK (~(IOPGD_SIZE - 1)) |
| 19 | #define IOSECTION_MASK IOPGD_MASK | ||
| 20 | #define PTRS_PER_IOPGD (1 << (32 - IOPGD_SHIFT)) | ||
| 21 | #define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) | ||
| 22 | 22 | ||
| 23 | #define IOSUPER_SIZE (IOPGD_SIZE << 4) | 23 | /* |
| 24 | * "section" address mask and size definitions. | ||
| 25 | */ | ||
| 26 | #define IOSECTION_SHIFT 20 | ||
| 27 | #define IOSECTION_SIZE (1UL << IOSECTION_SHIFT) | ||
| 28 | #define IOSECTION_MASK (~(IOSECTION_SIZE - 1)) | ||
| 29 | |||
| 30 | /* | ||
| 31 | * "supersection" address mask and size definitions. | ||
| 32 | */ | ||
| 33 | #define IOSUPER_SHIFT 24 | ||
| 34 | #define IOSUPER_SIZE (1UL << IOSUPER_SHIFT) | ||
| 24 | #define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) | 35 | #define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) |
| 25 | 36 | ||
| 37 | #define PTRS_PER_IOPGD (1UL << (32 - IOPGD_SHIFT)) | ||
| 38 | #define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) | ||
| 39 | |||
| 40 | /* | ||
| 41 | * "small page" address mask and size definitions. | ||
| 42 | */ | ||
| 26 | #define IOPTE_SHIFT 12 | 43 | #define IOPTE_SHIFT 12 |
| 27 | #define IOPTE_SIZE (1 << IOPTE_SHIFT) | 44 | #define IOPTE_SIZE (1UL << IOPTE_SHIFT) |
| 28 | #define IOPTE_MASK (~(IOPTE_SIZE - 1)) | 45 | #define IOPTE_MASK (~(IOPTE_SIZE - 1)) |
| 29 | #define IOPAGE_MASK IOPTE_MASK | ||
| 30 | #define PTRS_PER_IOPTE (1 << (IOPGD_SHIFT - IOPTE_SHIFT)) | ||
| 31 | #define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) | ||
| 32 | 46 | ||
| 33 | #define IOLARGE_SIZE (IOPTE_SIZE << 4) | 47 | /* |
| 48 | * "large page" address mask and size definitions. | ||
| 49 | */ | ||
| 50 | #define IOLARGE_SHIFT 16 | ||
| 51 | #define IOLARGE_SIZE (1UL << IOLARGE_SHIFT) | ||
| 34 | #define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) | 52 | #define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) |
| 35 | 53 | ||
| 54 | #define PTRS_PER_IOPTE (1UL << (IOPGD_SHIFT - IOPTE_SHIFT)) | ||
| 55 | #define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) | ||
| 56 | |||
| 57 | #define IOPAGE_MASK IOPTE_MASK | ||
| 58 | |||
| 59 | /* | ||
| 60 | * some descriptor attributes. | ||
| 61 | */ | ||
| 36 | #define IOPGD_TABLE (1 << 0) | 62 | #define IOPGD_TABLE (1 << 0) |
| 37 | #define IOPGD_SECTION (2 << 0) | 63 | #define IOPGD_SECTION (2 << 0) |
| 38 | #define IOPGD_SUPER (1 << 18 | 2 << 0) | 64 | #define IOPGD_SUPER (1 << 18 | 2 << 0) |
| @@ -40,12 +66,14 @@ | |||
| 40 | #define IOPTE_SMALL (2 << 0) | 66 | #define IOPTE_SMALL (2 << 0) |
| 41 | #define IOPTE_LARGE (1 << 0) | 67 | #define IOPTE_LARGE (1 << 0) |
| 42 | 68 | ||
| 69 | /* to find an entry in a page-table-directory */ | ||
| 43 | #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) | 70 | #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) |
| 44 | #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) | 71 | #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) |
| 45 | 72 | ||
| 46 | #define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) | 73 | #define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) |
| 47 | #define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) | 74 | #define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) |
| 48 | 75 | ||
| 76 | /* to find an entry in the second-level page table. */ | ||
| 49 | #define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) | 77 | #define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) |
| 50 | #define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) | 78 | #define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) |
| 51 | 79 | ||
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 8e90633e4cb9..4229cec53140 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | 28 | ||
| 29 | #include <plat/mailbox.h> | 29 | #include <plat/mailbox.h> |
| 30 | 30 | ||
| 31 | static struct workqueue_struct *mboxd; | ||
| 31 | static struct omap_mbox *mboxes; | 32 | static struct omap_mbox *mboxes; |
| 32 | static DEFINE_RWLOCK(mboxes_lock); | 33 | static DEFINE_RWLOCK(mboxes_lock); |
| 33 | 34 | ||
| @@ -188,7 +189,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox) | |||
| 188 | /* no more messages in the fifo. clear IRQ source. */ | 189 | /* no more messages in the fifo. clear IRQ source. */ |
| 189 | ack_mbox_irq(mbox, IRQ_RX); | 190 | ack_mbox_irq(mbox, IRQ_RX); |
| 190 | nomem: | 191 | nomem: |
| 191 | schedule_work(&mbox->rxq->work); | 192 | queue_work(mboxd, &mbox->rxq->work); |
| 192 | } | 193 | } |
| 193 | 194 | ||
| 194 | static irqreturn_t mbox_interrupt(int irq, void *p) | 195 | static irqreturn_t mbox_interrupt(int irq, void *p) |
| @@ -401,12 +402,17 @@ EXPORT_SYMBOL(omap_mbox_unregister); | |||
| 401 | 402 | ||
| 402 | static int __init omap_mbox_init(void) | 403 | static int __init omap_mbox_init(void) |
| 403 | { | 404 | { |
| 405 | mboxd = create_workqueue("mboxd"); | ||
| 406 | if (!mboxd) | ||
| 407 | return -ENOMEM; | ||
| 408 | |||
| 404 | return 0; | 409 | return 0; |
| 405 | } | 410 | } |
| 406 | module_init(omap_mbox_init); | 411 | module_init(omap_mbox_init); |
| 407 | 412 | ||
| 408 | static void __exit omap_mbox_exit(void) | 413 | static void __exit omap_mbox_exit(void) |
| 409 | { | 414 | { |
| 415 | destroy_workqueue(mboxd); | ||
| 410 | } | 416 | } |
| 411 | module_exit(omap_mbox_exit); | 417 | module_exit(omap_mbox_exit); |
| 412 | 418 | ||
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index f75767278fc3..e47686e0a633 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
| @@ -27,64 +27,97 @@ | |||
| 27 | #include <plat/dma.h> | 27 | #include <plat/dma.h> |
| 28 | #include <plat/mcbsp.h> | 28 | #include <plat/mcbsp.h> |
| 29 | 29 | ||
| 30 | #include "../mach-omap2/cm-regbits-34xx.h" | ||
| 31 | |||
| 30 | struct omap_mcbsp **mcbsp_ptr; | 32 | struct omap_mcbsp **mcbsp_ptr; |
| 31 | int omap_mcbsp_count; | 33 | int omap_mcbsp_count, omap_mcbsp_cache_size; |
| 32 | 34 | ||
| 33 | void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val) | 35 | void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) |
| 34 | { | 36 | { |
| 35 | if (cpu_class_is_omap1() || cpu_is_omap2420()) | 37 | if (cpu_class_is_omap1()) { |
| 36 | __raw_writew((u16)val, io_base + reg); | 38 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; |
| 37 | else | 39 | __raw_writew((u16)val, mcbsp->io_base + reg); |
| 38 | __raw_writel(val, io_base + reg); | 40 | } else if (cpu_is_omap2420()) { |
| 41 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; | ||
| 42 | __raw_writew((u16)val, mcbsp->io_base + reg); | ||
| 43 | } else { | ||
| 44 | ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; | ||
| 45 | __raw_writel(val, mcbsp->io_base + reg); | ||
| 46 | } | ||
| 39 | } | 47 | } |
| 40 | 48 | ||
| 41 | int omap_mcbsp_read(void __iomem *io_base, u16 reg) | 49 | int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) |
| 42 | { | 50 | { |
| 43 | if (cpu_class_is_omap1() || cpu_is_omap2420()) | 51 | if (cpu_class_is_omap1()) { |
| 44 | return __raw_readw(io_base + reg); | 52 | return !from_cache ? __raw_readw(mcbsp->io_base + reg) : |
| 45 | else | 53 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; |
| 46 | return __raw_readl(io_base + reg); | 54 | } else if (cpu_is_omap2420()) { |
| 55 | return !from_cache ? __raw_readw(mcbsp->io_base + reg) : | ||
| 56 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)]; | ||
| 57 | } else { | ||
| 58 | return !from_cache ? __raw_readl(mcbsp->io_base + reg) : | ||
| 59 | ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; | ||
| 60 | } | ||
| 61 | } | ||
| 62 | |||
| 63 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 64 | void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) | ||
| 65 | { | ||
| 66 | __raw_writel(val, mcbsp->st_data->io_base_st + reg); | ||
| 67 | } | ||
| 68 | |||
| 69 | int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) | ||
| 70 | { | ||
| 71 | return __raw_readl(mcbsp->st_data->io_base_st + reg); | ||
| 47 | } | 72 | } |
| 73 | #endif | ||
| 48 | 74 | ||
| 49 | #define OMAP_MCBSP_READ(base, reg) \ | 75 | #define MCBSP_READ(mcbsp, reg) \ |
| 50 | omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg) | 76 | omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) |
| 51 | #define OMAP_MCBSP_WRITE(base, reg, val) \ | 77 | #define MCBSP_WRITE(mcbsp, reg, val) \ |
| 52 | omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val) | 78 | omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) |
| 79 | #define MCBSP_READ_CACHE(mcbsp, reg) \ | ||
| 80 | omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) | ||
| 53 | 81 | ||
| 54 | #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) | 82 | #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) |
| 55 | #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; | 83 | #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; |
| 56 | 84 | ||
| 85 | #define MCBSP_ST_READ(mcbsp, reg) \ | ||
| 86 | omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) | ||
| 87 | #define MCBSP_ST_WRITE(mcbsp, reg, val) \ | ||
| 88 | omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val) | ||
| 89 | |||
| 57 | static void omap_mcbsp_dump_reg(u8 id) | 90 | static void omap_mcbsp_dump_reg(u8 id) |
| 58 | { | 91 | { |
| 59 | struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id); | 92 | struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id); |
| 60 | 93 | ||
| 61 | dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); | 94 | dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); |
| 62 | dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", | 95 | dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", |
| 63 | OMAP_MCBSP_READ(mcbsp->io_base, DRR2)); | 96 | MCBSP_READ(mcbsp, DRR2)); |
| 64 | dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", | 97 | dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", |
| 65 | OMAP_MCBSP_READ(mcbsp->io_base, DRR1)); | 98 | MCBSP_READ(mcbsp, DRR1)); |
| 66 | dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", | 99 | dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", |
| 67 | OMAP_MCBSP_READ(mcbsp->io_base, DXR2)); | 100 | MCBSP_READ(mcbsp, DXR2)); |
| 68 | dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", | 101 | dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", |
| 69 | OMAP_MCBSP_READ(mcbsp->io_base, DXR1)); | 102 | MCBSP_READ(mcbsp, DXR1)); |
| 70 | dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", | 103 | dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", |
| 71 | OMAP_MCBSP_READ(mcbsp->io_base, SPCR2)); | 104 | MCBSP_READ(mcbsp, SPCR2)); |
| 72 | dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", | 105 | dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", |
| 73 | OMAP_MCBSP_READ(mcbsp->io_base, SPCR1)); | 106 | MCBSP_READ(mcbsp, SPCR1)); |
| 74 | dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", | 107 | dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", |
| 75 | OMAP_MCBSP_READ(mcbsp->io_base, RCR2)); | 108 | MCBSP_READ(mcbsp, RCR2)); |
| 76 | dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", | 109 | dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", |
| 77 | OMAP_MCBSP_READ(mcbsp->io_base, RCR1)); | 110 | MCBSP_READ(mcbsp, RCR1)); |
| 78 | dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", | 111 | dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", |
| 79 | OMAP_MCBSP_READ(mcbsp->io_base, XCR2)); | 112 | MCBSP_READ(mcbsp, XCR2)); |
| 80 | dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", | 113 | dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", |
| 81 | OMAP_MCBSP_READ(mcbsp->io_base, XCR1)); | 114 | MCBSP_READ(mcbsp, XCR1)); |
| 82 | dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", | 115 | dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", |
| 83 | OMAP_MCBSP_READ(mcbsp->io_base, SRGR2)); | 116 | MCBSP_READ(mcbsp, SRGR2)); |
| 84 | dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", | 117 | dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", |
| 85 | OMAP_MCBSP_READ(mcbsp->io_base, SRGR1)); | 118 | MCBSP_READ(mcbsp, SRGR1)); |
| 86 | dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", | 119 | dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", |
| 87 | OMAP_MCBSP_READ(mcbsp->io_base, PCR0)); | 120 | MCBSP_READ(mcbsp, PCR0)); |
| 88 | dev_dbg(mcbsp->dev, "***********************\n"); | 121 | dev_dbg(mcbsp->dev, "***********************\n"); |
| 89 | } | 122 | } |
| 90 | 123 | ||
| @@ -93,15 +126,15 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) | |||
| 93 | struct omap_mcbsp *mcbsp_tx = dev_id; | 126 | struct omap_mcbsp *mcbsp_tx = dev_id; |
| 94 | u16 irqst_spcr2; | 127 | u16 irqst_spcr2; |
| 95 | 128 | ||
| 96 | irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2); | 129 | irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2); |
| 97 | dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); | 130 | dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); |
| 98 | 131 | ||
| 99 | if (irqst_spcr2 & XSYNC_ERR) { | 132 | if (irqst_spcr2 & XSYNC_ERR) { |
| 100 | dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n", | 133 | dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n", |
| 101 | irqst_spcr2); | 134 | irqst_spcr2); |
| 102 | /* Writing zero to XSYNC_ERR clears the IRQ */ | 135 | /* Writing zero to XSYNC_ERR clears the IRQ */ |
| 103 | OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2, | 136 | MCBSP_WRITE(mcbsp_tx, SPCR2, |
| 104 | irqst_spcr2 & ~(XSYNC_ERR)); | 137 | MCBSP_READ_CACHE(mcbsp_tx, SPCR2) & ~(XSYNC_ERR)); |
| 105 | } else { | 138 | } else { |
| 106 | complete(&mcbsp_tx->tx_irq_completion); | 139 | complete(&mcbsp_tx->tx_irq_completion); |
| 107 | } | 140 | } |
| @@ -114,15 +147,15 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) | |||
| 114 | struct omap_mcbsp *mcbsp_rx = dev_id; | 147 | struct omap_mcbsp *mcbsp_rx = dev_id; |
| 115 | u16 irqst_spcr1; | 148 | u16 irqst_spcr1; |
| 116 | 149 | ||
| 117 | irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1); | 150 | irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1); |
| 118 | dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); | 151 | dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); |
| 119 | 152 | ||
| 120 | if (irqst_spcr1 & RSYNC_ERR) { | 153 | if (irqst_spcr1 & RSYNC_ERR) { |
| 121 | dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n", | 154 | dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n", |
| 122 | irqst_spcr1); | 155 | irqst_spcr1); |
| 123 | /* Writing zero to RSYNC_ERR clears the IRQ */ | 156 | /* Writing zero to RSYNC_ERR clears the IRQ */ |
| 124 | OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1, | 157 | MCBSP_WRITE(mcbsp_rx, SPCR1, |
| 125 | irqst_spcr1 & ~(RSYNC_ERR)); | 158 | MCBSP_READ_CACHE(mcbsp_rx, SPCR1) & ~(RSYNC_ERR)); |
| 126 | } else { | 159 | } else { |
| 127 | complete(&mcbsp_rx->tx_irq_completion); | 160 | complete(&mcbsp_rx->tx_irq_completion); |
| 128 | } | 161 | } |
| @@ -135,7 +168,7 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data) | |||
| 135 | struct omap_mcbsp *mcbsp_dma_tx = data; | 168 | struct omap_mcbsp *mcbsp_dma_tx = data; |
| 136 | 169 | ||
| 137 | dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n", | 170 | dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n", |
| 138 | OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); | 171 | MCBSP_READ(mcbsp_dma_tx, SPCR2)); |
| 139 | 172 | ||
| 140 | /* We can free the channels */ | 173 | /* We can free the channels */ |
| 141 | omap_free_dma(mcbsp_dma_tx->dma_tx_lch); | 174 | omap_free_dma(mcbsp_dma_tx->dma_tx_lch); |
| @@ -149,7 +182,7 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) | |||
| 149 | struct omap_mcbsp *mcbsp_dma_rx = data; | 182 | struct omap_mcbsp *mcbsp_dma_rx = data; |
| 150 | 183 | ||
| 151 | dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n", | 184 | dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n", |
| 152 | OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); | 185 | MCBSP_READ(mcbsp_dma_rx, SPCR2)); |
| 153 | 186 | ||
| 154 | /* We can free the channels */ | 187 | /* We can free the channels */ |
| 155 | omap_free_dma(mcbsp_dma_rx->dma_rx_lch); | 188 | omap_free_dma(mcbsp_dma_rx->dma_rx_lch); |
| @@ -167,7 +200,6 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) | |||
| 167 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) | 200 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) |
| 168 | { | 201 | { |
| 169 | struct omap_mcbsp *mcbsp; | 202 | struct omap_mcbsp *mcbsp; |
| 170 | void __iomem *io_base; | ||
| 171 | 203 | ||
| 172 | if (!omap_mcbsp_check_valid_id(id)) { | 204 | if (!omap_mcbsp_check_valid_id(id)) { |
| 173 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | 205 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); |
| @@ -175,30 +207,280 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) | |||
| 175 | } | 207 | } |
| 176 | mcbsp = id_to_mcbsp_ptr(id); | 208 | mcbsp = id_to_mcbsp_ptr(id); |
| 177 | 209 | ||
| 178 | io_base = mcbsp->io_base; | ||
| 179 | dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", | 210 | dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", |
| 180 | mcbsp->id, mcbsp->phys_base); | 211 | mcbsp->id, mcbsp->phys_base); |
| 181 | 212 | ||
| 182 | /* We write the given config */ | 213 | /* We write the given config */ |
| 183 | OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); | 214 | MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); |
| 184 | OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1); | 215 | MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); |
| 185 | OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2); | 216 | MCBSP_WRITE(mcbsp, RCR2, config->rcr2); |
| 186 | OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1); | 217 | MCBSP_WRITE(mcbsp, RCR1, config->rcr1); |
| 187 | OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2); | 218 | MCBSP_WRITE(mcbsp, XCR2, config->xcr2); |
| 188 | OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1); | 219 | MCBSP_WRITE(mcbsp, XCR1, config->xcr1); |
| 189 | OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2); | 220 | MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); |
| 190 | OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1); | 221 | MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); |
| 191 | OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); | 222 | MCBSP_WRITE(mcbsp, MCR2, config->mcr2); |
| 192 | OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); | 223 | MCBSP_WRITE(mcbsp, MCR1, config->mcr1); |
| 193 | OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); | 224 | MCBSP_WRITE(mcbsp, PCR0, config->pcr0); |
| 194 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | 225 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
| 195 | OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr); | 226 | MCBSP_WRITE(mcbsp, XCCR, config->xccr); |
| 196 | OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr); | 227 | MCBSP_WRITE(mcbsp, RCCR, config->rccr); |
| 197 | } | 228 | } |
| 198 | } | 229 | } |
| 199 | EXPORT_SYMBOL(omap_mcbsp_config); | 230 | EXPORT_SYMBOL(omap_mcbsp_config); |
| 200 | 231 | ||
| 201 | #ifdef CONFIG_ARCH_OMAP34XX | 232 | #ifdef CONFIG_ARCH_OMAP3 |
| 233 | static void omap_st_on(struct omap_mcbsp *mcbsp) | ||
| 234 | { | ||
| 235 | unsigned int w; | ||
| 236 | |||
| 237 | /* | ||
| 238 | * Sidetone uses McBSP ICLK - which must not idle when sidetones | ||
| 239 | * are enabled or sidetones start sounding ugly. | ||
| 240 | */ | ||
| 241 | w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
| 242 | w &= ~(1 << (mcbsp->id - 2)); | ||
| 243 | cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
| 244 | |||
| 245 | /* Enable McBSP Sidetone */ | ||
| 246 | w = MCBSP_READ(mcbsp, SSELCR); | ||
| 247 | MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); | ||
| 248 | |||
| 249 | w = MCBSP_ST_READ(mcbsp, SYSCONFIG); | ||
| 250 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); | ||
| 251 | |||
| 252 | /* Enable Sidetone from Sidetone Core */ | ||
| 253 | w = MCBSP_ST_READ(mcbsp, SSELCR); | ||
| 254 | MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); | ||
| 255 | } | ||
| 256 | |||
| 257 | static void omap_st_off(struct omap_mcbsp *mcbsp) | ||
| 258 | { | ||
| 259 | unsigned int w; | ||
| 260 | |||
| 261 | w = MCBSP_ST_READ(mcbsp, SSELCR); | ||
| 262 | MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); | ||
| 263 | |||
| 264 | w = MCBSP_ST_READ(mcbsp, SYSCONFIG); | ||
| 265 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE); | ||
| 266 | |||
| 267 | w = MCBSP_READ(mcbsp, SSELCR); | ||
| 268 | MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); | ||
| 269 | |||
| 270 | w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
| 271 | w |= 1 << (mcbsp->id - 2); | ||
| 272 | cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
| 273 | } | ||
| 274 | |||
| 275 | static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) | ||
| 276 | { | ||
| 277 | u16 val, i; | ||
| 278 | |||
| 279 | val = MCBSP_ST_READ(mcbsp, SYSCONFIG); | ||
| 280 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE)); | ||
| 281 | |||
| 282 | val = MCBSP_ST_READ(mcbsp, SSELCR); | ||
| 283 | |||
| 284 | if (val & ST_COEFFWREN) | ||
| 285 | MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); | ||
| 286 | |||
| 287 | MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN); | ||
| 288 | |||
| 289 | for (i = 0; i < 128; i++) | ||
| 290 | MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]); | ||
| 291 | |||
| 292 | i = 0; | ||
| 293 | |||
| 294 | val = MCBSP_ST_READ(mcbsp, SSELCR); | ||
| 295 | while (!(val & ST_COEFFWRDONE) && (++i < 1000)) | ||
| 296 | val = MCBSP_ST_READ(mcbsp, SSELCR); | ||
| 297 | |||
| 298 | MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); | ||
| 299 | |||
| 300 | if (i == 1000) | ||
| 301 | dev_err(mcbsp->dev, "McBSP FIR load error!\n"); | ||
| 302 | } | ||
| 303 | |||
| 304 | static void omap_st_chgain(struct omap_mcbsp *mcbsp) | ||
| 305 | { | ||
| 306 | u16 w; | ||
| 307 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | ||
| 308 | |||
| 309 | w = MCBSP_ST_READ(mcbsp, SYSCONFIG); | ||
| 310 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); | ||
| 311 | |||
| 312 | w = MCBSP_ST_READ(mcbsp, SSELCR); | ||
| 313 | |||
| 314 | MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \ | ||
| 315 | ST_CH1GAIN(st_data->ch1gain)); | ||
| 316 | } | ||
| 317 | |||
| 318 | int omap_st_set_chgain(unsigned int id, int channel, s16 chgain) | ||
| 319 | { | ||
| 320 | struct omap_mcbsp *mcbsp; | ||
| 321 | struct omap_mcbsp_st_data *st_data; | ||
| 322 | int ret = 0; | ||
| 323 | |||
| 324 | if (!omap_mcbsp_check_valid_id(id)) { | ||
| 325 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
| 326 | return -ENODEV; | ||
| 327 | } | ||
| 328 | |||
| 329 | mcbsp = id_to_mcbsp_ptr(id); | ||
| 330 | st_data = mcbsp->st_data; | ||
| 331 | |||
| 332 | if (!st_data) | ||
| 333 | return -ENOENT; | ||
| 334 | |||
| 335 | spin_lock_irq(&mcbsp->lock); | ||
| 336 | if (channel == 0) | ||
| 337 | st_data->ch0gain = chgain; | ||
| 338 | else if (channel == 1) | ||
| 339 | st_data->ch1gain = chgain; | ||
| 340 | else | ||
| 341 | ret = -EINVAL; | ||
| 342 | |||
| 343 | if (st_data->enabled) | ||
| 344 | omap_st_chgain(mcbsp); | ||
| 345 | spin_unlock_irq(&mcbsp->lock); | ||
| 346 | |||
| 347 | return ret; | ||
| 348 | } | ||
| 349 | EXPORT_SYMBOL(omap_st_set_chgain); | ||
| 350 | |||
| 351 | int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain) | ||
| 352 | { | ||
| 353 | struct omap_mcbsp *mcbsp; | ||
| 354 | struct omap_mcbsp_st_data *st_data; | ||
| 355 | int ret = 0; | ||
| 356 | |||
| 357 | if (!omap_mcbsp_check_valid_id(id)) { | ||
| 358 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
| 359 | return -ENODEV; | ||
| 360 | } | ||
| 361 | |||
| 362 | mcbsp = id_to_mcbsp_ptr(id); | ||
| 363 | st_data = mcbsp->st_data; | ||
| 364 | |||
| 365 | if (!st_data) | ||
| 366 | return -ENOENT; | ||
| 367 | |||
| 368 | spin_lock_irq(&mcbsp->lock); | ||
| 369 | if (channel == 0) | ||
| 370 | *chgain = st_data->ch0gain; | ||
| 371 | else if (channel == 1) | ||
| 372 | *chgain = st_data->ch1gain; | ||
| 373 | else | ||
| 374 | ret = -EINVAL; | ||
| 375 | spin_unlock_irq(&mcbsp->lock); | ||
| 376 | |||
| 377 | return ret; | ||
| 378 | } | ||
| 379 | EXPORT_SYMBOL(omap_st_get_chgain); | ||
| 380 | |||
| 381 | static int omap_st_start(struct omap_mcbsp *mcbsp) | ||
| 382 | { | ||
| 383 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | ||
| 384 | |||
| 385 | if (st_data && st_data->enabled && !st_data->running) { | ||
| 386 | omap_st_fir_write(mcbsp, st_data->taps); | ||
| 387 | omap_st_chgain(mcbsp); | ||
| 388 | |||
| 389 | if (!mcbsp->free) { | ||
| 390 | omap_st_on(mcbsp); | ||
| 391 | st_data->running = 1; | ||
| 392 | } | ||
| 393 | } | ||
| 394 | |||
| 395 | return 0; | ||
| 396 | } | ||
| 397 | |||
| 398 | int omap_st_enable(unsigned int id) | ||
| 399 | { | ||
| 400 | struct omap_mcbsp *mcbsp; | ||
| 401 | struct omap_mcbsp_st_data *st_data; | ||
| 402 | |||
| 403 | if (!omap_mcbsp_check_valid_id(id)) { | ||
| 404 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
| 405 | return -ENODEV; | ||
| 406 | } | ||
| 407 | |||
| 408 | mcbsp = id_to_mcbsp_ptr(id); | ||
| 409 | st_data = mcbsp->st_data; | ||
| 410 | |||
| 411 | if (!st_data) | ||
| 412 | return -ENODEV; | ||
| 413 | |||
| 414 | spin_lock_irq(&mcbsp->lock); | ||
| 415 | st_data->enabled = 1; | ||
| 416 | omap_st_start(mcbsp); | ||
| 417 | spin_unlock_irq(&mcbsp->lock); | ||
| 418 | |||
| 419 | return 0; | ||
| 420 | } | ||
| 421 | EXPORT_SYMBOL(omap_st_enable); | ||
| 422 | |||
| 423 | static int omap_st_stop(struct omap_mcbsp *mcbsp) | ||
| 424 | { | ||
| 425 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | ||
| 426 | |||
| 427 | if (st_data && st_data->running) { | ||
| 428 | if (!mcbsp->free) { | ||
| 429 | omap_st_off(mcbsp); | ||
| 430 | st_data->running = 0; | ||
| 431 | } | ||
| 432 | } | ||
| 433 | |||
| 434 | return 0; | ||
| 435 | } | ||
| 436 | |||
| 437 | int omap_st_disable(unsigned int id) | ||
| 438 | { | ||
| 439 | struct omap_mcbsp *mcbsp; | ||
| 440 | struct omap_mcbsp_st_data *st_data; | ||
| 441 | int ret = 0; | ||
| 442 | |||
| 443 | if (!omap_mcbsp_check_valid_id(id)) { | ||
| 444 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
| 445 | return -ENODEV; | ||
| 446 | } | ||
| 447 | |||
| 448 | mcbsp = id_to_mcbsp_ptr(id); | ||
| 449 | st_data = mcbsp->st_data; | ||
| 450 | |||
| 451 | if (!st_data) | ||
| 452 | return -ENODEV; | ||
| 453 | |||
| 454 | spin_lock_irq(&mcbsp->lock); | ||
| 455 | omap_st_stop(mcbsp); | ||
| 456 | st_data->enabled = 0; | ||
| 457 | spin_unlock_irq(&mcbsp->lock); | ||
| 458 | |||
| 459 | return ret; | ||
| 460 | } | ||
| 461 | EXPORT_SYMBOL(omap_st_disable); | ||
| 462 | |||
| 463 | int omap_st_is_enabled(unsigned int id) | ||
| 464 | { | ||
| 465 | struct omap_mcbsp *mcbsp; | ||
| 466 | struct omap_mcbsp_st_data *st_data; | ||
| 467 | |||
| 468 | if (!omap_mcbsp_check_valid_id(id)) { | ||
| 469 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
| 470 | return -ENODEV; | ||
| 471 | } | ||
| 472 | |||
| 473 | mcbsp = id_to_mcbsp_ptr(id); | ||
| 474 | st_data = mcbsp->st_data; | ||
| 475 | |||
| 476 | if (!st_data) | ||
| 477 | return -ENODEV; | ||
| 478 | |||
| 479 | |||
| 480 | return st_data->enabled; | ||
| 481 | } | ||
| 482 | EXPORT_SYMBOL(omap_st_is_enabled); | ||
| 483 | |||
| 202 | /* | 484 | /* |
| 203 | * omap_mcbsp_set_tx_threshold configures how to deal | 485 | * omap_mcbsp_set_tx_threshold configures how to deal |
| 204 | * with transmit threshold. the threshold value and handler can be | 486 | * with transmit threshold. the threshold value and handler can be |
| @@ -207,7 +489,6 @@ EXPORT_SYMBOL(omap_mcbsp_config); | |||
| 207 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | 489 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) |
| 208 | { | 490 | { |
| 209 | struct omap_mcbsp *mcbsp; | 491 | struct omap_mcbsp *mcbsp; |
| 210 | void __iomem *io_base; | ||
| 211 | 492 | ||
| 212 | if (!cpu_is_omap34xx()) | 493 | if (!cpu_is_omap34xx()) |
| 213 | return; | 494 | return; |
| @@ -217,9 +498,8 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | |||
| 217 | return; | 498 | return; |
| 218 | } | 499 | } |
| 219 | mcbsp = id_to_mcbsp_ptr(id); | 500 | mcbsp = id_to_mcbsp_ptr(id); |
| 220 | io_base = mcbsp->io_base; | ||
| 221 | 501 | ||
| 222 | OMAP_MCBSP_WRITE(io_base, THRSH2, threshold); | 502 | MCBSP_WRITE(mcbsp, THRSH2, threshold); |
| 223 | } | 503 | } |
| 224 | EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); | 504 | EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); |
| 225 | 505 | ||
| @@ -231,7 +511,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); | |||
| 231 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | 511 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) |
| 232 | { | 512 | { |
| 233 | struct omap_mcbsp *mcbsp; | 513 | struct omap_mcbsp *mcbsp; |
| 234 | void __iomem *io_base; | ||
| 235 | 514 | ||
| 236 | if (!cpu_is_omap34xx()) | 515 | if (!cpu_is_omap34xx()) |
| 237 | return; | 516 | return; |
| @@ -241,9 +520,8 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | |||
| 241 | return; | 520 | return; |
| 242 | } | 521 | } |
| 243 | mcbsp = id_to_mcbsp_ptr(id); | 522 | mcbsp = id_to_mcbsp_ptr(id); |
| 244 | io_base = mcbsp->io_base; | ||
| 245 | 523 | ||
| 246 | OMAP_MCBSP_WRITE(io_base, THRSH1, threshold); | 524 | MCBSP_WRITE(mcbsp, THRSH1, threshold); |
| 247 | } | 525 | } |
| 248 | EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); | 526 | EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); |
| 249 | 527 | ||
| @@ -313,19 +591,18 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) | |||
| 313 | if (cpu_is_omap34xx()) { | 591 | if (cpu_is_omap34xx()) { |
| 314 | u16 syscon; | 592 | u16 syscon; |
| 315 | 593 | ||
| 316 | syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON); | 594 | syscon = MCBSP_READ(mcbsp, SYSCON); |
| 317 | syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); | 595 | syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); |
| 318 | 596 | ||
| 319 | if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { | 597 | if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { |
| 320 | syscon |= (ENAWAKEUP | SIDLEMODE(0x02) | | 598 | syscon |= (ENAWAKEUP | SIDLEMODE(0x02) | |
| 321 | CLOCKACTIVITY(0x02)); | 599 | CLOCKACTIVITY(0x02)); |
| 322 | OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, | 600 | MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); |
| 323 | XRDYEN | RRDYEN); | ||
| 324 | } else { | 601 | } else { |
| 325 | syscon |= SIDLEMODE(0x01); | 602 | syscon |= SIDLEMODE(0x01); |
| 326 | } | 603 | } |
| 327 | 604 | ||
| 328 | OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon); | 605 | MCBSP_WRITE(mcbsp, SYSCON, syscon); |
| 329 | } | 606 | } |
| 330 | } | 607 | } |
| 331 | 608 | ||
| @@ -337,7 +614,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) | |||
| 337 | if (cpu_is_omap34xx()) { | 614 | if (cpu_is_omap34xx()) { |
| 338 | u16 syscon; | 615 | u16 syscon; |
| 339 | 616 | ||
| 340 | syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON); | 617 | syscon = MCBSP_READ(mcbsp, SYSCON); |
| 341 | syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); | 618 | syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); |
| 342 | /* | 619 | /* |
| 343 | * HW bug workaround - If no_idle mode is taken, we need to | 620 | * HW bug workaround - If no_idle mode is taken, we need to |
| @@ -345,17 +622,19 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) | |||
| 345 | * device will not hit retention anymore. | 622 | * device will not hit retention anymore. |
| 346 | */ | 623 | */ |
| 347 | syscon |= SIDLEMODE(0x02); | 624 | syscon |= SIDLEMODE(0x02); |
| 348 | OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon); | 625 | MCBSP_WRITE(mcbsp, SYSCON, syscon); |
| 349 | 626 | ||
| 350 | syscon &= ~(SIDLEMODE(0x03)); | 627 | syscon &= ~(SIDLEMODE(0x03)); |
| 351 | OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon); | 628 | MCBSP_WRITE(mcbsp, SYSCON, syscon); |
| 352 | 629 | ||
| 353 | OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0); | 630 | MCBSP_WRITE(mcbsp, WAKEUPEN, 0); |
| 354 | } | 631 | } |
| 355 | } | 632 | } |
| 356 | #else | 633 | #else |
| 357 | static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {} | 634 | static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {} |
| 358 | static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {} | 635 | static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {} |
| 636 | static inline void omap_st_start(struct omap_mcbsp *mcbsp) {} | ||
| 637 | static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {} | ||
| 359 | #endif | 638 | #endif |
| 360 | 639 | ||
| 361 | /* | 640 | /* |
| @@ -392,6 +671,7 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type); | |||
| 392 | int omap_mcbsp_request(unsigned int id) | 671 | int omap_mcbsp_request(unsigned int id) |
| 393 | { | 672 | { |
| 394 | struct omap_mcbsp *mcbsp; | 673 | struct omap_mcbsp *mcbsp; |
| 674 | void *reg_cache; | ||
| 395 | int err; | 675 | int err; |
| 396 | 676 | ||
| 397 | if (!omap_mcbsp_check_valid_id(id)) { | 677 | if (!omap_mcbsp_check_valid_id(id)) { |
| @@ -400,15 +680,21 @@ int omap_mcbsp_request(unsigned int id) | |||
| 400 | } | 680 | } |
| 401 | mcbsp = id_to_mcbsp_ptr(id); | 681 | mcbsp = id_to_mcbsp_ptr(id); |
| 402 | 682 | ||
| 683 | reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL); | ||
| 684 | if (!reg_cache) { | ||
| 685 | return -ENOMEM; | ||
| 686 | } | ||
| 687 | |||
| 403 | spin_lock(&mcbsp->lock); | 688 | spin_lock(&mcbsp->lock); |
| 404 | if (!mcbsp->free) { | 689 | if (!mcbsp->free) { |
| 405 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", | 690 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", |
| 406 | mcbsp->id); | 691 | mcbsp->id); |
| 407 | spin_unlock(&mcbsp->lock); | 692 | err = -EBUSY; |
| 408 | return -EBUSY; | 693 | goto err_kfree; |
| 409 | } | 694 | } |
| 410 | 695 | ||
| 411 | mcbsp->free = 0; | 696 | mcbsp->free = 0; |
| 697 | mcbsp->reg_cache = reg_cache; | ||
| 412 | spin_unlock(&mcbsp->lock); | 698 | spin_unlock(&mcbsp->lock); |
| 413 | 699 | ||
| 414 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) | 700 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) |
| @@ -424,8 +710,8 @@ int omap_mcbsp_request(unsigned int id) | |||
| 424 | * Make sure that transmitter, receiver and sample-rate generator are | 710 | * Make sure that transmitter, receiver and sample-rate generator are |
| 425 | * not running before activating IRQs. | 711 | * not running before activating IRQs. |
| 426 | */ | 712 | */ |
| 427 | OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0); | 713 | MCBSP_WRITE(mcbsp, SPCR1, 0); |
| 428 | OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0); | 714 | MCBSP_WRITE(mcbsp, SPCR2, 0); |
| 429 | 715 | ||
| 430 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { | 716 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { |
| 431 | /* We need to get IRQs here */ | 717 | /* We need to get IRQs here */ |
| @@ -436,7 +722,7 @@ int omap_mcbsp_request(unsigned int id) | |||
| 436 | dev_err(mcbsp->dev, "Unable to request TX IRQ %d " | 722 | dev_err(mcbsp->dev, "Unable to request TX IRQ %d " |
| 437 | "for McBSP%d\n", mcbsp->tx_irq, | 723 | "for McBSP%d\n", mcbsp->tx_irq, |
| 438 | mcbsp->id); | 724 | mcbsp->id); |
| 439 | goto error; | 725 | goto err_clk_disable; |
| 440 | } | 726 | } |
| 441 | 727 | ||
| 442 | init_completion(&mcbsp->rx_irq_completion); | 728 | init_completion(&mcbsp->rx_irq_completion); |
| @@ -446,16 +732,16 @@ int omap_mcbsp_request(unsigned int id) | |||
| 446 | dev_err(mcbsp->dev, "Unable to request RX IRQ %d " | 732 | dev_err(mcbsp->dev, "Unable to request RX IRQ %d " |
| 447 | "for McBSP%d\n", mcbsp->rx_irq, | 733 | "for McBSP%d\n", mcbsp->rx_irq, |
| 448 | mcbsp->id); | 734 | mcbsp->id); |
| 449 | goto tx_irq; | 735 | goto err_free_irq; |
| 450 | } | 736 | } |
| 451 | } | 737 | } |
| 452 | 738 | ||
| 453 | return 0; | 739 | return 0; |
| 454 | tx_irq: | 740 | err_free_irq: |
| 455 | free_irq(mcbsp->tx_irq, (void *)mcbsp); | 741 | free_irq(mcbsp->tx_irq, (void *)mcbsp); |
| 456 | error: | 742 | err_clk_disable: |
| 457 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) | 743 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
| 458 | mcbsp->pdata->ops->free(id); | 744 | mcbsp->pdata->ops->free(id); |
| 459 | 745 | ||
| 460 | /* Do procedure specific to omap34xx arch, if applicable */ | 746 | /* Do procedure specific to omap34xx arch, if applicable */ |
| 461 | omap34xx_mcbsp_free(mcbsp); | 747 | omap34xx_mcbsp_free(mcbsp); |
| @@ -463,7 +749,12 @@ error: | |||
| 463 | clk_disable(mcbsp->fclk); | 749 | clk_disable(mcbsp->fclk); |
| 464 | clk_disable(mcbsp->iclk); | 750 | clk_disable(mcbsp->iclk); |
| 465 | 751 | ||
| 752 | spin_lock(&mcbsp->lock); | ||
| 466 | mcbsp->free = 1; | 753 | mcbsp->free = 1; |
| 754 | mcbsp->reg_cache = NULL; | ||
| 755 | err_kfree: | ||
| 756 | spin_unlock(&mcbsp->lock); | ||
| 757 | kfree(reg_cache); | ||
| 467 | 758 | ||
| 468 | return err; | 759 | return err; |
| 469 | } | 760 | } |
| @@ -472,6 +763,7 @@ EXPORT_SYMBOL(omap_mcbsp_request); | |||
| 472 | void omap_mcbsp_free(unsigned int id) | 763 | void omap_mcbsp_free(unsigned int id) |
| 473 | { | 764 | { |
| 474 | struct omap_mcbsp *mcbsp; | 765 | struct omap_mcbsp *mcbsp; |
| 766 | void *reg_cache; | ||
| 475 | 767 | ||
| 476 | if (!omap_mcbsp_check_valid_id(id)) { | 768 | if (!omap_mcbsp_check_valid_id(id)) { |
| 477 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | 769 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); |
| @@ -494,16 +786,18 @@ void omap_mcbsp_free(unsigned int id) | |||
| 494 | free_irq(mcbsp->tx_irq, (void *)mcbsp); | 786 | free_irq(mcbsp->tx_irq, (void *)mcbsp); |
| 495 | } | 787 | } |
| 496 | 788 | ||
| 497 | spin_lock(&mcbsp->lock); | 789 | reg_cache = mcbsp->reg_cache; |
| 498 | if (mcbsp->free) { | ||
| 499 | dev_err(mcbsp->dev, "McBSP%d was not reserved\n", | ||
| 500 | mcbsp->id); | ||
| 501 | spin_unlock(&mcbsp->lock); | ||
| 502 | return; | ||
| 503 | } | ||
| 504 | 790 | ||
| 505 | mcbsp->free = 1; | 791 | spin_lock(&mcbsp->lock); |
| 792 | if (mcbsp->free) | ||
| 793 | dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); | ||
| 794 | else | ||
| 795 | mcbsp->free = 1; | ||
| 796 | mcbsp->reg_cache = NULL; | ||
| 506 | spin_unlock(&mcbsp->lock); | 797 | spin_unlock(&mcbsp->lock); |
| 798 | |||
| 799 | if (reg_cache) | ||
| 800 | kfree(reg_cache); | ||
| 507 | } | 801 | } |
| 508 | EXPORT_SYMBOL(omap_mcbsp_free); | 802 | EXPORT_SYMBOL(omap_mcbsp_free); |
| 509 | 803 | ||
| @@ -515,7 +809,6 @@ EXPORT_SYMBOL(omap_mcbsp_free); | |||
| 515 | void omap_mcbsp_start(unsigned int id, int tx, int rx) | 809 | void omap_mcbsp_start(unsigned int id, int tx, int rx) |
| 516 | { | 810 | { |
| 517 | struct omap_mcbsp *mcbsp; | 811 | struct omap_mcbsp *mcbsp; |
| 518 | void __iomem *io_base; | ||
| 519 | int idle; | 812 | int idle; |
| 520 | u16 w; | 813 | u16 w; |
| 521 | 814 | ||
| @@ -524,28 +817,30 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) | |||
| 524 | return; | 817 | return; |
| 525 | } | 818 | } |
| 526 | mcbsp = id_to_mcbsp_ptr(id); | 819 | mcbsp = id_to_mcbsp_ptr(id); |
| 527 | io_base = mcbsp->io_base; | ||
| 528 | 820 | ||
| 529 | mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7; | 821 | if (cpu_is_omap34xx()) |
| 530 | mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7; | 822 | omap_st_start(mcbsp); |
| 823 | |||
| 824 | mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; | ||
| 825 | mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; | ||
| 531 | 826 | ||
| 532 | idle = !((OMAP_MCBSP_READ(io_base, SPCR2) | | 827 | idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | |
| 533 | OMAP_MCBSP_READ(io_base, SPCR1)) & 1); | 828 | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); |
| 534 | 829 | ||
| 535 | if (idle) { | 830 | if (idle) { |
| 536 | /* Start the sample generator */ | 831 | /* Start the sample generator */ |
| 537 | w = OMAP_MCBSP_READ(io_base, SPCR2); | 832 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
| 538 | OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6)); | 833 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); |
| 539 | } | 834 | } |
| 540 | 835 | ||
| 541 | /* Enable transmitter and receiver */ | 836 | /* Enable transmitter and receiver */ |
| 542 | tx &= 1; | 837 | tx &= 1; |
| 543 | w = OMAP_MCBSP_READ(io_base, SPCR2); | 838 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
| 544 | OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx); | 839 | MCBSP_WRITE(mcbsp, SPCR2, w | tx); |
| 545 | 840 | ||
| 546 | rx &= 1; | 841 | rx &= 1; |
| 547 | w = OMAP_MCBSP_READ(io_base, SPCR1); | 842 | w = MCBSP_READ_CACHE(mcbsp, SPCR1); |
| 548 | OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx); | 843 | MCBSP_WRITE(mcbsp, SPCR1, w | rx); |
| 549 | 844 | ||
| 550 | /* | 845 | /* |
| 551 | * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec | 846 | * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec |
| @@ -557,18 +852,18 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) | |||
| 557 | 852 | ||
| 558 | if (idle) { | 853 | if (idle) { |
| 559 | /* Start frame sync */ | 854 | /* Start frame sync */ |
| 560 | w = OMAP_MCBSP_READ(io_base, SPCR2); | 855 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
| 561 | OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7)); | 856 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); |
| 562 | } | 857 | } |
| 563 | 858 | ||
| 564 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | 859 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
| 565 | /* Release the transmitter and receiver */ | 860 | /* Release the transmitter and receiver */ |
| 566 | w = OMAP_MCBSP_READ(io_base, XCCR); | 861 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
| 567 | w &= ~(tx ? XDISABLE : 0); | 862 | w &= ~(tx ? XDISABLE : 0); |
| 568 | OMAP_MCBSP_WRITE(io_base, XCCR, w); | 863 | MCBSP_WRITE(mcbsp, XCCR, w); |
| 569 | w = OMAP_MCBSP_READ(io_base, RCCR); | 864 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
| 570 | w &= ~(rx ? RDISABLE : 0); | 865 | w &= ~(rx ? RDISABLE : 0); |
| 571 | OMAP_MCBSP_WRITE(io_base, RCCR, w); | 866 | MCBSP_WRITE(mcbsp, RCCR, w); |
| 572 | } | 867 | } |
| 573 | 868 | ||
| 574 | /* Dump McBSP Regs */ | 869 | /* Dump McBSP Regs */ |
| @@ -579,7 +874,6 @@ EXPORT_SYMBOL(omap_mcbsp_start); | |||
| 579 | void omap_mcbsp_stop(unsigned int id, int tx, int rx) | 874 | void omap_mcbsp_stop(unsigned int id, int tx, int rx) |
| 580 | { | 875 | { |
| 581 | struct omap_mcbsp *mcbsp; | 876 | struct omap_mcbsp *mcbsp; |
| 582 | void __iomem *io_base; | ||
| 583 | int idle; | 877 | int idle; |
| 584 | u16 w; | 878 | u16 w; |
| 585 | 879 | ||
| @@ -589,36 +883,38 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) | |||
| 589 | } | 883 | } |
| 590 | 884 | ||
| 591 | mcbsp = id_to_mcbsp_ptr(id); | 885 | mcbsp = id_to_mcbsp_ptr(id); |
| 592 | io_base = mcbsp->io_base; | ||
| 593 | 886 | ||
| 594 | /* Reset transmitter */ | 887 | /* Reset transmitter */ |
| 595 | tx &= 1; | 888 | tx &= 1; |
| 596 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | 889 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
| 597 | w = OMAP_MCBSP_READ(io_base, XCCR); | 890 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
| 598 | w |= (tx ? XDISABLE : 0); | 891 | w |= (tx ? XDISABLE : 0); |
| 599 | OMAP_MCBSP_WRITE(io_base, XCCR, w); | 892 | MCBSP_WRITE(mcbsp, XCCR, w); |
| 600 | } | 893 | } |
| 601 | w = OMAP_MCBSP_READ(io_base, SPCR2); | 894 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
| 602 | OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx); | 895 | MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); |
| 603 | 896 | ||
| 604 | /* Reset receiver */ | 897 | /* Reset receiver */ |
| 605 | rx &= 1; | 898 | rx &= 1; |
| 606 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | 899 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
| 607 | w = OMAP_MCBSP_READ(io_base, RCCR); | 900 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
| 608 | w |= (rx ? RDISABLE : 0); | 901 | w |= (rx ? RDISABLE : 0); |
| 609 | OMAP_MCBSP_WRITE(io_base, RCCR, w); | 902 | MCBSP_WRITE(mcbsp, RCCR, w); |
| 610 | } | 903 | } |
| 611 | w = OMAP_MCBSP_READ(io_base, SPCR1); | 904 | w = MCBSP_READ_CACHE(mcbsp, SPCR1); |
| 612 | OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx); | 905 | MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); |
| 613 | 906 | ||
| 614 | idle = !((OMAP_MCBSP_READ(io_base, SPCR2) | | 907 | idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | |
| 615 | OMAP_MCBSP_READ(io_base, SPCR1)) & 1); | 908 | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); |
| 616 | 909 | ||
| 617 | if (idle) { | 910 | if (idle) { |
| 618 | /* Reset the sample rate generator */ | 911 | /* Reset the sample rate generator */ |
| 619 | w = OMAP_MCBSP_READ(io_base, SPCR2); | 912 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
| 620 | OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); | 913 | MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); |
| 621 | } | 914 | } |
| 915 | |||
| 916 | if (cpu_is_omap34xx()) | ||
| 917 | omap_st_stop(mcbsp); | ||
| 622 | } | 918 | } |
| 623 | EXPORT_SYMBOL(omap_mcbsp_stop); | 919 | EXPORT_SYMBOL(omap_mcbsp_stop); |
| 624 | 920 | ||
| @@ -626,7 +922,6 @@ EXPORT_SYMBOL(omap_mcbsp_stop); | |||
| 626 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf) | 922 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf) |
| 627 | { | 923 | { |
| 628 | struct omap_mcbsp *mcbsp; | 924 | struct omap_mcbsp *mcbsp; |
| 629 | void __iomem *base; | ||
| 630 | 925 | ||
| 631 | if (!omap_mcbsp_check_valid_id(id)) { | 926 | if (!omap_mcbsp_check_valid_id(id)) { |
| 632 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | 927 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); |
| @@ -634,28 +929,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf) | |||
| 634 | } | 929 | } |
| 635 | 930 | ||
| 636 | mcbsp = id_to_mcbsp_ptr(id); | 931 | mcbsp = id_to_mcbsp_ptr(id); |
| 637 | base = mcbsp->io_base; | ||
| 638 | 932 | ||
| 639 | writew(buf, base + OMAP_MCBSP_REG_DXR1); | 933 | MCBSP_WRITE(mcbsp, DXR1, buf); |
| 640 | /* if frame sync error - clear the error */ | 934 | /* if frame sync error - clear the error */ |
| 641 | if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { | 935 | if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) { |
| 642 | /* clear error */ | 936 | /* clear error */ |
| 643 | writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR), | 937 | MCBSP_WRITE(mcbsp, SPCR2, |
| 644 | base + OMAP_MCBSP_REG_SPCR2); | 938 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XSYNC_ERR)); |
| 645 | /* resend */ | 939 | /* resend */ |
| 646 | return -1; | 940 | return -1; |
| 647 | } else { | 941 | } else { |
| 648 | /* wait for transmit confirmation */ | 942 | /* wait for transmit confirmation */ |
| 649 | int attemps = 0; | 943 | int attemps = 0; |
| 650 | while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) { | 944 | while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) { |
| 651 | if (attemps++ > 1000) { | 945 | if (attemps++ > 1000) { |
| 652 | writew(readw(base + OMAP_MCBSP_REG_SPCR2) & | 946 | MCBSP_WRITE(mcbsp, SPCR2, |
| 653 | (~XRST), | 947 | MCBSP_READ_CACHE(mcbsp, SPCR2) & |
| 654 | base + OMAP_MCBSP_REG_SPCR2); | 948 | (~XRST)); |
| 655 | udelay(10); | 949 | udelay(10); |
| 656 | writew(readw(base + OMAP_MCBSP_REG_SPCR2) | | 950 | MCBSP_WRITE(mcbsp, SPCR2, |
| 657 | (XRST), | 951 | MCBSP_READ_CACHE(mcbsp, SPCR2) | |
| 658 | base + OMAP_MCBSP_REG_SPCR2); | 952 | (XRST)); |
| 659 | udelay(10); | 953 | udelay(10); |
| 660 | dev_err(mcbsp->dev, "Could not write to" | 954 | dev_err(mcbsp->dev, "Could not write to" |
| 661 | " McBSP%d Register\n", mcbsp->id); | 955 | " McBSP%d Register\n", mcbsp->id); |
| @@ -671,7 +965,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite); | |||
| 671 | int omap_mcbsp_pollread(unsigned int id, u16 *buf) | 965 | int omap_mcbsp_pollread(unsigned int id, u16 *buf) |
| 672 | { | 966 | { |
| 673 | struct omap_mcbsp *mcbsp; | 967 | struct omap_mcbsp *mcbsp; |
| 674 | void __iomem *base; | ||
| 675 | 968 | ||
| 676 | if (!omap_mcbsp_check_valid_id(id)) { | 969 | if (!omap_mcbsp_check_valid_id(id)) { |
| 677 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | 970 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); |
| @@ -679,26 +972,25 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf) | |||
| 679 | } | 972 | } |
| 680 | mcbsp = id_to_mcbsp_ptr(id); | 973 | mcbsp = id_to_mcbsp_ptr(id); |
| 681 | 974 | ||
| 682 | base = mcbsp->io_base; | ||
| 683 | /* if frame sync error - clear the error */ | 975 | /* if frame sync error - clear the error */ |
| 684 | if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { | 976 | if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) { |
| 685 | /* clear error */ | 977 | /* clear error */ |
| 686 | writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR), | 978 | MCBSP_WRITE(mcbsp, SPCR1, |
| 687 | base + OMAP_MCBSP_REG_SPCR1); | 979 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RSYNC_ERR)); |
| 688 | /* resend */ | 980 | /* resend */ |
| 689 | return -1; | 981 | return -1; |
| 690 | } else { | 982 | } else { |
| 691 | /* wait for recieve confirmation */ | 983 | /* wait for recieve confirmation */ |
| 692 | int attemps = 0; | 984 | int attemps = 0; |
| 693 | while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) { | 985 | while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) { |
| 694 | if (attemps++ > 1000) { | 986 | if (attemps++ > 1000) { |
| 695 | writew(readw(base + OMAP_MCBSP_REG_SPCR1) & | 987 | MCBSP_WRITE(mcbsp, SPCR1, |
| 696 | (~RRST), | 988 | MCBSP_READ_CACHE(mcbsp, SPCR1) & |
| 697 | base + OMAP_MCBSP_REG_SPCR1); | 989 | (~RRST)); |
| 698 | udelay(10); | 990 | udelay(10); |
| 699 | writew(readw(base + OMAP_MCBSP_REG_SPCR1) | | 991 | MCBSP_WRITE(mcbsp, SPCR1, |
| 700 | (RRST), | 992 | MCBSP_READ_CACHE(mcbsp, SPCR1) | |
| 701 | base + OMAP_MCBSP_REG_SPCR1); | 993 | (RRST)); |
| 702 | udelay(10); | 994 | udelay(10); |
| 703 | dev_err(mcbsp->dev, "Could not read from" | 995 | dev_err(mcbsp->dev, "Could not read from" |
| 704 | " McBSP%d Register\n", mcbsp->id); | 996 | " McBSP%d Register\n", mcbsp->id); |
| @@ -706,7 +998,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf) | |||
| 706 | } | 998 | } |
| 707 | } | 999 | } |
| 708 | } | 1000 | } |
| 709 | *buf = readw(base + OMAP_MCBSP_REG_DRR1); | 1001 | *buf = MCBSP_READ(mcbsp, DRR1); |
| 710 | 1002 | ||
| 711 | return 0; | 1003 | return 0; |
| 712 | } | 1004 | } |
| @@ -718,7 +1010,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollread); | |||
| 718 | void omap_mcbsp_xmit_word(unsigned int id, u32 word) | 1010 | void omap_mcbsp_xmit_word(unsigned int id, u32 word) |
| 719 | { | 1011 | { |
| 720 | struct omap_mcbsp *mcbsp; | 1012 | struct omap_mcbsp *mcbsp; |
| 721 | void __iomem *io_base; | ||
| 722 | omap_mcbsp_word_length word_length; | 1013 | omap_mcbsp_word_length word_length; |
| 723 | 1014 | ||
| 724 | if (!omap_mcbsp_check_valid_id(id)) { | 1015 | if (!omap_mcbsp_check_valid_id(id)) { |
| @@ -727,21 +1018,19 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word) | |||
| 727 | } | 1018 | } |
| 728 | 1019 | ||
| 729 | mcbsp = id_to_mcbsp_ptr(id); | 1020 | mcbsp = id_to_mcbsp_ptr(id); |
| 730 | io_base = mcbsp->io_base; | ||
| 731 | word_length = mcbsp->tx_word_length; | 1021 | word_length = mcbsp->tx_word_length; |
| 732 | 1022 | ||
| 733 | wait_for_completion(&mcbsp->tx_irq_completion); | 1023 | wait_for_completion(&mcbsp->tx_irq_completion); |
| 734 | 1024 | ||
| 735 | if (word_length > OMAP_MCBSP_WORD_16) | 1025 | if (word_length > OMAP_MCBSP_WORD_16) |
| 736 | OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); | 1026 | MCBSP_WRITE(mcbsp, DXR2, word >> 16); |
| 737 | OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); | 1027 | MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); |
| 738 | } | 1028 | } |
| 739 | EXPORT_SYMBOL(omap_mcbsp_xmit_word); | 1029 | EXPORT_SYMBOL(omap_mcbsp_xmit_word); |
| 740 | 1030 | ||
| 741 | u32 omap_mcbsp_recv_word(unsigned int id) | 1031 | u32 omap_mcbsp_recv_word(unsigned int id) |
| 742 | { | 1032 | { |
| 743 | struct omap_mcbsp *mcbsp; | 1033 | struct omap_mcbsp *mcbsp; |
| 744 | void __iomem *io_base; | ||
| 745 | u16 word_lsb, word_msb = 0; | 1034 | u16 word_lsb, word_msb = 0; |
| 746 | omap_mcbsp_word_length word_length; | 1035 | omap_mcbsp_word_length word_length; |
| 747 | 1036 | ||
| @@ -752,13 +1041,12 @@ u32 omap_mcbsp_recv_word(unsigned int id) | |||
| 752 | mcbsp = id_to_mcbsp_ptr(id); | 1041 | mcbsp = id_to_mcbsp_ptr(id); |
| 753 | 1042 | ||
| 754 | word_length = mcbsp->rx_word_length; | 1043 | word_length = mcbsp->rx_word_length; |
| 755 | io_base = mcbsp->io_base; | ||
| 756 | 1044 | ||
| 757 | wait_for_completion(&mcbsp->rx_irq_completion); | 1045 | wait_for_completion(&mcbsp->rx_irq_completion); |
| 758 | 1046 | ||
| 759 | if (word_length > OMAP_MCBSP_WORD_16) | 1047 | if (word_length > OMAP_MCBSP_WORD_16) |
| 760 | word_msb = OMAP_MCBSP_READ(io_base, DRR2); | 1048 | word_msb = MCBSP_READ(mcbsp, DRR2); |
| 761 | word_lsb = OMAP_MCBSP_READ(io_base, DRR1); | 1049 | word_lsb = MCBSP_READ(mcbsp, DRR1); |
| 762 | 1050 | ||
| 763 | return (word_lsb | (word_msb << 16)); | 1051 | return (word_lsb | (word_msb << 16)); |
| 764 | } | 1052 | } |
| @@ -767,7 +1055,6 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word); | |||
| 767 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) | 1055 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) |
| 768 | { | 1056 | { |
| 769 | struct omap_mcbsp *mcbsp; | 1057 | struct omap_mcbsp *mcbsp; |
| 770 | void __iomem *io_base; | ||
| 771 | omap_mcbsp_word_length tx_word_length; | 1058 | omap_mcbsp_word_length tx_word_length; |
| 772 | omap_mcbsp_word_length rx_word_length; | 1059 | omap_mcbsp_word_length rx_word_length; |
| 773 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; | 1060 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; |
| @@ -777,7 +1064,6 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) | |||
| 777 | return -ENODEV; | 1064 | return -ENODEV; |
| 778 | } | 1065 | } |
| 779 | mcbsp = id_to_mcbsp_ptr(id); | 1066 | mcbsp = id_to_mcbsp_ptr(id); |
| 780 | io_base = mcbsp->io_base; | ||
| 781 | tx_word_length = mcbsp->tx_word_length; | 1067 | tx_word_length = mcbsp->tx_word_length; |
| 782 | rx_word_length = mcbsp->rx_word_length; | 1068 | rx_word_length = mcbsp->rx_word_length; |
| 783 | 1069 | ||
| @@ -785,14 +1071,16 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) | |||
| 785 | return -EINVAL; | 1071 | return -EINVAL; |
| 786 | 1072 | ||
| 787 | /* First we wait for the transmitter to be ready */ | 1073 | /* First we wait for the transmitter to be ready */ |
| 788 | spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); | 1074 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
| 789 | while (!(spcr2 & XRDY)) { | 1075 | while (!(spcr2 & XRDY)) { |
| 790 | spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); | 1076 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
| 791 | if (attempts++ > 1000) { | 1077 | if (attempts++ > 1000) { |
| 792 | /* We must reset the transmitter */ | 1078 | /* We must reset the transmitter */ |
| 793 | OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); | 1079 | MCBSP_WRITE(mcbsp, SPCR2, |
| 1080 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); | ||
| 794 | udelay(10); | 1081 | udelay(10); |
| 795 | OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); | 1082 | MCBSP_WRITE(mcbsp, SPCR2, |
| 1083 | MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); | ||
| 796 | udelay(10); | 1084 | udelay(10); |
| 797 | dev_err(mcbsp->dev, "McBSP%d transmitter not " | 1085 | dev_err(mcbsp->dev, "McBSP%d transmitter not " |
| 798 | "ready\n", mcbsp->id); | 1086 | "ready\n", mcbsp->id); |
| @@ -802,18 +1090,20 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) | |||
| 802 | 1090 | ||
| 803 | /* Now we can push the data */ | 1091 | /* Now we can push the data */ |
| 804 | if (tx_word_length > OMAP_MCBSP_WORD_16) | 1092 | if (tx_word_length > OMAP_MCBSP_WORD_16) |
| 805 | OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); | 1093 | MCBSP_WRITE(mcbsp, DXR2, word >> 16); |
| 806 | OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); | 1094 | MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); |
| 807 | 1095 | ||
| 808 | /* We wait for the receiver to be ready */ | 1096 | /* We wait for the receiver to be ready */ |
| 809 | spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); | 1097 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
| 810 | while (!(spcr1 & RRDY)) { | 1098 | while (!(spcr1 & RRDY)) { |
| 811 | spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); | 1099 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
| 812 | if (attempts++ > 1000) { | 1100 | if (attempts++ > 1000) { |
| 813 | /* We must reset the receiver */ | 1101 | /* We must reset the receiver */ |
| 814 | OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); | 1102 | MCBSP_WRITE(mcbsp, SPCR1, |
| 1103 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); | ||
| 815 | udelay(10); | 1104 | udelay(10); |
| 816 | OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); | 1105 | MCBSP_WRITE(mcbsp, SPCR1, |
| 1106 | MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); | ||
| 817 | udelay(10); | 1107 | udelay(10); |
| 818 | dev_err(mcbsp->dev, "McBSP%d receiver not " | 1108 | dev_err(mcbsp->dev, "McBSP%d receiver not " |
| 819 | "ready\n", mcbsp->id); | 1109 | "ready\n", mcbsp->id); |
| @@ -823,8 +1113,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) | |||
| 823 | 1113 | ||
| 824 | /* Receiver is ready, let's read the dummy data */ | 1114 | /* Receiver is ready, let's read the dummy data */ |
| 825 | if (rx_word_length > OMAP_MCBSP_WORD_16) | 1115 | if (rx_word_length > OMAP_MCBSP_WORD_16) |
| 826 | word_msb = OMAP_MCBSP_READ(io_base, DRR2); | 1116 | word_msb = MCBSP_READ(mcbsp, DRR2); |
| 827 | word_lsb = OMAP_MCBSP_READ(io_base, DRR1); | 1117 | word_lsb = MCBSP_READ(mcbsp, DRR1); |
| 828 | 1118 | ||
| 829 | return 0; | 1119 | return 0; |
| 830 | } | 1120 | } |
| @@ -834,7 +1124,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) | |||
| 834 | { | 1124 | { |
| 835 | struct omap_mcbsp *mcbsp; | 1125 | struct omap_mcbsp *mcbsp; |
| 836 | u32 clock_word = 0; | 1126 | u32 clock_word = 0; |
| 837 | void __iomem *io_base; | ||
| 838 | omap_mcbsp_word_length tx_word_length; | 1127 | omap_mcbsp_word_length tx_word_length; |
| 839 | omap_mcbsp_word_length rx_word_length; | 1128 | omap_mcbsp_word_length rx_word_length; |
| 840 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; | 1129 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; |
| @@ -845,7 +1134,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) | |||
| 845 | } | 1134 | } |
| 846 | 1135 | ||
| 847 | mcbsp = id_to_mcbsp_ptr(id); | 1136 | mcbsp = id_to_mcbsp_ptr(id); |
| 848 | io_base = mcbsp->io_base; | ||
| 849 | 1137 | ||
| 850 | tx_word_length = mcbsp->tx_word_length; | 1138 | tx_word_length = mcbsp->tx_word_length; |
| 851 | rx_word_length = mcbsp->rx_word_length; | 1139 | rx_word_length = mcbsp->rx_word_length; |
| @@ -854,14 +1142,16 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) | |||
| 854 | return -EINVAL; | 1142 | return -EINVAL; |
| 855 | 1143 | ||
| 856 | /* First we wait for the transmitter to be ready */ | 1144 | /* First we wait for the transmitter to be ready */ |
| 857 | spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); | 1145 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
| 858 | while (!(spcr2 & XRDY)) { | 1146 | while (!(spcr2 & XRDY)) { |
| 859 | spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); | 1147 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
| 860 | if (attempts++ > 1000) { | 1148 | if (attempts++ > 1000) { |
| 861 | /* We must reset the transmitter */ | 1149 | /* We must reset the transmitter */ |
| 862 | OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); | 1150 | MCBSP_WRITE(mcbsp, SPCR2, |
| 1151 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); | ||
| 863 | udelay(10); | 1152 | udelay(10); |
| 864 | OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); | 1153 | MCBSP_WRITE(mcbsp, SPCR2, |
| 1154 | MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); | ||
| 865 | udelay(10); | 1155 | udelay(10); |
| 866 | dev_err(mcbsp->dev, "McBSP%d transmitter not " | 1156 | dev_err(mcbsp->dev, "McBSP%d transmitter not " |
| 867 | "ready\n", mcbsp->id); | 1157 | "ready\n", mcbsp->id); |
| @@ -871,18 +1161,20 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) | |||
| 871 | 1161 | ||
| 872 | /* We first need to enable the bus clock */ | 1162 | /* We first need to enable the bus clock */ |
| 873 | if (tx_word_length > OMAP_MCBSP_WORD_16) | 1163 | if (tx_word_length > OMAP_MCBSP_WORD_16) |
| 874 | OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16); | 1164 | MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16); |
| 875 | OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff); | 1165 | MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff); |
| 876 | 1166 | ||
| 877 | /* We wait for the receiver to be ready */ | 1167 | /* We wait for the receiver to be ready */ |
| 878 | spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); | 1168 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
| 879 | while (!(spcr1 & RRDY)) { | 1169 | while (!(spcr1 & RRDY)) { |
| 880 | spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); | 1170 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
| 881 | if (attempts++ > 1000) { | 1171 | if (attempts++ > 1000) { |
| 882 | /* We must reset the receiver */ | 1172 | /* We must reset the receiver */ |
| 883 | OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); | 1173 | MCBSP_WRITE(mcbsp, SPCR1, |
| 1174 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); | ||
| 884 | udelay(10); | 1175 | udelay(10); |
| 885 | OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); | 1176 | MCBSP_WRITE(mcbsp, SPCR1, |
| 1177 | MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); | ||
| 886 | udelay(10); | 1178 | udelay(10); |
| 887 | dev_err(mcbsp->dev, "McBSP%d receiver not " | 1179 | dev_err(mcbsp->dev, "McBSP%d receiver not " |
| 888 | "ready\n", mcbsp->id); | 1180 | "ready\n", mcbsp->id); |
| @@ -892,8 +1184,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) | |||
| 892 | 1184 | ||
| 893 | /* Receiver is ready, there is something for us */ | 1185 | /* Receiver is ready, there is something for us */ |
| 894 | if (rx_word_length > OMAP_MCBSP_WORD_16) | 1186 | if (rx_word_length > OMAP_MCBSP_WORD_16) |
| 895 | word_msb = OMAP_MCBSP_READ(io_base, DRR2); | 1187 | word_msb = MCBSP_READ(mcbsp, DRR2); |
| 896 | word_lsb = OMAP_MCBSP_READ(io_base, DRR1); | 1188 | word_lsb = MCBSP_READ(mcbsp, DRR1); |
| 897 | 1189 | ||
| 898 | word[0] = (word_lsb | (word_msb << 16)); | 1190 | word[0] = (word_lsb | (word_msb << 16)); |
| 899 | 1191 | ||
| @@ -1107,7 +1399,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id, | |||
| 1107 | } | 1399 | } |
| 1108 | EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); | 1400 | EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); |
| 1109 | 1401 | ||
| 1110 | #ifdef CONFIG_ARCH_OMAP34XX | 1402 | #ifdef CONFIG_ARCH_OMAP3 |
| 1111 | #define max_thres(m) (mcbsp->pdata->buffer_size) | 1403 | #define max_thres(m) (mcbsp->pdata->buffer_size) |
| 1112 | #define valid_threshold(m, val) ((val) <= max_thres(m)) | 1404 | #define valid_threshold(m, val) ((val) <= max_thres(m)) |
| 1113 | #define THRESHOLD_PROP_BUILDER(prop) \ | 1405 | #define THRESHOLD_PROP_BUILDER(prop) \ |
| @@ -1198,6 +1490,64 @@ unlock: | |||
| 1198 | 1490 | ||
| 1199 | static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); | 1491 | static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); |
| 1200 | 1492 | ||
| 1493 | static ssize_t st_taps_show(struct device *dev, | ||
| 1494 | struct device_attribute *attr, char *buf) | ||
| 1495 | { | ||
| 1496 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | ||
| 1497 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | ||
| 1498 | ssize_t status = 0; | ||
| 1499 | int i; | ||
| 1500 | |||
| 1501 | spin_lock_irq(&mcbsp->lock); | ||
| 1502 | for (i = 0; i < st_data->nr_taps; i++) | ||
| 1503 | status += sprintf(&buf[status], (i ? ", %d" : "%d"), | ||
| 1504 | st_data->taps[i]); | ||
| 1505 | if (i) | ||
| 1506 | status += sprintf(&buf[status], "\n"); | ||
| 1507 | spin_unlock_irq(&mcbsp->lock); | ||
| 1508 | |||
| 1509 | return status; | ||
| 1510 | } | ||
| 1511 | |||
| 1512 | static ssize_t st_taps_store(struct device *dev, | ||
| 1513 | struct device_attribute *attr, | ||
| 1514 | const char *buf, size_t size) | ||
| 1515 | { | ||
| 1516 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | ||
| 1517 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | ||
| 1518 | int val, tmp, status, i = 0; | ||
| 1519 | |||
| 1520 | spin_lock_irq(&mcbsp->lock); | ||
| 1521 | memset(st_data->taps, 0, sizeof(st_data->taps)); | ||
| 1522 | st_data->nr_taps = 0; | ||
| 1523 | |||
| 1524 | do { | ||
| 1525 | status = sscanf(buf, "%d%n", &val, &tmp); | ||
| 1526 | if (status < 0 || status == 0) { | ||
| 1527 | size = -EINVAL; | ||
| 1528 | goto out; | ||
| 1529 | } | ||
| 1530 | if (val < -32768 || val > 32767) { | ||
| 1531 | size = -EINVAL; | ||
| 1532 | goto out; | ||
| 1533 | } | ||
| 1534 | st_data->taps[i++] = val; | ||
| 1535 | buf += tmp; | ||
| 1536 | if (*buf != ',') | ||
| 1537 | break; | ||
| 1538 | buf++; | ||
| 1539 | } while (1); | ||
| 1540 | |||
| 1541 | st_data->nr_taps = i; | ||
| 1542 | |||
| 1543 | out: | ||
| 1544 | spin_unlock_irq(&mcbsp->lock); | ||
| 1545 | |||
| 1546 | return size; | ||
| 1547 | } | ||
| 1548 | |||
| 1549 | static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store); | ||
| 1550 | |||
| 1201 | static const struct attribute *additional_attrs[] = { | 1551 | static const struct attribute *additional_attrs[] = { |
| 1202 | &dev_attr_max_tx_thres.attr, | 1552 | &dev_attr_max_tx_thres.attr, |
| 1203 | &dev_attr_max_rx_thres.attr, | 1553 | &dev_attr_max_rx_thres.attr, |
| @@ -1219,6 +1569,60 @@ static inline void __devexit omap_additional_remove(struct device *dev) | |||
| 1219 | sysfs_remove_group(&dev->kobj, &additional_attr_group); | 1569 | sysfs_remove_group(&dev->kobj, &additional_attr_group); |
| 1220 | } | 1570 | } |
| 1221 | 1571 | ||
| 1572 | static const struct attribute *sidetone_attrs[] = { | ||
| 1573 | &dev_attr_st_taps.attr, | ||
| 1574 | NULL, | ||
| 1575 | }; | ||
| 1576 | |||
| 1577 | static const struct attribute_group sidetone_attr_group = { | ||
| 1578 | .attrs = (struct attribute **)sidetone_attrs, | ||
| 1579 | }; | ||
| 1580 | |||
| 1581 | int __devinit omap_st_add(struct omap_mcbsp *mcbsp) | ||
| 1582 | { | ||
| 1583 | struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; | ||
| 1584 | struct omap_mcbsp_st_data *st_data; | ||
| 1585 | int err; | ||
| 1586 | |||
| 1587 | st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL); | ||
| 1588 | if (!st_data) { | ||
| 1589 | err = -ENOMEM; | ||
| 1590 | goto err1; | ||
| 1591 | } | ||
| 1592 | |||
| 1593 | st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); | ||
| 1594 | if (!st_data->io_base_st) { | ||
| 1595 | err = -ENOMEM; | ||
| 1596 | goto err2; | ||
| 1597 | } | ||
| 1598 | |||
| 1599 | err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group); | ||
| 1600 | if (err) | ||
| 1601 | goto err3; | ||
| 1602 | |||
| 1603 | mcbsp->st_data = st_data; | ||
| 1604 | return 0; | ||
| 1605 | |||
| 1606 | err3: | ||
| 1607 | iounmap(st_data->io_base_st); | ||
| 1608 | err2: | ||
| 1609 | kfree(st_data); | ||
| 1610 | err1: | ||
| 1611 | return err; | ||
| 1612 | |||
| 1613 | } | ||
| 1614 | |||
| 1615 | static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp) | ||
| 1616 | { | ||
| 1617 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | ||
| 1618 | |||
| 1619 | if (st_data) { | ||
| 1620 | sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); | ||
| 1621 | iounmap(st_data->io_base_st); | ||
| 1622 | kfree(st_data); | ||
| 1623 | } | ||
| 1624 | } | ||
| 1625 | |||
| 1222 | static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) | 1626 | static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) |
| 1223 | { | 1627 | { |
| 1224 | mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; | 1628 | mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; |
| @@ -1232,6 +1636,12 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) | |||
| 1232 | if (omap_additional_add(mcbsp->dev)) | 1636 | if (omap_additional_add(mcbsp->dev)) |
| 1233 | dev_warn(mcbsp->dev, | 1637 | dev_warn(mcbsp->dev, |
| 1234 | "Unable to create additional controls\n"); | 1638 | "Unable to create additional controls\n"); |
| 1639 | |||
| 1640 | if (mcbsp->id == 2 || mcbsp->id == 3) | ||
| 1641 | if (omap_st_add(mcbsp)) | ||
| 1642 | dev_warn(mcbsp->dev, | ||
| 1643 | "Unable to create sidetone controls\n"); | ||
| 1644 | |||
| 1235 | } else { | 1645 | } else { |
| 1236 | mcbsp->max_tx_thres = -EINVAL; | 1646 | mcbsp->max_tx_thres = -EINVAL; |
| 1237 | mcbsp->max_rx_thres = -EINVAL; | 1647 | mcbsp->max_rx_thres = -EINVAL; |
| @@ -1240,13 +1650,17 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) | |||
| 1240 | 1650 | ||
| 1241 | static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) | 1651 | static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) |
| 1242 | { | 1652 | { |
| 1243 | if (cpu_is_omap34xx()) | 1653 | if (cpu_is_omap34xx()) { |
| 1244 | omap_additional_remove(mcbsp->dev); | 1654 | omap_additional_remove(mcbsp->dev); |
| 1655 | |||
| 1656 | if (mcbsp->id == 2 || mcbsp->id == 3) | ||
| 1657 | omap_st_remove(mcbsp); | ||
| 1658 | } | ||
| 1245 | } | 1659 | } |
| 1246 | #else | 1660 | #else |
| 1247 | static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {} | 1661 | static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {} |
| 1248 | static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {} | 1662 | static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {} |
| 1249 | #endif /* CONFIG_ARCH_OMAP34XX */ | 1663 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 1250 | 1664 | ||
| 1251 | /* | 1665 | /* |
| 1252 | * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. | 1666 | * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. |
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 2ed72013c2e2..590435894848 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
| @@ -90,6 +90,8 @@ | |||
| 90 | #define IGNORE_WAKEUP_LAT 1 | 90 | #define IGNORE_WAKEUP_LAT 1 |
| 91 | 91 | ||
| 92 | 92 | ||
| 93 | #define OMAP_DEVICE_MAGIC 0xf00dcafe | ||
| 94 | |||
| 93 | /* Private functions */ | 95 | /* Private functions */ |
| 94 | 96 | ||
| 95 | /** | 97 | /** |
| @@ -138,10 +140,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) | |||
| 138 | "%llu nsec\n", od->pdev.name, od->pm_lat_level, | 140 | "%llu nsec\n", od->pdev.name, od->pm_lat_level, |
| 139 | act_lat); | 141 | act_lat); |
| 140 | 142 | ||
| 141 | WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " | 143 | if (act_lat > odpl->activate_lat) { |
| 142 | "activate step %d took longer than expected (%llu > %d)\n", | 144 | odpl->activate_lat_worst = act_lat; |
| 143 | od->pdev.name, od->pdev.id, od->pm_lat_level, | 145 | if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { |
| 144 | act_lat, odpl->activate_lat); | 146 | odpl->activate_lat = act_lat; |
| 147 | pr_warning("omap_device: %s.%d: new worst case " | ||
| 148 | "activate latency %d: %llu\n", | ||
| 149 | od->pdev.name, od->pdev.id, | ||
| 150 | od->pm_lat_level, act_lat); | ||
| 151 | } else | ||
| 152 | pr_warning("omap_device: %s.%d: activate " | ||
| 153 | "latency %d higher than exptected. " | ||
| 154 | "(%llu > %d)\n", | ||
| 155 | od->pdev.name, od->pdev.id, | ||
| 156 | od->pm_lat_level, act_lat, | ||
| 157 | odpl->activate_lat); | ||
| 158 | } | ||
| 145 | 159 | ||
| 146 | od->dev_wakeup_lat -= odpl->activate_lat; | 160 | od->dev_wakeup_lat -= odpl->activate_lat; |
| 147 | } | 161 | } |
| @@ -194,10 +208,23 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) | |||
| 194 | "%llu nsec\n", od->pdev.name, od->pm_lat_level, | 208 | "%llu nsec\n", od->pdev.name, od->pm_lat_level, |
| 195 | deact_lat); | 209 | deact_lat); |
| 196 | 210 | ||
| 197 | WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " | 211 | if (deact_lat > odpl->deactivate_lat) { |
| 198 | "deactivate step %d took longer than expected " | 212 | odpl->deactivate_lat_worst = deact_lat; |
| 199 | "(%llu > %d)\n", od->pdev.name, od->pdev.id, | 213 | if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { |
| 200 | od->pm_lat_level, deact_lat, odpl->deactivate_lat); | 214 | odpl->deactivate_lat = deact_lat; |
| 215 | pr_warning("omap_device: %s.%d: new worst case " | ||
| 216 | "deactivate latency %d: %llu\n", | ||
| 217 | od->pdev.name, od->pdev.id, | ||
| 218 | od->pm_lat_level, deact_lat); | ||
| 219 | } else | ||
| 220 | pr_warning("omap_device: %s.%d: deactivate " | ||
| 221 | "latency %d higher than exptected. " | ||
| 222 | "(%llu > %d)\n", | ||
| 223 | od->pdev.name, od->pdev.id, | ||
| 224 | od->pm_lat_level, deact_lat, | ||
| 225 | odpl->deactivate_lat); | ||
| 226 | } | ||
| 227 | |||
| 201 | 228 | ||
| 202 | od->dev_wakeup_lat += odpl->activate_lat; | 229 | od->dev_wakeup_lat += odpl->activate_lat; |
| 203 | 230 | ||
| @@ -280,6 +307,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res) | |||
| 280 | * @pdata_len: amount of memory pointed to by @pdata | 307 | * @pdata_len: amount of memory pointed to by @pdata |
| 281 | * @pm_lats: pointer to a omap_device_pm_latency array for this device | 308 | * @pm_lats: pointer to a omap_device_pm_latency array for this device |
| 282 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats | 309 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats |
| 310 | * @is_early_device: should the device be registered as an early device or not | ||
| 283 | * | 311 | * |
| 284 | * Convenience function for building and registering a single | 312 | * Convenience function for building and registering a single |
| 285 | * omap_device record, which in turn builds and registers a | 313 | * omap_device record, which in turn builds and registers a |
| @@ -291,7 +319,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
| 291 | struct omap_hwmod *oh, void *pdata, | 319 | struct omap_hwmod *oh, void *pdata, |
| 292 | int pdata_len, | 320 | int pdata_len, |
| 293 | struct omap_device_pm_latency *pm_lats, | 321 | struct omap_device_pm_latency *pm_lats, |
| 294 | int pm_lats_cnt) | 322 | int pm_lats_cnt, int is_early_device) |
| 295 | { | 323 | { |
| 296 | struct omap_hwmod *ohs[] = { oh }; | 324 | struct omap_hwmod *ohs[] = { oh }; |
| 297 | 325 | ||
| @@ -299,7 +327,8 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
| 299 | return ERR_PTR(-EINVAL); | 327 | return ERR_PTR(-EINVAL); |
| 300 | 328 | ||
| 301 | return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, | 329 | return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, |
| 302 | pdata_len, pm_lats, pm_lats_cnt); | 330 | pdata_len, pm_lats, pm_lats_cnt, |
| 331 | is_early_device); | ||
| 303 | } | 332 | } |
| 304 | 333 | ||
| 305 | /** | 334 | /** |
| @@ -311,6 +340,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
| 311 | * @pdata_len: amount of memory pointed to by @pdata | 340 | * @pdata_len: amount of memory pointed to by @pdata |
| 312 | * @pm_lats: pointer to a omap_device_pm_latency array for this device | 341 | * @pm_lats: pointer to a omap_device_pm_latency array for this device |
| 313 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats | 342 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats |
| 343 | * @is_early_device: should the device be registered as an early device or not | ||
| 314 | * | 344 | * |
| 315 | * Convenience function for building and registering an omap_device | 345 | * Convenience function for building and registering an omap_device |
| 316 | * subsystem record. Subsystem records consist of multiple | 346 | * subsystem record. Subsystem records consist of multiple |
| @@ -322,7 +352,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
| 322 | struct omap_hwmod **ohs, int oh_cnt, | 352 | struct omap_hwmod **ohs, int oh_cnt, |
| 323 | void *pdata, int pdata_len, | 353 | void *pdata, int pdata_len, |
| 324 | struct omap_device_pm_latency *pm_lats, | 354 | struct omap_device_pm_latency *pm_lats, |
| 325 | int pm_lats_cnt) | 355 | int pm_lats_cnt, int is_early_device) |
| 326 | { | 356 | { |
| 327 | int ret = -ENOMEM; | 357 | int ret = -ENOMEM; |
| 328 | struct omap_device *od; | 358 | struct omap_device *od; |
| @@ -378,7 +408,13 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
| 378 | od->pm_lats = pm_lats; | 408 | od->pm_lats = pm_lats; |
| 379 | od->pm_lats_cnt = pm_lats_cnt; | 409 | od->pm_lats_cnt = pm_lats_cnt; |
| 380 | 410 | ||
| 381 | ret = omap_device_register(od); | 411 | od->magic = OMAP_DEVICE_MAGIC; |
| 412 | |||
| 413 | if (is_early_device) | ||
| 414 | ret = omap_early_device_register(od); | ||
| 415 | else | ||
| 416 | ret = omap_device_register(od); | ||
| 417 | |||
| 382 | if (ret) | 418 | if (ret) |
| 383 | goto odbs_exit4; | 419 | goto odbs_exit4; |
| 384 | 420 | ||
| @@ -399,6 +435,24 @@ odbs_exit1: | |||
| 399 | } | 435 | } |
| 400 | 436 | ||
| 401 | /** | 437 | /** |
| 438 | * omap_early_device_register - register an omap_device as an early platform | ||
| 439 | * device. | ||
| 440 | * @od: struct omap_device * to register | ||
| 441 | * | ||
| 442 | * Register the omap_device structure. This currently just calls | ||
| 443 | * platform_early_add_device() on the underlying platform_device. | ||
| 444 | * Returns 0 by default. | ||
| 445 | */ | ||
| 446 | int omap_early_device_register(struct omap_device *od) | ||
| 447 | { | ||
| 448 | struct platform_device *devices[1]; | ||
| 449 | |||
| 450 | devices[0] = &(od->pdev); | ||
| 451 | early_platform_add_devices(devices, 1); | ||
| 452 | return 0; | ||
| 453 | } | ||
| 454 | |||
| 455 | /** | ||
| 402 | * omap_device_register - register an omap_device with one omap_hwmod | 456 | * omap_device_register - register an omap_device with one omap_hwmod |
| 403 | * @od: struct omap_device * to register | 457 | * @od: struct omap_device * to register |
| 404 | * | 458 | * |
| @@ -437,8 +491,8 @@ int omap_device_enable(struct platform_device *pdev) | |||
| 437 | od = _find_by_pdev(pdev); | 491 | od = _find_by_pdev(pdev); |
| 438 | 492 | ||
| 439 | if (od->_state == OMAP_DEVICE_STATE_ENABLED) { | 493 | if (od->_state == OMAP_DEVICE_STATE_ENABLED) { |
| 440 | WARN(1, "omap_device: %s.%d: omap_device_enable() called from " | 494 | WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", |
| 441 | "invalid state\n", od->pdev.name, od->pdev.id); | 495 | od->pdev.name, od->pdev.id, __func__, od->_state); |
| 442 | return -EINVAL; | 496 | return -EINVAL; |
| 443 | } | 497 | } |
| 444 | 498 | ||
| @@ -476,8 +530,8 @@ int omap_device_idle(struct platform_device *pdev) | |||
| 476 | od = _find_by_pdev(pdev); | 530 | od = _find_by_pdev(pdev); |
| 477 | 531 | ||
| 478 | if (od->_state != OMAP_DEVICE_STATE_ENABLED) { | 532 | if (od->_state != OMAP_DEVICE_STATE_ENABLED) { |
| 479 | WARN(1, "omap_device: %s.%d: omap_device_idle() called from " | 533 | WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", |
| 480 | "invalid state\n", od->pdev.name, od->pdev.id); | 534 | od->pdev.name, od->pdev.id, __func__, od->_state); |
| 481 | return -EINVAL; | 535 | return -EINVAL; |
| 482 | } | 536 | } |
| 483 | 537 | ||
| @@ -509,8 +563,8 @@ int omap_device_shutdown(struct platform_device *pdev) | |||
| 509 | 563 | ||
| 510 | if (od->_state != OMAP_DEVICE_STATE_ENABLED && | 564 | if (od->_state != OMAP_DEVICE_STATE_ENABLED && |
| 511 | od->_state != OMAP_DEVICE_STATE_IDLE) { | 565 | od->_state != OMAP_DEVICE_STATE_IDLE) { |
| 512 | WARN(1, "omap_device: %s.%d: omap_device_shutdown() called " | 566 | WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", |
| 513 | "from invalid state\n", od->pdev.name, od->pdev.id); | 567 | od->pdev.name, od->pdev.id, __func__, od->_state); |
| 514 | return -EINVAL; | 568 | return -EINVAL; |
| 515 | } | 569 | } |
| 516 | 570 | ||
| @@ -564,6 +618,18 @@ int omap_device_align_pm_lat(struct platform_device *pdev, | |||
| 564 | } | 618 | } |
| 565 | 619 | ||
| 566 | /** | 620 | /** |
| 621 | * omap_device_is_valid - Check if pointer is a valid omap_device | ||
| 622 | * @od: struct omap_device * | ||
| 623 | * | ||
| 624 | * Return whether struct omap_device pointer @od points to a valid | ||
| 625 | * omap_device. | ||
| 626 | */ | ||
| 627 | bool omap_device_is_valid(struct omap_device *od) | ||
| 628 | { | ||
| 629 | return (od && od->magic == OMAP_DEVICE_MAGIC); | ||
| 630 | } | ||
| 631 | |||
| 632 | /** | ||
| 567 | * omap_device_get_pwrdm - return the powerdomain * associated with @od | 633 | * omap_device_get_pwrdm - return the powerdomain * associated with @od |
| 568 | * @od: struct omap_device * | 634 | * @od: struct omap_device * |
| 569 | * | 635 | * |
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index d8d5094b37ed..51f4dfb82e2b 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
| @@ -53,7 +53,7 @@ | |||
| 53 | #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) | 53 | #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) |
| 54 | #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) | 54 | #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) |
| 55 | 55 | ||
| 56 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 56 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 57 | #define SRAM_BOOTLOADER_SZ 0x00 | 57 | #define SRAM_BOOTLOADER_SZ 0x00 |
| 58 | #else | 58 | #else |
| 59 | #define SRAM_BOOTLOADER_SZ 0x80 | 59 | #define SRAM_BOOTLOADER_SZ 0x80 |