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author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-05-07 16:58:56 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-05-07 16:58:56 -0400 |
commit | 417a9ef1f488e3cf92bacc4999e1cbabc0e7cf1a (patch) | |
tree | f9ea61b81f7de18687466d5a9d510ad9b563b79e /arch | |
parent | 91bc482ec5a615e8ecebc106aaf7d0c267d511de (diff) | |
parent | a47f6be45670465d45a3d27f7ff71986bd35d6c4 (diff) |
Merge branch 'v4l_for_2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6
* 'v4l_for_2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6:
V4L/DVB: pxa_camera: move fifo reset direct before dma start
V4L/DVB: video: testing unsigned for less than 0
V4L/DVB: mx1-camera: compile fix
V4L/DVB: budget: Oops: "BUG: unable to handle kernel NULL pointer dereference"
V4L/DVB: ngene: Workaround for stuck DiSEqC pin
V4L/DVB: saa7146: fix regression of the av7110/budget-av driver
V4L/DVB: v4l: fix config dependencies: mxb and saa7191 are V4L2 drivers, not V4L1
V4L/DVB: feature-removal: announce videotext.h removal
V4L/DVB: V4L - vpfe capture - fix for kernel crash
V4L/DVB: gspca: make usb id 0461:0815 get handled by the right driver
V4L/DVB: gspca - stv06xx: Remove the 046d:08da from the stv06xx driver
V4L/DVB: gspca - sn9c20x: Correct onstack wait_queue_head declaration
V4L/DVB: saa7146: fix up bytesperline if it is an impossible value
V4L/DVB: V4L: vpfe_capture - free ccdc_lock when memory allocation fails
V4L/DVB: V4L - Makfile:Removed duplicate entry of davinci
V4L/DVB: omap24xxcam: potential buffer overflow
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index 07be8ad7ec37..7c4870bd5a21 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | |||
@@ -31,7 +31,13 @@ | |||
31 | #define DMA_MODE_WRITE 1 | 31 | #define DMA_MODE_WRITE 1 |
32 | #define DMA_MODE_MASK 1 | 32 | #define DMA_MODE_MASK 1 |
33 | 33 | ||
34 | #define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) | 34 | #define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset)) |
35 | |||
36 | /* DMA Interrupt Mask Register */ | ||
37 | #define MX1_DMA_DIMR MX1_DMA_REG(0x08) | ||
38 | |||
39 | /* Channel Control Register */ | ||
40 | #define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6)) | ||
35 | 41 | ||
36 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | 42 | #define IMX_DMA_MEMSIZE_32 (0 << 4) |
37 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | 43 | #define IMX_DMA_MEMSIZE_8 (1 << 4) |