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authorKumar Gala <galak@kernel.crashing.org>2007-09-12 19:23:46 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-09-14 09:53:22 -0400
commit1b3c5cdab49a605f0e048e1ccbf4cc61a2626485 (patch)
treeb81e6642588b00a7dbb42611614e745517b6a6b9 /arch
parentf0c8ac8083cbd9347b398bfddcca20f1e2786016 (diff)
[POWERPC] Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts42
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts52
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts60
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts118
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts66
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts95
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts44
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts240
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts119
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts172
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts190
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts372
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts399
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts190
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts180
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts269
16 files changed, 1323 insertions, 1285 deletions
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index d8bcbb870fdc..324e1bd2aa60 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -182,27 +182,6 @@
182 interrupt-parent = <&mpc5200_pic>; 182 interrupt-parent = <&mpc5200_pic>;
183 }; 183 };
184 184
185 pci@0d00 {
186 #interrupt-cells = <1>;
187 #size-cells = <2>;
188 #address-cells = <3>;
189 device_type = "pci";
190 compatible = "mpc5200-pci";
191 reg = <d00 100>;
192 interrupt-map-mask = <f800 0 0 7>;
193 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
194 c000 0 0 2 &mpc5200_pic 0 0 3
195 c000 0 0 3 &mpc5200_pic 0 0 3
196 c000 0 0 4 &mpc5200_pic 0 0 3>;
197 clock-frequency = <0>; // From boot loader
198 interrupts = <2 8 0 2 9 0 2 a 0>;
199 interrupt-parent = <&mpc5200_pic>;
200 bus-range = <0 0>;
201 ranges = <42000000 0 80000000 80000000 0 20000000
202 02000000 0 a0000000 a0000000 0 10000000
203 01000000 0 00000000 b0000000 0 01000000>;
204 };
205
206 spi@f00 { 185 spi@f00 {
207 device_type = "spi"; 186 device_type = "spi";
208 compatible = "mpc5200-spi"; 187 compatible = "mpc5200-spi";
@@ -337,4 +316,25 @@
337 reg = <8000 4000>; 316 reg = <8000 4000>;
338 }; 317 };
339 }; 318 };
319
320 pci@f0000d00 {
321 #interrupt-cells = <1>;
322 #size-cells = <2>;
323 #address-cells = <3>;
324 device_type = "pci";
325 compatible = "mpc5200-pci";
326 reg = <f0000d00 100>;
327 interrupt-map-mask = <f800 0 0 7>;
328 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
329 c000 0 0 2 &mpc5200_pic 0 0 3
330 c000 0 0 3 &mpc5200_pic 0 0 3
331 c000 0 0 4 &mpc5200_pic 0 0 3>;
332 clock-frequency = <0>; // From boot loader
333 interrupts = <2 8 0 2 9 0 2 a 0>;
334 interrupt-parent = <&mpc5200_pic>;
335 bus-range = <0 0>;
336 ranges = <42000000 0 80000000 80000000 0 20000000
337 02000000 0 a0000000 a0000000 0 10000000
338 01000000 0 00000000 b0000000 0 01000000>;
339 };
340}; 340};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 5fe8998abb7c..3f74f73f70ad 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -182,32 +182,6 @@
182 interrupt-parent = <&mpc5200_pic>; 182 interrupt-parent = <&mpc5200_pic>;
183 }; 183 };
184 184
185 pci@0d00 {
186 #interrupt-cells = <1>;
187 #size-cells = <2>;
188 #address-cells = <3>;
189 device_type = "pci";
190 compatible = "mpc5200b-pci\0mpc5200-pci";
191 reg = <d00 100>;
192 interrupt-map-mask = <f800 0 0 7>;
193 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
194 c000 0 0 2 &mpc5200_pic 1 1 3
195 c000 0 0 3 &mpc5200_pic 1 2 3
196 c000 0 0 4 &mpc5200_pic 1 3 3
197
198 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
199 c800 0 0 2 &mpc5200_pic 1 2 3
200 c800 0 0 3 &mpc5200_pic 1 3 3
201 c800 0 0 4 &mpc5200_pic 0 0 3>;
202 clock-frequency = <0>; // From boot loader
203 interrupts = <2 8 0 2 9 0 2 a 0>;
204 interrupt-parent = <&mpc5200_pic>;
205 bus-range = <0 0>;
206 ranges = <42000000 0 80000000 80000000 0 20000000
207 02000000 0 a0000000 a0000000 0 10000000
208 01000000 0 00000000 b0000000 0 01000000>;
209 };
210
211 spi@f00 { 185 spi@f00 {
212 device_type = "spi"; 186 device_type = "spi";
213 compatible = "mpc5200b-spi\0mpc5200-spi"; 187 compatible = "mpc5200b-spi\0mpc5200-spi";
@@ -342,4 +316,30 @@
342 reg = <8000 4000>; 316 reg = <8000 4000>;
343 }; 317 };
344 }; 318 };
319
320 pci@f0000d00 {
321 #interrupt-cells = <1>;
322 #size-cells = <2>;
323 #address-cells = <3>;
324 device_type = "pci";
325 compatible = "mpc5200b-pci\0mpc5200-pci";
326 reg = <f0000d00 100>;
327 interrupt-map-mask = <f800 0 0 7>;
328 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
329 c000 0 0 2 &mpc5200_pic 1 1 3
330 c000 0 0 3 &mpc5200_pic 1 2 3
331 c000 0 0 4 &mpc5200_pic 1 3 3
332
333 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
334 c800 0 0 2 &mpc5200_pic 1 2 3
335 c800 0 0 3 &mpc5200_pic 1 3 3
336 c800 0 0 4 &mpc5200_pic 0 0 3>;
337 clock-frequency = <0>; // From boot loader
338 interrupts = <2 8 0 2 9 0 2 a 0>;
339 interrupt-parent = <&mpc5200_pic>;
340 bus-range = <0 0>;
341 ranges = <42000000 0 80000000 80000000 0 20000000
342 02000000 0 a0000000 a0000000 0 10000000
343 01000000 0 00000000 b0000000 0 01000000>;
344 };
345}; 345};
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index abd73a2c5e0c..a8eadc8c4497 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -150,36 +150,6 @@
150 interrupt-parent = < &ipic >; 150 interrupt-parent = < &ipic >;
151 }; 151 };
152 152
153 pci@8500 {
154 interrupt-map-mask = <f800 0 0 7>;
155 interrupt-map = <
156
157 /* IDSEL 0x0E -mini PCI */
158 7000 0 0 1 &ipic 12 8
159 7000 0 0 2 &ipic 12 8
160 7000 0 0 3 &ipic 12 8
161 7000 0 0 4 &ipic 12 8
162
163 /* IDSEL 0x0F - PCI slot */
164 7800 0 0 1 &ipic 11 8
165 7800 0 0 2 &ipic 12 8
166 7800 0 0 3 &ipic 11 8
167 7800 0 0 4 &ipic 12 8>;
168 interrupt-parent = < &ipic >;
169 interrupts = <42 8>;
170 bus-range = <0 0>;
171 ranges = <02000000 0 90000000 90000000 0 10000000
172 42000000 0 80000000 80000000 0 10000000
173 01000000 0 00000000 e2000000 0 00100000>;
174 clock-frequency = <3f940aa>;
175 #interrupt-cells = <1>;
176 #size-cells = <2>;
177 #address-cells = <3>;
178 reg = <8500 100>;
179 compatible = "fsl,mpc8349-pci";
180 device_type = "pci";
181 };
182
183 crypto@30000 { 153 crypto@30000 {
184 device_type = "crypto"; 154 device_type = "crypto";
185 model = "SEC2"; 155 model = "SEC2";
@@ -208,4 +178,34 @@
208 device_type = "ipic"; 178 device_type = "ipic";
209 }; 179 };
210 }; 180 };
181
182 pci@e0008500 {
183 interrupt-map-mask = <f800 0 0 7>;
184 interrupt-map = <
185
186 /* IDSEL 0x0E -mini PCI */
187 7000 0 0 1 &ipic 12 8
188 7000 0 0 2 &ipic 12 8
189 7000 0 0 3 &ipic 12 8
190 7000 0 0 4 &ipic 12 8
191
192 /* IDSEL 0x0F - PCI slot */
193 7800 0 0 1 &ipic 11 8
194 7800 0 0 2 &ipic 12 8
195 7800 0 0 3 &ipic 11 8
196 7800 0 0 4 &ipic 12 8>;
197 interrupt-parent = < &ipic >;
198 interrupts = <42 8>;
199 bus-range = <0 0>;
200 ranges = <02000000 0 90000000 90000000 0 10000000
201 42000000 0 80000000 80000000 0 10000000
202 01000000 0 00000000 e2000000 0 00100000>;
203 clock-frequency = <3f940aa>;
204 #interrupt-cells = <1>;
205 #size-cells = <2>;
206 #address-cells = <3>;
207 reg = <e0008500 100>;
208 compatible = "fsl,mpc8349-pci";
209 device_type = "pci";
210 };
211}; 211};
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index e88167dc1859..fcd333c391ec 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -97,65 +97,6 @@
97 descriptor-types-mask = <0122003f>; 97 descriptor-types-mask = <0122003f>;
98 }; 98 };
99 99
100 pci@8500 {
101 interrupt-map-mask = <f800 0 0 7>;
102 interrupt-map = <
103 /* IDSEL 0x11 AD17 */
104 8800 0 0 1 &ipic 14 8
105 8800 0 0 2 &ipic 15 8
106 8800 0 0 3 &ipic 16 8
107 8800 0 0 4 &ipic 17 8
108
109 /* IDSEL 0x12 AD18 */
110 9000 0 0 1 &ipic 16 8
111 9000 0 0 2 &ipic 17 8
112 9000 0 0 3 &ipic 14 8
113 9000 0 0 4 &ipic 15 8
114
115 /* IDSEL 0x13 AD19 */
116 9800 0 0 1 &ipic 17 8
117 9800 0 0 2 &ipic 14 8
118 9800 0 0 3 &ipic 15 8
119 9800 0 0 4 &ipic 16 8
120
121 /* IDSEL 0x15 AD21*/
122 a800 0 0 1 &ipic 14 8
123 a800 0 0 2 &ipic 15 8
124 a800 0 0 3 &ipic 16 8
125 a800 0 0 4 &ipic 17 8
126
127 /* IDSEL 0x16 AD22*/
128 b000 0 0 1 &ipic 17 8
129 b000 0 0 2 &ipic 14 8
130 b000 0 0 3 &ipic 15 8
131 b000 0 0 4 &ipic 16 8
132
133 /* IDSEL 0x17 AD23*/
134 b800 0 0 1 &ipic 16 8
135 b800 0 0 2 &ipic 17 8
136 b800 0 0 3 &ipic 14 8
137 b800 0 0 4 &ipic 15 8
138
139 /* IDSEL 0x18 AD24*/
140 c000 0 0 1 &ipic 15 8
141 c000 0 0 2 &ipic 16 8
142 c000 0 0 3 &ipic 17 8
143 c000 0 0 4 &ipic 14 8>;
144 interrupt-parent = < &ipic >;
145 interrupts = <42 8>;
146 bus-range = <0 0>;
147 ranges = <02000000 0 90000000 90000000 0 10000000
148 42000000 0 80000000 80000000 0 10000000
149 01000000 0 00000000 d0000000 0 00100000>;
150 clock-frequency = <0>;
151 #interrupt-cells = <1>;
152 #size-cells = <2>;
153 #address-cells = <3>;
154 reg = <8500 100>;
155 compatible = "fsl,mpc8349-pci";
156 device_type = "pci";
157 };
158
159 ipic: pic@700 { 100 ipic: pic@700 {
160 interrupt-controller; 101 interrupt-controller;
161 #address-cells = <0>; 102 #address-cells = <0>;
@@ -335,4 +276,63 @@
335 interrupt-parent = < &ipic >; 276 interrupt-parent = < &ipic >;
336 }; 277 };
337 }; 278 };
279
280 pci@e0008500 {
281 interrupt-map-mask = <f800 0 0 7>;
282 interrupt-map = <
283 /* IDSEL 0x11 AD17 */
284 8800 0 0 1 &ipic 14 8
285 8800 0 0 2 &ipic 15 8
286 8800 0 0 3 &ipic 16 8
287 8800 0 0 4 &ipic 17 8
288
289 /* IDSEL 0x12 AD18 */
290 9000 0 0 1 &ipic 16 8
291 9000 0 0 2 &ipic 17 8
292 9000 0 0 3 &ipic 14 8
293 9000 0 0 4 &ipic 15 8
294
295 /* IDSEL 0x13 AD19 */
296 9800 0 0 1 &ipic 17 8
297 9800 0 0 2 &ipic 14 8
298 9800 0 0 3 &ipic 15 8
299 9800 0 0 4 &ipic 16 8
300
301 /* IDSEL 0x15 AD21*/
302 a800 0 0 1 &ipic 14 8
303 a800 0 0 2 &ipic 15 8
304 a800 0 0 3 &ipic 16 8
305 a800 0 0 4 &ipic 17 8
306
307 /* IDSEL 0x16 AD22*/
308 b000 0 0 1 &ipic 17 8
309 b000 0 0 2 &ipic 14 8
310 b000 0 0 3 &ipic 15 8
311 b000 0 0 4 &ipic 16 8
312
313 /* IDSEL 0x17 AD23*/
314 b800 0 0 1 &ipic 16 8
315 b800 0 0 2 &ipic 17 8
316 b800 0 0 3 &ipic 14 8
317 b800 0 0 4 &ipic 15 8
318
319 /* IDSEL 0x18 AD24*/
320 c000 0 0 1 &ipic 15 8
321 c000 0 0 2 &ipic 16 8
322 c000 0 0 3 &ipic 17 8
323 c000 0 0 4 &ipic 14 8>;
324 interrupt-parent = < &ipic >;
325 interrupts = <42 8>;
326 bus-range = <0 0>;
327 ranges = <02000000 0 90000000 90000000 0 10000000
328 42000000 0 80000000 80000000 0 10000000
329 01000000 0 00000000 d0000000 0 00100000>;
330 clock-frequency = <0>;
331 #interrupt-cells = <1>;
332 #size-cells = <2>;
333 #address-cells = <3>;
334 reg = <e0008500 100>;
335 compatible = "fsl,mpc8349-pci";
336 device_type = "pci";
337 };
338}; 338};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 01393e6d7da9..cdc4a94e9c28 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -92,39 +92,6 @@
92 descriptor-types-mask = <0122003f>; 92 descriptor-types-mask = <0122003f>;
93 }; 93 };
94 94
95 pci@8500 {
96 interrupt-map-mask = <f800 0 0 7>;
97 interrupt-map = <
98 /* IDSEL 0x10 AD16 (USB) */
99 8000 0 0 1 &pic 11 8
100
101 /* IDSEL 0x11 AD17 (Mini1)*/
102 8800 0 0 1 &pic 12 8
103 8800 0 0 2 &pic 13 8
104 8800 0 0 3 &pic 14 8
105 8800 0 0 4 &pic 30 8
106
107 /* IDSEL 0x12 AD18 (PCI/Mini2) */
108 9000 0 0 1 &pic 13 8
109 9000 0 0 2 &pic 14 8
110 9000 0 0 3 &pic 30 8
111 9000 0 0 4 &pic 11 8>;
112
113 interrupt-parent = <&pic>;
114 interrupts = <42 8>;
115 bus-range = <0 0>;
116 ranges = <42000000 0 80000000 80000000 0 10000000
117 02000000 0 90000000 90000000 0 10000000
118 01000000 0 d0000000 d0000000 0 04000000>;
119 clock-frequency = <0>;
120 #interrupt-cells = <1>;
121 #size-cells = <2>;
122 #address-cells = <3>;
123 reg = <8500 100>;
124 compatible = "fsl,mpc8349-pci";
125 device_type = "pci";
126 };
127
128 pic:pic@700 { 95 pic:pic@700 {
129 interrupt-controller; 96 interrupt-controller;
130 #address-cells = <0>; 97 #address-cells = <0>;
@@ -294,4 +261,37 @@
294 interrupt-parent = <&pic>; 261 interrupt-parent = <&pic>;
295 }; 262 };
296 }; 263 };
264
265 pci@e0008500 {
266 interrupt-map-mask = <f800 0 0 7>;
267 interrupt-map = <
268 /* IDSEL 0x10 AD16 (USB) */
269 8000 0 0 1 &pic 11 8
270
271 /* IDSEL 0x11 AD17 (Mini1)*/
272 8800 0 0 1 &pic 12 8
273 8800 0 0 2 &pic 13 8
274 8800 0 0 3 &pic 14 8
275 8800 0 0 4 &pic 30 8
276
277 /* IDSEL 0x12 AD18 (PCI/Mini2) */
278 9000 0 0 1 &pic 13 8
279 9000 0 0 2 &pic 14 8
280 9000 0 0 3 &pic 30 8
281 9000 0 0 4 &pic 11 8>;
282
283 interrupt-parent = <&pic>;
284 interrupts = <42 8>;
285 bus-range = <0 0>;
286 ranges = <42000000 0 80000000 80000000 0 10000000
287 02000000 0 90000000 90000000 0 10000000
288 01000000 0 d0000000 d0000000 0 04000000>;
289 clock-frequency = <0>;
290 #interrupt-cells = <1>;
291 #size-cells = <2>;
292 #address-cells = <3>;
293 reg = <e0008500 100>;
294 compatible = "fsl,mpc8349-pci";
295 device_type = "pci";
296 };
297}; 297};
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index f98c785081bf..67781601b6b3 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -178,52 +178,6 @@
178 interrupt-parent = < &ipic >; 178 interrupt-parent = < &ipic >;
179 }; 179 };
180 180
181 pci@8500 {
182 interrupt-map-mask = <f800 0 0 7>;
183 interrupt-map = <
184 /* IDSEL 0x10 - SATA */
185 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
186 >;
187 interrupt-parent = < &ipic >;
188 interrupts = <42 8>;
189 bus-range = <0 0>;
190 ranges = <42000000 0 80000000 80000000 0 10000000
191 02000000 0 90000000 90000000 0 10000000
192 01000000 0 00000000 e2000000 0 01000000>;
193 clock-frequency = <3f940aa>;
194 #interrupt-cells = <1>;
195 #size-cells = <2>;
196 #address-cells = <3>;
197 reg = <8500 100>;
198 compatible = "fsl,mpc8349-pci";
199 device_type = "pci";
200 };
201
202 pci@8600 {
203 interrupt-map-mask = <f800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x0E - MiniPCI Slot */
206 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
207
208 /* IDSEL 0x0F - PCI Slot */
209 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
210 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
211 >;
212 interrupt-parent = < &ipic >;
213 interrupts = <43 8>;
214 bus-range = <1 1>;
215 ranges = <42000000 0 a0000000 a0000000 0 10000000
216 02000000 0 b0000000 b0000000 0 10000000
217 01000000 0 00000000 e3000000 0 01000000>;
218 clock-frequency = <3f940aa>;
219 #interrupt-cells = <1>;
220 #size-cells = <2>;
221 #address-cells = <3>;
222 reg = <8600 100>;
223 compatible = "fsl,mpc8349-pci";
224 device_type = "pci";
225 };
226
227 crypto@30000 { 181 crypto@30000 {
228 device_type = "crypto"; 182 device_type = "crypto";
229 model = "SEC2"; 183 model = "SEC2";
@@ -245,4 +199,53 @@
245 device_type = "ipic"; 199 device_type = "ipic";
246 }; 200 };
247 }; 201 };
202
203 pci@e0008500 {
204 interrupt-map-mask = <f800 0 0 7>;
205 interrupt-map = <
206 /* IDSEL 0x10 - SATA */
207 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
208 >;
209 interrupt-parent = < &ipic >;
210 interrupts = <42 8>;
211 bus-range = <0 0>;
212 ranges = <42000000 0 80000000 80000000 0 10000000
213 02000000 0 90000000 90000000 0 10000000
214 01000000 0 00000000 e2000000 0 01000000>;
215 clock-frequency = <3f940aa>;
216 #interrupt-cells = <1>;
217 #size-cells = <2>;
218 #address-cells = <3>;
219 reg = <e0008500 100>;
220 compatible = "fsl,mpc8349-pci";
221 device_type = "pci";
222 };
223
224 pci@e0008600 {
225 interrupt-map-mask = <f800 0 0 7>;
226 interrupt-map = <
227 /* IDSEL 0x0E - MiniPCI Slot */
228 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
229
230 /* IDSEL 0x0F - PCI Slot */
231 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
232 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
233 >;
234 interrupt-parent = < &ipic >;
235 interrupts = <43 8>;
236 bus-range = <0 0>;
237 ranges = <42000000 0 a0000000 a0000000 0 10000000
238 02000000 0 b0000000 b0000000 0 10000000
239 01000000 0 00000000 e3000000 0 01000000>;
240 clock-frequency = <3f940aa>;
241 #interrupt-cells = <1>;
242 #size-cells = <2>;
243 #address-cells = <3>;
244 reg = <e0008600 100>;
245 compatible = "fsl,mpc8349-pci";
246 device_type = "pci";
247 };
248
249
250
248}; 251};
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 7c89ff7f6a37..fa852ba1b6ba 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -134,28 +134,6 @@
134 interrupt-parent = < &ipic >; 134 interrupt-parent = < &ipic >;
135 }; 135 };
136 136
137 pci@8600 {
138 interrupt-map-mask = <f800 0 0 7>;
139 interrupt-map = <
140 /* IDSEL 0x0F - PCI Slot */
141 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
142 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
143 >;
144 interrupt-parent = < &ipic >;
145 interrupts = <43 8>;
146 bus-range = <1 1>;
147 ranges = <42000000 0 a0000000 a0000000 0 10000000
148 02000000 0 b0000000 b0000000 0 10000000
149 01000000 0 00000000 e3000000 0 01000000>;
150 clock-frequency = <3f940aa>;
151 #interrupt-cells = <1>;
152 #size-cells = <2>;
153 #address-cells = <3>;
154 reg = <8600 100>;
155 compatible = "fsl,mpc8349-pci";
156 device_type = "pci";
157 };
158
159 crypto@30000 { 137 crypto@30000 {
160 device_type = "crypto"; 138 device_type = "crypto";
161 model = "SEC2"; 139 model = "SEC2";
@@ -177,4 +155,26 @@
177 device_type = "ipic"; 155 device_type = "ipic";
178 }; 156 };
179 }; 157 };
158
159 pci@e0008600 {
160 interrupt-map-mask = <f800 0 0 7>;
161 interrupt-map = <
162 /* IDSEL 0x0F - PCI Slot */
163 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
164 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
165 >;
166 interrupt-parent = < &ipic >;
167 interrupts = <43 8>;
168 bus-range = <1 1>;
169 ranges = <42000000 0 a0000000 a0000000 0 10000000
170 02000000 0 b0000000 b0000000 0 10000000
171 01000000 0 00000000 e3000000 0 01000000>;
172 clock-frequency = <3f940aa>;
173 #interrupt-cells = <1>;
174 #size-cells = <2>;
175 #address-cells = <3>;
176 reg = <e0008600 100>;
177 compatible = "fsl,mpc8349-pci";
178 device_type = "pci";
179 };
180}; 180};
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index f4ba85775409..1b8882e20040 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -183,126 +183,6 @@
183 interrupt-parent = < &ipic >; 183 interrupt-parent = < &ipic >;
184 }; 184 };
185 185
186 pci@8500 {
187 interrupt-map-mask = <f800 0 0 7>;
188 interrupt-map = <
189
190 /* IDSEL 0x11 */
191 8800 0 0 1 &ipic 14 8
192 8800 0 0 2 &ipic 15 8
193 8800 0 0 3 &ipic 16 8
194 8800 0 0 4 &ipic 17 8
195
196 /* IDSEL 0x12 */
197 9000 0 0 1 &ipic 16 8
198 9000 0 0 2 &ipic 17 8
199 9000 0 0 3 &ipic 14 8
200 9000 0 0 4 &ipic 15 8
201
202 /* IDSEL 0x13 */
203 9800 0 0 1 &ipic 17 8
204 9800 0 0 2 &ipic 14 8
205 9800 0 0 3 &ipic 15 8
206 9800 0 0 4 &ipic 16 8
207
208 /* IDSEL 0x15 */
209 a800 0 0 1 &ipic 14 8
210 a800 0 0 2 &ipic 15 8
211 a800 0 0 3 &ipic 16 8
212 a800 0 0 4 &ipic 17 8
213
214 /* IDSEL 0x16 */
215 b000 0 0 1 &ipic 17 8
216 b000 0 0 2 &ipic 14 8
217 b000 0 0 3 &ipic 15 8
218 b000 0 0 4 &ipic 16 8
219
220 /* IDSEL 0x17 */
221 b800 0 0 1 &ipic 16 8
222 b800 0 0 2 &ipic 17 8
223 b800 0 0 3 &ipic 14 8
224 b800 0 0 4 &ipic 15 8
225
226 /* IDSEL 0x18 */
227 c000 0 0 1 &ipic 15 8
228 c000 0 0 2 &ipic 16 8
229 c000 0 0 3 &ipic 17 8
230 c000 0 0 4 &ipic 14 8>;
231 interrupt-parent = < &ipic >;
232 interrupts = <42 8>;
233 bus-range = <0 0>;
234 ranges = <02000000 0 90000000 90000000 0 10000000
235 42000000 0 80000000 80000000 0 10000000
236 01000000 0 00000000 e2000000 0 00100000>;
237 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>;
239 #size-cells = <2>;
240 #address-cells = <3>;
241 reg = <8500 100>;
242 compatible = "fsl,mpc8349-pci";
243 device_type = "pci";
244 };
245
246 pci@8600 {
247 interrupt-map-mask = <f800 0 0 7>;
248 interrupt-map = <
249
250 /* IDSEL 0x11 */
251 8800 0 0 1 &ipic 14 8
252 8800 0 0 2 &ipic 15 8
253 8800 0 0 3 &ipic 16 8
254 8800 0 0 4 &ipic 17 8
255
256 /* IDSEL 0x12 */
257 9000 0 0 1 &ipic 16 8
258 9000 0 0 2 &ipic 17 8
259 9000 0 0 3 &ipic 14 8
260 9000 0 0 4 &ipic 15 8
261
262 /* IDSEL 0x13 */
263 9800 0 0 1 &ipic 17 8
264 9800 0 0 2 &ipic 14 8
265 9800 0 0 3 &ipic 15 8
266 9800 0 0 4 &ipic 16 8
267
268 /* IDSEL 0x15 */
269 a800 0 0 1 &ipic 14 8
270 a800 0 0 2 &ipic 15 8
271 a800 0 0 3 &ipic 16 8
272 a800 0 0 4 &ipic 17 8
273
274 /* IDSEL 0x16 */
275 b000 0 0 1 &ipic 17 8
276 b000 0 0 2 &ipic 14 8
277 b000 0 0 3 &ipic 15 8
278 b000 0 0 4 &ipic 16 8
279
280 /* IDSEL 0x17 */
281 b800 0 0 1 &ipic 16 8
282 b800 0 0 2 &ipic 17 8
283 b800 0 0 3 &ipic 14 8
284 b800 0 0 4 &ipic 15 8
285
286 /* IDSEL 0x18 */
287 c000 0 0 1 &ipic 15 8
288 c000 0 0 2 &ipic 16 8
289 c000 0 0 3 &ipic 17 8
290 c000 0 0 4 &ipic 14 8>;
291 interrupt-parent = < &ipic >;
292 interrupts = <42 8>;
293 bus-range = <0 0>;
294 ranges = <02000000 0 b0000000 b0000000 0 10000000
295 42000000 0 a0000000 a0000000 0 10000000
296 01000000 0 00000000 e2100000 0 00100000>;
297 clock-frequency = <3f940aa>;
298 #interrupt-cells = <1>;
299 #size-cells = <2>;
300 #address-cells = <3>;
301 reg = <8600 100>;
302 compatible = "fsl,mpc8349-pci";
303 device_type = "pci";
304 };
305
306 /* May need to remove if on a part without crypto engine */ 186 /* May need to remove if on a part without crypto engine */
307 crypto@30000 { 187 crypto@30000 {
308 device_type = "crypto"; 188 device_type = "crypto";
@@ -333,4 +213,124 @@
333 device_type = "ipic"; 213 device_type = "ipic";
334 }; 214 };
335 }; 215 };
216
217 pci@e0008500 {
218 interrupt-map-mask = <f800 0 0 7>;
219 interrupt-map = <
220
221 /* IDSEL 0x11 */
222 8800 0 0 1 &ipic 14 8
223 8800 0 0 2 &ipic 15 8
224 8800 0 0 3 &ipic 16 8
225 8800 0 0 4 &ipic 17 8
226
227 /* IDSEL 0x12 */
228 9000 0 0 1 &ipic 16 8
229 9000 0 0 2 &ipic 17 8
230 9000 0 0 3 &ipic 14 8
231 9000 0 0 4 &ipic 15 8
232
233 /* IDSEL 0x13 */
234 9800 0 0 1 &ipic 17 8
235 9800 0 0 2 &ipic 14 8
236 9800 0 0 3 &ipic 15 8
237 9800 0 0 4 &ipic 16 8
238
239 /* IDSEL 0x15 */
240 a800 0 0 1 &ipic 14 8
241 a800 0 0 2 &ipic 15 8
242 a800 0 0 3 &ipic 16 8
243 a800 0 0 4 &ipic 17 8
244
245 /* IDSEL 0x16 */
246 b000 0 0 1 &ipic 17 8
247 b000 0 0 2 &ipic 14 8
248 b000 0 0 3 &ipic 15 8
249 b000 0 0 4 &ipic 16 8
250
251 /* IDSEL 0x17 */
252 b800 0 0 1 &ipic 16 8
253 b800 0 0 2 &ipic 17 8
254 b800 0 0 3 &ipic 14 8
255 b800 0 0 4 &ipic 15 8
256
257 /* IDSEL 0x18 */
258 c000 0 0 1 &ipic 15 8
259 c000 0 0 2 &ipic 16 8
260 c000 0 0 3 &ipic 17 8
261 c000 0 0 4 &ipic 14 8>;
262 interrupt-parent = < &ipic >;
263 interrupts = <42 8>;
264 bus-range = <0 0>;
265 ranges = <02000000 0 90000000 90000000 0 10000000
266 42000000 0 80000000 80000000 0 10000000
267 01000000 0 00000000 e2000000 0 00100000>;
268 clock-frequency = <3f940aa>;
269 #interrupt-cells = <1>;
270 #size-cells = <2>;
271 #address-cells = <3>;
272 reg = <e0008500 100>;
273 compatible = "fsl,mpc8349-pci";
274 device_type = "pci";
275 };
276
277 pci@e0008600 {
278 interrupt-map-mask = <f800 0 0 7>;
279 interrupt-map = <
280
281 /* IDSEL 0x11 */
282 8800 0 0 1 &ipic 14 8
283 8800 0 0 2 &ipic 15 8
284 8800 0 0 3 &ipic 16 8
285 8800 0 0 4 &ipic 17 8
286
287 /* IDSEL 0x12 */
288 9000 0 0 1 &ipic 16 8
289 9000 0 0 2 &ipic 17 8
290 9000 0 0 3 &ipic 14 8
291 9000 0 0 4 &ipic 15 8
292
293 /* IDSEL 0x13 */
294 9800 0 0 1 &ipic 17 8
295 9800 0 0 2 &ipic 14 8
296 9800 0 0 3 &ipic 15 8
297 9800 0 0 4 &ipic 16 8
298
299 /* IDSEL 0x15 */
300 a800 0 0 1 &ipic 14 8
301 a800 0 0 2 &ipic 15 8
302 a800 0 0 3 &ipic 16 8
303 a800 0 0 4 &ipic 17 8
304
305 /* IDSEL 0x16 */
306 b000 0 0 1 &ipic 17 8
307 b000 0 0 2 &ipic 14 8
308 b000 0 0 3 &ipic 15 8
309 b000 0 0 4 &ipic 16 8
310
311 /* IDSEL 0x17 */
312 b800 0 0 1 &ipic 16 8
313 b800 0 0 2 &ipic 17 8
314 b800 0 0 3 &ipic 14 8
315 b800 0 0 4 &ipic 15 8
316
317 /* IDSEL 0x18 */
318 c000 0 0 1 &ipic 15 8
319 c000 0 0 2 &ipic 16 8
320 c000 0 0 3 &ipic 17 8
321 c000 0 0 4 &ipic 14 8>;
322 interrupt-parent = < &ipic >;
323 interrupts = <42 8>;
324 bus-range = <0 0>;
325 ranges = <02000000 0 b0000000 b0000000 0 10000000
326 42000000 0 a0000000 a0000000 0 10000000
327 01000000 0 00000000 e2100000 0 00100000>;
328 clock-frequency = <3f940aa>;
329 #interrupt-cells = <1>;
330 #size-cells = <2>;
331 #address-cells = <3>;
332 reg = <e0008600 100>;
333 compatible = "fsl,mpc8349-pci";
334 device_type = "pci";
335 };
336}; 336};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index f14e88ee0f1c..fbd1573c348b 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -111,66 +111,6 @@
111 descriptor-types-mask = <01010ebf>; 111 descriptor-types-mask = <01010ebf>;
112 }; 112 };
113 113
114 pci@8500 {
115 interrupt-map-mask = <f800 0 0 7>;
116 interrupt-map = <
117
118 /* IDSEL 0x11 AD17 */
119 8800 0 0 1 &ipic 14 8
120 8800 0 0 2 &ipic 15 8
121 8800 0 0 3 &ipic 16 8
122 8800 0 0 4 &ipic 17 8
123
124 /* IDSEL 0x12 AD18 */
125 9000 0 0 1 &ipic 16 8
126 9000 0 0 2 &ipic 17 8
127 9000 0 0 3 &ipic 14 8
128 9000 0 0 4 &ipic 15 8
129
130 /* IDSEL 0x13 AD19 */
131 9800 0 0 1 &ipic 17 8
132 9800 0 0 2 &ipic 14 8
133 9800 0 0 3 &ipic 15 8
134 9800 0 0 4 &ipic 16 8
135
136 /* IDSEL 0x15 AD21*/
137 a800 0 0 1 &ipic 14 8
138 a800 0 0 2 &ipic 15 8
139 a800 0 0 3 &ipic 16 8
140 a800 0 0 4 &ipic 17 8
141
142 /* IDSEL 0x16 AD22*/
143 b000 0 0 1 &ipic 17 8
144 b000 0 0 2 &ipic 14 8
145 b000 0 0 3 &ipic 15 8
146 b000 0 0 4 &ipic 16 8
147
148 /* IDSEL 0x17 AD23*/
149 b800 0 0 1 &ipic 16 8
150 b800 0 0 2 &ipic 17 8
151 b800 0 0 3 &ipic 14 8
152 b800 0 0 4 &ipic 15 8
153
154 /* IDSEL 0x18 AD24*/
155 c000 0 0 1 &ipic 15 8
156 c000 0 0 2 &ipic 16 8
157 c000 0 0 3 &ipic 17 8
158 c000 0 0 4 &ipic 14 8>;
159 interrupt-parent = < &ipic >;
160 interrupts = <42 8>;
161 bus-range = <0 0>;
162 ranges = <02000000 0 a0000000 a0000000 0 10000000
163 42000000 0 80000000 80000000 0 10000000
164 01000000 0 00000000 e2000000 0 00100000>;
165 clock-frequency = <3f940aa>;
166 #interrupt-cells = <1>;
167 #size-cells = <2>;
168 #address-cells = <3>;
169 reg = <8500 100>;
170 compatible = "fsl,mpc8349-pci";
171 device_type = "pci";
172 };
173
174 ipic: pic@700 { 114 ipic: pic@700 {
175 interrupt-controller; 115 interrupt-controller;
176 #address-cells = <0>; 116 #address-cells = <0>;
@@ -365,6 +305,65 @@
365 interrupts = <20 8 21 8>; //high:32 low:33 305 interrupts = <20 8 21 8>; //high:32 low:33
366 interrupt-parent = < &ipic >; 306 interrupt-parent = < &ipic >;
367 }; 307 };
308 };
368 309
310 pci@e0008500 {
311 interrupt-map-mask = <f800 0 0 7>;
312 interrupt-map = <
313
314 /* IDSEL 0x11 AD17 */
315 8800 0 0 1 &ipic 14 8
316 8800 0 0 2 &ipic 15 8
317 8800 0 0 3 &ipic 16 8
318 8800 0 0 4 &ipic 17 8
319
320 /* IDSEL 0x12 AD18 */
321 9000 0 0 1 &ipic 16 8
322 9000 0 0 2 &ipic 17 8
323 9000 0 0 3 &ipic 14 8
324 9000 0 0 4 &ipic 15 8
325
326 /* IDSEL 0x13 AD19 */
327 9800 0 0 1 &ipic 17 8
328 9800 0 0 2 &ipic 14 8
329 9800 0 0 3 &ipic 15 8
330 9800 0 0 4 &ipic 16 8
331
332 /* IDSEL 0x15 AD21*/
333 a800 0 0 1 &ipic 14 8
334 a800 0 0 2 &ipic 15 8
335 a800 0 0 3 &ipic 16 8
336 a800 0 0 4 &ipic 17 8
337
338 /* IDSEL 0x16 AD22*/
339 b000 0 0 1 &ipic 17 8
340 b000 0 0 2 &ipic 14 8
341 b000 0 0 3 &ipic 15 8
342 b000 0 0 4 &ipic 16 8
343
344 /* IDSEL 0x17 AD23*/
345 b800 0 0 1 &ipic 16 8
346 b800 0 0 2 &ipic 17 8
347 b800 0 0 3 &ipic 14 8
348 b800 0 0 4 &ipic 15 8
349
350 /* IDSEL 0x18 AD24*/
351 c000 0 0 1 &ipic 15 8
352 c000 0 0 2 &ipic 16 8
353 c000 0 0 3 &ipic 17 8
354 c000 0 0 4 &ipic 14 8>;
355 interrupt-parent = < &ipic >;
356 interrupts = <42 8>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 a0000000 a0000000 0 10000000
359 42000000 0 80000000 80000000 0 10000000
360 01000000 0 00000000 e2000000 0 00100000>;
361 clock-frequency = <3f940aa>;
362 #interrupt-cells = <1>;
363 #size-cells = <2>;
364 #address-cells = <3>;
365 reg = <e0008500 100>;
366 compatible = "fsl,mpc8349-pci";
367 device_type = "pci";
369 }; 368 };
370}; 369};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index e038c04b4220..6442a717ec3b 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -171,104 +171,104 @@
171 interrupts = <2a 2>; 171 interrupts = <2a 2>;
172 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>;
173 }; 173 };
174 pci@8000 { 174 mpic: pic@40000 {
175 interrupt-map-mask = <f800 0 0 7>; 175 clock-frequency = <0>;
176 interrupt-map = < 176 interrupt-controller;
177 #address-cells = <0>;
178 #interrupt-cells = <2>;
179 reg = <40000 40000>;
180 compatible = "chrp,open-pic";
181 device_type = "open-pic";
182 big-endian;
183 };
184 };
177 185
178 /* IDSEL 0x02 */ 186 pci@e0008000 {
179 1000 0 0 1 &mpic 1 1 187 interrupt-map-mask = <f800 0 0 7>;
180 1000 0 0 2 &mpic 2 1 188 interrupt-map = <
181 1000 0 0 3 &mpic 3 1
182 1000 0 0 4 &mpic 4 1
183 189
184 /* IDSEL 0x03 */ 190 /* IDSEL 0x02 */
185 1800 0 0 1 &mpic 4 1 191 1000 0 0 1 &mpic 1 1
186 1800 0 0 2 &mpic 1 1 192 1000 0 0 2 &mpic 2 1
187 1800 0 0 3 &mpic 2 1 193 1000 0 0 3 &mpic 3 1
188 1800 0 0 4 &mpic 3 1 194 1000 0 0 4 &mpic 4 1
189 195
190 /* IDSEL 0x04 */ 196 /* IDSEL 0x03 */
191 2000 0 0 1 &mpic 3 1 197 1800 0 0 1 &mpic 4 1
192 2000 0 0 2 &mpic 4 1 198 1800 0 0 2 &mpic 1 1
193 2000 0 0 3 &mpic 1 1 199 1800 0 0 3 &mpic 2 1
194 2000 0 0 4 &mpic 2 1 200 1800 0 0 4 &mpic 3 1
195 201
196 /* IDSEL 0x05 */ 202 /* IDSEL 0x04 */
197 2800 0 0 1 &mpic 2 1 203 2000 0 0 1 &mpic 3 1
198 2800 0 0 2 &mpic 3 1 204 2000 0 0 2 &mpic 4 1
199 2800 0 0 3 &mpic 4 1 205 2000 0 0 3 &mpic 1 1
200 2800 0 0 4 &mpic 1 1 206 2000 0 0 4 &mpic 2 1
201 207
202 /* IDSEL 0x0c */ 208 /* IDSEL 0x05 */
203 6000 0 0 1 &mpic 1 1 209 2800 0 0 1 &mpic 2 1
204 6000 0 0 2 &mpic 2 1 210 2800 0 0 2 &mpic 3 1
205 6000 0 0 3 &mpic 3 1 211 2800 0 0 3 &mpic 4 1
206 6000 0 0 4 &mpic 4 1 212 2800 0 0 4 &mpic 1 1
207 213
208 /* IDSEL 0x0d */ 214 /* IDSEL 0x0c */
209 6800 0 0 1 &mpic 4 1 215 6000 0 0 1 &mpic 1 1
210 6800 0 0 2 &mpic 1 1 216 6000 0 0 2 &mpic 2 1
211 6800 0 0 3 &mpic 2 1 217 6000 0 0 3 &mpic 3 1
212 6800 0 0 4 &mpic 3 1 218 6000 0 0 4 &mpic 4 1
213 219
214 /* IDSEL 0x0e */ 220 /* IDSEL 0x0d */
215 7000 0 0 1 &mpic 3 1 221 6800 0 0 1 &mpic 4 1
216 7000 0 0 2 &mpic 4 1 222 6800 0 0 2 &mpic 1 1
217 7000 0 0 3 &mpic 1 1 223 6800 0 0 3 &mpic 2 1
218 7000 0 0 4 &mpic 2 1 224 6800 0 0 4 &mpic 3 1
219 225
220 /* IDSEL 0x0f */ 226 /* IDSEL 0x0e */
221 7800 0 0 1 &mpic 2 1 227 7000 0 0 1 &mpic 3 1
222 7800 0 0 2 &mpic 3 1 228 7000 0 0 2 &mpic 4 1
223 7800 0 0 3 &mpic 4 1 229 7000 0 0 3 &mpic 1 1
224 7800 0 0 4 &mpic 1 1 230 7000 0 0 4 &mpic 2 1
225 231
226 /* IDSEL 0x12 */ 232 /* IDSEL 0x0f */
227 9000 0 0 1 &mpic 1 1 233 7800 0 0 1 &mpic 2 1
228 9000 0 0 2 &mpic 2 1 234 7800 0 0 2 &mpic 3 1
229 9000 0 0 3 &mpic 3 1 235 7800 0 0 3 &mpic 4 1
230 9000 0 0 4 &mpic 4 1 236 7800 0 0 4 &mpic 1 1
231 237
232 /* IDSEL 0x13 */ 238 /* IDSEL 0x12 */
233 9800 0 0 1 &mpic 4 1 239 9000 0 0 1 &mpic 1 1
234 9800 0 0 2 &mpic 1 1 240 9000 0 0 2 &mpic 2 1
235 9800 0 0 3 &mpic 2 1 241 9000 0 0 3 &mpic 3 1
236 9800 0 0 4 &mpic 3 1 242 9000 0 0 4 &mpic 4 1
237 243
238 /* IDSEL 0x14 */ 244 /* IDSEL 0x13 */
239 a000 0 0 1 &mpic 3 1 245 9800 0 0 1 &mpic 4 1
240 a000 0 0 2 &mpic 4 1 246 9800 0 0 2 &mpic 1 1
241 a000 0 0 3 &mpic 1 1 247 9800 0 0 3 &mpic 2 1
242 a000 0 0 4 &mpic 2 1 248 9800 0 0 4 &mpic 3 1
243 249
244 /* IDSEL 0x15 */ 250 /* IDSEL 0x14 */
245 a800 0 0 1 &mpic 2 1 251 a000 0 0 1 &mpic 3 1
246 a800 0 0 2 &mpic 3 1 252 a000 0 0 2 &mpic 4 1
247 a800 0 0 3 &mpic 4 1 253 a000 0 0 3 &mpic 1 1
248 a800 0 0 4 &mpic 1 1>; 254 a000 0 0 4 &mpic 2 1
249 interrupt-parent = <&mpic>;
250 interrupts = <18 2>;
251 bus-range = <0 0>;
252 ranges = <02000000 0 80000000 80000000 0 20000000
253 01000000 0 00000000 e2000000 0 00100000>;
254 clock-frequency = <3f940aa>;
255 #interrupt-cells = <1>;
256 #size-cells = <2>;
257 #address-cells = <3>;
258 reg = <8000 1000>;
259 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
260 device_type = "pci";
261 };
262 255
263 mpic: pic@40000 { 256 /* IDSEL 0x15 */
264 clock-frequency = <0>; 257 a800 0 0 1 &mpic 2 1
265 interrupt-controller; 258 a800 0 0 2 &mpic 3 1
266 #address-cells = <0>; 259 a800 0 0 3 &mpic 4 1
267 #interrupt-cells = <2>; 260 a800 0 0 4 &mpic 1 1>;
268 reg = <40000 40000>; 261 interrupt-parent = <&mpic>;
269 compatible = "chrp,open-pic"; 262 interrupts = <18 2>;
270 device_type = "open-pic"; 263 bus-range = <0 0>;
271 big-endian; 264 ranges = <02000000 0 80000000 80000000 0 20000000
272 }; 265 01000000 0 00000000 e2000000 0 00100000>;
266 clock-frequency = <3f940aa>;
267 #interrupt-cells = <1>;
268 #size-cells = <2>;
269 #address-cells = <3>;
270 reg = <e0008000 1000>;
271 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
272 device_type = "pci";
273 }; 273 };
274}; 274};
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 98afd4df27bf..6633e07d9f4d 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -43,7 +43,7 @@
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00001000>; // CCSRBAR 1M
47 bus-frequency = <0>; 47 bus-frequency = <0>;
48 48
49 memory-controller@2000 { 49 memory-controller@2000 {
@@ -135,100 +135,6 @@
135 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
136 }; 136 };
137 137
138 pci1: pci@8000 {
139 interrupt-map-mask = <1f800 0 0 7>;
140 interrupt-map = <
141
142 /* IDSEL 0x10 */
143 08000 0 0 1 &mpic 0 1
144 08000 0 0 2 &mpic 1 1
145 08000 0 0 3 &mpic 2 1
146 08000 0 0 4 &mpic 3 1
147
148 /* IDSEL 0x11 */
149 08800 0 0 1 &mpic 0 1
150 08800 0 0 2 &mpic 1 1
151 08800 0 0 3 &mpic 2 1
152 08800 0 0 4 &mpic 3 1
153
154 /* IDSEL 0x12 (Slot 1) */
155 09000 0 0 1 &mpic 0 1
156 09000 0 0 2 &mpic 1 1
157 09000 0 0 3 &mpic 2 1
158 09000 0 0 4 &mpic 3 1
159
160 /* IDSEL 0x13 (Slot 2) */
161 09800 0 0 1 &mpic 1 1
162 09800 0 0 2 &mpic 2 1
163 09800 0 0 3 &mpic 3 1
164 09800 0 0 4 &mpic 0 1
165
166 /* IDSEL 0x14 (Slot 3) */
167 0a000 0 0 1 &mpic 2 1
168 0a000 0 0 2 &mpic 3 1
169 0a000 0 0 3 &mpic 0 1
170 0a000 0 0 4 &mpic 1 1
171
172 /* IDSEL 0x15 (Slot 4) */
173 0a800 0 0 1 &mpic 3 1
174 0a800 0 0 2 &mpic 0 1
175 0a800 0 0 3 &mpic 1 1
176 0a800 0 0 4 &mpic 2 1
177
178 /* Bus 1 (Tundra Bridge) */
179 /* IDSEL 0x12 (ISA bridge) */
180 19000 0 0 1 &mpic 0 1
181 19000 0 0 2 &mpic 1 1
182 19000 0 0 3 &mpic 2 1
183 19000 0 0 4 &mpic 3 1>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 bus-range = <0 0>;
187 ranges = <02000000 0 80000000 80000000 0 20000000
188 01000000 0 00000000 e2000000 0 00100000>;
189 clock-frequency = <3f940aa>;
190 #interrupt-cells = <1>;
191 #size-cells = <2>;
192 #address-cells = <3>;
193 reg = <8000 1000>;
194 compatible = "fsl,mpc8540-pci";
195 device_type = "pci";
196
197 i8259@19000 {
198 interrupt-controller;
199 device_type = "interrupt-controller";
200 reg = <19000 0 0 0 1>;
201 #address-cells = <0>;
202 #interrupt-cells = <2>;
203 compatible = "chrp,iic";
204 interrupts = <1>;
205 interrupt-parent = <&pci1>;
206 };
207 };
208
209 pci@9000 {
210 interrupt-map-mask = <f800 0 0 7>;
211 interrupt-map = <
212
213 /* IDSEL 0x15 */
214 a800 0 0 1 &mpic b 1
215 a800 0 0 2 &mpic b 1
216 a800 0 0 3 &mpic b 1
217 a800 0 0 4 &mpic b 1>;
218 interrupt-parent = <&mpic>;
219 interrupts = <19 2>;
220 bus-range = <0 0>;
221 ranges = <02000000 0 a0000000 a0000000 0 20000000
222 01000000 0 00000000 e3000000 0 00100000>;
223 clock-frequency = <3f940aa>;
224 #interrupt-cells = <1>;
225 #size-cells = <2>;
226 #address-cells = <3>;
227 reg = <9000 1000>;
228 compatible = "fsl,mpc8540-pci";
229 device_type = "pci";
230 };
231
232 mpic: pic@40000 { 138 mpic: pic@40000 {
233 clock-frequency = <0>; 139 clock-frequency = <0>;
234 interrupt-controller; 140 interrupt-controller;
@@ -240,4 +146,98 @@
240 big-endian; 146 big-endian;
241 }; 147 };
242 }; 148 };
149
150 pci1: pci@e0008000 {
151 interrupt-map-mask = <1f800 0 0 7>;
152 interrupt-map = <
153
154 /* IDSEL 0x10 */
155 08000 0 0 1 &mpic 0 1
156 08000 0 0 2 &mpic 1 1
157 08000 0 0 3 &mpic 2 1
158 08000 0 0 4 &mpic 3 1
159
160 /* IDSEL 0x11 */
161 08800 0 0 1 &mpic 0 1
162 08800 0 0 2 &mpic 1 1
163 08800 0 0 3 &mpic 2 1
164 08800 0 0 4 &mpic 3 1
165
166 /* IDSEL 0x12 (Slot 1) */
167 09000 0 0 1 &mpic 0 1
168 09000 0 0 2 &mpic 1 1
169 09000 0 0 3 &mpic 2 1
170 09000 0 0 4 &mpic 3 1
171
172 /* IDSEL 0x13 (Slot 2) */
173 09800 0 0 1 &mpic 1 1
174 09800 0 0 2 &mpic 2 1
175 09800 0 0 3 &mpic 3 1
176 09800 0 0 4 &mpic 0 1
177
178 /* IDSEL 0x14 (Slot 3) */
179 0a000 0 0 1 &mpic 2 1
180 0a000 0 0 2 &mpic 3 1
181 0a000 0 0 3 &mpic 0 1
182 0a000 0 0 4 &mpic 1 1
183
184 /* IDSEL 0x15 (Slot 4) */
185 0a800 0 0 1 &mpic 3 1
186 0a800 0 0 2 &mpic 0 1
187 0a800 0 0 3 &mpic 1 1
188 0a800 0 0 4 &mpic 2 1
189
190 /* Bus 1 (Tundra Bridge) */
191 /* IDSEL 0x12 (ISA bridge) */
192 19000 0 0 1 &mpic 0 1
193 19000 0 0 2 &mpic 1 1
194 19000 0 0 3 &mpic 2 1
195 19000 0 0 4 &mpic 3 1>;
196 interrupt-parent = <&mpic>;
197 interrupts = <18 2>;
198 bus-range = <0 0>;
199 ranges = <02000000 0 80000000 80000000 0 20000000
200 01000000 0 00000000 e2000000 0 00100000>;
201 clock-frequency = <3f940aa>;
202 #interrupt-cells = <1>;
203 #size-cells = <2>;
204 #address-cells = <3>;
205 reg = <e0008000 1000>;
206 compatible = "fsl,mpc8540-pci";
207 device_type = "pci";
208
209 i8259@19000 {
210 interrupt-controller;
211 device_type = "interrupt-controller";
212 reg = <19000 0 0 0 1>;
213 #address-cells = <0>;
214 #interrupt-cells = <2>;
215 compatible = "chrp,iic";
216 interrupts = <1>;
217 interrupt-parent = <&pci1>;
218 };
219 };
220
221 pci@e0009000 {
222 interrupt-map-mask = <f800 0 0 7>;
223 interrupt-map = <
224
225 /* IDSEL 0x15 */
226 a800 0 0 1 &mpic b 1
227 a800 0 0 2 &mpic b 1
228 a800 0 0 3 &mpic b 1
229 a800 0 0 4 &mpic b 1>;
230 interrupt-parent = <&mpic>;
231 interrupts = <19 2>;
232 bus-range = <0 0>;
233 ranges = <02000000 0 a0000000 a0000000 0 20000000
234 01000000 0 00000000 e3000000 0 00100000>;
235 clock-frequency = <3f940aa>;
236 #interrupt-cells = <1>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 reg = <e0009000 1000>;
240 compatible = "fsl,mpc8540-pci";
241 device_type = "pci";
242 };
243}; 243};
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 88082ac6f2cd..3f9d15cf13e0 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -43,16 +43,7 @@
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 45
46 46 ranges = <00000000 e0000000 00100000>;
47 ranges = <00001000 e0001000 000ff000
48 80000000 80000000 20000000
49 a0000000 a0000000 10000000
50 b0000000 b0000000 00100000
51 c0000000 c0000000 20000000
52 b0100000 b0100000 00100000
53 e1000000 e1000000 00010000
54 e1010000 e1010000 00010000
55 e1020000 e1020000 00010000>;
56 reg = <e0000000 00001000>; // CCSRBAR 1M 47 reg = <e0000000 00001000>; // CCSRBAR 1M
57 bus-frequency = <0>; // Filled out by uboot. 48 bus-frequency = <0>; // Filled out by uboot.
58 49
@@ -147,115 +138,173 @@
147 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
148 }; 139 };
149 140
150 pci@8000 { 141 global-utilities@e0000 { //global utilities block
151 compatible = "fsl,mpc8540-pci"; 142 compatible = "fsl,mpc8548-guts";
152 device_type = "pci"; 143 reg = <e0000 1000>;
153 interrupt-map-mask = <f800 0 0 7>; 144 fsl,has-rstcr;
154 interrupt-map = < 145 };
155
156 /* IDSEL 0x11 J17 Slot 1 */
157 8800 0 0 1 &mpic 2 1
158 8800 0 0 2 &mpic 3 1
159 8800 0 0 3 &mpic 4 1
160 8800 0 0 4 &mpic 1 1
161 146
162 /* IDSEL 0x12 J16 Slot 2 */ 147 mpic: pic@40000 {
148 clock-frequency = <0>;
149 interrupt-controller;
150 #address-cells = <0>;
151 #interrupt-cells = <2>;
152 reg = <40000 40000>;
153 compatible = "chrp,open-pic";
154 device_type = "open-pic";
155 big-endian;
156 };
157 };
163 158
164 9000 0 0 1 &mpic 3 1 159 pci@e0008000 {
165 9000 0 0 2 &mpic 4 1 160 compatible = "fsl,mpc8540-pci";
166 9000 0 0 3 &mpic 2 1 161 device_type = "pci";
167 9000 0 0 4 &mpic 1 1>; 162 interrupt-map-mask = <f800 0 0 7>;
163 interrupt-map = <
164
165 /* IDSEL 0x11 J17 Slot 1 */
166 8800 0 0 1 &mpic 2 1
167 8800 0 0 2 &mpic 3 1
168 8800 0 0 3 &mpic 4 1
169 8800 0 0 4 &mpic 1 1
170
171 /* IDSEL 0x12 J16 Slot 2 */
172
173 9000 0 0 1 &mpic 3 1
174 9000 0 0 2 &mpic 4 1
175 9000 0 0 3 &mpic 2 1
176 9000 0 0 4 &mpic 1 1>;
177
178 interrupt-parent = <&mpic>;
179 interrupts = <18 2>;
180 bus-range = <0 ff>;
181 ranges = <02000000 0 c0000000 c0000000 0 20000000
182 01000000 0 00000000 e1000000 0 00010000>;
183 clock-frequency = <3f940aa>;
184 #interrupt-cells = <1>;
185 #size-cells = <2>;
186 #address-cells = <3>;
187 reg = <e0008000 1000>;
188 };
168 189
169 interrupt-parent = <&mpic>; 190 pcie@e0009000 {
170 interrupts = <18 2>; 191 compatible = "fsl,mpc8548-pcie";
171 bus-range = <0 ff>; 192 device_type = "pci";
172 ranges = <02000000 0 c0000000 c0000000 0 20000000 193 #interrupt-cells = <1>;
173 01000000 0 00000000 e1000000 0 00010000>; 194 #size-cells = <2>;
174 clock-frequency = <3f940aa>; 195 #address-cells = <3>;
175 #interrupt-cells = <1>; 196 reg = <e0009000 1000>;
197 bus-range = <0 ff>;
198 ranges = <02000000 0 80000000 80000000 0 20000000
199 01000000 0 00000000 e1010000 0 00010000>;
200 clock-frequency = <1fca055>;
201 interrupt-parent = <&mpic>;
202 interrupts = <1a 2>;
203 interrupt-map-mask = <f800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x0 */
206 0000 0 0 1 &mpic 4 1
207 0000 0 0 2 &mpic 5 1
208 0000 0 0 3 &mpic 6 1
209 0000 0 0 4 &mpic 7 1
210 >;
211 pcie@0 {
212 reg = <0 0 0 0 0>;
176 #size-cells = <2>; 213 #size-cells = <2>;
177 #address-cells = <3>; 214 #address-cells = <3>;
178 reg = <8000 1000>;
179 };
180
181 pcie@9000 {
182 compatible = "fsl,mpc8548-pcie";
183 device_type = "pci"; 215 device_type = "pci";
184 #interrupt-cells = <1>; 216 ranges = <02000000 0 80000000
185 #size-cells = <2>; 217 02000000 0 80000000
186 #address-cells = <3>; 218 0 20000000
187 reg = <9000 1000>; 219
188 bus-range = <0 ff>; 220 01000000 0 00000000
189 ranges = <02000000 0 80000000 80000000 0 20000000 221 01000000 0 00000000
190 01000000 0 00000000 e1010000 0 00010000>; 222 0 00010000>;
191 clock-frequency = <1fca055>;
192 interrupt-parent = <&mpic>;
193 interrupts = <1a 2>;
194 interrupt-map-mask = <f800 0 0 7>;
195 interrupt-map = <
196 /* IDSEL 0x0 */
197 0000 0 0 1 &mpic 4 1
198 0000 0 0 2 &mpic 5 1
199 0000 0 0 3 &mpic 6 1
200 0000 0 0 4 &mpic 7 1
201 >;
202 }; 223 };
224 };
203 225
204 pcie@a000 { 226 pcie@e000a000 {
205 compatible = "fsl,mpc8548-pcie"; 227 compatible = "fsl,mpc8548-pcie";
206 device_type = "pci"; 228 device_type = "pci";
207 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <e000a000 1000>;
233 bus-range = <0 ff>;
234 ranges = <02000000 0 a0000000 a0000000 0 10000000
235 01000000 0 00000000 e1020000 0 00010000>;
236 clock-frequency = <1fca055>;
237 interrupt-parent = <&mpic>;
238 interrupts = <19 2>;
239 interrupt-map-mask = <f800 0 0 7>;
240 interrupt-map = <
241 /* IDSEL 0x0 */
242 0000 0 0 1 &mpic 0 1
243 0000 0 0 2 &mpic 1 1
244 0000 0 0 3 &mpic 2 1
245 0000 0 0 4 &mpic 3 1
246 >;
247 pcie@0 {
248 reg = <0 0 0 0 0>;
208 #size-cells = <2>; 249 #size-cells = <2>;
209 #address-cells = <3>; 250 #address-cells = <3>;
210 reg = <a000 1000>; 251 device_type = "pci";
211 bus-range = <0 ff>; 252 ranges = <02000000 0 a0000000
212 ranges = <02000000 0 a0000000 a0000000 0 10000000 253 02000000 0 a0000000
213 01000000 0 00000000 e1020000 0 00010000>; 254 0 10000000
214 clock-frequency = <1fca055>; 255
215 interrupt-parent = <&mpic>; 256 01000000 0 00000000
216 interrupts = <19 2>; 257 01000000 0 00000000
217 interrupt-map-mask = <f800 0 0 7>; 258 0 00010000>;
218 interrupt-map = <
219 /* IDSEL 0x0 */
220 0000 0 0 1 &mpic 0 1
221 0000 0 0 2 &mpic 1 1
222 0000 0 0 3 &mpic 2 1
223 0000 0 0 4 &mpic 3 1
224 >;
225 }; 259 };
260 };
226 261
227 pcie@b000 { 262 pcie@e000b000 {
228 compatible = "fsl,mpc8548-pcie"; 263 compatible = "fsl,mpc8548-pcie";
229 device_type = "pci"; 264 device_type = "pci";
230 #interrupt-cells = <1>; 265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e000b000 1000>;
269 bus-range = <0 ff>;
270 ranges = <02000000 0 b0000000 b0000000 0 00100000
271 01000000 0 00000000 b0100000 0 00100000>;
272 clock-frequency = <1fca055>;
273 interrupt-parent = <&mpic>;
274 interrupts = <1b 2>;
275 interrupt-map-mask = <fb00 0 0 0>;
276 interrupt-map = <
277 // IDSEL 0x1c USB
278 e000 0 0 0 &i8259 c 2
279 e100 0 0 0 &i8259 9 2
280 e200 0 0 0 &i8259 a 2
281 e300 0 0 0 &i8259 b 2
282
283 // IDSEL 0x1d Audio
284 e800 0 0 0 &i8259 6 2
285
286 // IDSEL 0x1e Legacy
287 f000 0 0 0 &i8259 7 2
288 f100 0 0 0 &i8259 7 2
289
290 // IDSEL 0x1f IDE/SATA
291 f800 0 0 0 &i8259 e 2
292 f900 0 0 0 &i8259 5 2
293 >;
294
295 pcie@0 {
296 reg = <0 0 0 0 0>;
231 #size-cells = <2>; 297 #size-cells = <2>;
232 #address-cells = <3>; 298 #address-cells = <3>;
233 reg = <b000 1000>; 299 device_type = "pci";
234 bus-range = <0 ff>; 300 ranges = <02000000 0 b0000000
235 ranges = <02000000 0 b0000000 b0000000 0 00100000 301 02000000 0 b0000000
236 01000000 0 00000000 b0100000 0 00100000>; 302 0 00100000
237 clock-frequency = <1fca055>; 303
238 interrupt-parent = <&mpic>; 304 01000000 0 00000000
239 interrupts = <1b 2>; 305 01000000 0 00000000
240 interrupt-map-mask = <fb00 0 0 0>; 306 0 00100000>;
241 interrupt-map = < 307
242 // IDSEL 0x1c USB
243 e000 0 0 0 &i8259 c 2
244 e100 0 0 0 &i8259 9 2
245 e200 0 0 0 &i8259 a 2
246 e300 0 0 0 &i8259 b 2
247
248 // IDSEL 0x1d Audio
249 e800 0 0 0 &i8259 6 2
250
251 // IDSEL 0x1e Legacy
252 f000 0 0 0 &i8259 7 2
253 f100 0 0 0 &i8259 7 2
254
255 // IDSEL 0x1f IDE/SATA
256 f800 0 0 0 &i8259 e 2
257 f900 0 0 0 &i8259 5 2
258 >;
259 uli1575@0 { 308 uli1575@0 {
260 reg = <0 0 0 0 0>; 309 reg = <0 0 0 0 0>;
261 #size-cells = <2>; 310 #size-cells = <2>;
@@ -263,92 +312,63 @@
263 ranges = <02000000 0 b0000000 312 ranges = <02000000 0 b0000000
264 02000000 0 b0000000 313 02000000 0 b0000000
265 0 00100000 314 0 00100000
315
266 01000000 0 00000000 316 01000000 0 00000000
267 01000000 0 00000000 317 01000000 0 00000000
268 0 00100000>; 318 0 00100000>;
269 319 isa@1e {
270 pci_bridge@0 { 320 device_type = "isa";
271 reg = <0 0 0 0 0>; 321 #interrupt-cells = <2>;
272 #size-cells = <2>; 322 #size-cells = <1>;
273 #address-cells = <3>; 323 #address-cells = <2>;
274 ranges = <02000000 0 b0000000 324 reg = <f000 0 0 0 0>;
275 02000000 0 b0000000 325 ranges = <1 0
276 0 00100000 326 01000000 0 0
277 01000000 0 00000000 327 00001000>;
278 01000000 0 00000000 328 interrupt-parent = <&i8259>;
279 0 00100000>; 329
280 330 i8259: interrupt-controller@20 {
281 isa@1e { 331 reg = <1 20 2
282 device_type = "isa"; 332 1 a0 2
333 1 4d0 2>;
334 interrupt-controller;
335 device_type = "interrupt-controller";
336 #address-cells = <0>;
283 #interrupt-cells = <2>; 337 #interrupt-cells = <2>;
284 #size-cells = <1>; 338 compatible = "chrp,iic";
285 #address-cells = <2>; 339 interrupts = <9 2>;
286 reg = <f000 0 0 0 0>; 340 interrupt-parent = <&mpic>;
287 ranges = <1 0 341 };
288 01000000 0 0 342
289 00001000>; 343 i8042@60 {
344 #size-cells = <0>;
345 #address-cells = <1>;
346 reg = <1 60 1 1 64 1>;
347 interrupts = <1 3 c 3>;
290 interrupt-parent = <&i8259>; 348 interrupt-parent = <&i8259>;
291 349
292 i8259: interrupt-controller@20 { 350 keyboard@0 {
293 reg = <1 20 2 351 reg = <0>;
294 1 a0 2 352 compatible = "pnpPNP,303";
295 1 4d0 2>;
296 interrupt-controller;
297 device_type = "interrupt-controller";
298 #address-cells = <0>;
299 #interrupt-cells = <2>;
300 compatible = "chrp,iic";
301 interrupts = <9 2>;
302 interrupt-parent = <&mpic>;
303 }; 353 };
304 354
305 i8042@60 { 355 mouse@1 {
306 #size-cells = <0>; 356 reg = <1>;
307 #address-cells = <1>; 357 compatible = "pnpPNP,f03";
308 reg = <1 60 1 1 64 1>;
309 interrupts = <1 3 c 3>;
310 interrupt-parent = <&i8259>;
311
312 keyboard@0 {
313 reg = <0>;
314 compatible = "pnpPNP,303";
315 };
316
317 mouse@1 {
318 reg = <1>;
319 compatible = "pnpPNP,f03";
320 };
321 }; 358 };
359 };
322 360
323 rtc@70 { 361 rtc@70 {
324 compatible = "pnpPNP,b00"; 362 compatible = "pnpPNP,b00";
325 reg = <1 70 2>; 363 reg = <1 70 2>;
326 }; 364 };
327 365
328 gpio@400 { 366 gpio@400 {
329 reg = <1 400 80>; 367 reg = <1 400 80>;
330 };
331 }; 368 };
332 }; 369 };
333 }; 370 };
334
335 }; 371 };
336 372
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,mpc8548-guts";
339 reg = <e0000 1000>;
340 fsl,has-rstcr;
341 };
342
343 mpic: pic@40000 {
344 clock-frequency = <0>;
345 interrupt-controller;
346 #address-cells = <0>;
347 #interrupt-cells = <2>;
348 reg = <40000 40000>;
349 compatible = "chrp,open-pic";
350 device_type = "open-pic";
351 big-endian;
352 };
353 }; 373 };
354}; 374};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 11b823595a08..69ca5025d972 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -42,13 +42,7 @@
42 #address-cells = <1>; 42 #address-cells = <1>;
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 ranges = <00001000 e0001000 000ff000 45 ranges = <00000000 e0000000 00100000>;
46 80000000 80000000 10000000
47 e2000000 e2000000 00800000
48 90000000 90000000 10000000
49 e2800000 e2800000 00800000
50 a0000000 a0000000 20000000
51 e3000000 e3000000 01000000>;
52 reg = <e0000000 00001000>; // CCSRBAR 46 reg = <e0000000 00001000>; // CCSRBAR
53 bus-frequency = <0>; 47 bus-frequency = <0>;
54 48
@@ -187,212 +181,225 @@
187 fsl,has-rstcr; 181 fsl,has-rstcr;
188 }; 182 };
189 183
190 pci@8000 { 184 mpic: pic@40000 {
185 clock-frequency = <0>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
189 reg = <40000 40000>;
190 compatible = "chrp,open-pic";
191 device_type = "open-pic";
192 big-endian;
193 };
194 };
195
196 pci@e0008000 {
197 interrupt-map-mask = <f800 0 0 7>;
198 interrupt-map = <
199 /* IDSEL 0x4 (PCIX Slot 2) */
200 02000 0 0 1 &mpic 0 1
201 02000 0 0 2 &mpic 1 1
202 02000 0 0 3 &mpic 2 1
203 02000 0 0 4 &mpic 3 1
204
205 /* IDSEL 0x5 (PCIX Slot 3) */
206 02800 0 0 1 &mpic 1 1
207 02800 0 0 2 &mpic 2 1
208 02800 0 0 3 &mpic 3 1
209 02800 0 0 4 &mpic 0 1
210
211 /* IDSEL 0x6 (PCIX Slot 4) */
212 03000 0 0 1 &mpic 2 1
213 03000 0 0 2 &mpic 3 1
214 03000 0 0 3 &mpic 0 1
215 03000 0 0 4 &mpic 1 1
216
217 /* IDSEL 0x8 (PCIX Slot 5) */
218 04000 0 0 1 &mpic 0 1
219 04000 0 0 2 &mpic 1 1
220 04000 0 0 3 &mpic 2 1
221 04000 0 0 4 &mpic 3 1
222
223 /* IDSEL 0xC (Tsi310 bridge) */
224 06000 0 0 1 &mpic 0 1
225 06000 0 0 2 &mpic 1 1
226 06000 0 0 3 &mpic 2 1
227 06000 0 0 4 &mpic 3 1
228
229 /* IDSEL 0x14 (Slot 2) */
230 0a000 0 0 1 &mpic 0 1
231 0a000 0 0 2 &mpic 1 1
232 0a000 0 0 3 &mpic 2 1
233 0a000 0 0 4 &mpic 3 1
234
235 /* IDSEL 0x15 (Slot 3) */
236 0a800 0 0 1 &mpic 1 1
237 0a800 0 0 2 &mpic 2 1
238 0a800 0 0 3 &mpic 3 1
239 0a800 0 0 4 &mpic 0 1
240
241 /* IDSEL 0x16 (Slot 4) */
242 0b000 0 0 1 &mpic 2 1
243 0b000 0 0 2 &mpic 3 1
244 0b000 0 0 3 &mpic 0 1
245 0b000 0 0 4 &mpic 1 1
246
247 /* IDSEL 0x18 (Slot 5) */
248 0c000 0 0 1 &mpic 0 1
249 0c000 0 0 2 &mpic 1 1
250 0c000 0 0 3 &mpic 2 1
251 0c000 0 0 4 &mpic 3 1
252
253 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
254 0E000 0 0 1 &mpic 0 1
255 0E000 0 0 2 &mpic 1 1
256 0E000 0 0 3 &mpic 2 1
257 0E000 0 0 4 &mpic 3 1>;
258
259 interrupt-parent = <&mpic>;
260 interrupts = <18 2>;
261 bus-range = <0 0>;
262 ranges = <02000000 0 80000000 80000000 0 10000000
263 01000000 0 00000000 e2000000 0 00800000>;
264 clock-frequency = <3f940aa>;
265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e0008000 1000>;
269 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
270 device_type = "pci";
271
272 pci_bridge@1c {
191 interrupt-map-mask = <f800 0 0 7>; 273 interrupt-map-mask = <f800 0 0 7>;
192 interrupt-map = < 274 interrupt-map = <
193 /* IDSEL 0x4 (PCIX Slot 2) */
194 02000 0 0 1 &mpic 0 1
195 02000 0 0 2 &mpic 1 1
196 02000 0 0 3 &mpic 2 1
197 02000 0 0 4 &mpic 3 1
198
199 /* IDSEL 0x5 (PCIX Slot 3) */
200 02800 0 0 1 &mpic 1 1
201 02800 0 0 2 &mpic 2 1
202 02800 0 0 3 &mpic 3 1
203 02800 0 0 4 &mpic 0 1
204
205 /* IDSEL 0x6 (PCIX Slot 4) */
206 03000 0 0 1 &mpic 2 1
207 03000 0 0 2 &mpic 3 1
208 03000 0 0 3 &mpic 0 1
209 03000 0 0 4 &mpic 1 1
210
211 /* IDSEL 0x8 (PCIX Slot 5) */
212 04000 0 0 1 &mpic 0 1
213 04000 0 0 2 &mpic 1 1
214 04000 0 0 3 &mpic 2 1
215 04000 0 0 4 &mpic 3 1
216
217 /* IDSEL 0xC (Tsi310 bridge) */
218 06000 0 0 1 &mpic 0 1
219 06000 0 0 2 &mpic 1 1
220 06000 0 0 3 &mpic 2 1
221 06000 0 0 4 &mpic 3 1
222
223 /* IDSEL 0x14 (Slot 2) */
224 0a000 0 0 1 &mpic 0 1
225 0a000 0 0 2 &mpic 1 1
226 0a000 0 0 3 &mpic 2 1
227 0a000 0 0 4 &mpic 3 1
228
229 /* IDSEL 0x15 (Slot 3) */
230 0a800 0 0 1 &mpic 1 1
231 0a800 0 0 2 &mpic 2 1
232 0a800 0 0 3 &mpic 3 1
233 0a800 0 0 4 &mpic 0 1
234
235 /* IDSEL 0x16 (Slot 4) */
236 0b000 0 0 1 &mpic 2 1
237 0b000 0 0 2 &mpic 3 1
238 0b000 0 0 3 &mpic 0 1
239 0b000 0 0 4 &mpic 1 1
240
241 /* IDSEL 0x18 (Slot 5) */
242 0c000 0 0 1 &mpic 0 1
243 0c000 0 0 2 &mpic 1 1
244 0c000 0 0 3 &mpic 2 1
245 0c000 0 0 4 &mpic 3 1
246
247 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
248 0E000 0 0 1 &mpic 0 1
249 0E000 0 0 2 &mpic 1 1
250 0E000 0 0 3 &mpic 2 1
251 0E000 0 0 4 &mpic 3 1>;
252 275
253 interrupt-parent = <&mpic>; 276 /* IDSEL 0x00 (PrPMC Site) */
254 interrupts = <18 2>; 277 0000 0 0 1 &mpic 0 1
255 bus-range = <0 0>; 278 0000 0 0 2 &mpic 1 1
256 ranges = <02000000 0 80000000 80000000 0 10000000 279 0000 0 0 3 &mpic 2 1
257 01000000 0 00000000 e2000000 0 00800000>; 280 0000 0 0 4 &mpic 3 1
258 clock-frequency = <3f940aa>; 281
282 /* IDSEL 0x04 (VIA chip) */
283 2000 0 0 1 &mpic 0 1
284 2000 0 0 2 &mpic 1 1
285 2000 0 0 3 &mpic 2 1
286 2000 0 0 4 &mpic 3 1
287
288 /* IDSEL 0x05 (8139) */
289 2800 0 0 1 &mpic 1 1
290
291 /* IDSEL 0x06 (Slot 6) */
292 3000 0 0 1 &mpic 2 1
293 3000 0 0 2 &mpic 3 1
294 3000 0 0 3 &mpic 0 1
295 3000 0 0 4 &mpic 1 1
296
297 /* IDESL 0x07 (Slot 7) */
298 3800 0 0 1 &mpic 3 1
299 3800 0 0 2 &mpic 0 1
300 3800 0 0 3 &mpic 1 1
301 3800 0 0 4 &mpic 2 1>;
302
303 reg = <e000 0 0 0 0>;
259 #interrupt-cells = <1>; 304 #interrupt-cells = <1>;
260 #size-cells = <2>; 305 #size-cells = <2>;
261 #address-cells = <3>; 306 #address-cells = <3>;
262 reg = <8000 1000>; 307 ranges = <02000000 0 80000000
263 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 308 02000000 0 80000000
264 device_type = "pci"; 309 0 20000000
310 01000000 0 00000000
311 01000000 0 00000000
312 0 00080000>;
313 clock-frequency = <1fca055>;
265 314
266 pci_bridge@1c { 315 isa@4 {
267 interrupt-map-mask = <f800 0 0 7>; 316 device_type = "isa";
268 interrupt-map = < 317 #interrupt-cells = <2>;
269 318 #size-cells = <1>;
270 /* IDSEL 0x00 (PrPMC Site) */ 319 #address-cells = <2>;
271 0000 0 0 1 &mpic 0 1 320 reg = <2000 0 0 0 0>;
272 0000 0 0 2 &mpic 1 1 321 ranges = <1 0 01000000 0 0 00001000>;
273 0000 0 0 3 &mpic 2 1 322 interrupt-parent = <&i8259>;
274 0000 0 0 4 &mpic 3 1 323
275 324 i8259: interrupt-controller@20 {
276 /* IDSEL 0x04 (VIA chip) */ 325 interrupt-controller;
277 2000 0 0 1 &mpic 0 1 326 device_type = "interrupt-controller";
278 2000 0 0 2 &mpic 1 1 327 reg = <1 20 2
279 2000 0 0 3 &mpic 2 1 328 1 a0 2
280 2000 0 0 4 &mpic 3 1 329 1 4d0 2>;
281 330 #address-cells = <0>;
282 /* IDSEL 0x05 (8139) */
283 2800 0 0 1 &mpic 1 1
284
285 /* IDSEL 0x06 (Slot 6) */
286 3000 0 0 1 &mpic 2 1
287 3000 0 0 2 &mpic 3 1
288 3000 0 0 3 &mpic 0 1
289 3000 0 0 4 &mpic 1 1
290
291 /* IDESL 0x07 (Slot 7) */
292 3800 0 0 1 &mpic 3 1
293 3800 0 0 2 &mpic 0 1
294 3800 0 0 3 &mpic 1 1
295 3800 0 0 4 &mpic 2 1>;
296
297 reg = <e000 0 0 0 0>;
298 #interrupt-cells = <1>;
299 #size-cells = <2>;
300 #address-cells = <3>;
301 ranges = <02000000 0 80000000
302 02000000 0 80000000
303 0 20000000
304 01000000 0 00000000
305 01000000 0 00000000
306 0 00080000>;
307 clock-frequency = <1fca055>;
308
309 isa@4 {
310 device_type = "isa";
311 #interrupt-cells = <2>; 331 #interrupt-cells = <2>;
312 #size-cells = <1>; 332 compatible = "chrp,iic";
313 #address-cells = <2>; 333 interrupts = <0 1>;
314 reg = <2000 0 0 0 0>; 334 interrupt-parent = <&mpic>;
315 ranges = <1 0 01000000 0 0 00001000>;
316 interrupt-parent = <&i8259>;
317
318 i8259: interrupt-controller@20 {
319 interrupt-controller;
320 device_type = "interrupt-controller";
321 reg = <1 20 2
322 1 a0 2
323 1 4d0 2>;
324 #address-cells = <0>;
325 #interrupt-cells = <2>;
326 compatible = "chrp,iic";
327 interrupts = <0 1>;
328 interrupt-parent = <&mpic>;
329 };
330
331 rtc@70 {
332 compatible = "pnpPNP,b00";
333 reg = <1 70 2>;
334 };
335 }; 335 };
336 };
337 };
338 336
339 pci@9000 { 337 rtc@70 {
340 interrupt-map-mask = <f800 0 0 7>; 338 compatible = "pnpPNP,b00";
341 interrupt-map = < 339 reg = <1 70 2>;
342 340 };
343 /* IDSEL 0x15 */ 341 };
344 a800 0 0 1 &mpic b 1
345 a800 0 0 2 &mpic 1 1
346 a800 0 0 3 &mpic 2 1
347 a800 0 0 4 &mpic 3 1>;
348
349 interrupt-parent = <&mpic>;
350 interrupts = <19 2>;
351 bus-range = <0 0>;
352 ranges = <02000000 0 90000000 90000000 0 10000000
353 01000000 0 00000000 e2800000 0 00800000>;
354 clock-frequency = <3f940aa>;
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <9000 1000>;
359 compatible = "fsl,mpc8540-pci";
360 device_type = "pci";
361 }; 342 };
362 /* PCI Express */ 343 };
363 pcie@a000 {
364 interrupt-map-mask = <f800 0 0 7>;
365 interrupt-map = <
366 344
367 /* IDSEL 0x0 (PEX) */ 345 pci@e0009000 {
368 00000 0 0 1 &mpic 0 1 346 interrupt-map-mask = <f800 0 0 7>;
369 00000 0 0 2 &mpic 1 1 347 interrupt-map = <
370 00000 0 0 3 &mpic 2 1 348
371 00000 0 0 4 &mpic 3 1>; 349 /* IDSEL 0x15 */
350 a800 0 0 1 &mpic b 1
351 a800 0 0 2 &mpic 1 1
352 a800 0 0 3 &mpic 2 1
353 a800 0 0 4 &mpic 3 1>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <19 2>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 90000000 90000000 0 10000000
359 01000000 0 00000000 e2800000 0 00800000>;
360 clock-frequency = <3f940aa>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <e0009000 1000>;
365 compatible = "fsl,mpc8540-pci";
366 device_type = "pci";
367 };
372 368
373 interrupt-parent = <&mpic>; 369 pcie@e000a000 {
374 interrupts = <1a 2>; 370 interrupt-map-mask = <f800 0 0 7>;
375 bus-range = <0 ff>; 371 interrupt-map = <
376 ranges = <02000000 0 a0000000 a0000000 0 20000000 372
377 01000000 0 00000000 e3000000 0 08000000>; 373 /* IDSEL 0x0 (PEX) */
378 clock-frequency = <1fca055>; 374 00000 0 0 1 &mpic 0 1
379 #interrupt-cells = <1>; 375 00000 0 0 2 &mpic 1 1
376 00000 0 0 3 &mpic 2 1
377 00000 0 0 4 &mpic 3 1>;
378
379 interrupt-parent = <&mpic>;
380 interrupts = <1a 2>;
381 bus-range = <0 ff>;
382 ranges = <02000000 0 a0000000 a0000000 0 20000000
383 01000000 0 00000000 e3000000 0 08000000>;
384 clock-frequency = <1fca055>;
385 #interrupt-cells = <1>;
386 #size-cells = <2>;
387 #address-cells = <3>;
388 reg = <e000a000 1000>;
389 compatible = "fsl,mpc8548-pcie";
390 device_type = "pci";
391 pcie@0 {
392 reg = <0 0 0 0 0>;
380 #size-cells = <2>; 393 #size-cells = <2>;
381 #address-cells = <3>; 394 #address-cells = <3>;
382 reg = <a000 1000>;
383 compatible = "fsl,mpc8548-pcie";
384 device_type = "pci"; 395 device_type = "pci";
385 }; 396 ranges = <02000000 0 a0000000
397 02000000 0 a0000000
398 0 20000000
386 399
387 mpic: pic@40000 { 400 01000000 0 00000000
388 clock-frequency = <0>; 401 01000000 0 00000000
389 interrupt-controller; 402 0 08000000>;
390 #address-cells = <0>;
391 #interrupt-cells = <2>;
392 reg = <40000 40000>;
393 compatible = "chrp,open-pic";
394 device_type = "open-pic";
395 big-endian;
396 }; 403 };
397 }; 404 };
398}; 405};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index ce11d11293d0..99199295147e 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -43,7 +43,7 @@
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00001000>; // CCSRBAR 1M
47 bus-frequency = <0>; 47 bus-frequency = <0>;
48 48
49 memory-controller@2000 { 49 memory-controller@2000 {
@@ -135,100 +135,6 @@
135 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
136 }; 136 };
137 137
138 pci1: pci@8000 {
139 interrupt-map-mask = <1f800 0 0 7>;
140 interrupt-map = <
141
142 /* IDSEL 0x10 */
143 08000 0 0 1 &mpic 0 1
144 08000 0 0 2 &mpic 1 1
145 08000 0 0 3 &mpic 2 1
146 08000 0 0 4 &mpic 3 1
147
148 /* IDSEL 0x11 */
149 08800 0 0 1 &mpic 0 1
150 08800 0 0 2 &mpic 1 1
151 08800 0 0 3 &mpic 2 1
152 08800 0 0 4 &mpic 3 1
153
154 /* IDSEL 0x12 (Slot 1) */
155 09000 0 0 1 &mpic 0 1
156 09000 0 0 2 &mpic 1 1
157 09000 0 0 3 &mpic 2 1
158 09000 0 0 4 &mpic 3 1
159
160 /* IDSEL 0x13 (Slot 2) */
161 09800 0 0 1 &mpic 1 1
162 09800 0 0 2 &mpic 2 1
163 09800 0 0 3 &mpic 3 1
164 09800 0 0 4 &mpic 0 1
165
166 /* IDSEL 0x14 (Slot 3) */
167 0a000 0 0 1 &mpic 2 1
168 0a000 0 0 2 &mpic 3 1
169 0a000 0 0 3 &mpic 0 1
170 0a000 0 0 4 &mpic 1 1
171
172 /* IDSEL 0x15 (Slot 4) */
173 0a800 0 0 1 &mpic 3 1
174 0a800 0 0 2 &mpic 0 1
175 0a800 0 0 3 &mpic 1 1
176 0a800 0 0 4 &mpic 2 1
177
178 /* Bus 1 (Tundra Bridge) */
179 /* IDSEL 0x12 (ISA bridge) */
180 19000 0 0 1 &mpic 0 1
181 19000 0 0 2 &mpic 1 1
182 19000 0 0 3 &mpic 2 1
183 19000 0 0 4 &mpic 3 1>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 bus-range = <0 0>;
187 ranges = <02000000 0 80000000 80000000 0 20000000
188 01000000 0 00000000 e2000000 0 00100000>;
189 clock-frequency = <3f940aa>;
190 #interrupt-cells = <1>;
191 #size-cells = <2>;
192 #address-cells = <3>;
193 reg = <8000 1000>;
194 compatible = "fsl,mpc8540-pci";
195 device_type = "pci";
196
197 i8259@19000 {
198 interrupt-controller;
199 device_type = "interrupt-controller";
200 reg = <19000 0 0 0 1>;
201 #address-cells = <0>;
202 #interrupt-cells = <2>;
203 compatible = "chrp,iic";
204 interrupts = <1>;
205 interrupt-parent = <&pci1>;
206 };
207 };
208
209 pci@9000 {
210 interrupt-map-mask = <f800 0 0 7>;
211 interrupt-map = <
212
213 /* IDSEL 0x15 */
214 a800 0 0 1 &mpic b 1
215 a800 0 0 2 &mpic b 1
216 a800 0 0 3 &mpic b 1
217 a800 0 0 4 &mpic b 1>;
218 interrupt-parent = <&mpic>;
219 interrupts = <19 2>;
220 bus-range = <0 0>;
221 ranges = <02000000 0 a0000000 a0000000 0 20000000
222 01000000 0 00000000 e3000000 0 00100000>;
223 clock-frequency = <3f940aa>;
224 #interrupt-cells = <1>;
225 #size-cells = <2>;
226 #address-cells = <3>;
227 reg = <9000 1000>;
228 compatible = "fsl,mpc8540-pci";
229 device_type = "pci";
230 };
231
232 mpic: pic@40000 { 138 mpic: pic@40000 {
233 clock-frequency = <0>; 139 clock-frequency = <0>;
234 interrupt-controller; 140 interrupt-controller;
@@ -240,4 +146,98 @@
240 big-endian; 146 big-endian;
241 }; 147 };
242 }; 148 };
149
150 pci1: pci@e0008000 {
151 interrupt-map-mask = <1f800 0 0 7>;
152 interrupt-map = <
153
154 /* IDSEL 0x10 */
155 08000 0 0 1 &mpic 0 1
156 08000 0 0 2 &mpic 1 1
157 08000 0 0 3 &mpic 2 1
158 08000 0 0 4 &mpic 3 1
159
160 /* IDSEL 0x11 */
161 08800 0 0 1 &mpic 0 1
162 08800 0 0 2 &mpic 1 1
163 08800 0 0 3 &mpic 2 1
164 08800 0 0 4 &mpic 3 1
165
166 /* IDSEL 0x12 (Slot 1) */
167 09000 0 0 1 &mpic 0 1
168 09000 0 0 2 &mpic 1 1
169 09000 0 0 3 &mpic 2 1
170 09000 0 0 4 &mpic 3 1
171
172 /* IDSEL 0x13 (Slot 2) */
173 09800 0 0 1 &mpic 1 1
174 09800 0 0 2 &mpic 2 1
175 09800 0 0 3 &mpic 3 1
176 09800 0 0 4 &mpic 0 1
177
178 /* IDSEL 0x14 (Slot 3) */
179 0a000 0 0 1 &mpic 2 1
180 0a000 0 0 2 &mpic 3 1
181 0a000 0 0 3 &mpic 0 1
182 0a000 0 0 4 &mpic 1 1
183
184 /* IDSEL 0x15 (Slot 4) */
185 0a800 0 0 1 &mpic 3 1
186 0a800 0 0 2 &mpic 0 1
187 0a800 0 0 3 &mpic 1 1
188 0a800 0 0 4 &mpic 2 1
189
190 /* Bus 1 (Tundra Bridge) */
191 /* IDSEL 0x12 (ISA bridge) */
192 19000 0 0 1 &mpic 0 1
193 19000 0 0 2 &mpic 1 1
194 19000 0 0 3 &mpic 2 1
195 19000 0 0 4 &mpic 3 1>;
196 interrupt-parent = <&mpic>;
197 interrupts = <18 2>;
198 bus-range = <0 0>;
199 ranges = <02000000 0 80000000 80000000 0 20000000
200 01000000 0 00000000 e2000000 0 00100000>;
201 clock-frequency = <3f940aa>;
202 #interrupt-cells = <1>;
203 #size-cells = <2>;
204 #address-cells = <3>;
205 reg = <e0008000 1000>;
206 compatible = "fsl,mpc8540-pci";
207 device_type = "pci";
208
209 i8259@19000 {
210 interrupt-controller;
211 device_type = "interrupt-controller";
212 reg = <19000 0 0 0 1>;
213 #address-cells = <0>;
214 #interrupt-cells = <2>;
215 compatible = "chrp,iic";
216 interrupts = <1>;
217 interrupt-parent = <&pci1>;
218 };
219 };
220
221 pci@e0009000 {
222 interrupt-map-mask = <f800 0 0 7>;
223 interrupt-map = <
224
225 /* IDSEL 0x15 */
226 a800 0 0 1 &mpic b 1
227 a800 0 0 2 &mpic b 1
228 a800 0 0 3 &mpic b 1
229 a800 0 0 4 &mpic b 1>;
230 interrupt-parent = <&mpic>;
231 interrupts = <19 2>;
232 bus-range = <0 0>;
233 ranges = <02000000 0 a0000000 a0000000 0 20000000
234 01000000 0 00000000 e3000000 0 00100000>;
235 clock-frequency = <3f940aa>;
236 #interrupt-cells = <1>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 reg = <e0009000 1000>;
240 compatible = "fsl,mpc8540-pci";
241 device_type = "pci";
242 };
243}; 243};
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index cf87c30cf6a8..5577ec1f312b 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -130,96 +130,6 @@
130 phy-handle = <&phy1>; 130 phy-handle = <&phy1>;
131 }; 131 };
132 132
133 pci@8000 {
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
138 device_type = "pci";
139 reg = <8000 1000>;
140 clock-frequency = <3f940aa>;
141 interrupt-map-mask = <f800 0 0 7>;
142 interrupt-map = <
143
144 /* IDSEL 0x2 */
145 1000 0 0 1 &mpic 1 1
146 1000 0 0 2 &mpic 2 1
147 1000 0 0 3 &mpic 3 1
148 1000 0 0 4 &mpic 4 1
149
150 /* IDSEL 0x3 */
151 1800 0 0 1 &mpic 4 1
152 1800 0 0 2 &mpic 1 1
153 1800 0 0 3 &mpic 2 1
154 1800 0 0 4 &mpic 3 1
155
156 /* IDSEL 0x4 */
157 2000 0 0 1 &mpic 3 1
158 2000 0 0 2 &mpic 4 1
159 2000 0 0 3 &mpic 1 1
160 2000 0 0 4 &mpic 2 1
161
162 /* IDSEL 0x5 */
163 2800 0 0 1 &mpic 2 1
164 2800 0 0 2 &mpic 3 1
165 2800 0 0 3 &mpic 4 1
166 2800 0 0 4 &mpic 1 1
167
168 /* IDSEL 12 */
169 6000 0 0 1 &mpic 1 1
170 6000 0 0 2 &mpic 2 1
171 6000 0 0 3 &mpic 3 1
172 6000 0 0 4 &mpic 4 1
173
174 /* IDSEL 13 */
175 6800 0 0 1 &mpic 4 1
176 6800 0 0 2 &mpic 1 1
177 6800 0 0 3 &mpic 2 1
178 6800 0 0 4 &mpic 3 1
179
180 /* IDSEL 14*/
181 7000 0 0 1 &mpic 3 1
182 7000 0 0 2 &mpic 4 1
183 7000 0 0 3 &mpic 1 1
184 7000 0 0 4 &mpic 2 1
185
186 /* IDSEL 15 */
187 7800 0 0 1 &mpic 2 1
188 7800 0 0 2 &mpic 3 1
189 7800 0 0 3 &mpic 4 1
190 7800 0 0 4 &mpic 1 1
191
192 /* IDSEL 18 */
193 9000 0 0 1 &mpic 1 1
194 9000 0 0 2 &mpic 2 1
195 9000 0 0 3 &mpic 3 1
196 9000 0 0 4 &mpic 4 1
197
198 /* IDSEL 19 */
199 9800 0 0 1 &mpic 4 1
200 9800 0 0 2 &mpic 1 1
201 9800 0 0 3 &mpic 2 1
202 9800 0 0 4 &mpic 3 1
203
204 /* IDSEL 20 */
205 a000 0 0 1 &mpic 3 1
206 a000 0 0 2 &mpic 4 1
207 a000 0 0 3 &mpic 1 1
208 a000 0 0 4 &mpic 2 1
209
210 /* IDSEL 21 */
211 a800 0 0 1 &mpic 2 1
212 a800 0 0 2 &mpic 3 1
213 a800 0 0 3 &mpic 4 1
214 a800 0 0 4 &mpic 1 1>;
215
216 interrupt-parent = <&mpic>;
217 interrupts = <18 2>;
218 bus-range = <0 0>;
219 ranges = <02000000 0 80000000 80000000 0 20000000
220 01000000 0 00000000 e2000000 0 01000000>;
221 };
222
223 mpic: pic@40000 { 133 mpic: pic@40000 {
224 interrupt-controller; 134 interrupt-controller;
225 #address-cells = <0>; 135 #address-cells = <0>;
@@ -319,4 +229,94 @@
319 }; 229 };
320 }; 230 };
321 }; 231 };
232
233 pci@e0008000 {
234 #interrupt-cells = <1>;
235 #size-cells = <2>;
236 #address-cells = <3>;
237 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
238 device_type = "pci";
239 reg = <e0008000 1000>;
240 clock-frequency = <3f940aa>;
241 interrupt-map-mask = <f800 0 0 7>;
242 interrupt-map = <
243
244 /* IDSEL 0x2 */
245 1000 0 0 1 &mpic 1 1
246 1000 0 0 2 &mpic 2 1
247 1000 0 0 3 &mpic 3 1
248 1000 0 0 4 &mpic 4 1
249
250 /* IDSEL 0x3 */
251 1800 0 0 1 &mpic 4 1
252 1800 0 0 2 &mpic 1 1
253 1800 0 0 3 &mpic 2 1
254 1800 0 0 4 &mpic 3 1
255
256 /* IDSEL 0x4 */
257 2000 0 0 1 &mpic 3 1
258 2000 0 0 2 &mpic 4 1
259 2000 0 0 3 &mpic 1 1
260 2000 0 0 4 &mpic 2 1
261
262 /* IDSEL 0x5 */
263 2800 0 0 1 &mpic 2 1
264 2800 0 0 2 &mpic 3 1
265 2800 0 0 3 &mpic 4 1
266 2800 0 0 4 &mpic 1 1
267
268 /* IDSEL 12 */
269 6000 0 0 1 &mpic 1 1
270 6000 0 0 2 &mpic 2 1
271 6000 0 0 3 &mpic 3 1
272 6000 0 0 4 &mpic 4 1
273
274 /* IDSEL 13 */
275 6800 0 0 1 &mpic 4 1
276 6800 0 0 2 &mpic 1 1
277 6800 0 0 3 &mpic 2 1
278 6800 0 0 4 &mpic 3 1
279
280 /* IDSEL 14*/
281 7000 0 0 1 &mpic 3 1
282 7000 0 0 2 &mpic 4 1
283 7000 0 0 3 &mpic 1 1
284 7000 0 0 4 &mpic 2 1
285
286 /* IDSEL 15 */
287 7800 0 0 1 &mpic 2 1
288 7800 0 0 2 &mpic 3 1
289 7800 0 0 3 &mpic 4 1
290 7800 0 0 4 &mpic 1 1
291
292 /* IDSEL 18 */
293 9000 0 0 1 &mpic 1 1
294 9000 0 0 2 &mpic 2 1
295 9000 0 0 3 &mpic 3 1
296 9000 0 0 4 &mpic 4 1
297
298 /* IDSEL 19 */
299 9800 0 0 1 &mpic 4 1
300 9800 0 0 2 &mpic 1 1
301 9800 0 0 3 &mpic 2 1
302 9800 0 0 4 &mpic 3 1
303
304 /* IDSEL 20 */
305 a000 0 0 1 &mpic 3 1
306 a000 0 0 2 &mpic 4 1
307 a000 0 0 3 &mpic 1 1
308 a000 0 0 4 &mpic 2 1
309
310 /* IDSEL 21 */
311 a800 0 0 1 &mpic 2 1
312 a800 0 0 2 &mpic 3 1
313 a800 0 0 3 &mpic 4 1
314 a800 0 0 4 &mpic 1 1>;
315
316 interrupt-parent = <&mpic>;
317 interrupts = <18 2>;
318 bus-range = <0 0>;
319 ranges = <02000000 0 80000000 80000000 0 20000000
320 01000000 0 00000000 e2000000 0 01000000>;
321 };
322}; 322};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 4d53d9bc3a9d..f797662212ba 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -53,11 +53,7 @@
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 ranges = <00001000 f8001000 000ff000 56 ranges = <00000000 f8000000 00100000>;
57 80000000 80000000 20000000
58 e2000000 e2000000 00100000
59 a0000000 a0000000 20000000
60 e3000000 e3000000 00100000>;
61 reg = <f8000000 00001000>; // CCSRBAR 57 reg = <f8000000 00001000>; // CCSRBAR
62 bus-frequency = <0>; 58 bus-frequency = <0>;
63 59
@@ -208,50 +204,75 @@
208 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>;
209 }; 205 };
210 206
211 pcie@8000 { 207 mpic: pic@40000 {
212 compatible = "fsl,mpc8641-pcie"; 208 clock-frequency = <0>;
213 device_type = "pci"; 209 interrupt-controller;
214 #interrupt-cells = <1>; 210 #address-cells = <0>;
215 #size-cells = <2>; 211 #interrupt-cells = <2>;
216 #address-cells = <3>; 212 reg = <40000 40000>;
217 reg = <8000 1000>; 213 compatible = "chrp,open-pic";
218 bus-range = <0 ff>; 214 device_type = "open-pic";
219 ranges = <02000000 0 80000000 80000000 0 20000000 215 big-endian;
220 01000000 0 00000000 e2000000 0 00100000>; 216 };
221 clock-frequency = <1fca055>; 217 };
222 interrupt-parent = <&mpic>;
223 interrupts = <18 2>;
224 interrupt-map-mask = <fb00 0 0 0>;
225 interrupt-map = <
226 /* IDSEL 0x11 */
227 8800 0 0 1 &i8259 9 2
228 8800 0 0 2 &i8259 a 2
229 8800 0 0 3 &i8259 b 2
230 8800 0 0 4 &i8259 c 2
231 218
232 /* IDSEL 0x12 */ 219 pcie@f8008000 {
233 9000 0 0 1 &i8259 a 2 220 compatible = "fsl,mpc8641-pcie";
234 9000 0 0 2 &i8259 b 2 221 device_type = "pci";
235 9000 0 0 3 &i8259 c 2 222 #interrupt-cells = <1>;
236 9000 0 0 4 &i8259 9 2 223 #size-cells = <2>;
224 #address-cells = <3>;
225 reg = <f8008000 1000>;
226 bus-range = <0 ff>;
227 ranges = <02000000 0 80000000 80000000 0 20000000
228 01000000 0 00000000 e2000000 0 00100000>;
229 clock-frequency = <1fca055>;
230 interrupt-parent = <&mpic>;
231 interrupts = <18 2>;
232 interrupt-map-mask = <fb00 0 0 0>;
233 interrupt-map = <
234 /* IDSEL 0x11 */
235 8800 0 0 1 &i8259 9 2
236 8800 0 0 2 &i8259 a 2
237 8800 0 0 3 &i8259 b 2
238 8800 0 0 4 &i8259 c 2
237 239
238 // IDSEL 0x1c USB 240 /* IDSEL 0x12 */
239 e000 0 0 0 &i8259 c 2 241 9000 0 0 1 &i8259 a 2
240 e100 0 0 0 &i8259 9 2 242 9000 0 0 2 &i8259 b 2
241 e200 0 0 0 &i8259 a 2 243 9000 0 0 3 &i8259 c 2
242 e300 0 0 0 &i8259 b 2 244 9000 0 0 4 &i8259 9 2
243 245
244 // IDSEL 0x1d Audio 246 // IDSEL 0x1c USB
245 e800 0 0 0 &i8259 6 2 247 e000 0 0 0 &i8259 c 2
248 e100 0 0 0 &i8259 9 2
249 e200 0 0 0 &i8259 a 2
250 e300 0 0 0 &i8259 b 2
246 251
247 // IDSEL 0x1e Legacy 252 // IDSEL 0x1d Audio
248 f000 0 0 0 &i8259 7 2 253 e800 0 0 0 &i8259 6 2
249 f100 0 0 0 &i8259 7 2
250 254
251 // IDSEL 0x1f IDE/SATA 255 // IDSEL 0x1e Legacy
252 f800 0 0 0 &i8259 e 2 256 f000 0 0 0 &i8259 7 2
253 f900 0 0 0 &i8259 5 2 257 f100 0 0 0 &i8259 7 2
254 >; 258
259 // IDSEL 0x1f IDE/SATA
260 f800 0 0 0 &i8259 e 2
261 f900 0 0 0 &i8259 5 2
262 >;
263
264 pcie@0 {
265 reg = <0 0 0 0 0>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 device_type = "pci";
269 ranges = <02000000 0 80000000
270 02000000 0 80000000
271 0 20000000
272
273 01000000 0 00000000
274 01000000 0 00000000
275 0 00100000>;
255 uli1575@0 { 276 uli1575@0 {
256 reg = <0 0 0 0 0>; 277 reg = <0 0 0 0 0>;
257 #size-cells = <2>; 278 #size-cells = <2>;
@@ -262,108 +283,96 @@
262 01000000 0 00000000 283 01000000 0 00000000
263 01000000 0 00000000 284 01000000 0 00000000
264 0 00100000>; 285 0 00100000>;
286 isa@1e {
287 device_type = "isa";
288 #interrupt-cells = <2>;
289 #size-cells = <1>;
290 #address-cells = <2>;
291 reg = <f000 0 0 0 0>;
292 ranges = <1 0 01000000 0 0
293 00001000>;
294 interrupt-parent = <&i8259>;
265 295
266 pci_bridge@0 { 296 i8259: interrupt-controller@20 {
267 reg = <0 0 0 0 0>; 297 reg = <1 20 2
268 #size-cells = <2>; 298 1 a0 2
269 #address-cells = <3>; 299 1 4d0 2>;
270 ranges = <02000000 0 80000000 300 interrupt-controller;
271 02000000 0 80000000 301 device_type = "interrupt-controller";
272 0 20000000 302 #address-cells = <0>;
273 01000000 0 00000000
274 01000000 0 00000000
275 0 00100000>;
276
277 isa@1e {
278 device_type = "isa";
279 #interrupt-cells = <2>; 303 #interrupt-cells = <2>;
280 #size-cells = <1>; 304 compatible = "chrp,iic";
281 #address-cells = <2>; 305 interrupts = <9 2>;
282 reg = <f000 0 0 0 0>; 306 interrupt-parent = <&mpic>;
283 ranges = <1 0 01000000 0 0 307 };
284 00001000>;
285 interrupt-parent = <&i8259>;
286
287 i8259: interrupt-controller@20 {
288 reg = <1 20 2
289 1 a0 2
290 1 4d0 2>;
291 interrupt-controller;
292 device_type = "interrupt-controller";
293 #address-cells = <0>;
294 #interrupt-cells = <2>;
295 compatible = "chrp,iic";
296 interrupts = <9 2>;
297 interrupt-parent =
298 <&mpic>;
299 };
300
301 i8042@60 {
302 #size-cells = <0>;
303 #address-cells = <1>;
304 reg = <1 60 1 1 64 1>;
305 interrupts = <1 3 c 3>;
306 interrupt-parent =
307 <&i8259>;
308 308
309 keyboard@0 { 309 i8042@60 {
310 reg = <0>; 310 #size-cells = <0>;
311 compatible = "pnpPNP,303"; 311 #address-cells = <1>;
312 }; 312 reg = <1 60 1 1 64 1>;
313 interrupts = <1 3 c 3>;
314 interrupt-parent =
315 <&i8259>;
313 316
314 mouse@1 { 317 keyboard@0 {
315 reg = <1>; 318 reg = <0>;
316 compatible = "pnpPNP,f03"; 319 compatible = "pnpPNP,303";
317 };
318 }; 320 };
319 321
320 rtc@70 { 322 mouse@1 {
321 compatible = 323 reg = <1>;
322 "pnpPNP,b00"; 324 compatible = "pnpPNP,f03";
323 reg = <1 70 2>;
324 }; 325 };
326 };
325 327
326 gpio@400 { 328 rtc@70 {
327 reg = <1 400 80>; 329 compatible =
328 }; 330 "pnpPNP,b00";
331 reg = <1 70 2>;
332 };
333
334 gpio@400 {
335 reg = <1 400 80>;
329 }; 336 };
330 }; 337 };
331 }; 338 };
332
333 }; 339 };
334 340
335 pcie@9000 { 341 };
336 compatible = "fsl,mpc8641-pcie"; 342
337 device_type = "pci"; 343 pcie@f8009000 {
338 #interrupt-cells = <1>; 344 compatible = "fsl,mpc8641-pcie";
345 device_type = "pci";
346 #interrupt-cells = <1>;
347 #size-cells = <2>;
348 #address-cells = <3>;
349 reg = <f8009000 1000>;
350 bus-range = <0 ff>;
351 ranges = <02000000 0 a0000000 a0000000 0 20000000
352 01000000 0 00000000 e3000000 0 00100000>;
353 clock-frequency = <1fca055>;
354 interrupt-parent = <&mpic>;
355 interrupts = <19 2>;
356 interrupt-map-mask = <f800 0 0 7>;
357 interrupt-map = <
358 /* IDSEL 0x0 */
359 0000 0 0 1 &mpic 4 1
360 0000 0 0 2 &mpic 5 1
361 0000 0 0 3 &mpic 6 1
362 0000 0 0 4 &mpic 7 1
363 >;
364 pcie@0 {
365 reg = <0 0 0 0 0>;
339 #size-cells = <2>; 366 #size-cells = <2>;
340 #address-cells = <3>; 367 #address-cells = <3>;
341 reg = <9000 1000>; 368 device_type = "pci";
342 bus-range = <0 ff>; 369 ranges = <02000000 0 a0000000
343 ranges = <02000000 0 a0000000 a0000000 0 20000000 370 02000000 0 a0000000
344 01000000 0 00000000 e3000000 0 00100000>; 371 0 20000000
345 clock-frequency = <1fca055>;
346 interrupt-parent = <&mpic>;
347 interrupts = <19 2>;
348 interrupt-map-mask = <f800 0 0 7>;
349 interrupt-map = <
350 /* IDSEL 0x0 */
351 0000 0 0 1 &mpic 4 1
352 0000 0 0 2 &mpic 5 1
353 0000 0 0 3 &mpic 6 1
354 0000 0 0 4 &mpic 7 1
355 >;
356 };
357 372
358 mpic: pic@40000 { 373 01000000 0 00000000
359 clock-frequency = <0>; 374 01000000 0 00000000
360 interrupt-controller; 375 0 00100000>;
361 #address-cells = <0>;
362 #interrupt-cells = <2>;
363 reg = <40000 40000>;
364 compatible = "chrp,open-pic";
365 device_type = "open-pic";
366 big-endian;
367 }; 376 };
368 }; 377 };
369}; 378};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 11:00:35 -0500