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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2012-04-12 02:45:32 -0400
committerPaul Mundt <lethal@linux-sh.org>2012-04-17 03:20:23 -0400
commitfea88a0c02822fbb91a0b8301bf9af04377876a3 (patch)
treef48ab61efdcd32f5d1f574fca3a93b91db8c3d1f /arch
parente00e7cb3b70e8aec5aa732b51394b841c7b4b571 (diff)
sh: Add initial support for SH7734 CPU subtype
This implements initial support for the SH7734. This adds support SCIF, TMU and RTC. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/Kconfig12
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h5
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7734.h306
-rw-r--r--arch/sh/kernel/cpu/proc.c3
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7734.c266
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c800
9 files changed, 1396 insertions, 3 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ff9e033ce626..ed2419f7afe5 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -427,6 +427,16 @@ config CPU_SUBTYPE_SH7724
427 help 427 help
428 Select SH7724 if you have an SH-MobileR2R CPU. 428 Select SH7724 if you have an SH-MobileR2R CPU.
429 429
430config CPU_SUBTYPE_SH7734
431 bool "Support SH7734 processor"
432 select CPU_SH4A
433 select CPU_SHX2
434 select ARCH_WANT_OPTIONAL_GPIOLIB
435 select USB_ARCH_HAS_OHCI
436 select USB_ARCH_HAS_EHCI
437 help
438 Select SH7734 if you have a SH4A SH7734 CPU.
439
430config CPU_SUBTYPE_SH7757 440config CPU_SUBTYPE_SH7757
431 bool "Support SH7757 processor" 441 bool "Support SH7757 processor"
432 select CPU_SH4A 442 select CPU_SH4A
@@ -584,7 +594,7 @@ config SH_CLK_CPG
584config SH_CLK_CPG_LEGACY 594config SH_CLK_CPG_LEGACY
585 depends on SH_CLK_CPG 595 depends on SH_CLK_CPG
586 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ 596 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
587 !CPU_SHX3 && !CPU_SUBTYPE_SH7757 597 !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && !CPU_SUBTYPE_SH7734
588 598
589source "kernel/time/Kconfig" 599source "kernel/time/Kconfig"
590 600
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index a229c393826a..26b12fd8fcbd 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index cffd25ed0240..1631fc238e6f 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -47,6 +47,11 @@
47#define MSTPCR1 0xa4150034 47#define MSTPCR1 0xa4150034
48#define MSTPCR2 0xa4150038 48#define MSTPCR2 0xa4150038
49 49
50#elif defined(CONFIG_CPU_SUBTYPE_SH7734)
51#define FRQCR0 0xffc80000
52#define FRQCR2 0xffc80008
53#define FRQMR1 0xffc80014
54#define FRQMR2 0xffc80018
50#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 55#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
51#define FRQCR0 0xffc80000 56#define FRQCR0 0xffc80000
52#define FRQCR1 0xffc80004 57#define FRQCR1 0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7734.h b/arch/sh/include/cpu-sh4/cpu/sh7734.h
new file mode 100644
index 000000000000..2fb9a7b71b41
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7734.h
@@ -0,0 +1,306 @@
1#ifndef __ASM_SH7734_H__
2#define __ASM_SH7734_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
10 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
11 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
12 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
13 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
14 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
15 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
16 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
17
18 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
19 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
20 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
21 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
22 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
23 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
24 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
25 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
26
27 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
28 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
29 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
30 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
31 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
32 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
33 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
34 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
35
36 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
37 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
38 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
39 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
40 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
41 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
42 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
43 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
44
45 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
46 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
47 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
48 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
49 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
50 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
51 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
52 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
53
54 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
55 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
56 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
57
58 GPIO_FN_CLKOUT, GPIO_FN_BS, GPIO_FN_CS0, GPIO_FN_EX_CS0, GPIO_FN_RD,
59 GPIO_FN_WE0, GPIO_FN_WE1,
60
61 GPIO_FN_SCL0, GPIO_FN_PENC0, GPIO_FN_USB_OVC0,
62
63 GPIO_FN_IRQ2_B, GPIO_FN_IRQ3_B,
64
65 /* IPSR0 */
66 GPIO_FN_A15, GPIO_FN_ST0_VCO_CLKIN, GPIO_FN_LCD_DATA15_A,
67 GPIO_FN_TIOC3D_C,
68 GPIO_FN_A14, GPIO_FN_LCD_DATA14_A, GPIO_FN_TIOC3C_C,
69 GPIO_FN_A13, GPIO_FN_LCD_DATA13_A, GPIO_FN_TIOC3B_C,
70 GPIO_FN_A12, GPIO_FN_LCD_DATA12_A, GPIO_FN_TIOC3A_C,
71 GPIO_FN_A11, GPIO_FN_ST0_D7, GPIO_FN_LCD_DATA11_A,
72 GPIO_FN_TIOC2B_C,
73 GPIO_FN_A10, GPIO_FN_ST0_D6, GPIO_FN_LCD_DATA10_A,
74 GPIO_FN_TIOC2A_C,
75 GPIO_FN_A9, GPIO_FN_ST0_D5, GPIO_FN_LCD_DATA9_A,
76 GPIO_FN_TIOC1B_C,
77 GPIO_FN_A8, GPIO_FN_ST0_D4, GPIO_FN_LCD_DATA8_A,
78 GPIO_FN_TIOC1A_C,
79 GPIO_FN_A7, GPIO_FN_ST0_D3, GPIO_FN_LCD_DATA7_A, GPIO_FN_TIOC0D_C,
80 GPIO_FN_A6, GPIO_FN_ST0_D2, GPIO_FN_LCD_DATA6_A, GPIO_FN_TIOC0C_C,
81 GPIO_FN_A5, GPIO_FN_ST0_D1, GPIO_FN_LCD_DATA5_A, GPIO_FN_TIOC0B_C,
82 GPIO_FN_A4, GPIO_FN_ST0_D0, GPIO_FN_LCD_DATA4_A, GPIO_FN_TIOC0A_C,
83 GPIO_FN_A3, GPIO_FN_ST0_VLD, GPIO_FN_LCD_DATA3_A, GPIO_FN_TCLKD_C,
84 GPIO_FN_A2, GPIO_FN_ST0_SYC, GPIO_FN_LCD_DATA2_A, GPIO_FN_TCLKC_C,
85 GPIO_FN_A1, GPIO_FN_ST0_REQ, GPIO_FN_LCD_DATA1_A, GPIO_FN_TCLKB_C,
86 GPIO_FN_A0, GPIO_FN_ST0_CLKIN, GPIO_FN_LCD_DATA0_A, GPIO_FN_TCLKA_C,
87
88 /* IPSR1 */
89 GPIO_FN_D3, GPIO_FN_SD0_DAT3_A, GPIO_FN_MMC_D3_A, GPIO_FN_ST1_D6,
90 GPIO_FN_FD3_A,
91 GPIO_FN_D2, GPIO_FN_SD0_DAT2_A, GPIO_FN_MMC_D2_A, GPIO_FN_ST1_D5,
92 GPIO_FN_FD2_A,
93 GPIO_FN_D1, GPIO_FN_SD0_DAT1_A, GPIO_FN_MMC_D1_A, GPIO_FN_ST1_D4,
94 GPIO_FN_FD1_A,
95 GPIO_FN_D0, GPIO_FN_SD0_DAT0_A, GPIO_FN_MMC_D0_A, GPIO_FN_ST1_D3,
96 GPIO_FN_FD0_A,
97 GPIO_FN_A25, GPIO_FN_TX2_D, GPIO_FN_ST1_D2,
98 GPIO_FN_A24, GPIO_FN_RX2_D, GPIO_FN_ST1_D1,
99 GPIO_FN_A23, GPIO_FN_ST1_D0, GPIO_FN_LCD_M_DISP_A,
100 GPIO_FN_A22, GPIO_FN_ST1_VLD, GPIO_FN_LCD_VEPWC_A,
101 GPIO_FN_A21, GPIO_FN_ST1_SYC, GPIO_FN_LCD_VCPWC_A,
102 GPIO_FN_A20, GPIO_FN_ST1_REQ, GPIO_FN_LCD_FLM_A,
103 GPIO_FN_A19, GPIO_FN_ST1_CLKIN, GPIO_FN_LCD_CLK_A, GPIO_FN_TIOC4D_C,
104 GPIO_FN_A18, GPIO_FN_ST1_PWM, GPIO_FN_LCD_CL2_A, GPIO_FN_TIOC4C_C,
105 GPIO_FN_A17, GPIO_FN_ST1_VCO_CLKIN, GPIO_FN_LCD_CL1_A, GPIO_FN_TIOC4B_C,
106 GPIO_FN_A16, GPIO_FN_ST0_PWM, GPIO_FN_LCD_DON_A, GPIO_FN_TIOC4A_C,
107
108 /* IPSR2 */
109 GPIO_FN_D14, GPIO_FN_TX2_B, GPIO_FN_FSE_A, GPIO_FN_ET0_TX_CLK_B,
110 GPIO_FN_D13, GPIO_FN_RX2_B, GPIO_FN_FRB_A, GPIO_FN_ET0_ETXD6_B,
111 GPIO_FN_D12, GPIO_FN_FWE_A, GPIO_FN_ET0_ETXD5_B,
112 GPIO_FN_D11, GPIO_FN_RSPI_MISO_A, GPIO_FN_QMI_QIO1_A,
113 GPIO_FN_FRE_A, GPIO_FN_ET0_ETXD3_B,
114 GPIO_FN_D10, GPIO_FN_RSPI_MOSI_A, GPIO_FN_QMO_QIO0_A,
115 GPIO_FN_FALE_A, GPIO_FN_ET0_ETXD2_B,
116 GPIO_FN_D9, GPIO_FN_SD0_CMD_A, GPIO_FN_MMC_CMD_A, GPIO_FN_QIO3_A,
117 GPIO_FN_FCLE_A, GPIO_FN_ET0_ETXD1_B,
118 GPIO_FN_D8, GPIO_FN_SD0_CLK_A, GPIO_FN_MMC_CLK_A, GPIO_FN_QIO2_A,
119 GPIO_FN_FCE_A, GPIO_FN_ET0_GTX_CLK_B,
120 GPIO_FN_D7, GPIO_FN_RSPI_SSL_A, GPIO_FN_MMC_D7_A, GPIO_FN_QSSL_A,
121 GPIO_FN_FD7_A,
122 GPIO_FN_D6, GPIO_FN_RSPI_RSPCK_A, GPIO_FN_MMC_D6_A, GPIO_FN_QSPCLK_A,
123 GPIO_FN_FD6_A,
124 GPIO_FN_D5, GPIO_FN_SD0_WP_A, GPIO_FN_MMC_D5_A, GPIO_FN_FD5_A,
125 GPIO_FN_D4, GPIO_FN_SD0_CD_A, GPIO_FN_MMC_D4_A, GPIO_FN_ST1_D7,
126 GPIO_FN_FD4_A,
127
128 /* IPSR3 */
129 GPIO_FN_DRACK0, GPIO_FN_SD1_DAT2_A, GPIO_FN_ATAG, GPIO_FN_TCLK1_A,
130 GPIO_FN_ET0_ETXD7,
131 GPIO_FN_EX_WAIT2, GPIO_FN_SD1_DAT1_A, GPIO_FN_DACK2, GPIO_FN_CAN1_RX_C,
132 GPIO_FN_ET0_MAGIC_C, GPIO_FN_ET0_ETXD6_A,
133 GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
134 GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
135 GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
136 GPIO_FN_RD_WR, GPIO_FN_TCLK0,
137 GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
138 GPIO_FN_ET0_ETXD3_A,
139 GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
140 GPIO_FN_ET0_ETXD2_A,
141 GPIO_FN_EX_CS3, GPIO_FN_SD1_CD_A, GPIO_FN_ATARD, GPIO_FN_QMO_QIO0_B,
142 GPIO_FN_ET0_ETXD1_A,
143 GPIO_FN_EX_CS2, GPIO_FN_TX3_B, GPIO_FN_ATACS1, GPIO_FN_QSPCLK_B,
144 GPIO_FN_ET0_GTX_CLK_A,
145 GPIO_FN_EX_CS1, GPIO_FN_RX3_B, GPIO_FN_ATACS0, GPIO_FN_QIO2_B,
146 GPIO_FN_ET0_ETXD0,
147 GPIO_FN_CS1_A26, GPIO_FN_QIO3_B,
148 GPIO_FN_D15, GPIO_FN_SCK2_B,
149
150 /* IPSR4 */
151 GPIO_FN_SCK2_A, GPIO_FN_VI0_G3,
152 GPIO_FN_RTS1_B, GPIO_FN_VI0_G2,
153 GPIO_FN_CTS1_B, GPIO_FN_VI0_DATA7_VI0_G1,
154 GPIO_FN_TX1_B, GPIO_FN_VI0_DATA6_VI0_G0, GPIO_FN_ET0_PHY_INT_A,
155 GPIO_FN_RX1_B, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_ET0_MAGIC_A,
156 GPIO_FN_SCK1_B, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ET0_LINK_A,
157 GPIO_FN_RTS0_B, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ET0_MDIO_A,
158 GPIO_FN_CTS0_B, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_RMII0_MDIO_A,
159 GPIO_FN_ET0_MDC,
160 GPIO_FN_HTX0_A, GPIO_FN_TX1_A, GPIO_FN_VI0_DATA1_VI0_B1,
161 GPIO_FN_RMII0_MDC_A, GPIO_FN_ET0_COL,
162 GPIO_FN_HRX0_A, GPIO_FN_RX1_A, GPIO_FN_VI0_DATA0_VI0_B0,
163 GPIO_FN_RMII0_CRS_DV_A, GPIO_FN_ET0_CRS,
164 GPIO_FN_HSCK0_A, GPIO_FN_SCK1_A, GPIO_FN_VI0_VSYNC,
165 GPIO_FN_RMII0_RX_ER_A, GPIO_FN_ET0_RX_ER,
166 GPIO_FN_HRTS0_A, GPIO_FN_RTS1_A, GPIO_FN_VI0_HSYNC,
167 GPIO_FN_RMII0_TXD_EN_A, GPIO_FN_ET0_RX_DV,
168 GPIO_FN_HCTS0_A, GPIO_FN_CTS1_A, GPIO_FN_VI0_FIELD,
169 GPIO_FN_RMII0_RXD1_A, GPIO_FN_ET0_ERXD7,
170
171 /* IPSR5 */
172 GPIO_FN_SD2_CLK_A, GPIO_FN_RX2_A, GPIO_FN_VI0_G4, GPIO_FN_ET0_RX_CLK_B,
173 GPIO_FN_SD2_CMD_A, GPIO_FN_TX2_A, GPIO_FN_VI0_G5, GPIO_FN_ET0_ERXD2_B,
174 GPIO_FN_SD2_DAT0_A, GPIO_FN_RX3_A, GPIO_FN_VI0_R0, GPIO_FN_ET0_ERXD3_B,
175 GPIO_FN_SD2_DAT1_A, GPIO_FN_TX3_A, GPIO_FN_VI0_R1, GPIO_FN_ET0_MDIO_B,
176 GPIO_FN_SD2_DAT2_A, GPIO_FN_RX4_A, GPIO_FN_VI0_R2, GPIO_FN_ET0_LINK_B,
177 GPIO_FN_SD2_DAT3_A, GPIO_FN_TX4_A, GPIO_FN_VI0_R3, GPIO_FN_ET0_MAGIC_B,
178 GPIO_FN_SD2_CD_A, GPIO_FN_RX5_A, GPIO_FN_VI0_R4, GPIO_FN_ET0_PHY_INT_B,
179 GPIO_FN_SD2_WP_A, GPIO_FN_TX5_A, GPIO_FN_VI0_R5,
180 GPIO_FN_REF125CK, GPIO_FN_ADTRG, GPIO_FN_RX5_C,
181 GPIO_FN_REF50CK, GPIO_FN_CTS1_E, GPIO_FN_HCTS0_D,
182
183 /* IPSR6 */
184 GPIO_FN_DU0_DR0, GPIO_FN_SCIF_CLK_B, GPIO_FN_HRX0_D, GPIO_FN_IETX_A,
185 GPIO_FN_TCLKA_A, GPIO_FN_HIFD00,
186 GPIO_FN_DU0_DR1, GPIO_FN_SCK0_B, GPIO_FN_HTX0_D, GPIO_FN_IERX_A,
187 GPIO_FN_TCLKB_A, GPIO_FN_HIFD01,
188 GPIO_FN_DU0_DR2, GPIO_FN_RX0_B, GPIO_FN_TCLKC_A, GPIO_FN_HIFD02,
189 GPIO_FN_DU0_DR3, GPIO_FN_TX0_B, GPIO_FN_TCLKD_A, GPIO_FN_HIFD03,
190 GPIO_FN_DU0_DR4, GPIO_FN_CTS0_C, GPIO_FN_TIOC0A_A, GPIO_FN_HIFD04,
191 GPIO_FN_DU0_DR5, GPIO_FN_RTS0_C, GPIO_FN_TIOC0B_A, GPIO_FN_HIFD05,
192 GPIO_FN_DU0_DR6, GPIO_FN_SCK1_C, GPIO_FN_TIOC0C_A, GPIO_FN_HIFD06,
193 GPIO_FN_DU0_DR7, GPIO_FN_RX1_C, GPIO_FN_TIOC0D_A, GPIO_FN_HIFD07,
194 GPIO_FN_DU0_DG0, GPIO_FN_TX1_C, GPIO_FN_HSCK0_D, GPIO_FN_IECLK_A,
195 GPIO_FN_TIOC1A_A, GPIO_FN_HIFD08,
196 GPIO_FN_DU0_DG1, GPIO_FN_CTS1_C, GPIO_FN_HRTS0_D, GPIO_FN_TIOC1B_A,
197 GPIO_FN_HIFD09,
198
199 /* IPSR7 */
200 GPIO_FN_DU0_DG2, GPIO_FN_RTS1_C, GPIO_FN_RMII0_MDC_B, GPIO_FN_TIOC2A_A,
201 GPIO_FN_HIFD10,
202 GPIO_FN_DU0_DG3, GPIO_FN_SCK2_C, GPIO_FN_RMII0_MDIO_B, GPIO_FN_TIOC2B_A,
203 GPIO_FN_HIFD11,
204 GPIO_FN_DU0_DG4, GPIO_FN_RX2_C, GPIO_FN_RMII0_CRS_DV_B,
205 GPIO_FN_TIOC3A_A, GPIO_FN_HIFD12,
206 GPIO_FN_DU0_DG5, GPIO_FN_TX2_C, GPIO_FN_RMII0_RX_ER_B,
207 GPIO_FN_TIOC3B_A, GPIO_FN_HIFD13,
208 GPIO_FN_DU0_DG6, GPIO_FN_RX3_C, GPIO_FN_RMII0_RXD0_B,
209 GPIO_FN_TIOC3C_A, GPIO_FN_HIFD14,
210 GPIO_FN_DU0_DG7, GPIO_FN_TX3_C, GPIO_FN_RMII0_RXD1_B,
211 GPIO_FN_TIOC3D_A, GPIO_FN_HIFD15,
212 GPIO_FN_DU0_DB0, GPIO_FN_RX4_C, GPIO_FN_RMII0_TXD_EN_B,
213 GPIO_FN_TIOC4A_A, GPIO_FN_HIFCS,
214 GPIO_FN_DU0_DB1, GPIO_FN_TX4_C, GPIO_FN_RMII0_TXD0_B,
215 GPIO_FN_TIOC4B_A, GPIO_FN_HIFRS,
216 GPIO_FN_DU0_DB2, GPIO_FN_RX5_B, GPIO_FN_RMII0_TXD1_B,
217 GPIO_FN_TIOC4C_A, GPIO_FN_HIFWR,
218 GPIO_FN_DU0_DB3, GPIO_FN_TX5_B, GPIO_FN_TIOC4D_A, GPIO_FN_HIFRD,
219 GPIO_FN_DU0_DB4, GPIO_FN_HIFINT,
220
221 /* IPSR8 */
222 GPIO_FN_DU0_DB5, GPIO_FN_HIFDREQ,
223 GPIO_FN_DU0_DB6, GPIO_FN_HIFRDY,
224 GPIO_FN_DU0_DB7, GPIO_FN_SSI_SCK0_B, GPIO_FN_HIFEBL_B,
225 GPIO_FN_DU0_DOTCLKIN, GPIO_FN_HSPI_CS0_C, GPIO_FN_SSI_WS0_B,
226 GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_HSPI_CLK0_C, GPIO_FN_SSI_SDATA0_B,
227 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_HSPI_TX0_C, GPIO_FN_SSI_SCK1_B,
228 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_HSPI_RX0_C, GPIO_FN_SSI_WS1_B,
229 GPIO_FN_DU0_EXODDF_DU0_ODDF, GPIO_FN_CAN0_RX_B, GPIO_FN_HSCK0_B,
230 GPIO_FN_SSI_SDATA1_B,
231 GPIO_FN_DU0_DISP, GPIO_FN_CAN0_TX_B, GPIO_FN_HRX0_B,
232 GPIO_FN_AUDIO_CLKA_B,
233 GPIO_FN_DU0_CDE, GPIO_FN_HTX0_B, GPIO_FN_AUDIO_CLKB_B,
234 GPIO_FN_LCD_VCPWC_B,
235 GPIO_FN_IRQ0_A, GPIO_FN_HSPI_TX_B, GPIO_FN_RX3_E, GPIO_FN_ET0_ERXD0,
236 GPIO_FN_IRQ1_A, GPIO_FN_HSPI_RX_B, GPIO_FN_TX3_E, GPIO_FN_ET0_ERXD1,
237 GPIO_FN_IRQ2_A, GPIO_FN_CTS0_A, GPIO_FN_HCTS0_B, GPIO_FN_ET0_ERXD2_A,
238 GPIO_FN_IRQ3_A, GPIO_FN_RTS0_A, GPIO_FN_HRTS0_B, GPIO_FN_ET0_ERXD3_A,
239
240 /* IPSR9 */
241 GPIO_FN_VI1_CLK_A, GPIO_FN_FD0_B, GPIO_FN_LCD_DATA0_B,
242 GPIO_FN_VI1_0_A, GPIO_FN_FD1_B, GPIO_FN_LCD_DATA1_B,
243 GPIO_FN_VI1_1_A, GPIO_FN_FD2_B, GPIO_FN_LCD_DATA2_B,
244 GPIO_FN_VI1_2_A, GPIO_FN_FD3_B, GPIO_FN_LCD_DATA3_B,
245 GPIO_FN_VI1_3_A, GPIO_FN_FD4_B, GPIO_FN_LCD_DATA4_B,
246 GPIO_FN_VI1_4_A, GPIO_FN_FD5_B, GPIO_FN_LCD_DATA5_B,
247 GPIO_FN_VI1_5_A, GPIO_FN_FD6_B, GPIO_FN_LCD_DATA6_B,
248 GPIO_FN_VI1_6_A, GPIO_FN_FD7_B, GPIO_FN_LCD_DATA7_B,
249 GPIO_FN_VI1_7_A, GPIO_FN_FCE_B, GPIO_FN_LCD_DATA8_B,
250 GPIO_FN_SSI_SCK0_A, GPIO_FN_TIOC1A_B, GPIO_FN_LCD_DATA9_B,
251 GPIO_FN_SSI_WS0_A, GPIO_FN_TIOC1B_B, GPIO_FN_LCD_DATA10_B,
252 GPIO_FN_SSI_SDATA0_A, GPIO_FN_VI1_0_B, GPIO_FN_TIOC2A_B,
253 GPIO_FN_LCD_DATA11_B,
254 GPIO_FN_SSI_SCK1_A, GPIO_FN_VI1_1_B, GPIO_FN_TIOC2B_B,
255 GPIO_FN_LCD_DATA12_B,
256 GPIO_FN_SSI_WS1_A, GPIO_FN_VI1_2_B, GPIO_FN_LCD_DATA13_B,
257 GPIO_FN_SSI_SDATA1_A, GPIO_FN_VI1_3_B, GPIO_FN_LCD_DATA14_B,
258
259 /* IPSR10 */
260 GPIO_FN_SSI_SCK23, GPIO_FN_VI1_4_B, GPIO_FN_RX1_D, GPIO_FN_FCLE_B,
261 GPIO_FN_LCD_DATA15_B,
262 GPIO_FN_SSI_WS23, GPIO_FN_VI1_5_B, GPIO_FN_TX1_D, GPIO_FN_HSCK0_C,
263 GPIO_FN_FALE_B, GPIO_FN_LCD_DON_B,
264 GPIO_FN_SSI_SDATA2, GPIO_FN_VI1_6_B, GPIO_FN_HRX0_C, GPIO_FN_FRE_B,
265 GPIO_FN_LCD_CL1_B,
266 GPIO_FN_SSI_SDATA3, GPIO_FN_VI1_7_B, GPIO_FN_HTX0_C, GPIO_FN_FWE_B,
267 GPIO_FN_LCD_CL2_B,
268 GPIO_FN_AUDIO_CLKA_A, GPIO_FN_VI1_CLK_B, GPIO_FN_SCK1_D,
269 GPIO_FN_IECLK_B, GPIO_FN_LCD_FLM_B,
270 GPIO_FN_AUDIO_CLKB_A, GPIO_FN_LCD_CLK_B,
271 GPIO_FN_AUDIO_CLKC, GPIO_FN_SCK1_E, GPIO_FN_HCTS0_C, GPIO_FN_FRB_B,
272 GPIO_FN_LCD_VEPWC_B,
273 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_TX1_E, GPIO_FN_HRTS0_C, GPIO_FN_FSE_B,
274 GPIO_FN_LCD_M_DISP_B,
275 GPIO_FN_CAN_CLK_A, GPIO_FN_RX4_D,
276 GPIO_FN_CAN0_TX_A, GPIO_FN_TX4_D, GPIO_FN_MLB_CLK,
277 GPIO_FN_CAN1_RX_A, GPIO_FN_IRQ1_B,
278 GPIO_FN_CAN0_RX_A, GPIO_FN_IRQ0_B, GPIO_FN_MLB_SIG,
279 GPIO_FN_CAN1_TX_A, GPIO_FN_TX5_C, GPIO_FN_MLB_DAT,
280
281 /* IPSR11 */
282 GPIO_FN_SCL1, GPIO_FN_SCIF_CLK_C,
283 GPIO_FN_SDA1, GPIO_FN_RX1_E,
284 GPIO_FN_SDA0, GPIO_FN_HIFEBL_A,
285 GPIO_FN_SDSELF, GPIO_FN_RTS1_E,
286 GPIO_FN_SCIF_CLK_A, GPIO_FN_HSPI_CLK_A, GPIO_FN_VI0_CLK,
287 GPIO_FN_RMII0_TXD0_A, GPIO_FN_ET0_ERXD4,
288 GPIO_FN_SCK0_A, GPIO_FN_HSPI_CS_A, GPIO_FN_VI0_CLKENB,
289 GPIO_FN_RMII0_TXD1_A, GPIO_FN_ET0_ERXD5,
290 GPIO_FN_RX0_A, GPIO_FN_HSPI_RX_A, GPIO_FN_RMII0_RXD0_A,
291 GPIO_FN_ET0_ERXD6,
292 GPIO_FN_TX0_A, GPIO_FN_HSPI_TX_A,
293 GPIO_FN_PENC1, GPIO_FN_TX3_D, GPIO_FN_CAN1_TX_B, GPIO_FN_TX5_D,
294 GPIO_FN_IETX_B,
295 GPIO_FN_USB_OVC1, GPIO_FN_RX3_D, GPIO_FN_CAN1_RX_B, GPIO_FN_RX5_D,
296 GPIO_FN_IERX_B,
297 GPIO_FN_DREQ0, GPIO_FN_SD1_CLK_A, GPIO_FN_ET0_TX_EN,
298 GPIO_FN_DACK0, GPIO_FN_SD1_DAT3_A, GPIO_FN_ET0_TX_ER,
299 GPIO_FN_DREQ1, GPIO_FN_HSPI_CLK_B, GPIO_FN_RX4_B, GPIO_FN_ET0_PHY_INT_C,
300 GPIO_FN_ET0_TX_CLK_A,
301 GPIO_FN_DACK1, GPIO_FN_HSPI_CS_B, GPIO_FN_TX4_B, GPIO_FN_ET0_RX_CLK_A,
302 GPIO_FN_PRESETOUT, GPIO_FN_ST_CLKOUT,
303
304};
305
306#endif /* __ASM_SH7734_H__ */
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
index f47be8727b3b..e3a16d104528 100644
--- a/arch/sh/kernel/cpu/proc.c
+++ b/arch/sh/kernel/cpu/proc.c
@@ -25,7 +25,8 @@ static const char *cpu_name[] = {
25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724", 27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
28 [CPU_SH7372] = "SH7372", [CPU_SH_NONE] = "Unknown" 28 [CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
29 [CPU_SH_NONE] = "Unknown"
29}; 30};
30 31
31const char *get_cpu_subtype(struct sh_cpuinfo *c) 32const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 971cf0fce4f5..0fbbd50bc8ad 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -158,6 +158,9 @@ void __cpuinit cpu_probe(void)
158 case 0x40: /* yon-ten-go */ 158 case 0x40: /* yon-ten-go */
159 boot_cpu_data.type = CPU_SH7372; 159 boot_cpu_data.type = CPU_SH7372;
160 break; 160 break;
161 case 0xE0: /* 0x4E0 */
162 boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */
163 break;
161 164
162 } 165 }
163 break; 166 break;
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 0b22d108f4c5..ed71c3f197c8 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7734) += setup-sh7734.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 17obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o 18obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
18 19
@@ -30,6 +31,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
34clock-$(CONFIG_CPU_SUBTYPE_SH7734) := clock-sh7734.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 35clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 36clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 37
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
new file mode 100644
index 000000000000..1697642c1f73
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
@@ -0,0 +1,266 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7734.c
3 *
4 * Clock framework for SH7734
5 *
6 * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * Copyright (C) 2011, 2012 Renesas Solutions Corp.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/clkdev.h>
18#include <linux/delay.h>
19#include <asm/clock.h>
20#include <asm/freq.h>
21
22static struct clk extal_clk = {
23 .rate = 33333333,
24};
25
26#define MODEMR (0xFFCC0020)
27#define MODEMR_MASK (0x6)
28#define MODEMR_533MHZ (0x2)
29
30static unsigned long pll_recalc(struct clk *clk)
31{
32 int mode = 12;
33 u32 r = __raw_readl(MODEMR);
34
35 if ((r & MODEMR_MASK) & MODEMR_533MHZ)
36 mode = 16;
37
38 return clk->parent->rate * mode;
39}
40
41static struct sh_clk_ops pll_clk_ops = {
42 .recalc = pll_recalc,
43};
44
45static struct clk pll_clk = {
46 .ops = &pll_clk_ops,
47 .parent = &extal_clk,
48 .flags = CLK_ENABLE_ON_INIT,
49};
50
51static struct clk *main_clks[] = {
52 &extal_clk,
53 &pll_clk,
54};
55
56static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
57static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 };
58
59static struct clk_div_mult_table div4_div_mult_table = {
60 .divisors = divisors,
61 .nr_divisors = ARRAY_SIZE(divisors),
62 .multipliers = multipliers,
63 .nr_multipliers = ARRAY_SIZE(multipliers),
64};
65
66static struct clk_div4_table div4_table = {
67 .div_mult_table = &div4_div_mult_table,
68};
69
70enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR };
71
72#define DIV4(_reg, _bit, _mask, _flags) \
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
74
75struct clk div4_clks[DIV4_NR] = {
76 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
77 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
78 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
79 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
80 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
81 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
82};
83
84#define MSTPCR0 0xFFC80030
85#define MSTPCR1 0xFFC80034
86#define MSTPCR3 0xFFC8003C
87
88enum {
89 MSTP030, MSTP029, /* IIC */
90 MSTP026, MSTP025, MSTP024, /* SCIF */
91 MSTP023,
92 MSTP022, MSTP021,
93 MSTP019, /* HSCIF */
94 MSTP016, MSTP015, MSTP014, /* TMU / TIMER */
95 MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */
96 MSTP007, /* HSPI */
97 MSTP115, /* ADMAC */
98 MSTP114, /* GETHER */
99 MSTP111, /* DMAC */
100 MSTP109, /* VIDEOIN1 */
101 MSTP108, /* VIDEOIN0 */
102 MSTP107, /* RGPVBG */
103 MSTP106, /* 2DG */
104 MSTP103, /* VIEW */
105 MSTP100, /* USB */
106 MSTP331, /* MMC */
107 MSTP330, /* MIMLB */
108 MSTP323, /* SDHI0 */
109 MSTP322, /* SDHI1 */
110 MSTP321, /* SDHI2 */
111 MSTP320, /* RQSPI */
112 MSTP319, /* SRC0 */
113 MSTP318, /* SRC1 */
114 MSTP317, /* RSPI */
115 MSTP316, /* RCAN0 */
116 MSTP315, /* RCAN1 */
117 MSTP314, /* FLTCL */
118 MSTP313, /* ADC */
119 MSTP312, /* MTU */
120 MSTP304, /* IE-BUS */
121 MSTP303, /* RTC */
122 MSTP302, /* HIF */
123 MSTP301, /* STIF0 */
124 MSTP300, /* STIF1 */
125 MSTP_NR };
126
127static struct clk mstp_clks[MSTP_NR] = {
128 /* MSTPCR0 */
129 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
130 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
131 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
132 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
133 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
134 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
135 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
136 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
137 [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
138 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
139 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
140 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
141 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
142 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
143 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
144 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
145 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
146 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
147
148 /* MSTPCR1 */
149 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
150 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
151 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
152 [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
153 [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
154 [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
155 [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
156 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
157 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
158
159 /* MSTPCR3 */
160 [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
161 [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
162 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
163 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
164 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
165 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
166 [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
167 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
168 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
169 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
170 [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
171 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
172 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
173 [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
174 [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0),
175 [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0),
176 [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0),
177 [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0),
178 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0),
179};
180
181static struct clk_lookup lookups[] = {
182 /* main clocks */
183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("pll_clk", &pll_clk),
185
186 /* clocks */
187 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
188 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
189 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
190 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
191 CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
192 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
193
194 /* MSTP32 clocks */
195 CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]),
196 CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]),
197 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP026]),
198 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
199 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP024]),
200 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP023]),
201 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP022]),
202 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP021]),
203 CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
204 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP016]),
205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP016]),
206 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP016]),
207 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP015]),
208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP015]),
209 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP015]),
210 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP014]),
211 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP014]),
212 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP014]),
213 CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]),
214 CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]),
215 CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]),
216 CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]),
217 CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]),
218 CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]),
219 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]),
220 CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]),
221 CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]),
222 CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]),
223 CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]),
224 CLKDEV_CON_ID("view", &mstp_clks[MSTP103]),
225
226 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]),
227 CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]),
228 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]),
229 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]),
230 CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]),
231 CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]),
232 CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]),
233 CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]),
234 CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]),
235 CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]),
236 CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]),
237 CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]),
238 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]),
239 CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]),
240 CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]),
241 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[MSTP114]),
242 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]),
243 CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]),
244 CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]),
245 CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]),
246};
247
248int __init arch_clk_init(void)
249{
250 int i, ret = 0;
251
252 for (i = 0; i < ARRAY_SIZE(main_clks); i++)
253 ret |= clk_register(main_clks[i]);
254
255 for (i = 0; i < ARRAY_SIZE(lookups); i++)
256 clkdev_add(&lookups[i]);
257
258 if (!ret)
259 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
260 &div4_table);
261
262 if (!ret)
263 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
264
265 return ret;
266}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
new file mode 100644
index 000000000000..f799971d453c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -0,0 +1,800 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/setup-sh7734.c
3
4 * SH7734 Setup
5 *
6 * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * Copyright (C) 2011,2012 Renesas Solutions Corp.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/mm.h>
18#include <linux/dma-mapping.h>
19#include <linux/serial_sci.h>
20#include <linux/sh_timer.h>
21#include <linux/io.h>
22#include <asm/clock.h>
23#include <asm/irq.h>
24#include <cpu/sh7734.h>
25
26/* SCIF */
27static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xFFE40000,
29 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF,
33 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34 .regtype = SCIx_SH4_SCIF_REGTYPE,
35};
36
37static struct platform_device scif0_device = {
38 .name = "sh-sci",
39 .id = 0,
40 .dev = {
41 .platform_data = &scif0_platform_data,
42 },
43};
44
45static struct plat_sci_port scif1_platform_data = {
46 .mapbase = 0xFFE41000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52 .regtype = SCIx_SH4_SCIF_REGTYPE,
53};
54
55static struct platform_device scif1_device = {
56 .name = "sh-sci",
57 .id = 1,
58 .dev = {
59 .platform_data = &scif1_platform_data,
60 },
61};
62
63static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xFFE42000,
65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70 .regtype = SCIx_SH4_SCIF_REGTYPE,
71};
72
73static struct platform_device scif2_device = {
74 .name = "sh-sci",
75 .id = 2,
76 .dev = {
77 .platform_data = &scif2_platform_data,
78 },
79};
80
81static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xFFE43000,
83 .flags = UPF_BOOT_AUTOCONF,
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2,
86 .type = PORT_SCIF,
87 .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88 .regtype = SCIx_SH4_SCIF_REGTYPE,
89};
90
91static struct platform_device scif3_device = {
92 .name = "sh-sci",
93 .id = 3,
94 .dev = {
95 .platform_data = &scif3_platform_data,
96 },
97};
98
99static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xFFE44000,
101 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103 .scbrr_algo_id = SCBRR_ALGO_2,
104 .type = PORT_SCIF,
105 .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106 .regtype = SCIx_SH4_SCIF_REGTYPE,
107};
108
109static struct platform_device scif4_device = {
110 .name = "sh-sci",
111 .id = 4,
112 .dev = {
113 .platform_data = &scif4_platform_data,
114 },
115};
116
117static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xFFE43000,
119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121 .scbrr_algo_id = SCBRR_ALGO_2,
122 .type = PORT_SCIF,
123 .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124 .regtype = SCIx_SH4_SCIF_REGTYPE,
125};
126
127static struct platform_device scif5_device = {
128 .name = "sh-sci",
129 .id = 5,
130 .dev = {
131 .platform_data = &scif5_platform_data,
132 },
133};
134
135/* RTC */
136static struct resource rtc_resources[] = {
137 [0] = {
138 .name = "rtc",
139 .start = 0xFFFC5000,
140 .end = 0xFFFC5000 + 0x26 - 1,
141 .flags = IORESOURCE_IO,
142 },
143 [1] = {
144 .start = evt2irq(0xC00),
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct platform_device rtc_device = {
150 .name = "sh-rtc",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(rtc_resources),
153 .resource = rtc_resources,
154};
155
156/* I2C 0 */
157static struct resource i2c0_resources[] = {
158 [0] = {
159 .name = "IIC0",
160 .start = 0xFFC70000,
161 .end = 0xFFC7000A - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 [1] = {
165 .start = evt2irq(0x860),
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170static struct platform_device i2c0_device = {
171 .name = "i2c-sh7734",
172 .id = 0,
173 .num_resources = ARRAY_SIZE(i2c0_resources),
174 .resource = i2c0_resources,
175};
176
177/* TMU */
178static struct sh_timer_config tmu0_platform_data = {
179 .channel_offset = 0x04,
180 .timer_bit = 0,
181 .clockevent_rating = 200,
182};
183
184static struct resource tmu0_resources[] = {
185 [0] = {
186 .start = 0xFFD80008,
187 .end = 0xFFD80014 - 1,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = evt2irq(0x400),
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196static struct platform_device tmu0_device = {
197 .name = "sh_tmu",
198 .id = 0,
199 .dev = {
200 .platform_data = &tmu0_platform_data,
201 },
202 .resource = tmu0_resources,
203 .num_resources = ARRAY_SIZE(tmu0_resources),
204};
205
206static struct sh_timer_config tmu1_platform_data = {
207 .channel_offset = 0x10,
208 .timer_bit = 1,
209 .clocksource_rating = 200,
210};
211
212static struct resource tmu1_resources[] = {
213 [0] = {
214 .start = 0xFFD80014,
215 .end = 0xFFD80020 - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = evt2irq(0x420),
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device tmu1_device = {
225 .name = "sh_tmu",
226 .id = 1,
227 .dev = {
228 .platform_data = &tmu1_platform_data,
229 },
230 .resource = tmu1_resources,
231 .num_resources = ARRAY_SIZE(tmu1_resources),
232};
233
234static struct sh_timer_config tmu2_platform_data = {
235 .channel_offset = 0x1c,
236 .timer_bit = 2,
237};
238
239static struct resource tmu2_resources[] = {
240 [0] = {
241 .start = 0xFFD80020,
242 .end = 0xFFD80030 - 1,
243 .flags = IORESOURCE_MEM,
244 },
245 [1] = {
246 .start = evt2irq(0x440),
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static struct platform_device tmu2_device = {
252 .name = "sh_tmu",
253 .id = 2,
254 .dev = {
255 .platform_data = &tmu2_platform_data,
256 },
257 .resource = tmu2_resources,
258 .num_resources = ARRAY_SIZE(tmu2_resources),
259};
260
261
262static struct sh_timer_config tmu3_platform_data = {
263 .channel_offset = 0x04,
264 .timer_bit = 0,
265};
266
267static struct resource tmu3_resources[] = {
268 [0] = {
269 .start = 0xFFD81008,
270 .end = 0xFFD81014 - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = evt2irq(0x480),
275 .flags = IORESOURCE_IRQ,
276 },
277};
278
279static struct platform_device tmu3_device = {
280 .name = "sh_tmu",
281 .id = 3,
282 .dev = {
283 .platform_data = &tmu3_platform_data,
284 },
285 .resource = tmu3_resources,
286 .num_resources = ARRAY_SIZE(tmu3_resources),
287};
288
289static struct sh_timer_config tmu4_platform_data = {
290 .channel_offset = 0x10,
291 .timer_bit = 1,
292};
293
294static struct resource tmu4_resources[] = {
295 [0] = {
296 .start = 0xFFD81014,
297 .end = 0xFFD81020 - 1,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = evt2irq(0x4A0),
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu4_device = {
307 .name = "sh_tmu",
308 .id = 4,
309 .dev = {
310 .platform_data = &tmu4_platform_data,
311 },
312 .resource = tmu4_resources,
313 .num_resources = ARRAY_SIZE(tmu4_resources),
314};
315
316static struct sh_timer_config tmu5_platform_data = {
317 .channel_offset = 0x1c,
318 .timer_bit = 2,
319};
320
321static struct resource tmu5_resources[] = {
322 [0] = {
323 .start = 0xFFD81020,
324 .end = 0xFFD81030 - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = evt2irq(0x4C0),
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333static struct platform_device tmu5_device = {
334 .name = "sh_tmu",
335 .id = 5,
336 .dev = {
337 .platform_data = &tmu5_platform_data,
338 },
339 .resource = tmu5_resources,
340 .num_resources = ARRAY_SIZE(tmu5_resources),
341};
342
343static struct sh_timer_config tmu6_platform_data = {
344 .channel_offset = 0x4,
345 .timer_bit = 0,
346};
347
348static struct resource tmu6_resources[] = {
349 [0] = {
350 .start = 0xFFD82008,
351 .end = 0xFFD82014 - 1,
352 .flags = IORESOURCE_MEM,
353 },
354 [1] = {
355 .start = evt2irq(0x500),
356 .flags = IORESOURCE_IRQ,
357 },
358};
359
360static struct platform_device tmu6_device = {
361 .name = "sh_tmu",
362 .id = 6,
363 .dev = {
364 .platform_data = &tmu6_platform_data,
365 },
366 .resource = tmu6_resources,
367 .num_resources = ARRAY_SIZE(tmu6_resources),
368};
369
370static struct sh_timer_config tmu7_platform_data = {
371 .channel_offset = 0x10,
372 .timer_bit = 1,
373};
374
375static struct resource tmu7_resources[] = {
376 [0] = {
377 .start = 0xFFD82014,
378 .end = 0xFFD82020 - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = evt2irq(0x520),
383 .flags = IORESOURCE_IRQ,
384 },
385};
386
387static struct platform_device tmu7_device = {
388 .name = "sh_tmu",
389 .id = 7,
390 .dev = {
391 .platform_data = &tmu7_platform_data,
392 },
393 .resource = tmu7_resources,
394 .num_resources = ARRAY_SIZE(tmu7_resources),
395};
396
397static struct sh_timer_config tmu8_platform_data = {
398 .channel_offset = 0x1c,
399 .timer_bit = 2,
400};
401
402static struct resource tmu8_resources[] = {
403 [0] = {
404 .start = 0xFFD82020,
405 .end = 0xFFD82030 - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = evt2irq(0x540),
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device tmu8_device = {
415 .name = "sh_tmu",
416 .id = 8,
417 .dev = {
418 .platform_data = &tmu8_platform_data,
419 },
420 .resource = tmu8_resources,
421 .num_resources = ARRAY_SIZE(tmu8_resources),
422};
423
424static struct platform_device *sh7734_devices[] __initdata = {
425 &scif0_device,
426 &scif1_device,
427 &scif2_device,
428 &scif3_device,
429 &scif4_device,
430 &scif5_device,
431 &tmu0_device,
432 &tmu1_device,
433 &tmu2_device,
434 &tmu3_device,
435 &tmu4_device,
436 &tmu5_device,
437 &tmu6_device,
438 &tmu7_device,
439 &tmu8_device,
440 &rtc_device,
441};
442
443static struct platform_device *sh7734_early_devices[] __initdata = {
444 &scif0_device,
445 &scif1_device,
446 &scif2_device,
447 &scif3_device,
448 &scif4_device,
449 &scif5_device,
450 &tmu0_device,
451 &tmu1_device,
452 &tmu2_device,
453 &tmu3_device,
454 &tmu4_device,
455 &tmu5_device,
456 &tmu6_device,
457 &tmu7_device,
458 &tmu8_device,
459};
460
461void __init plat_early_device_setup(void)
462{
463 early_platform_add_devices(sh7734_early_devices,
464 ARRAY_SIZE(sh7734_early_devices));
465}
466
467#define GROUP 0
468enum {
469 UNUSED = 0,
470
471 /* interrupt sources */
472
473 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
474 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
475 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
476 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
477
478 IRQ0, IRQ1, IRQ2, IRQ3,
479 DU,
480 TMU00, TMU10, TMU20, TMU21,
481 TMU30, TMU40, TMU50, TMU51,
482 TMU60, TMU70, TMU80,
483 RESET_WDT,
484 USB,
485 HUDI,
486 SHDMAC,
487 SSI0, SSI1, SSI2, SSI3,
488 VIN0,
489 RGPVG,
490 _2DG,
491 MMC,
492 HSPI,
493 LBSCATA,
494 I2C0,
495 RCAN0,
496 MIMLB,
497 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
498 LBSCDMAC0, LBSCDMAC1, LBSCDMAC2,
499 RCAN1,
500 SDHI0, SDHI1,
501 IEBUS,
502 HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28,
503 RTC,
504 VIN1,
505 LCDC,
506 SRC0, SRC1,
507 GETHER,
508 SDHI2,
509 GPIO0_3, GPIO4_5,
510 STIF0, STIF1,
511 ADMAC,
512 HIF,
513 FLCTL,
514 ADC,
515 MTU2,
516 RSPI,
517 QSPI,
518 HSCIF,
519 VEU3F_VE3,
520
521 /* Group */
522 /* Mask */
523 STIF_M,
524 GPIO_M,
525 HPBDMAC_M,
526 LBSCDMAC_M,
527 RCAN_M,
528 SRC_M,
529 SCIF_M,
530 LCDC_M,
531 _2DG_M,
532 VIN_M,
533 TMU_3_M,
534 TMU_0_M,
535
536 /* Priority */
537 RCAN_P,
538 LBSCDMAC_P,
539
540 /* Common */
541 SDHI,
542 SSI,
543 SPI,
544};
545
546static struct intc_vect vectors[] __initdata = {
547 INTC_VECT(DU, 0x3E0),
548 INTC_VECT(TMU00, 0x400),
549 INTC_VECT(TMU10, 0x420),
550 INTC_VECT(TMU20, 0x440),
551 INTC_VECT(TMU30, 0x480),
552 INTC_VECT(TMU40, 0x4A0),
553 INTC_VECT(TMU50, 0x4C0),
554 INTC_VECT(TMU51, 0x4E0),
555 INTC_VECT(TMU60, 0x500),
556 INTC_VECT(TMU70, 0x520),
557 INTC_VECT(TMU80, 0x540),
558 INTC_VECT(RESET_WDT, 0x560),
559 INTC_VECT(USB, 0x580),
560 INTC_VECT(HUDI, 0x600),
561 INTC_VECT(SHDMAC, 0x620),
562 INTC_VECT(SSI0, 0x6C0),
563 INTC_VECT(SSI1, 0x6E0),
564 INTC_VECT(SSI2, 0x700),
565 INTC_VECT(SSI3, 0x720),
566 INTC_VECT(VIN0, 0x740),
567 INTC_VECT(RGPVG, 0x760),
568 INTC_VECT(_2DG, 0x780),
569 INTC_VECT(MMC, 0x7A0),
570 INTC_VECT(HSPI, 0x7E0),
571 INTC_VECT(LBSCATA, 0x840),
572 INTC_VECT(I2C0, 0x860),
573 INTC_VECT(RCAN0, 0x880),
574 INTC_VECT(SCIF0, 0x8A0),
575 INTC_VECT(SCIF1, 0x8C0),
576 INTC_VECT(SCIF2, 0x900),
577 INTC_VECT(SCIF3, 0x920),
578 INTC_VECT(SCIF4, 0x940),
579 INTC_VECT(SCIF5, 0x960),
580 INTC_VECT(LBSCDMAC0, 0x9E0),
581 INTC_VECT(LBSCDMAC1, 0xA00),
582 INTC_VECT(LBSCDMAC2, 0xA20),
583 INTC_VECT(RCAN1, 0xA60),
584 INTC_VECT(SDHI0, 0xAE0),
585 INTC_VECT(SDHI1, 0xB00),
586 INTC_VECT(IEBUS, 0xB20),
587 INTC_VECT(HPBDMAC0_3, 0xB60),
588 INTC_VECT(HPBDMAC4_10, 0xB80),
589 INTC_VECT(HPBDMAC11_18, 0xBA0),
590 INTC_VECT(HPBDMAC19_22, 0xBC0),
591 INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
592 INTC_VECT(RTC, 0xC00),
593 INTC_VECT(VIN1, 0xC20),
594 INTC_VECT(LCDC, 0xC40),
595 INTC_VECT(SRC0, 0xC60),
596 INTC_VECT(SRC1, 0xC80),
597 INTC_VECT(GETHER, 0xCA0),
598 INTC_VECT(SDHI2, 0xCC0),
599 INTC_VECT(GPIO0_3, 0xCE0),
600 INTC_VECT(GPIO4_5, 0xD00),
601 INTC_VECT(STIF0, 0xD20),
602 INTC_VECT(STIF1, 0xD40),
603 INTC_VECT(ADMAC, 0xDA0),
604 INTC_VECT(HIF, 0xDC0),
605 INTC_VECT(FLCTL, 0xDE0),
606 INTC_VECT(ADC, 0xE00),
607 INTC_VECT(MTU2, 0xE20),
608 INTC_VECT(RSPI, 0xE40),
609 INTC_VECT(QSPI, 0xE60),
610 INTC_VECT(HSCIF, 0xFC0),
611 INTC_VECT(VEU3F_VE3, 0xF40),
612};
613
614static struct intc_group groups[] __initdata = {
615 /* Common */
616 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
617 INTC_GROUP(SPI, HSPI, RSPI, QSPI),
618 INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
619
620 /* Mask group */
621 INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */
622 INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */
623 INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18,
624 HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */
625 INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */
626 INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */
627 INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */
628 INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
629 HSCIF), /* 14 */
630 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
631 INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */
632 INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */
633 INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51,
634 TMU60, TMU60, TMU70, TMU80), /* 2 */
635 INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */
636
637 /* Priority group*/
638 INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */
639 INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */
640};
641
642static struct intc_mask_reg mask_registers[] __initdata = {
643 { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
644 { 0,
645 VEU3F_VE3,
646 SDHI, /* SDHI 0-2 */
647 ADMAC,
648 FLCTL,
649 RESET_WDT,
650 HIF,
651 ADC,
652 MTU2,
653 STIF_M, /* STIF 0,1 */
654 GPIO_M, /* GPIO 0-5*/
655 GETHER,
656 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
657 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
658 RCAN_M, /* RCAN, IEBUS */
659 SRC_M, /* SRC 0,1 */
660 LBSCATA,
661 SCIF_M, /* SCIF 0-5, HSCIF */
662 LCDC_M, /* LCDC, MIMLB */
663 _2DG_M, /* 2DG, RGPVG */
664 SPI, /* HSPI, RSPI, QSPI */
665 VIN_M, /* VIN0, 1 */
666 SSI, /* SSI 0-3 */
667 USB,
668 SHDMAC,
669 HUDI,
670 MMC,
671 RTC,
672 I2C0, /* I2C */ /* I2C 0, 1*/
673 TMU_3_M, /* TMU30 - TMU80 */
674 TMU_0_M, /* TMU00 - TMU21 */
675 DU } },
676};
677
678static struct intc_prio_reg prio_registers[] __initdata = {
679 { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
680 { DU, TMU00, TMU10, TMU20 } },
681 { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
682 { TMU30, TMU60, RTC, SDHI } },
683 { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
684 { HUDI, SHDMAC, USB, SSI } },
685 { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
686 { VIN0, SPI, _2DG, LBSCATA } },
687 { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
688 { SCIF0, SCIF3, HSCIF, LCDC } },
689 { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
690 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } },
691 { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
692 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } },
693 { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
694 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } },
695 { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
696 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
697 { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
698 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } },
699 { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
700 { STIF0, STIF1, VEU3F_VE3, GETHER } },
701 { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
702 { MTU2, RGPVG, MIMLB, IEBUS } },
703};
704
705static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups,
706 mask_registers, prio_registers, NULL);
707
708/* Support for external interrupt pins in IRQ mode */
709
710static struct intc_vect irq3210_vectors[] __initdata = {
711 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
712 INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
713};
714
715static struct intc_sense_reg irq3210_sense_registers[] __initdata = {
716 { 0xFF80201C, 32, 2, /* ICR1 */
717 { IRQ0, IRQ1, IRQ2, IRQ3, } },
718};
719
720static struct intc_mask_reg irq3210_ack_registers[] __initdata = {
721 { 0xFF802024, 0, 32, /* INTREQ */
722 { IRQ0, IRQ1, IRQ2, IRQ3, } },
723};
724
725static struct intc_mask_reg irq3210_mask_registers[] __initdata = {
726 { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
727 { IRQ0, IRQ1, IRQ2, IRQ3, } },
728};
729
730static struct intc_prio_reg irq3210_prio_registers[] __initdata = {
731 { 0xFF802010, 0, 32, 4, /* INTPRI */
732 { IRQ0, IRQ1, IRQ2, IRQ3, } },
733};
734
735static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210",
736 irq3210_vectors, NULL,
737 irq3210_mask_registers, irq3210_prio_registers,
738 irq3210_sense_registers, irq3210_ack_registers);
739
740/* External interrupt pins in IRL mode */
741
742static struct intc_vect vectors_irl3210[] __initdata = {
743 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
744 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
745 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
746 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
747 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
748 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
749 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
750 INTC_VECT(IRL0_HHHL, 0x3c0),
751};
752
753static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210",
754 vectors_irl3210, NULL, mask_registers, NULL, NULL);
755
756#define INTC_ICR0 0xFF802000
757#define INTC_INTMSK0 0xFF802044
758#define INTC_INTMSK1 0xFF802048
759#define INTC_INTMSKCLR0 0xFF802064
760#define INTC_INTMSKCLR1 0xFF802068
761
762void __init plat_irq_setup(void)
763{
764 /* disable IRQ3-0 */
765 __raw_writel(0xF0000000, INTC_INTMSK0);
766
767 /* disable IRL3-0 */
768 __raw_writel(0x80000000, INTC_INTMSK1);
769
770 /* select IRL mode for IRL3-0 */
771 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
772
773 /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */
774 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
775
776 register_intc_controller(&intc_desc);
777}
778
779void __init plat_irq_setup_pins(int mode)
780{
781 switch (mode) {
782 case IRQ_MODE_IRQ3210:
783 /* select IRQ mode for IRL3-0 */
784 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
785 register_intc_controller(&intc_desc_irq3210);
786 break;
787 case IRQ_MODE_IRL3210:
788 /* enable IRL0-3 but don't provide any masking */
789 __raw_writel(0x80000000, INTC_INTMSKCLR1);
790 __raw_writel(0xf0000000, INTC_INTMSKCLR0);
791 break;
792 case IRQ_MODE_IRL3210_MASK:
793 /* enable IRL0-3 and mask using cpu intc controller */
794 __raw_writel(0x80000000, INTC_INTMSKCLR0);
795 register_intc_controller(&intc_desc_irl3210);
796 break;
797 default:
798 BUG();
799 }
800}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 09:23:31 -0500