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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-01-14 22:22:35 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-01-14 22:22:35 -0500
commitfac515db45207718168cb55ca4d0a390e43b61af (patch)
tree7dd2fe9b94f769a2009ff6c7402c52ef3dd3b640 /arch
parent3ac8ff1c475bda7174fce63230c0932454287cd5 (diff)
parentd064f30e5063ec54ab50af08c64fb5055e759bfd (diff)
Merge remote-tracking branch 'scott/next' into next
Freescale updates from Scott: << Highlights include 32-bit booke relocatable support, e6500 hardware tablewalk support, various e500 SPE fixes, some new/revived boards, and e6500 deeper idle and altivec powerdown modes. >>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/Kconfig5
-rw-r--r--arch/powerpc/boot/Makefile7
-rw-r--r--arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi82
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/mvme5100.dts185
-rw-r--r--arch/powerpc/boot/dts/p1010rdb-pa.dts23
-rw-r--r--arch/powerpc/boot/dts/p1010rdb-pa.dtsi85
-rw-r--r--arch/powerpc/boot/dts/p1010rdb-pa_36b.dts (renamed from arch/powerpc/boot/dts/p1010rdb_36b.dts)47
-rw-r--r--arch/powerpc/boot/dts/p1010rdb-pb.dts35
-rw-r--r--arch/powerpc/boot/dts/p1010rdb-pb_36b.dts58
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts66
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dtsi43
-rw-r--r--arch/powerpc/boot/dts/p1010rdb_32b.dtsi79
-rw-r--r--arch/powerpc/boot/dts/p1010rdb_36b.dtsi79
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dtsi3
-rw-r--r--arch/powerpc/boot/dts/p1025twr.dts95
-rw-r--r--arch/powerpc/boot/dts/p1025twr.dtsi280
-rw-r--r--arch/powerpc/boot/mvme5100.c27
-rwxr-xr-xarch/powerpc/boot/wrapper4
-rw-r--r--arch/powerpc/configs/85xx/p1023_defconfig188
-rw-r--r--arch/powerpc/configs/adder875_defconfig1
-rw-r--r--arch/powerpc/configs/ep88xc_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig3
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig3
-rw-r--r--arch/powerpc/configs/mpc866_ads_defconfig1
-rw-r--r--arch/powerpc/configs/mpc885_ads_defconfig1
-rw-r--r--arch/powerpc/configs/mvme5100_defconfig144
-rw-r--r--arch/powerpc/configs/tqm8xx_defconfig1
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h2
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h1
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h13
-rw-r--r--arch/powerpc/include/asm/mmu.h21
-rw-r--r--arch/powerpc/include/asm/paca.h6
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h13
-rw-r--r--arch/powerpc/include/asm/processor.h6
-rw-r--r--arch/powerpc/include/asm/reg.h2
-rw-r--r--arch/powerpc/include/asm/reg_booke.h10
-rw-r--r--arch/powerpc/kernel/asm-offsets.c9
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S54
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S27
-rw-r--r--arch/powerpc/kernel/fsl_booke_entry_mapping.S2
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S266
-rw-r--r--arch/powerpc/kernel/paca.c5
-rw-r--r--arch/powerpc/kernel/process.c30
-rw-r--r--arch/powerpc/kernel/prom.c41
-rw-r--r--arch/powerpc/kernel/setup_64.c31
-rw-r--r--arch/powerpc/kernel/swsusp_booke.S32
-rw-r--r--arch/powerpc/kernel/sysfs.c316
-rw-r--r--arch/powerpc/kvm/bookehv_interrupts.S2
-rw-r--r--arch/powerpc/math-emu/math_efp.c316
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c80
-rw-r--r--arch/powerpc/mm/hugetlbpage-book3e.c54
-rw-r--r--arch/powerpc/mm/mem.c6
-rw-r--r--arch/powerpc/mm/mmu_decl.h2
-rw-r--r--arch/powerpc/mm/pgtable_32.c1
-rw-r--r--arch/powerpc/mm/pgtable_64.c12
-rw-r--r--arch/powerpc/mm/tlb_low_64e.S174
-rw-r--r--arch/powerpc/mm/tlb_nohash.c93
-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S4
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig6
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/common.c38
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx.h6
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c29
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c25
-rw-r--r--arch/powerpc/platforms/85xx/smp.c17
-rw-r--r--arch/powerpc/platforms/85xx/twr_p102x.c147
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig13
-rw-r--r--arch/powerpc/platforms/embedded6xx/Makefile1
-rw-r--r--arch/powerpc/platforms/embedded6xx/mvme5100.c221
-rw-r--r--arch/powerpc/sysdev/fsl_lbc.c31
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c3
-rw-r--r--arch/powerpc/sysdev/indirect_pci.c6
-rw-r--r--arch/powerpc/sysdev/mpic_timer.c10
77 files changed, 3132 insertions, 611 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index f0a893142cee..fa395179ddd6 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -402,8 +402,7 @@ config KEXEC
402config CRASH_DUMP 402config CRASH_DUMP
403 bool "Build a kdump crash kernel" 403 bool "Build a kdump crash kernel"
404 depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP) 404 depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP)
405 select RELOCATABLE if PPC64 || 44x 405 select RELOCATABLE if PPC64 || 44x || FSL_BOOKE
406 select DYNAMIC_MEMSTART if FSL_BOOKE
407 help 406 help
408 Build a kernel suitable for use as a kdump capture kernel. 407 Build a kernel suitable for use as a kdump capture kernel.
409 The same kernel binary can be used as production kernel and dump 408 The same kernel binary can be used as production kernel and dump
@@ -884,7 +883,7 @@ config DYNAMIC_MEMSTART
884 883
885config RELOCATABLE 884config RELOCATABLE
886 bool "Build a relocatable kernel" 885 bool "Build a relocatable kernel"
887 depends on ADVANCED_OPTIONS && FLATMEM && 44x 886 depends on ADVANCED_OPTIONS && FLATMEM && (44x || FSL_BOOKE)
888 select NONSTATIC_KERNEL 887 select NONSTATIC_KERNEL
889 help 888 help
890 This builds a kernel image that is capable of running at the 889 This builds a kernel image that is capable of running at the
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index ca7f08cc4afd..90e9d9548660 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -71,9 +71,9 @@ src-wlib-y := string.S crt0.S crtsavres.S stdio.c main.c \
71 uartlite.c mpc52xx-psc.c 71 uartlite.c mpc52xx-psc.c
72src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c 72src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
73src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c 73src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
74src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c 74src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c fsl-soc.c
75src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c 75src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
76src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c 76src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c fsl-soc.c
77 77
78src-plat-y := of.c epapr.c 78src-plat-y := of.c epapr.c
79src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \ 79src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
@@ -95,7 +95,7 @@ src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
95src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \ 95src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
96 cuboot-c2k.c gamecube-head.S \ 96 cuboot-c2k.c gamecube-head.S \
97 gamecube.c wii-head.S wii.c holly.c \ 97 gamecube.c wii-head.S wii.c holly.c \
98 prpmc2800.c 98 prpmc2800.c fixed-head.S mvme5100.c
99src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c 99src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
100src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c 100src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
101src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c 101src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
@@ -286,6 +286,7 @@ image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
286image-$(CONFIG_PPC_C2K) += cuImage.c2k 286image-$(CONFIG_PPC_C2K) += cuImage.c2k
287image-$(CONFIG_GAMECUBE) += dtbImage.gamecube 287image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
288image-$(CONFIG_WII) += dtbImage.wii 288image-$(CONFIG_WII) += dtbImage.wii
289image-$(CONFIG_MVME5100) += dtbImage.mvme5100
289 290
290# Board port in arch/powerpc/platform/amigaone/Kconfig 291# Board port in arch/powerpc/platform/amigaone/Kconfig
291image-$(CONFIG_AMIGAONE) += cuImage.amigaone 292image-$(CONFIG_AMIGAONE) += cuImage.amigaone
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
new file mode 100644
index 000000000000..d3cc8d0f7c25
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
@@ -0,0 +1,82 @@
1/*
2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma2: dma@102300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
39 reg = <0x102300 0x4>,
40 <0x102600 0x4>;
41 ranges = <0x0 0x102100 0x500>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 interrupts = <464 2 0 0>;
46 };
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
49 reg = <0x80 0x80>;
50 interrupts = <465 2 0 0>;
51 };
52 dma-channel@100 {
53 compatible = "fsl,eloplus-dma-channel";
54 reg = <0x100 0x80>;
55 interrupts = <466 2 0 0>;
56 };
57 dma-channel@180 {
58 compatible = "fsl,eloplus-dma-channel";
59 reg = <0x180 0x80>;
60 interrupts = <467 2 0 0>;
61 };
62 dma-channel@300 {
63 compatible = "fsl,eloplus-dma-channel";
64 reg = <0x300 0x80>;
65 interrupts = <468 2 0 0>;
66 };
67 dma-channel@380 {
68 compatible = "fsl,eloplus-dma-channel";
69 reg = <0x380 0x80>;
70 interrupts = <469 2 0 0>;
71 };
72 dma-channel@400 {
73 compatible = "fsl,eloplus-dma-channel";
74 reg = <0x400 0x80>;
75 interrupts = <470 2 0 0>;
76 };
77 dma-channel@480 {
78 compatible = "fsl,eloplus-dma-channel";
79 reg = <0x480 0x80>;
80 interrupts = <471 2 0 0>;
81 };
82};
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 68cc5e7f6477..642dc3a83d0e 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -36,7 +36,8 @@
36 #address-cells = <2>; 36 #address-cells = <2>;
37 #size-cells = <1>; 37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; 38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>; 39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
40}; 41};
41 42
42/* controller at 0x9000 */ 43/* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index adb82fd9057f..407cb5fd0f5b 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -36,7 +36,8 @@
36 #address-cells = <2>; 36 #address-cells = <2>;
37 #size-cells = <1>; 37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus"; 38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>; 39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
40}; 41};
41 42
42/* controller at 0x9000 */ 43/* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index e179803a81ef..ebf202234549 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -40,7 +40,8 @@
40 * pin muxing when the DIU is enabled. 40 * pin muxing when the DIU is enabled.
41 */ 41 */
42 compatible = "fsl,p1022-elbc", "fsl,elbc"; 42 compatible = "fsl,p1022-elbc", "fsl,elbc";
43 interrupts = <19 2 0 0>; 43 interrupts = <19 2 0 0>,
44 <16 2 0 0>;
44}; 45};
45 46
46/* controller at 0x9000 */ 47/* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index f1105bffa915..81437fdf1db4 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -36,7 +36,8 @@
36 #address-cells = <2>; 36 #address-cells = <2>;
37 #size-cells = <1>; 37 #size-cells = <1>;
38 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus"; 38 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>; 39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
40}; 41};
41 42
42/* controller at 0xa000 */ 43/* controller at 0xa000 */
diff --git a/arch/powerpc/boot/dts/mvme5100.dts b/arch/powerpc/boot/dts/mvme5100.dts
new file mode 100644
index 000000000000..1ecb341a232a
--- /dev/null
+++ b/arch/powerpc/boot/dts/mvme5100.dts
@@ -0,0 +1,185 @@
1/*
2 * Device Tree Source for Motorola/Emerson MVME5100.
3 *
4 * Copyright 2013 CSC Australia Pty. Ltd.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 model = "MVME5100";
15 compatible = "MVME5100";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 serial0 = &serial0;
21 pci0 = &pci0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,7410 {
29 device_type = "cpu";
30 reg = <0x0>;
31 /* Following required by dtc but not used */
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 i-cache-size = <32768>;
35 d-cache-size = <32768>;
36 timebase-frequency = <25000000>;
37 clock-frequency = <500000000>;
38 bus-frequency = <100000000>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 reg = <0x0 0x20000000>;
45 };
46
47 hawk@fef80000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "hawk-bridge", "simple-bus";
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
53
54 serial0: serial@8000 {
55 device_type = "serial";
56 compatible = "ns16550";
57 reg = <0x8000 0x80>;
58 reg-shift = <4>;
59 clock-frequency = <1843200>;
60 current-speed = <9600>;
61 interrupts = <1 1>; // IRQ1 Level Active Low.
62 interrupt-parent = <&mpic>;
63 };
64
65 serial1: serial@8200 {
66 device_type = "serial";
67 compatible = "ns16550";
68 reg = <0x8200 0x80>;
69 reg-shift = <4>;
70 clock-frequency = <1843200>;
71 current-speed = <9600>;
72 interrupts = <1 1>; // IRQ1 Level Active Low.
73 interrupt-parent = <&mpic>;
74 };
75
76 mpic: interrupt-controller@f3f80000 {
77 #interrupt-cells = <2>;
78 #address-cells = <0>;
79 device_type = "open-pic";
80 compatible = "chrp,open-pic";
81 interrupt-controller;
82 reg = <0xf3f80000 0x40000>;
83 };
84 };
85
86 pci0: pci@feff0000 {
87 #address-cells = <3>;
88 #size-cells = <2>;
89 #interrupt-cells = <1>;
90 device_type = "pci";
91 compatible = "hawk-pci";
92 reg = <0xfec00000 0x400000>;
93 8259-interrupt-acknowledge = <0xfeff0030>;
94 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0x800000
95 0x2000000 0x0 0x80000000 0x80000000 0x0 0x74000000>;
96 bus-range = <0 255>;
97 clock-frequency = <33333333>;
98 interrupt-parent = <&mpic>;
99 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
100 interrupt-map = <
101
102 /*
103 * This definition (IDSEL 11) duplicates the
104 * interrupts definition in the i8259
105 * interrupt controller below.
106 *
107 * Do not change the interrupt sense/polarity from
108 * 0x2 to anything else, doing so will cause endless
109 * "spurious" i8259 interrupts to be fielded.
110 */
111 // IDSEL 11 - iPMC712 PCI/ISA Bridge
112 0x5800 0x0 0x0 0x1 &mpic 0x0 0x2
113 0x5800 0x0 0x0 0x2 &mpic 0x0 0x2
114 0x5800 0x0 0x0 0x3 &mpic 0x0 0x2
115 0x5800 0x0 0x0 0x4 &mpic 0x0 0x2
116
117 /* IDSEL 12 - Not Used */
118
119 /* IDSEL 13 - Universe VME Bridge */
120 0x6800 0x0 0x0 0x1 &mpic 0x5 0x1
121 0x6800 0x0 0x0 0x2 &mpic 0x6 0x1
122 0x6800 0x0 0x0 0x3 &mpic 0x7 0x1
123 0x6800 0x0 0x0 0x4 &mpic 0x8 0x1
124
125 /* IDSEL 14 - ENET 1 */
126 0x7000 0x0 0x0 0x1 &mpic 0x2 0x1
127
128 /* IDSEL 15 - Not Used */
129
130 /* IDSEL 16 - PMC Slot 1 */
131 0x8000 0x0 0x0 0x1 &mpic 0x9 0x1
132 0x8000 0x0 0x0 0x2 &mpic 0xa 0x1
133 0x8000 0x0 0x0 0x3 &mpic 0xb 0x1
134 0x8000 0x0 0x0 0x4 &mpic 0xc 0x1
135
136 /* IDSEL 17 - PMC Slot 2 */
137 0x8800 0x0 0x0 0x1 &mpic 0xc 0x1
138 0x8800 0x0 0x0 0x2 &mpic 0x9 0x1
139 0x8800 0x0 0x0 0x3 &mpic 0xa 0x1
140 0x8800 0x0 0x0 0x4 &mpic 0xb 0x1
141
142 /* IDSEL 18 - Not Used */
143
144 /* IDSEL 19 - ENET 2 */
145 0x9800 0x0 0x0 0x1 &mpic 0xd 0x1
146
147 /* IDSEL 20 - PMCSPAN (PCI-X) */
148 0xa000 0x0 0x0 0x1 &mpic 0x9 0x1
149 0xa000 0x0 0x0 0x2 &mpic 0xa 0x1
150 0xa000 0x0 0x0 0x3 &mpic 0xb 0x1
151 0xa000 0x0 0x0 0x4 &mpic 0xc 0x1
152
153 >;
154
155 isa {
156 #address-cells = <2>;
157 #size-cells = <1>;
158 #interrupt-cells = <2>;
159 device_type = "isa";
160 compatible = "isa";
161 ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
162 interrupt-parent = <&i8259>;
163
164 i8259: interrupt-controller@20 {
165 #interrupt-cells = <2>;
166 #address-cells = <0>;
167 interrupts = <0 2>;
168 device_type = "interrupt-controller";
169 compatible = "chrp,iic";
170 interrupt-controller;
171 reg = <1 0x00000020 0x00000002
172 1 0x000000a0 0x00000002
173 1 0x000004d0 0x00000002>;
174 interrupt-parent = <&mpic>;
175 };
176
177 };
178
179 };
180
181 chosen {
182 linux,stdout-path = &serial0;
183 };
184
185};
diff --git a/arch/powerpc/boot/dts/p1010rdb-pa.dts b/arch/powerpc/boot/dts/p1010rdb-pa.dts
new file mode 100644
index 000000000000..767d4c032857
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pa.dts
@@ -0,0 +1,23 @@
1/*
2 * P1010 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/p1010si-pre.dtsi"
13
14/ {
15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB";
17
18 /include/ "p1010rdb_32b.dtsi"
19};
20
21/include/ "p1010rdb.dtsi"
22/include/ "p1010rdb-pa.dtsi"
23/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb-pa.dtsi b/arch/powerpc/boot/dts/p1010rdb-pa.dtsi
new file mode 100644
index 000000000000..434fb2d58575
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pa.dtsi
@@ -0,0 +1,85 @@
1/*
2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc_nand {
36 partition@0 {
37 /* This location must not be altered */
38 /* 1MB for u-boot Bootloader Image */
39 reg = <0x0 0x00100000>;
40 label = "NAND U-Boot Image";
41 read-only;
42 };
43
44 partition@100000 {
45 /* 1MB for DTB Image */
46 reg = <0x00100000 0x00100000>;
47 label = "NAND DTB Image";
48 };
49
50 partition@200000 {
51 /* 4MB for Linux Kernel Image */
52 reg = <0x00200000 0x00400000>;
53 label = "NAND Linux Kernel Image";
54 };
55
56 partition@600000 {
57 /* 4MB for Compressed Root file System Image */
58 reg = <0x00600000 0x00400000>;
59 label = "NAND Compressed RFS Image";
60 };
61
62 partition@a00000 {
63 /* 15MB for JFFS2 based Root file System */
64 reg = <0x00a00000 0x00f00000>;
65 label = "NAND JFFS2 Root File System";
66 };
67
68 partition@1900000 {
69 /* 7MB for User Area */
70 reg = <0x01900000 0x00700000>;
71 label = "NAND User area";
72 };
73};
74
75&phy0 {
76 interrupts = <1 1 0 0>;
77};
78
79&phy1 {
80 interrupts = <2 1 0 0>;
81};
82
83&phy2 {
84 interrupts = <4 1 0 0>;
85};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dts b/arch/powerpc/boot/dts/p1010rdb-pa_36b.dts
index 64776f4a4651..3033371bc007 100644
--- a/arch/powerpc/boot/dts/p1010rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1010rdb-pa_36b.dts
@@ -38,52 +38,9 @@
38 model = "fsl,P1010RDB"; 38 model = "fsl,P1010RDB";
39 compatible = "fsl,P1010RDB"; 39 compatible = "fsl,P1010RDB";
40 40
41 memory { 41 /include/ "p1010rdb_36b.dtsi"
42 device_type = "memory";
43 };
44
45 board_ifc: ifc: ifc@fffe1e000 {
46 /* NOR, NAND Flashes and CPLD on board */
47 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x3 0x0 0xf 0xffb00000 0x00000020>;
50 reg = <0xf 0xffe1e000 0 0x2000>;
51 };
52
53 board_soc: soc: soc@fffe00000 {
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@fffe09000 {
58 reg = <0xf 0xffe09000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xc0000000
63 0x2000000 0x0 0xc0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@fffe0a000 {
73 reg = <0xf 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0xc0000000
78 0x2000000 0x0 0xc0000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86}; 42};
87 43
88/include/ "p1010rdb.dtsi" 44/include/ "p1010rdb.dtsi"
45/include/ "p1010rdb-pa.dtsi"
89/include/ "fsl/p1010si-post.dtsi" 46/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb-pb.dts b/arch/powerpc/boot/dts/p1010rdb-pb.dts
new file mode 100644
index 000000000000..6eeb7d3185be
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pb.dts
@@ -0,0 +1,35 @@
1/*
2 * P1010 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/p1010si-pre.dtsi"
13
14/ {
15 model = "fsl,P1010RDB-PB";
16 compatible = "fsl,P1010RDB-PB";
17
18 /include/ "p1010rdb_32b.dtsi"
19};
20
21/include/ "p1010rdb.dtsi"
22
23&phy0 {
24 interrupts = <0 1 0 0>;
25};
26
27&phy1 {
28 interrupts = <2 1 0 0>;
29};
30
31&phy2 {
32 interrupts = <1 1 0 0>;
33};
34
35/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb-pb_36b.dts b/arch/powerpc/boot/dts/p1010rdb-pb_36b.dts
new file mode 100644
index 000000000000..7ab3c907b326
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pb_36b.dts
@@ -0,0 +1,58 @@
1/*
2 * P1010 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1010si-pre.dtsi"
36
37/ {
38 model = "fsl,P1010RDB-PB";
39 compatible = "fsl,P1010RDB-PB";
40
41 /include/ "p1010rdb_36b.dtsi"
42};
43
44/include/ "p1010rdb.dtsi"
45
46&phy0 {
47 interrupts = <0 1 0 0>;
48};
49
50&phy1 {
51 interrupts = <2 1 0 0>;
52};
53
54&phy2 {
55 interrupts = <1 1 0 0>;
56};
57
58/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
deleted file mode 100644
index b868d22984e9..000000000000
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * P1010 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/p1010si-pre.dtsi"
13
14/ {
15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB";
17
18 memory {
19 device_type = "memory";
20 };
21
22 board_ifc: ifc: ifc@ffe1e000 {
23 /* NOR, NAND Flashes and CPLD on board */
24 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
25 0x1 0x0 0x0 0xff800000 0x00010000
26 0x3 0x0 0x0 0xffb00000 0x00000020>;
27 reg = <0x0 0xffe1e000 0 0x2000>;
28 };
29
30 board_soc: soc: soc@ffe00000 {
31 ranges = <0x0 0x0 0xffe00000 0x100000>;
32 };
33
34 pci0: pcie@ffe09000 {
35 reg = <0 0xffe09000 0 0x1000>;
36 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
37 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
38 pcie@0 {
39 ranges = <0x2000000 0x0 0xa0000000
40 0x2000000 0x0 0xa0000000
41 0x0 0x20000000
42
43 0x1000000 0x0 0x0
44 0x1000000 0x0 0x0
45 0x0 0x100000>;
46 };
47 };
48
49 pci1: pcie@ffe0a000 {
50 reg = <0 0xffe0a000 0 0x1000>;
51 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
52 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
53 pcie@0 {
54 ranges = <0x2000000 0x0 0x80000000
55 0x2000000 0x0 0x80000000
56 0x0 0x20000000
57
58 0x1000000 0x0 0x0
59 0x1000000 0x0 0x0
60 0x0 0x100000>;
61 };
62 };
63};
64
65/include/ "p1010rdb.dtsi"
66/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index ec7c27a64671..ea534efa790d 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -69,49 +69,11 @@
69 }; 69 };
70 }; 70 };
71 71
72 nand@1,0 { 72 ifc_nand: nand@1,0 {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <1>; 74 #size-cells = <1>;
75 compatible = "fsl,ifc-nand"; 75 compatible = "fsl,ifc-nand";
76 reg = <0x1 0x0 0x10000>; 76 reg = <0x1 0x0 0x10000>;
77
78 partition@0 {
79 /* This location must not be altered */
80 /* 1MB for u-boot Bootloader Image */
81 reg = <0x0 0x00100000>;
82 label = "NAND U-Boot Image";
83 read-only;
84 };
85
86 partition@100000 {
87 /* 1MB for DTB Image */
88 reg = <0x00100000 0x00100000>;
89 label = "NAND DTB Image";
90 };
91
92 partition@200000 {
93 /* 4MB for Linux Kernel Image */
94 reg = <0x00200000 0x00400000>;
95 label = "NAND Linux Kernel Image";
96 };
97
98 partition@600000 {
99 /* 4MB for Compressed Root file System Image */
100 reg = <0x00600000 0x00400000>;
101 label = "NAND Compressed RFS Image";
102 };
103
104 partition@a00000 {
105 /* 15MB for JFFS2 based Root file System */
106 reg = <0x00a00000 0x00f00000>;
107 label = "NAND JFFS2 Root File System";
108 };
109
110 partition@1900000 {
111 /* 7MB for User Area */
112 reg = <0x01900000 0x00700000>;
113 label = "NAND User area";
114 };
115 }; 77 };
116 78
117 cpld@3,0 { 79 cpld@3,0 {
@@ -193,17 +155,14 @@
193 155
194 mdio@24000 { 156 mdio@24000 {
195 phy0: ethernet-phy@0 { 157 phy0: ethernet-phy@0 {
196 interrupts = <3 1 0 0>;
197 reg = <0x1>; 158 reg = <0x1>;
198 }; 159 };
199 160
200 phy1: ethernet-phy@1 { 161 phy1: ethernet-phy@1 {
201 interrupts = <2 1 0 0>;
202 reg = <0x0>; 162 reg = <0x0>;
203 }; 163 };
204 164
205 phy2: ethernet-phy@2 { 165 phy2: ethernet-phy@2 {
206 interrupts = <2 1 0 0>;
207 reg = <0x2>; 166 reg = <0x2>;
208 }; 167 };
209 168
diff --git a/arch/powerpc/boot/dts/p1010rdb_32b.dtsi b/arch/powerpc/boot/dts/p1010rdb_32b.dtsi
new file mode 100644
index 000000000000..fdc19aab2f70
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_32b.dtsi
@@ -0,0 +1,79 @@
1/*
2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35memory {
36 device_type = "memory";
37};
38
39board_ifc: ifc: ifc@ffe1e000 {
40 /* NOR, NAND Flashes and CPLD on board */
41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
45};
46
47board_soc: soc: soc@ffe00000 {
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
49};
50
51pci0: pcie@ffe09000 {
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
57 0x2000000 0x0 0xa0000000
58 0x0 0x20000000
59
60 0x1000000 0x0 0x0
61 0x1000000 0x0 0x0
62 0x0 0x100000>;
63 };
64};
65
66pci1: pcie@ffe0a000 {
67 reg = <0 0xffe0a000 0 0x1000>;
68 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
69 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
70 pcie@0 {
71 ranges = <0x2000000 0x0 0x80000000
72 0x2000000 0x0 0x80000000
73 0x0 0x20000000
74
75 0x1000000 0x0 0x0
76 0x1000000 0x0 0x0
77 0x0 0x100000>;
78 };
79};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dtsi b/arch/powerpc/boot/dts/p1010rdb_36b.dtsi
new file mode 100644
index 000000000000..de2fceed4f79
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_36b.dtsi
@@ -0,0 +1,79 @@
1/*
2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35memory {
36 device_type = "memory";
37};
38
39board_ifc: ifc: ifc@fffe1e000 {
40 /* NOR, NAND Flashes and CPLD on board */
41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
45};
46
47board_soc: soc: soc@fffe00000 {
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
49};
50
51pci0: pcie@fffe09000 {
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
57 0x2000000 0x0 0xc0000000
58 0x0 0x20000000
59
60 0x1000000 0x0 0x0
61 0x1000000 0x0 0x0
62 0x0 0x100000>;
63 };
64};
65
66pci1: pcie@fffe0a000 {
67 reg = <0xf 0xffe0a000 0 0x1000>;
68 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
69 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
70 pcie@0 {
71 ranges = <0x2000000 0x0 0xc0000000
72 0x2000000 0x0 0xc0000000
73 0x0 0x20000000
74
75 0x1000000 0x0 0x0
76 0x1000000 0x0 0x0
77 0x0 0x100000>;
78 };
79};
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
index 873da350d01b..957e0dc1dc0f 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -146,8 +146,9 @@
146 */ 146 */
147 }; 147 };
148 rtc@68 { 148 rtc@68 {
149 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds3232";
150 reg = <0x68>; 150 reg = <0x68>;
151 interrupts = <0x1 0x1 0 0>;
151 }; 152 };
152 adt7461@4c { 153 adt7461@4c {
153 compatible = "adi,adt7461"; 154 compatible = "adi,adt7461";
diff --git a/arch/powerpc/boot/dts/p1025twr.dts b/arch/powerpc/boot/dts/p1025twr.dts
new file mode 100644
index 000000000000..9036a4987905
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dts
@@ -0,0 +1,95 @@
1/*
2 * P1025 TWR Device Tree Source (32-bit address map)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1025";
38 compatible = "fsl,TWR-P1025";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR Flash and SSD1289 */
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x2 0x0 0x0 0xe0000000 0x00020000>;
50 };
51
52 soc: soc@ffe00000 {
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@ffe09000 {
57 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xa0000000
62 0x2000000 0x0 0xa0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@ffe0a000 {
72 reg = <0 0xffe0a000 0 0x1000>;
73 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
74 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0x80000000
77 0x2000000 0x0 0x80000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 qe: qe@ffe80000 {
87 ranges = <0x0 0x0 0xffe80000 0x40000>;
88 reg = <0 0xffe80000 0 0x480>;
89 brg-frequency = <0>;
90 bus-frequency = <0>;
91 };
92};
93
94/include/ "p1025twr.dtsi"
95/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000000000000..8453501c256e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,280 @@
1/*
2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/{
36 aliases {
37 ethernet3 = &enet3;
38 ethernet4 = &enet4;
39 };
40};
41
42&lbc {
43 nor@0,0 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
47 reg = <0x0 0x0 0x4000000>;
48 bank-width = <2>;
49 device-width = <1>;
50
51 partition@0 {
52 /* This location must not be altered */
53 /* 256KB for Vitesse 7385 Switch firmware */
54 reg = <0x0 0x00040000>;
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
57 };
58
59 partition@40000 {
60 /* 256KB for DTB Image */
61 reg = <0x00040000 0x00040000>;
62 label = "NOR DTB Image";
63 };
64
65 partition@80000 {
66 /* 5.5 MB for Linux Kernel Image */
67 reg = <0x00080000 0x00580000>;
68 label = "NOR Linux Kernel Image";
69 };
70
71 partition@400000 {
72 /* 56.75MB for Root file System */
73 reg = <0x00600000 0x038c0000>;
74 label = "NOR Root File System";
75 };
76
77 partition@ec0000 {
78 /* This location must not be altered */
79 /* 256KB for QE ucode firmware*/
80 reg = <0x03ec0000 0x00040000>;
81 label = "NOR QE microcode firmware";
82 read-only;
83 };
84
85 partition@f00000 {
86 /* This location must not be altered */
87 /* 512KB for u-boot Bootloader Image */
88 /* 512KB for u-boot Environment Variables */
89 reg = <0x03f00000 0x00100000>;
90 label = "NOR U-Boot Image";
91 read-only;
92 };
93 };
94
95 /* CS2 for Display */
96 display@2,0 {
97 compatible = "solomon,ssd1289fb";
98 reg = <0x2 0x0000 0x0004>;
99 };
100
101};
102
103&soc {
104 usb@22000 {
105 phy_type = "ulpi";
106 };
107
108 mdio@24000 {
109 phy0: ethernet-phy@2 {
110 interrupt-parent = <&mpic>;
111 interrupts = <1 1 0 0>;
112 reg = <0x2>;
113 };
114
115 phy1: ethernet-phy@1 {
116 interrupt-parent = <&mpic>;
117 interrupts = <2 1 0 0>;
118 reg = <0x1>;
119 };
120
121 tbi0: tbi-phy@11 {
122 reg = <0x11>;
123 device_type = "tbi-phy";
124 };
125 };
126
127 mdio@25000 {
128 tbi1: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133
134 mdio@26000 {
135 tbi2: tbi-phy@11 {
136 reg = <0x11>;
137 device_type = "tbi-phy";
138 };
139 };
140
141 enet0: ethernet@b0000 {
142 phy-handle = <&phy0>;
143 phy-connection-type = "rgmii-id";
144
145 };
146
147 enet1: ethernet@b1000 {
148 status = "disabled";
149 };
150
151 enet2: ethernet@b2000 {
152 phy-handle = <&phy1>;
153 phy-connection-type = "rgmii-id";
154 };
155
156 par_io@e0100 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 reg = <0xe0100 0x60>;
160 ranges = <0x0 0xe0100 0x60>;
161 device_type = "par_io";
162 num-ports = <3>;
163 pio1: ucc_pin@01 {
164 pio-map = <
165 /* port pin dir open_drain assignment has_irq */
166 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
167 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
168 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
169 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
170 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
171 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
172 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
173 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
174 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
175 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
176 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
177 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
178 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
179 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
180 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
181 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
182 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
183 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
184 };
185
186 pio2: ucc_pin@02 {
187 pio-map = <
188 /* port pin dir open_drain assignment has_irq */
189 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
190 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
191 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
192 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
193 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
194 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
195 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
196 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
197 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
198 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
199 };
200
201 pio3: ucc_pin@03 {
202 pio-map = <
203 /* port pin dir open_drain assignment has_irq */
204 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
205 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
206 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
207 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
208 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
209 };
210
211 pio4: ucc_pin@04 {
212 pio-map = <
213 /* port pin dir open_drain assignment has_irq */
214 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
215 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
216 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
217 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
218 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
219 };
220 };
221};
222
223&qe {
224 enet3: ucc@2000 {
225 device_type = "network";
226 compatible = "ucc_geth";
227 rx-clock-name = "clk12";
228 tx-clock-name = "clk9";
229 pio-handle = <&pio1>;
230 phy-handle = <&qe_phy0>;
231 phy-connection-type = "mii";
232 };
233
234 mdio@2120 {
235 qe_phy0: ethernet-phy@18 {
236 interrupt-parent = <&mpic>;
237 interrupts = <4 1 0 0>;
238 reg = <0x18>;
239 device_type = "ethernet-phy";
240 };
241 qe_phy1: ethernet-phy@19 {
242 interrupt-parent = <&mpic>;
243 interrupts = <5 1 0 0>;
244 reg = <0x19>;
245 device_type = "ethernet-phy";
246 };
247 tbi-phy@11 {
248 reg = <0x11>;
249 device_type = "tbi-phy";
250 };
251 };
252
253 enet4: ucc@2400 {
254 device_type = "network";
255 compatible = "ucc_geth";
256 rx-clock-name = "none";
257 tx-clock-name = "clk13";
258 pio-handle = <&pio2>;
259 phy-handle = <&qe_phy1>;
260 phy-connection-type = "rmii";
261 };
262
263 serial2: ucc@2600 {
264 device_type = "serial";
265 compatible = "ucc_uart";
266 port-number = <0>;
267 rx-clock-name = "brg6";
268 tx-clock-name = "brg6";
269 pio-handle = <&pio3>;
270 };
271
272 serial3: ucc@2200 {
273 device_type = "serial";
274 compatible = "ucc_uart";
275 port-number = <1>;
276 rx-clock-name = "brg2";
277 tx-clock-name = "brg2";
278 pio-handle = <&pio4>;
279 };
280};
diff --git a/arch/powerpc/boot/mvme5100.c b/arch/powerpc/boot/mvme5100.c
new file mode 100644
index 000000000000..cb865f83c60b
--- /dev/null
+++ b/arch/powerpc/boot/mvme5100.c
@@ -0,0 +1,27 @@
1/*
2 * Motorola/Emerson MVME5100 with PPCBug firmware.
3 *
4 * Author: Stephen Chivers <schivers@csc.com>
5 *
6 * Copyright 2013 CSC Australia Pty. Ltd.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 */
13#include "types.h"
14#include "ops.h"
15#include "io.h"
16
17BSS_STACK(4096);
18
19void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
20{
21 u32 heapsize;
22
23 heapsize = 0x8000000 - (u32)_end; /* 128M */
24 simple_alloc_init(_end, heapsize, 32, 64);
25 fdt_init(_dtb_start);
26 serial_console_init();
27}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 2e1af74a64be..d27a25518b01 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -265,6 +265,10 @@ epapr)
265 link_address='0x20000000' 265 link_address='0x20000000'
266 pie=-pie 266 pie=-pie
267 ;; 267 ;;
268mvme5100)
269 platformo="$object/fixed-head.o $object/mvme5100.o"
270 binary=y
271 ;;
268esac 272esac
269 273
270vmz="$tmpdir/`basename \"$kernel\"`.$ext" 274vmz="$tmpdir/`basename \"$kernel\"`.$ext"
diff --git a/arch/powerpc/configs/85xx/p1023_defconfig b/arch/powerpc/configs/85xx/p1023_defconfig
deleted file mode 100644
index b06d37da44f4..000000000000
--- a/arch/powerpc/configs/85xx/p1023_defconfig
+++ /dev/null
@@ -1,188 +0,0 @@
1CONFIG_PPC_85xx=y
2CONFIG_SMP=y
3CONFIG_NR_CPUS=2
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6CONFIG_BSD_PROCESS_ACCT=y
7CONFIG_AUDIT=y
8CONFIG_NO_HZ=y
9CONFIG_HIGH_RES_TIMERS=y
10CONFIG_RCU_FANOUT=32
11CONFIG_IKCONFIG=y
12CONFIG_IKCONFIG_PROC=y
13CONFIG_LOG_BUF_SHIFT=14
14CONFIG_BLK_DEV_INITRD=y
15CONFIG_KALLSYMS_ALL=y
16CONFIG_EMBEDDED=y
17CONFIG_MODULES=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_MODVERSIONS=y
21# CONFIG_BLK_DEV_BSG is not set
22CONFIG_PARTITION_ADVANCED=y
23CONFIG_MAC_PARTITION=y
24CONFIG_PHYSICAL_START=0x00000000
25CONFIG_P1023_RDB=y
26CONFIG_P1023_RDS=y
27CONFIG_QUICC_ENGINE=y
28CONFIG_QE_GPIO=y
29CONFIG_CPM2=y
30CONFIG_HIGHMEM=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32CONFIG_BINFMT_MISC=m
33CONFIG_MATH_EMULATION=y
34CONFIG_SWIOTLB=y
35CONFIG_PCI=y
36CONFIG_PCIEPORTBUS=y
37# CONFIG_PCIEAER is not set
38# CONFIG_PCIEASPM is not set
39CONFIG_PCI_MSI=y
40CONFIG_NET=y
41CONFIG_PACKET=y
42CONFIG_UNIX=y
43CONFIG_XFRM_USER=y
44CONFIG_NET_KEY=y
45CONFIG_INET=y
46CONFIG_IP_MULTICAST=y
47CONFIG_IP_ADVANCED_ROUTER=y
48CONFIG_IP_MULTIPLE_TABLES=y
49CONFIG_IP_ROUTE_MULTIPATH=y
50CONFIG_IP_ROUTE_VERBOSE=y
51CONFIG_IP_PNP=y
52CONFIG_IP_PNP_DHCP=y
53CONFIG_IP_PNP_BOOTP=y
54CONFIG_IP_PNP_RARP=y
55CONFIG_NET_IPIP=y
56CONFIG_IP_MROUTE=y
57CONFIG_IP_PIMSM_V1=y
58CONFIG_IP_PIMSM_V2=y
59CONFIG_ARPD=y
60CONFIG_INET_ESP=y
61# CONFIG_INET_XFRM_MODE_BEET is not set
62# CONFIG_INET_LRO is not set
63CONFIG_IPV6=y
64CONFIG_IP_SCTP=m
65CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
66CONFIG_DEVTMPFS=y
67CONFIG_DEVTMPFS_MOUNT=y
68CONFIG_MTD=y
69CONFIG_MTD_CMDLINE_PARTS=y
70CONFIG_MTD_CHAR=y
71CONFIG_MTD_BLOCK=y
72CONFIG_MTD_CFI=y
73CONFIG_MTD_CFI_AMDSTD=y
74CONFIG_MTD_PHYSMAP_OF=y
75CONFIG_MTD_NAND=y
76CONFIG_MTD_NAND_FSL_ELBC=y
77CONFIG_PROC_DEVICETREE=y
78CONFIG_BLK_DEV_LOOP=y
79CONFIG_BLK_DEV_RAM=y
80CONFIG_BLK_DEV_RAM_SIZE=131072
81CONFIG_EEPROM_AT24=y
82CONFIG_EEPROM_LEGACY=y
83CONFIG_BLK_DEV_SD=y
84CONFIG_CHR_DEV_ST=y
85CONFIG_BLK_DEV_SR=y
86CONFIG_CHR_DEV_SG=y
87CONFIG_SCSI_MULTI_LUN=y
88CONFIG_SCSI_LOGGING=y
89CONFIG_ATA=y
90CONFIG_SATA_FSL=y
91CONFIG_SATA_SIL24=y
92CONFIG_NETDEVICES=y
93CONFIG_DUMMY=y
94CONFIG_FS_ENET=y
95CONFIG_FSL_PQ_MDIO=y
96CONFIG_E1000E=y
97CONFIG_PHYLIB=y
98CONFIG_AT803X_PHY=y
99CONFIG_MARVELL_PHY=y
100CONFIG_DAVICOM_PHY=y
101CONFIG_CICADA_PHY=y
102CONFIG_VITESSE_PHY=y
103CONFIG_FIXED_PHY=y
104CONFIG_INPUT_FF_MEMLESS=m
105# CONFIG_INPUT_MOUSEDEV is not set
106# CONFIG_INPUT_KEYBOARD is not set
107# CONFIG_INPUT_MOUSE is not set
108CONFIG_SERIO_LIBPS2=y
109CONFIG_SERIAL_8250=y
110CONFIG_SERIAL_8250_CONSOLE=y
111CONFIG_SERIAL_8250_NR_UARTS=2
112CONFIG_SERIAL_8250_RUNTIME_UARTS=2
113CONFIG_SERIAL_8250_EXTENDED=y
114CONFIG_SERIAL_8250_MANY_PORTS=y
115CONFIG_SERIAL_8250_SHARE_IRQ=y
116CONFIG_SERIAL_8250_DETECT_IRQ=y
117CONFIG_SERIAL_8250_RSA=y
118CONFIG_HW_RANDOM=y
119CONFIG_NVRAM=y
120CONFIG_I2C=y
121CONFIG_I2C_CHARDEV=y
122CONFIG_I2C_CPM=m
123CONFIG_I2C_MPC=y
124CONFIG_GPIO_MPC8XXX=y
125# CONFIG_HWMON is not set
126CONFIG_VIDEO_OUTPUT_CONTROL=y
127CONFIG_SOUND=y
128CONFIG_SND=y
129CONFIG_SND_MIXER_OSS=y
130CONFIG_SND_PCM_OSS=y
131# CONFIG_SND_SUPPORT_OLD_API is not set
132CONFIG_USB=y
133CONFIG_USB_DEVICEFS=y
134CONFIG_USB_MON=y
135CONFIG_USB_EHCI_HCD=y
136CONFIG_USB_EHCI_FSL=y
137CONFIG_USB_STORAGE=y
138CONFIG_EDAC=y
139CONFIG_EDAC_MM_EDAC=y
140CONFIG_RTC_CLASS=y
141CONFIG_RTC_DRV_DS1307=y
142CONFIG_RTC_DRV_CMOS=y
143CONFIG_DMADEVICES=y
144CONFIG_FSL_DMA=y
145# CONFIG_NET_DMA is not set
146CONFIG_STAGING=y
147CONFIG_EXT2_FS=y
148CONFIG_EXT3_FS=y
149# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
150CONFIG_ISO9660_FS=m
151CONFIG_JOLIET=y
152CONFIG_ZISOFS=y
153CONFIG_UDF_FS=m
154CONFIG_MSDOS_FS=m
155CONFIG_VFAT_FS=y
156CONFIG_NTFS_FS=y
157CONFIG_PROC_KCORE=y
158CONFIG_TMPFS=y
159CONFIG_ADFS_FS=m
160CONFIG_AFFS_FS=m
161CONFIG_HFS_FS=m
162CONFIG_HFSPLUS_FS=m
163CONFIG_BEFS_FS=m
164CONFIG_BFS_FS=m
165CONFIG_EFS_FS=m
166CONFIG_CRAMFS=y
167CONFIG_VXFS_FS=m
168CONFIG_HPFS_FS=m
169CONFIG_QNX4FS_FS=m
170CONFIG_SYSV_FS=m
171CONFIG_UFS_FS=m
172CONFIG_NFS_FS=y
173CONFIG_NFS_V4=y
174CONFIG_ROOT_NFS=y
175CONFIG_NFSD=y
176CONFIG_CRC_T10DIF=y
177CONFIG_FRAME_WARN=8092
178CONFIG_DEBUG_FS=y
179CONFIG_DETECT_HUNG_TASK=y
180# CONFIG_DEBUG_BUGVERBOSE is not set
181CONFIG_DEBUG_INFO=y
182CONFIG_STRICT_DEVMEM=y
183CONFIG_CRYPTO_PCBC=m
184CONFIG_CRYPTO_SHA256=y
185CONFIG_CRYPTO_SHA512=y
186CONFIG_CRYPTO_AES=y
187# CONFIG_CRYPTO_ANSI_CPRNG is not set
188CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs/adder875_defconfig
index 69128740c14d..15b1ff5d96e7 100644
--- a/arch/powerpc/configs/adder875_defconfig
+++ b/arch/powerpc/configs/adder875_defconfig
@@ -70,3 +70,4 @@ CONFIG_DEBUG_KERNEL=y
70CONFIG_DETECT_HUNG_TASK=y 70CONFIG_DETECT_HUNG_TASK=y
71CONFIG_DEBUG_INFO=y 71CONFIG_DEBUG_INFO=y
72# CONFIG_RCU_CPU_STALL_DETECTOR is not set 72# CONFIG_RCU_CPU_STALL_DETECTOR is not set
73CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/ep88xc_defconfig b/arch/powerpc/configs/ep88xc_defconfig
index 219fd470ed22..b8a79d7ee89f 100644
--- a/arch/powerpc/configs/ep88xc_defconfig
+++ b/arch/powerpc/configs/ep88xc_defconfig
@@ -72,3 +72,4 @@ CONFIG_DEBUG_KERNEL=y
72CONFIG_DETECT_HUNG_TASK=y 72CONFIG_DETECT_HUNG_TASK=y
73CONFIG_DEBUG_INFO=y 73CONFIG_DEBUG_INFO=y
74# CONFIG_RCU_CPU_STALL_DETECTOR is not set 74# CONFIG_RCU_CPU_STALL_DETECTOR is not set
75CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index d2e0fab5ee5b..83d3550fdb54 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -31,6 +31,7 @@ CONFIG_C293_PCIE=y
31CONFIG_P1010_RDB=y 31CONFIG_P1010_RDB=y
32CONFIG_P1022_DS=y 32CONFIG_P1022_DS=y
33CONFIG_P1022_RDK=y 33CONFIG_P1022_RDK=y
34CONFIG_P1023_RDB=y
34CONFIG_P1023_RDS=y 35CONFIG_P1023_RDS=y
35CONFIG_SOCRATES=y 36CONFIG_SOCRATES=y
36CONFIG_KSI8560=y 37CONFIG_KSI8560=y
@@ -113,6 +114,7 @@ CONFIG_BLK_DEV_LOOP=y
113CONFIG_BLK_DEV_NBD=y 114CONFIG_BLK_DEV_NBD=y
114CONFIG_BLK_DEV_RAM=y 115CONFIG_BLK_DEV_RAM=y
115CONFIG_BLK_DEV_RAM_SIZE=131072 116CONFIG_BLK_DEV_RAM_SIZE=131072
117CONFIG_EEPROM_AT24=y
116CONFIG_EEPROM_LEGACY=y 118CONFIG_EEPROM_LEGACY=y
117CONFIG_BLK_DEV_SD=y 119CONFIG_BLK_DEV_SD=y
118CONFIG_CHR_DEV_ST=y 120CONFIG_CHR_DEV_ST=y
@@ -211,6 +213,7 @@ CONFIG_EDAC=y
211CONFIG_EDAC_MM_EDAC=y 213CONFIG_EDAC_MM_EDAC=y
212CONFIG_RTC_CLASS=y 214CONFIG_RTC_CLASS=y
213CONFIG_RTC_DRV_CMOS=y 215CONFIG_RTC_DRV_CMOS=y
216CONFIG_RTC_DRV_DS1307=y
214CONFIG_DMADEVICES=y 217CONFIG_DMADEVICES=y
215CONFIG_FSL_DMA=y 218CONFIG_FSL_DMA=y
216# CONFIG_NET_DMA is not set 219# CONFIG_NET_DMA is not set
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4cb7b59e98bd..4b686294feb4 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -34,6 +34,7 @@ CONFIG_C293_PCIE=y
34CONFIG_P1010_RDB=y 34CONFIG_P1010_RDB=y
35CONFIG_P1022_DS=y 35CONFIG_P1022_DS=y
36CONFIG_P1022_RDK=y 36CONFIG_P1022_RDK=y
37CONFIG_P1023_RDB=y
37CONFIG_P1023_RDS=y 38CONFIG_P1023_RDS=y
38CONFIG_SOCRATES=y 39CONFIG_SOCRATES=y
39CONFIG_KSI8560=y 40CONFIG_KSI8560=y
@@ -116,6 +117,7 @@ CONFIG_BLK_DEV_LOOP=y
116CONFIG_BLK_DEV_NBD=y 117CONFIG_BLK_DEV_NBD=y
117CONFIG_BLK_DEV_RAM=y 118CONFIG_BLK_DEV_RAM=y
118CONFIG_BLK_DEV_RAM_SIZE=131072 119CONFIG_BLK_DEV_RAM_SIZE=131072
120CONFIG_EEPROM_AT24=y
119CONFIG_EEPROM_LEGACY=y 121CONFIG_EEPROM_LEGACY=y
120CONFIG_BLK_DEV_SD=y 122CONFIG_BLK_DEV_SD=y
121CONFIG_CHR_DEV_ST=y 123CONFIG_CHR_DEV_ST=y
@@ -212,6 +214,7 @@ CONFIG_EDAC=y
212CONFIG_EDAC_MM_EDAC=y 214CONFIG_EDAC_MM_EDAC=y
213CONFIG_RTC_CLASS=y 215CONFIG_RTC_CLASS=y
214CONFIG_RTC_DRV_CMOS=y 216CONFIG_RTC_DRV_CMOS=y
217CONFIG_RTC_DRV_DS1307=y
215CONFIG_DMADEVICES=y 218CONFIG_DMADEVICES=y
216CONFIG_FSL_DMA=y 219CONFIG_FSL_DMA=y
217# CONFIG_NET_DMA is not set 220# CONFIG_NET_DMA is not set
diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig
index 5c258823e694..d954e80c286a 100644
--- a/arch/powerpc/configs/mpc866_ads_defconfig
+++ b/arch/powerpc/configs/mpc866_ads_defconfig
@@ -55,3 +55,4 @@ CONFIG_PARTITION_ADVANCED=y
55CONFIG_CRC_CCITT=y 55CONFIG_CRC_CCITT=y
56# CONFIG_RCU_CPU_STALL_DETECTOR is not set 56# CONFIG_RCU_CPU_STALL_DETECTOR is not set
57# CONFIG_CRYPTO_ANSI_CPRNG is not set 57# CONFIG_CRYPTO_ANSI_CPRNG is not set
58CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig
index 9e146cdf63de..3f47d00a10c0 100644
--- a/arch/powerpc/configs/mpc885_ads_defconfig
+++ b/arch/powerpc/configs/mpc885_ads_defconfig
@@ -78,3 +78,4 @@ CONFIG_DEBUG_KERNEL=y
78CONFIG_DETECT_HUNG_TASK=y 78CONFIG_DETECT_HUNG_TASK=y
79CONFIG_DEBUG_INFO=y 79CONFIG_DEBUG_INFO=y
80# CONFIG_RCU_CPU_STALL_DETECTOR is not set 80# CONFIG_RCU_CPU_STALL_DETECTOR is not set
81CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/mvme5100_defconfig b/arch/powerpc/configs/mvme5100_defconfig
new file mode 100644
index 000000000000..93c7752e2dbb
--- /dev/null
+++ b/arch/powerpc/configs/mvme5100_defconfig
@@ -0,0 +1,144 @@
1CONFIG_SYSVIPC=y
2CONFIG_POSIX_MQUEUE=y
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
5CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y
7CONFIG_LOG_BUF_SHIFT=14
8# CONFIG_UTS_NS is not set
9# CONFIG_IPC_NS is not set
10# CONFIG_PID_NS is not set
11# CONFIG_NET_NS is not set
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13# CONFIG_COMPAT_BRK is not set
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16# CONFIG_BLK_DEV_BSG is not set
17# CONFIG_PPC_CHRP is not set
18# CONFIG_PPC_PMAC is not set
19CONFIG_EMBEDDED6xx=y
20CONFIG_MVME5100=y
21CONFIG_KVM_GUEST=y
22CONFIG_HZ_100=y
23# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
24# CONFIG_COMPACTION is not set
25CONFIG_CMDLINE_BOOL=y
26CONFIG_CMDLINE="console=ttyS0,9600 ip=dhcp root=/dev/nfs"
27CONFIG_NET=y
28CONFIG_PACKET=y
29CONFIG_UNIX=y
30CONFIG_INET=y
31CONFIG_IP_MULTICAST=y
32CONFIG_IP_PNP=y
33CONFIG_IP_PNP_DHCP=y
34CONFIG_IP_PNP_BOOTP=y
35# CONFIG_INET_LRO is not set
36# CONFIG_IPV6 is not set
37CONFIG_NETFILTER=y
38CONFIG_NF_CONNTRACK=m
39CONFIG_NF_CT_PROTO_SCTP=m
40CONFIG_NF_CONNTRACK_AMANDA=m
41CONFIG_NF_CONNTRACK_FTP=m
42CONFIG_NF_CONNTRACK_H323=m
43CONFIG_NF_CONNTRACK_IRC=m
44CONFIG_NF_CONNTRACK_NETBIOS_NS=m
45CONFIG_NF_CONNTRACK_PPTP=m
46CONFIG_NF_CONNTRACK_SIP=m
47CONFIG_NF_CONNTRACK_TFTP=m
48CONFIG_NETFILTER_XT_MATCH_MAC=m
49CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
50CONFIG_NETFILTER_XT_MATCH_STATE=m
51CONFIG_NF_CONNTRACK_IPV4=m
52CONFIG_IP_NF_IPTABLES=m
53CONFIG_IP_NF_FILTER=m
54CONFIG_IP_NF_TARGET_REJECT=m
55CONFIG_IP_NF_MANGLE=m
56CONFIG_IP_NF_TARGET_ECN=m
57CONFIG_IP_NF_TARGET_TTL=m
58CONFIG_IP_NF_RAW=m
59CONFIG_IP_NF_ARPTABLES=m
60CONFIG_IP_NF_ARPFILTER=m
61CONFIG_IP_NF_ARP_MANGLE=m
62CONFIG_LAPB=m
63CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
64CONFIG_PROC_DEVICETREE=y
65CONFIG_BLK_DEV_LOOP=y
66CONFIG_BLK_DEV_RAM=y
67CONFIG_BLK_DEV_RAM_COUNT=2
68CONFIG_BLK_DEV_RAM_SIZE=8192
69CONFIG_EEPROM_LEGACY=m
70CONFIG_NETDEVICES=y
71CONFIG_TUN=m
72# CONFIG_NET_VENDOR_3COM is not set
73CONFIG_E100=y
74# CONFIG_WLAN is not set
75# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
76# CONFIG_INPUT_KEYBOARD is not set
77# CONFIG_INPUT_MOUSE is not set
78# CONFIG_SERIO is not set
79CONFIG_SERIAL_8250=y
80CONFIG_SERIAL_8250_CONSOLE=y
81CONFIG_SERIAL_8250_NR_UARTS=10
82CONFIG_SERIAL_8250_EXTENDED=y
83CONFIG_SERIAL_8250_MANY_PORTS=y
84CONFIG_SERIAL_8250_SHARE_IRQ=y
85CONFIG_SERIAL_OF_PLATFORM=y
86CONFIG_HW_RANDOM=y
87CONFIG_I2C=y
88CONFIG_I2C_CHARDEV=y
89CONFIG_I2C_MPC=y
90# CONFIG_HWMON is not set
91CONFIG_VIDEO_OUTPUT_CONTROL=m
92# CONFIG_VGA_CONSOLE is not set
93# CONFIG_HID is not set
94# CONFIG_USB_SUPPORT is not set
95# CONFIG_IOMMU_SUPPORT is not set
96CONFIG_VME_BUS=m
97CONFIG_VME_CA91CX42=m
98CONFIG_EXT2_FS=m
99CONFIG_EXT3_FS=m
100# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
101CONFIG_XFS_FS=m
102CONFIG_ISO9660_FS=m
103CONFIG_JOLIET=y
104CONFIG_ZISOFS=y
105CONFIG_UDF_FS=m
106CONFIG_MSDOS_FS=m
107CONFIG_VFAT_FS=m
108CONFIG_PROC_KCORE=y
109CONFIG_TMPFS=y
110CONFIG_NFS_FS=y
111CONFIG_NFS_V3_ACL=y
112CONFIG_NFS_V4=y
113CONFIG_ROOT_NFS=y
114CONFIG_NFSD=m
115CONFIG_NFSD_V3=y
116CONFIG_CIFS=m
117CONFIG_NLS=y
118CONFIG_NLS_CODEPAGE_437=m
119CONFIG_NLS_CODEPAGE_932=m
120CONFIG_NLS_ISO8859_1=m
121CONFIG_NLS_UTF8=m
122CONFIG_CRC_CCITT=m
123CONFIG_CRC_T10DIF=y
124CONFIG_XZ_DEC=y
125CONFIG_XZ_DEC_X86=y
126CONFIG_XZ_DEC_IA64=y
127CONFIG_XZ_DEC_ARM=y
128CONFIG_XZ_DEC_ARMTHUMB=y
129CONFIG_XZ_DEC_SPARC=y
130CONFIG_MAGIC_SYSRQ=y
131CONFIG_DEBUG_KERNEL=y
132CONFIG_DETECT_HUNG_TASK=y
133CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20
134CONFIG_CRYPTO_CBC=y
135CONFIG_CRYPTO_PCBC=m
136CONFIG_CRYPTO_MD5=y
137CONFIG_CRYPTO_MICHAEL_MIC=m
138CONFIG_CRYPTO_SHA1=m
139CONFIG_CRYPTO_BLOWFISH=m
140CONFIG_CRYPTO_DES=y
141CONFIG_CRYPTO_SERPENT=m
142CONFIG_CRYPTO_TWOFISH=m
143CONFIG_CRYPTO_DEFLATE=m
144# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig
index 8616fde0896f..4b6f8bf104e0 100644
--- a/arch/powerpc/configs/tqm8xx_defconfig
+++ b/arch/powerpc/configs/tqm8xx_defconfig
@@ -84,3 +84,4 @@ CONFIG_DEBUG_KERNEL=y
84CONFIG_DETECT_HUNG_TASK=y 84CONFIG_DETECT_HUNG_TASK=y
85CONFIG_DEBUG_INFO=y 85CONFIG_DEBUG_INFO=y
86# CONFIG_RCU_CPU_STALL_DETECTOR is not set 86# CONFIG_RCU_CPU_STALL_DETECTOR is not set
87CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 420b45368fcf..067fb0dca549 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -285,7 +285,7 @@ struct fsl_lbc_ctrl {
285 /* device info */ 285 /* device info */
286 struct device *dev; 286 struct device *dev;
287 struct fsl_lbc_regs __iomem *regs; 287 struct fsl_lbc_regs __iomem *regs;
288 int irq; 288 int irq[2];
289 wait_queue_head_t irq_wait; 289 wait_queue_head_t irq_wait;
290 spinlock_t lock; 290 spinlock_t lock;
291 void *nand; 291 void *nand;
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 1bd92fd43cfb..1503d8c7c41b 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -74,6 +74,7 @@
74#define BOOKE_INTERRUPT_GUEST_DBELL_CRIT 39 74#define BOOKE_INTERRUPT_GUEST_DBELL_CRIT 39
75#define BOOKE_INTERRUPT_HV_SYSCALL 40 75#define BOOKE_INTERRUPT_HV_SYSCALL 40
76#define BOOKE_INTERRUPT_HV_PRIV 41 76#define BOOKE_INTERRUPT_HV_PRIV 41
77#define BOOKE_INTERRUPT_LRAT_ERROR 42
77 78
78/* book3s */ 79/* book3s */
79 80
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 936db360790a..89b785d16846 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -286,8 +286,21 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
286extern int mmu_linear_psize; 286extern int mmu_linear_psize;
287extern int mmu_vmemmap_psize; 287extern int mmu_vmemmap_psize;
288 288
289struct tlb_core_data {
290 /* For software way selection, as on Freescale TLB1 */
291 u8 esel_next, esel_max, esel_first;
292
293 /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
294 u8 lock;
295};
296
289#ifdef CONFIG_PPC64 297#ifdef CONFIG_PPC64
290extern unsigned long linear_map_top; 298extern unsigned long linear_map_top;
299extern int book3e_htw_mode;
300
301#define PPC_HTW_NONE 0
302#define PPC_HTW_IBM 1
303#define PPC_HTW_E6500 2
291 304
292/* 305/*
293 * 64-bit booke platforms don't load the tlb in the tlb miss handler code. 306 * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 691fd8aca939..f8d1d6dcf7db 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -180,16 +180,17 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
180#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 180#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
181#define MMU_PAGE_256K 4 181#define MMU_PAGE_256K 4
182#define MMU_PAGE_1M 5 182#define MMU_PAGE_1M 5
183#define MMU_PAGE_4M 6 183#define MMU_PAGE_2M 6
184#define MMU_PAGE_8M 7 184#define MMU_PAGE_4M 7
185#define MMU_PAGE_16M 8 185#define MMU_PAGE_8M 8
186#define MMU_PAGE_64M 9 186#define MMU_PAGE_16M 9
187#define MMU_PAGE_256M 10 187#define MMU_PAGE_64M 10
188#define MMU_PAGE_1G 11 188#define MMU_PAGE_256M 11
189#define MMU_PAGE_16G 12 189#define MMU_PAGE_1G 12
190#define MMU_PAGE_64G 13 190#define MMU_PAGE_16G 13
191 191#define MMU_PAGE_64G 14
192#define MMU_PAGE_COUNT 14 192
193#define MMU_PAGE_COUNT 15
193 194
194#if defined(CONFIG_PPC_STD_MMU_64) 195#if defined(CONFIG_PPC_STD_MMU_64)
195/* 64-bit classic hash table MMU */ 196/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 68bee4636045..9c5dbc3833fb 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -112,6 +112,10 @@ struct paca_struct {
112 /* Keep pgd in the same cacheline as the start of extlb */ 112 /* Keep pgd in the same cacheline as the start of extlb */
113 pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */ 113 pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
114 pgd_t *kernel_pgd; /* Kernel PGD */ 114 pgd_t *kernel_pgd; /* Kernel PGD */
115
116 /* Shared by all threads of a core -- points to tcd of first thread */
117 struct tlb_core_data *tcd_ptr;
118
115 /* We can have up to 3 levels of reentrancy in the TLB miss handler */ 119 /* We can have up to 3 levels of reentrancy in the TLB miss handler */
116 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)]; 120 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
117 u64 exmc[8]; /* used for machine checks */ 121 u64 exmc[8]; /* used for machine checks */
@@ -122,6 +126,8 @@ struct paca_struct {
122 void *mc_kstack; 126 void *mc_kstack;
123 void *crit_kstack; 127 void *crit_kstack;
124 void *dbg_kstack; 128 void *dbg_kstack;
129
130 struct tlb_core_data tcd;
125#endif /* CONFIG_PPC_BOOK3E */ 131#endif /* CONFIG_PPC_BOOK3E */
126 132
127 mm_context_t context; 133 mm_context_t context;
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 7689e0e98d33..6586a40a46ce 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -294,6 +294,11 @@ n:
294 * you want to access various offsets within it). On ppc32 this is 294 * you want to access various offsets within it). On ppc32 this is
295 * identical to LOAD_REG_IMMEDIATE. 295 * identical to LOAD_REG_IMMEDIATE.
296 * 296 *
297 * LOAD_REG_ADDR_PIC(rn, name)
298 * Loads the address of label 'name' into register 'run'. Use this when
299 * the kernel doesn't run at the linked or relocated address. Please
300 * note that this macro will clobber the lr register.
301 *
297 * LOAD_REG_ADDRBASE(rn, name) 302 * LOAD_REG_ADDRBASE(rn, name)
298 * ADDROFF(name) 303 * ADDROFF(name)
299 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 304 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
@@ -304,6 +309,14 @@ n:
304 * LOAD_REG_ADDRBASE(rX, name) 309 * LOAD_REG_ADDRBASE(rX, name)
305 * ld rY,ADDROFF(name)(rX) 310 * ld rY,ADDROFF(name)(rX)
306 */ 311 */
312
313/* Be careful, this will clobber the lr register. */
314#define LOAD_REG_ADDR_PIC(reg, name) \
315 bl 0f; \
3160: mflr reg; \
317 addis reg,reg,(name - 0b)@ha; \
318 addi reg,reg,(name - 0b)@l;
319
307#ifdef __powerpc64__ 320#ifdef __powerpc64__
308#define LOAD_REG_IMMEDIATE(reg,expr) \ 321#define LOAD_REG_IMMEDIATE(reg,expr) \
309 lis reg,(expr)@highest; \ 322 lis reg,(expr)@highest; \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 232a2fa5b483..8ca20ac28dc2 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -256,6 +256,8 @@ struct thread_struct {
256 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 256 unsigned long evr[32]; /* upper 32-bits of SPE regs */
257 u64 acc; /* Accumulator */ 257 u64 acc; /* Accumulator */
258 unsigned long spefscr; /* SPE & eFP status */ 258 unsigned long spefscr; /* SPE & eFP status */
259 unsigned long spefscr_last; /* SPEFSCR value on last prctl
260 call or trap return */
259 int used_spe; /* set if process has used spe */ 261 int used_spe; /* set if process has used spe */
260#endif /* CONFIG_SPE */ 262#endif /* CONFIG_SPE */
261#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 263#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -317,7 +319,9 @@ struct thread_struct {
317 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 319 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
318 320
319#ifdef CONFIG_SPE 321#ifdef CONFIG_SPE
320#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 322#define SPEFSCR_INIT \
323 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
324 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
321#else 325#else
322#define SPEFSCR_INIT 326#define SPEFSCR_INIT
323#endif 327#endif
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fa8388ed94c5..62b114e079cf 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1075,6 +1075,8 @@
1075#define PVR_8560 0x80200000 1075#define PVR_8560 0x80200000
1076#define PVR_VER_E500V1 0x8020 1076#define PVR_VER_E500V1 0x8020
1077#define PVR_VER_E500V2 0x8021 1077#define PVR_VER_E500V2 0x8021
1078#define PVR_VER_E6500 0x8040
1079
1078/* 1080/*
1079 * For the 8xx processors, all of them report the same PVR family for 1081 * For the 8xx processors, all of them report the same PVR family for
1080 * the PowerPC core. The various versions of these processors must be 1082 * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 2e31aacd8acc..163c3b05a76e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -101,6 +101,7 @@
101#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */ 101#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
102#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */ 102#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
103#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */ 103#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
104#define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */
104#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */ 105#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */
105#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */ 106#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */
106#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */ 107#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */
@@ -170,6 +171,7 @@
170#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ 171#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
171#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 172#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
172#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 173#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
174#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
173#define SPRN_SVR 0x3FF /* System Version Register */ 175#define SPRN_SVR 0x3FF /* System Version Register */
174 176
175/* 177/*
@@ -216,6 +218,14 @@
216#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 218#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
217#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 219#define CCR1_TCS 0x00000080 /* Timer Clock Select */
218 220
221/* Bit definitions for PWRMGTCR0. */
222#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
223#define PWRMGTCR0_PW20_ENT_SHIFT 8
224#define PWRMGTCR0_PW20_ENT 0x3F00
225#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
226#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
227#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
228
219/* Bit definitions for the MCSR. */ 229/* Bit definitions for the MCSR. */
220#define MCSR_MCS 0x80000000 /* Machine Check Summary */ 230#define MCSR_MCS 0x80000000 /* Machine Check Summary */
221#define MCSR_IB 0x40000000 /* Instruction PLB Error */ 231#define MCSR_IB 0x40000000 /* Instruction PLB Error */
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 41a283956a29..ed8d68ce71f3 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -203,6 +203,15 @@ int main(void)
203 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack)); 203 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
204 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack)); 204 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
205 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack)); 205 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
206 DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
207
208 DEFINE(TCD_ESEL_NEXT,
209 offsetof(struct tlb_core_data, esel_next));
210 DEFINE(TCD_ESEL_MAX,
211 offsetof(struct tlb_core_data, esel_max));
212 DEFINE(TCD_ESEL_FIRST,
213 offsetof(struct tlb_core_data, esel_first));
214 DEFINE(TCD_LOCK, offsetof(struct tlb_core_data, lock));
206#endif /* CONFIG_PPC_BOOK3E */ 215#endif /* CONFIG_PPC_BOOK3E */
207 216
208#ifdef CONFIG_PPC_STD_MMU_64 217#ifdef CONFIG_PPC_STD_MMU_64
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7290b7..cc2d8962e090 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,57 @@ _GLOBAL(__e500_dcache_setup)
53 isync 53 isync
54 blr 54 blr
55 55
56/*
57 * FIXME - we haven't yet done testing to determine a reasonable default
58 * value for PW20_WAIT_IDLE_BIT.
59 */
60#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
61_GLOBAL(setup_pw20_idle)
62 mfspr r3, SPRN_PWRMGTCR0
63
64 /* Set PW20_WAIT bit, enable pw20 state*/
65 ori r3, r3, PWRMGTCR0_PW20_WAIT
66 li r11, PW20_WAIT_IDLE_BIT
67
68 /* Set Automatic PW20 Core Idle Count */
69 rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
70
71 mtspr SPRN_PWRMGTCR0, r3
72
73 blr
74
75/*
76 * FIXME - we haven't yet done testing to determine a reasonable default
77 * value for AV_WAIT_IDLE_BIT.
78 */
79#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
80_GLOBAL(setup_altivec_idle)
81 mfspr r3, SPRN_PWRMGTCR0
82
83 /* Enable Altivec Idle */
84 oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
85 li r11, AV_WAIT_IDLE_BIT
86
87 /* Set Automatic AltiVec Idle Count */
88 rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
89
90 mtspr SPRN_PWRMGTCR0, r3
91
92 blr
93
56_GLOBAL(__setup_cpu_e6500) 94_GLOBAL(__setup_cpu_e6500)
57 mflr r6 95 mflr r6
58#ifdef CONFIG_PPC64 96#ifdef CONFIG_PPC64
59 bl .setup_altivec_ivors 97 bl .setup_altivec_ivors
98 /* Touch IVOR42 only if the CPU supports E.HV category */
99 mfspr r10,SPRN_MMUCFG
100 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
101 beq 1f
102 bl .setup_lrat_ivor
1031:
60#endif 104#endif
105 bl setup_pw20_idle
106 bl setup_altivec_idle
61 bl __setup_cpu_e5500 107 bl __setup_cpu_e5500
62 mtlr r6 108 mtlr r6
63 blr 109 blr
@@ -119,6 +165,14 @@ _GLOBAL(__setup_cpu_e5500)
119_GLOBAL(__restore_cpu_e6500) 165_GLOBAL(__restore_cpu_e6500)
120 mflr r5 166 mflr r5
121 bl .setup_altivec_ivors 167 bl .setup_altivec_ivors
168 /* Touch IVOR42 only if the CPU supports E.HV category */
169 mfspr r10,SPRN_MMUCFG
170 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
171 beq 1f
172 bl .setup_lrat_ivor
1731:
174 bl .setup_pw20_idle
175 bl .setup_altivec_idle
122 bl __restore_cpu_e5500 176 bl __restore_cpu_e5500
123 mtlr r5 177 mtlr r5
124 blr 178 blr
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index e7751561fd1d..063b65dd4f27 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -308,6 +308,7 @@ interrupt_base_book3e: /* fake trap */
308 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 308 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
309 EXCEPTION_STUB(0x300, hypercall) 309 EXCEPTION_STUB(0x300, hypercall)
310 EXCEPTION_STUB(0x320, ehpriv) 310 EXCEPTION_STUB(0x320, ehpriv)
311 EXCEPTION_STUB(0x340, lrat_error)
311 312
312 .globl interrupt_end_book3e 313 .globl interrupt_end_book3e
313interrupt_end_book3e: 314interrupt_end_book3e:
@@ -677,6 +678,17 @@ kernel_dbg_exc:
677 bl .unknown_exception 678 bl .unknown_exception
678 b .ret_from_except 679 b .ret_from_except
679 680
681/* LRAT Error interrupt */
682 START_EXCEPTION(lrat_error);
683 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
684 PROLOG_ADDITION_NONE)
685 EXCEPTION_COMMON(0x340, PACA_EXGEN, INTS_KEEP)
686 addi r3,r1,STACK_FRAME_OVERHEAD
687 bl .save_nvgprs
688 INTS_RESTORE_HARD
689 bl .unknown_exception
690 b .ret_from_except
691
680/* 692/*
681 * An interrupt came in while soft-disabled; We mark paca->irq_happened 693 * An interrupt came in while soft-disabled; We mark paca->irq_happened
682 * accordingly and if the interrupt is level sensitive, we hard disable 694 * accordingly and if the interrupt is level sensitive, we hard disable
@@ -859,6 +871,7 @@ BAD_STACK_TRAMPOLINE(0x2e0)
859BAD_STACK_TRAMPOLINE(0x300) 871BAD_STACK_TRAMPOLINE(0x300)
860BAD_STACK_TRAMPOLINE(0x310) 872BAD_STACK_TRAMPOLINE(0x310)
861BAD_STACK_TRAMPOLINE(0x320) 873BAD_STACK_TRAMPOLINE(0x320)
874BAD_STACK_TRAMPOLINE(0x340)
862BAD_STACK_TRAMPOLINE(0x400) 875BAD_STACK_TRAMPOLINE(0x400)
863BAD_STACK_TRAMPOLINE(0x500) 876BAD_STACK_TRAMPOLINE(0x500)
864BAD_STACK_TRAMPOLINE(0x600) 877BAD_STACK_TRAMPOLINE(0x600)
@@ -1055,12 +1068,9 @@ skpinv: addi r6,r6,1 /* Increment */
1055 mtspr SPRN_MAS0,r3 1068 mtspr SPRN_MAS0,r3
1056 tlbre 1069 tlbre
1057 mfspr r6,SPRN_MAS1 1070 mfspr r6,SPRN_MAS1
1058 rlwinm r6,r6,0,2,0 /* clear IPROT */ 1071 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
1059 mtspr SPRN_MAS1,r6 1072 mtspr SPRN_MAS1,r6
1060 tlbwe 1073 tlbwe
1061
1062 /* Invalidate TLB1 */
1063 PPC_TLBILX_ALL(0,R0)
1064 sync 1074 sync
1065 isync 1075 isync
1066 1076
@@ -1114,12 +1124,9 @@ skpinv: addi r6,r6,1 /* Increment */
1114 mtspr SPRN_MAS0,r4 1124 mtspr SPRN_MAS0,r4
1115 tlbre 1125 tlbre
1116 mfspr r5,SPRN_MAS1 1126 mfspr r5,SPRN_MAS1
1117 rlwinm r5,r5,0,2,0 /* clear IPROT */ 1127 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
1118 mtspr SPRN_MAS1,r5 1128 mtspr SPRN_MAS1,r5
1119 tlbwe 1129 tlbwe
1120
1121 /* Invalidate TLB1 */
1122 PPC_TLBILX_ALL(0,R0)
1123 sync 1130 sync
1124 isync 1131 isync
1125 1132
@@ -1414,3 +1421,7 @@ _GLOBAL(setup_ehv_ivors)
1414 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1421 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1415 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1422 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1416 blr 1423 blr
1424
1425_GLOBAL(setup_lrat_ivor)
1426 SET_IVOR(42, 0x340) /* LRAT Error */
1427 blr
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
index a92c79be2728..f22e7e44fbf3 100644
--- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -176,6 +176,8 @@ skpinv: addi r6,r6,1 /* Increment */
176/* 7. Jump to KERNELBASE mapping */ 176/* 7. Jump to KERNELBASE mapping */
177 lis r6,(KERNELBASE & ~0xfff)@h 177 lis r6,(KERNELBASE & ~0xfff)@h
178 ori r6,r6,(KERNELBASE & ~0xfff)@l 178 ori r6,r6,(KERNELBASE & ~0xfff)@l
179 rlwinm r7,r25,0,0x03ffffff
180 add r6,r7,r6
179 181
180#elif defined(ENTRY_MAPPING_KEXEC_SETUP) 182#elif defined(ENTRY_MAPPING_KEXEC_SETUP)
181/* 183/*
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index f45726a1d963..b497188a94a1 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -65,29 +65,78 @@ _ENTRY(_start);
65 nop 65 nop
66 66
67 /* Translate device tree address to physical, save in r30/r31 */ 67 /* Translate device tree address to physical, save in r30/r31 */
68 mfmsr r16 68 bl get_phys_addr
69 mfspr r17,SPRN_PID 69 mr r30,r3
70 rlwinm r17,r17,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 70 mr r31,r4
71 rlwimi r17,r16,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
72 mtspr SPRN_MAS6,r17
73
74 tlbsx 0,r3 /* must succeed */
75
76 mfspr r16,SPRN_MAS1
77 mfspr r20,SPRN_MAS3
78 rlwinm r17,r16,25,0x1f /* r17 = log2(page size) */
79 li r18,1024
80 slw r18,r18,r17 /* r18 = page size */
81 addi r18,r18,-1
82 and r19,r3,r18 /* r19 = page offset */
83 andc r31,r20,r18 /* r31 = page base */
84 or r31,r31,r19 /* r31 = devtree phys addr */
85 mfspr r30,SPRN_MAS7
86 71
87 li r25,0 /* phys kernel start (low) */ 72 li r25,0 /* phys kernel start (low) */
88 li r24,0 /* CPU number */ 73 li r24,0 /* CPU number */
89 li r23,0 /* phys kernel start (high) */ 74 li r23,0 /* phys kernel start (high) */
90 75
76#ifdef CONFIG_RELOCATABLE
77 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
78
79 /* Translate _stext address to physical, save in r23/r25 */
80 bl get_phys_addr
81 mr r23,r3
82 mr r25,r4
83
84 bl 0f
850: mflr r8
86 addis r3,r8,(is_second_reloc - 0b)@ha
87 lwz r19,(is_second_reloc - 0b)@l(r3)
88
89 /* Check if this is the second relocation. */
90 cmpwi r19,1
91 bne 1f
92
93 /*
94 * For the second relocation, we already get the real memstart_addr
95 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
96 * then the virtual address of start kernel should be:
97 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
98 * Since the offset between kernstart_addr and memstart_addr should
99 * never be beyond 1G, so we can just use the lower 32bit of them
100 * for the calculation.
101 */
102 lis r3,PAGE_OFFSET@h
103
104 addis r4,r8,(kernstart_addr - 0b)@ha
105 addi r4,r4,(kernstart_addr - 0b)@l
106 lwz r5,4(r4)
107
108 addis r6,r8,(memstart_addr - 0b)@ha
109 addi r6,r6,(memstart_addr - 0b)@l
110 lwz r7,4(r6)
111
112 subf r5,r7,r5
113 add r3,r3,r5
114 b 2f
115
1161:
117 /*
118 * We have the runtime (virutal) address of our base.
119 * We calculate our shift of offset from a 64M page.
120 * We could map the 64M page we belong to at PAGE_OFFSET and
121 * get going from there.
122 */
123 lis r4,KERNELBASE@h
124 ori r4,r4,KERNELBASE@l
125 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
126 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
127 subf r3,r5,r6 /* r3 = r6 - r5 */
128 add r3,r4,r3 /* Required Virtual Address */
129
1302: bl relocate
131
132 /*
133 * For the second relocation, we already set the right tlb entries
134 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
135 */
136 cmpwi r19,1
137 beq set_ivor
138#endif
139
91/* We try to not make any assumptions about how the boot loader 140/* We try to not make any assumptions about how the boot loader
92 * setup or used the TLBs. We invalidate all mappings from the 141 * setup or used the TLBs. We invalidate all mappings from the
93 * boot loader and load a single entry in TLB1[0] to map the 142 * boot loader and load a single entry in TLB1[0] to map the
@@ -113,6 +162,7 @@ _ENTRY(__early_start)
113#include "fsl_booke_entry_mapping.S" 162#include "fsl_booke_entry_mapping.S"
114#undef ENTRY_MAPPING_BOOT_SETUP 163#undef ENTRY_MAPPING_BOOT_SETUP
115 164
165set_ivor:
116 /* Establish the interrupt vector offsets */ 166 /* Establish the interrupt vector offsets */
117 SET_IVOR(0, CriticalInput); 167 SET_IVOR(0, CriticalInput);
118 SET_IVOR(1, MachineCheck); 168 SET_IVOR(1, MachineCheck);
@@ -166,8 +216,7 @@ _ENTRY(__early_start)
166 /* Check to see if we're the second processor, and jump 216 /* Check to see if we're the second processor, and jump
167 * to the secondary_start code if so 217 * to the secondary_start code if so
168 */ 218 */
169 lis r24, boot_cpuid@h 219 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
170 ori r24, r24, boot_cpuid@l
171 lwz r24, 0(r24) 220 lwz r24, 0(r24)
172 cmpwi r24, -1 221 cmpwi r24, -1
173 mfspr r24,SPRN_PIR 222 mfspr r24,SPRN_PIR
@@ -197,6 +246,18 @@ _ENTRY(__early_start)
197 246
198 bl early_init 247 bl early_init
199 248
249#ifdef CONFIG_RELOCATABLE
250 mr r3,r30
251 mr r4,r31
252#ifdef CONFIG_PHYS_64BIT
253 mr r5,r23
254 mr r6,r25
255#else
256 mr r5,r25
257#endif
258 bl relocate_init
259#endif
260
200#ifdef CONFIG_DYNAMIC_MEMSTART 261#ifdef CONFIG_DYNAMIC_MEMSTART
201 lis r3,kernstart_addr@ha 262 lis r3,kernstart_addr@ha
202 la r3,kernstart_addr@l(r3) 263 la r3,kernstart_addr@l(r3)
@@ -856,6 +917,33 @@ KernelSPE:
856#endif /* CONFIG_SPE */ 917#endif /* CONFIG_SPE */
857 918
858/* 919/*
920 * Translate the effec addr in r3 to phys addr. The phys addr will be put
921 * into r3(higher 32bit) and r4(lower 32bit)
922 */
923get_phys_addr:
924 mfmsr r8
925 mfspr r9,SPRN_PID
926 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
927 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
928 mtspr SPRN_MAS6,r9
929
930 tlbsx 0,r3 /* must succeed */
931
932 mfspr r8,SPRN_MAS1
933 mfspr r12,SPRN_MAS3
934 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
935 li r10,1024
936 slw r10,r10,r9 /* r10 = page size */
937 addi r10,r10,-1
938 and r11,r3,r10 /* r11 = page offset */
939 andc r4,r12,r10 /* r4 = page base */
940 or r4,r4,r11 /* r4 = devtree phys addr */
941#ifdef CONFIG_PHYS_64BIT
942 mfspr r3,SPRN_MAS7
943#endif
944 blr
945
946/*
859 * Global functions 947 * Global functions
860 */ 948 */
861 949
@@ -1057,24 +1145,36 @@ _GLOBAL(__flush_disable_L1)
1057/* When we get here, r24 needs to hold the CPU # */ 1145/* When we get here, r24 needs to hold the CPU # */
1058 .globl __secondary_start 1146 .globl __secondary_start
1059__secondary_start: 1147__secondary_start:
1060 lis r3,__secondary_hold_acknowledge@h 1148 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1061 ori r3,r3,__secondary_hold_acknowledge@l 1149 lwz r3,0(r3)
1062 stw r24,0(r3)
1063
1064 li r3,0
1065 mr r4,r24 /* Why? */
1066 bl call_setup_cpu
1067
1068 lis r3,tlbcam_index@ha
1069 lwz r3,tlbcam_index@l(r3)
1070 mtctr r3 1150 mtctr r3
1071 li r26,0 /* r26 safe? */ 1151 li r26,0 /* r26 safe? */
1072 1152
1153 bl switch_to_as1
1154 mr r27,r3 /* tlb entry */
1073 /* Load each CAM entry */ 1155 /* Load each CAM entry */
10741: mr r3,r26 11561: mr r3,r26
1075 bl loadcam_entry 1157 bl loadcam_entry
1076 addi r26,r26,1 1158 addi r26,r26,1
1077 bdnz 1b 1159 bdnz 1b
1160 mr r3,r27 /* tlb entry */
1161 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1162 lwz r4,0(r4)
1163 mr r5,r25 /* phys kernel start */
1164 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1165 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1166 li r5,0 /* no device tree */
1167 li r6,0 /* not boot cpu */
1168 bl restore_to_as0
1169
1170
1171 lis r3,__secondary_hold_acknowledge@h
1172 ori r3,r3,__secondary_hold_acknowledge@l
1173 stw r24,0(r3)
1174
1175 li r3,0
1176 mr r4,r24 /* Why? */
1177 bl call_setup_cpu
1078 1178
1079 /* get current_thread_info and current */ 1179 /* get current_thread_info and current */
1080 lis r1,secondary_ti@ha 1180 lis r1,secondary_ti@ha
@@ -1111,6 +1211,112 @@ __secondary_hold_acknowledge:
1111#endif 1211#endif
1112 1212
1113/* 1213/*
1214 * Create a tlb entry with the same effective and physical address as
1215 * the tlb entry used by the current running code. But set the TS to 1.
1216 * Then switch to the address space 1. It will return with the r3 set to
1217 * the ESEL of the new created tlb.
1218 */
1219_GLOBAL(switch_to_as1)
1220 mflr r5
1221
1222 /* Find a entry not used */
1223 mfspr r3,SPRN_TLB1CFG
1224 andi. r3,r3,0xfff
1225 mfspr r4,SPRN_PID
1226 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1227 mtspr SPRN_MAS6,r4
12281: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1229 addi r3,r3,-1
1230 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1231 mtspr SPRN_MAS0,r4
1232 tlbre
1233 mfspr r4,SPRN_MAS1
1234 andis. r4,r4,MAS1_VALID@h
1235 bne 1b
1236
1237 /* Get the tlb entry used by the current running code */
1238 bl 0f
12390: mflr r4
1240 tlbsx 0,r4
1241
1242 mfspr r4,SPRN_MAS1
1243 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1244 mtspr SPRN_MAS1,r4
1245
1246 mfspr r4,SPRN_MAS0
1247 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1248 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1249 mtspr SPRN_MAS0,r4
1250 tlbwe
1251 isync
1252 sync
1253
1254 mfmsr r4
1255 ori r4,r4,MSR_IS | MSR_DS
1256 mtspr SPRN_SRR0,r5
1257 mtspr SPRN_SRR1,r4
1258 sync
1259 rfi
1260
1261/*
1262 * Restore to the address space 0 and also invalidate the tlb entry created
1263 * by switch_to_as1.
1264 * r3 - the tlb entry which should be invalidated
1265 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1266 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1267 * r6 - boot cpu
1268*/
1269_GLOBAL(restore_to_as0)
1270 mflr r0
1271
1272 bl 0f
12730: mflr r9
1274 addi r9,r9,1f - 0b
1275
1276 /*
1277 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1278 * so we need calculate the right jump and device tree address based
1279 * on the offset passed by r4.
1280 */
1281 add r9,r9,r4
1282 add r5,r5,r4
1283 add r0,r0,r4
1284
12852: mfmsr r7
1286 li r8,(MSR_IS | MSR_DS)
1287 andc r7,r7,r8
1288
1289 mtspr SPRN_SRR0,r9
1290 mtspr SPRN_SRR1,r7
1291 sync
1292 rfi
1293
1294 /* Invalidate the temporary tlb entry for AS1 */
12951: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1296 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1297 mtspr SPRN_MAS0,r9
1298 tlbre
1299 mfspr r9,SPRN_MAS1
1300 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1301 mtspr SPRN_MAS1,r9
1302 tlbwe
1303 isync
1304
1305 cmpwi r4,0
1306 cmpwi cr1,r6,0
1307 cror eq,4*cr1+eq,eq
1308 bne 3f /* offset != 0 && is_boot_cpu */
1309 mtlr r0
1310 blr
1311
1312 /*
1313 * The PAGE_OFFSET will map to a different physical address,
1314 * jump to _start to do another relocation again.
1315 */
13163: mr r3,r5
1317 bl _start
1318
1319/*
1114 * We put a few things here that have to be page-aligned. This stuff 1320 * We put a few things here that have to be page-aligned. This stuff
1115 * goes at the beginning of the data segment, which is page-aligned. 1321 * goes at the beginning of the data segment, which is page-aligned.
1116 */ 1322 */
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 623c356fe34f..bf0aada02fe4 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -160,6 +160,11 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
160#ifdef CONFIG_PPC_STD_MMU_64 160#ifdef CONFIG_PPC_STD_MMU_64
161 new_paca->slb_shadow_ptr = init_slb_shadow(cpu); 161 new_paca->slb_shadow_ptr = init_slb_shadow(cpu);
162#endif /* CONFIG_PPC_STD_MMU_64 */ 162#endif /* CONFIG_PPC_STD_MMU_64 */
163
164#ifdef CONFIG_PPC_BOOK3E
165 /* For now -- if we have threads this will be adjusted later */
166 new_paca->tcd_ptr = &new_paca->tcd;
167#endif
163} 168}
164 169
165/* Put the paca pointer into r13 and SPRG_PACA */ 170/* Put the paca pointer into r13 and SPRG_PACA */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 3573d186505f..5fc5906ec337 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1296,6 +1296,19 @@ int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1296 if (val & PR_FP_EXC_SW_ENABLE) { 1296 if (val & PR_FP_EXC_SW_ENABLE) {
1297#ifdef CONFIG_SPE 1297#ifdef CONFIG_SPE
1298 if (cpu_has_feature(CPU_FTR_SPE)) { 1298 if (cpu_has_feature(CPU_FTR_SPE)) {
1299 /*
1300 * When the sticky exception bits are set
1301 * directly by userspace, it must call prctl
1302 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1303 * in the existing prctl settings) or
1304 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1305 * the bits being set). <fenv.h> functions
1306 * saving and restoring the whole
1307 * floating-point environment need to do so
1308 * anyway to restore the prctl settings from
1309 * the saved environment.
1310 */
1311 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1299 tsk->thread.fpexc_mode = val & 1312 tsk->thread.fpexc_mode = val &
1300 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1313 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1301 return 0; 1314 return 0;
@@ -1327,9 +1340,22 @@ int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1327 1340
1328 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1341 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1329#ifdef CONFIG_SPE 1342#ifdef CONFIG_SPE
1330 if (cpu_has_feature(CPU_FTR_SPE)) 1343 if (cpu_has_feature(CPU_FTR_SPE)) {
1344 /*
1345 * When the sticky exception bits are set
1346 * directly by userspace, it must call prctl
1347 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1348 * in the existing prctl settings) or
1349 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1350 * the bits being set). <fenv.h> functions
1351 * saving and restoring the whole
1352 * floating-point environment need to do so
1353 * anyway to restore the prctl settings from
1354 * the saved environment.
1355 */
1356 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1331 val = tsk->thread.fpexc_mode; 1357 val = tsk->thread.fpexc_mode;
1332 else 1358 } else
1333 return -EINVAL; 1359 return -EINVAL;
1334#else 1360#else
1335 return -EINVAL; 1361 return -EINVAL;
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index fa0ad8aafbcc..f58c0d3aaeb4 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -523,6 +523,20 @@ static int __init early_init_dt_scan_memory_ppc(unsigned long node,
523 return early_init_dt_scan_memory(node, uname, depth, data); 523 return early_init_dt_scan_memory(node, uname, depth, data);
524} 524}
525 525
526/*
527 * For a relocatable kernel, we need to get the memstart_addr first,
528 * then use it to calculate the virtual kernel start address. This has
529 * to happen at a very early stage (before machine_init). In this case,
530 * we just want to get the memstart_address and would not like to mess the
531 * memblock at this stage. So introduce a variable to skip the memblock_add()
532 * for this reason.
533 */
534#ifdef CONFIG_RELOCATABLE
535static int add_mem_to_memblock = 1;
536#else
537#define add_mem_to_memblock 1
538#endif
539
526void __init early_init_dt_add_memory_arch(u64 base, u64 size) 540void __init early_init_dt_add_memory_arch(u64 base, u64 size)
527{ 541{
528#ifdef CONFIG_PPC64 542#ifdef CONFIG_PPC64
@@ -543,7 +557,8 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
543 } 557 }
544 558
545 /* Add the chunk to the MEMBLOCK list */ 559 /* Add the chunk to the MEMBLOCK list */
546 memblock_add(base, size); 560 if (add_mem_to_memblock)
561 memblock_add(base, size);
547} 562}
548 563
549static void __init early_reserve_mem_dt(void) 564static void __init early_reserve_mem_dt(void)
@@ -740,6 +755,30 @@ void __init early_init_devtree(void *params)
740 DBG(" <- early_init_devtree()\n"); 755 DBG(" <- early_init_devtree()\n");
741} 756}
742 757
758#ifdef CONFIG_RELOCATABLE
759/*
760 * This function run before early_init_devtree, so we have to init
761 * initial_boot_params.
762 */
763void __init early_get_first_memblock_info(void *params, phys_addr_t *size)
764{
765 /* Setup flat device-tree pointer */
766 initial_boot_params = params;
767
768 /*
769 * Scan the memory nodes and set add_mem_to_memblock to 0 to avoid
770 * mess the memblock.
771 */
772 add_mem_to_memblock = 0;
773 of_scan_flat_dt(early_init_dt_scan_root, NULL);
774 of_scan_flat_dt(early_init_dt_scan_memory_ppc, NULL);
775 add_mem_to_memblock = 1;
776
777 if (size)
778 *size = first_memblock_size;
779}
780#endif
781
743/******* 782/*******
744 * 783 *
745 * New implementation of the OF "find" APIs, return a refcounted 784 * New implementation of the OF "find" APIs, return a refcounted
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 2232aff66059..1ce9b87d7df8 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -97,6 +97,36 @@ int dcache_bsize;
97int icache_bsize; 97int icache_bsize;
98int ucache_bsize; 98int ucache_bsize;
99 99
100#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
101static void setup_tlb_core_data(void)
102{
103 int cpu;
104
105 for_each_possible_cpu(cpu) {
106 int first = cpu_first_thread_sibling(cpu);
107
108 paca[cpu].tcd_ptr = &paca[first].tcd;
109
110 /*
111 * If we have threads, we need either tlbsrx.
112 * or e6500 tablewalk mode, or else TLB handlers
113 * will be racy and could produce duplicate entries.
114 */
115 if (smt_enabled_at_boot >= 2 &&
116 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
117 book3e_htw_mode != PPC_HTW_E6500) {
118 /* Should we panic instead? */
119 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
120 __func__);
121 }
122 }
123}
124#else
125static void setup_tlb_core_data(void)
126{
127}
128#endif
129
100#ifdef CONFIG_SMP 130#ifdef CONFIG_SMP
101 131
102static char *smt_enabled_cmdline; 132static char *smt_enabled_cmdline;
@@ -445,6 +475,7 @@ void __init setup_system(void)
445 475
446 smp_setup_cpu_maps(); 476 smp_setup_cpu_maps();
447 check_smt_enabled(); 477 check_smt_enabled();
478 setup_tlb_core_data();
448 479
449#ifdef CONFIG_SMP 480#ifdef CONFIG_SMP
450 /* Release secondary cpus out of their spinloops at 0x60 now that 481 /* Release secondary cpus out of their spinloops at 0x60 now that
diff --git a/arch/powerpc/kernel/swsusp_booke.S b/arch/powerpc/kernel/swsusp_booke.S
index 0f204053e5b5..553c1405ee05 100644
--- a/arch/powerpc/kernel/swsusp_booke.S
+++ b/arch/powerpc/kernel/swsusp_booke.S
@@ -74,21 +74,21 @@ _GLOBAL(swsusp_arch_suspend)
74 bne 1b 74 bne 1b
75 75
76 /* Save SPRGs */ 76 /* Save SPRGs */
77 mfsprg r4,0 77 mfspr r4,SPRN_SPRG0
78 stw r4,SL_SPRG0(r11) 78 stw r4,SL_SPRG0(r11)
79 mfsprg r4,1 79 mfspr r4,SPRN_SPRG1
80 stw r4,SL_SPRG1(r11) 80 stw r4,SL_SPRG1(r11)
81 mfsprg r4,2 81 mfspr r4,SPRN_SPRG2
82 stw r4,SL_SPRG2(r11) 82 stw r4,SL_SPRG2(r11)
83 mfsprg r4,3 83 mfspr r4,SPRN_SPRG3
84 stw r4,SL_SPRG3(r11) 84 stw r4,SL_SPRG3(r11)
85 mfsprg r4,4 85 mfspr r4,SPRN_SPRG4
86 stw r4,SL_SPRG4(r11) 86 stw r4,SL_SPRG4(r11)
87 mfsprg r4,5 87 mfspr r4,SPRN_SPRG5
88 stw r4,SL_SPRG5(r11) 88 stw r4,SL_SPRG5(r11)
89 mfsprg r4,6 89 mfspr r4,SPRN_SPRG6
90 stw r4,SL_SPRG6(r11) 90 stw r4,SL_SPRG6(r11)
91 mfsprg r4,7 91 mfspr r4,SPRN_SPRG7
92 stw r4,SL_SPRG7(r11) 92 stw r4,SL_SPRG7(r11)
93 93
94 /* Call the low level suspend stuff (we should probably have made 94 /* Call the low level suspend stuff (we should probably have made
@@ -150,21 +150,21 @@ _GLOBAL(swsusp_arch_resume)
150 bl _tlbil_all 150 bl _tlbil_all
151 151
152 lwz r4,SL_SPRG0(r11) 152 lwz r4,SL_SPRG0(r11)
153 mtsprg 0,r4 153 mtspr SPRN_SPRG0,r4
154 lwz r4,SL_SPRG1(r11) 154 lwz r4,SL_SPRG1(r11)
155 mtsprg 1,r4 155 mtspr SPRN_SPRG1,r4
156 lwz r4,SL_SPRG2(r11) 156 lwz r4,SL_SPRG2(r11)
157 mtsprg 2,r4 157 mtspr SPRN_SPRG2,r4
158 lwz r4,SL_SPRG3(r11) 158 lwz r4,SL_SPRG3(r11)
159 mtsprg 3,r4 159 mtspr SPRN_SPRG3,r4
160 lwz r4,SL_SPRG4(r11) 160 lwz r4,SL_SPRG4(r11)
161 mtsprg 4,r4 161 mtspr SPRN_SPRG4,r4
162 lwz r4,SL_SPRG5(r11) 162 lwz r4,SL_SPRG5(r11)
163 mtsprg 5,r4 163 mtspr SPRN_SPRG5,r4
164 lwz r4,SL_SPRG6(r11) 164 lwz r4,SL_SPRG6(r11)
165 mtsprg 6,r4 165 mtspr SPRN_SPRG6,r4
166 lwz r4,SL_SPRG7(r11) 166 lwz r4,SL_SPRG7(r11)
167 mtsprg 7,r4 167 mtspr SPRN_SPRG7,r4
168 168
169 /* restore the MSR */ 169 /* restore the MSR */
170 lwz r3,SL_MSR(r11) 170 lwz r3,SL_MSR(r11)
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index cad777eb613a..d4a43e64a6a9 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -86,6 +86,304 @@ __setup("smt-snooze-delay=", setup_smt_snooze_delay);
86 86
87#endif /* CONFIG_PPC64 */ 87#endif /* CONFIG_PPC64 */
88 88
89#ifdef CONFIG_PPC_FSL_BOOK3E
90#define MAX_BIT 63
91
92static u64 pw20_wt;
93static u64 altivec_idle_wt;
94
95static unsigned int get_idle_ticks_bit(u64 ns)
96{
97 u64 cycle;
98
99 if (ns >= 10000)
100 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
101 else
102 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
103
104 if (!cycle)
105 return 0;
106
107 return ilog2(cycle);
108}
109
110static void do_show_pwrmgtcr0(void *val)
111{
112 u32 *value = val;
113
114 *value = mfspr(SPRN_PWRMGTCR0);
115}
116
117static ssize_t show_pw20_state(struct device *dev,
118 struct device_attribute *attr, char *buf)
119{
120 u32 value;
121 unsigned int cpu = dev->id;
122
123 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
124
125 value &= PWRMGTCR0_PW20_WAIT;
126
127 return sprintf(buf, "%u\n", value ? 1 : 0);
128}
129
130static void do_store_pw20_state(void *val)
131{
132 u32 *value = val;
133 u32 pw20_state;
134
135 pw20_state = mfspr(SPRN_PWRMGTCR0);
136
137 if (*value)
138 pw20_state |= PWRMGTCR0_PW20_WAIT;
139 else
140 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
141
142 mtspr(SPRN_PWRMGTCR0, pw20_state);
143}
144
145static ssize_t store_pw20_state(struct device *dev,
146 struct device_attribute *attr,
147 const char *buf, size_t count)
148{
149 u32 value;
150 unsigned int cpu = dev->id;
151
152 if (kstrtou32(buf, 0, &value))
153 return -EINVAL;
154
155 if (value > 1)
156 return -EINVAL;
157
158 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
159
160 return count;
161}
162
163static ssize_t show_pw20_wait_time(struct device *dev,
164 struct device_attribute *attr, char *buf)
165{
166 u32 value;
167 u64 tb_cycle = 1;
168 u64 time;
169
170 unsigned int cpu = dev->id;
171
172 if (!pw20_wt) {
173 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
174 value = (value & PWRMGTCR0_PW20_ENT) >>
175 PWRMGTCR0_PW20_ENT_SHIFT;
176
177 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
178 /* convert ms to ns */
179 if (tb_ticks_per_usec > 1000) {
180 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
181 } else {
182 u32 rem_us;
183
184 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
185 &rem_us);
186 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
187 }
188 } else {
189 time = pw20_wt;
190 }
191
192 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
193}
194
195static void set_pw20_wait_entry_bit(void *val)
196{
197 u32 *value = val;
198 u32 pw20_idle;
199
200 pw20_idle = mfspr(SPRN_PWRMGTCR0);
201
202 /* Set Automatic PW20 Core Idle Count */
203 /* clear count */
204 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
205
206 /* set count */
207 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
208
209 mtspr(SPRN_PWRMGTCR0, pw20_idle);
210}
211
212static ssize_t store_pw20_wait_time(struct device *dev,
213 struct device_attribute *attr,
214 const char *buf, size_t count)
215{
216 u32 entry_bit;
217 u64 value;
218
219 unsigned int cpu = dev->id;
220
221 if (kstrtou64(buf, 0, &value))
222 return -EINVAL;
223
224 if (!value)
225 return -EINVAL;
226
227 entry_bit = get_idle_ticks_bit(value);
228 if (entry_bit > MAX_BIT)
229 return -EINVAL;
230
231 pw20_wt = value;
232
233 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
234 &entry_bit, 1);
235
236 return count;
237}
238
239static ssize_t show_altivec_idle(struct device *dev,
240 struct device_attribute *attr, char *buf)
241{
242 u32 value;
243 unsigned int cpu = dev->id;
244
245 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
246
247 value &= PWRMGTCR0_AV_IDLE_PD_EN;
248
249 return sprintf(buf, "%u\n", value ? 1 : 0);
250}
251
252static void do_store_altivec_idle(void *val)
253{
254 u32 *value = val;
255 u32 altivec_idle;
256
257 altivec_idle = mfspr(SPRN_PWRMGTCR0);
258
259 if (*value)
260 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
261 else
262 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
263
264 mtspr(SPRN_PWRMGTCR0, altivec_idle);
265}
266
267static ssize_t store_altivec_idle(struct device *dev,
268 struct device_attribute *attr,
269 const char *buf, size_t count)
270{
271 u32 value;
272 unsigned int cpu = dev->id;
273
274 if (kstrtou32(buf, 0, &value))
275 return -EINVAL;
276
277 if (value > 1)
278 return -EINVAL;
279
280 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
281
282 return count;
283}
284
285static ssize_t show_altivec_idle_wait_time(struct device *dev,
286 struct device_attribute *attr, char *buf)
287{
288 u32 value;
289 u64 tb_cycle = 1;
290 u64 time;
291
292 unsigned int cpu = dev->id;
293
294 if (!altivec_idle_wt) {
295 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
296 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
297 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
298
299 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
300 /* convert ms to ns */
301 if (tb_ticks_per_usec > 1000) {
302 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
303 } else {
304 u32 rem_us;
305
306 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
307 &rem_us);
308 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
309 }
310 } else {
311 time = altivec_idle_wt;
312 }
313
314 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
315}
316
317static void set_altivec_idle_wait_entry_bit(void *val)
318{
319 u32 *value = val;
320 u32 altivec_idle;
321
322 altivec_idle = mfspr(SPRN_PWRMGTCR0);
323
324 /* Set Automatic AltiVec Idle Count */
325 /* clear count */
326 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
327
328 /* set count */
329 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
330
331 mtspr(SPRN_PWRMGTCR0, altivec_idle);
332}
333
334static ssize_t store_altivec_idle_wait_time(struct device *dev,
335 struct device_attribute *attr,
336 const char *buf, size_t count)
337{
338 u32 entry_bit;
339 u64 value;
340
341 unsigned int cpu = dev->id;
342
343 if (kstrtou64(buf, 0, &value))
344 return -EINVAL;
345
346 if (!value)
347 return -EINVAL;
348
349 entry_bit = get_idle_ticks_bit(value);
350 if (entry_bit > MAX_BIT)
351 return -EINVAL;
352
353 altivec_idle_wt = value;
354
355 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
356 &entry_bit, 1);
357
358 return count;
359}
360
361/*
362 * Enable/Disable interface:
363 * 0, disable. 1, enable.
364 */
365static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
366static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
367
368/*
369 * Set wait time interface:(Nanosecond)
370 * Example: Base on TBfreq is 41MHZ.
371 * 1~48(ns): TB[63]
372 * 49~97(ns): TB[62]
373 * 98~195(ns): TB[61]
374 * 196~390(ns): TB[60]
375 * 391~780(ns): TB[59]
376 * 781~1560(ns): TB[58]
377 * ...
378 */
379static DEVICE_ATTR(pw20_wait_time, 0600,
380 show_pw20_wait_time,
381 store_pw20_wait_time);
382static DEVICE_ATTR(altivec_idle_wait_time, 0600,
383 show_altivec_idle_wait_time,
384 store_altivec_idle_wait_time);
385#endif
386
89/* 387/*
90 * Enabling PMCs will slow partition context switch times so we only do 388 * Enabling PMCs will slow partition context switch times so we only do
91 * it the first time we write to the PMCs. 389 * it the first time we write to the PMCs.
@@ -425,6 +723,15 @@ static void register_cpu_online(unsigned int cpu)
425 device_create_file(s, &dev_attr_pir); 723 device_create_file(s, &dev_attr_pir);
426#endif /* CONFIG_PPC64 */ 724#endif /* CONFIG_PPC64 */
427 725
726#ifdef CONFIG_PPC_FSL_BOOK3E
727 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
728 device_create_file(s, &dev_attr_pw20_state);
729 device_create_file(s, &dev_attr_pw20_wait_time);
730
731 device_create_file(s, &dev_attr_altivec_idle);
732 device_create_file(s, &dev_attr_altivec_idle_wait_time);
733 }
734#endif
428 cacheinfo_cpu_online(cpu); 735 cacheinfo_cpu_online(cpu);
429} 736}
430 737
@@ -497,6 +804,15 @@ static void unregister_cpu_online(unsigned int cpu)
497 device_remove_file(s, &dev_attr_pir); 804 device_remove_file(s, &dev_attr_pir);
498#endif /* CONFIG_PPC64 */ 805#endif /* CONFIG_PPC64 */
499 806
807#ifdef CONFIG_PPC_FSL_BOOK3E
808 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
809 device_remove_file(s, &dev_attr_pw20_state);
810 device_remove_file(s, &dev_attr_pw20_wait_time);
811
812 device_remove_file(s, &dev_attr_altivec_idle);
813 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
814 }
815#endif
500 cacheinfo_cpu_offline(cpu); 816 cacheinfo_cpu_offline(cpu);
501} 817}
502 818
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index e8ed7d659c55..a0d6929d8678 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -319,6 +319,8 @@ kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
319 SPRN_DSRR0, SPRN_DSRR1, 0 319 SPRN_DSRR0, SPRN_DSRR1, 0
320kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \ 320kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
321 SPRN_CSRR0, SPRN_CSRR1, 0 321 SPRN_CSRR0, SPRN_CSRR1, 0
322kvm_handler BOOKE_INTERRUPT_LRAT_ERROR, EX_PARAMS(GEN), \
323 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
322#else 324#else
323/* 325/*
324 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h 326 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c
index a73f0884d358..28337c9709ae 100644
--- a/arch/powerpc/math-emu/math_efp.c
+++ b/arch/powerpc/math-emu/math_efp.c
@@ -20,6 +20,7 @@
20 */ 20 */
21 21
22#include <linux/types.h> 22#include <linux/types.h>
23#include <linux/prctl.h>
23 24
24#include <asm/uaccess.h> 25#include <asm/uaccess.h>
25#include <asm/reg.h> 26#include <asm/reg.h>
@@ -275,21 +276,13 @@ int do_spe_mathemu(struct pt_regs *regs)
275 276
276 case EFSCTSF: 277 case EFSCTSF:
277 case EFSCTUF: 278 case EFSCTUF:
278 if (!((vb.wp[1] >> 23) == 0xff && ((vb.wp[1] & 0x7fffff) > 0))) { 279 if (SB_c == FP_CLS_NAN) {
279 /* NaN */ 280 vc.wp[1] = 0;
280 if (((vb.wp[1] >> 23) & 0xff) == 0) { 281 FP_SET_EXCEPTION(FP_EX_INVALID);
281 /* denorm */ 282 } else {
282 vc.wp[1] = 0x0; 283 SB_e += (func == EFSCTSF ? 31 : 32);
283 } else if ((vb.wp[1] >> 31) == 0) { 284 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
284 /* positive normal */ 285 (func == EFSCTSF));
285 vc.wp[1] = (func == EFSCTSF) ?
286 0x7fffffff : 0xffffffff;
287 } else { /* negative normal */
288 vc.wp[1] = (func == EFSCTSF) ?
289 0x80000000 : 0x0;
290 }
291 } else { /* rB is NaN */
292 vc.wp[1] = 0x0;
293 } 286 }
294 goto update_regs; 287 goto update_regs;
295 288
@@ -306,16 +299,25 @@ int do_spe_mathemu(struct pt_regs *regs)
306 } 299 }
307 300
308 case EFSCTSI: 301 case EFSCTSI:
309 case EFSCTSIZ:
310 case EFSCTUI: 302 case EFSCTUI:
303 if (SB_c == FP_CLS_NAN) {
304 vc.wp[1] = 0;
305 FP_SET_EXCEPTION(FP_EX_INVALID);
306 } else {
307 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
308 ((func & 0x3) != 0));
309 }
310 goto update_regs;
311
312 case EFSCTSIZ:
311 case EFSCTUIZ: 313 case EFSCTUIZ:
312 if (func & 0x4) { 314 if (SB_c == FP_CLS_NAN) {
313 _FP_ROUND(1, SB); 315 vc.wp[1] = 0;
316 FP_SET_EXCEPTION(FP_EX_INVALID);
314 } else { 317 } else {
315 _FP_ROUND_ZERO(1, SB); 318 FP_TO_INT_S(vc.wp[1], SB, 32,
319 ((func & 0x3) != 0));
316 } 320 }
317 FP_TO_INT_S(vc.wp[1], SB, 32,
318 (((func & 0x3) != 0) || SB_s));
319 goto update_regs; 321 goto update_regs;
320 322
321 default: 323 default:
@@ -404,22 +406,13 @@ cmp_s:
404 406
405 case EFDCTSF: 407 case EFDCTSF:
406 case EFDCTUF: 408 case EFDCTUF:
407 if (!((vb.wp[0] >> 20) == 0x7ff && 409 if (DB_c == FP_CLS_NAN) {
408 ((vb.wp[0] & 0xfffff) > 0 || (vb.wp[1] > 0)))) { 410 vc.wp[1] = 0;
409 /* not a NaN */ 411 FP_SET_EXCEPTION(FP_EX_INVALID);
410 if (((vb.wp[0] >> 20) & 0x7ff) == 0) { 412 } else {
411 /* denorm */ 413 DB_e += (func == EFDCTSF ? 31 : 32);
412 vc.wp[1] = 0x0; 414 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
413 } else if ((vb.wp[0] >> 31) == 0) { 415 (func == EFDCTSF));
414 /* positive normal */
415 vc.wp[1] = (func == EFDCTSF) ?
416 0x7fffffff : 0xffffffff;
417 } else { /* negative normal */
418 vc.wp[1] = (func == EFDCTSF) ?
419 0x80000000 : 0x0;
420 }
421 } else { /* NaN */
422 vc.wp[1] = 0x0;
423 } 416 }
424 goto update_regs; 417 goto update_regs;
425 418
@@ -437,21 +430,35 @@ cmp_s:
437 430
438 case EFDCTUIDZ: 431 case EFDCTUIDZ:
439 case EFDCTSIDZ: 432 case EFDCTSIDZ:
440 _FP_ROUND_ZERO(2, DB); 433 if (DB_c == FP_CLS_NAN) {
441 FP_TO_INT_D(vc.dp[0], DB, 64, ((func & 0x1) == 0)); 434 vc.dp[0] = 0;
435 FP_SET_EXCEPTION(FP_EX_INVALID);
436 } else {
437 FP_TO_INT_D(vc.dp[0], DB, 64,
438 ((func & 0x1) == 0));
439 }
442 goto update_regs; 440 goto update_regs;
443 441
444 case EFDCTUI: 442 case EFDCTUI:
445 case EFDCTSI: 443 case EFDCTSI:
444 if (DB_c == FP_CLS_NAN) {
445 vc.wp[1] = 0;
446 FP_SET_EXCEPTION(FP_EX_INVALID);
447 } else {
448 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
449 ((func & 0x3) != 0));
450 }
451 goto update_regs;
452
446 case EFDCTUIZ: 453 case EFDCTUIZ:
447 case EFDCTSIZ: 454 case EFDCTSIZ:
448 if (func & 0x4) { 455 if (DB_c == FP_CLS_NAN) {
449 _FP_ROUND(2, DB); 456 vc.wp[1] = 0;
457 FP_SET_EXCEPTION(FP_EX_INVALID);
450 } else { 458 } else {
451 _FP_ROUND_ZERO(2, DB); 459 FP_TO_INT_D(vc.wp[1], DB, 32,
460 ((func & 0x3) != 0));
452 } 461 }
453 FP_TO_INT_D(vc.wp[1], DB, 32,
454 (((func & 0x3) != 0) || DB_s));
455 goto update_regs; 462 goto update_regs;
456 463
457 default: 464 default:
@@ -556,37 +563,60 @@ cmp_d:
556 cmp = -1; 563 cmp = -1;
557 goto cmp_vs; 564 goto cmp_vs;
558 565
559 case EVFSCTSF:
560 __asm__ __volatile__ ("mtspr 512, %4\n"
561 "efsctsf %0, %2\n"
562 "efsctsf %1, %3\n"
563 : "=r" (vc.wp[0]), "=r" (vc.wp[1])
564 : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
565 goto update_regs;
566
567 case EVFSCTUF: 566 case EVFSCTUF:
568 __asm__ __volatile__ ("mtspr 512, %4\n" 567 case EVFSCTSF:
569 "efsctuf %0, %2\n" 568 if (SB0_c == FP_CLS_NAN) {
570 "efsctuf %1, %3\n" 569 vc.wp[0] = 0;
571 : "=r" (vc.wp[0]), "=r" (vc.wp[1]) 570 FP_SET_EXCEPTION(FP_EX_INVALID);
572 : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0)); 571 } else {
572 SB0_e += (func == EVFSCTSF ? 31 : 32);
573 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
574 (func == EVFSCTSF));
575 }
576 if (SB1_c == FP_CLS_NAN) {
577 vc.wp[1] = 0;
578 FP_SET_EXCEPTION(FP_EX_INVALID);
579 } else {
580 SB1_e += (func == EVFSCTSF ? 31 : 32);
581 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
582 (func == EVFSCTSF));
583 }
573 goto update_regs; 584 goto update_regs;
574 585
575 case EVFSCTUI: 586 case EVFSCTUI:
576 case EVFSCTSI: 587 case EVFSCTSI:
588 if (SB0_c == FP_CLS_NAN) {
589 vc.wp[0] = 0;
590 FP_SET_EXCEPTION(FP_EX_INVALID);
591 } else {
592 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
593 ((func & 0x3) != 0));
594 }
595 if (SB1_c == FP_CLS_NAN) {
596 vc.wp[1] = 0;
597 FP_SET_EXCEPTION(FP_EX_INVALID);
598 } else {
599 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
600 ((func & 0x3) != 0));
601 }
602 goto update_regs;
603
577 case EVFSCTUIZ: 604 case EVFSCTUIZ:
578 case EVFSCTSIZ: 605 case EVFSCTSIZ:
579 if (func & 0x4) { 606 if (SB0_c == FP_CLS_NAN) {
580 _FP_ROUND(1, SB0); 607 vc.wp[0] = 0;
581 _FP_ROUND(1, SB1); 608 FP_SET_EXCEPTION(FP_EX_INVALID);
582 } else { 609 } else {
583 _FP_ROUND_ZERO(1, SB0); 610 FP_TO_INT_S(vc.wp[0], SB0, 32,
584 _FP_ROUND_ZERO(1, SB1); 611 ((func & 0x3) != 0));
612 }
613 if (SB1_c == FP_CLS_NAN) {
614 vc.wp[1] = 0;
615 FP_SET_EXCEPTION(FP_EX_INVALID);
616 } else {
617 FP_TO_INT_S(vc.wp[1], SB1, 32,
618 ((func & 0x3) != 0));
585 } 619 }
586 FP_TO_INT_S(vc.wp[0], SB0, 32,
587 (((func & 0x3) != 0) || SB0_s));
588 FP_TO_INT_S(vc.wp[1], SB1, 32,
589 (((func & 0x3) != 0) || SB1_s));
590 goto update_regs; 620 goto update_regs;
591 621
592 default: 622 default:
@@ -630,9 +660,27 @@ update_ccr:
630 regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2)); 660 regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
631 661
632update_regs: 662update_regs:
633 __FPU_FPSCR &= ~FP_EX_MASK; 663 /*
664 * If the "invalid" exception sticky bit was set by the
665 * processor for non-finite input, but was not set before the
666 * instruction being emulated, clear it. Likewise for the
667 * "underflow" bit, which may have been set by the processor
668 * for exact underflow, not just inexact underflow when the
669 * flag should be set for IEEE 754 semantics. Other sticky
670 * exceptions will only be set by the processor when they are
671 * correct according to IEEE 754 semantics, and we must not
672 * clear sticky bits that were already set before the emulated
673 * instruction as they represent the user-visible sticky
674 * exception status. "inexact" traps to kernel are not
675 * required for IEEE semantics and are not enabled by default,
676 * so the "inexact" sticky bit may have been set by a previous
677 * instruction without the kernel being aware of it.
678 */
679 __FPU_FPSCR
680 &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last;
634 __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK); 681 __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
635 mtspr(SPRN_SPEFSCR, __FPU_FPSCR); 682 mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
683 current->thread.spefscr_last = __FPU_FPSCR;
636 684
637 current->thread.evr[fc] = vc.wp[0]; 685 current->thread.evr[fc] = vc.wp[0];
638 regs->gpr[fc] = vc.wp[1]; 686 regs->gpr[fc] = vc.wp[1];
@@ -644,6 +692,23 @@ update_regs:
644 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); 692 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
645 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); 693 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
646 694
695 if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
696 if ((FP_CUR_EXCEPTIONS & FP_EX_DIVZERO)
697 && (current->thread.fpexc_mode & PR_FP_EXC_DIV))
698 return 1;
699 if ((FP_CUR_EXCEPTIONS & FP_EX_OVERFLOW)
700 && (current->thread.fpexc_mode & PR_FP_EXC_OVF))
701 return 1;
702 if ((FP_CUR_EXCEPTIONS & FP_EX_UNDERFLOW)
703 && (current->thread.fpexc_mode & PR_FP_EXC_UND))
704 return 1;
705 if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT)
706 && (current->thread.fpexc_mode & PR_FP_EXC_RES))
707 return 1;
708 if ((FP_CUR_EXCEPTIONS & FP_EX_INVALID)
709 && (current->thread.fpexc_mode & PR_FP_EXC_INV))
710 return 1;
711 }
647 return 0; 712 return 0;
648 713
649illegal: 714illegal:
@@ -662,21 +727,28 @@ int speround_handler(struct pt_regs *regs)
662{ 727{
663 union dw_union fgpr; 728 union dw_union fgpr;
664 int s_lo, s_hi; 729 int s_lo, s_hi;
665 unsigned long speinsn, type, fc; 730 int lo_inexact, hi_inexact;
731 int fp_result;
732 unsigned long speinsn, type, fb, fc, fptype, func;
666 733
667 if (get_user(speinsn, (unsigned int __user *) regs->nip)) 734 if (get_user(speinsn, (unsigned int __user *) regs->nip))
668 return -EFAULT; 735 return -EFAULT;
669 if ((speinsn >> 26) != 4) 736 if ((speinsn >> 26) != 4)
670 return -EINVAL; /* not an spe instruction */ 737 return -EINVAL; /* not an spe instruction */
671 738
672 type = insn_type(speinsn & 0x7ff); 739 func = speinsn & 0x7ff;
740 type = insn_type(func);
673 if (type == XCR) return -ENOSYS; 741 if (type == XCR) return -ENOSYS;
674 742
675 __FPU_FPSCR = mfspr(SPRN_SPEFSCR); 743 __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
676 pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR); 744 pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
677 745
746 fptype = (speinsn >> 5) & 0x7;
747
678 /* No need to round if the result is exact */ 748 /* No need to round if the result is exact */
679 if (!(__FPU_FPSCR & FP_EX_INEXACT)) 749 lo_inexact = __FPU_FPSCR & (SPEFSCR_FG | SPEFSCR_FX);
750 hi_inexact = __FPU_FPSCR & (SPEFSCR_FGH | SPEFSCR_FXH);
751 if (!(lo_inexact || (hi_inexact && fptype == VCT)))
680 return 0; 752 return 0;
681 753
682 fc = (speinsn >> 21) & 0x1f; 754 fc = (speinsn >> 21) & 0x1f;
@@ -685,9 +757,68 @@ int speround_handler(struct pt_regs *regs)
685 fgpr.wp[0] = current->thread.evr[fc]; 757 fgpr.wp[0] = current->thread.evr[fc];
686 fgpr.wp[1] = regs->gpr[fc]; 758 fgpr.wp[1] = regs->gpr[fc];
687 759
760 fb = (speinsn >> 11) & 0x1f;
761 switch (func) {
762 case EFSCTUIZ:
763 case EFSCTSIZ:
764 case EVFSCTUIZ:
765 case EVFSCTSIZ:
766 case EFDCTUIDZ:
767 case EFDCTSIDZ:
768 case EFDCTUIZ:
769 case EFDCTSIZ:
770 /*
771 * These instructions always round to zero,
772 * independent of the rounding mode.
773 */
774 return 0;
775
776 case EFSCTUI:
777 case EFSCTUF:
778 case EVFSCTUI:
779 case EVFSCTUF:
780 case EFDCTUI:
781 case EFDCTUF:
782 fp_result = 0;
783 s_lo = 0;
784 s_hi = 0;
785 break;
786
787 case EFSCTSI:
788 case EFSCTSF:
789 fp_result = 0;
790 /* Recover the sign of a zero result if possible. */
791 if (fgpr.wp[1] == 0)
792 s_lo = regs->gpr[fb] & SIGN_BIT_S;
793 break;
794
795 case EVFSCTSI:
796 case EVFSCTSF:
797 fp_result = 0;
798 /* Recover the sign of a zero result if possible. */
799 if (fgpr.wp[1] == 0)
800 s_lo = regs->gpr[fb] & SIGN_BIT_S;
801 if (fgpr.wp[0] == 0)
802 s_hi = current->thread.evr[fb] & SIGN_BIT_S;
803 break;
804
805 case EFDCTSI:
806 case EFDCTSF:
807 fp_result = 0;
808 s_hi = s_lo;
809 /* Recover the sign of a zero result if possible. */
810 if (fgpr.wp[1] == 0)
811 s_hi = current->thread.evr[fb] & SIGN_BIT_S;
812 break;
813
814 default:
815 fp_result = 1;
816 break;
817 }
818
688 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); 819 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
689 820
690 switch ((speinsn >> 5) & 0x7) { 821 switch (fptype) {
691 /* Since SPE instructions on E500 core can handle round to nearest 822 /* Since SPE instructions on E500 core can handle round to nearest
692 * and round toward zero with IEEE-754 complied, we just need 823 * and round toward zero with IEEE-754 complied, we just need
693 * to handle round toward +Inf and round toward -Inf by software. 824 * to handle round toward +Inf and round toward -Inf by software.
@@ -696,25 +827,52 @@ int speround_handler(struct pt_regs *regs)
696 if ((FP_ROUNDMODE) == FP_RND_PINF) { 827 if ((FP_ROUNDMODE) == FP_RND_PINF) {
697 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ 828 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */
698 } else { /* round to -Inf */ 829 } else { /* round to -Inf */
699 if (s_lo) fgpr.wp[1]++; /* Z < 0, choose Z2 */ 830 if (s_lo) {
831 if (fp_result)
832 fgpr.wp[1]++; /* Z < 0, choose Z2 */
833 else
834 fgpr.wp[1]--; /* Z < 0, choose Z2 */
835 }
700 } 836 }
701 break; 837 break;
702 838
703 case DPFP: 839 case DPFP:
704 if (FP_ROUNDMODE == FP_RND_PINF) { 840 if (FP_ROUNDMODE == FP_RND_PINF) {
705 if (!s_hi) fgpr.dp[0]++; /* Z > 0, choose Z1 */ 841 if (!s_hi) {
842 if (fp_result)
843 fgpr.dp[0]++; /* Z > 0, choose Z1 */
844 else
845 fgpr.wp[1]++; /* Z > 0, choose Z1 */
846 }
706 } else { /* round to -Inf */ 847 } else { /* round to -Inf */
707 if (s_hi) fgpr.dp[0]++; /* Z < 0, choose Z2 */ 848 if (s_hi) {
849 if (fp_result)
850 fgpr.dp[0]++; /* Z < 0, choose Z2 */
851 else
852 fgpr.wp[1]--; /* Z < 0, choose Z2 */
853 }
708 } 854 }
709 break; 855 break;
710 856
711 case VCT: 857 case VCT:
712 if (FP_ROUNDMODE == FP_RND_PINF) { 858 if (FP_ROUNDMODE == FP_RND_PINF) {
713 if (!s_lo) fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ 859 if (lo_inexact && !s_lo)
714 if (!s_hi) fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ 860 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
861 if (hi_inexact && !s_hi)
862 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
715 } else { /* round to -Inf */ 863 } else { /* round to -Inf */
716 if (s_lo) fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ 864 if (lo_inexact && s_lo) {
717 if (s_hi) fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ 865 if (fp_result)
866 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
867 else
868 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */
869 }
870 if (hi_inexact && s_hi) {
871 if (fp_result)
872 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
873 else
874 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */
875 }
718 } 876 }
719 break; 877 break;
720 878
@@ -727,6 +885,8 @@ int speround_handler(struct pt_regs *regs)
727 885
728 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); 886 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
729 887
888 if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
889 return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0;
730 return 0; 890 return 0;
731} 891}
732 892
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 07ba45b0f07c..94cd728166d3 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -52,6 +52,7 @@
52#include <asm/smp.h> 52#include <asm/smp.h>
53#include <asm/machdep.h> 53#include <asm/machdep.h>
54#include <asm/setup.h> 54#include <asm/setup.h>
55#include <asm/paca.h>
55 56
56#include "mmu_decl.h" 57#include "mmu_decl.h"
57 58
@@ -171,11 +172,10 @@ unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
171 return 1UL << camsize; 172 return 1UL << camsize;
172} 173}
173 174
174unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx) 175static unsigned long map_mem_in_cams_addr(phys_addr_t phys, unsigned long virt,
176 unsigned long ram, int max_cam_idx)
175{ 177{
176 int i; 178 int i;
177 unsigned long virt = PAGE_OFFSET;
178 phys_addr_t phys = memstart_addr;
179 unsigned long amount_mapped = 0; 179 unsigned long amount_mapped = 0;
180 180
181 /* Calculate CAM values */ 181 /* Calculate CAM values */
@@ -192,9 +192,23 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
192 } 192 }
193 tlbcam_index = i; 193 tlbcam_index = i;
194 194
195#ifdef CONFIG_PPC64
196 get_paca()->tcd.esel_next = i;
197 get_paca()->tcd.esel_max = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
198 get_paca()->tcd.esel_first = i;
199#endif
200
195 return amount_mapped; 201 return amount_mapped;
196} 202}
197 203
204unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
205{
206 unsigned long virt = PAGE_OFFSET;
207 phys_addr_t phys = memstart_addr;
208
209 return map_mem_in_cams_addr(phys, virt, ram, max_cam_idx);
210}
211
198#ifdef CONFIG_PPC32 212#ifdef CONFIG_PPC32
199 213
200#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS) 214#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
@@ -222,7 +236,9 @@ void __init adjust_total_lowmem(void)
222 /* adjust lowmem size to __max_low_memory */ 236 /* adjust lowmem size to __max_low_memory */
223 ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem); 237 ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
224 238
239 i = switch_to_as1();
225 __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM); 240 __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);
241 restore_to_as0(i, 0, 0, 1);
226 242
227 pr_info("Memory CAM mapping: "); 243 pr_info("Memory CAM mapping: ");
228 for (i = 0; i < tlbcam_index - 1; i++) 244 for (i = 0; i < tlbcam_index - 1; i++)
@@ -241,4 +257,62 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
241 /* 64M mapped initially according to head_fsl_booke.S */ 257 /* 64M mapped initially according to head_fsl_booke.S */
242 memblock_set_current_limit(min_t(u64, limit, 0x04000000)); 258 memblock_set_current_limit(min_t(u64, limit, 0x04000000));
243} 259}
260
261#ifdef CONFIG_RELOCATABLE
262int __initdata is_second_reloc;
263notrace void __init relocate_init(u64 dt_ptr, phys_addr_t start)
264{
265 unsigned long base = KERNELBASE;
266
267 kernstart_addr = start;
268 if (is_second_reloc) {
269 virt_phys_offset = PAGE_OFFSET - memstart_addr;
270 return;
271 }
272
273 /*
274 * Relocatable kernel support based on processing of dynamic
275 * relocation entries. Before we get the real memstart_addr,
276 * We will compute the virt_phys_offset like this:
277 * virt_phys_offset = stext.run - kernstart_addr
278 *
279 * stext.run = (KERNELBASE & ~0x3ffffff) +
280 * (kernstart_addr & 0x3ffffff)
281 * When we relocate, we have :
282 *
283 * (kernstart_addr & 0x3ffffff) = (stext.run & 0x3ffffff)
284 *
285 * hence:
286 * virt_phys_offset = (KERNELBASE & ~0x3ffffff) -
287 * (kernstart_addr & ~0x3ffffff)
288 *
289 */
290 start &= ~0x3ffffff;
291 base &= ~0x3ffffff;
292 virt_phys_offset = base - start;
293 early_get_first_memblock_info(__va(dt_ptr), NULL);
294 /*
295 * We now get the memstart_addr, then we should check if this
296 * address is the same as what the PAGE_OFFSET map to now. If
297 * not we have to change the map of PAGE_OFFSET to memstart_addr
298 * and do a second relocation.
299 */
300 if (start != memstart_addr) {
301 int n;
302 long offset = start - memstart_addr;
303
304 is_second_reloc = 1;
305 n = switch_to_as1();
306 /* map a 64M area for the second relocation */
307 if (memstart_addr > start)
308 map_mem_in_cams(0x4000000, CONFIG_LOWMEM_CAM_NUM);
309 else
310 map_mem_in_cams_addr(start, PAGE_OFFSET + offset,
311 0x4000000, CONFIG_LOWMEM_CAM_NUM);
312 restore_to_as0(n, offset, __va(dt_ptr), 1);
313 /* We should never reach here */
314 panic("Relocation error");
315 }
316}
317#endif
244#endif 318#endif
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 74551b5e41e5..5e4ee2573903 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -8,6 +8,44 @@
8#include <linux/mm.h> 8#include <linux/mm.h>
9#include <linux/hugetlb.h> 9#include <linux/hugetlb.h>
10 10
11#ifdef CONFIG_PPC_FSL_BOOK3E
12#ifdef CONFIG_PPC64
13static inline int tlb1_next(void)
14{
15 struct paca_struct *paca = get_paca();
16 struct tlb_core_data *tcd;
17 int this, next;
18
19 tcd = paca->tcd_ptr;
20 this = tcd->esel_next;
21
22 next = this + 1;
23 if (next >= tcd->esel_max)
24 next = tcd->esel_first;
25
26 tcd->esel_next = next;
27 return this;
28}
29#else
30static inline int tlb1_next(void)
31{
32 int index, ncams;
33
34 ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
35
36 index = __get_cpu_var(next_tlbcam_idx);
37
38 /* Just round-robin the entries and wrap when we hit the end */
39 if (unlikely(index == ncams - 1))
40 __get_cpu_var(next_tlbcam_idx) = tlbcam_index;
41 else
42 __get_cpu_var(next_tlbcam_idx)++;
43
44 return index;
45}
46#endif /* !PPC64 */
47#endif /* FSL */
48
11static inline int mmu_get_tsize(int psize) 49static inline int mmu_get_tsize(int psize)
12{ 50{
13 return mmu_psize_defs[psize].enc; 51 return mmu_psize_defs[psize].enc;
@@ -47,7 +85,7 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
47 struct mm_struct *mm; 85 struct mm_struct *mm;
48 86
49#ifdef CONFIG_PPC_FSL_BOOK3E 87#ifdef CONFIG_PPC_FSL_BOOK3E
50 int index, ncams; 88 int index;
51#endif 89#endif
52 90
53 if (unlikely(is_kernel_addr(ea))) 91 if (unlikely(is_kernel_addr(ea)))
@@ -77,18 +115,11 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
77 } 115 }
78 116
79#ifdef CONFIG_PPC_FSL_BOOK3E 117#ifdef CONFIG_PPC_FSL_BOOK3E
80 ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
81
82 /* We have to use the CAM(TLB1) on FSL parts for hugepages */ 118 /* We have to use the CAM(TLB1) on FSL parts for hugepages */
83 index = __get_cpu_var(next_tlbcam_idx); 119 index = tlb1_next();
84 mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1)); 120 mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1));
85
86 /* Just round-robin the entries and wrap when we hit the end */
87 if (unlikely(index == ncams - 1))
88 __get_cpu_var(next_tlbcam_idx) = tlbcam_index;
89 else
90 __get_cpu_var(next_tlbcam_idx)++;
91#endif 121#endif
122
92 mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize); 123 mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize);
93 mas2 = ea & ~((1UL << shift) - 1); 124 mas2 = ea & ~((1UL << shift) - 1);
94 mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK; 125 mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
@@ -103,7 +134,8 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
103 if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) { 134 if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
104 mtspr(SPRN_MAS7_MAS3, mas7_3); 135 mtspr(SPRN_MAS7_MAS3, mas7_3);
105 } else { 136 } else {
106 mtspr(SPRN_MAS7, upper_32_bits(mas7_3)); 137 if (mmu_has_feature(MMU_FTR_BIG_PHYS))
138 mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
107 mtspr(SPRN_MAS3, lower_32_bits(mas7_3)); 139 mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
108 } 140 }
109 141
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 9c25feba7c40..b1c5734bc2ce 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -307,6 +307,12 @@ static void __init register_page_bootmem_info(void)
307 307
308void __init mem_init(void) 308void __init mem_init(void)
309{ 309{
310 /*
311 * book3s is limited to 16 page sizes due to encoding this in
312 * a 4-bit field for slices.
313 */
314 BUILD_BUG_ON(MMU_PAGE_COUNT > 16);
315
310#ifdef CONFIG_SWIOTLB 316#ifdef CONFIG_SWIOTLB
311 swiotlb_init(0); 317 swiotlb_init(0);
312#endif 318#endif
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 83eb5d5f53d5..9615d82919b8 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -148,6 +148,8 @@ extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
148extern void MMU_init_hw(void); 148extern void MMU_init_hw(void);
149extern unsigned long mmu_mapin_ram(unsigned long top); 149extern unsigned long mmu_mapin_ram(unsigned long top);
150extern void adjust_total_lowmem(void); 150extern void adjust_total_lowmem(void);
151extern int switch_to_as1(void);
152extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
151#endif 153#endif
152extern void loadcam_entry(unsigned int index); 154extern void loadcam_entry(unsigned int index);
153 155
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 5b9601715289..343a87fa78b5 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -299,6 +299,7 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
299 set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT, 299 set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT,
300 __pgprot(flags))); 300 __pgprot(flags)));
301 } 301 }
302 smp_wmb();
302 return err; 303 return err;
303} 304}
304 305
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 7f0e872ab83d..65b7b65e8708 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -152,6 +152,18 @@ int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
152 } 152 }
153#endif /* !CONFIG_PPC_MMU_NOHASH */ 153#endif /* !CONFIG_PPC_MMU_NOHASH */
154 } 154 }
155
156#ifdef CONFIG_PPC_BOOK3E_64
157 /*
158 * With hardware tablewalk, a sync is needed to ensure that
159 * subsequent accesses see the PTE we just wrote. Unlike userspace
160 * mappings, we can't tolerate spurious faults, so make sure
161 * the new PTE will be seen the first time.
162 */
163 mb();
164#else
165 smp_wmb();
166#endif
155 return 0; 167 return 0;
156} 168}
157 169
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index b4113bf86353..16250b162375 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -136,7 +136,7 @@ BEGIN_MMU_FTR_SECTION
136 */ 136 */
137 PPC_TLBSRX_DOT(0,R16) 137 PPC_TLBSRX_DOT(0,R16)
138 ldx r14,r14,r15 /* grab pgd entry */ 138 ldx r14,r14,r15 /* grab pgd entry */
139 beq normal_tlb_miss_done /* tlb exists already, bail */ 139 beq tlb_miss_done_bolted /* tlb exists already, bail */
140MMU_FTR_SECTION_ELSE 140MMU_FTR_SECTION_ELSE
141 ldx r14,r14,r15 /* grab pgd entry */ 141 ldx r14,r14,r15 /* grab pgd entry */
142ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) 142ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
@@ -192,6 +192,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
192 mtspr SPRN_MAS7_MAS3,r15 192 mtspr SPRN_MAS7_MAS3,r15
193 tlbwe 193 tlbwe
194 194
195tlb_miss_done_bolted:
195 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) 196 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
196 tlb_epilog_bolted 197 tlb_epilog_bolted
197 rfi 198 rfi
@@ -239,6 +240,177 @@ itlb_miss_fault_bolted:
239 beq tlb_miss_common_bolted 240 beq tlb_miss_common_bolted
240 b itlb_miss_kernel_bolted 241 b itlb_miss_kernel_bolted
241 242
243/*
244 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
245 *
246 * Linear mapping is bolted: no virtual page table or nested TLB misses
247 * Indirect entries in TLB1, hardware loads resulting direct entries
248 * into TLB0
249 * No HES or NV hint on TLB1, so we need to do software round-robin
250 * No tlbsrx. so we need a spinlock, and we have to deal
251 * with MAS-damage caused by tlbsx
252 * 4K pages only
253 */
254
255 START_EXCEPTION(instruction_tlb_miss_e6500)
256 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
257
258 ld r11,PACA_TCD_PTR(r13)
259 srdi. r15,r16,60 /* get region */
260 ori r16,r16,1
261
262 TLB_MISS_STATS_SAVE_INFO_BOLTED
263 bne tlb_miss_kernel_e6500 /* user/kernel test */
264
265 b tlb_miss_common_e6500
266
267 START_EXCEPTION(data_tlb_miss_e6500)
268 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
269
270 ld r11,PACA_TCD_PTR(r13)
271 srdi. r15,r16,60 /* get region */
272 rldicr r16,r16,0,62
273
274 TLB_MISS_STATS_SAVE_INFO_BOLTED
275 bne tlb_miss_kernel_e6500 /* user vs kernel check */
276
277/*
278 * This is the guts of the TLB miss handler for e6500 and derivatives.
279 * We are entered with:
280 *
281 * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
282 * r15 = crap (free to use)
283 * r14 = page table base
284 * r13 = PACA
285 * r11 = tlb_per_core ptr
286 * r10 = crap (free to use)
287 */
288tlb_miss_common_e6500:
289 /*
290 * Search if we already have an indirect entry for that virtual
291 * address, and if we do, bail out.
292 *
293 * MAS6:IND should be already set based on MAS4
294 */
295 addi r10,r11,TCD_LOCK
2961: lbarx r15,0,r10
297 cmpdi r15,0
298 bne 2f
299 li r15,1
300 stbcx. r15,0,r10
301 bne 1b
302 .subsection 1
3032: lbz r15,0(r10)
304 cmpdi r15,0
305 bne 2b
306 b 1b
307 .previous
308
309 mfspr r15,SPRN_MAS2
310
311 tlbsx 0,r16
312 mfspr r10,SPRN_MAS1
313 andis. r10,r10,MAS1_VALID@h
314 bne tlb_miss_done_e6500
315
316 /* Undo MAS-damage from the tlbsx */
317 mfspr r10,SPRN_MAS1
318 oris r10,r10,MAS1_VALID@h
319 mtspr SPRN_MAS1,r10
320 mtspr SPRN_MAS2,r15
321
322 /* Now, we need to walk the page tables. First check if we are in
323 * range.
324 */
325 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
326 bne- tlb_miss_fault_e6500
327
328 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
329 cmpldi cr0,r14,0
330 clrrdi r15,r15,3
331 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
332 ldx r14,r14,r15 /* grab pgd entry */
333
334 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
335 clrrdi r15,r15,3
336 cmpdi cr0,r14,0
337 bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */
338 ldx r14,r14,r15 /* grab pud entry */
339
340 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
341 clrrdi r15,r15,3
342 cmpdi cr0,r14,0
343 bge tlb_miss_fault_e6500
344 ldx r14,r14,r15 /* Grab pmd entry */
345
346 mfspr r10,SPRN_MAS0
347 cmpdi cr0,r14,0
348 bge tlb_miss_fault_e6500
349
350 /* Now we build the MAS for a 2M indirect page:
351 *
352 * MAS 0 : ESEL needs to be filled by software round-robin
353 * MAS 1 : Fully set up
354 * - PID already updated by caller if necessary
355 * - TSIZE for now is base ind page size always
356 * - TID already cleared if necessary
357 * MAS 2 : Default not 2M-aligned, need to be redone
358 * MAS 3+7 : Needs to be done
359 */
360
361 ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
362 mtspr SPRN_MAS7_MAS3,r14
363
364 clrrdi r15,r16,21 /* make EA 2M-aligned */
365 mtspr SPRN_MAS2,r15
366
367 lbz r15,TCD_ESEL_NEXT(r11)
368 lbz r16,TCD_ESEL_MAX(r11)
369 lbz r14,TCD_ESEL_FIRST(r11)
370 rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */
371 addi r15,r15,1 /* increment esel_next */
372 mtspr SPRN_MAS0,r10
373 cmpw r15,r16
374 iseleq r15,r14,r15 /* if next == last use first */
375 stb r15,TCD_ESEL_NEXT(r11)
376
377 tlbwe
378
379tlb_miss_done_e6500:
380 .macro tlb_unlock_e6500
381 li r15,0
382 isync
383 stb r15,TCD_LOCK(r11)
384 .endm
385
386 tlb_unlock_e6500
387 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
388 tlb_epilog_bolted
389 rfi
390
391tlb_miss_kernel_e6500:
392 mfspr r10,SPRN_MAS1
393 ld r14,PACA_KERNELPGD(r13)
394 cmpldi cr0,r15,8 /* Check for vmalloc region */
395 rlwinm r10,r10,0,16,1 /* Clear TID */
396 mtspr SPRN_MAS1,r10
397 beq+ tlb_miss_common_e6500
398
399tlb_miss_fault_e6500:
400 tlb_unlock_e6500
401 /* We need to check if it was an instruction miss */
402 andi. r16,r16,1
403 bne itlb_miss_fault_e6500
404dtlb_miss_fault_e6500:
405 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
406 tlb_epilog_bolted
407 b exc_data_storage_book3e
408itlb_miss_fault_e6500:
409 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
410 tlb_epilog_bolted
411 b exc_instruction_storage_book3e
412
413
242/********************************************************************** 414/**********************************************************************
243 * * 415 * *
244 * TLB miss handling for Book3E with TLB reservation and HES support * 416 * TLB miss handling for Book3E with TLB reservation and HES support *
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 8805b7b87dc6..735839b74dc5 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -43,6 +43,7 @@
43#include <asm/tlb.h> 43#include <asm/tlb.h>
44#include <asm/code-patching.h> 44#include <asm/code-patching.h>
45#include <asm/hugetlb.h> 45#include <asm/hugetlb.h>
46#include <asm/paca.h>
46 47
47#include "mmu_decl.h" 48#include "mmu_decl.h"
48 49
@@ -58,6 +59,10 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
58 .shift = 12, 59 .shift = 12,
59 .enc = BOOK3E_PAGESZ_4K, 60 .enc = BOOK3E_PAGESZ_4K,
60 }, 61 },
62 [MMU_PAGE_2M] = {
63 .shift = 21,
64 .enc = BOOK3E_PAGESZ_2M,
65 },
61 [MMU_PAGE_4M] = { 66 [MMU_PAGE_4M] = {
62 .shift = 22, 67 .shift = 22,
63 .enc = BOOK3E_PAGESZ_4M, 68 .enc = BOOK3E_PAGESZ_4M,
@@ -136,7 +141,7 @@ static inline int mmu_get_tsize(int psize)
136int mmu_linear_psize; /* Page size used for the linear mapping */ 141int mmu_linear_psize; /* Page size used for the linear mapping */
137int mmu_pte_psize; /* Page size used for PTE pages */ 142int mmu_pte_psize; /* Page size used for PTE pages */
138int mmu_vmemmap_psize; /* Page size used for the virtual mem map */ 143int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
139int book3e_htw_enabled; /* Is HW tablewalk enabled ? */ 144int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
140unsigned long linear_map_top; /* Top of linear mapping */ 145unsigned long linear_map_top; /* Top of linear mapping */
141 146
142#endif /* CONFIG_PPC64 */ 147#endif /* CONFIG_PPC64 */
@@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
377{ 382{
378 int tsize = mmu_psize_defs[mmu_pte_psize].enc; 383 int tsize = mmu_psize_defs[mmu_pte_psize].enc;
379 384
380 if (book3e_htw_enabled) { 385 if (book3e_htw_mode != PPC_HTW_NONE) {
381 unsigned long start = address & PMD_MASK; 386 unsigned long start = address & PMD_MASK;
382 unsigned long end = address + PMD_SIZE; 387 unsigned long end = address + PMD_SIZE;
383 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift; 388 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
@@ -430,7 +435,7 @@ static void setup_page_sizes(void)
430 def = &mmu_psize_defs[psize]; 435 def = &mmu_psize_defs[psize];
431 shift = def->shift; 436 shift = def->shift;
432 437
433 if (shift == 0) 438 if (shift == 0 || shift & 1)
434 continue; 439 continue;
435 440
436 /* adjust to be in terms of 4^shift Kb */ 441 /* adjust to be in terms of 4^shift Kb */
@@ -440,21 +445,40 @@ static void setup_page_sizes(void)
440 def->flags |= MMU_PAGE_SIZE_DIRECT; 445 def->flags |= MMU_PAGE_SIZE_DIRECT;
441 } 446 }
442 447
443 goto no_indirect; 448 goto out;
444 } 449 }
445 450
446 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { 451 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
447 u32 tlb1ps = mfspr(SPRN_TLB1PS); 452 u32 tlb1cfg, tlb1ps;
453
454 tlb0cfg = mfspr(SPRN_TLB0CFG);
455 tlb1cfg = mfspr(SPRN_TLB1CFG);
456 tlb1ps = mfspr(SPRN_TLB1PS);
457 eptcfg = mfspr(SPRN_EPTCFG);
458
459 if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
460 book3e_htw_mode = PPC_HTW_E6500;
461
462 /*
463 * We expect 4K subpage size and unrestricted indirect size.
464 * The lack of a restriction on indirect size is a Freescale
465 * extension, indicated by PSn = 0 but SPSn != 0.
466 */
467 if (eptcfg != 2)
468 book3e_htw_mode = PPC_HTW_NONE;
448 469
449 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 470 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
450 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 471 struct mmu_psize_def *def = &mmu_psize_defs[psize];
451 472
452 if (tlb1ps & (1U << (def->shift - 10))) { 473 if (tlb1ps & (1U << (def->shift - 10))) {
453 def->flags |= MMU_PAGE_SIZE_DIRECT; 474 def->flags |= MMU_PAGE_SIZE_DIRECT;
475
476 if (book3e_htw_mode && psize == MMU_PAGE_2M)
477 def->flags |= MMU_PAGE_SIZE_INDIRECT;
454 } 478 }
455 } 479 }
456 480
457 goto no_indirect; 481 goto out;
458 } 482 }
459#endif 483#endif
460 484
@@ -471,8 +495,11 @@ static void setup_page_sizes(void)
471 } 495 }
472 496
473 /* Indirect page sizes supported ? */ 497 /* Indirect page sizes supported ? */
474 if ((tlb0cfg & TLBnCFG_IND) == 0) 498 if ((tlb0cfg & TLBnCFG_IND) == 0 ||
475 goto no_indirect; 499 (tlb0cfg & TLBnCFG_PT) == 0)
500 goto out;
501
502 book3e_htw_mode = PPC_HTW_IBM;
476 503
477 /* Now, we only deal with one IND page size for each 504 /* Now, we only deal with one IND page size for each
478 * direct size. Hopefully all implementations today are 505 * direct size. Hopefully all implementations today are
@@ -497,8 +524,8 @@ static void setup_page_sizes(void)
497 def->ind = ps + 10; 524 def->ind = ps + 10;
498 } 525 }
499 } 526 }
500 no_indirect:
501 527
528out:
502 /* Cleanup array and print summary */ 529 /* Cleanup array and print summary */
503 pr_info("MMU: Supported page sizes\n"); 530 pr_info("MMU: Supported page sizes\n");
504 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 531 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
@@ -520,23 +547,23 @@ static void setup_page_sizes(void)
520 547
521static void setup_mmu_htw(void) 548static void setup_mmu_htw(void)
522{ 549{
523 /* Check if HW tablewalk is present, and if yes, enable it by: 550 /*
524 * 551 * If we want to use HW tablewalk, enable it by patching the TLB miss
525 * - patching the TLB miss handlers to branch to the 552 * handlers to branch to the one dedicated to it.
526 * one dedicates to it 553 */
527 *
528 * - setting the global book3e_htw_enabled
529 */
530 unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
531 554
532 if ((tlb0cfg & TLBnCFG_IND) && 555 switch (book3e_htw_mode) {
533 (tlb0cfg & TLBnCFG_PT)) { 556 case PPC_HTW_IBM:
534 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e); 557 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
535 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e); 558 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
536 book3e_htw_enabled = 1; 559 break;
560 case PPC_HTW_E6500:
561 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
562 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
563 break;
537 } 564 }
538 pr_info("MMU: Book3E HW tablewalk %s\n", 565 pr_info("MMU: Book3E HW tablewalk %s\n",
539 book3e_htw_enabled ? "enabled" : "not supported"); 566 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
540} 567}
541 568
542/* 569/*
@@ -576,8 +603,16 @@ static void __early_init_mmu(int boot_cpu)
576 /* Set MAS4 based on page table setting */ 603 /* Set MAS4 based on page table setting */
577 604
578 mas4 = 0x4 << MAS4_WIMGED_SHIFT; 605 mas4 = 0x4 << MAS4_WIMGED_SHIFT;
579 if (book3e_htw_enabled) { 606 switch (book3e_htw_mode) {
580 mas4 |= mas4 | MAS4_INDD; 607 case PPC_HTW_E6500:
608 mas4 |= MAS4_INDD;
609 mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
610 mas4 |= MAS4_TLBSELD(1);
611 mmu_pte_psize = MMU_PAGE_2M;
612 break;
613
614 case PPC_HTW_IBM:
615 mas4 |= MAS4_INDD;
581#ifdef CONFIG_PPC_64K_PAGES 616#ifdef CONFIG_PPC_64K_PAGES
582 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT; 617 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
583 mmu_pte_psize = MMU_PAGE_256M; 618 mmu_pte_psize = MMU_PAGE_256M;
@@ -585,13 +620,16 @@ static void __early_init_mmu(int boot_cpu)
585 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT; 620 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
586 mmu_pte_psize = MMU_PAGE_1M; 621 mmu_pte_psize = MMU_PAGE_1M;
587#endif 622#endif
588 } else { 623 break;
624
625 case PPC_HTW_NONE:
589#ifdef CONFIG_PPC_64K_PAGES 626#ifdef CONFIG_PPC_64K_PAGES
590 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT; 627 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
591#else 628#else
592 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT; 629 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
593#endif 630#endif
594 mmu_pte_psize = mmu_virtual_psize; 631 mmu_pte_psize = mmu_virtual_psize;
632 break;
595 } 633 }
596 mtspr(SPRN_MAS4, mas4); 634 mtspr(SPRN_MAS4, mas4);
597 635
@@ -611,8 +649,11 @@ static void __early_init_mmu(int boot_cpu)
611 /* limit memory so we dont have linear faults */ 649 /* limit memory so we dont have linear faults */
612 memblock_enforce_memory_limit(linear_map_top); 650 memblock_enforce_memory_limit(linear_map_top);
613 651
614 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); 652 if (book3e_htw_mode == PPC_HTW_NONE) {
615 patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e); 653 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
654 patch_exception(0x1e0,
655 exc_instruction_tlb_miss_bolted_book3e);
656 }
616 } 657 }
617#endif 658#endif
618 659
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 626ad081639f..43ff3c797fbf 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -402,7 +402,9 @@ _GLOBAL(set_context)
402 * Load TLBCAM[index] entry in to the L2 CAM MMU 402 * Load TLBCAM[index] entry in to the L2 CAM MMU
403 */ 403 */
404_GLOBAL(loadcam_entry) 404_GLOBAL(loadcam_entry)
405 LOAD_REG_ADDR(r4, TLBCAM) 405 mflr r5
406 LOAD_REG_ADDR_PIC(r4, TLBCAM)
407 mtlr r5
406 mulli r5,r3,TLBCAM_SIZE 408 mulli r5,r3,TLBCAM_SIZE
407 add r3,r5,r4 409 add r3,r5,r4
408 lwz r4,TLBCAM_MAS0(r3) 410 lwz r4,TLBCAM_MAS0(r3)
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 4d4634958cfb..c17aae80e7ff 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -123,6 +123,12 @@ config P1023_RDS
123 help 123 help
124 This option enables support for the P1023 RDS and RDB boards 124 This option enables support for the P1023 RDS and RDB boards
125 125
126config TWR_P102x
127 bool "Freescale TWR-P102x"
128 select DEFAULT_UIMAGE
129 help
130 This option enables support for the TWR-P1025 board.
131
126config SOCRATES 132config SOCRATES
127 bool "Socrates" 133 bool "Socrates"
128 select DEFAULT_UIMAGE 134 select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index dd4c0b59577b..25cebe74ac46 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
18obj-$(CONFIG_P1022_DS) += p1022_ds.o 18obj-$(CONFIG_P1022_DS) += p1022_ds.o
19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o 19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
20obj-$(CONFIG_P1023_RDS) += p1023_rds.o 20obj-$(CONFIG_P1023_RDS) += p1023_rds.o
21obj-$(CONFIG_TWR_P102x) += twr_p102x.o
21obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o 22obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
22obj-$(CONFIG_STX_GP3) += stx_gp3.o 23obj-$(CONFIG_STX_GP3) += stx_gp3.o
23obj-$(CONFIG_TQM85xx) += tqm85xx.o 24obj-$(CONFIG_TQM85xx) += tqm85xx.o
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index eba78c85303f..3b085c7ee539 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -9,6 +9,7 @@
9#include <linux/of_irq.h> 9#include <linux/of_irq.h>
10#include <linux/of_platform.h> 10#include <linux/of_platform.h>
11 11
12#include <asm/qe.h>
12#include <sysdev/cpm2_pic.h> 13#include <sysdev/cpm2_pic.h>
13 14
14#include "mpc85xx.h" 15#include "mpc85xx.h"
@@ -82,3 +83,40 @@ void __init mpc85xx_cpm2_pic_init(void)
82 irq_set_chained_handler(irq, cpm2_cascade); 83 irq_set_chained_handler(irq, cpm2_cascade);
83} 84}
84#endif 85#endif
86
87#ifdef CONFIG_QUICC_ENGINE
88void __init mpc85xx_qe_init(void)
89{
90 struct device_node *np;
91
92 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
93 if (!np) {
94 np = of_find_node_by_name(NULL, "qe");
95 if (!np) {
96 pr_err("%s: Could not find Quicc Engine node\n",
97 __func__);
98 return;
99 }
100 }
101
102 if (!of_device_is_available(np)) {
103 of_node_put(np);
104 return;
105 }
106
107 qe_reset();
108 of_node_put(np);
109
110 np = of_find_node_by_name(NULL, "par_io");
111 if (np) {
112 struct device_node *ucc;
113
114 par_io_init(np);
115 of_node_put(np);
116
117 for_each_node_by_name(ucc, "ucc")
118 par_io_of_config(ucc);
119
120 }
121}
122#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5dc2c7f..fc51dd4092e5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,10 @@ extern void mpc85xx_cpm2_pic_init(void);
8static inline void __init mpc85xx_cpm2_pic_init(void) {} 8static inline void __init mpc85xx_cpm2_pic_init(void) {}
9#endif /* CONFIG_CPM2 */ 9#endif /* CONFIG_CPM2 */
10 10
11#ifdef CONFIG_QUICC_ENGINE
12extern void mpc85xx_qe_init(void);
13#else
14static inline void __init mpc85xx_qe_init(void) {}
15#endif
16
11#endif 17#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621a8df5..34f3c5eb3bee 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2006-2010, 2012 Freescale Semiconductor, Inc. 2 * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
3 * All rights reserved. 3 * All rights reserved.
4 * 4 *
5 * Author: Andy Fleming <afleming@freescale.com> 5 * Author: Andy Fleming <afleming@freescale.com>
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
238{ 238{
239 struct device_node *np; 239 struct device_node *np;
240 240
241 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 241 mpc85xx_qe_init();
242 if (!np) {
243 np = of_find_node_by_name(NULL, "qe");
244 if (!np)
245 return;
246 }
247
248 if (!of_device_is_available(np)) {
249 of_node_put(np);
250 return;
251 }
252
253 qe_reset();
254 of_node_put(np);
255
256 np = of_find_node_by_name(NULL, "par_io");
257 if (np) {
258 struct device_node *ucc;
259
260 par_io_init(np);
261 of_node_put(np);
262
263 for_each_node_by_name(ucc, "ucc")
264 par_io_of_config(ucc);
265 }
266
267 mpc85xx_mds_reset_ucc_phys(); 242 mpc85xx_mds_reset_ucc_phys();
268 243
269 if (machine_is(p1021_mds)) { 244 if (machine_is(p1021_mds)) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0a3d56..e15bdd18fdb2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC85xx RDB Board Setup 2 * MPC85xx RDB Board Setup
3 * 3 *
4 * Copyright 2009,2012 Freescale Semiconductor Inc. 4 * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -98,26 +98,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
98 fsl_pci_assign_primary(); 98 fsl_pci_assign_primary();
99 99
100#ifdef CONFIG_QUICC_ENGINE 100#ifdef CONFIG_QUICC_ENGINE
101 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 101 mpc85xx_qe_init();
102 if (!np) {
103 pr_err("%s: Could not find Quicc Engine node\n", __func__);
104 goto qe_fail;
105 }
106
107 qe_reset();
108 of_node_put(np);
109
110 np = of_find_node_by_name(NULL, "par_io");
111 if (np) {
112 struct device_node *ucc;
113
114 par_io_init(np);
115 of_node_put(np);
116
117 for_each_node_by_name(ucc, "ucc")
118 par_io_of_config(ucc);
119
120 }
121#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 102#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
122 if (machine_is(p1025_rdb)) { 103 if (machine_is(p1025_rdb)) {
123 104
@@ -148,8 +129,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
148 129
149 } 130 }
150#endif 131#endif
151
152qe_fail:
153#endif /* CONFIG_QUICC_ENGINE */ 132#endif /* CONFIG_QUICC_ENGINE */
154 133
155 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 134 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 393f975ab397..6382098d6f8d 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -389,15 +389,18 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
389} 389}
390#endif /* CONFIG_KEXEC */ 390#endif /* CONFIG_KEXEC */
391 391
392static void smp_85xx_setup_cpu(int cpu_nr) 392static void smp_85xx_basic_setup(int cpu_nr)
393{ 393{
394 if (smp_85xx_ops.probe == smp_mpic_probe)
395 mpic_setup_this_cpu();
396
397 if (cpu_has_feature(CPU_FTR_DBELL)) 394 if (cpu_has_feature(CPU_FTR_DBELL))
398 doorbell_setup_this_cpu(); 395 doorbell_setup_this_cpu();
399} 396}
400 397
398static void smp_85xx_setup_cpu(int cpu_nr)
399{
400 mpic_setup_this_cpu();
401 smp_85xx_basic_setup(cpu_nr);
402}
403
401static const struct of_device_id mpc85xx_smp_guts_ids[] = { 404static const struct of_device_id mpc85xx_smp_guts_ids[] = {
402 { .compatible = "fsl,mpc8572-guts", }, 405 { .compatible = "fsl,mpc8572-guts", },
403 { .compatible = "fsl,p1020-guts", }, 406 { .compatible = "fsl,p1020-guts", },
@@ -412,13 +415,14 @@ void __init mpc85xx_smp_init(void)
412{ 415{
413 struct device_node *np; 416 struct device_node *np;
414 417
415 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
416 418
417 np = of_find_node_by_type(NULL, "open-pic"); 419 np = of_find_node_by_type(NULL, "open-pic");
418 if (np) { 420 if (np) {
419 smp_85xx_ops.probe = smp_mpic_probe; 421 smp_85xx_ops.probe = smp_mpic_probe;
422 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
420 smp_85xx_ops.message_pass = smp_mpic_message_pass; 423 smp_85xx_ops.message_pass = smp_mpic_message_pass;
421 } 424 } else
425 smp_85xx_ops.setup_cpu = smp_85xx_basic_setup;
422 426
423 if (cpu_has_feature(CPU_FTR_DBELL)) { 427 if (cpu_has_feature(CPU_FTR_DBELL)) {
424 /* 428 /*
@@ -427,6 +431,7 @@ void __init mpc85xx_smp_init(void)
427 */ 431 */
428 smp_85xx_ops.message_pass = NULL; 432 smp_85xx_ops.message_pass = NULL;
429 smp_85xx_ops.cause_ipi = doorbell_cause_ipi; 433 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
434 smp_85xx_ops.probe = NULL;
430 } 435 }
431 436
432 np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids); 437 np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
new file mode 100644
index 000000000000..c25ff10f05ee
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Michael Johnston <michael.johnston@freescale.com>
5 *
6 * Description:
7 * TWR-P102x Board Setup
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/of_platform.h>
20
21#include <asm/pci-bridge.h>
22#include <asm/udbg.h>
23#include <asm/mpic.h>
24#include <asm/qe.h>
25#include <asm/qe_ic.h>
26#include <asm/fsl_guts.h>
27
28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h>
30#include "smp.h"
31
32#include "mpc85xx.h"
33
34static void __init twr_p1025_pic_init(void)
35{
36 struct mpic *mpic;
37
38#ifdef CONFIG_QUICC_ENGINE
39 struct device_node *np;
40#endif
41
42 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
43 MPIC_SINGLE_DEST_CPU,
44 0, 256, " OpenPIC ");
45
46 BUG_ON(mpic == NULL);
47 mpic_init(mpic);
48
49#ifdef CONFIG_QUICC_ENGINE
50 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
51 if (np) {
52 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
53 qe_ic_cascade_high_mpic);
54 of_node_put(np);
55 } else
56 pr_err("Could not find qe-ic node\n");
57#endif
58}
59
60/* ************************************************************************
61 *
62 * Setup the architecture
63 *
64 */
65static void __init twr_p1025_setup_arch(void)
66{
67#ifdef CONFIG_QUICC_ENGINE
68 struct device_node *np;
69#endif
70
71 if (ppc_md.progress)
72 ppc_md.progress("twr_p1025_setup_arch()", 0);
73
74 mpc85xx_smp_init();
75
76 fsl_pci_assign_primary();
77
78#ifdef CONFIG_QUICC_ENGINE
79 mpc85xx_qe_init();
80
81#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
82 if (machine_is(twr_p1025)) {
83 struct ccsr_guts __iomem *guts;
84
85 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
86 if (np) {
87 guts = of_iomap(np, 0);
88 if (!guts)
89 pr_err("twr_p1025: could not map global utilities register\n");
90 else {
91 /* P1025 has pins muxed for QE and other functions. To
92 * enable QE UEC mode, we need to set bit QE0 for UCC1
93 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
94 * and QE12 for QE MII management signals in PMUXCR
95 * register.
96 * Set QE mux bits in PMUXCR */
97 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
98 MPC85xx_PMUXCR_QE(3) |
99 MPC85xx_PMUXCR_QE(9) |
100 MPC85xx_PMUXCR_QE(12));
101 iounmap(guts);
102
103#if defined(CONFIG_SERIAL_QE)
104 /* On P1025TWR board, the UCC7 acted as UART port.
105 * However, The UCC7's CTS pin is low level in default,
106 * it will impact the transmission in full duplex
107 * communication. So disable the Flow control pin PA18.
108 * The UCC7 UART just can use RXD and TXD pins.
109 */
110 par_io_config_pin(0, 18, 0, 0, 0, 0);
111#endif
112 /* Drive PB29 to CPLD low - CPLD will then change
113 * muxing from LBC to QE */
114 par_io_config_pin(1, 29, 1, 0, 0, 0);
115 par_io_data_set(1, 29, 0);
116 }
117 of_node_put(np);
118 }
119 }
120#endif
121#endif /* CONFIG_QUICC_ENGINE */
122
123 pr_info("TWR-P1025 board from Freescale Semiconductor\n");
124}
125
126machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
127
128static int __init twr_p1025_probe(void)
129{
130 unsigned long root = of_get_flat_dt_root();
131
132 return of_flat_dt_is_compatible(root, "fsl,TWR-P1025");
133}
134
135define_machine(twr_p1025) {
136 .name = "TWR-P1025",
137 .probe = twr_p1025_probe,
138 .setup_arch = twr_p1025_setup_arch,
139 .init_IRQ = twr_p1025_pic_init,
140#ifdef CONFIG_PCI
141 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
142#endif
143 .get_irq = mpic_get_irq,
144 .restart = fsl_rstcr_restart,
145 .calibrate_decr = generic_calibrate_decr,
146 .progress = udbg_progress,
147};
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 302ba43d73a1..6d3c7a9fd047 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -67,6 +67,18 @@ config PPC_C2K
67 This option enables support for the GE Fanuc C2K board (formerly 67 This option enables support for the GE Fanuc C2K board (formerly
68 an SBS board). 68 an SBS board).
69 69
70config MVME5100
71 bool "Motorola/Emerson MVME5100"
72 depends on EMBEDDED6xx
73 select MPIC
74 select PCI
75 select PPC_INDIRECT_PCI
76 select PPC_I8259
77 select PPC_NATIVE
78 help
79 This option enables support for the Motorola (now Emerson) MVME5100
80 board.
81
70config TSI108_BRIDGE 82config TSI108_BRIDGE
71 bool 83 bool
72 select PCI 84 select PCI
@@ -113,4 +125,3 @@ config WII
113 help 125 help
114 Select WII if configuring for the Nintendo Wii. 126 Select WII if configuring for the Nintendo Wii.
115 More information at: <http://gc-linux.sourceforge.net/> 127 More information at: <http://gc-linux.sourceforge.net/>
116
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index 66c23e423f40..cdd48d402b93 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_USBGECKO_UDBG) += usbgecko_udbg.o
11obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o 11obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o
12obj-$(CONFIG_GAMECUBE) += gamecube.o 12obj-$(CONFIG_GAMECUBE) += gamecube.o
13obj-$(CONFIG_WII) += wii.o hlwd-pic.o 13obj-$(CONFIG_WII) += wii.o hlwd-pic.o
14obj-$(CONFIG_MVME5100) += mvme5100.o
diff --git a/arch/powerpc/platforms/embedded6xx/mvme5100.c b/arch/powerpc/platforms/embedded6xx/mvme5100.c
new file mode 100644
index 000000000000..25e3bfb64efb
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/mvme5100.c
@@ -0,0 +1,221 @@
1/*
2 * Board setup routines for the Motorola/Emerson MVME5100.
3 *
4 * Copyright 2013 CSC Australia Pty. Ltd.
5 *
6 * Based on earlier code by:
7 *
8 * Matt Porter, MontaVista Software Inc.
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * Author: Stephen Chivers <schivers@csc.com>
17 *
18 */
19
20#include <linux/of_platform.h>
21
22#include <asm/i8259.h>
23#include <asm/pci-bridge.h>
24#include <asm/mpic.h>
25#include <asm/prom.h>
26#include <mm/mmu_decl.h>
27#include <asm/udbg.h>
28
29#define HAWK_MPIC_SIZE 0x00040000U
30#define MVME5100_PCI_MEM_OFFSET 0x00000000
31
32/* Board register addresses. */
33#define BOARD_STATUS_REG 0xfef88080
34#define BOARD_MODFAIL_REG 0xfef88090
35#define BOARD_MODRST_REG 0xfef880a0
36#define BOARD_TBEN_REG 0xfef880c0
37#define BOARD_SW_READ_REG 0xfef880e0
38#define BOARD_GEO_ADDR_REG 0xfef880e8
39#define BOARD_EXT_FEATURE1_REG 0xfef880f0
40#define BOARD_EXT_FEATURE2_REG 0xfef88100
41
42static phys_addr_t pci_membase;
43static u_char *restart;
44
45static void mvme5100_8259_cascade(unsigned int irq, struct irq_desc *desc)
46{
47 struct irq_chip *chip = irq_desc_get_chip(desc);
48 unsigned int cascade_irq = i8259_irq();
49
50 if (cascade_irq != NO_IRQ)
51 generic_handle_irq(cascade_irq);
52
53 chip->irq_eoi(&desc->irq_data);
54}
55
56static void __init mvme5100_pic_init(void)
57{
58 struct mpic *mpic;
59 struct device_node *np;
60 struct device_node *cp = NULL;
61 unsigned int cirq;
62 unsigned long intack = 0;
63 const u32 *prop = NULL;
64
65 np = of_find_node_by_type(NULL, "open-pic");
66 if (!np) {
67 pr_err("Could not find open-pic node\n");
68 return;
69 }
70
71 mpic = mpic_alloc(np, pci_membase, 0, 16, 256, " OpenPIC ");
72
73 BUG_ON(mpic == NULL);
74 of_node_put(np);
75
76 mpic_assign_isu(mpic, 0, pci_membase + 0x10000);
77
78 mpic_init(mpic);
79
80 cp = of_find_compatible_node(NULL, NULL, "chrp,iic");
81 if (cp == NULL) {
82 pr_warn("mvme5100_pic_init: couldn't find i8259\n");
83 return;
84 }
85
86 cirq = irq_of_parse_and_map(cp, 0);
87 if (cirq == NO_IRQ) {
88 pr_warn("mvme5100_pic_init: no cascade interrupt?\n");
89 return;
90 }
91
92 np = of_find_compatible_node(NULL, "pci", "mpc10x-pci");
93 if (np) {
94 prop = of_get_property(np, "8259-interrupt-acknowledge", NULL);
95
96 if (prop)
97 intack = prop[0];
98
99 of_node_put(np);
100 }
101
102 if (intack)
103 pr_debug("mvme5100_pic_init: PCI 8259 intack at 0x%016lx\n",
104 intack);
105
106 i8259_init(cp, intack);
107 of_node_put(cp);
108 irq_set_chained_handler(cirq, mvme5100_8259_cascade);
109}
110
111static int __init mvme5100_add_bridge(struct device_node *dev)
112{
113 const int *bus_range;
114 int len;
115 struct pci_controller *hose;
116 unsigned short devid;
117
118 pr_info("Adding PCI host bridge %s\n", dev->full_name);
119
120 bus_range = of_get_property(dev, "bus-range", &len);
121
122 hose = pcibios_alloc_controller(dev);
123 if (hose == NULL)
124 return -ENOMEM;
125
126 hose->first_busno = bus_range ? bus_range[0] : 0;
127 hose->last_busno = bus_range ? bus_range[1] : 0xff;
128
129 setup_indirect_pci(hose, 0xfe000cf8, 0xfe000cfc, 0);
130
131 pci_process_bridge_OF_ranges(hose, dev, 1);
132
133 early_read_config_word(hose, 0, 0, PCI_DEVICE_ID, &devid);
134
135 if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) {
136 pr_err("HAWK PHB not present?\n");
137 return 0;
138 }
139
140 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
141
142 if (pci_membase == 0) {
143 pr_err("HAWK PHB mibar not correctly set?\n");
144 return 0;
145 }
146
147 pr_info("mvme5100_pic_init: pci_membase: %x\n", pci_membase);
148
149 return 0;
150}
151
152static struct of_device_id mvme5100_of_bus_ids[] __initdata = {
153 { .compatible = "hawk-bridge", },
154 {},
155};
156
157/*
158 * Setup the architecture
159 */
160static void __init mvme5100_setup_arch(void)
161{
162 struct device_node *np;
163
164 if (ppc_md.progress)
165 ppc_md.progress("mvme5100_setup_arch()", 0);
166
167 for_each_compatible_node(np, "pci", "hawk-pci")
168 mvme5100_add_bridge(np);
169
170 restart = ioremap(BOARD_MODRST_REG, 4);
171}
172
173
174static void mvme5100_show_cpuinfo(struct seq_file *m)
175{
176 seq_puts(m, "Vendor\t\t: Motorola/Emerson\n");
177 seq_puts(m, "Machine\t\t: MVME5100\n");
178}
179
180static void mvme5100_restart(char *cmd)
181{
182
183 local_irq_disable();
184 mtmsr(mfmsr() | MSR_IP);
185
186 out_8((u_char *) restart, 0x01);
187
188 while (1)
189 ;
190}
191
192/*
193 * Called very early, device-tree isn't unflattened
194 */
195static int __init mvme5100_probe(void)
196{
197 unsigned long root = of_get_flat_dt_root();
198
199 return of_flat_dt_is_compatible(root, "MVME5100");
200}
201
202static int __init probe_of_platform_devices(void)
203{
204
205 of_platform_bus_probe(NULL, mvme5100_of_bus_ids, NULL);
206 return 0;
207}
208
209machine_device_initcall(mvme5100, probe_of_platform_devices);
210
211define_machine(mvme5100) {
212 .name = "MVME5100",
213 .probe = mvme5100_probe,
214 .setup_arch = mvme5100_setup_arch,
215 .init_IRQ = mvme5100_pic_init,
216 .show_cpuinfo = mvme5100_show_cpuinfo,
217 .get_irq = mpic_get_irq,
218 .restart = mvme5100_restart,
219 .calibrate_decr = generic_calibrate_decr,
220 .progress = udbg_progress,
221};
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 6bc5a546d49f..d631022ffb4b 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -214,10 +214,14 @@ static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
214 struct fsl_lbc_ctrl *ctrl = data; 214 struct fsl_lbc_ctrl *ctrl = data;
215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
216 u32 status; 216 u32 status;
217 unsigned long flags;
217 218
219 spin_lock_irqsave(&fsl_lbc_lock, flags);
218 status = in_be32(&lbc->ltesr); 220 status = in_be32(&lbc->ltesr);
219 if (!status) 221 if (!status) {
222 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
220 return IRQ_NONE; 223 return IRQ_NONE;
224 }
221 225
222 out_be32(&lbc->ltesr, LTESR_CLEAR); 226 out_be32(&lbc->ltesr, LTESR_CLEAR);
223 out_be32(&lbc->lteatr, 0); 227 out_be32(&lbc->lteatr, 0);
@@ -260,6 +264,7 @@ static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
260 if (status & ~LTESR_MASK) 264 if (status & ~LTESR_MASK)
261 dev_err(ctrl->dev, "Unknown error: " 265 dev_err(ctrl->dev, "Unknown error: "
262 "LTESR 0x%08X\n", status); 266 "LTESR 0x%08X\n", status);
267 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
263 return IRQ_HANDLED; 268 return IRQ_HANDLED;
264} 269}
265 270
@@ -298,8 +303,8 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
298 goto err; 303 goto err;
299 } 304 }
300 305
301 fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0); 306 fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
302 if (fsl_lbc_ctrl_dev->irq == NO_IRQ) { 307 if (!fsl_lbc_ctrl_dev->irq[0]) {
303 dev_err(&dev->dev, "failed to get irq resource\n"); 308 dev_err(&dev->dev, "failed to get irq resource\n");
304 ret = -ENODEV; 309 ret = -ENODEV;
305 goto err; 310 goto err;
@@ -311,20 +316,34 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
311 if (ret < 0) 316 if (ret < 0)
312 goto err; 317 goto err;
313 318
314 ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0, 319 ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
315 "fsl-lbc", fsl_lbc_ctrl_dev); 320 "fsl-lbc", fsl_lbc_ctrl_dev);
316 if (ret != 0) { 321 if (ret != 0) {
317 dev_err(&dev->dev, "failed to install irq (%d)\n", 322 dev_err(&dev->dev, "failed to install irq (%d)\n",
318 fsl_lbc_ctrl_dev->irq); 323 fsl_lbc_ctrl_dev->irq[0]);
319 ret = fsl_lbc_ctrl_dev->irq; 324 ret = fsl_lbc_ctrl_dev->irq[0];
320 goto err; 325 goto err;
321 } 326 }
322 327
328 fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
329 if (fsl_lbc_ctrl_dev->irq[1]) {
330 ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
331 IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
332 if (ret) {
333 dev_err(&dev->dev, "failed to install irq (%d)\n",
334 fsl_lbc_ctrl_dev->irq[1]);
335 ret = fsl_lbc_ctrl_dev->irq[1];
336 goto err1;
337 }
338 }
339
323 /* Enable interrupts for any detected events */ 340 /* Enable interrupts for any detected events */
324 out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE); 341 out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
325 342
326 return 0; 343 return 0;
327 344
345err1:
346 free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
328err: 347err:
329 iounmap(fsl_lbc_ctrl_dev->regs); 348 iounmap(fsl_lbc_ctrl_dev->regs);
330 kfree(fsl_lbc_ctrl_dev); 349 kfree(fsl_lbc_ctrl_dev);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 7066e5262468..a625dcf26b2b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -454,7 +454,7 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
454 } 454 }
455} 455}
456 456
457int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) 457int fsl_add_bridge(struct platform_device *pdev, int is_primary)
458{ 458{
459 int len; 459 int len;
460 struct pci_controller *hose; 460 struct pci_controller *hose;
@@ -1035,6 +1035,7 @@ static const struct of_device_id pci_ids[] = {
1035 { .compatible = "fsl,mpc8548-pcie", }, 1035 { .compatible = "fsl,mpc8548-pcie", },
1036 { .compatible = "fsl,mpc8610-pci", }, 1036 { .compatible = "fsl,mpc8610-pci", },
1037 { .compatible = "fsl,mpc8641-pcie", }, 1037 { .compatible = "fsl,mpc8641-pcie", },
1038 { .compatible = "fsl,qoriq-pcie", },
1038 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1039 { .compatible = "fsl,qoriq-pcie-v2.1", },
1039 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1040 { .compatible = "fsl,qoriq-pcie-v2.2", },
1040 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1041 { .compatible = "fsl,qoriq-pcie-v2.3", },
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index c6c8b526a4f6..1f6c570d66d4 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -152,10 +152,8 @@ static struct pci_ops indirect_pci_ops =
152 .write = indirect_write_config, 152 .write = indirect_write_config,
153}; 153};
154 154
155void __init 155void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
156setup_indirect_pci(struct pci_controller* hose, 156 resource_size_t cfg_data, u32 flags)
157 resource_size_t cfg_addr,
158 resource_size_t cfg_data, u32 flags)
159{ 157{
160 resource_size_t base = cfg_addr & PAGE_MASK; 158 resource_size_t base = cfg_addr & PAGE_MASK;
161 void __iomem *mbase; 159 void __iomem *mbase;
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 22d7d57eead9..9d9b06217f8b 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -41,6 +41,7 @@
41#define MPIC_TIMER_TCR_ROVR_OFFSET 24 41#define MPIC_TIMER_TCR_ROVR_OFFSET 24
42 42
43#define TIMER_STOP 0x80000000 43#define TIMER_STOP 0x80000000
44#define GTCCR_TOG 0x80000000
44#define TIMERS_PER_GROUP 4 45#define TIMERS_PER_GROUP 4
45#define MAX_TICKS (~0U >> 1) 46#define MAX_TICKS (~0U >> 1)
46#define MAX_TICKS_CASCADE (~0U) 47#define MAX_TICKS_CASCADE (~0U)
@@ -96,8 +97,11 @@ static void convert_ticks_to_time(struct timer_group_priv *priv,
96 time->tv_sec = (__kernel_time_t)div_u64(ticks, priv->timerfreq); 97 time->tv_sec = (__kernel_time_t)div_u64(ticks, priv->timerfreq);
97 tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq; 98 tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq;
98 99
99 time->tv_usec = (__kernel_suseconds_t) 100 time->tv_usec = 0;
100 div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq); 101
102 if (tmp_sec <= ticks)
103 time->tv_usec = (__kernel_suseconds_t)
104 div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq);
101 105
102 return; 106 return;
103} 107}
@@ -327,11 +331,13 @@ void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time)
327 casc_priv = priv->timer[handle->num].cascade_handle; 331 casc_priv = priv->timer[handle->num].cascade_handle;
328 if (casc_priv) { 332 if (casc_priv) {
329 tmp_ticks = in_be32(&priv->regs[handle->num].gtccr); 333 tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
334 tmp_ticks &= ~GTCCR_TOG;
330 ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE; 335 ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
331 tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr); 336 tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
332 ticks += tmp_ticks; 337 ticks += tmp_ticks;
333 } else { 338 } else {
334 ticks = in_be32(&priv->regs[handle->num].gtccr); 339 ticks = in_be32(&priv->regs[handle->num].gtccr);
340 ticks &= ~GTCCR_TOG;
335 } 341 }
336 342
337 convert_ticks_to_time(priv, ticks, time); 343 convert_ticks_to_time(priv, ticks, time);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 05:16:13 -0500