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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-07-14 16:52:54 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-08-19 20:12:27 -0400
commitee43eb788b3a06425fffb912677e2e1c8b00dd3b (patch)
tree7233cb47647837ab00af81270b3a16555d88a1f1 /arch
parent8aa34ab8b2dc96ca6c4feecfb87ed13f0d40ef98 (diff)
powerpc: Use names rather than numbers for SPRGs (v2)
The kernel uses SPRG registers for various purposes, typically in low level assembly code as scratch registers or to hold per-cpu global infos such as the PACA or the current thread_info pointer. We want to be able to easily shuffle the usage of those registers as some implementations have specific constraints realted to some of them, for example, some have userspace readable aliases, etc.. and the current choice isn't always the best. This patch should not change any code generation, and replaces the usage of SPRN_SPRGn everywhere in the kernel with a named replacement and adds documentation next to the definition of the names as to what those are used for on each processor family. The only parts that still use the original numbers are bits of KVM or suspend/resume code that just blindly needs to save/restore all the SPRGs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/exception-64s.h18
-rw-r--r--arch/powerpc/include/asm/reg.h113
-rw-r--r--arch/powerpc/kernel/cpu_setup_6xx.S2
-rw-r--r--arch/powerpc/kernel/entry_32.S20
-rw-r--r--arch/powerpc/kernel/entry_64.S4
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S44
-rw-r--r--arch/powerpc/kernel/fpu.S2
-rw-r--r--arch/powerpc/kernel/head_32.S40
-rw-r--r--arch/powerpc/kernel/head_40x.S124
-rw-r--r--arch/powerpc/kernel/head_44x.S56
-rw-r--r--arch/powerpc/kernel/head_64.S14
-rw-r--r--arch/powerpc/kernel/head_8xx.S13
-rw-r--r--arch/powerpc/kernel/head_booke.h50
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S60
-rw-r--r--arch/powerpc/kernel/setup_64.c4
-rw-r--r--arch/powerpc/kernel/vector.S2
-rw-r--r--arch/powerpc/kvm/booke_interrupts.S18
-rw-r--r--arch/powerpc/mm/hash_low_32.S4
-rw-r--r--arch/powerpc/platforms/iseries/exception.S28
-rw-r--r--arch/powerpc/platforms/iseries/exception.h4
20 files changed, 356 insertions, 264 deletions
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index d3d4534e3c74..773e380b5fe8 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -57,12 +57,12 @@
57 addi reg,reg,(label)-_stext; /* virt addr of handler ... */ 57 addi reg,reg,(label)-_stext; /* virt addr of handler ... */
58 58
59#define EXCEPTION_PROLOG_1(area) \ 59#define EXCEPTION_PROLOG_1(area) \
60 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 60 mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
61 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 61 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
62 std r10,area+EX_R10(r13); \ 62 std r10,area+EX_R10(r13); \
63 std r11,area+EX_R11(r13); \ 63 std r11,area+EX_R11(r13); \
64 std r12,area+EX_R12(r13); \ 64 std r12,area+EX_R12(r13); \
65 mfspr r9,SPRN_SPRG1; \ 65 mfspr r9,SPRN_SPRG_SCRATCH0; \
66 std r9,area+EX_R13(r13); \ 66 std r9,area+EX_R13(r13); \
67 mfcr r9 67 mfcr r9
68 68
@@ -144,7 +144,7 @@
144 .globl label##_pSeries; \ 144 .globl label##_pSeries; \
145label##_pSeries: \ 145label##_pSeries: \
146 HMT_MEDIUM; \ 146 HMT_MEDIUM; \
147 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 147 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
148 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 148 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
149 149
150#define HSTD_EXCEPTION_PSERIES(n, label) \ 150#define HSTD_EXCEPTION_PSERIES(n, label) \
@@ -152,13 +152,13 @@ label##_pSeries: \
152 .globl label##_pSeries; \ 152 .globl label##_pSeries; \
153label##_pSeries: \ 153label##_pSeries: \
154 HMT_MEDIUM; \ 154 HMT_MEDIUM; \
155 mtspr SPRN_SPRG1,r20; /* save r20 */ \ 155 mtspr SPRN_SPRG_SCRATCH0,r20; /* save r20 */ \
156 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ 156 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
157 mtspr SPRN_SRR0,r20; \ 157 mtspr SPRN_SRR0,r20; \
158 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ 158 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
159 mtspr SPRN_SRR1,r20; \ 159 mtspr SPRN_SRR1,r20; \
160 mfspr r20,SPRN_SPRG1; /* restore r20 */ \ 160 mfspr r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
161 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 161 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
162 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 162 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
163 163
164 164
@@ -167,15 +167,15 @@ label##_pSeries: \
167 .globl label##_pSeries; \ 167 .globl label##_pSeries; \
168label##_pSeries: \ 168label##_pSeries: \
169 HMT_MEDIUM; \ 169 HMT_MEDIUM; \
170 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 170 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
171 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 171 mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
172 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ 172 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
173 std r10,PACA_EXGEN+EX_R10(r13); \ 173 std r10,PACA_EXGEN+EX_R10(r13); \
174 lbz r10,PACASOFTIRQEN(r13); \ 174 lbz r10,PACASOFTIRQEN(r13); \
175 mfcr r9; \ 175 mfcr r9; \
176 cmpwi r10,0; \ 176 cmpwi r10,0; \
177 beq masked_interrupt; \ 177 beq masked_interrupt; \
178 mfspr r10,SPRN_SPRG1; \ 178 mfspr r10,SPRN_SPRG_SCRATCH0; \
179 std r10,PACA_EXGEN+EX_R13(r13); \ 179 std r10,PACA_EXGEN+EX_R13(r13); \
180 std r11,PACA_EXGEN+EX_R11(r13); \ 180 std r11,PACA_EXGEN+EX_R11(r13); \
181 std r12,PACA_EXGEN+EX_R12(r13); \ 181 std r12,PACA_EXGEN+EX_R12(r13); \
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1170267736d3..a8179cc99ac4 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -646,6 +646,119 @@
646#endif 646#endif
647 647
648/* 648/*
649 * SPRG usage:
650 *
651 * All 64-bit:
652 * - SPRG3 stores PACA pointer
653 *
654 * 64-bit server:
655 * - SPRG0 unused (reserved for HV on Power4)
656 * - SPRG1 scratch for exception vectors
657 * - SPRG2 scratch for exception vectors
658 *
659 * All 32-bit:
660 * - SPRG3 current thread_info pointer
661 * (virtual on BookE, physical on others)
662 *
663 * 32-bit classic:
664 * - SPRG0 scratch for exception vectors
665 * - SPRG1 scratch for exception vectors
666 * - SPRG2 indicator that we are in RTAS
667 * - SPRG4 (603 only) pseudo TLB LRU data
668 *
669 * 32-bit 40x:
670 * - SPRG0 scratch for exception vectors
671 * - SPRG1 scratch for exception vectors
672 * - SPRG2 scratch for exception vectors
673 * - SPRG4 scratch for exception vectors (not 403)
674 * - SPRG5 scratch for exception vectors (not 403)
675 * - SPRG6 scratch for exception vectors (not 403)
676 * - SPRG7 scratch for exception vectors (not 403)
677 *
678 * 32-bit 440 and FSL BookE:
679 * - SPRG0 scratch for exception vectors
680 * - SPRG1 scratch for exception vectors (*)
681 * - SPRG2 scratch for crit interrupts handler
682 * - SPRG4 scratch for exception vectors
683 * - SPRG5 scratch for exception vectors
684 * - SPRG6 scratch for machine check handler
685 * - SPRG7 scratch for exception vectors
686 * - SPRG9 scratch for debug vectors (e500 only)
687 *
688 * Additionally, BookE separates "read" and "write"
689 * of those registers. That allows to use the userspace
690 * readable variant for reads, which can avoid a fault
691 * with KVM type virtualization.
692 *
693 * (*) Under KVM, the host SPRG1 is used to point to
694 * the current VCPU data structure
695 *
696 * 32-bit 8xx:
697 * - SPRG0 scratch for exception vectors
698 * - SPRG1 scratch for exception vectors
699 * - SPRG2 apparently unused but initialized
700 *
701 */
702#ifdef CONFIG_PPC64
703#define SPRN_SPRG_PACA SPRN_SPRG3
704#else
705#define SPRN_SPRG_THREAD SPRN_SPRG3
706#endif
707
708#ifdef CONFIG_PPC_BOOK3S_64
709#define SPRN_SPRG_SCRATCH0 SPRN_SPRG1
710#define SPRN_SPRG_SCRATCH1 SPRN_SPRG2
711#endif
712
713#ifdef CONFIG_PPC_BOOK3S_32
714#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
715#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
716#define SPRN_SPRG_RTAS SPRN_SPRG2
717#define SPRN_SPRG_603_LRU SPRN_SPRG4
718#endif
719
720#ifdef CONFIG_40x
721#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
722#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
723#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
724#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
725#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
726#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
727#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
728#endif
729
730#ifdef CONFIG_BOOKE
731#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
732#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
733#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
734#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
735#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
736#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
737#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
738#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
739#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
740#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
741#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R
742#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W
743#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
744#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
745#ifdef CONFIG_E200
746#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
747#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
748#else
749#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
750#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
751#endif
752#define SPRN_SPRG_RVCPU SPRN_SPRG1
753#define SPRN_SPRG_WVCPU SPRN_SPRG1
754#endif
755
756#ifdef CONFIG_8xx
757#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
758#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
759#endif
760
761/*
649 * An mtfsf instruction with the L bit set. On CPUs that support this a 762 * An mtfsf instruction with the L bit set. On CPUs that support this a
650 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 763 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
651 * 764 *
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 1e9949e68856..55cba4a8a959 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -21,7 +21,7 @@ _GLOBAL(__setup_cpu_603)
21 mflr r4 21 mflr r4
22BEGIN_MMU_FTR_SECTION 22BEGIN_MMU_FTR_SECTION
23 li r10,0 23 li r10,0
24 mtspr SPRN_SPRG4,r10 /* init SW LRU tracking */ 24 mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
25END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) 25END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
26BEGIN_FTR_SECTION 26BEGIN_FTR_SECTION
27 bl __init_fpu_registers 27 bl __init_fpu_registers
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 3cadba60a4b6..1175a8539e6c 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -88,7 +88,7 @@ crit_transfer_to_handler:
88 mfspr r0,SPRN_SRR1 88 mfspr r0,SPRN_SRR1
89 stw r0,_SRR1(r11) 89 stw r0,_SRR1(r11)
90 90
91 mfspr r8,SPRN_SPRG3 91 mfspr r8,SPRN_SPRG_THREAD
92 lwz r0,KSP_LIMIT(r8) 92 lwz r0,KSP_LIMIT(r8)
93 stw r0,SAVED_KSP_LIMIT(r11) 93 stw r0,SAVED_KSP_LIMIT(r11)
94 rlwimi r0,r1,0,0,(31-THREAD_SHIFT) 94 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
@@ -108,7 +108,7 @@ crit_transfer_to_handler:
108 mfspr r0,SPRN_SRR1 108 mfspr r0,SPRN_SRR1
109 stw r0,crit_srr1@l(0) 109 stw r0,crit_srr1@l(0)
110 110
111 mfspr r8,SPRN_SPRG3 111 mfspr r8,SPRN_SPRG_THREAD
112 lwz r0,KSP_LIMIT(r8) 112 lwz r0,KSP_LIMIT(r8)
113 stw r0,saved_ksp_limit@l(0) 113 stw r0,saved_ksp_limit@l(0)
114 rlwimi r0,r1,0,0,(31-THREAD_SHIFT) 114 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
@@ -138,7 +138,7 @@ transfer_to_handler:
138 mfspr r2,SPRN_XER 138 mfspr r2,SPRN_XER
139 stw r12,_CTR(r11) 139 stw r12,_CTR(r11)
140 stw r2,_XER(r11) 140 stw r2,_XER(r11)
141 mfspr r12,SPRN_SPRG3 141 mfspr r12,SPRN_SPRG_THREAD
142 addi r2,r12,-THREAD 142 addi r2,r12,-THREAD
143 tovirt(r2,r2) /* set r2 to current */ 143 tovirt(r2,r2) /* set r2 to current */
144 beq 2f /* if from user, fix up THREAD.regs */ 144 beq 2f /* if from user, fix up THREAD.regs */
@@ -680,7 +680,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE)
680 680
681 tophys(r0,r4) 681 tophys(r0,r4)
682 CLR_TOP32(r0) 682 CLR_TOP32(r0)
683 mtspr SPRN_SPRG3,r0 /* Update current THREAD phys addr */ 683 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
684 lwz r1,KSP(r4) /* Load new stack pointer */ 684 lwz r1,KSP(r4) /* Load new stack pointer */
685 685
686 /* save the old current 'last' for return value */ 686 /* save the old current 'last' for return value */
@@ -1057,7 +1057,7 @@ exc_exit_restart_end:
1057#ifdef CONFIG_40x 1057#ifdef CONFIG_40x
1058 .globl ret_from_crit_exc 1058 .globl ret_from_crit_exc
1059ret_from_crit_exc: 1059ret_from_crit_exc:
1060 mfspr r9,SPRN_SPRG3 1060 mfspr r9,SPRN_SPRG_THREAD
1061 lis r10,saved_ksp_limit@ha; 1061 lis r10,saved_ksp_limit@ha;
1062 lwz r10,saved_ksp_limit@l(r10); 1062 lwz r10,saved_ksp_limit@l(r10);
1063 tovirt(r9,r9); 1063 tovirt(r9,r9);
@@ -1074,7 +1074,7 @@ ret_from_crit_exc:
1074#ifdef CONFIG_BOOKE 1074#ifdef CONFIG_BOOKE
1075 .globl ret_from_crit_exc 1075 .globl ret_from_crit_exc
1076ret_from_crit_exc: 1076ret_from_crit_exc:
1077 mfspr r9,SPRN_SPRG3 1077 mfspr r9,SPRN_SPRG_THREAD
1078 lwz r10,SAVED_KSP_LIMIT(r1) 1078 lwz r10,SAVED_KSP_LIMIT(r1)
1079 stw r10,KSP_LIMIT(r9) 1079 stw r10,KSP_LIMIT(r9)
1080 RESTORE_xSRR(SRR0,SRR1); 1080 RESTORE_xSRR(SRR0,SRR1);
@@ -1083,7 +1083,7 @@ ret_from_crit_exc:
1083 1083
1084 .globl ret_from_debug_exc 1084 .globl ret_from_debug_exc
1085ret_from_debug_exc: 1085ret_from_debug_exc:
1086 mfspr r9,SPRN_SPRG3 1086 mfspr r9,SPRN_SPRG_THREAD
1087 lwz r10,SAVED_KSP_LIMIT(r1) 1087 lwz r10,SAVED_KSP_LIMIT(r1)
1088 stw r10,KSP_LIMIT(r9) 1088 stw r10,KSP_LIMIT(r9)
1089 lwz r9,THREAD_INFO-THREAD(r9) 1089 lwz r9,THREAD_INFO-THREAD(r9)
@@ -1097,7 +1097,7 @@ ret_from_debug_exc:
1097 1097
1098 .globl ret_from_mcheck_exc 1098 .globl ret_from_mcheck_exc
1099ret_from_mcheck_exc: 1099ret_from_mcheck_exc:
1100 mfspr r9,SPRN_SPRG3 1100 mfspr r9,SPRN_SPRG_THREAD
1101 lwz r10,SAVED_KSP_LIMIT(r1) 1101 lwz r10,SAVED_KSP_LIMIT(r1)
1102 stw r10,KSP_LIMIT(r9) 1102 stw r10,KSP_LIMIT(r9)
1103 RESTORE_xSRR(SRR0,SRR1); 1103 RESTORE_xSRR(SRR0,SRR1);
@@ -1255,7 +1255,7 @@ _GLOBAL(enter_rtas)
1255 MTMSRD(r0) /* don't get trashed */ 1255 MTMSRD(r0) /* don't get trashed */
1256 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR) 1256 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1257 mtlr r6 1257 mtlr r6
1258 mtspr SPRN_SPRG2,r7 1258 mtspr SPRN_SPRG_RTAS,r7
1259 mtspr SPRN_SRR0,r8 1259 mtspr SPRN_SRR0,r8
1260 mtspr SPRN_SRR1,r9 1260 mtspr SPRN_SRR1,r9
1261 RFI 1261 RFI
@@ -1265,7 +1265,7 @@ _GLOBAL(enter_rtas)
1265 FIX_SRR1(r9,r0) 1265 FIX_SRR1(r9,r0)
1266 addi r1,r1,INT_FRAME_SIZE 1266 addi r1,r1,INT_FRAME_SIZE
1267 li r0,0 1267 li r0,0
1268 mtspr SPRN_SPRG2,r0 1268 mtspr SPRN_SPRG_RTAS,r0
1269 mtspr SPRN_SRR0,r8 1269 mtspr SPRN_SRR0,r8
1270 mtspr SPRN_SRR1,r9 1270 mtspr SPRN_SRR1,r9
1271 RFI /* return to caller */ 1271 RFI /* return to caller */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 43e073477c34..dbf0e3115611 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -762,7 +762,7 @@ _GLOBAL(enter_rtas)
762 762
763_STATIC(rtas_return_loc) 763_STATIC(rtas_return_loc)
764 /* relocation is off at this point */ 764 /* relocation is off at this point */
765 mfspr r4,SPRN_SPRG3 /* Get PACA */ 765 mfspr r4,SPRN_SPRG_PACA /* Get PACA */
766 clrldi r4,r4,2 /* convert to realmode address */ 766 clrldi r4,r4,2 /* convert to realmode address */
767 767
768 bcl 20,31,$+4 768 bcl 20,31,$+4
@@ -793,7 +793,7 @@ _STATIC(rtas_restore_regs)
793 REST_8GPRS(14, r1) /* Restore the non-volatiles */ 793 REST_8GPRS(14, r1) /* Restore the non-volatiles */
794 REST_10GPRS(22, r1) /* ditto */ 794 REST_10GPRS(22, r1) /* ditto */
795 795
796 mfspr r13,SPRN_SPRG3 796 mfspr r13,SPRN_SPRG_PACA
797 797
798 ld r4,_CCR(r1) 798 ld r4,_CCR(r1)
799 mtcr r4 799 mtcr r4
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 72644cf22cac..4e9640cc0563 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -24,18 +24,6 @@
24 * 0x8000 - : Early init and support code 24 * 0x8000 - : Early init and support code
25 */ 25 */
26 26
27
28/*
29 * SPRG Usage
30 *
31 * Register Definition
32 *
33 * SPRG0 reserved for hypervisor
34 * SPRG1 temp - used to save gpr
35 * SPRG2 temp - used to save gpr
36 * SPRG3 virt addr of paca
37 */
38
39/* 27/*
40 * This is the start of the interrupt handlers for pSeries 28 * This is the start of the interrupt handlers for pSeries
41 * This code runs with relocation off. 29 * This code runs with relocation off.
@@ -53,16 +41,16 @@ __start_interrupts:
53 . = 0x200 41 . = 0x200
54_machine_check_pSeries: 42_machine_check_pSeries:
55 HMT_MEDIUM 43 HMT_MEDIUM
56 mtspr SPRN_SPRG1,r13 /* save r13 */ 44 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
57 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 45 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
58 46
59 . = 0x300 47 . = 0x300
60 .globl data_access_pSeries 48 .globl data_access_pSeries
61data_access_pSeries: 49data_access_pSeries:
62 HMT_MEDIUM 50 HMT_MEDIUM
63 mtspr SPRN_SPRG1,r13 51 mtspr SPRN_SPRG_SCRATCH0,r13
64BEGIN_FTR_SECTION 52BEGIN_FTR_SECTION
65 mtspr SPRN_SPRG2,r12 53 mtspr SPRN_SPRG_SCRATCH1,r12
66 mfspr r13,SPRN_DAR 54 mfspr r13,SPRN_DAR
67 mfspr r12,SPRN_DSISR 55 mfspr r12,SPRN_DSISR
68 srdi r13,r13,60 56 srdi r13,r13,60
@@ -71,7 +59,7 @@ BEGIN_FTR_SECTION
71 cmpwi r13,0x2c 59 cmpwi r13,0x2c
72 beq do_stab_bolted_pSeries 60 beq do_stab_bolted_pSeries
73 mtcrf 0x80,r12 61 mtcrf 0x80,r12
74 mfspr r12,SPRN_SPRG2 62 mfspr r12,SPRN_SPRG_SCRATCH1
75END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 63END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
76 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 64 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
77 65
@@ -79,8 +67,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
79 .globl data_access_slb_pSeries 67 .globl data_access_slb_pSeries
80data_access_slb_pSeries: 68data_access_slb_pSeries:
81 HMT_MEDIUM 69 HMT_MEDIUM
82 mtspr SPRN_SPRG1,r13 70 mtspr SPRN_SPRG_SCRATCH0,r13
83 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 71 mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
84 std r3,PACA_EXSLB+EX_R3(r13) 72 std r3,PACA_EXSLB+EX_R3(r13)
85 mfspr r3,SPRN_DAR 73 mfspr r3,SPRN_DAR
86 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 74 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
@@ -93,7 +81,7 @@ data_access_slb_pSeries:
93 std r10,PACA_EXSLB+EX_R10(r13) 81 std r10,PACA_EXSLB+EX_R10(r13)
94 std r11,PACA_EXSLB+EX_R11(r13) 82 std r11,PACA_EXSLB+EX_R11(r13)
95 std r12,PACA_EXSLB+EX_R12(r13) 83 std r12,PACA_EXSLB+EX_R12(r13)
96 mfspr r10,SPRN_SPRG1 84 mfspr r10,SPRN_SPRG_SCRATCH0
97 std r10,PACA_EXSLB+EX_R13(r13) 85 std r10,PACA_EXSLB+EX_R13(r13)
98 mfspr r12,SPRN_SRR1 /* and SRR1 */ 86 mfspr r12,SPRN_SRR1 /* and SRR1 */
99#ifndef CONFIG_RELOCATABLE 87#ifndef CONFIG_RELOCATABLE
@@ -117,8 +105,8 @@ data_access_slb_pSeries:
117 .globl instruction_access_slb_pSeries 105 .globl instruction_access_slb_pSeries
118instruction_access_slb_pSeries: 106instruction_access_slb_pSeries:
119 HMT_MEDIUM 107 HMT_MEDIUM
120 mtspr SPRN_SPRG1,r13 108 mtspr SPRN_SPRG_SCRATCH0,r13
121 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 109 mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
122 std r3,PACA_EXSLB+EX_R3(r13) 110 std r3,PACA_EXSLB+EX_R3(r13)
123 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 111 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
124 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 112 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
@@ -131,7 +119,7 @@ instruction_access_slb_pSeries:
131 std r10,PACA_EXSLB+EX_R10(r13) 119 std r10,PACA_EXSLB+EX_R10(r13)
132 std r11,PACA_EXSLB+EX_R11(r13) 120 std r11,PACA_EXSLB+EX_R11(r13)
133 std r12,PACA_EXSLB+EX_R12(r13) 121 std r12,PACA_EXSLB+EX_R12(r13)
134 mfspr r10,SPRN_SPRG1 122 mfspr r10,SPRN_SPRG_SCRATCH0
135 std r10,PACA_EXSLB+EX_R13(r13) 123 std r10,PACA_EXSLB+EX_R13(r13)
136 mfspr r12,SPRN_SRR1 /* and SRR1 */ 124 mfspr r12,SPRN_SRR1 /* and SRR1 */
137#ifndef CONFIG_RELOCATABLE 125#ifndef CONFIG_RELOCATABLE
@@ -161,7 +149,7 @@ BEGIN_FTR_SECTION
161 beq- 1f 149 beq- 1f
162END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 150END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
163 mr r9,r13 151 mr r9,r13
164 mfspr r13,SPRN_SPRG3 152 mfspr r13,SPRN_SPRG_PACA
165 mfspr r11,SPRN_SRR0 153 mfspr r11,SPRN_SRR0
166 ld r12,PACAKBASE(r13) 154 ld r12,PACAKBASE(r13)
167 ld r10,PACAKMSR(r13) 155 ld r10,PACAKMSR(r13)
@@ -230,14 +218,14 @@ masked_interrupt:
230 rotldi r10,r10,16 218 rotldi r10,r10,16
231 mtspr SPRN_SRR1,r10 219 mtspr SPRN_SRR1,r10
232 ld r10,PACA_EXGEN+EX_R10(r13) 220 ld r10,PACA_EXGEN+EX_R10(r13)
233 mfspr r13,SPRN_SPRG1 221 mfspr r13,SPRN_SPRG_SCRATCH0
234 rfid 222 rfid
235 b . 223 b .
236 224
237 .align 7 225 .align 7
238do_stab_bolted_pSeries: 226do_stab_bolted_pSeries:
239 mtcrf 0x80,r12 227 mtcrf 0x80,r12
240 mfspr r12,SPRN_SPRG2 228 mfspr r12,SPRN_SPRG_SCRATCH1
241 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 229 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
242 230
243#ifdef CONFIG_PPC_PSERIES 231#ifdef CONFIG_PPC_PSERIES
@@ -248,14 +236,14 @@ do_stab_bolted_pSeries:
248 .align 7 236 .align 7
249system_reset_fwnmi: 237system_reset_fwnmi:
250 HMT_MEDIUM 238 HMT_MEDIUM
251 mtspr SPRN_SPRG1,r13 /* save r13 */ 239 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
252 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) 240 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
253 241
254 .globl machine_check_fwnmi 242 .globl machine_check_fwnmi
255 .align 7 243 .align 7
256machine_check_fwnmi: 244machine_check_fwnmi:
257 HMT_MEDIUM 245 HMT_MEDIUM
258 mtspr SPRN_SPRG1,r13 /* save r13 */ 246 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
259 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 247 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
260 248
261#endif /* CONFIG_PPC_PSERIES */ 249#endif /* CONFIG_PPC_PSERIES */
@@ -270,7 +258,7 @@ slb_miss_user_pseries:
270 std r10,PACA_EXGEN+EX_R10(r13) 258 std r10,PACA_EXGEN+EX_R10(r13)
271 std r11,PACA_EXGEN+EX_R11(r13) 259 std r11,PACA_EXGEN+EX_R11(r13)
272 std r12,PACA_EXGEN+EX_R12(r13) 260 std r12,PACA_EXGEN+EX_R12(r13)
273 mfspr r10,SPRG1 261 mfspr r10,SPRG_SCRATCH0
274 ld r11,PACA_EXSLB+EX_R9(r13) 262 ld r11,PACA_EXSLB+EX_R9(r13)
275 ld r12,PACA_EXSLB+EX_R3(r13) 263 ld r12,PACA_EXSLB+EX_R3(r13)
276 std r10,PACA_EXGEN+EX_R13(r13) 264 std r10,PACA_EXGEN+EX_R13(r13)
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 2436df33c6f4..fc8f5b14019c 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -91,7 +91,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
91#endif /* CONFIG_SMP */ 91#endif /* CONFIG_SMP */
92 /* enable use of FP after return */ 92 /* enable use of FP after return */
93#ifdef CONFIG_PPC32 93#ifdef CONFIG_PPC32
94 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 94 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
95 lwz r4,THREAD_FPEXC_MODE(r5) 95 lwz r4,THREAD_FPEXC_MODE(r5)
96 ori r9,r9,MSR_FP /* enable FP for current */ 96 ori r9,r9,MSR_FP /* enable FP for current */
97 or r9,r9,r4 97 or r9,r9,r4
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index fc2132942754..829c3fe7c5a2 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -244,8 +244,8 @@ __secondary_hold_acknowledge:
244 * task's thread_struct. 244 * task's thread_struct.
245 */ 245 */
246#define EXCEPTION_PROLOG \ 246#define EXCEPTION_PROLOG \
247 mtspr SPRN_SPRG0,r10; \ 247 mtspr SPRN_SPRG_SCRATCH0,r10; \
248 mtspr SPRN_SPRG1,r11; \ 248 mtspr SPRN_SPRG_SCRATCH1,r11; \
249 mfcr r10; \ 249 mfcr r10; \
250 EXCEPTION_PROLOG_1; \ 250 EXCEPTION_PROLOG_1; \
251 EXCEPTION_PROLOG_2 251 EXCEPTION_PROLOG_2
@@ -255,7 +255,7 @@ __secondary_hold_acknowledge:
255 andi. r11,r11,MSR_PR; \ 255 andi. r11,r11,MSR_PR; \
256 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 256 tophys(r11,r1); /* use tophys(r1) if kernel */ \
257 beq 1f; \ 257 beq 1f; \
258 mfspr r11,SPRN_SPRG3; \ 258 mfspr r11,SPRN_SPRG_THREAD; \
259 lwz r11,THREAD_INFO-THREAD(r11); \ 259 lwz r11,THREAD_INFO-THREAD(r11); \
260 addi r11,r11,THREAD_SIZE; \ 260 addi r11,r11,THREAD_SIZE; \
261 tophys(r11,r11); \ 261 tophys(r11,r11); \
@@ -267,9 +267,9 @@ __secondary_hold_acknowledge:
267 stw r10,_CCR(r11); /* save registers */ \ 267 stw r10,_CCR(r11); /* save registers */ \
268 stw r12,GPR12(r11); \ 268 stw r12,GPR12(r11); \
269 stw r9,GPR9(r11); \ 269 stw r9,GPR9(r11); \
270 mfspr r10,SPRN_SPRG0; \ 270 mfspr r10,SPRN_SPRG_SCRATCH0; \
271 stw r10,GPR10(r11); \ 271 stw r10,GPR10(r11); \
272 mfspr r12,SPRN_SPRG1; \ 272 mfspr r12,SPRN_SPRG_SCRATCH1; \
273 stw r12,GPR11(r11); \ 273 stw r12,GPR11(r11); \
274 mflr r10; \ 274 mflr r10; \
275 stw r10,_LINK(r11); \ 275 stw r10,_LINK(r11); \
@@ -355,11 +355,11 @@ i##n: \
355 * -- paulus. 355 * -- paulus.
356 */ 356 */
357 . = 0x200 357 . = 0x200
358 mtspr SPRN_SPRG0,r10 358 mtspr SPRN_SPRG_SCRATCH0,r10
359 mtspr SPRN_SPRG1,r11 359 mtspr SPRN_SPRG_SCRATCH1,r11
360 mfcr r10 360 mfcr r10
361#ifdef CONFIG_PPC_CHRP 361#ifdef CONFIG_PPC_CHRP
362 mfspr r11,SPRN_SPRG2 362 mfspr r11,SPRN_SPRG_RTAS
363 cmpwi 0,r11,0 363 cmpwi 0,r11,0
364 bne 7f 364 bne 7f
365#endif /* CONFIG_PPC_CHRP */ 365#endif /* CONFIG_PPC_CHRP */
@@ -367,7 +367,7 @@ i##n: \
3677: EXCEPTION_PROLOG_2 3677: EXCEPTION_PROLOG_2
368 addi r3,r1,STACK_FRAME_OVERHEAD 368 addi r3,r1,STACK_FRAME_OVERHEAD
369#ifdef CONFIG_PPC_CHRP 369#ifdef CONFIG_PPC_CHRP
370 mfspr r4,SPRN_SPRG2 370 mfspr r4,SPRN_SPRG_RTAS
371 cmpwi cr1,r4,0 371 cmpwi cr1,r4,0
372 bne cr1,1f 372 bne cr1,1f
373#endif 373#endif
@@ -485,7 +485,7 @@ InstructionTLBMiss:
485 mfspr r3,SPRN_IMISS 485 mfspr r3,SPRN_IMISS
486 lis r1,PAGE_OFFSET@h /* check if kernel address */ 486 lis r1,PAGE_OFFSET@h /* check if kernel address */
487 cmplw 0,r1,r3 487 cmplw 0,r1,r3
488 mfspr r2,SPRN_SPRG3 488 mfspr r2,SPRN_SPRG_THREAD
489 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ 489 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
490 lwz r2,PGDIR(r2) 490 lwz r2,PGDIR(r2)
491 bge- 112f 491 bge- 112f
@@ -559,7 +559,7 @@ DataLoadTLBMiss:
559 mfspr r3,SPRN_DMISS 559 mfspr r3,SPRN_DMISS
560 lis r1,PAGE_OFFSET@h /* check if kernel address */ 560 lis r1,PAGE_OFFSET@h /* check if kernel address */
561 cmplw 0,r1,r3 561 cmplw 0,r1,r3
562 mfspr r2,SPRN_SPRG3 562 mfspr r2,SPRN_SPRG_THREAD
563 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ 563 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
564 lwz r2,PGDIR(r2) 564 lwz r2,PGDIR(r2)
565 bge- 112f 565 bge- 112f
@@ -598,12 +598,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
598 mtcrf 0x80,r2 598 mtcrf 0x80,r2
599BEGIN_MMU_FTR_SECTION 599BEGIN_MMU_FTR_SECTION
600 li r0,1 600 li r0,1
601 mfspr r1,SPRN_SPRG4 601 mfspr r1,SPRN_SPRG_603_LRU
602 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */ 602 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
603 slw r0,r0,r2 603 slw r0,r0,r2
604 xor r1,r0,r1 604 xor r1,r0,r1
605 srw r0,r1,r2 605 srw r0,r1,r2
606 mtspr SPRN_SPRG4,r1 606 mtspr SPRN_SPRG_603_LRU,r1
607 mfspr r2,SPRN_SRR1 607 mfspr r2,SPRN_SRR1
608 rlwimi r2,r0,31-14,14,14 608 rlwimi r2,r0,31-14,14,14
609 mtspr SPRN_SRR1,r2 609 mtspr SPRN_SRR1,r2
@@ -643,7 +643,7 @@ DataStoreTLBMiss:
643 mfspr r3,SPRN_DMISS 643 mfspr r3,SPRN_DMISS
644 lis r1,PAGE_OFFSET@h /* check if kernel address */ 644 lis r1,PAGE_OFFSET@h /* check if kernel address */
645 cmplw 0,r1,r3 645 cmplw 0,r1,r3
646 mfspr r2,SPRN_SPRG3 646 mfspr r2,SPRN_SPRG_THREAD
647 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ 647 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
648 lwz r2,PGDIR(r2) 648 lwz r2,PGDIR(r2)
649 bge- 112f 649 bge- 112f
@@ -678,12 +678,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
678 mtcrf 0x80,r2 678 mtcrf 0x80,r2
679BEGIN_MMU_FTR_SECTION 679BEGIN_MMU_FTR_SECTION
680 li r0,1 680 li r0,1
681 mfspr r1,SPRN_SPRG4 681 mfspr r1,SPRN_SPRG_603_LRU
682 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */ 682 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
683 slw r0,r0,r2 683 slw r0,r0,r2
684 xor r1,r0,r1 684 xor r1,r0,r1
685 srw r0,r1,r2 685 srw r0,r1,r2
686 mtspr SPRN_SPRG4,r1 686 mtspr SPRN_SPRG_603_LRU,r1
687 mfspr r2,SPRN_SRR1 687 mfspr r2,SPRN_SRR1
688 rlwimi r2,r0,31-14,14,14 688 rlwimi r2,r0,31-14,14,14
689 mtspr SPRN_SRR1,r2 689 mtspr SPRN_SRR1,r2
@@ -864,9 +864,9 @@ __secondary_start:
864 tophys(r4,r2) 864 tophys(r4,r2)
865 addi r4,r4,THREAD /* phys address of our thread_struct */ 865 addi r4,r4,THREAD /* phys address of our thread_struct */
866 CLR_TOP32(r4) 866 CLR_TOP32(r4)
867 mtspr SPRN_SPRG3,r4 867 mtspr SPRN_SPRG_THREAD,r4
868 li r3,0 868 li r3,0
869 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ 869 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
870 870
871 /* enable MMU and jump to start_secondary */ 871 /* enable MMU and jump to start_secondary */
872 li r4,MSR_KERNEL 872 li r4,MSR_KERNEL
@@ -947,9 +947,9 @@ start_here:
947 tophys(r4,r2) 947 tophys(r4,r2)
948 addi r4,r4,THREAD /* init task's THREAD */ 948 addi r4,r4,THREAD /* init task's THREAD */
949 CLR_TOP32(r4) 949 CLR_TOP32(r4)
950 mtspr SPRN_SPRG3,r4 950 mtspr SPRN_SPRG_THREAD,r4
951 li r3,0 951 li r3,0
952 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ 952 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
953 953
954 /* stack */ 954 /* stack */
955 lis r1,init_thread_union@ha 955 lis r1,init_thread_union@ha
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 0c96911d4299..a90625f9b485 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -103,21 +103,21 @@ _ENTRY(saved_ksp_limit)
103 103
104/* 104/*
105 * Exception vector entry code. This code runs with address translation 105 * Exception vector entry code. This code runs with address translation
106 * turned off (i.e. using physical addresses). We assume SPRG3 has the 106 * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
107 * physical address of the current task thread_struct. 107 * the physical address of the current task thread_struct.
108 * Note that we have to have decremented r1 before we write to any fields 108 * Note that we have to have decremented r1 before we write to any fields
109 * of the exception frame, since a critical interrupt could occur at any 109 * of the exception frame, since a critical interrupt could occur at any
110 * time, and it will write to the area immediately below the current r1. 110 * time, and it will write to the area immediately below the current r1.
111 */ 111 */
112#define NORMAL_EXCEPTION_PROLOG \ 112#define NORMAL_EXCEPTION_PROLOG \
113 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ 113 mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
114 mtspr SPRN_SPRG1,r11; \ 114 mtspr SPRN_SPRG_SCRATCH1,r11; \
115 mtspr SPRN_SPRG2,r1; \ 115 mtspr SPRN_SPRG_SCRATCH2,r1; \
116 mfcr r10; /* save CR in r10 for now */\ 116 mfcr r10; /* save CR in r10 for now */\
117 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ 117 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
118 andi. r11,r11,MSR_PR; \ 118 andi. r11,r11,MSR_PR; \
119 beq 1f; \ 119 beq 1f; \
120 mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ 120 mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\
121 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ 121 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
122 addi r1,r1,THREAD_SIZE; \ 122 addi r1,r1,THREAD_SIZE; \
1231: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ 1231: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
@@ -125,13 +125,13 @@ _ENTRY(saved_ksp_limit)
125 stw r10,_CCR(r11); /* save various registers */\ 125 stw r10,_CCR(r11); /* save various registers */\
126 stw r12,GPR12(r11); \ 126 stw r12,GPR12(r11); \
127 stw r9,GPR9(r11); \ 127 stw r9,GPR9(r11); \
128 mfspr r10,SPRN_SPRG0; \ 128 mfspr r10,SPRN_SPRG_SCRATCH0; \
129 stw r10,GPR10(r11); \ 129 stw r10,GPR10(r11); \
130 mfspr r12,SPRN_SPRG1; \ 130 mfspr r12,SPRN_SPRG_SCRATCH1; \
131 stw r12,GPR11(r11); \ 131 stw r12,GPR11(r11); \
132 mflr r10; \ 132 mflr r10; \
133 stw r10,_LINK(r11); \ 133 stw r10,_LINK(r11); \
134 mfspr r10,SPRN_SPRG2; \ 134 mfspr r10,SPRN_SPRG_SCRATCH2; \
135 mfspr r12,SPRN_SRR0; \ 135 mfspr r12,SPRN_SRR0; \
136 stw r10,GPR1(r11); \ 136 stw r10,GPR1(r11); \
137 mfspr r9,SPRN_SRR1; \ 137 mfspr r9,SPRN_SRR1; \
@@ -160,7 +160,7 @@ _ENTRY(saved_ksp_limit)
160 lwz r11,critirq_ctx@l(r11); \ 160 lwz r11,critirq_ctx@l(r11); \
161 beq 1f; \ 161 beq 1f; \
162 /* COMING FROM USER MODE */ \ 162 /* COMING FROM USER MODE */ \
163 mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ 163 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
164 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 164 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
1651: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\ 1651: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\
166 tophys(r11,r11); \ 166 tophys(r11,r11); \
@@ -265,8 +265,8 @@ label:
265 * and exit. Otherwise, we call heavywight functions to do the work. 265 * and exit. Otherwise, we call heavywight functions to do the work.
266 */ 266 */
267 START_EXCEPTION(0x0300, DataStorage) 267 START_EXCEPTION(0x0300, DataStorage)
268 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 268 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
269 mtspr SPRN_SPRG1, r11 269 mtspr SPRN_SPRG_SCRATCH1, r11
270#ifdef CONFIG_403GCX 270#ifdef CONFIG_403GCX
271 stw r12, 0(r0) 271 stw r12, 0(r0)
272 stw r9, 4(r0) 272 stw r9, 4(r0)
@@ -275,12 +275,12 @@ label:
275 stw r11, 8(r0) 275 stw r11, 8(r0)
276 stw r12, 12(r0) 276 stw r12, 12(r0)
277#else 277#else
278 mtspr SPRN_SPRG4, r12 278 mtspr SPRN_SPRG_SCRATCH3, r12
279 mtspr SPRN_SPRG5, r9 279 mtspr SPRN_SPRG_SCRATCH4, r9
280 mfcr r11 280 mfcr r11
281 mfspr r12, SPRN_PID 281 mfspr r12, SPRN_PID
282 mtspr SPRN_SPRG7, r11 282 mtspr SPRN_SPRG_SCRATCH6, r11
283 mtspr SPRN_SPRG6, r12 283 mtspr SPRN_SPRG_SCRATCH5, r12
284#endif 284#endif
285 285
286 /* First, check if it was a zone fault (which means a user 286 /* First, check if it was a zone fault (which means a user
@@ -308,7 +308,7 @@ label:
308 /* Get the PGD for the current thread. 308 /* Get the PGD for the current thread.
309 */ 309 */
3103: 3103:
311 mfspr r11,SPRN_SPRG3 311 mfspr r11,SPRN_SPRG_THREAD
312 lwz r11,PGDIR(r11) 312 lwz r11,PGDIR(r11)
3134: 3134:
314 tophys(r11, r11) 314 tophys(r11, r11)
@@ -355,15 +355,15 @@ label:
355 lwz r9, 4(r0) 355 lwz r9, 4(r0)
356 lwz r12, 0(r0) 356 lwz r12, 0(r0)
357#else 357#else
358 mfspr r12, SPRN_SPRG6 358 mfspr r12, SPRN_SPRG_SCRATCH5
359 mfspr r11, SPRN_SPRG7 359 mfspr r11, SPRN_SPRG_SCRATCH6
360 mtspr SPRN_PID, r12 360 mtspr SPRN_PID, r12
361 mtcr r11 361 mtcr r11
362 mfspr r9, SPRN_SPRG5 362 mfspr r9, SPRN_SPRG_SCRATCH4
363 mfspr r12, SPRN_SPRG4 363 mfspr r12, SPRN_SPRG_SCRATCH3
364#endif 364#endif
365 mfspr r11, SPRN_SPRG1 365 mfspr r11, SPRN_SPRG_SCRATCH1
366 mfspr r10, SPRN_SPRG0 366 mfspr r10, SPRN_SPRG_SCRATCH0
367 PPC405_ERR77_SYNC 367 PPC405_ERR77_SYNC
368 rfi /* Should sync shadow TLBs */ 368 rfi /* Should sync shadow TLBs */
369 b . /* prevent prefetch past rfi */ 369 b . /* prevent prefetch past rfi */
@@ -380,15 +380,15 @@ label:
380 lwz r9, 4(r0) 380 lwz r9, 4(r0)
381 lwz r12, 0(r0) 381 lwz r12, 0(r0)
382#else 382#else
383 mfspr r12, SPRN_SPRG6 383 mfspr r12, SPRN_SPRG_SCRATCH5
384 mfspr r11, SPRN_SPRG7 384 mfspr r11, SPRN_SPRG_SCRATCH6
385 mtspr SPRN_PID, r12 385 mtspr SPRN_PID, r12
386 mtcr r11 386 mtcr r11
387 mfspr r9, SPRN_SPRG5 387 mfspr r9, SPRN_SPRG_SCRATCH4
388 mfspr r12, SPRN_SPRG4 388 mfspr r12, SPRN_SPRG_SCRATCH3
389#endif 389#endif
390 mfspr r11, SPRN_SPRG1 390 mfspr r11, SPRN_SPRG_SCRATCH1
391 mfspr r10, SPRN_SPRG0 391 mfspr r10, SPRN_SPRG_SCRATCH0
392 b DataAccess 392 b DataAccess
393 393
394/* 394/*
@@ -466,8 +466,8 @@ label:
466 * load TLB entries from the page table if they exist. 466 * load TLB entries from the page table if they exist.
467 */ 467 */
468 START_EXCEPTION(0x1100, DTLBMiss) 468 START_EXCEPTION(0x1100, DTLBMiss)
469 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 469 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
470 mtspr SPRN_SPRG1, r11 470 mtspr SPRN_SPRG_SCRATCH1, r11
471#ifdef CONFIG_403GCX 471#ifdef CONFIG_403GCX
472 stw r12, 0(r0) 472 stw r12, 0(r0)
473 stw r9, 4(r0) 473 stw r9, 4(r0)
@@ -476,12 +476,12 @@ label:
476 stw r11, 8(r0) 476 stw r11, 8(r0)
477 stw r12, 12(r0) 477 stw r12, 12(r0)
478#else 478#else
479 mtspr SPRN_SPRG4, r12 479 mtspr SPRN_SPRG_SCRATCH3, r12
480 mtspr SPRN_SPRG5, r9 480 mtspr SPRN_SPRG_SCRATCH4, r9
481 mfcr r11 481 mfcr r11
482 mfspr r12, SPRN_PID 482 mfspr r12, SPRN_PID
483 mtspr SPRN_SPRG7, r11 483 mtspr SPRN_SPRG_SCRATCH6, r11
484 mtspr SPRN_SPRG6, r12 484 mtspr SPRN_SPRG_SCRATCH5, r12
485#endif 485#endif
486 mfspr r10, SPRN_DEAR /* Get faulting address */ 486 mfspr r10, SPRN_DEAR /* Get faulting address */
487 487
@@ -500,7 +500,7 @@ label:
500 /* Get the PGD for the current thread. 500 /* Get the PGD for the current thread.
501 */ 501 */
5023: 5023:
503 mfspr r11,SPRN_SPRG3 503 mfspr r11,SPRN_SPRG_THREAD
504 lwz r11,PGDIR(r11) 504 lwz r11,PGDIR(r11)
5054: 5054:
506 tophys(r11, r11) 506 tophys(r11, r11)
@@ -550,15 +550,15 @@ label:
550 lwz r9, 4(r0) 550 lwz r9, 4(r0)
551 lwz r12, 0(r0) 551 lwz r12, 0(r0)
552#else 552#else
553 mfspr r12, SPRN_SPRG6 553 mfspr r12, SPRN_SPRG_SCRATCH5
554 mfspr r11, SPRN_SPRG7 554 mfspr r11, SPRN_SPRG_SCRATCH6
555 mtspr SPRN_PID, r12 555 mtspr SPRN_PID, r12
556 mtcr r11 556 mtcr r11
557 mfspr r9, SPRN_SPRG5 557 mfspr r9, SPRN_SPRG_SCRATCH4
558 mfspr r12, SPRN_SPRG4 558 mfspr r12, SPRN_SPRG_SCRATCH3
559#endif 559#endif
560 mfspr r11, SPRN_SPRG1 560 mfspr r11, SPRN_SPRG_SCRATCH1
561 mfspr r10, SPRN_SPRG0 561 mfspr r10, SPRN_SPRG_SCRATCH0
562 b DataAccess 562 b DataAccess
563 563
564/* 0x1200 - Instruction TLB Miss Exception 564/* 0x1200 - Instruction TLB Miss Exception
@@ -566,8 +566,8 @@ label:
566 * registers and bailout to a different point. 566 * registers and bailout to a different point.
567 */ 567 */
568 START_EXCEPTION(0x1200, ITLBMiss) 568 START_EXCEPTION(0x1200, ITLBMiss)
569 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 569 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
570 mtspr SPRN_SPRG1, r11 570 mtspr SPRN_SPRG_SCRATCH1, r11
571#ifdef CONFIG_403GCX 571#ifdef CONFIG_403GCX
572 stw r12, 0(r0) 572 stw r12, 0(r0)
573 stw r9, 4(r0) 573 stw r9, 4(r0)
@@ -576,12 +576,12 @@ label:
576 stw r11, 8(r0) 576 stw r11, 8(r0)
577 stw r12, 12(r0) 577 stw r12, 12(r0)
578#else 578#else
579 mtspr SPRN_SPRG4, r12 579 mtspr SPRN_SPRG_SCRATCH3, r12
580 mtspr SPRN_SPRG5, r9 580 mtspr SPRN_SPRG_SCRATCH4, r9
581 mfcr r11 581 mfcr r11
582 mfspr r12, SPRN_PID 582 mfspr r12, SPRN_PID
583 mtspr SPRN_SPRG7, r11 583 mtspr SPRN_SPRG_SCRATCH6, r11
584 mtspr SPRN_SPRG6, r12 584 mtspr SPRN_SPRG_SCRATCH5, r12
585#endif 585#endif
586 mfspr r10, SPRN_SRR0 /* Get faulting address */ 586 mfspr r10, SPRN_SRR0 /* Get faulting address */
587 587
@@ -600,7 +600,7 @@ label:
600 /* Get the PGD for the current thread. 600 /* Get the PGD for the current thread.
601 */ 601 */
6023: 6023:
603 mfspr r11,SPRN_SPRG3 603 mfspr r11,SPRN_SPRG_THREAD
604 lwz r11,PGDIR(r11) 604 lwz r11,PGDIR(r11)
6054: 6054:
606 tophys(r11, r11) 606 tophys(r11, r11)
@@ -650,15 +650,15 @@ label:
650 lwz r9, 4(r0) 650 lwz r9, 4(r0)
651 lwz r12, 0(r0) 651 lwz r12, 0(r0)
652#else 652#else
653 mfspr r12, SPRN_SPRG6 653 mfspr r12, SPRN_SPRG_SCRATCH5
654 mfspr r11, SPRN_SPRG7 654 mfspr r11, SPRN_SPRG_SCRATCH6
655 mtspr SPRN_PID, r12 655 mtspr SPRN_PID, r12
656 mtcr r11 656 mtcr r11
657 mfspr r9, SPRN_SPRG5 657 mfspr r9, SPRN_SPRG_SCRATCH4
658 mfspr r12, SPRN_SPRG4 658 mfspr r12, SPRN_SPRG_SCRATCH3
659#endif 659#endif
660 mfspr r11, SPRN_SPRG1 660 mfspr r11, SPRN_SPRG_SCRATCH1
661 mfspr r10, SPRN_SPRG0 661 mfspr r10, SPRN_SPRG_SCRATCH0
662 b InstructionAccess 662 b InstructionAccess
663 663
664 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) 664 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
@@ -803,15 +803,15 @@ finish_tlb_load:
803 lwz r9, 4(r0) 803 lwz r9, 4(r0)
804 lwz r12, 0(r0) 804 lwz r12, 0(r0)
805#else 805#else
806 mfspr r12, SPRN_SPRG6 806 mfspr r12, SPRN_SPRG_SCRATCH5
807 mfspr r11, SPRN_SPRG7 807 mfspr r11, SPRN_SPRG_SCRATCH6
808 mtspr SPRN_PID, r12 808 mtspr SPRN_PID, r12
809 mtcr r11 809 mtcr r11
810 mfspr r9, SPRN_SPRG5 810 mfspr r9, SPRN_SPRG_SCRATCH4
811 mfspr r12, SPRN_SPRG4 811 mfspr r12, SPRN_SPRG_SCRATCH3
812#endif 812#endif
813 mfspr r11, SPRN_SPRG1 813 mfspr r11, SPRN_SPRG_SCRATCH1
814 mfspr r10, SPRN_SPRG0 814 mfspr r10, SPRN_SPRG_SCRATCH0
815 PPC405_ERR77_SYNC 815 PPC405_ERR77_SYNC
816 rfi /* Should sync shadow TLBs */ 816 rfi /* Should sync shadow TLBs */
817 b . /* prevent prefetch past rfi */ 817 b . /* prevent prefetch past rfi */
@@ -835,7 +835,7 @@ start_here:
835 /* ptr to phys current thread */ 835 /* ptr to phys current thread */
836 tophys(r4,r2) 836 tophys(r4,r2)
837 addi r4,r4,THREAD /* init task's THREAD */ 837 addi r4,r4,THREAD /* init task's THREAD */
838 mtspr SPRN_SPRG3,r4 838 mtspr SPRN_SPRG_THREAD,r4
839 839
840 /* stack */ 840 /* stack */
841 lis r1,init_thread_union@ha 841 lis r1,init_thread_union@ha
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 18d8a1677c4d..656cfb2d6666 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -239,7 +239,7 @@ skpinv: addi r4,r4,1 /* Increment */
239 239
240 /* ptr to current thread */ 240 /* ptr to current thread */
241 addi r4,r2,THREAD /* init task's THREAD */ 241 addi r4,r2,THREAD /* init task's THREAD */
242 mtspr SPRN_SPRG3,r4 242 mtspr SPRN_SPRG_THREAD,r4
243 243
244 /* stack */ 244 /* stack */
245 lis r1,init_thread_union@h 245 lis r1,init_thread_union@h
@@ -350,12 +350,12 @@ interrupt_base:
350 350
351 /* Data TLB Error Interrupt */ 351 /* Data TLB Error Interrupt */
352 START_EXCEPTION(DataTLBError) 352 START_EXCEPTION(DataTLBError)
353 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 353 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
354 mtspr SPRN_SPRG1, r11 354 mtspr SPRN_SPRG_WSCRATCH1, r11
355 mtspr SPRN_SPRG4W, r12 355 mtspr SPRN_SPRG_WSCRATCH2, r12
356 mtspr SPRN_SPRG5W, r13 356 mtspr SPRN_SPRG_WSCRATCH3, r13
357 mfcr r11 357 mfcr r11
358 mtspr SPRN_SPRG7W, r11 358 mtspr SPRN_SPRG_WSCRATCH4, r11
359 mfspr r10, SPRN_DEAR /* Get faulting address */ 359 mfspr r10, SPRN_DEAR /* Get faulting address */
360 360
361 /* If we are faulting a kernel address, we have to use the 361 /* If we are faulting a kernel address, we have to use the
@@ -374,7 +374,7 @@ interrupt_base:
374 374
375 /* Get the PGD for the current thread */ 375 /* Get the PGD for the current thread */
3763: 3763:
377 mfspr r11,SPRN_SPRG3 377 mfspr r11,SPRN_SPRG_THREAD
378 lwz r11,PGDIR(r11) 378 lwz r11,PGDIR(r11)
379 379
380 /* Load PID into MMUCR TID */ 380 /* Load PID into MMUCR TID */
@@ -446,12 +446,12 @@ tlb_44x_patch_hwater_D:
446 /* The bailout. Restore registers to pre-exception conditions 446 /* The bailout. Restore registers to pre-exception conditions
447 * and call the heavyweights to help us out. 447 * and call the heavyweights to help us out.
448 */ 448 */
449 mfspr r11, SPRN_SPRG7R 449 mfspr r11, SPRN_SPRG_RSCRATCH4
450 mtcr r11 450 mtcr r11
451 mfspr r13, SPRN_SPRG5R 451 mfspr r13, SPRN_SPRG_RSCRATCH3
452 mfspr r12, SPRN_SPRG4R 452 mfspr r12, SPRN_SPRG_RSCRATCH2
453 mfspr r11, SPRN_SPRG1 453 mfspr r11, SPRN_SPRG_RSCRATCH1
454 mfspr r10, SPRN_SPRG0 454 mfspr r10, SPRN_SPRG_RSCRATCH0
455 b DataStorage 455 b DataStorage
456 456
457 /* Instruction TLB Error Interrupt */ 457 /* Instruction TLB Error Interrupt */
@@ -461,12 +461,12 @@ tlb_44x_patch_hwater_D:
461 * to a different point. 461 * to a different point.
462 */ 462 */
463 START_EXCEPTION(InstructionTLBError) 463 START_EXCEPTION(InstructionTLBError)
464 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 464 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
465 mtspr SPRN_SPRG1, r11 465 mtspr SPRN_SPRG_WSCRATCH1, r11
466 mtspr SPRN_SPRG4W, r12 466 mtspr SPRN_SPRG_WSCRATCH2, r12
467 mtspr SPRN_SPRG5W, r13 467 mtspr SPRN_SPRG_WSCRATCH3, r13
468 mfcr r11 468 mfcr r11
469 mtspr SPRN_SPRG7W, r11 469 mtspr SPRN_SPRG_WSCRATCH4, r11
470 mfspr r10, SPRN_SRR0 /* Get faulting address */ 470 mfspr r10, SPRN_SRR0 /* Get faulting address */
471 471
472 /* If we are faulting a kernel address, we have to use the 472 /* If we are faulting a kernel address, we have to use the
@@ -485,7 +485,7 @@ tlb_44x_patch_hwater_D:
485 485
486 /* Get the PGD for the current thread */ 486 /* Get the PGD for the current thread */
4873: 4873:
488 mfspr r11,SPRN_SPRG3 488 mfspr r11,SPRN_SPRG_THREAD
489 lwz r11,PGDIR(r11) 489 lwz r11,PGDIR(r11)
490 490
491 /* Load PID into MMUCR TID */ 491 /* Load PID into MMUCR TID */
@@ -542,12 +542,12 @@ tlb_44x_patch_hwater_I:
542 /* The bailout. Restore registers to pre-exception conditions 542 /* The bailout. Restore registers to pre-exception conditions
543 * and call the heavyweights to help us out. 543 * and call the heavyweights to help us out.
544 */ 544 */
545 mfspr r11, SPRN_SPRG7R 545 mfspr r11, SPRN_SPRG_RSCRATCH4
546 mtcr r11 546 mtcr r11
547 mfspr r13, SPRN_SPRG5R 547 mfspr r13, SPRN_SPRG_RSCRATCH3
548 mfspr r12, SPRN_SPRG4R 548 mfspr r12, SPRN_SPRG_RSCRATCH2
549 mfspr r11, SPRN_SPRG1 549 mfspr r11, SPRN_SPRG_RSCRATCH1
550 mfspr r10, SPRN_SPRG0 550 mfspr r10, SPRN_SPRG_RSCRATCH0
551 b InstructionStorage 551 b InstructionStorage
552 552
553 /* Debug Interrupt */ 553 /* Debug Interrupt */
@@ -593,12 +593,12 @@ finish_tlb_load:
593 593
594 /* Done...restore registers and get out of here. 594 /* Done...restore registers and get out of here.
595 */ 595 */
596 mfspr r11, SPRN_SPRG7R 596 mfspr r11, SPRN_SPRG_RSCRATCH4
597 mtcr r11 597 mtcr r11
598 mfspr r13, SPRN_SPRG5R 598 mfspr r13, SPRN_SPRG_RSCRATCH3
599 mfspr r12, SPRN_SPRG4R 599 mfspr r12, SPRN_SPRG_RSCRATCH2
600 mfspr r11, SPRN_SPRG1 600 mfspr r11, SPRN_SPRG_RSCRATCH1
601 mfspr r10, SPRN_SPRG0 601 mfspr r10, SPRN_SPRG_RSCRATCH0
602 rfi /* Force context change */ 602 rfi /* Force context change */
603 603
604/* 604/*
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 9196ef36d433..0552f01041ab 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -195,7 +195,7 @@ _GLOBAL(generic_secondary_smp_init)
195 mr r3,r24 /* not found, copy phys to r3 */ 195 mr r3,r24 /* not found, copy phys to r3 */
196 b .kexec_wait /* next kernel might do better */ 196 b .kexec_wait /* next kernel might do better */
197 197
1982: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1982: mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG */
199 /* From now on, r24 is expected to be logical cpuid */ 199 /* From now on, r24 is expected to be logical cpuid */
200 mr r24,r5 200 mr r24,r5
2013: HMT_LOW 2013: HMT_LOW
@@ -484,7 +484,7 @@ _GLOBAL(pmac_secondary_start)
484 LOAD_REG_ADDR(r4,paca) /* Get base vaddr of paca array */ 484 LOAD_REG_ADDR(r4,paca) /* Get base vaddr of paca array */
485 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 485 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
486 add r13,r13,r4 /* for this processor. */ 486 add r13,r13,r4 /* for this processor. */
487 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 487 mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/
488 488
489 /* Create a temp kernel stack for use before relocation is on. */ 489 /* Create a temp kernel stack for use before relocation is on. */
490 ld r1,PACAEMERGSP(r13) 490 ld r1,PACAEMERGSP(r13)
@@ -502,10 +502,10 @@ _GLOBAL(pmac_secondary_start)
502 * 1. Processor number 502 * 1. Processor number
503 * 2. Segment table pointer (virtual address) 503 * 2. Segment table pointer (virtual address)
504 * On entry the following are set: 504 * On entry the following are set:
505 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 505 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
506 * r24 = cpu# (in Linux terms) 506 * r24 = cpu# (in Linux terms)
507 * r13 = paca virtual address 507 * r13 = paca virtual address
508 * SPRG3 = paca virtual address 508 * SPRG_PACA = paca virtual address
509 */ 509 */
510 .globl __secondary_start 510 .globl __secondary_start
511__secondary_start: 511__secondary_start:
@@ -641,7 +641,7 @@ _INIT_STATIC(start_here_multiplatform)
641 641
642 /* Restore parameters passed from prom_init/kexec */ 642 /* Restore parameters passed from prom_init/kexec */
643 mr r3,r31 643 mr r3,r31
644 bl .early_setup /* also sets r13 and SPRG3 */ 644 bl .early_setup /* also sets r13 and SPRG_PACA */
645 645
646 LOAD_REG_ADDR(r3, .start_here_common) 646 LOAD_REG_ADDR(r3, .start_here_common)
647 ld r4,PACAKMSR(r13) 647 ld r4,PACAKMSR(r13)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 52ff8c53b93c..6ded19d01891 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -110,8 +110,8 @@ turn_on_mmu:
110 * task's thread_struct. 110 * task's thread_struct.
111 */ 111 */
112#define EXCEPTION_PROLOG \ 112#define EXCEPTION_PROLOG \
113 mtspr SPRN_SPRG0,r10; \ 113 mtspr SPRN_SPRG_SCRATCH0,r10; \
114 mtspr SPRN_SPRG1,r11; \ 114 mtspr SPRN_SPRG_SCRATCH1,r11; \
115 mfcr r10; \ 115 mfcr r10; \
116 EXCEPTION_PROLOG_1; \ 116 EXCEPTION_PROLOG_1; \
117 EXCEPTION_PROLOG_2 117 EXCEPTION_PROLOG_2
@@ -121,7 +121,7 @@ turn_on_mmu:
121 andi. r11,r11,MSR_PR; \ 121 andi. r11,r11,MSR_PR; \
122 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 122 tophys(r11,r1); /* use tophys(r1) if kernel */ \
123 beq 1f; \ 123 beq 1f; \
124 mfspr r11,SPRN_SPRG3; \ 124 mfspr r11,SPRN_SPRG_THREAD; \
125 lwz r11,THREAD_INFO-THREAD(r11); \ 125 lwz r11,THREAD_INFO-THREAD(r11); \
126 addi r11,r11,THREAD_SIZE; \ 126 addi r11,r11,THREAD_SIZE; \
127 tophys(r11,r11); \ 127 tophys(r11,r11); \
@@ -133,9 +133,9 @@ turn_on_mmu:
133 stw r10,_CCR(r11); /* save registers */ \ 133 stw r10,_CCR(r11); /* save registers */ \
134 stw r12,GPR12(r11); \ 134 stw r12,GPR12(r11); \
135 stw r9,GPR9(r11); \ 135 stw r9,GPR9(r11); \
136 mfspr r10,SPRN_SPRG0; \ 136 mfspr r10,SPRN_SPRG_SCRATCH0; \
137 stw r10,GPR10(r11); \ 137 stw r10,GPR10(r11); \
138 mfspr r12,SPRN_SPRG1; \ 138 mfspr r12,SPRN_SPRG_SCRATCH1; \
139 stw r12,GPR11(r11); \ 139 stw r12,GPR11(r11); \
140 mflr r10; \ 140 mflr r10; \
141 stw r10,_LINK(r11); \ 141 stw r10,_LINK(r11); \
@@ -603,8 +603,9 @@ start_here:
603 /* ptr to phys current thread */ 603 /* ptr to phys current thread */
604 tophys(r4,r2) 604 tophys(r4,r2)
605 addi r4,r4,THREAD /* init task's THREAD */ 605 addi r4,r4,THREAD /* init task's THREAD */
606 mtspr SPRN_SPRG3,r4 606 mtspr SPRN_SPRG_THREAD,r4
607 li r3,0 607 li r3,0
608 /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */
608 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ 609 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
609 610
610 /* stack */ 611 /* stack */
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 5f9febc8d143..50504ae39cb7 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -20,14 +20,14 @@
20#endif 20#endif
21 21
22#define NORMAL_EXCEPTION_PROLOG \ 22#define NORMAL_EXCEPTION_PROLOG \
23 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ 23 mtspr SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\
24 mtspr SPRN_SPRG1,r11; \ 24 mtspr SPRN_SPRG_WSCRATCH1,r11; \
25 mtspr SPRN_SPRG4W,r1; \ 25 mtspr SPRN_SPRG_WSCRATCH2,r1; \
26 mfcr r10; /* save CR in r10 for now */\ 26 mfcr r10; /* save CR in r10 for now */\
27 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ 27 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
28 andi. r11,r11,MSR_PR; \ 28 andi. r11,r11,MSR_PR; \
29 beq 1f; \ 29 beq 1f; \
30 mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ 30 mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\
31 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ 31 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
32 ALLOC_STACK_FRAME(r1, THREAD_SIZE); \ 32 ALLOC_STACK_FRAME(r1, THREAD_SIZE); \
331: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ 331: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
@@ -35,13 +35,13 @@
35 stw r10,_CCR(r11); /* save various registers */\ 35 stw r10,_CCR(r11); /* save various registers */\
36 stw r12,GPR12(r11); \ 36 stw r12,GPR12(r11); \
37 stw r9,GPR9(r11); \ 37 stw r9,GPR9(r11); \
38 mfspr r10,SPRN_SPRG0; \ 38 mfspr r10,SPRN_SPRG_RSCRATCH0; \
39 stw r10,GPR10(r11); \ 39 stw r10,GPR10(r11); \
40 mfspr r12,SPRN_SPRG1; \ 40 mfspr r12,SPRN_SPRG_RSCRATCH1; \
41 stw r12,GPR11(r11); \ 41 stw r12,GPR11(r11); \
42 mflr r10; \ 42 mflr r10; \
43 stw r10,_LINK(r11); \ 43 stw r10,_LINK(r11); \
44 mfspr r10,SPRN_SPRG4R; \ 44 mfspr r10,SPRN_SPRG_RSCRATCH2; \
45 mfspr r12,SPRN_SRR0; \ 45 mfspr r12,SPRN_SRR0; \
46 stw r10,GPR1(r11); \ 46 stw r10,GPR1(r11); \
47 mfspr r9,SPRN_SRR1; \ 47 mfspr r9,SPRN_SRR1; \
@@ -69,21 +69,11 @@
69 * providing configurations that micro-optimize space usage. 69 * providing configurations that micro-optimize space usage.
70 */ 70 */
71 71
72/* CRIT_SPRG only used in critical exception handling */ 72#define MC_STACK_BASE mcheckirq_ctx
73#define CRIT_SPRG SPRN_SPRG2
74/* MCHECK_SPRG only used in machine check exception handling */
75#define MCHECK_SPRG SPRN_SPRG6W
76
77#define MCHECK_STACK_BASE mcheckirq_ctx
78#define CRIT_STACK_BASE critirq_ctx 73#define CRIT_STACK_BASE critirq_ctx
79 74
80/* only on e500mc/e200 */ 75/* only on e500mc/e200 */
81#define DEBUG_STACK_BASE dbgirq_ctx 76#define DBG_STACK_BASE dbgirq_ctx
82#ifdef CONFIG_E200
83#define DEBUG_SPRG SPRN_SPRG6W
84#else
85#define DEBUG_SPRG SPRN_SPRG9
86#endif
87 77
88#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 78#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
89 79
@@ -110,7 +100,7 @@
110 * critical/machine check exception stack at low physical addresses. 100 * critical/machine check exception stack at low physical addresses.
111 */ 101 */
112#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \ 102#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
113 mtspr exc_level##_SPRG,r8; \ 103 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
114 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 104 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
115 stw r9,GPR9(r8); /* save various registers */\ 105 stw r9,GPR9(r8); /* save various registers */\
116 mfcr r9; /* save CR in r9 for now */\ 106 mfcr r9; /* save CR in r9 for now */\
@@ -119,7 +109,7 @@
119 stw r9,_CCR(r8); /* save CR on stack */\ 109 stw r9,_CCR(r8); /* save CR on stack */\
120 mfspr r10,exc_level_srr1; /* check whether user or kernel */\ 110 mfspr r10,exc_level_srr1; /* check whether user or kernel */\
121 andi. r10,r10,MSR_PR; \ 111 andi. r10,r10,MSR_PR; \
122 mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ 112 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
123 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 113 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
124 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 114 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
125 beq 1f; \ 115 beq 1f; \
@@ -140,7 +130,7 @@
140 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \ 130 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \
141 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \ 131 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \
142 mr r11,r8; \ 132 mr r11,r8; \
1432: mfspr r8,exc_level##_SPRG; \ 1332: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
144 stw r12,GPR12(r11); /* save various registers */\ 134 stw r12,GPR12(r11); /* save various registers */\
145 mflr r10; \ 135 mflr r10; \
146 stw r10,_LINK(r11); \ 136 stw r10,_LINK(r11); \
@@ -161,9 +151,9 @@
161#define CRITICAL_EXCEPTION_PROLOG \ 151#define CRITICAL_EXCEPTION_PROLOG \
162 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1) 152 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
163#define DEBUG_EXCEPTION_PROLOG \ 153#define DEBUG_EXCEPTION_PROLOG \
164 EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1) 154 EXC_LEVEL_EXCEPTION_PROLOG(DBG, SPRN_DSRR0, SPRN_DSRR1)
165#define MCHECK_EXCEPTION_PROLOG \ 155#define MCHECK_EXCEPTION_PROLOG \
166 EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1) 156 EXC_LEVEL_EXCEPTION_PROLOG(MC, SPRN_MCSRR0, SPRN_MCSRR1)
167 157
168/* 158/*
169 * Exception vectors. 159 * Exception vectors.
@@ -282,13 +272,13 @@ label:
282 mtspr SPRN_DSRR1,r9; \ 272 mtspr SPRN_DSRR1,r9; \
283 lwz r9,GPR9(r11); \ 273 lwz r9,GPR9(r11); \
284 lwz r12,GPR12(r11); \ 274 lwz r12,GPR12(r11); \
285 mtspr DEBUG_SPRG,r8; \ 275 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
286 BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \ 276 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
287 lwz r10,GPR10(r8); \ 277 lwz r10,GPR10(r8); \
288 lwz r11,GPR11(r8); \ 278 lwz r11,GPR11(r8); \
289 mfspr r8,DEBUG_SPRG; \ 279 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
290 \ 280 \
291 PPC_RFDI; \ 281 PPC_RFDI; \
292 b .; \ 282 b .; \
293 \ 283 \
294 /* continue normal handling for a debug exception... */ \ 284 /* continue normal handling for a debug exception... */ \
@@ -335,11 +325,11 @@ label:
335 mtspr SPRN_CSRR1,r9; \ 325 mtspr SPRN_CSRR1,r9; \
336 lwz r9,GPR9(r11); \ 326 lwz r9,GPR9(r11); \
337 lwz r12,GPR12(r11); \ 327 lwz r12,GPR12(r11); \
338 mtspr CRIT_SPRG,r8; \ 328 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
339 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 329 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
340 lwz r10,GPR10(r8); \ 330 lwz r10,GPR10(r8); \
341 lwz r11,GPR11(r8); \ 331 lwz r11,GPR11(r8); \
342 mfspr r8,CRIT_SPRG; \ 332 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
343 \ 333 \
344 rfci; \ 334 rfci; \
345 b .; \ 335 b .; \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 5bdcc06d294c..eca80482ae72 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -361,7 +361,7 @@ skpinv: addi r6,r6,1 /* Increment */
361 361
362 /* ptr to current thread */ 362 /* ptr to current thread */
363 addi r4,r2,THREAD /* init task's THREAD */ 363 addi r4,r2,THREAD /* init task's THREAD */
364 mtspr SPRN_SPRG3,r4 364 mtspr SPRN_SPRG_THREAD,r4
365 365
366 /* stack */ 366 /* stack */
367 lis r1,init_thread_union@h 367 lis r1,init_thread_union@h
@@ -532,12 +532,12 @@ interrupt_base:
532 532
533 /* Data TLB Error Interrupt */ 533 /* Data TLB Error Interrupt */
534 START_EXCEPTION(DataTLBError) 534 START_EXCEPTION(DataTLBError)
535 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 535 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
536 mtspr SPRN_SPRG1, r11 536 mtspr SPRN_SPRG_WSCRATCH1, r11
537 mtspr SPRN_SPRG4W, r12 537 mtspr SPRN_SPRG_WSCRATCH2, r12
538 mtspr SPRN_SPRG5W, r13 538 mtspr SPRN_SPRG_WSCRATCH3, r13
539 mfcr r11 539 mfcr r11
540 mtspr SPRN_SPRG7W, r11 540 mtspr SPRN_SPRG_WSCRATCH4, r11
541 mfspr r10, SPRN_DEAR /* Get faulting address */ 541 mfspr r10, SPRN_DEAR /* Get faulting address */
542 542
543 /* If we are faulting a kernel address, we have to use the 543 /* If we are faulting a kernel address, we have to use the
@@ -557,7 +557,7 @@ interrupt_base:
557 557
558 /* Get the PGD for the current thread */ 558 /* Get the PGD for the current thread */
5593: 5593:
560 mfspr r11,SPRN_SPRG3 560 mfspr r11,SPRN_SPRG_THREAD
561 lwz r11,PGDIR(r11) 561 lwz r11,PGDIR(r11)
562 562
5634: 5634:
@@ -598,12 +598,12 @@ interrupt_base:
598 /* The bailout. Restore registers to pre-exception conditions 598 /* The bailout. Restore registers to pre-exception conditions
599 * and call the heavyweights to help us out. 599 * and call the heavyweights to help us out.
600 */ 600 */
601 mfspr r11, SPRN_SPRG7R 601 mfspr r11, SPRN_SPRG_RSCRATCH4
602 mtcr r11 602 mtcr r11
603 mfspr r13, SPRN_SPRG5R 603 mfspr r13, SPRN_SPRG_RSCRATCH3
604 mfspr r12, SPRN_SPRG4R 604 mfspr r12, SPRN_SPRG_RSCRATCH2
605 mfspr r11, SPRN_SPRG1 605 mfspr r11, SPRN_SPRG_RSCRATCH1
606 mfspr r10, SPRN_SPRG0 606 mfspr r10, SPRN_SPRG_RSCRATCH0
607 b DataStorage 607 b DataStorage
608 608
609 /* Instruction TLB Error Interrupt */ 609 /* Instruction TLB Error Interrupt */
@@ -613,12 +613,12 @@ interrupt_base:
613 * to a different point. 613 * to a different point.
614 */ 614 */
615 START_EXCEPTION(InstructionTLBError) 615 START_EXCEPTION(InstructionTLBError)
616 mtspr SPRN_SPRG0, r10 /* Save some working registers */ 616 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
617 mtspr SPRN_SPRG1, r11 617 mtspr SPRN_SPRG_WSCRATCH1, r11
618 mtspr SPRN_SPRG4W, r12 618 mtspr SPRN_SPRG_WSCRATCH2, r12
619 mtspr SPRN_SPRG5W, r13 619 mtspr SPRN_SPRG_WSCRATCH3, r13
620 mfcr r11 620 mfcr r11
621 mtspr SPRN_SPRG7W, r11 621 mtspr SPRN_SPRG_WSCRATCH4, r11
622 mfspr r10, SPRN_SRR0 /* Get faulting address */ 622 mfspr r10, SPRN_SRR0 /* Get faulting address */
623 623
624 /* If we are faulting a kernel address, we have to use the 624 /* If we are faulting a kernel address, we have to use the
@@ -638,7 +638,7 @@ interrupt_base:
638 638
639 /* Get the PGD for the current thread */ 639 /* Get the PGD for the current thread */
6403: 6403:
641 mfspr r11,SPRN_SPRG3 641 mfspr r11,SPRN_SPRG_THREAD
642 lwz r11,PGDIR(r11) 642 lwz r11,PGDIR(r11)
643 643
6444: 6444:
@@ -666,12 +666,12 @@ interrupt_base:
666 /* The bailout. Restore registers to pre-exception conditions 666 /* The bailout. Restore registers to pre-exception conditions
667 * and call the heavyweights to help us out. 667 * and call the heavyweights to help us out.
668 */ 668 */
669 mfspr r11, SPRN_SPRG7R 669 mfspr r11, SPRN_SPRG_RSCRATCH4
670 mtcr r11 670 mtcr r11
671 mfspr r13, SPRN_SPRG5R 671 mfspr r13, SPRN_SPRG_RSCRATCH3
672 mfspr r12, SPRN_SPRG4R 672 mfspr r12, SPRN_SPRG_RSCRATCH2
673 mfspr r11, SPRN_SPRG1 673 mfspr r11, SPRN_SPRG_RSCRATCH1
674 mfspr r10, SPRN_SPRG0 674 mfspr r10, SPRN_SPRG_RSCRATCH0
675 b InstructionStorage 675 b InstructionStorage
676 676
677#ifdef CONFIG_SPE 677#ifdef CONFIG_SPE
@@ -790,12 +790,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
790 tlbwe 790 tlbwe
791 791
792 /* Done...restore registers and get out of here. */ 792 /* Done...restore registers and get out of here. */
793 mfspr r11, SPRN_SPRG7R 793 mfspr r11, SPRN_SPRG_RSCRATCH4
794 mtcr r11 794 mtcr r11
795 mfspr r13, SPRN_SPRG5R 795 mfspr r13, SPRN_SPRG_RSCRATCH3
796 mfspr r12, SPRN_SPRG4R 796 mfspr r12, SPRN_SPRG_RSCRATCH2
797 mfspr r11, SPRN_SPRG1 797 mfspr r11, SPRN_SPRG_RSCRATCH1
798 mfspr r10, SPRN_SPRG0 798 mfspr r10, SPRN_SPRG_RSCRATCH0
799 rfi /* Force context change */ 799 rfi /* Force context change */
800 800
801#ifdef CONFIG_SPE 801#ifdef CONFIG_SPE
@@ -839,7 +839,7 @@ load_up_spe:
839#endif /* !CONFIG_SMP */ 839#endif /* !CONFIG_SMP */
840 /* enable use of SPE after return */ 840 /* enable use of SPE after return */
841 oris r9,r9,MSR_SPE@h 841 oris r9,r9,MSR_SPE@h
842 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 842 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
843 li r4,1 843 li r4,1
844 li r10,THREAD_ACC 844 li r10,THREAD_ACC
845 stw r4,THREAD_USED_SPE(r5) 845 stw r4,THREAD_USED_SPE(r5)
@@ -1118,7 +1118,7 @@ __secondary_start:
1118 1118
1119 /* ptr to current thread */ 1119 /* ptr to current thread */
1120 addi r4,r2,THREAD /* address of our thread_struct */ 1120 addi r4,r2,THREAD /* address of our thread_struct */
1121 mtspr SPRN_SPRG3,r4 1121 mtspr SPRN_SPRG_THREAD,r4
1122 1122
1123 /* Setup the defaults for TLB entries */ 1123 /* Setup the defaults for TLB entries */
1124 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 1124 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 1f6816003ebe..91b89b8d63d8 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -142,11 +142,11 @@ early_param("smt-enabled", early_smt_enabled);
142#define check_smt_enabled() 142#define check_smt_enabled()
143#endif /* CONFIG_SMP */ 143#endif /* CONFIG_SMP */
144 144
145/* Put the paca pointer into r13 and SPRG3 */ 145/* Put the paca pointer into r13 and SPRG_PACA */
146void __init setup_paca(int cpu) 146void __init setup_paca(int cpu)
147{ 147{
148 local_paca = &paca[cpu]; 148 local_paca = &paca[cpu];
149 mtspr(SPRN_SPRG3, local_paca); 149 mtspr(SPRN_SPRG_PACA, local_paca);
150} 150}
151 151
152/* 152/*
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index ea4d64644d02..67b6916f0e94 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -65,7 +65,7 @@ _GLOBAL(load_up_altivec)
651: 651:
66 /* enable use of VMX after return */ 66 /* enable use of VMX after return */
67#ifdef CONFIG_PPC32 67#ifdef CONFIG_PPC32
68 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 68 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
69 oris r9,r9,MSR_VEC@h 69 oris r9,r9,MSR_VEC@h
70#else 70#else
71 ld r4,PACACURRENT(r13) 71 ld r4,PACACURRENT(r13)
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index d0c6f841bbd1..380a78cf484d 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -56,8 +56,8 @@
56.macro KVM_HANDLER ivor_nr 56.macro KVM_HANDLER ivor_nr
57_GLOBAL(kvmppc_handler_\ivor_nr) 57_GLOBAL(kvmppc_handler_\ivor_nr)
58 /* Get pointer to vcpu and record exit number. */ 58 /* Get pointer to vcpu and record exit number. */
59 mtspr SPRN_SPRG0, r4 59 mtspr SPRN_SPRG_WSCRATCH0, r4
60 mfspr r4, SPRN_SPRG1 60 mfspr r4, SPRN_SPRG_RVCPU
61 stw r5, VCPU_GPR(r5)(r4) 61 stw r5, VCPU_GPR(r5)(r4)
62 stw r6, VCPU_GPR(r6)(r4) 62 stw r6, VCPU_GPR(r6)(r4)
63 mfctr r5 63 mfctr r5
@@ -95,7 +95,7 @@ _GLOBAL(kvmppc_handler_len)
95 95
96 96
97/* Registers: 97/* Registers:
98 * SPRG0: guest r4 98 * SPRG_SCRATCH0: guest r4
99 * r4: vcpu pointer 99 * r4: vcpu pointer
100 * r5: KVM exit number 100 * r5: KVM exit number
101 */ 101 */
@@ -181,7 +181,7 @@ _GLOBAL(kvmppc_resume_host)
181 stw r3, VCPU_LR(r4) 181 stw r3, VCPU_LR(r4)
182 mfxer r3 182 mfxer r3
183 stw r3, VCPU_XER(r4) 183 stw r3, VCPU_XER(r4)
184 mfspr r3, SPRN_SPRG0 184 mfspr r3, SPRN_SPRG_RSCRATCH0
185 stw r3, VCPU_GPR(r4)(r4) 185 stw r3, VCPU_GPR(r4)(r4)
186 mfspr r3, SPRN_SRR0 186 mfspr r3, SPRN_SRR0
187 stw r3, VCPU_PC(r4) 187 stw r3, VCPU_PC(r4)
@@ -374,7 +374,7 @@ lightweight_exit:
374 mtspr SPRN_IVPR, r8 374 mtspr SPRN_IVPR, r8
375 375
376 /* Save vcpu pointer for the exception handlers. */ 376 /* Save vcpu pointer for the exception handlers. */
377 mtspr SPRN_SPRG1, r4 377 mtspr SPRN_SPRG_WVCPU, r4
378 378
379 /* Can't switch the stack pointer until after IVPR is switched, 379 /* Can't switch the stack pointer until after IVPR is switched,
380 * because host interrupt handlers would get confused. */ 380 * because host interrupt handlers would get confused. */
@@ -384,13 +384,13 @@ lightweight_exit:
384 /* Host interrupt handlers may have clobbered these guest-readable 384 /* Host interrupt handlers may have clobbered these guest-readable
385 * SPRGs, so we need to reload them here with the guest's values. */ 385 * SPRGs, so we need to reload them here with the guest's values. */
386 lwz r3, VCPU_SPRG4(r4) 386 lwz r3, VCPU_SPRG4(r4)
387 mtspr SPRN_SPRG4, r3 387 mtspr SPRN_SPRG4W, r3
388 lwz r3, VCPU_SPRG5(r4) 388 lwz r3, VCPU_SPRG5(r4)
389 mtspr SPRN_SPRG5, r3 389 mtspr SPRN_SPRG5W, r3
390 lwz r3, VCPU_SPRG6(r4) 390 lwz r3, VCPU_SPRG6(r4)
391 mtspr SPRN_SPRG6, r3 391 mtspr SPRN_SPRG6W, r3
392 lwz r3, VCPU_SPRG7(r4) 392 lwz r3, VCPU_SPRG7(r4)
393 mtspr SPRN_SPRG7, r3 393 mtspr SPRN_SPRG7W, r3
394 394
395#ifdef CONFIG_KVM_EXIT_TIMING 395#ifdef CONFIG_KVM_EXIT_TIMING
396 /* save enter time */ 396 /* save enter time */
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 14af8cedab70..b13d58932bf6 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -40,7 +40,7 @@ mmu_hash_lock:
40 * The address is in r4, and r3 contains an access flag: 40 * The address is in r4, and r3 contains an access flag:
41 * _PAGE_RW (0x400) if a write. 41 * _PAGE_RW (0x400) if a write.
42 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 42 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
43 * SPRG3 contains the physical address of the current task's thread. 43 * SPRG_THREAD contains the physical address of the current task's thread.
44 * 44 *
45 * Returns to the caller if the access is illegal or there is no 45 * Returns to the caller if the access is illegal or there is no
46 * mapping for the address. Otherwise it places an appropriate PTE 46 * mapping for the address. Otherwise it places an appropriate PTE
@@ -68,7 +68,7 @@ _GLOBAL(hash_page)
68 /* Get PTE (linux-style) and check access */ 68 /* Get PTE (linux-style) and check access */
69 lis r0,KERNELBASE@h /* check if kernel address */ 69 lis r0,KERNELBASE@h /* check if kernel address */
70 cmplw 0,r4,r0 70 cmplw 0,r4,r0
71 mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */ 71 mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
72 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 72 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
73 lwz r5,PGDIR(r8) /* virt page-table root */ 73 lwz r5,PGDIR(r8) /* virt page-table root */
74 blt+ 112f /* assume user more likely */ 74 blt+ 112f /* assume user more likely */
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 2f581521eb9b..2b8075979237 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -47,7 +47,7 @@ system_reset_iSeries:
47 LOAD_REG_ADDR(r13, paca) 47 LOAD_REG_ADDR(r13, paca)
48 mulli r0,r23,PACA_SIZE 48 mulli r0,r23,PACA_SIZE
49 add r13,r13,r0 49 add r13,r13,r0
50 mtspr SPRN_SPRG3,r13 /* Save it away for the future */ 50 mtspr SPRN_SPRG_PACA,r13 /* Save it away for the future */
51 mfmsr r24 51 mfmsr r24
52 ori r24,r24,MSR_RI 52 ori r24,r24,MSR_RI
53 mtmsrd r24 /* RI on */ 53 mtmsrd r24 /* RI on */
@@ -116,7 +116,7 @@ iSeries_secondary_smp_loop:
116#endif /* CONFIG_SMP */ 116#endif /* CONFIG_SMP */
117 li r0,-1 /* r0=-1 indicates a Hypervisor call */ 117 li r0,-1 /* r0=-1 indicates a Hypervisor call */
118 sc /* Invoke the hypervisor via a system call */ 118 sc /* Invoke the hypervisor via a system call */
119 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 119 mfspr r13,SPRN_SPRG_PACA /* Put r13 back ???? */
120 b 2b /* If SMP not configured, secondaries 120 b 2b /* If SMP not configured, secondaries
121 * loop forever */ 121 * loop forever */
122 122
@@ -126,9 +126,9 @@ iSeries_secondary_smp_loop:
126 126
127 .globl data_access_iSeries 127 .globl data_access_iSeries
128data_access_iSeries: 128data_access_iSeries:
129 mtspr SPRN_SPRG1,r13 129 mtspr SPRN_SPRG_SCRATCH0,r13
130BEGIN_FTR_SECTION 130BEGIN_FTR_SECTION
131 mtspr SPRN_SPRG2,r12 131 mtspr SPRN_SPRG_SCRATCH1,r12
132 mfspr r13,SPRN_DAR 132 mfspr r13,SPRN_DAR
133 mfspr r12,SPRN_DSISR 133 mfspr r12,SPRN_DSISR
134 srdi r13,r13,60 134 srdi r13,r13,60
@@ -137,7 +137,7 @@ BEGIN_FTR_SECTION
137 cmpwi r13,0x2c 137 cmpwi r13,0x2c
138 beq .do_stab_bolted_iSeries 138 beq .do_stab_bolted_iSeries
139 mtcrf 0x80,r12 139 mtcrf 0x80,r12
140 mfspr r12,SPRN_SPRG2 140 mfspr r12,SPRN_SPRG_SCRATCH1
141END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 141END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
142 EXCEPTION_PROLOG_1(PACA_EXGEN) 142 EXCEPTION_PROLOG_1(PACA_EXGEN)
143 EXCEPTION_PROLOG_ISERIES_1 143 EXCEPTION_PROLOG_ISERIES_1
@@ -145,15 +145,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
145 145
146.do_stab_bolted_iSeries: 146.do_stab_bolted_iSeries:
147 mtcrf 0x80,r12 147 mtcrf 0x80,r12
148 mfspr r12,SPRN_SPRG2 148 mfspr r12,SPRN_SPRG_SCRATCH1
149 EXCEPTION_PROLOG_1(PACA_EXSLB) 149 EXCEPTION_PROLOG_1(PACA_EXSLB)
150 EXCEPTION_PROLOG_ISERIES_1 150 EXCEPTION_PROLOG_ISERIES_1
151 b .do_stab_bolted 151 b .do_stab_bolted
152 152
153 .globl data_access_slb_iSeries 153 .globl data_access_slb_iSeries
154data_access_slb_iSeries: 154data_access_slb_iSeries:
155 mtspr SPRN_SPRG1,r13 /* save r13 */ 155 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
156 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 156 mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
157 std r3,PACA_EXSLB+EX_R3(r13) 157 std r3,PACA_EXSLB+EX_R3(r13)
158 mfspr r3,SPRN_DAR 158 mfspr r3,SPRN_DAR
159 std r9,PACA_EXSLB+EX_R9(r13) 159 std r9,PACA_EXSLB+EX_R9(r13)
@@ -165,7 +165,7 @@ data_access_slb_iSeries:
165 std r10,PACA_EXSLB+EX_R10(r13) 165 std r10,PACA_EXSLB+EX_R10(r13)
166 std r11,PACA_EXSLB+EX_R11(r13) 166 std r11,PACA_EXSLB+EX_R11(r13)
167 std r12,PACA_EXSLB+EX_R12(r13) 167 std r12,PACA_EXSLB+EX_R12(r13)
168 mfspr r10,SPRN_SPRG1 168 mfspr r10,SPRN_SPRG_SCRATCH0
169 std r10,PACA_EXSLB+EX_R13(r13) 169 std r10,PACA_EXSLB+EX_R13(r13)
170 ld r12,PACALPPACAPTR(r13) 170 ld r12,PACALPPACAPTR(r13)
171 ld r12,LPPACASRR1(r12) 171 ld r12,LPPACASRR1(r12)
@@ -175,8 +175,8 @@ data_access_slb_iSeries:
175 175
176 .globl instruction_access_slb_iSeries 176 .globl instruction_access_slb_iSeries
177instruction_access_slb_iSeries: 177instruction_access_slb_iSeries:
178 mtspr SPRN_SPRG1,r13 /* save r13 */ 178 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
179 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 179 mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
180 std r3,PACA_EXSLB+EX_R3(r13) 180 std r3,PACA_EXSLB+EX_R3(r13)
181 ld r3,PACALPPACAPTR(r13) 181 ld r3,PACALPPACAPTR(r13)
182 ld r3,LPPACASRR0(r3) /* get SRR0 value */ 182 ld r3,LPPACASRR0(r3) /* get SRR0 value */
@@ -189,7 +189,7 @@ instruction_access_slb_iSeries:
189 std r10,PACA_EXSLB+EX_R10(r13) 189 std r10,PACA_EXSLB+EX_R10(r13)
190 std r11,PACA_EXSLB+EX_R11(r13) 190 std r11,PACA_EXSLB+EX_R11(r13)
191 std r12,PACA_EXSLB+EX_R12(r13) 191 std r12,PACA_EXSLB+EX_R12(r13)
192 mfspr r10,SPRN_SPRG1 192 mfspr r10,SPRN_SPRG_SCRATCH0
193 std r10,PACA_EXSLB+EX_R13(r13) 193 std r10,PACA_EXSLB+EX_R13(r13)
194 ld r12,PACALPPACAPTR(r13) 194 ld r12,PACALPPACAPTR(r13)
195 ld r12,LPPACASRR1(r12) 195 ld r12,LPPACASRR1(r12)
@@ -200,7 +200,7 @@ slb_miss_user_iseries:
200 std r10,PACA_EXGEN+EX_R10(r13) 200 std r10,PACA_EXGEN+EX_R10(r13)
201 std r11,PACA_EXGEN+EX_R11(r13) 201 std r11,PACA_EXGEN+EX_R11(r13)
202 std r12,PACA_EXGEN+EX_R12(r13) 202 std r12,PACA_EXGEN+EX_R12(r13)
203 mfspr r10,SPRG1 203 mfspr r10,SPRG_SCRATCH0
204 ld r11,PACA_EXSLB+EX_R9(r13) 204 ld r11,PACA_EXSLB+EX_R9(r13)
205 ld r12,PACA_EXSLB+EX_R3(r13) 205 ld r12,PACA_EXSLB+EX_R3(r13)
206 std r10,PACA_EXGEN+EX_R13(r13) 206 std r10,PACA_EXGEN+EX_R13(r13)
@@ -221,7 +221,7 @@ slb_miss_user_iseries:
221 .globl system_call_iSeries 221 .globl system_call_iSeries
222system_call_iSeries: 222system_call_iSeries:
223 mr r9,r13 223 mr r9,r13
224 mfspr r13,SPRN_SPRG3 224 mfspr r13,SPRN_SPRG_PACA
225 EXCEPTION_PROLOG_ISERIES_1 225 EXCEPTION_PROLOG_ISERIES_1
226 b system_call_common 226 b system_call_common
227 227
diff --git a/arch/powerpc/platforms/iseries/exception.h b/arch/powerpc/platforms/iseries/exception.h
index e26eb86ac73d..bae3fba5ad8e 100644
--- a/arch/powerpc/platforms/iseries/exception.h
+++ b/arch/powerpc/platforms/iseries/exception.h
@@ -38,7 +38,7 @@
38 .globl label##_iSeries; \ 38 .globl label##_iSeries; \
39label##_iSeries: \ 39label##_iSeries: \
40 HMT_MEDIUM; \ 40 HMT_MEDIUM; \
41 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 41 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
42 EXCEPTION_PROLOG_1(area); \ 42 EXCEPTION_PROLOG_1(area); \
43 EXCEPTION_PROLOG_ISERIES_1; \ 43 EXCEPTION_PROLOG_ISERIES_1; \
44 b label##_common 44 b label##_common
@@ -47,7 +47,7 @@ label##_iSeries: \
47 .globl label##_iSeries; \ 47 .globl label##_iSeries; \
48label##_iSeries: \ 48label##_iSeries: \
49 HMT_MEDIUM; \ 49 HMT_MEDIUM; \
50 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 50 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
51 EXCEPTION_PROLOG_1(PACA_EXGEN); \ 51 EXCEPTION_PROLOG_1(PACA_EXGEN); \
52 lbz r10,PACASOFTIRQEN(r13); \ 52 lbz r10,PACASOFTIRQEN(r13); \
53 cmpwi 0,r10,0; \ 53 cmpwi 0,r10,0; \
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 12:59:45 -0500