diff options
author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2012-04-12 23:14:00 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2012-04-17 03:17:30 -0400 |
commit | eb0cdbe6b8cde26318666f86f8f5fb08d2336ce5 (patch) | |
tree | 5ca5954517857638f9e43b8d599e5e9af0e85660 /arch | |
parent | 33cd5cffd50a789f4e2f0f8bcd7ed9cf8a07da16 (diff) |
sh: sh4a: Change the specification method of IRQ to SCIx_IRQ_MUXED
Some SCIF devices specify the same IRQ. We can use SCIx_IRQ_MUXED for this.
And change use to evt2irq(), without specifying the value of IRQ directly.
This is correction to the SH4A series.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7343.c | 8 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7366.c | 2 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 6 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 6 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7724.c | 12 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7757.c | 6 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7763.c | 6 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7770.c | 20 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 12 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7786.c | 10 |
10 files changed, 44 insertions, 44 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 1b8848317e9c..476f4747df98 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |||
@@ -22,7 +22,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
23 | .scbrr_algo_id = SCBRR_ALGO_2, | 23 | .scbrr_algo_id = SCBRR_ALGO_2, |
24 | .type = PORT_SCIF, | 24 | .type = PORT_SCIF, |
25 | .irqs = { 80, 80, 80, 80 }, | 25 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), |
26 | }; | 26 | }; |
27 | 27 | ||
28 | static struct platform_device scif0_device = { | 28 | static struct platform_device scif0_device = { |
@@ -39,7 +39,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
39 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 39 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
40 | .scbrr_algo_id = SCBRR_ALGO_2, | 40 | .scbrr_algo_id = SCBRR_ALGO_2, |
41 | .type = PORT_SCIF, | 41 | .type = PORT_SCIF, |
42 | .irqs = { 81, 81, 81, 81 }, | 42 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), |
43 | }; | 43 | }; |
44 | 44 | ||
45 | static struct platform_device scif1_device = { | 45 | static struct platform_device scif1_device = { |
@@ -56,7 +56,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
56 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 56 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
57 | .scbrr_algo_id = SCBRR_ALGO_2, | 57 | .scbrr_algo_id = SCBRR_ALGO_2, |
58 | .type = PORT_SCIF, | 58 | .type = PORT_SCIF, |
59 | .irqs = { 82, 82, 82, 82 }, | 59 | .irq = SCIx_IRQ_MUXED(evt2irq(0xC40)), |
60 | }; | 60 | }; |
61 | 61 | ||
62 | static struct platform_device scif2_device = { | 62 | static struct platform_device scif2_device = { |
@@ -73,7 +73,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
74 | .scbrr_algo_id = SCBRR_ALGO_2, | 74 | .scbrr_algo_id = SCBRR_ALGO_2, |
75 | .type = PORT_SCIF, | 75 | .type = PORT_SCIF, |
76 | .irqs = { 83, 83, 83, 83 }, | 76 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC60)), |
77 | }; | 77 | }; |
78 | 78 | ||
79 | static struct platform_device scif3_device = { | 79 | static struct platform_device scif3_device = { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 87773869a2f3..20f9e366a814 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c | |||
@@ -25,7 +25,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
26 | .scbrr_algo_id = SCBRR_ALGO_2, | 26 | .scbrr_algo_id = SCBRR_ALGO_2, |
27 | .type = PORT_SCIF, | 27 | .type = PORT_SCIF, |
28 | .irqs = { 80, 80, 80, 80 }, | 28 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), |
29 | }; | 29 | }; |
30 | 30 | ||
31 | static struct platform_device scif0_device = { | 31 | static struct platform_device scif0_device = { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 8420d4bc8bfc..34b2ee5805d3 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
@@ -182,7 +182,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
183 | .scbrr_algo_id = SCBRR_ALGO_2, | 183 | .scbrr_algo_id = SCBRR_ALGO_2, |
184 | .type = PORT_SCIF, | 184 | .type = PORT_SCIF, |
185 | .irqs = { 80, 80, 80, 80 }, | 185 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), |
186 | .ops = &sh7722_sci_port_ops, | 186 | .ops = &sh7722_sci_port_ops, |
187 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 187 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
188 | }; | 188 | }; |
@@ -201,7 +201,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
202 | .scbrr_algo_id = SCBRR_ALGO_2, | 202 | .scbrr_algo_id = SCBRR_ALGO_2, |
203 | .type = PORT_SCIF, | 203 | .type = PORT_SCIF, |
204 | .irqs = { 81, 81, 81, 81 }, | 204 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), |
205 | .ops = &sh7722_sci_port_ops, | 205 | .ops = &sh7722_sci_port_ops, |
206 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 206 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
207 | }; | 207 | }; |
@@ -220,7 +220,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
220 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 220 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
221 | .scbrr_algo_id = SCBRR_ALGO_2, | 221 | .scbrr_algo_id = SCBRR_ALGO_2, |
222 | .type = PORT_SCIF, | 222 | .type = PORT_SCIF, |
223 | .irqs = { 82, 82, 82, 82 }, | 223 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), |
224 | .ops = &sh7722_sci_port_ops, | 224 | .ops = &sh7722_sci_port_ops, |
225 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 225 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
226 | }; | 226 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a188c9ea4393..3c1da7e3067d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -28,7 +28,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
29 | .scbrr_algo_id = SCBRR_ALGO_2, | 29 | .scbrr_algo_id = SCBRR_ALGO_2, |
30 | .type = PORT_SCIF, | 30 | .type = PORT_SCIF, |
31 | .irqs = { 80, 80, 80, 80 }, | 31 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), |
32 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 32 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
33 | }; | 33 | }; |
34 | 34 | ||
@@ -47,7 +47,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
47 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 47 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
48 | .scbrr_algo_id = SCBRR_ALGO_2, | 48 | .scbrr_algo_id = SCBRR_ALGO_2, |
49 | .type = PORT_SCIF, | 49 | .type = PORT_SCIF, |
50 | .irqs = { 81, 81, 81, 81 }, | 50 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), |
51 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 51 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
52 | }; | 52 | }; |
53 | 53 | ||
@@ -66,7 +66,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
67 | .scbrr_algo_id = SCBRR_ALGO_2, | 67 | .scbrr_algo_id = SCBRR_ALGO_2, |
68 | .type = PORT_SCIF, | 68 | .type = PORT_SCIF, |
69 | .irqs = { 82, 82, 82, 82 }, | 69 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), |
70 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 70 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
71 | }; | 71 | }; |
72 | 72 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 4c671cfe68aa..20623baeb1c6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c | |||
@@ -295,7 +295,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
295 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 295 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
296 | .scbrr_algo_id = SCBRR_ALGO_2, | 296 | .scbrr_algo_id = SCBRR_ALGO_2, |
297 | .type = PORT_SCIF, | 297 | .type = PORT_SCIF, |
298 | .irqs = { 80, 80, 80, 80 }, | 298 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)), |
299 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 299 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
300 | }; | 300 | }; |
301 | 301 | ||
@@ -314,7 +314,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
314 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 314 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
315 | .scbrr_algo_id = SCBRR_ALGO_2, | 315 | .scbrr_algo_id = SCBRR_ALGO_2, |
316 | .type = PORT_SCIF, | 316 | .type = PORT_SCIF, |
317 | .irqs = { 81, 81, 81, 81 }, | 317 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)), |
318 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 318 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
319 | }; | 319 | }; |
320 | 320 | ||
@@ -333,7 +333,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
333 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 333 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
334 | .scbrr_algo_id = SCBRR_ALGO_2, | 334 | .scbrr_algo_id = SCBRR_ALGO_2, |
335 | .type = PORT_SCIF, | 335 | .type = PORT_SCIF, |
336 | .irqs = { 82, 82, 82, 82 }, | 336 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)), |
337 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 337 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
338 | }; | 338 | }; |
339 | 339 | ||
@@ -352,7 +352,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
352 | .scscr = SCSCR_RE | SCSCR_TE, | 352 | .scscr = SCSCR_RE | SCSCR_TE, |
353 | .scbrr_algo_id = SCBRR_ALGO_3, | 353 | .scbrr_algo_id = SCBRR_ALGO_3, |
354 | .type = PORT_SCIFA, | 354 | .type = PORT_SCIFA, |
355 | .irqs = { 56, 56, 56, 56 }, | 355 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), |
356 | }; | 356 | }; |
357 | 357 | ||
358 | static struct platform_device scif3_device = { | 358 | static struct platform_device scif3_device = { |
@@ -370,7 +370,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
370 | .scscr = SCSCR_RE | SCSCR_TE, | 370 | .scscr = SCSCR_RE | SCSCR_TE, |
371 | .scbrr_algo_id = SCBRR_ALGO_3, | 371 | .scbrr_algo_id = SCBRR_ALGO_3, |
372 | .type = PORT_SCIFA, | 372 | .type = PORT_SCIFA, |
373 | .irqs = { 88, 88, 88, 88 }, | 373 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xD00)), |
374 | }; | 374 | }; |
375 | 375 | ||
376 | static struct platform_device scif4_device = { | 376 | static struct platform_device scif4_device = { |
@@ -388,7 +388,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
388 | .scscr = SCSCR_RE | SCSCR_TE, | 388 | .scscr = SCSCR_RE | SCSCR_TE, |
389 | .scbrr_algo_id = SCBRR_ALGO_3, | 389 | .scbrr_algo_id = SCBRR_ALGO_3, |
390 | .type = PORT_SCIFA, | 390 | .type = PORT_SCIFA, |
391 | .irqs = { 109, 109, 109, 109 }, | 391 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xFA0)), |
392 | }; | 392 | }; |
393 | 393 | ||
394 | static struct platform_device scif5_device = { | 394 | static struct platform_device scif5_device = { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index c8836cffa216..fe45e4cb183d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c | |||
@@ -28,7 +28,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
29 | .scbrr_algo_id = SCBRR_ALGO_2, | 29 | .scbrr_algo_id = SCBRR_ALGO_2, |
30 | .type = PORT_SCIF, | 30 | .type = PORT_SCIF, |
31 | .irqs = { 40, 40, 40, 40 }, | 31 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), |
32 | }; | 32 | }; |
33 | 33 | ||
34 | static struct platform_device scif2_device = { | 34 | static struct platform_device scif2_device = { |
@@ -45,7 +45,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
46 | .scbrr_algo_id = SCBRR_ALGO_2, | 46 | .scbrr_algo_id = SCBRR_ALGO_2, |
47 | .type = PORT_SCIF, | 47 | .type = PORT_SCIF, |
48 | .irqs = { 76, 76, 76, 76 }, | 48 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xB80)), |
49 | }; | 49 | }; |
50 | 50 | ||
51 | static struct platform_device scif3_device = { | 51 | static struct platform_device scif3_device = { |
@@ -62,7 +62,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
62 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 62 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
63 | .scbrr_algo_id = SCBRR_ALGO_2, | 63 | .scbrr_algo_id = SCBRR_ALGO_2, |
64 | .type = PORT_SCIF, | 64 | .type = PORT_SCIF, |
65 | .irqs = { 104, 104, 104, 104 }, | 65 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), |
66 | }; | 66 | }; |
67 | 67 | ||
68 | static struct platform_device scif4_device = { | 68 | static struct platform_device scif4_device = { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 00113515f233..197e4c9a4a01 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c | |||
@@ -22,7 +22,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
23 | .scbrr_algo_id = SCBRR_ALGO_2, | 23 | .scbrr_algo_id = SCBRR_ALGO_2, |
24 | .type = PORT_SCIF, | 24 | .type = PORT_SCIF, |
25 | .irqs = { 40, 40, 40, 40 }, | 25 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), |
26 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 26 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
27 | }; | 27 | }; |
28 | 28 | ||
@@ -40,7 +40,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
40 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 40 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
41 | .scbrr_algo_id = SCBRR_ALGO_2, | 41 | .scbrr_algo_id = SCBRR_ALGO_2, |
42 | .type = PORT_SCIF, | 42 | .type = PORT_SCIF, |
43 | .irqs = { 76, 76, 76, 76 }, | 43 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xB80)), |
44 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 44 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
45 | }; | 45 | }; |
46 | 46 | ||
@@ -58,7 +58,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
58 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 58 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
59 | .scbrr_algo_id = SCBRR_ALGO_2, | 59 | .scbrr_algo_id = SCBRR_ALGO_2, |
60 | .type = PORT_SCIF, | 60 | .type = PORT_SCIF, |
61 | .irqs = { 104, 104, 104, 104 }, | 61 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), |
62 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 62 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
63 | }; | 63 | }; |
64 | 64 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 2c6aa22cf5f6..46ea8703d18a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
@@ -20,7 +20,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
21 | .scbrr_algo_id = SCBRR_ALGO_2, | 21 | .scbrr_algo_id = SCBRR_ALGO_2, |
22 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
23 | .irqs = { 61, 61, 61, 61 }, | 23 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9A0)), |
24 | }; | 24 | }; |
25 | 25 | ||
26 | static struct platform_device scif0_device = { | 26 | static struct platform_device scif0_device = { |
@@ -37,7 +37,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
37 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 37 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
38 | .scbrr_algo_id = SCBRR_ALGO_2, | 38 | .scbrr_algo_id = SCBRR_ALGO_2, |
39 | .type = PORT_SCIF, | 39 | .type = PORT_SCIF, |
40 | .irqs = { 62, 62, 62, 62 }, | 40 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9C0)), |
41 | }; | 41 | }; |
42 | 42 | ||
43 | static struct platform_device scif1_device = { | 43 | static struct platform_device scif1_device = { |
@@ -54,7 +54,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
54 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 54 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
55 | .scbrr_algo_id = SCBRR_ALGO_2, | 55 | .scbrr_algo_id = SCBRR_ALGO_2, |
56 | .type = PORT_SCIF, | 56 | .type = PORT_SCIF, |
57 | .irqs = { 63, 63, 63, 63 }, | 57 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9E0)), |
58 | }; | 58 | }; |
59 | 59 | ||
60 | static struct platform_device scif2_device = { | 60 | static struct platform_device scif2_device = { |
@@ -71,7 +71,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
71 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 71 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
72 | .scbrr_algo_id = SCBRR_ALGO_2, | 72 | .scbrr_algo_id = SCBRR_ALGO_2, |
73 | .type = PORT_SCIF, | 73 | .type = PORT_SCIF, |
74 | .irqs = { 64, 64, 64, 64 }, | 74 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xA00)), |
75 | }; | 75 | }; |
76 | 76 | ||
77 | static struct platform_device scif3_device = { | 77 | static struct platform_device scif3_device = { |
@@ -88,7 +88,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
89 | .scbrr_algo_id = SCBRR_ALGO_2, | 89 | .scbrr_algo_id = SCBRR_ALGO_2, |
90 | .type = PORT_SCIF, | 90 | .type = PORT_SCIF, |
91 | .irqs = { 65, 65, 65, 65 }, | 91 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xA20)), |
92 | }; | 92 | }; |
93 | 93 | ||
94 | static struct platform_device scif4_device = { | 94 | static struct platform_device scif4_device = { |
@@ -105,7 +105,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
105 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 105 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
106 | .scbrr_algo_id = SCBRR_ALGO_2, | 106 | .scbrr_algo_id = SCBRR_ALGO_2, |
107 | .type = PORT_SCIF, | 107 | .type = PORT_SCIF, |
108 | .irqs = { 66, 66, 66, 66 }, | 108 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xA40)), |
109 | }; | 109 | }; |
110 | 110 | ||
111 | static struct platform_device scif5_device = { | 111 | static struct platform_device scif5_device = { |
@@ -122,7 +122,7 @@ static struct plat_sci_port scif6_platform_data = { | |||
122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
123 | .scbrr_algo_id = SCBRR_ALGO_2, | 123 | .scbrr_algo_id = SCBRR_ALGO_2, |
124 | .type = PORT_SCIF, | 124 | .type = PORT_SCIF, |
125 | .irqs = { 67, 67, 67, 67 }, | 125 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xA60)), |
126 | }; | 126 | }; |
127 | 127 | ||
128 | static struct platform_device scif6_device = { | 128 | static struct platform_device scif6_device = { |
@@ -139,7 +139,7 @@ static struct plat_sci_port scif7_platform_data = { | |||
139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
140 | .scbrr_algo_id = SCBRR_ALGO_2, | 140 | .scbrr_algo_id = SCBRR_ALGO_2, |
141 | .type = PORT_SCIF, | 141 | .type = PORT_SCIF, |
142 | .irqs = { 68, 68, 68, 68 }, | 142 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xA80)), |
143 | }; | 143 | }; |
144 | 144 | ||
145 | static struct platform_device scif7_device = { | 145 | static struct platform_device scif7_device = { |
@@ -156,7 +156,7 @@ static struct plat_sci_port scif8_platform_data = { | |||
156 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 156 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
157 | .scbrr_algo_id = SCBRR_ALGO_2, | 157 | .scbrr_algo_id = SCBRR_ALGO_2, |
158 | .type = PORT_SCIF, | 158 | .type = PORT_SCIF, |
159 | .irqs = { 69, 69, 69, 69 }, | 159 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xAA0)), |
160 | }; | 160 | }; |
161 | 161 | ||
162 | static struct platform_device scif8_device = { | 162 | static struct platform_device scif8_device = { |
@@ -173,7 +173,7 @@ static struct plat_sci_port scif9_platform_data = { | |||
173 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 173 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
174 | .scbrr_algo_id = SCBRR_ALGO_2, | 174 | .scbrr_algo_id = SCBRR_ALGO_2, |
175 | .type = PORT_SCIF, | 175 | .type = PORT_SCIF, |
176 | .irqs = { 70, 70, 70, 70 }, | 176 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xAC0)), |
177 | }; | 177 | }; |
178 | 178 | ||
179 | static struct platform_device scif9_device = { | 179 | static struct platform_device scif9_device = { |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 81588ef15a6c..304339fe7a24 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
@@ -24,7 +24,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
25 | .scbrr_algo_id = SCBRR_ALGO_1, | 25 | .scbrr_algo_id = SCBRR_ALGO_1, |
26 | .type = PORT_SCIF, | 26 | .type = PORT_SCIF, |
27 | .irqs = { 40, 40, 40, 40 }, | 27 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), |
28 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 28 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
29 | }; | 29 | }; |
30 | 30 | ||
@@ -42,7 +42,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
42 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 42 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
43 | .scbrr_algo_id = SCBRR_ALGO_1, | 43 | .scbrr_algo_id = SCBRR_ALGO_1, |
44 | .type = PORT_SCIF, | 44 | .type = PORT_SCIF, |
45 | .irqs = { 44, 44, 44, 44 }, | 45 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), |
46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
47 | }; | 47 | }; |
48 | 48 | ||
@@ -60,7 +60,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
61 | .scbrr_algo_id = SCBRR_ALGO_1, | 61 | .scbrr_algo_id = SCBRR_ALGO_1, |
62 | .type = PORT_SCIF, | 62 | .type = PORT_SCIF, |
63 | .irqs = { 60, 60, 60, 60 }, | 63 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)), |
64 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 64 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
65 | }; | 65 | }; |
66 | 66 | ||
@@ -78,7 +78,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
78 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 78 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
79 | .scbrr_algo_id = SCBRR_ALGO_1, | 79 | .scbrr_algo_id = SCBRR_ALGO_1, |
80 | .type = PORT_SCIF, | 80 | .type = PORT_SCIF, |
81 | .irqs = { 61, 61, 61, 61 }, | 81 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9A0)), |
82 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 82 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
83 | }; | 83 | }; |
84 | 84 | ||
@@ -96,7 +96,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
96 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 96 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
97 | .scbrr_algo_id = SCBRR_ALGO_1, | 97 | .scbrr_algo_id = SCBRR_ALGO_1, |
98 | .type = PORT_SCIF, | 98 | .type = PORT_SCIF, |
99 | .irqs = { 62, 62, 62, 62 }, | 99 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9C0)), |
100 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 100 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
101 | }; | 101 | }; |
102 | 102 | ||
@@ -114,7 +114,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
114 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 114 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
115 | .scbrr_algo_id = SCBRR_ALGO_1, | 115 | .scbrr_algo_id = SCBRR_ALGO_1, |
116 | .type = PORT_SCIF, | 116 | .type = PORT_SCIF, |
117 | .irqs = { 63, 63, 63, 63 }, | 117 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9E0)), |
118 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 118 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
119 | }; | 119 | }; |
120 | 120 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 599022d73b28..9befe2dcf45e 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c | |||
@@ -53,7 +53,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
54 | .scbrr_algo_id = SCBRR_ALGO_1, | 54 | .scbrr_algo_id = SCBRR_ALGO_1, |
55 | .type = PORT_SCIF, | 55 | .type = PORT_SCIF, |
56 | .irqs = { 44, 44, 44, 44 }, | 56 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), |
57 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 57 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
58 | }; | 58 | }; |
59 | 59 | ||
@@ -71,7 +71,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
71 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 71 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
72 | .scbrr_algo_id = SCBRR_ALGO_1, | 72 | .scbrr_algo_id = SCBRR_ALGO_1, |
73 | .type = PORT_SCIF, | 73 | .type = PORT_SCIF, |
74 | .irqs = { 50, 50, 50, 50 }, | 74 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)), |
75 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 75 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
76 | }; | 76 | }; |
77 | 77 | ||
@@ -89,7 +89,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
89 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 89 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
90 | .scbrr_algo_id = SCBRR_ALGO_1, | 90 | .scbrr_algo_id = SCBRR_ALGO_1, |
91 | .type = PORT_SCIF, | 91 | .type = PORT_SCIF, |
92 | .irqs = { 51, 51, 51, 51 }, | 92 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)), |
93 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 93 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
94 | }; | 94 | }; |
95 | 95 | ||
@@ -107,7 +107,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
107 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 107 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
108 | .scbrr_algo_id = SCBRR_ALGO_1, | 108 | .scbrr_algo_id = SCBRR_ALGO_1, |
109 | .type = PORT_SCIF, | 109 | .type = PORT_SCIF, |
110 | .irqs = { 52, 52, 52, 52 }, | 110 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), |
111 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 111 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
112 | }; | 112 | }; |
113 | 113 | ||
@@ -125,7 +125,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
125 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 125 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
126 | .scbrr_algo_id = SCBRR_ALGO_1, | 126 | .scbrr_algo_id = SCBRR_ALGO_1, |
127 | .type = PORT_SCIF, | 127 | .type = PORT_SCIF, |
128 | .irqs = { 53, 53, 53, 53 }, | 128 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8A0)), |
129 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 129 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
130 | }; | 130 | }; |
131 | 131 | ||