diff options
| author | Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> | 2014-11-12 03:55:57 -0500 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-11-18 19:22:12 -0500 |
| commit | dc3cf93d89c525dcaebf4460109196fd9752c706 (patch) | |
| tree | 8cacdc796273e649fd20ca671ec928a00b054620 /arch | |
| parent | 3e58a5424c8325df8b62f1de175dc95c7373bfe1 (diff) | |
ARM: shmobile: r8a7794: Add MMP and VSP1 clocks to device tree
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index b6f8f451e3b1..19c9de3f2a5a 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi | |||
| @@ -461,15 +461,19 @@ | |||
| 461 | mstp1_clks: mstp1_clks@e6150134 { | 461 | mstp1_clks: mstp1_clks@e6150134 { |
| 462 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | 462 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 463 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | 463 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| 464 | clocks = <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | 464 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
| 465 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; | 465 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, |
| 466 | <&zs_clk>, <&zs_clk>; | ||
| 466 | #clock-cells = <1>; | 467 | #clock-cells = <1>; |
| 467 | renesas,clock-indices = < | 468 | renesas,clock-indices = < |
| 468 | R8A7794_CLK_TMU1 R8A7794_CLK_3DG R8A7794_CLK_TMU3 | 469 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
| 469 | R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 | 470 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 |
| 471 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 | ||
| 472 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S | ||
| 470 | >; | 473 | >; |
| 471 | clock-output-names = | 474 | clock-output-names = |
| 472 | "tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0"; | 475 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
| 476 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; | ||
| 473 | }; | 477 | }; |
| 474 | mstp2_clks: mstp2_clks@e6150138 { | 478 | mstp2_clks: mstp2_clks@e6150138 { |
| 475 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | 479 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |