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authorArnd Bergmann <arnd@arndb.de>2012-03-04 15:55:46 -0500
committerArnd Bergmann <arnd@arndb.de>2012-03-04 15:57:06 -0500
commitc71656c018c8551eca45b2f873b239f0303d74cb (patch)
treebab4825a6ed993c98ac4967f2aa976536f58568a /arch
parentcb66bb1d6fab2d91960c20f256c6986d5afac1a1 (diff)
parente186ad74c0941f5caeda28bde76dab903b342c1c (diff)
Merge tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/soc
From: Olof Johansson <olof@lixom.net> SoC new development for tegra SoCs, mostly tegra30 core support. It also includes one stray bugfix that was misapplied (should have been in soc-drivers), but it went out to the stable branches before I noticed so I've left it in. * tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra: ARM: tegra: Demote EMC clock inconsistency BUG to WARN ARM: tegra: Avoid compiling cpuidle code when not configured ARM: tegra: cpuidle driver for tegra ARM: tegra: assembler code for LP3 ARM: tegra: definitions for flow controller ARM: tegra: initialize basic system clocks ARM: tegra: enable tegra30 clock framework ARM: tegra: implement basic tegra30 clock framework ARM: tegra: add support for new clock framework features ARM: tegra: add support for tegra30 interrupts Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c24
-rw-r--r--arch/arm/mach-tegra/clock.c22
-rw-r--r--arch/arm/mach-tegra/clock.h15
-rw-r--r--arch/arm/mach-tegra/common.c1
-rw-r--r--arch/arm/mach-tegra/cpuidle.c107
-rw-r--r--arch/arm/mach-tegra/flowctrl.h37
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h10
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h3
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h7
-rw-r--r--arch/arm/mach-tegra/irq.c20
-rw-r--r--arch/arm/mach-tegra/sleep.S91
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c30
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c3099
14 files changed, 3456 insertions, 13 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e120ff54f663..fc4ebe35f484 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,12 +7,15 @@ obj-y += clock.o
7obj-y += timer.o 7obj-y += timer.o
8obj-y += pinmux.o 8obj-y += pinmux.o
9obj-y += fuse.o 9obj-y += fuse.o
10obj-$(CONFIG_CPU_IDLE) += cpuidle.o
11obj-$(CONFIG_CPU_IDLE) += sleep.o
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 12obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
11obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
12obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
14obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o 16obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
16obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o 19obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
17obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 20obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
18obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o 21obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 3c197e2440b7..b4124b12a779 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -34,16 +34,38 @@
34#include <asm/hardware/gic.h> 34#include <asm/hardware/gic.h>
35 35
36#include "board.h" 36#include "board.h"
37#include "clock.h"
37 38
38static struct of_device_id tegra_dt_match_table[] __initdata = { 39static struct of_device_id tegra_dt_match_table[] __initdata = {
39 { .compatible = "simple-bus", }, 40 { .compatible = "simple-bus", },
40 {} 41 {}
41}; 42};
42 43
44struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
45 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
46 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
47 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
48 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
49 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
50 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
51 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
52 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
54 {}
55};
56
57static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
58 /* name parent rate enabled */
59 { "uartd", "pll_p", 408000000, true },
60 { NULL, NULL, 0, 0},
61};
62
43static void __init tegra30_dt_init(void) 63static void __init tegra30_dt_init(void)
44{ 64{
65 tegra_clk_init_from_table(tegra_dt_clk_init_table);
66
45 of_platform_populate(NULL, tegra_dt_match_table, 67 of_platform_populate(NULL, tegra_dt_match_table,
46 NULL, NULL); 68 tegra30_auxdata_lookup, NULL);
47} 69}
48 70
49static const char *tegra30_dt_board_compat[] = { 71static const char *tegra30_dt_board_compat[] = {
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 8337068a4abe..8dad8d18cb49 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -399,6 +399,28 @@ void tegra_periph_reset_assert(struct clk *c)
399} 399}
400EXPORT_SYMBOL(tegra_periph_reset_assert); 400EXPORT_SYMBOL(tegra_periph_reset_assert);
401 401
402/* Several extended clock configuration bits (e.g., clock routing, clock
403 * phase control) are included in PLL and peripheral clock source
404 * registers. */
405int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
406{
407 int ret = 0;
408 unsigned long flags;
409
410 spin_lock_irqsave(&c->spinlock, flags);
411
412 if (!c->ops || !c->ops->clk_cfg_ex) {
413 ret = -ENOSYS;
414 goto out;
415 }
416 ret = c->ops->clk_cfg_ex(c, p, setting);
417
418out:
419 spin_unlock_irqrestore(&c->spinlock, flags);
420
421 return ret;
422}
423
402#ifdef CONFIG_DEBUG_FS 424#ifdef CONFIG_DEBUG_FS
403 425
404static int __clk_lock_all_spinlocks(void) 426static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 5c44106616c5..bc300657deba 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -24,6 +24,8 @@
24#include <linux/list.h> 24#include <linux/list.h>
25#include <linux/spinlock.h> 25#include <linux/spinlock.h>
26 26
27#include <mach/clk.h>
28
27#define DIV_BUS (1 << 0) 29#define DIV_BUS (1 << 0)
28#define DIV_U71 (1 << 1) 30#define DIV_U71 (1 << 1)
29#define DIV_U71_FIXED (1 << 2) 31#define DIV_U71_FIXED (1 << 2)
@@ -39,7 +41,16 @@
39#define PERIPH_MANUAL_RESET (1 << 12) 41#define PERIPH_MANUAL_RESET (1 << 12)
40#define PLL_ALT_MISC_REG (1 << 13) 42#define PLL_ALT_MISC_REG (1 << 13)
41#define PLLU (1 << 14) 43#define PLLU (1 << 14)
44#define PLLX (1 << 15)
45#define MUX_PWM (1 << 16)
46#define MUX8 (1 << 17)
47#define DIV_U71_UART (1 << 18)
48#define MUX_CLK_OUT (1 << 19)
49#define PLLM (1 << 20)
50#define DIV_U71_INT (1 << 21)
51#define DIV_U71_IDLE (1 << 22)
42#define ENABLE_ON_INIT (1 << 28) 52#define ENABLE_ON_INIT (1 << 28)
53#define PERIPH_ON_APB (1 << 29)
43 54
44struct clk; 55struct clk;
45 56
@@ -65,6 +76,8 @@ struct clk_ops {
65 int (*set_rate)(struct clk *, unsigned long); 76 int (*set_rate)(struct clk *, unsigned long);
66 long (*round_rate)(struct clk *, unsigned long); 77 long (*round_rate)(struct clk *, unsigned long);
67 void (*reset)(struct clk *, bool); 78 void (*reset)(struct clk *, bool);
79 int (*clk_cfg_ex)(struct clk *,
80 enum tegra_clk_ex_param, u32);
68}; 81};
69 82
70enum clk_state { 83enum clk_state {
@@ -114,6 +127,7 @@ struct clk {
114 unsigned long vco_max; 127 unsigned long vco_max;
115 const struct clk_pll_freq_table *freq_table; 128 const struct clk_pll_freq_table *freq_table;
116 int lock_delay; 129 int lock_delay;
130 unsigned long fixed_rate;
117 } pll; 131 } pll;
118 struct { 132 struct {
119 u32 sel; 133 u32 sel;
@@ -146,6 +160,7 @@ struct tegra_clk_init_table {
146}; 160};
147 161
148void tegra2_init_clocks(void); 162void tegra2_init_clocks(void);
163void tegra30_init_clocks(void);
149void clk_init(struct clk *clk); 164void clk_init(struct clk *clk);
150struct clk *tegra_get_clock_by_name(const char *name); 165struct clk *tegra_get_clock_by_name(const char *name);
151int clk_reparent(struct clk *c, struct clk *parent); 166int clk_reparent(struct clk *c, struct clk *parent);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 2db20da1d585..29a3f5702af2 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -106,6 +106,7 @@ void __init tegra20_init_early(void)
106#ifdef CONFIG_ARCH_TEGRA_3x_SOC 106#ifdef CONFIG_ARCH_TEGRA_3x_SOC
107void __init tegra30_init_early(void) 107void __init tegra30_init_early(void)
108{ 108{
109 tegra30_init_clocks();
109 tegra_init_cache(0x441, 0x551); 110 tegra_init_cache(0x441, 0x551);
110} 111}
111#endif 112#endif
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
new file mode 100644
index 000000000000..d83a8c0296f5
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -0,0 +1,107 @@
1/*
2 * arch/arm/mach-tegra/cpuidle.c
3 *
4 * CPU idle driver for Tegra CPUs
5 *
6 * Copyright (c) 2010-2012, NVIDIA Corporation.
7 * Copyright (c) 2011 Google, Inc.
8 * Author: Colin Cross <ccross@android.com>
9 * Gary King <gking@nvidia.com>
10 *
11 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/cpu.h>
27#include <linux/cpuidle.h>
28#include <linux/hrtimer.h>
29
30#include <mach/iomap.h>
31
32extern void tegra_cpu_wfi(void);
33
34static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
35 struct cpuidle_driver *drv, int index);
36
37struct cpuidle_driver tegra_idle_driver = {
38 .name = "tegra_idle",
39 .owner = THIS_MODULE,
40 .state_count = 1,
41 .states = {
42 [0] = {
43 .enter = tegra_idle_enter_lp3,
44 .exit_latency = 10,
45 .target_residency = 10,
46 .power_usage = 600,
47 .flags = CPUIDLE_FLAG_TIME_VALID,
48 .name = "LP3",
49 .desc = "CPU flow-controlled",
50 },
51 },
52};
53
54static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
55
56static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
57 struct cpuidle_driver *drv, int index)
58{
59 ktime_t enter, exit;
60 s64 us;
61
62 local_irq_disable();
63 local_fiq_disable();
64
65 enter = ktime_get();
66
67 tegra_cpu_wfi();
68
69 exit = ktime_sub(ktime_get(), enter);
70 us = ktime_to_us(exit);
71
72 local_fiq_enable();
73 local_irq_enable();
74
75 dev->last_residency = us;
76
77 return index;
78}
79
80static int __init tegra_cpuidle_init(void)
81{
82 int ret;
83 unsigned int cpu;
84 struct cpuidle_device *dev;
85 struct cpuidle_driver *drv = &tegra_idle_driver;
86
87 ret = cpuidle_register_driver(&tegra_idle_driver);
88 if (ret) {
89 pr_err("CPUidle driver registration failed\n");
90 return ret;
91 }
92
93 for_each_possible_cpu(cpu) {
94 dev = &per_cpu(tegra_idle_device, cpu);
95 dev->cpu = cpu;
96
97 dev->state_count = drv->state_count;
98 ret = cpuidle_register_device(dev);
99 if (ret) {
100 pr_err("CPU%u: CPUidle device registration failed\n",
101 cpu);
102 return ret;
103 }
104 }
105 return 0;
106}
107device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
new file mode 100644
index 000000000000..74c6efbe52fa
--- /dev/null
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-tegra/flowctrl.h
3 *
4 * functions and macros to control the flowcontroller
5 *
6 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __MACH_TEGRA_FLOWCTRL_H
22#define __MACH_TEGRA_FLOWCTRL_H
23
24#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
25#define FLOW_CTRL_WAITEVENT (2 << 29)
26#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
27#define FLOW_CTRL_JTAG_RESUME (1 << 28)
28#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
29#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
30#define FLOW_CTRL_CPU0_CSR 0x8
31#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
32#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
33#define FLOW_CTRL_CSR_ENABLE (1 << 0)
34#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
35#define FLOW_CTRL_CPU1_CSR 0x18
36
37#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index fc3ecb66de08..d97e403303a0 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -22,10 +22,20 @@
22 22
23struct clk; 23struct clk;
24 24
25enum tegra_clk_ex_param {
26 TEGRA_CLK_VI_INP_SEL,
27 TEGRA_CLK_DTV_INVERT,
28 TEGRA_CLK_NAND_PAD_DIV2_ENB,
29 TEGRA_CLK_PLLD_CSI_OUT_ENB,
30 TEGRA_CLK_PLLD_DSI_OUT_ENB,
31 TEGRA_CLK_PLLD_MIPI_MUX_SEL,
32};
33
25void tegra_periph_reset_deassert(struct clk *c); 34void tegra_periph_reset_deassert(struct clk *c);
26void tegra_periph_reset_assert(struct clk *c); 35void tegra_periph_reset_assert(struct clk *c);
27 36
28unsigned long clk_get_rate_all_locked(struct clk *c); 37unsigned long clk_get_rate_all_locked(struct clk *c);
29void tegra2_sdmmc_tap_delay(struct clk *c, int delay); 38void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
39int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
30 40
31#endif 41#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 19dec3ac0854..67644c905d8e 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -74,6 +74,9 @@
74#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 74#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
75#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 75#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
76 76
77#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
78#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
79
77#define TEGRA_TMR1_BASE 0x60005000 80#define TEGRA_TMR1_BASE 0x60005000
78#define TEGRA_TMR1_SIZE SZ_8 81#define TEGRA_TMR1_SIZE SZ_8
79 82
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index a2146cd6867d..aad1a2c1d714 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -165,11 +165,12 @@
165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) 165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) 166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
167 167
168#define INT_MAIN_NR (INT_QUAD_BASE + 32 - INT_PRI_BASE) 168/* Tegra30 has 5 banks of 32 IRQs */
169 169#define INT_MAIN_NR (32 * 5)
170#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR) 170#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
171 171
172#define INT_GPIO_NR (28 * 8) 172/* Tegra30 has 8 banks of 32 GPIOs */
173#define INT_GPIO_NR (32 * 8)
173 174
174#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) 175#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
175 176
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4e1afcd54fae..2f5bd2db8e1f 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -44,14 +44,16 @@
44#define ICTLR_COP_IER_CLR 0x38 44#define ICTLR_COP_IER_CLR 0x38
45#define ICTLR_COP_IEP_CLASS 0x3c 45#define ICTLR_COP_IEP_CLASS 0x3c
46 46
47#define NUM_ICTLRS 4
48#define FIRST_LEGACY_IRQ 32 47#define FIRST_LEGACY_IRQ 32
49 48
49static int num_ictlrs;
50
50static void __iomem *ictlr_reg_base[] = { 51static void __iomem *ictlr_reg_base[] = {
51 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), 52 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
52 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), 53 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
53 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), 54 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
54 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), 55 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
56 IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
55}; 57};
56 58
57static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) 59static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
@@ -60,7 +62,7 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
60 u32 mask; 62 u32 mask;
61 63
62 BUG_ON(irq < FIRST_LEGACY_IRQ || 64 BUG_ON(irq < FIRST_LEGACY_IRQ ||
63 irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32); 65 irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32);
64 66
65 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; 67 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
66 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); 68 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
@@ -113,8 +115,18 @@ static int tegra_retrigger(struct irq_data *d)
113void __init tegra_init_irq(void) 115void __init tegra_init_irq(void)
114{ 116{
115 int i; 117 int i;
118 void __iomem *distbase;
119
120 distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
121 num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
122
123 if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
124 WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
125 num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
126 num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
127 }
116 128
117 for (i = 0; i < NUM_ICTLRS; i++) { 129 for (i = 0; i < num_ictlrs; i++) {
118 void __iomem *ictlr = ictlr_reg_base[i]; 130 void __iomem *ictlr = ictlr_reg_base[i];
119 writel(~0, ictlr + ICTLR_CPU_IER_CLR); 131 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
120 writel(0, ictlr + ICTLR_CPU_IEP_CLASS); 132 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
@@ -131,6 +143,6 @@ void __init tegra_init_irq(void)
131 * initialized elsewhere under DT. 143 * initialized elsewhere under DT.
132 */ 144 */
133 if (!of_have_populated_dt()) 145 if (!of_have_populated_dt())
134 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 146 gic_init(0, 29, distbase,
135 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 147 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
136} 148}
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
new file mode 100644
index 000000000000..8f9fde161c34
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.S
@@ -0,0 +1,91 @@
1/*
2 * arch/arm/mach-tegra/sleep.S
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
6 *
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
23 */
24
25#include <linux/linkage.h>
26#include <mach/io.h>
27#include <mach/iomap.h>
28
29#include "flowctrl.h"
30
31#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
32 + IO_PPSB_VIRT)
33
34/* returns the offset of the flow controller halt register for a cpu */
35.macro cpu_to_halt_reg rd, rcpu
36 cmp \rcpu, #0
37 subne \rd, \rcpu, #1
38 movne \rd, \rd, lsl #3
39 addne \rd, \rd, #0x14
40 moveq \rd, #0
41.endm
42
43/* returns the offset of the flow controller csr register for a cpu */
44.macro cpu_to_csr_reg rd, rcpu
45 cmp \rcpu, #0
46 subne \rd, \rcpu, #1
47 movne \rd, \rd, lsl #3
48 addne \rd, \rd, #0x18
49 moveq \rd, #8
50.endm
51
52/* returns the ID of the current processor */
53.macro cpu_id, rd
54 mrc p15, 0, \rd, c0, c0, 5
55 and \rd, \rd, #0xF
56.endm
57
58/* loads a 32-bit value into a register without a data access */
59.macro mov32, reg, val
60 movw \reg, #:lower16:\val
61 movt \reg, #:upper16:\val
62.endm
63
64/*
65 * tegra_cpu_wfi
66 *
67 * puts current CPU in clock-gated wfi using the flow controller
68 *
69 * corrupts r0-r3
70 * must be called with MMU on
71 */
72
73ENTRY(tegra_cpu_wfi)
74 cpu_id r0
75 cpu_to_halt_reg r1, r0
76 cpu_to_csr_reg r2, r0
77 mov32 r0, TEGRA_FLOW_CTRL_VIRT
78 mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
79 str r3, [r0, r2] @ clear event & interrupt status
80 mov r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
81 str r3, [r0, r1] @ put flow controller in wait irq mode
82 dsb
83 wfi
84 mov r3, #0
85 str r3, [r0, r1] @ clear flow controller halt status
86 mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
87 str r3, [r0, r2] @ clear event & interrupt status
88 dsb
89 mov pc, lr
90ENDPROC(tegra_cpu_wfi)
91
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index ff9e6b6c0460..1976e934cdd9 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1143,15 +1143,35 @@ static void tegra2_emc_clk_init(struct clk *c)
1143 1143
1144static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate) 1144static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1145{ 1145{
1146 long new_rate = rate; 1146 long emc_rate;
1147 long clk_rate;
1147 1148
1148 new_rate = tegra_emc_round_rate(new_rate); 1149 /*
1149 if (new_rate < 0) 1150 * The slowest entry in the EMC clock table that is at least as
1151 * fast as rate.
1152 */
1153 emc_rate = tegra_emc_round_rate(rate);
1154 if (emc_rate < 0)
1150 return c->max_rate; 1155 return c->max_rate;
1151 1156
1152 BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate)); 1157 /*
1158 * The fastest rate the PLL will generate that is at most the
1159 * requested rate.
1160 */
1161 clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
1162
1163 /*
1164 * If this fails, and emc_rate > clk_rate, it's because the maximum
1165 * rate in the EMC tables is larger than the maximum rate of the EMC
1166 * clock. The EMC clock's max rate is the rate it was running when the
1167 * kernel booted. Such a mismatch is probably due to using the wrong
1168 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1169 */
1170 WARN_ONCE(emc_rate != clk_rate,
1171 "emc_rate %ld != clk_rate %ld",
1172 emc_rate, clk_rate);
1153 1173
1154 return new_rate; 1174 return emc_rate;
1155} 1175}
1156 1176
1157static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate) 1177static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
new file mode 100644
index 000000000000..6d08b53f92d2
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -0,0 +1,3099 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2011 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29#include <linux/cpufreq.h>
30#include <linux/syscore_ops.h>
31
32#include <asm/clkdev.h>
33
34#include <mach/iomap.h>
35
36#include "clock.h"
37#include "fuse.h"
38
39#define USE_PLL_LOCK_BITS 0
40
41#define RST_DEVICES_L 0x004
42#define RST_DEVICES_H 0x008
43#define RST_DEVICES_U 0x00C
44#define RST_DEVICES_V 0x358
45#define RST_DEVICES_W 0x35C
46#define RST_DEVICES_SET_L 0x300
47#define RST_DEVICES_CLR_L 0x304
48#define RST_DEVICES_SET_V 0x430
49#define RST_DEVICES_CLR_V 0x434
50#define RST_DEVICES_NUM 5
51
52#define CLK_OUT_ENB_L 0x010
53#define CLK_OUT_ENB_H 0x014
54#define CLK_OUT_ENB_U 0x018
55#define CLK_OUT_ENB_V 0x360
56#define CLK_OUT_ENB_W 0x364
57#define CLK_OUT_ENB_SET_L 0x320
58#define CLK_OUT_ENB_CLR_L 0x324
59#define CLK_OUT_ENB_SET_V 0x440
60#define CLK_OUT_ENB_CLR_V 0x444
61#define CLK_OUT_ENB_NUM 5
62
63#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
64#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
65
66#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
67#define PERIPH_CLK_TO_RST_REG(c) \
68 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
69#define PERIPH_CLK_TO_RST_SET_REG(c) \
70 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
71#define PERIPH_CLK_TO_RST_CLR_REG(c) \
72 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
73
74#define PERIPH_CLK_TO_ENB_REG(c) \
75 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
76#define PERIPH_CLK_TO_ENB_SET_REG(c) \
77 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
78#define PERIPH_CLK_TO_ENB_CLR_REG(c) \
79 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
80
81#define CLK_MASK_ARM 0x44
82#define MISC_CLK_ENB 0x48
83
84#define OSC_CTRL 0x50
85#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
86#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
87#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
88#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
89#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
90#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
91#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
92#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
93#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
94
95#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
96#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
97#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
98#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
99
100#define OSC_FREQ_DET 0x58
101#define OSC_FREQ_DET_TRIG (1<<31)
102
103#define OSC_FREQ_DET_STATUS 0x5C
104#define OSC_FREQ_DET_BUSY (1<<31)
105#define OSC_FREQ_DET_CNT_MASK 0xFFFF
106
107#define PERIPH_CLK_SOURCE_I2S1 0x100
108#define PERIPH_CLK_SOURCE_EMC 0x19c
109#define PERIPH_CLK_SOURCE_OSC 0x1fc
110#define PERIPH_CLK_SOURCE_NUM1 \
111 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
112
113#define PERIPH_CLK_SOURCE_G3D2 0x3b0
114#define PERIPH_CLK_SOURCE_SE 0x42c
115#define PERIPH_CLK_SOURCE_NUM2 \
116 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
117
118#define AUDIO_DLY_CLK 0x49c
119#define AUDIO_SYNC_CLK_SPDIF 0x4b4
120#define PERIPH_CLK_SOURCE_NUM3 \
121 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
122
123#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
124 PERIPH_CLK_SOURCE_NUM2 + \
125 PERIPH_CLK_SOURCE_NUM3)
126
127#define CPU_SOFTRST_CTRL 0x380
128
129#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
130#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
131#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
132#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
133#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
134#define PERIPH_CLK_UART_DIV_ENB (1<<24)
135#define PERIPH_CLK_VI_SEL_EX_SHIFT 24
136#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
137#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
138#define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
139
140#define AUDIO_SYNC_SOURCE_MASK 0x0F
141#define AUDIO_SYNC_DISABLE_BIT 0x10
142#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
143
144#define PLL_BASE 0x0
145#define PLL_BASE_BYPASS (1<<31)
146#define PLL_BASE_ENABLE (1<<30)
147#define PLL_BASE_REF_ENABLE (1<<29)
148#define PLL_BASE_OVERRIDE (1<<28)
149#define PLL_BASE_LOCK (1<<27)
150#define PLL_BASE_DIVP_MASK (0x7<<20)
151#define PLL_BASE_DIVP_SHIFT 20
152#define PLL_BASE_DIVN_MASK (0x3FF<<8)
153#define PLL_BASE_DIVN_SHIFT 8
154#define PLL_BASE_DIVM_MASK (0x1F)
155#define PLL_BASE_DIVM_SHIFT 0
156
157#define PLL_OUT_RATIO_MASK (0xFF<<8)
158#define PLL_OUT_RATIO_SHIFT 8
159#define PLL_OUT_OVERRIDE (1<<2)
160#define PLL_OUT_CLKEN (1<<1)
161#define PLL_OUT_RESET_DISABLE (1<<0)
162
163#define PLL_MISC(c) \
164 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
165#define PLL_MISC_LOCK_ENABLE(c) \
166 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
167
168#define PLL_MISC_DCCON_SHIFT 20
169#define PLL_MISC_CPCON_SHIFT 8
170#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
171#define PLL_MISC_LFCON_SHIFT 4
172#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
173#define PLL_MISC_VCOCON_SHIFT 0
174#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
175#define PLLD_MISC_CLKENABLE (1<<30)
176
177#define PLLU_BASE_POST_DIV (1<<20)
178
179#define PLLD_BASE_DSIB_MUX_SHIFT 25
180#define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
181#define PLLD_BASE_CSI_CLKENABLE (1<<26)
182#define PLLD_MISC_DSI_CLKENABLE (1<<30)
183#define PLLD_MISC_DIV_RST (1<<23)
184#define PLLD_MISC_DCCON_SHIFT 12
185
186#define PLLDU_LFCON_SET_DIVN 600
187
188/* FIXME: OUT_OF_TABLE_CPCON per pll */
189#define OUT_OF_TABLE_CPCON 0x8
190
191#define SUPER_CLK_MUX 0x00
192#define SUPER_STATE_SHIFT 28
193#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
194#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
195#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
196#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
197#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
198#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
199#define SUPER_LP_DIV2_BYPASS (0x1 << 16)
200#define SUPER_SOURCE_MASK 0xF
201#define SUPER_FIQ_SOURCE_SHIFT 12
202#define SUPER_IRQ_SOURCE_SHIFT 8
203#define SUPER_RUN_SOURCE_SHIFT 4
204#define SUPER_IDLE_SOURCE_SHIFT 0
205
206#define SUPER_CLK_DIVIDER 0x04
207#define SUPER_CLOCK_DIV_U71_SHIFT 16
208#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
209/* guarantees safe cpu backup */
210#define SUPER_CLOCK_DIV_U71_MIN 0x2
211
212#define BUS_CLK_DISABLE (1<<3)
213#define BUS_CLK_DIV_MASK 0x3
214
215#define PMC_CTRL 0x0
216 #define PMC_CTRL_BLINK_ENB (1 << 7)
217
218#define PMC_DPD_PADS_ORIDE 0x1c
219 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
220
221#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
222#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
223#define PMC_BLINK_TIMER_ENB (1 << 15)
224#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
225#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
226
227#define PMC_PLLP_WB0_OVERRIDE 0xf8
228#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
229
230#define UTMIP_PLL_CFG2 0x488
231#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
232#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
233#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
234#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
235#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
236
237#define UTMIP_PLL_CFG1 0x484
238#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
239#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
240#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
241#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
242#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
243
244#define PLLE_BASE_CML_ENABLE (1<<31)
245#define PLLE_BASE_ENABLE (1<<30)
246#define PLLE_BASE_DIVCML_SHIFT 24
247#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
248#define PLLE_BASE_DIVP_SHIFT 16
249#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
250#define PLLE_BASE_DIVN_SHIFT 8
251#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
252#define PLLE_BASE_DIVM_SHIFT 0
253#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
254#define PLLE_BASE_DIV_MASK \
255 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
256 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
257#define PLLE_BASE_DIV(m, n, p, cml) \
258 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
259 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
260
261#define PLLE_MISC_SETUP_BASE_SHIFT 16
262#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
263#define PLLE_MISC_READY (1<<15)
264#define PLLE_MISC_LOCK (1<<11)
265#define PLLE_MISC_LOCK_ENABLE (1<<9)
266#define PLLE_MISC_SETUP_EX_SHIFT 2
267#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
268#define PLLE_MISC_SETUP_MASK \
269 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
270#define PLLE_MISC_SETUP_VALUE \
271 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
272
273#define PLLE_SS_CTRL 0x68
274#define PLLE_SS_INCINTRV_SHIFT 24
275#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
276#define PLLE_SS_INC_SHIFT 16
277#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
278#define PLLE_SS_MAX_SHIFT 0
279#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
280#define PLLE_SS_COEFFICIENTS_MASK \
281 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
282#define PLLE_SS_COEFFICIENTS_12MHZ \
283 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
284 (0x24<<PLLE_SS_MAX_SHIFT))
285#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
286
287#define PLLE_AUX 0x48c
288#define PLLE_AUX_PLLP_SEL (1<<2)
289#define PLLE_AUX_CML_SATA_ENABLE (1<<1)
290#define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
291
292#define PMC_SATA_PWRGT 0x1ac
293#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
294#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
295
296#define ROUND_DIVIDER_UP 0
297#define ROUND_DIVIDER_DOWN 1
298
299/* FIXME: recommended safety delay after lock is detected */
300#define PLL_POST_LOCK_DELAY 100
301
302/**
303* Structure defining the fields for USB UTMI clocks Parameters.
304*/
305struct utmi_clk_param {
306 /* Oscillator Frequency in KHz */
307 u32 osc_frequency;
308 /* UTMIP PLL Enable Delay Count */
309 u8 enable_delay_count;
310 /* UTMIP PLL Stable count */
311 u8 stable_count;
312 /* UTMIP PLL Active delay count */
313 u8 active_delay_count;
314 /* UTMIP PLL Xtal frequency count */
315 u8 xtal_freq_count;
316};
317
318static const struct utmi_clk_param utmi_parameters[] = {
319 {
320 .osc_frequency = 13000000,
321 .enable_delay_count = 0x02,
322 .stable_count = 0x33,
323 .active_delay_count = 0x05,
324 .xtal_freq_count = 0x7F
325 },
326 {
327 .osc_frequency = 19200000,
328 .enable_delay_count = 0x03,
329 .stable_count = 0x4B,
330 .active_delay_count = 0x06,
331 .xtal_freq_count = 0xBB},
332 {
333 .osc_frequency = 12000000,
334 .enable_delay_count = 0x02,
335 .stable_count = 0x2F,
336 .active_delay_count = 0x04,
337 .xtal_freq_count = 0x76
338 },
339 {
340 .osc_frequency = 26000000,
341 .enable_delay_count = 0x04,
342 .stable_count = 0x66,
343 .active_delay_count = 0x09,
344 .xtal_freq_count = 0xFE
345 },
346 {
347 .osc_frequency = 16800000,
348 .enable_delay_count = 0x03,
349 .stable_count = 0x41,
350 .active_delay_count = 0x0A,
351 .xtal_freq_count = 0xA4
352 },
353};
354
355static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
356static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
357static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
358
359#define MISC_GP_HIDREV 0x804
360
361/*
362 * Some peripheral clocks share an enable bit, so refcount the enable bits
363 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
364 */
365static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
366
367#define clk_writel(value, reg) \
368 __raw_writel(value, (u32)reg_clk_base + (reg))
369#define clk_readl(reg) \
370 __raw_readl((u32)reg_clk_base + (reg))
371#define pmc_writel(value, reg) \
372 __raw_writel(value, (u32)reg_pmc_base + (reg))
373#define pmc_readl(reg) \
374 __raw_readl((u32)reg_pmc_base + (reg))
375#define chipid_readl() \
376 __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
377
378#define clk_writel_delay(value, reg) \
379 do { \
380 __raw_writel((value), (u32)reg_clk_base + (reg)); \
381 udelay(2); \
382 } while (0)
383
384
385static inline int clk_set_div(struct clk *c, u32 n)
386{
387 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
388}
389
390static inline u32 periph_clk_to_reg(
391 struct clk *c, u32 reg_L, u32 reg_V, int offs)
392{
393 u32 reg = c->u.periph.clk_num / 32;
394 BUG_ON(reg >= RST_DEVICES_NUM);
395 if (reg < 3)
396 reg = reg_L + (reg * offs);
397 else
398 reg = reg_V + ((reg - 3) * offs);
399 return reg;
400}
401
402static unsigned long clk_measure_input_freq(void)
403{
404 u32 clock_autodetect;
405 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
406 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
407 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
408 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
409 return 12000000;
410 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
411 return 13000000;
412 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
413 return 19200000;
414 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
415 return 26000000;
416 } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
417 return 16800000;
418 } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
419 return 38400000;
420 } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
421 return 48000000;
422 } else {
423 pr_err("%s: Unexpected clock autodetect value %d", __func__,
424 clock_autodetect);
425 BUG();
426 return 0;
427 }
428}
429
430static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
431 u32 flags, u32 round_mode)
432{
433 s64 divider_u71 = parent_rate;
434 if (!rate)
435 return -EINVAL;
436
437 if (!(flags & DIV_U71_INT))
438 divider_u71 *= 2;
439 if (round_mode == ROUND_DIVIDER_UP)
440 divider_u71 += rate - 1;
441 do_div(divider_u71, rate);
442 if (flags & DIV_U71_INT)
443 divider_u71 *= 2;
444
445 if (divider_u71 - 2 < 0)
446 return 0;
447
448 if (divider_u71 - 2 > 255)
449 return -EINVAL;
450
451 return divider_u71 - 2;
452}
453
454static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
455{
456 s64 divider_u16;
457
458 divider_u16 = parent_rate;
459 if (!rate)
460 return -EINVAL;
461 divider_u16 += rate - 1;
462 do_div(divider_u16, rate);
463
464 if (divider_u16 - 1 < 0)
465 return 0;
466
467 if (divider_u16 - 1 > 0xFFFF)
468 return -EINVAL;
469
470 return divider_u16 - 1;
471}
472
473/* clk_m functions */
474static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
475{
476 u32 osc_ctrl = clk_readl(OSC_CTRL);
477 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
478 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
479
480 c->rate = clk_measure_input_freq();
481 switch (c->rate) {
482 case 12000000:
483 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
484 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
485 break;
486 case 13000000:
487 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
488 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
489 break;
490 case 19200000:
491 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
492 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
493 break;
494 case 26000000:
495 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
496 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
497 break;
498 case 16800000:
499 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
500 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
501 break;
502 case 38400000:
503 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
504 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
505 break;
506 case 48000000:
507 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
508 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
509 break;
510 default:
511 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
512 BUG();
513 }
514 clk_writel(auto_clock_control, OSC_CTRL);
515 return c->rate;
516}
517
518static void tegra30_clk_m_init(struct clk *c)
519{
520 pr_debug("%s on clock %s\n", __func__, c->name);
521 tegra30_clk_m_autodetect_rate(c);
522}
523
524static int tegra30_clk_m_enable(struct clk *c)
525{
526 pr_debug("%s on clock %s\n", __func__, c->name);
527 return 0;
528}
529
530static void tegra30_clk_m_disable(struct clk *c)
531{
532 pr_debug("%s on clock %s\n", __func__, c->name);
533 WARN(1, "Attempting to disable main SoC clock\n");
534}
535
536static struct clk_ops tegra_clk_m_ops = {
537 .init = tegra30_clk_m_init,
538 .enable = tegra30_clk_m_enable,
539 .disable = tegra30_clk_m_disable,
540};
541
542static struct clk_ops tegra_clk_m_div_ops = {
543 .enable = tegra30_clk_m_enable,
544};
545
546/* PLL reference divider functions */
547static void tegra30_pll_ref_init(struct clk *c)
548{
549 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
550 pr_debug("%s on clock %s\n", __func__, c->name);
551
552 switch (pll_ref_div) {
553 case OSC_CTRL_PLL_REF_DIV_1:
554 c->div = 1;
555 break;
556 case OSC_CTRL_PLL_REF_DIV_2:
557 c->div = 2;
558 break;
559 case OSC_CTRL_PLL_REF_DIV_4:
560 c->div = 4;
561 break;
562 default:
563 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
564 BUG();
565 }
566 c->mul = 1;
567 c->state = ON;
568}
569
570static struct clk_ops tegra_pll_ref_ops = {
571 .init = tegra30_pll_ref_init,
572 .enable = tegra30_clk_m_enable,
573 .disable = tegra30_clk_m_disable,
574};
575
576/* super clock functions */
577/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
578 * clock skipping super divider. We will ignore the clock skipping divider,
579 * since we can't lower the voltage when using the clock skip, but we can if
580 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
581 * only when its parent is a fixed rate PLL, since we can't change PLL rate
582 * in this case.
583 */
584static void tegra30_super_clk_init(struct clk *c)
585{
586 u32 val;
587 int source;
588 int shift;
589 const struct clk_mux_sel *sel;
590 val = clk_readl(c->reg + SUPER_CLK_MUX);
591 c->state = ON;
592 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
593 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
594 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
595 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
596 source = (val >> shift) & SUPER_SOURCE_MASK;
597 if (c->flags & DIV_2)
598 source |= val & SUPER_LP_DIV2_BYPASS;
599 for (sel = c->inputs; sel->input != NULL; sel++) {
600 if (sel->value == source)
601 break;
602 }
603 BUG_ON(sel->input == NULL);
604 c->parent = sel->input;
605
606 if (c->flags & DIV_U71) {
607 /* Init safe 7.1 divider value (does not affect PLLX path) */
608 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
609 c->reg + SUPER_CLK_DIVIDER);
610 c->mul = 2;
611 c->div = 2;
612 if (!(c->parent->flags & PLLX))
613 c->div += SUPER_CLOCK_DIV_U71_MIN;
614 } else
615 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
616}
617
618static int tegra30_super_clk_enable(struct clk *c)
619{
620 return 0;
621}
622
623static void tegra30_super_clk_disable(struct clk *c)
624{
625 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
626 geared up g-mode super clock - mode switch may request to disable
627 either of them; accept request with no affect on h/w */
628}
629
630static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
631{
632 u32 val;
633 const struct clk_mux_sel *sel;
634 int shift;
635
636 val = clk_readl(c->reg + SUPER_CLK_MUX);
637 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
638 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
639 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
640 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
641 for (sel = c->inputs; sel->input != NULL; sel++) {
642 if (sel->input == p) {
643 /* For LP mode super-clock switch between PLLX direct
644 and divided-by-2 outputs is allowed only when other
645 than PLLX clock source is current parent */
646 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
647 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
648 if (c->parent->flags & PLLX)
649 return -EINVAL;
650 val ^= SUPER_LP_DIV2_BYPASS;
651 clk_writel_delay(val, c->reg);
652 }
653 val &= ~(SUPER_SOURCE_MASK << shift);
654 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
655
656 /* 7.1 divider for CPU super-clock does not affect
657 PLLX path */
658 if (c->flags & DIV_U71) {
659 u32 div = 0;
660 if (!(p->flags & PLLX)) {
661 div = clk_readl(c->reg +
662 SUPER_CLK_DIVIDER);
663 div &= SUPER_CLOCK_DIV_U71_MASK;
664 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
665 }
666 c->div = div + 2;
667 c->mul = 2;
668 }
669
670 if (c->refcnt)
671 clk_enable(p);
672
673 clk_writel_delay(val, c->reg);
674
675 if (c->refcnt && c->parent)
676 clk_disable(c->parent);
677
678 clk_reparent(c, p);
679 return 0;
680 }
681 }
682 return -EINVAL;
683}
684
685/*
686 * Do not use super clocks "skippers", since dividing using a clock skipper
687 * does not allow the voltage to be scaled down. Instead adjust the rate of
688 * the parent clock. This requires that the parent of a super clock have no
689 * other children, otherwise the rate will change underneath the other
690 * children. Special case: if fixed rate PLL is CPU super clock parent the
691 * rate of this PLL can't be changed, and it has many other children. In
692 * this case use 7.1 fractional divider to adjust the super clock rate.
693 */
694static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
695{
696 if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
697 int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
698 rate, c->flags, ROUND_DIVIDER_DOWN);
699 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
700
701 clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
702 c->reg + SUPER_CLK_DIVIDER);
703 c->div = div + 2;
704 c->mul = 2;
705 return 0;
706 }
707 return clk_set_rate(c->parent, rate);
708}
709
710static struct clk_ops tegra_super_ops = {
711 .init = tegra30_super_clk_init,
712 .enable = tegra30_super_clk_enable,
713 .disable = tegra30_super_clk_disable,
714 .set_parent = tegra30_super_clk_set_parent,
715 .set_rate = tegra30_super_clk_set_rate,
716};
717
718static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
719{
720 /* The input value 'rate' is the clock rate of the CPU complex. */
721 c->rate = (rate * c->mul) / c->div;
722 return 0;
723}
724
725static struct clk_ops tegra30_twd_ops = {
726 .set_rate = tegra30_twd_clk_set_rate,
727};
728
729/* Blink output functions */
730
731static void tegra30_blink_clk_init(struct clk *c)
732{
733 u32 val;
734
735 val = pmc_readl(PMC_CTRL);
736 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
737 c->mul = 1;
738 val = pmc_readl(c->reg);
739
740 if (val & PMC_BLINK_TIMER_ENB) {
741 unsigned int on_off;
742
743 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
744 PMC_BLINK_TIMER_DATA_ON_MASK;
745 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
746 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
747 on_off += val;
748 /* each tick in the blink timer is 4 32KHz clocks */
749 c->div = on_off * 4;
750 } else {
751 c->div = 1;
752 }
753}
754
755static int tegra30_blink_clk_enable(struct clk *c)
756{
757 u32 val;
758
759 val = pmc_readl(PMC_DPD_PADS_ORIDE);
760 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
761
762 val = pmc_readl(PMC_CTRL);
763 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
764
765 return 0;
766}
767
768static void tegra30_blink_clk_disable(struct clk *c)
769{
770 u32 val;
771
772 val = pmc_readl(PMC_CTRL);
773 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
774
775 val = pmc_readl(PMC_DPD_PADS_ORIDE);
776 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
777}
778
779static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
780{
781 unsigned long parent_rate = clk_get_rate(c->parent);
782 if (rate >= parent_rate) {
783 c->div = 1;
784 pmc_writel(0, c->reg);
785 } else {
786 unsigned int on_off;
787 u32 val;
788
789 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
790 c->div = on_off * 8;
791
792 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
793 PMC_BLINK_TIMER_DATA_ON_SHIFT;
794 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
795 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
796 val |= on_off;
797 val |= PMC_BLINK_TIMER_ENB;
798 pmc_writel(val, c->reg);
799 }
800
801 return 0;
802}
803
804static struct clk_ops tegra_blink_clk_ops = {
805 .init = &tegra30_blink_clk_init,
806 .enable = &tegra30_blink_clk_enable,
807 .disable = &tegra30_blink_clk_disable,
808 .set_rate = &tegra30_blink_clk_set_rate,
809};
810
811/* PLL Functions */
812static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
813 u32 lock_bit)
814{
815#if USE_PLL_LOCK_BITS
816 int i;
817 for (i = 0; i < c->u.pll.lock_delay; i++) {
818 if (clk_readl(lock_reg) & lock_bit) {
819 udelay(PLL_POST_LOCK_DELAY);
820 return 0;
821 }
822 udelay(2); /* timeout = 2 * lock time */
823 }
824 pr_err("Timed out waiting for lock bit on pll %s", c->name);
825 return -1;
826#endif
827 udelay(c->u.pll.lock_delay);
828
829 return 0;
830}
831
832
833static void tegra30_utmi_param_configure(struct clk *c)
834{
835 u32 reg;
836 int i;
837 unsigned long main_rate =
838 clk_get_rate(c->parent->parent);
839
840 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
841 if (main_rate == utmi_parameters[i].osc_frequency)
842 break;
843 }
844
845 if (i >= ARRAY_SIZE(utmi_parameters)) {
846 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
847 return;
848 }
849
850 reg = clk_readl(UTMIP_PLL_CFG2);
851
852 /* Program UTMIP PLL stable and active counts */
853 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
854 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
855 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
856 utmi_parameters[i].stable_count);
857
858 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
859
860 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
861 utmi_parameters[i].active_delay_count);
862
863 /* Remove power downs from UTMIP PLL control bits */
864 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
865 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
866 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
867
868 clk_writel(reg, UTMIP_PLL_CFG2);
869
870 /* Program UTMIP PLL delay and oscillator frequency counts */
871 reg = clk_readl(UTMIP_PLL_CFG1);
872 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
873
874 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
875 utmi_parameters[i].enable_delay_count);
876
877 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
878 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
879 utmi_parameters[i].xtal_freq_count);
880
881 /* Remove power downs from UTMIP PLL control bits */
882 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
883 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
884 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
885
886 clk_writel(reg, UTMIP_PLL_CFG1);
887}
888
889static void tegra30_pll_clk_init(struct clk *c)
890{
891 u32 val = clk_readl(c->reg + PLL_BASE);
892
893 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
894
895 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
896 const struct clk_pll_freq_table *sel;
897 unsigned long input_rate = clk_get_rate(c->parent);
898 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
899 if (sel->input_rate == input_rate &&
900 sel->output_rate == c->u.pll.fixed_rate) {
901 c->mul = sel->n;
902 c->div = sel->m * sel->p;
903 return;
904 }
905 }
906 pr_err("Clock %s has unknown fixed frequency\n", c->name);
907 BUG();
908 } else if (val & PLL_BASE_BYPASS) {
909 c->mul = 1;
910 c->div = 1;
911 } else {
912 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
913 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
914 if (c->flags & PLLU)
915 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
916 else
917 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
918 PLL_BASE_DIVP_SHIFT));
919 if (c->flags & PLL_FIXED) {
920 unsigned long rate = clk_get_rate_locked(c);
921 BUG_ON(rate != c->u.pll.fixed_rate);
922 }
923 }
924
925 if (c->flags & PLLU)
926 tegra30_utmi_param_configure(c);
927}
928
929static int tegra30_pll_clk_enable(struct clk *c)
930{
931 u32 val;
932 pr_debug("%s on clock %s\n", __func__, c->name);
933
934#if USE_PLL_LOCK_BITS
935 val = clk_readl(c->reg + PLL_MISC(c));
936 val |= PLL_MISC_LOCK_ENABLE(c);
937 clk_writel(val, c->reg + PLL_MISC(c));
938#endif
939 val = clk_readl(c->reg + PLL_BASE);
940 val &= ~PLL_BASE_BYPASS;
941 val |= PLL_BASE_ENABLE;
942 clk_writel(val, c->reg + PLL_BASE);
943
944 if (c->flags & PLLM) {
945 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
946 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
947 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
948 }
949
950 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
951
952 return 0;
953}
954
955static void tegra30_pll_clk_disable(struct clk *c)
956{
957 u32 val;
958 pr_debug("%s on clock %s\n", __func__, c->name);
959
960 val = clk_readl(c->reg);
961 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
962 clk_writel(val, c->reg);
963
964 if (c->flags & PLLM) {
965 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
966 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
967 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
968 }
969}
970
971static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
972{
973 u32 val, p_div, old_base;
974 unsigned long input_rate;
975 const struct clk_pll_freq_table *sel;
976 struct clk_pll_freq_table cfg;
977
978 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
979
980 if (c->flags & PLL_FIXED) {
981 int ret = 0;
982 if (rate != c->u.pll.fixed_rate) {
983 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
984 __func__, c->name, c->u.pll.fixed_rate, rate);
985 ret = -EINVAL;
986 }
987 return ret;
988 }
989
990 if (c->flags & PLLM) {
991 if (rate != clk_get_rate_locked(c)) {
992 pr_err("%s: Can not change memory %s rate in flight\n",
993 __func__, c->name);
994 return -EINVAL;
995 }
996 return 0;
997 }
998
999 p_div = 0;
1000 input_rate = clk_get_rate(c->parent);
1001
1002 /* Check if the target rate is tabulated */
1003 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1004 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1005 if (c->flags & PLLU) {
1006 BUG_ON(sel->p < 1 || sel->p > 2);
1007 if (sel->p == 1)
1008 p_div = PLLU_BASE_POST_DIV;
1009 } else {
1010 BUG_ON(sel->p < 1);
1011 for (val = sel->p; val > 1; val >>= 1)
1012 p_div++;
1013 p_div <<= PLL_BASE_DIVP_SHIFT;
1014 }
1015 break;
1016 }
1017 }
1018
1019 /* Configure out-of-table rate */
1020 if (sel->input_rate == 0) {
1021 unsigned long cfreq;
1022 BUG_ON(c->flags & PLLU);
1023 sel = &cfg;
1024
1025 switch (input_rate) {
1026 case 12000000:
1027 case 26000000:
1028 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1029 break;
1030 case 13000000:
1031 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1032 break;
1033 case 16800000:
1034 case 19200000:
1035 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1036 break;
1037 default:
1038 pr_err("%s: Unexpected reference rate %lu\n",
1039 __func__, input_rate);
1040 BUG();
1041 }
1042
1043 /* Raise VCO to guarantee 0.5% accuracy */
1044 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1045 cfg.output_rate <<= 1)
1046 p_div++;
1047
1048 cfg.p = 0x1 << p_div;
1049 cfg.m = input_rate / cfreq;
1050 cfg.n = cfg.output_rate / cfreq;
1051 cfg.cpcon = OUT_OF_TABLE_CPCON;
1052
1053 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
1054 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
1055 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1056 (cfg.output_rate > c->u.pll.vco_max)) {
1057 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1058 __func__, c->name, rate);
1059 return -EINVAL;
1060 }
1061 p_div <<= PLL_BASE_DIVP_SHIFT;
1062 }
1063
1064 c->mul = sel->n;
1065 c->div = sel->m * sel->p;
1066
1067 old_base = val = clk_readl(c->reg + PLL_BASE);
1068 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
1069 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
1070 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
1071 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
1072 if (val == old_base)
1073 return 0;
1074
1075 if (c->state == ON) {
1076 tegra30_pll_clk_disable(c);
1077 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1078 }
1079 clk_writel(val, c->reg + PLL_BASE);
1080
1081 if (c->flags & PLL_HAS_CPCON) {
1082 val = clk_readl(c->reg + PLL_MISC(c));
1083 val &= ~PLL_MISC_CPCON_MASK;
1084 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
1085 if (c->flags & (PLLU | PLLD)) {
1086 val &= ~PLL_MISC_LFCON_MASK;
1087 if (sel->n >= PLLDU_LFCON_SET_DIVN)
1088 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
1089 } else if (c->flags & (PLLX | PLLM)) {
1090 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
1091 if (rate >= (c->u.pll.vco_max >> 1))
1092 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
1093 }
1094 clk_writel(val, c->reg + PLL_MISC(c));
1095 }
1096
1097 if (c->state == ON)
1098 tegra30_pll_clk_enable(c);
1099
1100 return 0;
1101}
1102
1103static struct clk_ops tegra_pll_ops = {
1104 .init = tegra30_pll_clk_init,
1105 .enable = tegra30_pll_clk_enable,
1106 .disable = tegra30_pll_clk_disable,
1107 .set_rate = tegra30_pll_clk_set_rate,
1108};
1109
1110static int
1111tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1112{
1113 u32 val, mask, reg;
1114
1115 switch (p) {
1116 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
1117 mask = PLLD_BASE_CSI_CLKENABLE;
1118 reg = c->reg + PLL_BASE;
1119 break;
1120 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
1121 mask = PLLD_MISC_DSI_CLKENABLE;
1122 reg = c->reg + PLL_MISC(c);
1123 break;
1124 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
1125 if (!(c->flags & PLL_ALT_MISC_REG)) {
1126 mask = PLLD_BASE_DSIB_MUX_MASK;
1127 reg = c->reg + PLL_BASE;
1128 break;
1129 }
1130 /* fall through - error since PLLD2 does not have MUX_SEL control */
1131 default:
1132 return -EINVAL;
1133 }
1134
1135 val = clk_readl(reg);
1136 if (setting)
1137 val |= mask;
1138 else
1139 val &= ~mask;
1140 clk_writel(val, reg);
1141 return 0;
1142}
1143
1144static struct clk_ops tegra_plld_ops = {
1145 .init = tegra30_pll_clk_init,
1146 .enable = tegra30_pll_clk_enable,
1147 .disable = tegra30_pll_clk_disable,
1148 .set_rate = tegra30_pll_clk_set_rate,
1149 .clk_cfg_ex = tegra30_plld_clk_cfg_ex,
1150};
1151
1152static void tegra30_plle_clk_init(struct clk *c)
1153{
1154 u32 val;
1155
1156 val = clk_readl(PLLE_AUX);
1157 c->parent = (val & PLLE_AUX_PLLP_SEL) ?
1158 tegra_get_clock_by_name("pll_p") :
1159 tegra_get_clock_by_name("pll_ref");
1160
1161 val = clk_readl(c->reg + PLL_BASE);
1162 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1163 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1164 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1165 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1166}
1167
1168static void tegra30_plle_clk_disable(struct clk *c)
1169{
1170 u32 val;
1171 pr_debug("%s on clock %s\n", __func__, c->name);
1172
1173 val = clk_readl(c->reg + PLL_BASE);
1174 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1175 clk_writel(val, c->reg + PLL_BASE);
1176}
1177
1178static void tegra30_plle_training(struct clk *c)
1179{
1180 u32 val;
1181
1182 /* PLLE is already disabled, and setup cleared;
1183 * create falling edge on PLLE IDDQ input */
1184 val = pmc_readl(PMC_SATA_PWRGT);
1185 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1186 pmc_writel(val, PMC_SATA_PWRGT);
1187
1188 val = pmc_readl(PMC_SATA_PWRGT);
1189 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
1190 pmc_writel(val, PMC_SATA_PWRGT);
1191
1192 val = pmc_readl(PMC_SATA_PWRGT);
1193 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1194 pmc_writel(val, PMC_SATA_PWRGT);
1195
1196 do {
1197 val = clk_readl(c->reg + PLL_MISC(c));
1198 } while (!(val & PLLE_MISC_READY));
1199}
1200
1201static int tegra30_plle_configure(struct clk *c, bool force_training)
1202{
1203 u32 val;
1204 const struct clk_pll_freq_table *sel;
1205 unsigned long rate = c->u.pll.fixed_rate;
1206 unsigned long input_rate = clk_get_rate(c->parent);
1207
1208 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1209 if (sel->input_rate == input_rate && sel->output_rate == rate)
1210 break;
1211 }
1212
1213 if (sel->input_rate == 0)
1214 return -ENOSYS;
1215
1216 /* disable PLLE, clear setup fiels */
1217 tegra30_plle_clk_disable(c);
1218
1219 val = clk_readl(c->reg + PLL_MISC(c));
1220 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
1221 clk_writel(val, c->reg + PLL_MISC(c));
1222
1223 /* training */
1224 val = clk_readl(c->reg + PLL_MISC(c));
1225 if (force_training || (!(val & PLLE_MISC_READY)))
1226 tegra30_plle_training(c);
1227
1228 /* configure dividers, setup, disable SS */
1229 val = clk_readl(c->reg + PLL_BASE);
1230 val &= ~PLLE_BASE_DIV_MASK;
1231 val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
1232 clk_writel(val, c->reg + PLL_BASE);
1233 c->mul = sel->n;
1234 c->div = sel->m * sel->p;
1235
1236 val = clk_readl(c->reg + PLL_MISC(c));
1237 val |= PLLE_MISC_SETUP_VALUE;
1238 val |= PLLE_MISC_LOCK_ENABLE;
1239 clk_writel(val, c->reg + PLL_MISC(c));
1240
1241 val = clk_readl(PLLE_SS_CTRL);
1242 val |= PLLE_SS_DISABLE;
1243 clk_writel(val, PLLE_SS_CTRL);
1244
1245 /* enable and lock PLLE*/
1246 val = clk_readl(c->reg + PLL_BASE);
1247 val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1248 clk_writel(val, c->reg + PLL_BASE);
1249
1250 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
1251
1252 return 0;
1253}
1254
1255static int tegra30_plle_clk_enable(struct clk *c)
1256{
1257 pr_debug("%s on clock %s\n", __func__, c->name);
1258 return tegra30_plle_configure(c, !c->set);
1259}
1260
1261static struct clk_ops tegra_plle_ops = {
1262 .init = tegra30_plle_clk_init,
1263 .enable = tegra30_plle_clk_enable,
1264 .disable = tegra30_plle_clk_disable,
1265};
1266
1267/* Clock divider ops */
1268static void tegra30_pll_div_clk_init(struct clk *c)
1269{
1270 if (c->flags & DIV_U71) {
1271 u32 divu71;
1272 u32 val = clk_readl(c->reg);
1273 val >>= c->reg_shift;
1274 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1275 if (!(val & PLL_OUT_RESET_DISABLE))
1276 c->state = OFF;
1277
1278 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1279 c->div = (divu71 + 2);
1280 c->mul = 2;
1281 } else if (c->flags & DIV_2) {
1282 c->state = ON;
1283 if (c->flags & (PLLD | PLLX)) {
1284 c->div = 2;
1285 c->mul = 1;
1286 } else
1287 BUG();
1288 } else {
1289 c->state = ON;
1290 c->div = 1;
1291 c->mul = 1;
1292 }
1293}
1294
1295static int tegra30_pll_div_clk_enable(struct clk *c)
1296{
1297 u32 val;
1298 u32 new_val;
1299
1300 pr_debug("%s: %s\n", __func__, c->name);
1301 if (c->flags & DIV_U71) {
1302 val = clk_readl(c->reg);
1303 new_val = val >> c->reg_shift;
1304 new_val &= 0xFFFF;
1305
1306 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
1307
1308 val &= ~(0xFFFF << c->reg_shift);
1309 val |= new_val << c->reg_shift;
1310 clk_writel_delay(val, c->reg);
1311 return 0;
1312 } else if (c->flags & DIV_2) {
1313 return 0;
1314 }
1315 return -EINVAL;
1316}
1317
1318static void tegra30_pll_div_clk_disable(struct clk *c)
1319{
1320 u32 val;
1321 u32 new_val;
1322
1323 pr_debug("%s: %s\n", __func__, c->name);
1324 if (c->flags & DIV_U71) {
1325 val = clk_readl(c->reg);
1326 new_val = val >> c->reg_shift;
1327 new_val &= 0xFFFF;
1328
1329 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
1330
1331 val &= ~(0xFFFF << c->reg_shift);
1332 val |= new_val << c->reg_shift;
1333 clk_writel_delay(val, c->reg);
1334 }
1335}
1336
1337static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
1338{
1339 u32 val;
1340 u32 new_val;
1341 int divider_u71;
1342 unsigned long parent_rate = clk_get_rate(c->parent);
1343
1344 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1345 if (c->flags & DIV_U71) {
1346 divider_u71 = clk_div71_get_divider(
1347 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1348 if (divider_u71 >= 0) {
1349 val = clk_readl(c->reg);
1350 new_val = val >> c->reg_shift;
1351 new_val &= 0xFFFF;
1352 if (c->flags & DIV_U71_FIXED)
1353 new_val |= PLL_OUT_OVERRIDE;
1354 new_val &= ~PLL_OUT_RATIO_MASK;
1355 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1356
1357 val &= ~(0xFFFF << c->reg_shift);
1358 val |= new_val << c->reg_shift;
1359 clk_writel_delay(val, c->reg);
1360 c->div = divider_u71 + 2;
1361 c->mul = 2;
1362 return 0;
1363 }
1364 } else if (c->flags & DIV_2)
1365 return clk_set_rate(c->parent, rate * 2);
1366
1367 return -EINVAL;
1368}
1369
1370static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1371{
1372 int divider;
1373 unsigned long parent_rate = clk_get_rate(c->parent);
1374 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1375
1376 if (c->flags & DIV_U71) {
1377 divider = clk_div71_get_divider(
1378 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1379 if (divider < 0)
1380 return divider;
1381 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1382 } else if (c->flags & DIV_2)
1383 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
1384 return rate;
1385
1386 return -EINVAL;
1387}
1388
1389static struct clk_ops tegra_pll_div_ops = {
1390 .init = tegra30_pll_div_clk_init,
1391 .enable = tegra30_pll_div_clk_enable,
1392 .disable = tegra30_pll_div_clk_disable,
1393 .set_rate = tegra30_pll_div_clk_set_rate,
1394 .round_rate = tegra30_pll_div_clk_round_rate,
1395};
1396
1397/* Periph clk ops */
1398static inline u32 periph_clk_source_mask(struct clk *c)
1399{
1400 if (c->flags & MUX8)
1401 return 7 << 29;
1402 else if (c->flags & MUX_PWM)
1403 return 3 << 28;
1404 else if (c->flags & MUX_CLK_OUT)
1405 return 3 << (c->u.periph.clk_num + 4);
1406 else if (c->flags & PLLD)
1407 return PLLD_BASE_DSIB_MUX_MASK;
1408 else
1409 return 3 << 30;
1410}
1411
1412static inline u32 periph_clk_source_shift(struct clk *c)
1413{
1414 if (c->flags & MUX8)
1415 return 29;
1416 else if (c->flags & MUX_PWM)
1417 return 28;
1418 else if (c->flags & MUX_CLK_OUT)
1419 return c->u.periph.clk_num + 4;
1420 else if (c->flags & PLLD)
1421 return PLLD_BASE_DSIB_MUX_SHIFT;
1422 else
1423 return 30;
1424}
1425
1426static void tegra30_periph_clk_init(struct clk *c)
1427{
1428 u32 val = clk_readl(c->reg);
1429 const struct clk_mux_sel *mux = 0;
1430 const struct clk_mux_sel *sel;
1431 if (c->flags & MUX) {
1432 for (sel = c->inputs; sel->input != NULL; sel++) {
1433 if (((val & periph_clk_source_mask(c)) >>
1434 periph_clk_source_shift(c)) == sel->value)
1435 mux = sel;
1436 }
1437 BUG_ON(!mux);
1438
1439 c->parent = mux->input;
1440 } else {
1441 c->parent = c->inputs[0].input;
1442 }
1443
1444 if (c->flags & DIV_U71) {
1445 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1446 if ((c->flags & DIV_U71_UART) &&
1447 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1448 divu71 = 0;
1449 }
1450 if (c->flags & DIV_U71_IDLE) {
1451 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1452 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1453 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1454 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1455 clk_writel(val, c->reg);
1456 }
1457 c->div = divu71 + 2;
1458 c->mul = 2;
1459 } else if (c->flags & DIV_U16) {
1460 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1461 c->div = divu16 + 1;
1462 c->mul = 1;
1463 } else {
1464 c->div = 1;
1465 c->mul = 1;
1466 }
1467
1468 c->state = ON;
1469 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1470 c->state = OFF;
1471 if (!(c->flags & PERIPH_NO_RESET))
1472 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1473 c->state = OFF;
1474}
1475
1476static int tegra30_periph_clk_enable(struct clk *c)
1477{
1478 pr_debug("%s on clock %s\n", __func__, c->name);
1479
1480 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1481 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1482 return 0;
1483
1484 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
1485 if (!(c->flags & PERIPH_NO_RESET) &&
1486 !(c->flags & PERIPH_MANUAL_RESET)) {
1487 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
1488 PERIPH_CLK_TO_BIT(c)) {
1489 udelay(5); /* reset propagation delay */
1490 clk_writel(PERIPH_CLK_TO_BIT(c),
1491 PERIPH_CLK_TO_RST_CLR_REG(c));
1492 }
1493 }
1494 return 0;
1495}
1496
1497static void tegra30_periph_clk_disable(struct clk *c)
1498{
1499 unsigned long val;
1500 pr_debug("%s on clock %s\n", __func__, c->name);
1501
1502 if (c->refcnt)
1503 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1504
1505 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
1506 /* If peripheral is in the APB bus then read the APB bus to
1507 * flush the write operation in apb bus. This will avoid the
1508 * peripheral access after disabling clock*/
1509 if (c->flags & PERIPH_ON_APB)
1510 val = chipid_readl();
1511
1512 clk_writel_delay(
1513 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1514 }
1515}
1516
1517static void tegra30_periph_clk_reset(struct clk *c, bool assert)
1518{
1519 unsigned long val;
1520 pr_debug("%s %s on clock %s\n", __func__,
1521 assert ? "assert" : "deassert", c->name);
1522
1523 if (!(c->flags & PERIPH_NO_RESET)) {
1524 if (assert) {
1525 /* If peripheral is in the APB bus then read the APB
1526 * bus to flush the write operation in apb bus. This
1527 * will avoid the peripheral access after disabling
1528 * clock */
1529 if (c->flags & PERIPH_ON_APB)
1530 val = chipid_readl();
1531
1532 clk_writel(PERIPH_CLK_TO_BIT(c),
1533 PERIPH_CLK_TO_RST_SET_REG(c));
1534 } else
1535 clk_writel(PERIPH_CLK_TO_BIT(c),
1536 PERIPH_CLK_TO_RST_CLR_REG(c));
1537 }
1538}
1539
1540static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
1541{
1542 u32 val;
1543 const struct clk_mux_sel *sel;
1544 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1545
1546 if (!(c->flags & MUX))
1547 return (p == c->parent) ? 0 : (-EINVAL);
1548
1549 for (sel = c->inputs; sel->input != NULL; sel++) {
1550 if (sel->input == p) {
1551 val = clk_readl(c->reg);
1552 val &= ~periph_clk_source_mask(c);
1553 val |= (sel->value << periph_clk_source_shift(c));
1554
1555 if (c->refcnt)
1556 clk_enable(p);
1557
1558 clk_writel_delay(val, c->reg);
1559
1560 if (c->refcnt && c->parent)
1561 clk_disable(c->parent);
1562
1563 clk_reparent(c, p);
1564 return 0;
1565 }
1566 }
1567
1568 return -EINVAL;
1569}
1570
1571static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
1572{
1573 u32 val;
1574 int divider;
1575 unsigned long parent_rate = clk_get_rate(c->parent);
1576
1577 if (c->flags & DIV_U71) {
1578 divider = clk_div71_get_divider(
1579 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1580 if (divider >= 0) {
1581 val = clk_readl(c->reg);
1582 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1583 val |= divider;
1584 if (c->flags & DIV_U71_UART) {
1585 if (divider)
1586 val |= PERIPH_CLK_UART_DIV_ENB;
1587 else
1588 val &= ~PERIPH_CLK_UART_DIV_ENB;
1589 }
1590 clk_writel_delay(val, c->reg);
1591 c->div = divider + 2;
1592 c->mul = 2;
1593 return 0;
1594 }
1595 } else if (c->flags & DIV_U16) {
1596 divider = clk_div16_get_divider(parent_rate, rate);
1597 if (divider >= 0) {
1598 val = clk_readl(c->reg);
1599 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1600 val |= divider;
1601 clk_writel_delay(val, c->reg);
1602 c->div = divider + 1;
1603 c->mul = 1;
1604 return 0;
1605 }
1606 } else if (parent_rate <= rate) {
1607 c->div = 1;
1608 c->mul = 1;
1609 return 0;
1610 }
1611 return -EINVAL;
1612}
1613
1614static long tegra30_periph_clk_round_rate(struct clk *c,
1615 unsigned long rate)
1616{
1617 int divider;
1618 unsigned long parent_rate = clk_get_rate(c->parent);
1619 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1620
1621 if (c->flags & DIV_U71) {
1622 divider = clk_div71_get_divider(
1623 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1624 if (divider < 0)
1625 return divider;
1626
1627 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1628 } else if (c->flags & DIV_U16) {
1629 divider = clk_div16_get_divider(parent_rate, rate);
1630 if (divider < 0)
1631 return divider;
1632 return DIV_ROUND_UP(parent_rate, divider + 1);
1633 }
1634 return -EINVAL;
1635}
1636
1637static struct clk_ops tegra_periph_clk_ops = {
1638 .init = &tegra30_periph_clk_init,
1639 .enable = &tegra30_periph_clk_enable,
1640 .disable = &tegra30_periph_clk_disable,
1641 .set_parent = &tegra30_periph_clk_set_parent,
1642 .set_rate = &tegra30_periph_clk_set_rate,
1643 .round_rate = &tegra30_periph_clk_round_rate,
1644 .reset = &tegra30_periph_clk_reset,
1645};
1646
1647
1648/* Periph extended clock configuration ops */
1649static int
1650tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1651{
1652 if (p == TEGRA_CLK_VI_INP_SEL) {
1653 u32 val = clk_readl(c->reg);
1654 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
1655 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
1656 PERIPH_CLK_VI_SEL_EX_MASK;
1657 clk_writel(val, c->reg);
1658 return 0;
1659 }
1660 return -EINVAL;
1661}
1662
1663static struct clk_ops tegra_vi_clk_ops = {
1664 .init = &tegra30_periph_clk_init,
1665 .enable = &tegra30_periph_clk_enable,
1666 .disable = &tegra30_periph_clk_disable,
1667 .set_parent = &tegra30_periph_clk_set_parent,
1668 .set_rate = &tegra30_periph_clk_set_rate,
1669 .round_rate = &tegra30_periph_clk_round_rate,
1670 .clk_cfg_ex = &tegra30_vi_clk_cfg_ex,
1671 .reset = &tegra30_periph_clk_reset,
1672};
1673
1674static int
1675tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1676{
1677 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
1678 u32 val = clk_readl(c->reg);
1679 if (setting)
1680 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
1681 else
1682 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
1683 clk_writel(val, c->reg);
1684 return 0;
1685 }
1686 return -EINVAL;
1687}
1688
1689static struct clk_ops tegra_nand_clk_ops = {
1690 .init = &tegra30_periph_clk_init,
1691 .enable = &tegra30_periph_clk_enable,
1692 .disable = &tegra30_periph_clk_disable,
1693 .set_parent = &tegra30_periph_clk_set_parent,
1694 .set_rate = &tegra30_periph_clk_set_rate,
1695 .round_rate = &tegra30_periph_clk_round_rate,
1696 .clk_cfg_ex = &tegra30_nand_clk_cfg_ex,
1697 .reset = &tegra30_periph_clk_reset,
1698};
1699
1700
1701static int
1702tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1703{
1704 if (p == TEGRA_CLK_DTV_INVERT) {
1705 u32 val = clk_readl(c->reg);
1706 if (setting)
1707 val |= PERIPH_CLK_DTV_POLARITY_INV;
1708 else
1709 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
1710 clk_writel(val, c->reg);
1711 return 0;
1712 }
1713 return -EINVAL;
1714}
1715
1716static struct clk_ops tegra_dtv_clk_ops = {
1717 .init = &tegra30_periph_clk_init,
1718 .enable = &tegra30_periph_clk_enable,
1719 .disable = &tegra30_periph_clk_disable,
1720 .set_parent = &tegra30_periph_clk_set_parent,
1721 .set_rate = &tegra30_periph_clk_set_rate,
1722 .round_rate = &tegra30_periph_clk_round_rate,
1723 .clk_cfg_ex = &tegra30_dtv_clk_cfg_ex,
1724 .reset = &tegra30_periph_clk_reset,
1725};
1726
1727static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
1728{
1729 const struct clk_mux_sel *sel;
1730 struct clk *d = tegra_get_clock_by_name("pll_d");
1731
1732 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1733
1734 for (sel = c->inputs; sel->input != NULL; sel++) {
1735 if (sel->input == p) {
1736 if (c->refcnt)
1737 clk_enable(p);
1738
1739 /* The DSIB parent selection bit is in PLLD base
1740 register - can not do direct r-m-w, must be
1741 protected by PLLD lock */
1742 tegra_clk_cfg_ex(
1743 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
1744
1745 if (c->refcnt && c->parent)
1746 clk_disable(c->parent);
1747
1748 clk_reparent(c, p);
1749 return 0;
1750 }
1751 }
1752
1753 return -EINVAL;
1754}
1755
1756static struct clk_ops tegra_dsib_clk_ops = {
1757 .init = &tegra30_periph_clk_init,
1758 .enable = &tegra30_periph_clk_enable,
1759 .disable = &tegra30_periph_clk_disable,
1760 .set_parent = &tegra30_dsib_clk_set_parent,
1761 .set_rate = &tegra30_periph_clk_set_rate,
1762 .round_rate = &tegra30_periph_clk_round_rate,
1763 .reset = &tegra30_periph_clk_reset,
1764};
1765
1766/* pciex clock support only reset function */
1767static struct clk_ops tegra_pciex_clk_ops = {
1768 .reset = tegra30_periph_clk_reset,
1769};
1770
1771/* Output clock ops */
1772
1773static DEFINE_SPINLOCK(clk_out_lock);
1774
1775static void tegra30_clk_out_init(struct clk *c)
1776{
1777 const struct clk_mux_sel *mux = 0;
1778 const struct clk_mux_sel *sel;
1779 u32 val = pmc_readl(c->reg);
1780
1781 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
1782 c->mul = 1;
1783 c->div = 1;
1784
1785 for (sel = c->inputs; sel->input != NULL; sel++) {
1786 if (((val & periph_clk_source_mask(c)) >>
1787 periph_clk_source_shift(c)) == sel->value)
1788 mux = sel;
1789 }
1790 BUG_ON(!mux);
1791 c->parent = mux->input;
1792}
1793
1794static int tegra30_clk_out_enable(struct clk *c)
1795{
1796 u32 val;
1797 unsigned long flags;
1798
1799 pr_debug("%s on clock %s\n", __func__, c->name);
1800
1801 spin_lock_irqsave(&clk_out_lock, flags);
1802 val = pmc_readl(c->reg);
1803 val |= (0x1 << c->u.periph.clk_num);
1804 pmc_writel(val, c->reg);
1805 spin_unlock_irqrestore(&clk_out_lock, flags);
1806
1807 return 0;
1808}
1809
1810static void tegra30_clk_out_disable(struct clk *c)
1811{
1812 u32 val;
1813 unsigned long flags;
1814
1815 pr_debug("%s on clock %s\n", __func__, c->name);
1816
1817 spin_lock_irqsave(&clk_out_lock, flags);
1818 val = pmc_readl(c->reg);
1819 val &= ~(0x1 << c->u.periph.clk_num);
1820 pmc_writel(val, c->reg);
1821 spin_unlock_irqrestore(&clk_out_lock, flags);
1822}
1823
1824static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
1825{
1826 u32 val;
1827 unsigned long flags;
1828 const struct clk_mux_sel *sel;
1829
1830 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1831
1832 for (sel = c->inputs; sel->input != NULL; sel++) {
1833 if (sel->input == p) {
1834 if (c->refcnt)
1835 clk_enable(p);
1836
1837 spin_lock_irqsave(&clk_out_lock, flags);
1838 val = pmc_readl(c->reg);
1839 val &= ~periph_clk_source_mask(c);
1840 val |= (sel->value << periph_clk_source_shift(c));
1841 pmc_writel(val, c->reg);
1842 spin_unlock_irqrestore(&clk_out_lock, flags);
1843
1844 if (c->refcnt && c->parent)
1845 clk_disable(c->parent);
1846
1847 clk_reparent(c, p);
1848 return 0;
1849 }
1850 }
1851 return -EINVAL;
1852}
1853
1854static struct clk_ops tegra_clk_out_ops = {
1855 .init = &tegra30_clk_out_init,
1856 .enable = &tegra30_clk_out_enable,
1857 .disable = &tegra30_clk_out_disable,
1858 .set_parent = &tegra30_clk_out_set_parent,
1859};
1860
1861
1862/* Clock doubler ops */
1863static void tegra30_clk_double_init(struct clk *c)
1864{
1865 u32 val = clk_readl(c->reg);
1866 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
1867 c->div = 1;
1868 c->state = ON;
1869 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1870 c->state = OFF;
1871};
1872
1873static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
1874{
1875 u32 val;
1876 unsigned long parent_rate = clk_get_rate(c->parent);
1877 if (rate == parent_rate) {
1878 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
1879 clk_writel(val, c->reg);
1880 c->mul = 1;
1881 c->div = 1;
1882 return 0;
1883 } else if (rate == 2 * parent_rate) {
1884 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
1885 clk_writel(val, c->reg);
1886 c->mul = 2;
1887 c->div = 1;
1888 return 0;
1889 }
1890 return -EINVAL;
1891}
1892
1893static struct clk_ops tegra_clk_double_ops = {
1894 .init = &tegra30_clk_double_init,
1895 .enable = &tegra30_periph_clk_enable,
1896 .disable = &tegra30_periph_clk_disable,
1897 .set_rate = &tegra30_clk_double_set_rate,
1898};
1899
1900/* Audio sync clock ops */
1901static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
1902{
1903 c->rate = rate;
1904 return 0;
1905}
1906
1907static struct clk_ops tegra_sync_source_ops = {
1908 .set_rate = &tegra30_sync_source_set_rate,
1909};
1910
1911static void tegra30_audio_sync_clk_init(struct clk *c)
1912{
1913 int source;
1914 const struct clk_mux_sel *sel;
1915 u32 val = clk_readl(c->reg);
1916 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
1917 source = val & AUDIO_SYNC_SOURCE_MASK;
1918 for (sel = c->inputs; sel->input != NULL; sel++)
1919 if (sel->value == source)
1920 break;
1921 BUG_ON(sel->input == NULL);
1922 c->parent = sel->input;
1923}
1924
1925static int tegra30_audio_sync_clk_enable(struct clk *c)
1926{
1927 u32 val = clk_readl(c->reg);
1928 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
1929 return 0;
1930}
1931
1932static void tegra30_audio_sync_clk_disable(struct clk *c)
1933{
1934 u32 val = clk_readl(c->reg);
1935 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
1936}
1937
1938static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1939{
1940 u32 val;
1941 const struct clk_mux_sel *sel;
1942 for (sel = c->inputs; sel->input != NULL; sel++) {
1943 if (sel->input == p) {
1944 val = clk_readl(c->reg);
1945 val &= ~AUDIO_SYNC_SOURCE_MASK;
1946 val |= sel->value;
1947
1948 if (c->refcnt)
1949 clk_enable(p);
1950
1951 clk_writel(val, c->reg);
1952
1953 if (c->refcnt && c->parent)
1954 clk_disable(c->parent);
1955
1956 clk_reparent(c, p);
1957 return 0;
1958 }
1959 }
1960
1961 return -EINVAL;
1962}
1963
1964static struct clk_ops tegra_audio_sync_clk_ops = {
1965 .init = tegra30_audio_sync_clk_init,
1966 .enable = tegra30_audio_sync_clk_enable,
1967 .disable = tegra30_audio_sync_clk_disable,
1968 .set_parent = tegra30_audio_sync_clk_set_parent,
1969};
1970
1971/* cml0 (pcie), and cml1 (sata) clock ops */
1972static void tegra30_cml_clk_init(struct clk *c)
1973{
1974 u32 val = clk_readl(c->reg);
1975 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
1976}
1977
1978static int tegra30_cml_clk_enable(struct clk *c)
1979{
1980 u32 val = clk_readl(c->reg);
1981 val |= (0x1 << c->u.periph.clk_num);
1982 clk_writel(val, c->reg);
1983 return 0;
1984}
1985
1986static void tegra30_cml_clk_disable(struct clk *c)
1987{
1988 u32 val = clk_readl(c->reg);
1989 val &= ~(0x1 << c->u.periph.clk_num);
1990 clk_writel(val, c->reg);
1991}
1992
1993static struct clk_ops tegra_cml_clk_ops = {
1994 .init = &tegra30_cml_clk_init,
1995 .enable = &tegra30_cml_clk_enable,
1996 .disable = &tegra30_cml_clk_disable,
1997};
1998
1999/* Clock definitions */
2000static struct clk tegra_clk_32k = {
2001 .name = "clk_32k",
2002 .rate = 32768,
2003 .ops = NULL,
2004 .max_rate = 32768,
2005};
2006
2007static struct clk tegra_clk_m = {
2008 .name = "clk_m",
2009 .flags = ENABLE_ON_INIT,
2010 .ops = &tegra_clk_m_ops,
2011 .reg = 0x1fc,
2012 .reg_shift = 28,
2013 .max_rate = 48000000,
2014};
2015
2016static struct clk tegra_clk_m_div2 = {
2017 .name = "clk_m_div2",
2018 .ops = &tegra_clk_m_div_ops,
2019 .parent = &tegra_clk_m,
2020 .mul = 1,
2021 .div = 2,
2022 .state = ON,
2023 .max_rate = 24000000,
2024};
2025
2026static struct clk tegra_clk_m_div4 = {
2027 .name = "clk_m_div4",
2028 .ops = &tegra_clk_m_div_ops,
2029 .parent = &tegra_clk_m,
2030 .mul = 1,
2031 .div = 4,
2032 .state = ON,
2033 .max_rate = 12000000,
2034};
2035
2036static struct clk tegra_pll_ref = {
2037 .name = "pll_ref",
2038 .flags = ENABLE_ON_INIT,
2039 .ops = &tegra_pll_ref_ops,
2040 .parent = &tegra_clk_m,
2041 .max_rate = 26000000,
2042};
2043
2044static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
2045 { 12000000, 1040000000, 520, 6, 1, 8},
2046 { 13000000, 1040000000, 480, 6, 1, 8},
2047 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
2048 { 19200000, 1040000000, 325, 6, 1, 6},
2049 { 26000000, 1040000000, 520, 13, 1, 8},
2050
2051 { 12000000, 832000000, 416, 6, 1, 8},
2052 { 13000000, 832000000, 832, 13, 1, 8},
2053 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
2054 { 19200000, 832000000, 260, 6, 1, 8},
2055 { 26000000, 832000000, 416, 13, 1, 8},
2056
2057 { 12000000, 624000000, 624, 12, 1, 8},
2058 { 13000000, 624000000, 624, 13, 1, 8},
2059 { 16800000, 600000000, 520, 14, 1, 8},
2060 { 19200000, 624000000, 520, 16, 1, 8},
2061 { 26000000, 624000000, 624, 26, 1, 8},
2062
2063 { 12000000, 600000000, 600, 12, 1, 8},
2064 { 13000000, 600000000, 600, 13, 1, 8},
2065 { 16800000, 600000000, 500, 14, 1, 8},
2066 { 19200000, 600000000, 375, 12, 1, 6},
2067 { 26000000, 600000000, 600, 26, 1, 8},
2068
2069 { 12000000, 520000000, 520, 12, 1, 8},
2070 { 13000000, 520000000, 520, 13, 1, 8},
2071 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
2072 { 19200000, 520000000, 325, 12, 1, 6},
2073 { 26000000, 520000000, 520, 26, 1, 8},
2074
2075 { 12000000, 416000000, 416, 12, 1, 8},
2076 { 13000000, 416000000, 416, 13, 1, 8},
2077 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
2078 { 19200000, 416000000, 260, 12, 1, 6},
2079 { 26000000, 416000000, 416, 26, 1, 8},
2080 { 0, 0, 0, 0, 0, 0 },
2081};
2082
2083static struct clk tegra_pll_c = {
2084 .name = "pll_c",
2085 .flags = PLL_HAS_CPCON,
2086 .ops = &tegra_pll_ops,
2087 .reg = 0x80,
2088 .parent = &tegra_pll_ref,
2089 .max_rate = 1400000000,
2090 .u.pll = {
2091 .input_min = 2000000,
2092 .input_max = 31000000,
2093 .cf_min = 1000000,
2094 .cf_max = 6000000,
2095 .vco_min = 20000000,
2096 .vco_max = 1400000000,
2097 .freq_table = tegra_pll_c_freq_table,
2098 .lock_delay = 300,
2099 },
2100};
2101
2102static struct clk tegra_pll_c_out1 = {
2103 .name = "pll_c_out1",
2104 .ops = &tegra_pll_div_ops,
2105 .flags = DIV_U71,
2106 .parent = &tegra_pll_c,
2107 .reg = 0x84,
2108 .reg_shift = 0,
2109 .max_rate = 700000000,
2110};
2111
2112static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
2113 { 12000000, 666000000, 666, 12, 1, 8},
2114 { 13000000, 666000000, 666, 13, 1, 8},
2115 { 16800000, 666000000, 555, 14, 1, 8},
2116 { 19200000, 666000000, 555, 16, 1, 8},
2117 { 26000000, 666000000, 666, 26, 1, 8},
2118 { 12000000, 600000000, 600, 12, 1, 8},
2119 { 13000000, 600000000, 600, 13, 1, 8},
2120 { 16800000, 600000000, 500, 14, 1, 8},
2121 { 19200000, 600000000, 375, 12, 1, 6},
2122 { 26000000, 600000000, 600, 26, 1, 8},
2123 { 0, 0, 0, 0, 0, 0 },
2124};
2125
2126static struct clk tegra_pll_m = {
2127 .name = "pll_m",
2128 .flags = PLL_HAS_CPCON | PLLM,
2129 .ops = &tegra_pll_ops,
2130 .reg = 0x90,
2131 .parent = &tegra_pll_ref,
2132 .max_rate = 800000000,
2133 .u.pll = {
2134 .input_min = 2000000,
2135 .input_max = 31000000,
2136 .cf_min = 1000000,
2137 .cf_max = 6000000,
2138 .vco_min = 20000000,
2139 .vco_max = 1200000000,
2140 .freq_table = tegra_pll_m_freq_table,
2141 .lock_delay = 300,
2142 },
2143};
2144
2145static struct clk tegra_pll_m_out1 = {
2146 .name = "pll_m_out1",
2147 .ops = &tegra_pll_div_ops,
2148 .flags = DIV_U71,
2149 .parent = &tegra_pll_m,
2150 .reg = 0x94,
2151 .reg_shift = 0,
2152 .max_rate = 600000000,
2153};
2154
2155static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
2156 { 12000000, 216000000, 432, 12, 2, 8},
2157 { 13000000, 216000000, 432, 13, 2, 8},
2158 { 16800000, 216000000, 360, 14, 2, 8},
2159 { 19200000, 216000000, 360, 16, 2, 8},
2160 { 26000000, 216000000, 432, 26, 2, 8},
2161 { 0, 0, 0, 0, 0, 0 },
2162};
2163
2164static struct clk tegra_pll_p = {
2165 .name = "pll_p",
2166 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
2167 .ops = &tegra_pll_ops,
2168 .reg = 0xa0,
2169 .parent = &tegra_pll_ref,
2170 .max_rate = 432000000,
2171 .u.pll = {
2172 .input_min = 2000000,
2173 .input_max = 31000000,
2174 .cf_min = 1000000,
2175 .cf_max = 6000000,
2176 .vco_min = 20000000,
2177 .vco_max = 1400000000,
2178 .freq_table = tegra_pll_p_freq_table,
2179 .lock_delay = 300,
2180 .fixed_rate = 408000000,
2181 },
2182};
2183
2184static struct clk tegra_pll_p_out1 = {
2185 .name = "pll_p_out1",
2186 .ops = &tegra_pll_div_ops,
2187 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2188 .parent = &tegra_pll_p,
2189 .reg = 0xa4,
2190 .reg_shift = 0,
2191 .max_rate = 432000000,
2192};
2193
2194static struct clk tegra_pll_p_out2 = {
2195 .name = "pll_p_out2",
2196 .ops = &tegra_pll_div_ops,
2197 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2198 .parent = &tegra_pll_p,
2199 .reg = 0xa4,
2200 .reg_shift = 16,
2201 .max_rate = 432000000,
2202};
2203
2204static struct clk tegra_pll_p_out3 = {
2205 .name = "pll_p_out3",
2206 .ops = &tegra_pll_div_ops,
2207 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2208 .parent = &tegra_pll_p,
2209 .reg = 0xa8,
2210 .reg_shift = 0,
2211 .max_rate = 432000000,
2212};
2213
2214static struct clk tegra_pll_p_out4 = {
2215 .name = "pll_p_out4",
2216 .ops = &tegra_pll_div_ops,
2217 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2218 .parent = &tegra_pll_p,
2219 .reg = 0xa8,
2220 .reg_shift = 16,
2221 .max_rate = 432000000,
2222};
2223
2224static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
2225 { 9600000, 564480000, 294, 5, 1, 4},
2226 { 9600000, 552960000, 288, 5, 1, 4},
2227 { 9600000, 24000000, 5, 2, 1, 1},
2228
2229 { 28800000, 56448000, 49, 25, 1, 1},
2230 { 28800000, 73728000, 64, 25, 1, 1},
2231 { 28800000, 24000000, 5, 6, 1, 1},
2232 { 0, 0, 0, 0, 0, 0 },
2233};
2234
2235static struct clk tegra_pll_a = {
2236 .name = "pll_a",
2237 .flags = PLL_HAS_CPCON,
2238 .ops = &tegra_pll_ops,
2239 .reg = 0xb0,
2240 .parent = &tegra_pll_p_out1,
2241 .max_rate = 700000000,
2242 .u.pll = {
2243 .input_min = 2000000,
2244 .input_max = 31000000,
2245 .cf_min = 1000000,
2246 .cf_max = 6000000,
2247 .vco_min = 20000000,
2248 .vco_max = 1400000000,
2249 .freq_table = tegra_pll_a_freq_table,
2250 .lock_delay = 300,
2251 },
2252};
2253
2254static struct clk tegra_pll_a_out0 = {
2255 .name = "pll_a_out0",
2256 .ops = &tegra_pll_div_ops,
2257 .flags = DIV_U71,
2258 .parent = &tegra_pll_a,
2259 .reg = 0xb4,
2260 .reg_shift = 0,
2261 .max_rate = 100000000,
2262};
2263
2264static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
2265 { 12000000, 216000000, 216, 12, 1, 4},
2266 { 13000000, 216000000, 216, 13, 1, 4},
2267 { 16800000, 216000000, 180, 14, 1, 4},
2268 { 19200000, 216000000, 180, 16, 1, 4},
2269 { 26000000, 216000000, 216, 26, 1, 4},
2270
2271 { 12000000, 594000000, 594, 12, 1, 8},
2272 { 13000000, 594000000, 594, 13, 1, 8},
2273 { 16800000, 594000000, 495, 14, 1, 8},
2274 { 19200000, 594000000, 495, 16, 1, 8},
2275 { 26000000, 594000000, 594, 26, 1, 8},
2276
2277 { 12000000, 1000000000, 1000, 12, 1, 12},
2278 { 13000000, 1000000000, 1000, 13, 1, 12},
2279 { 19200000, 1000000000, 625, 12, 1, 8},
2280 { 26000000, 1000000000, 1000, 26, 1, 12},
2281
2282 { 0, 0, 0, 0, 0, 0 },
2283};
2284
2285static struct clk tegra_pll_d = {
2286 .name = "pll_d",
2287 .flags = PLL_HAS_CPCON | PLLD,
2288 .ops = &tegra_plld_ops,
2289 .reg = 0xd0,
2290 .parent = &tegra_pll_ref,
2291 .max_rate = 1000000000,
2292 .u.pll = {
2293 .input_min = 2000000,
2294 .input_max = 40000000,
2295 .cf_min = 1000000,
2296 .cf_max = 6000000,
2297 .vco_min = 40000000,
2298 .vco_max = 1000000000,
2299 .freq_table = tegra_pll_d_freq_table,
2300 .lock_delay = 1000,
2301 },
2302};
2303
2304static struct clk tegra_pll_d_out0 = {
2305 .name = "pll_d_out0",
2306 .ops = &tegra_pll_div_ops,
2307 .flags = DIV_2 | PLLD,
2308 .parent = &tegra_pll_d,
2309 .max_rate = 500000000,
2310};
2311
2312static struct clk tegra_pll_d2 = {
2313 .name = "pll_d2",
2314 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
2315 .ops = &tegra_plld_ops,
2316 .reg = 0x4b8,
2317 .parent = &tegra_pll_ref,
2318 .max_rate = 1000000000,
2319 .u.pll = {
2320 .input_min = 2000000,
2321 .input_max = 40000000,
2322 .cf_min = 1000000,
2323 .cf_max = 6000000,
2324 .vco_min = 40000000,
2325 .vco_max = 1000000000,
2326 .freq_table = tegra_pll_d_freq_table,
2327 .lock_delay = 1000,
2328 },
2329};
2330
2331static struct clk tegra_pll_d2_out0 = {
2332 .name = "pll_d2_out0",
2333 .ops = &tegra_pll_div_ops,
2334 .flags = DIV_2 | PLLD,
2335 .parent = &tegra_pll_d2,
2336 .max_rate = 500000000,
2337};
2338
2339static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
2340 { 12000000, 480000000, 960, 12, 2, 12},
2341 { 13000000, 480000000, 960, 13, 2, 12},
2342 { 16800000, 480000000, 400, 7, 2, 5},
2343 { 19200000, 480000000, 200, 4, 2, 3},
2344 { 26000000, 480000000, 960, 26, 2, 12},
2345 { 0, 0, 0, 0, 0, 0 },
2346};
2347
2348static struct clk tegra_pll_u = {
2349 .name = "pll_u",
2350 .flags = PLL_HAS_CPCON | PLLU,
2351 .ops = &tegra_pll_ops,
2352 .reg = 0xc0,
2353 .parent = &tegra_pll_ref,
2354 .max_rate = 480000000,
2355 .u.pll = {
2356 .input_min = 2000000,
2357 .input_max = 40000000,
2358 .cf_min = 1000000,
2359 .cf_max = 6000000,
2360 .vco_min = 480000000,
2361 .vco_max = 960000000,
2362 .freq_table = tegra_pll_u_freq_table,
2363 .lock_delay = 1000,
2364 },
2365};
2366
2367static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
2368 /* 1.7 GHz */
2369 { 12000000, 1700000000, 850, 6, 1, 8},
2370 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
2371 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
2372 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
2373 { 26000000, 1700000000, 850, 13, 1, 8},
2374
2375 /* 1.6 GHz */
2376 { 12000000, 1600000000, 800, 6, 1, 8},
2377 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
2378 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
2379 { 19200000, 1600000000, 500, 6, 1, 8},
2380 { 26000000, 1600000000, 800, 13, 1, 8},
2381
2382 /* 1.5 GHz */
2383 { 12000000, 1500000000, 750, 6, 1, 8},
2384 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
2385 { 16800000, 1500000000, 625, 7, 1, 8},
2386 { 19200000, 1500000000, 625, 8, 1, 8},
2387 { 26000000, 1500000000, 750, 13, 1, 8},
2388
2389 /* 1.4 GHz */
2390 { 12000000, 1400000000, 700, 6, 1, 8},
2391 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
2392 { 16800000, 1400000000, 1000, 12, 1, 8},
2393 { 19200000, 1400000000, 875, 12, 1, 8},
2394 { 26000000, 1400000000, 700, 13, 1, 8},
2395
2396 /* 1.3 GHz */
2397 { 12000000, 1300000000, 975, 9, 1, 8},
2398 { 13000000, 1300000000, 1000, 10, 1, 8},
2399 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
2400 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
2401 { 26000000, 1300000000, 650, 13, 1, 8},
2402
2403 /* 1.2 GHz */
2404 { 12000000, 1200000000, 1000, 10, 1, 8},
2405 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
2406 { 16800000, 1200000000, 1000, 14, 1, 8},
2407 { 19200000, 1200000000, 1000, 16, 1, 8},
2408 { 26000000, 1200000000, 600, 13, 1, 8},
2409
2410 /* 1.1 GHz */
2411 { 12000000, 1100000000, 825, 9, 1, 8},
2412 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
2413 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
2414 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
2415 { 26000000, 1100000000, 550, 13, 1, 8},
2416
2417 /* 1 GHz */
2418 { 12000000, 1000000000, 1000, 12, 1, 8},
2419 { 13000000, 1000000000, 1000, 13, 1, 8},
2420 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
2421 { 19200000, 1000000000, 625, 12, 1, 8},
2422 { 26000000, 1000000000, 1000, 26, 1, 8},
2423
2424 { 0, 0, 0, 0, 0, 0 },
2425};
2426
2427static struct clk tegra_pll_x = {
2428 .name = "pll_x",
2429 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
2430 .ops = &tegra_pll_ops,
2431 .reg = 0xe0,
2432 .parent = &tegra_pll_ref,
2433 .max_rate = 1700000000,
2434 .u.pll = {
2435 .input_min = 2000000,
2436 .input_max = 31000000,
2437 .cf_min = 1000000,
2438 .cf_max = 6000000,
2439 .vco_min = 20000000,
2440 .vco_max = 1700000000,
2441 .freq_table = tegra_pll_x_freq_table,
2442 .lock_delay = 300,
2443 },
2444};
2445
2446static struct clk tegra_pll_x_out0 = {
2447 .name = "pll_x_out0",
2448 .ops = &tegra_pll_div_ops,
2449 .flags = DIV_2 | PLLX,
2450 .parent = &tegra_pll_x,
2451 .max_rate = 850000000,
2452};
2453
2454
2455static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
2456 /* PLLE special case: use cpcon field to store cml divider value */
2457 { 12000000, 100000000, 150, 1, 18, 11},
2458 { 216000000, 100000000, 200, 18, 24, 13},
2459 { 0, 0, 0, 0, 0, 0 },
2460};
2461
2462static struct clk tegra_pll_e = {
2463 .name = "pll_e",
2464 .flags = PLL_ALT_MISC_REG,
2465 .ops = &tegra_plle_ops,
2466 .reg = 0xe8,
2467 .max_rate = 100000000,
2468 .u.pll = {
2469 .input_min = 12000000,
2470 .input_max = 216000000,
2471 .cf_min = 12000000,
2472 .cf_max = 12000000,
2473 .vco_min = 1200000000,
2474 .vco_max = 2400000000U,
2475 .freq_table = tegra_pll_e_freq_table,
2476 .lock_delay = 300,
2477 .fixed_rate = 100000000,
2478 },
2479};
2480
2481static struct clk tegra_cml0_clk = {
2482 .name = "cml0",
2483 .parent = &tegra_pll_e,
2484 .ops = &tegra_cml_clk_ops,
2485 .reg = PLLE_AUX,
2486 .max_rate = 100000000,
2487 .u.periph = {
2488 .clk_num = 0,
2489 },
2490};
2491
2492static struct clk tegra_cml1_clk = {
2493 .name = "cml1",
2494 .parent = &tegra_pll_e,
2495 .ops = &tegra_cml_clk_ops,
2496 .reg = PLLE_AUX,
2497 .max_rate = 100000000,
2498 .u.periph = {
2499 .clk_num = 1,
2500 },
2501};
2502
2503static struct clk tegra_pciex_clk = {
2504 .name = "pciex",
2505 .parent = &tegra_pll_e,
2506 .ops = &tegra_pciex_clk_ops,
2507 .max_rate = 100000000,
2508 .u.periph = {
2509 .clk_num = 74,
2510 },
2511};
2512
2513/* Audio sync clocks */
2514#define SYNC_SOURCE(_id) \
2515 { \
2516 .name = #_id "_sync", \
2517 .rate = 24000000, \
2518 .max_rate = 24000000, \
2519 .ops = &tegra_sync_source_ops \
2520 }
2521static struct clk tegra_sync_source_list[] = {
2522 SYNC_SOURCE(spdif_in),
2523 SYNC_SOURCE(i2s0),
2524 SYNC_SOURCE(i2s1),
2525 SYNC_SOURCE(i2s2),
2526 SYNC_SOURCE(i2s3),
2527 SYNC_SOURCE(i2s4),
2528 SYNC_SOURCE(vimclk),
2529};
2530
2531static struct clk_mux_sel mux_audio_sync_clk[] = {
2532 { .input = &tegra_sync_source_list[0], .value = 0},
2533 { .input = &tegra_sync_source_list[1], .value = 1},
2534 { .input = &tegra_sync_source_list[2], .value = 2},
2535 { .input = &tegra_sync_source_list[3], .value = 3},
2536 { .input = &tegra_sync_source_list[4], .value = 4},
2537 { .input = &tegra_sync_source_list[5], .value = 5},
2538 { .input = &tegra_pll_a_out0, .value = 6},
2539 { .input = &tegra_sync_source_list[6], .value = 7},
2540 { 0, 0 }
2541};
2542
2543#define AUDIO_SYNC_CLK(_id, _index) \
2544 { \
2545 .name = #_id, \
2546 .inputs = mux_audio_sync_clk, \
2547 .reg = 0x4A0 + (_index) * 4, \
2548 .max_rate = 24000000, \
2549 .ops = &tegra_audio_sync_clk_ops \
2550 }
2551static struct clk tegra_clk_audio_list[] = {
2552 AUDIO_SYNC_CLK(audio0, 0),
2553 AUDIO_SYNC_CLK(audio1, 1),
2554 AUDIO_SYNC_CLK(audio2, 2),
2555 AUDIO_SYNC_CLK(audio3, 3),
2556 AUDIO_SYNC_CLK(audio4, 4),
2557 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
2558};
2559
2560#define AUDIO_SYNC_2X_CLK(_id, _index) \
2561 { \
2562 .name = #_id "_2x", \
2563 .flags = PERIPH_NO_RESET, \
2564 .max_rate = 48000000, \
2565 .ops = &tegra_clk_double_ops, \
2566 .reg = 0x49C, \
2567 .reg_shift = 24 + (_index), \
2568 .parent = &tegra_clk_audio_list[(_index)], \
2569 .u.periph = { \
2570 .clk_num = 113 + (_index), \
2571 }, \
2572 }
2573static struct clk tegra_clk_audio_2x_list[] = {
2574 AUDIO_SYNC_2X_CLK(audio0, 0),
2575 AUDIO_SYNC_2X_CLK(audio1, 1),
2576 AUDIO_SYNC_2X_CLK(audio2, 2),
2577 AUDIO_SYNC_2X_CLK(audio3, 3),
2578 AUDIO_SYNC_2X_CLK(audio4, 4),
2579 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
2580};
2581
2582#define MUX_I2S_SPDIF(_id, _index) \
2583static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
2584 {.input = &tegra_pll_a_out0, .value = 0}, \
2585 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
2586 {.input = &tegra_pll_p, .value = 2}, \
2587 {.input = &tegra_clk_m, .value = 3}, \
2588 { 0, 0}, \
2589}
2590MUX_I2S_SPDIF(audio0, 0);
2591MUX_I2S_SPDIF(audio1, 1);
2592MUX_I2S_SPDIF(audio2, 2);
2593MUX_I2S_SPDIF(audio3, 3);
2594MUX_I2S_SPDIF(audio4, 4);
2595MUX_I2S_SPDIF(audio, 5); /* SPDIF */
2596
2597/* External clock outputs (through PMC) */
2598#define MUX_EXTERN_OUT(_id) \
2599static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
2600 {.input = &tegra_clk_m, .value = 0}, \
2601 {.input = &tegra_clk_m_div2, .value = 1}, \
2602 {.input = &tegra_clk_m_div4, .value = 2}, \
2603 {.input = NULL, .value = 3}, /* placeholder */ \
2604 { 0, 0}, \
2605}
2606MUX_EXTERN_OUT(1);
2607MUX_EXTERN_OUT(2);
2608MUX_EXTERN_OUT(3);
2609
2610static struct clk_mux_sel *mux_extern_out_list[] = {
2611 mux_clkm_clkm2_clkm4_extern1,
2612 mux_clkm_clkm2_clkm4_extern2,
2613 mux_clkm_clkm2_clkm4_extern3,
2614};
2615
2616#define CLK_OUT_CLK(_id) \
2617 { \
2618 .name = "clk_out_" #_id, \
2619 .lookup = { \
2620 .dev_id = "clk_out_" #_id, \
2621 .con_id = "extern" #_id, \
2622 }, \
2623 .ops = &tegra_clk_out_ops, \
2624 .reg = 0x1a8, \
2625 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
2626 .flags = MUX_CLK_OUT, \
2627 .max_rate = 216000000, \
2628 .u.periph = { \
2629 .clk_num = (_id - 1) * 8 + 2, \
2630 }, \
2631 }
2632static struct clk tegra_clk_out_list[] = {
2633 CLK_OUT_CLK(1),
2634 CLK_OUT_CLK(2),
2635 CLK_OUT_CLK(3),
2636};
2637
2638/* called after peripheral external clocks are initialized */
2639static void init_clk_out_mux(void)
2640{
2641 int i;
2642 struct clk *c;
2643
2644 /* output clock con_id is the name of peripheral
2645 external clock connected to input 3 of the output mux */
2646 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
2647 c = tegra_get_clock_by_name(
2648 tegra_clk_out_list[i].lookup.con_id);
2649 if (!c)
2650 pr_err("%s: could not find clk %s\n", __func__,
2651 tegra_clk_out_list[i].lookup.con_id);
2652 mux_extern_out_list[i][3].input = c;
2653 }
2654}
2655
2656/* Peripheral muxes */
2657static struct clk_mux_sel mux_sclk[] = {
2658 { .input = &tegra_clk_m, .value = 0},
2659 { .input = &tegra_pll_c_out1, .value = 1},
2660 { .input = &tegra_pll_p_out4, .value = 2},
2661 { .input = &tegra_pll_p_out3, .value = 3},
2662 { .input = &tegra_pll_p_out2, .value = 4},
2663 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
2664 { .input = &tegra_clk_32k, .value = 6},
2665 { .input = &tegra_pll_m_out1, .value = 7},
2666 { 0, 0},
2667};
2668
2669static struct clk tegra_clk_sclk = {
2670 .name = "sclk",
2671 .inputs = mux_sclk,
2672 .reg = 0x28,
2673 .ops = &tegra_super_ops,
2674 .max_rate = 334000000,
2675 .min_rate = 40000000,
2676};
2677
2678static struct clk tegra_clk_blink = {
2679 .name = "blink",
2680 .parent = &tegra_clk_32k,
2681 .reg = 0x40,
2682 .ops = &tegra_blink_clk_ops,
2683 .max_rate = 32768,
2684};
2685
2686static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2687 { .input = &tegra_pll_m, .value = 0},
2688 { .input = &tegra_pll_c, .value = 1},
2689 { .input = &tegra_pll_p, .value = 2},
2690 { .input = &tegra_pll_a_out0, .value = 3},
2691 { 0, 0},
2692};
2693
2694static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2695 { .input = &tegra_pll_p, .value = 0},
2696 { .input = &tegra_pll_c, .value = 1},
2697 { .input = &tegra_pll_m, .value = 2},
2698 { .input = &tegra_clk_m, .value = 3},
2699 { 0, 0},
2700};
2701
2702static struct clk_mux_sel mux_pllp_clkm[] = {
2703 { .input = &tegra_pll_p, .value = 0},
2704 { .input = &tegra_clk_m, .value = 3},
2705 { 0, 0},
2706};
2707
2708static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2709 {.input = &tegra_pll_p, .value = 0},
2710 {.input = &tegra_pll_d_out0, .value = 1},
2711 {.input = &tegra_pll_c, .value = 2},
2712 {.input = &tegra_clk_m, .value = 3},
2713 { 0, 0},
2714};
2715
2716static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
2717 {.input = &tegra_pll_p, .value = 0},
2718 {.input = &tegra_pll_m, .value = 1},
2719 {.input = &tegra_pll_d_out0, .value = 2},
2720 {.input = &tegra_pll_a_out0, .value = 3},
2721 {.input = &tegra_pll_c, .value = 4},
2722 {.input = &tegra_pll_d2_out0, .value = 5},
2723 {.input = &tegra_clk_m, .value = 6},
2724 { 0, 0},
2725};
2726
2727static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
2728 { .input = &tegra_pll_a_out0, .value = 0},
2729 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
2730 { .input = &tegra_pll_p, .value = 2},
2731 { .input = &tegra_clk_m, .value = 3},
2732 { 0, 0},
2733};
2734
2735static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
2736 {.input = &tegra_pll_p, .value = 0},
2737 {.input = &tegra_pll_c, .value = 1},
2738 {.input = &tegra_clk_32k, .value = 2},
2739 {.input = &tegra_clk_m, .value = 3},
2740 { 0, 0},
2741};
2742
2743static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
2744 {.input = &tegra_pll_p, .value = 0},
2745 {.input = &tegra_pll_c, .value = 1},
2746 {.input = &tegra_clk_m, .value = 2},
2747 {.input = &tegra_clk_32k, .value = 3},
2748 { 0, 0},
2749};
2750
2751static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2752 {.input = &tegra_pll_p, .value = 0},
2753 {.input = &tegra_pll_c, .value = 1},
2754 {.input = &tegra_pll_m, .value = 2},
2755 { 0, 0},
2756};
2757
2758static struct clk_mux_sel mux_clk_m[] = {
2759 { .input = &tegra_clk_m, .value = 0},
2760 { 0, 0},
2761};
2762
2763static struct clk_mux_sel mux_pllp_out3[] = {
2764 { .input = &tegra_pll_p_out3, .value = 0},
2765 { 0, 0},
2766};
2767
2768static struct clk_mux_sel mux_plld_out0[] = {
2769 { .input = &tegra_pll_d_out0, .value = 0},
2770 { 0, 0},
2771};
2772
2773static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
2774 { .input = &tegra_pll_d_out0, .value = 0},
2775 { .input = &tegra_pll_d2_out0, .value = 1},
2776 { 0, 0},
2777};
2778
2779static struct clk_mux_sel mux_clk_32k[] = {
2780 { .input = &tegra_clk_32k, .value = 0},
2781 { 0, 0},
2782};
2783
2784static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
2785 { .input = &tegra_pll_a_out0, .value = 0},
2786 { .input = &tegra_clk_32k, .value = 1},
2787 { .input = &tegra_pll_p, .value = 2},
2788 { .input = &tegra_clk_m, .value = 3},
2789 { .input = &tegra_pll_e, .value = 4},
2790 { 0, 0},
2791};
2792
2793static struct clk_mux_sel mux_cclk_g[] = {
2794 { .input = &tegra_clk_m, .value = 0},
2795 { .input = &tegra_pll_c, .value = 1},
2796 { .input = &tegra_clk_32k, .value = 2},
2797 { .input = &tegra_pll_m, .value = 3},
2798 { .input = &tegra_pll_p, .value = 4},
2799 { .input = &tegra_pll_p_out4, .value = 5},
2800 { .input = &tegra_pll_p_out3, .value = 6},
2801 { .input = &tegra_pll_x, .value = 8},
2802 { 0, 0},
2803};
2804
2805static struct clk tegra_clk_cclk_g = {
2806 .name = "cclk_g",
2807 .flags = DIV_U71 | DIV_U71_INT,
2808 .inputs = mux_cclk_g,
2809 .reg = 0x368,
2810 .ops = &tegra_super_ops,
2811 .max_rate = 1700000000,
2812};
2813
2814static struct clk tegra30_clk_twd = {
2815 .parent = &tegra_clk_cclk_g,
2816 .name = "twd",
2817 .ops = &tegra30_twd_ops,
2818 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
2819 .mul = 1,
2820 .div = 2,
2821};
2822
2823#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2824 { \
2825 .name = _name, \
2826 .lookup = { \
2827 .dev_id = _dev, \
2828 .con_id = _con, \
2829 }, \
2830 .ops = &tegra_periph_clk_ops, \
2831 .reg = _reg, \
2832 .inputs = _inputs, \
2833 .flags = _flags, \
2834 .max_rate = _max, \
2835 .u.periph = { \
2836 .clk_num = _clk_num, \
2837 }, \
2838 }
2839
2840#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
2841 _flags, _ops) \
2842 { \
2843 .name = _name, \
2844 .lookup = { \
2845 .dev_id = _dev, \
2846 .con_id = _con, \
2847 }, \
2848 .ops = _ops, \
2849 .reg = _reg, \
2850 .inputs = _inputs, \
2851 .flags = _flags, \
2852 .max_rate = _max, \
2853 .u.periph = { \
2854 .clk_num = _clk_num, \
2855 }, \
2856 }
2857
2858#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
2859 { \
2860 .name = _name, \
2861 .lookup = { \
2862 .dev_id = _dev, \
2863 .con_id = _con, \
2864 }, \
2865 .ops = &tegra_clk_shared_bus_ops, \
2866 .parent = _parent, \
2867 .u.shared_bus_user = { \
2868 .client_id = _id, \
2869 .client_div = _div, \
2870 .mode = _mode, \
2871 }, \
2872 }
2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2878 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
2879 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2880 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2881 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
2882 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2883 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2884 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2885 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2893 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2894 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2895 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2896 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
2897 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2898 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2899 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2900 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2901 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2902 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2903 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2904 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2905 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
2906 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
2907 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2908 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2909 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2910 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2911 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2912 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2913 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2914 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2915 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2916 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2917 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2918 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2919 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2920 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2921 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
2922 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2923 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2933 PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2934 PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2935 PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2936 PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2937 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2938 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2939 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2940 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
2941 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
2942 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2943 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2944 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2945 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2946 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2947 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
2948 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
2949 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2950 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2951 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2952 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2953 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2954 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2955 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
2956 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
2957 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
2958 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2959 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2960
2961 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
2962 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
2963 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2964 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2965 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2966 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2967 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
2968 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
2969 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2970};
2971
2972#define CLK_DUPLICATE(_name, _dev, _con) \
2973 { \
2974 .name = _name, \
2975 .lookup = { \
2976 .dev_id = _dev, \
2977 .con_id = _con, \
2978 }, \
2979 }
2980
2981/* Some clocks may be used by different drivers depending on the board
2982 * configuration. List those here to register them twice in the clock lookup
2983 * table under two names.
2984 */
2985struct clk_duplicate tegra_clk_duplicates[] = {
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2989 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2994 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2995 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2996 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2997 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2998 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2999 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
3000 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
3001 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
3002 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
3003 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
3004 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
3005 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
3006 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
3007 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
3008 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
3009 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
3010 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
3011 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
3012 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
3013 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
3014 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
3015 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
3016 CLK_DUPLICATE("twd", "smp_twd", NULL),
3017 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
3018};
3019
3020struct clk *tegra_ptr_clks[] = {
3021 &tegra_clk_32k,
3022 &tegra_clk_m,
3023 &tegra_clk_m_div2,
3024 &tegra_clk_m_div4,
3025 &tegra_pll_ref,
3026 &tegra_pll_m,
3027 &tegra_pll_m_out1,
3028 &tegra_pll_c,
3029 &tegra_pll_c_out1,
3030 &tegra_pll_p,
3031 &tegra_pll_p_out1,
3032 &tegra_pll_p_out2,
3033 &tegra_pll_p_out3,
3034 &tegra_pll_p_out4,
3035 &tegra_pll_a,
3036 &tegra_pll_a_out0,
3037 &tegra_pll_d,
3038 &tegra_pll_d_out0,
3039 &tegra_pll_d2,
3040 &tegra_pll_d2_out0,
3041 &tegra_pll_u,
3042 &tegra_pll_x,
3043 &tegra_pll_x_out0,
3044 &tegra_pll_e,
3045 &tegra_clk_cclk_g,
3046 &tegra_cml0_clk,
3047 &tegra_cml1_clk,
3048 &tegra_pciex_clk,
3049 &tegra_clk_sclk,
3050 &tegra_clk_blink,
3051 &tegra30_clk_twd,
3052};
3053
3054
3055static void tegra30_init_one_clock(struct clk *c)
3056{
3057 clk_init(c);
3058 INIT_LIST_HEAD(&c->shared_bus_list);
3059 if (!c->lookup.dev_id && !c->lookup.con_id)
3060 c->lookup.con_id = c->name;
3061 c->lookup.clk = c;
3062 clkdev_add(&c->lookup);
3063}
3064
3065void __init tegra30_init_clocks(void)
3066{
3067 int i;
3068 struct clk *c;
3069
3070 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
3071 tegra30_init_one_clock(tegra_ptr_clks[i]);
3072
3073 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
3074 tegra30_init_one_clock(&tegra_list_clks[i]);
3075
3076 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
3077 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
3078 if (!c) {
3079 pr_err("%s: Unknown duplicate clock %s\n", __func__,
3080 tegra_clk_duplicates[i].name);
3081 continue;
3082 }
3083
3084 tegra_clk_duplicates[i].lookup.clk = c;
3085 clkdev_add(&tegra_clk_duplicates[i].lookup);
3086 }
3087
3088 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
3089 tegra30_init_one_clock(&tegra_sync_source_list[i]);
3090 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
3091 tegra30_init_one_clock(&tegra_clk_audio_list[i]);
3092 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
3093 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
3094
3095 init_clk_out_mux();
3096 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
3097 tegra30_init_one_clock(&tegra_clk_out_list[i]);
3098
3099}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 01:41:48 -0500