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authorChris Metcalf <cmetcalf@tilera.com>2012-04-07 16:53:03 -0400
committerChris Metcalf <cmetcalf@tilera.com>2012-07-11 16:04:58 -0400
commitbce5bbbb23f780a792be7e594af7cd4b4aae1cd4 (patch)
treed140d8badb0ed24f4ccc2f89266772ae6836f0f3 /arch
parent10104a1ad670889adc1ae3779df968db621b5dbd (diff)
arch/tile: provide kernel support for the tilegx TRIO shim
Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/tile/gxio/Kconfig6
-rw-r--r--arch/tile/gxio/Makefile1
-rw-r--r--arch/tile/gxio/iorpc_trio.c327
-rw-r--r--arch/tile/gxio/trio.c49
-rw-r--r--arch/tile/include/arch/trio.h72
-rw-r--r--arch/tile/include/arch/trio_constants.h36
-rw-r--r--arch/tile/include/arch/trio_def.h41
-rw-r--r--arch/tile/include/arch/trio_pcie_intfc.h229
-rw-r--r--arch/tile/include/arch/trio_pcie_intfc_def.h32
-rw-r--r--arch/tile/include/arch/trio_pcie_rc.h156
-rw-r--r--arch/tile/include/arch/trio_pcie_rc_def.h24
-rw-r--r--arch/tile/include/arch/trio_shm.h125
-rw-r--r--arch/tile/include/arch/trio_shm_def.h19
-rw-r--r--arch/tile/include/gxio/iorpc_trio.h97
-rw-r--r--arch/tile/include/gxio/trio.h298
-rw-r--r--arch/tile/include/hv/drv_trio_intf.h195
16 files changed, 1707 insertions, 0 deletions
diff --git a/arch/tile/gxio/Kconfig b/arch/tile/gxio/Kconfig
index 8aeebb70a3df..68e1cca2cce5 100644
--- a/arch/tile/gxio/Kconfig
+++ b/arch/tile/gxio/Kconfig
@@ -15,3 +15,9 @@ config TILE_GXIO_MPIPE
15 bool 15 bool
16 select TILE_GXIO 16 select TILE_GXIO
17 select TILE_GXIO_DMA 17 select TILE_GXIO_DMA
18
19# Support direct access to the TILE-Gx TRIO hardware from kernel space.
20config TILE_GXIO_TRIO
21 bool
22 select TILE_GXIO
23 select TILE_GXIO_DMA
diff --git a/arch/tile/gxio/Makefile b/arch/tile/gxio/Makefile
index 130eec48c152..2389ef307c73 100644
--- a/arch/tile/gxio/Makefile
+++ b/arch/tile/gxio/Makefile
@@ -5,3 +5,4 @@
5obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o 5obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o
6obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o 6obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o
7obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o 7obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o
8obj-$(CONFIG_TILE_GXIO_TRIO) += trio.o iorpc_trio.o
diff --git a/arch/tile/gxio/iorpc_trio.c b/arch/tile/gxio/iorpc_trio.c
new file mode 100644
index 000000000000..cef4b2209cda
--- /dev/null
+++ b/arch/tile/gxio/iorpc_trio.c
@@ -0,0 +1,327 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16#include "gxio/iorpc_trio.h"
17
18struct alloc_asids_param {
19 unsigned int count;
20 unsigned int first;
21 unsigned int flags;
22};
23
24int gxio_trio_alloc_asids(gxio_trio_context_t * context, unsigned int count,
25 unsigned int first, unsigned int flags)
26{
27 struct alloc_asids_param temp;
28 struct alloc_asids_param *params = &temp;
29
30 params->count = count;
31 params->first = first;
32 params->flags = flags;
33
34 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
35 sizeof(*params), GXIO_TRIO_OP_ALLOC_ASIDS);
36}
37
38EXPORT_SYMBOL(gxio_trio_alloc_asids);
39
40
41struct alloc_memory_maps_param {
42 unsigned int count;
43 unsigned int first;
44 unsigned int flags;
45};
46
47int gxio_trio_alloc_memory_maps(gxio_trio_context_t * context,
48 unsigned int count, unsigned int first,
49 unsigned int flags)
50{
51 struct alloc_memory_maps_param temp;
52 struct alloc_memory_maps_param *params = &temp;
53
54 params->count = count;
55 params->first = first;
56 params->flags = flags;
57
58 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
59 sizeof(*params), GXIO_TRIO_OP_ALLOC_MEMORY_MAPS);
60}
61
62EXPORT_SYMBOL(gxio_trio_alloc_memory_maps);
63
64
65struct alloc_pio_regions_param {
66 unsigned int count;
67 unsigned int first;
68 unsigned int flags;
69};
70
71int gxio_trio_alloc_pio_regions(gxio_trio_context_t * context,
72 unsigned int count, unsigned int first,
73 unsigned int flags)
74{
75 struct alloc_pio_regions_param temp;
76 struct alloc_pio_regions_param *params = &temp;
77
78 params->count = count;
79 params->first = first;
80 params->flags = flags;
81
82 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
83 sizeof(*params), GXIO_TRIO_OP_ALLOC_PIO_REGIONS);
84}
85
86EXPORT_SYMBOL(gxio_trio_alloc_pio_regions);
87
88struct init_pio_region_aux_param {
89 unsigned int pio_region;
90 unsigned int mac;
91 uint32_t bus_address_hi;
92 unsigned int flags;
93};
94
95int gxio_trio_init_pio_region_aux(gxio_trio_context_t * context,
96 unsigned int pio_region, unsigned int mac,
97 uint32_t bus_address_hi, unsigned int flags)
98{
99 struct init_pio_region_aux_param temp;
100 struct init_pio_region_aux_param *params = &temp;
101
102 params->pio_region = pio_region;
103 params->mac = mac;
104 params->bus_address_hi = bus_address_hi;
105 params->flags = flags;
106
107 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
108 sizeof(*params), GXIO_TRIO_OP_INIT_PIO_REGION_AUX);
109}
110
111EXPORT_SYMBOL(gxio_trio_init_pio_region_aux);
112
113
114struct init_memory_map_mmu_aux_param {
115 unsigned int map;
116 unsigned long va;
117 uint64_t size;
118 unsigned int asid;
119 unsigned int mac;
120 uint64_t bus_address;
121 unsigned int node;
122 unsigned int order_mode;
123};
124
125int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t * context,
126 unsigned int map, unsigned long va,
127 uint64_t size, unsigned int asid,
128 unsigned int mac, uint64_t bus_address,
129 unsigned int node,
130 unsigned int order_mode)
131{
132 struct init_memory_map_mmu_aux_param temp;
133 struct init_memory_map_mmu_aux_param *params = &temp;
134
135 params->map = map;
136 params->va = va;
137 params->size = size;
138 params->asid = asid;
139 params->mac = mac;
140 params->bus_address = bus_address;
141 params->node = node;
142 params->order_mode = order_mode;
143
144 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
145 sizeof(*params),
146 GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX);
147}
148
149EXPORT_SYMBOL(gxio_trio_init_memory_map_mmu_aux);
150
151struct get_port_property_param {
152 struct pcie_trio_ports_property trio_ports;
153};
154
155int gxio_trio_get_port_property(gxio_trio_context_t * context,
156 struct pcie_trio_ports_property *trio_ports)
157{
158 int __result;
159 struct get_port_property_param temp;
160 struct get_port_property_param *params = &temp;
161
162 __result =
163 hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
164 GXIO_TRIO_OP_GET_PORT_PROPERTY);
165 *trio_ports = params->trio_ports;
166
167 return __result;
168}
169
170EXPORT_SYMBOL(gxio_trio_get_port_property);
171
172struct config_legacy_intr_param {
173 union iorpc_interrupt interrupt;
174 unsigned int mac;
175 unsigned int intx;
176};
177
178int gxio_trio_config_legacy_intr(gxio_trio_context_t * context, int inter_x,
179 int inter_y, int inter_ipi, int inter_event,
180 unsigned int mac, unsigned int intx)
181{
182 struct config_legacy_intr_param temp;
183 struct config_legacy_intr_param *params = &temp;
184
185 params->interrupt.kernel.x = inter_x;
186 params->interrupt.kernel.y = inter_y;
187 params->interrupt.kernel.ipi = inter_ipi;
188 params->interrupt.kernel.event = inter_event;
189 params->mac = mac;
190 params->intx = intx;
191
192 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
193 sizeof(*params), GXIO_TRIO_OP_CONFIG_LEGACY_INTR);
194}
195
196EXPORT_SYMBOL(gxio_trio_config_legacy_intr);
197
198struct config_msi_intr_param {
199 union iorpc_interrupt interrupt;
200 unsigned int mac;
201 unsigned int mem_map;
202 uint64_t mem_map_base;
203 uint64_t mem_map_limit;
204 unsigned int asid;
205};
206
207int gxio_trio_config_msi_intr(gxio_trio_context_t * context, int inter_x,
208 int inter_y, int inter_ipi, int inter_event,
209 unsigned int mac, unsigned int mem_map,
210 uint64_t mem_map_base, uint64_t mem_map_limit,
211 unsigned int asid)
212{
213 struct config_msi_intr_param temp;
214 struct config_msi_intr_param *params = &temp;
215
216 params->interrupt.kernel.x = inter_x;
217 params->interrupt.kernel.y = inter_y;
218 params->interrupt.kernel.ipi = inter_ipi;
219 params->interrupt.kernel.event = inter_event;
220 params->mac = mac;
221 params->mem_map = mem_map;
222 params->mem_map_base = mem_map_base;
223 params->mem_map_limit = mem_map_limit;
224 params->asid = asid;
225
226 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
227 sizeof(*params), GXIO_TRIO_OP_CONFIG_MSI_INTR);
228}
229
230EXPORT_SYMBOL(gxio_trio_config_msi_intr);
231
232
233struct set_mps_mrs_param {
234 uint16_t mps;
235 uint16_t mrs;
236 unsigned int mac;
237};
238
239int gxio_trio_set_mps_mrs(gxio_trio_context_t * context, uint16_t mps,
240 uint16_t mrs, unsigned int mac)
241{
242 struct set_mps_mrs_param temp;
243 struct set_mps_mrs_param *params = &temp;
244
245 params->mps = mps;
246 params->mrs = mrs;
247 params->mac = mac;
248
249 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
250 sizeof(*params), GXIO_TRIO_OP_SET_MPS_MRS);
251}
252
253EXPORT_SYMBOL(gxio_trio_set_mps_mrs);
254
255struct force_rc_link_up_param {
256 unsigned int mac;
257};
258
259int gxio_trio_force_rc_link_up(gxio_trio_context_t * context, unsigned int mac)
260{
261 struct force_rc_link_up_param temp;
262 struct force_rc_link_up_param *params = &temp;
263
264 params->mac = mac;
265
266 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
267 sizeof(*params), GXIO_TRIO_OP_FORCE_RC_LINK_UP);
268}
269
270EXPORT_SYMBOL(gxio_trio_force_rc_link_up);
271
272struct force_ep_link_up_param {
273 unsigned int mac;
274};
275
276int gxio_trio_force_ep_link_up(gxio_trio_context_t * context, unsigned int mac)
277{
278 struct force_ep_link_up_param temp;
279 struct force_ep_link_up_param *params = &temp;
280
281 params->mac = mac;
282
283 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
284 sizeof(*params), GXIO_TRIO_OP_FORCE_EP_LINK_UP);
285}
286
287EXPORT_SYMBOL(gxio_trio_force_ep_link_up);
288
289struct get_mmio_base_param {
290 HV_PTE base;
291};
292
293int gxio_trio_get_mmio_base(gxio_trio_context_t * context, HV_PTE *base)
294{
295 int __result;
296 struct get_mmio_base_param temp;
297 struct get_mmio_base_param *params = &temp;
298
299 __result =
300 hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
301 GXIO_TRIO_OP_GET_MMIO_BASE);
302 *base = params->base;
303
304 return __result;
305}
306
307EXPORT_SYMBOL(gxio_trio_get_mmio_base);
308
309struct check_mmio_offset_param {
310 unsigned long offset;
311 unsigned long size;
312};
313
314int gxio_trio_check_mmio_offset(gxio_trio_context_t * context,
315 unsigned long offset, unsigned long size)
316{
317 struct check_mmio_offset_param temp;
318 struct check_mmio_offset_param *params = &temp;
319
320 params->offset = offset;
321 params->size = size;
322
323 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
324 sizeof(*params), GXIO_TRIO_OP_CHECK_MMIO_OFFSET);
325}
326
327EXPORT_SYMBOL(gxio_trio_check_mmio_offset);
diff --git a/arch/tile/gxio/trio.c b/arch/tile/gxio/trio.c
new file mode 100644
index 000000000000..69f0b8df3ce3
--- /dev/null
+++ b/arch/tile/gxio/trio.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * Implementation of trio gxio calls.
17 */
18
19#include <linux/errno.h>
20#include <linux/io.h>
21#include <linux/module.h>
22
23#include <gxio/trio.h>
24#include <gxio/iorpc_globals.h>
25#include <gxio/iorpc_trio.h>
26#include <gxio/kiorpc.h>
27
28int gxio_trio_init(gxio_trio_context_t *context, unsigned int trio_index)
29{
30 char file[32];
31 int fd;
32
33 snprintf(file, sizeof(file), "trio/%d/iorpc", trio_index);
34 fd = hv_dev_open((HV_VirtAddr) file, 0);
35 if (fd < 0) {
36 context->fd = -1;
37
38 if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
39 return fd;
40 else
41 return -ENODEV;
42 }
43
44 context->fd = fd;
45
46 return 0;
47}
48
49EXPORT_SYMBOL_GPL(gxio_trio_init);
diff --git a/arch/tile/include/arch/trio.h b/arch/tile/include/arch/trio.h
new file mode 100644
index 000000000000..d3000a871a21
--- /dev/null
+++ b/arch/tile/include/arch/trio.h
@@ -0,0 +1,72 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_H__
18#define __ARCH_TRIO_H__
19
20#include <arch/abi.h>
21#include <arch/trio_def.h>
22
23#ifndef __ASSEMBLER__
24
25/*
26 * Tile PIO Region Configuration - CFG Address Format.
27 * This register describes the address format for PIO accesses when the
28 * associated region is setup with TYPE=CFG.
29 */
30
31__extension__
32typedef union
33{
34 struct
35 {
36#ifndef __BIG_ENDIAN__
37 /* Register Address (full byte address). */
38 uint_reg_t reg_addr : 12;
39 /* Function Number */
40 uint_reg_t fn : 3;
41 /* Device Number */
42 uint_reg_t dev : 5;
43 /* BUS Number */
44 uint_reg_t bus : 8;
45 /* Config Type: 0 for access to directly-attached device. 1 otherwise. */
46 uint_reg_t type : 1;
47 /* Reserved. */
48 uint_reg_t __reserved_0 : 1;
49 /*
50 * MAC select. This must match the configuration in
51 * TILE_PIO_REGION_SETUP.MAC.
52 */
53 uint_reg_t mac : 2;
54 /* Reserved. */
55 uint_reg_t __reserved_1 : 32;
56#else /* __BIG_ENDIAN__ */
57 uint_reg_t __reserved_1 : 32;
58 uint_reg_t mac : 2;
59 uint_reg_t __reserved_0 : 1;
60 uint_reg_t type : 1;
61 uint_reg_t bus : 8;
62 uint_reg_t dev : 5;
63 uint_reg_t fn : 3;
64 uint_reg_t reg_addr : 12;
65#endif
66 };
67
68 uint_reg_t word;
69} TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t;
70#endif /* !defined(__ASSEMBLER__) */
71
72#endif /* !defined(__ARCH_TRIO_H__) */
diff --git a/arch/tile/include/arch/trio_constants.h b/arch/tile/include/arch/trio_constants.h
new file mode 100644
index 000000000000..628b045436b8
--- /dev/null
+++ b/arch/tile/include/arch/trio_constants.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15
16#ifndef __ARCH_TRIO_CONSTANTS_H__
17#define __ARCH_TRIO_CONSTANTS_H__
18
19#define TRIO_NUM_ASIDS 16
20#define TRIO_NUM_TLBS_PER_ASID 16
21
22#define TRIO_NUM_TPIO_REGIONS 8
23#define TRIO_LOG2_NUM_TPIO_REGIONS 3
24
25#define TRIO_NUM_MAP_MEM_REGIONS 16
26#define TRIO_LOG2_NUM_MAP_MEM_REGIONS 4
27#define TRIO_NUM_MAP_SQ_REGIONS 8
28#define TRIO_LOG2_NUM_MAP_SQ_REGIONS 3
29
30#define TRIO_LOG2_NUM_SQ_FIFO_ENTRIES 6
31
32#define TRIO_NUM_PUSH_DMA_RINGS 32
33
34#define TRIO_NUM_PULL_DMA_RINGS 32
35
36#endif /* __ARCH_TRIO_CONSTANTS_H__ */
diff --git a/arch/tile/include/arch/trio_def.h b/arch/tile/include/arch/trio_def.h
new file mode 100644
index 000000000000..e80500317dc4
--- /dev/null
+++ b/arch/tile/include/arch/trio_def.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_DEF_H__
18#define __ARCH_TRIO_DEF_H__
19#define TRIO_CFG_REGION_ADDR__REG_SHIFT 0
20#define TRIO_CFG_REGION_ADDR__INTFC_SHIFT 16
21#define TRIO_CFG_REGION_ADDR__INTFC_VAL_TRIO 0x0
22#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE 0x1
23#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD 0x2
24#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 0x3
25#define TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT 18
26#define TRIO_CFG_REGION_ADDR__PROT_SHIFT 20
27#define TRIO_PIO_REGIONS_ADDR__REGION_SHIFT 32
28#define TRIO_MAP_MEM_REG_INT0 0x1000000000
29#define TRIO_MAP_MEM_REG_INT1 0x1000000008
30#define TRIO_MAP_MEM_REG_INT2 0x1000000010
31#define TRIO_MAP_MEM_REG_INT3 0x1000000018
32#define TRIO_MAP_MEM_REG_INT4 0x1000000020
33#define TRIO_MAP_MEM_REG_INT5 0x1000000028
34#define TRIO_MAP_MEM_REG_INT6 0x1000000030
35#define TRIO_MAP_MEM_REG_INT7 0x1000000038
36#define TRIO_MAP_MEM_LIM__ADDR_SHIFT 12
37#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED 0x0
38#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT 0x1
39#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD 0x2
40#define TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT 30
41#endif /* !defined(__ARCH_TRIO_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_intfc.h b/arch/tile/include/arch/trio_pcie_intfc.h
new file mode 100644
index 000000000000..0487fdb9d581
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_intfc.h
@@ -0,0 +1,229 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_PCIE_INTFC_H__
18#define __ARCH_TRIO_PCIE_INTFC_H__
19
20#include <arch/abi.h>
21#include <arch/trio_pcie_intfc_def.h>
22
23#ifndef __ASSEMBLER__
24
25/*
26 * Port Configuration.
27 * Configuration of the PCIe Port
28 */
29
30__extension__
31typedef union
32{
33 struct
34 {
35#ifndef __BIG_ENDIAN__
36 /* Provides the state of the strapping pins for this port. */
37 uint_reg_t strap_state : 3;
38 /* Reserved. */
39 uint_reg_t __reserved_0 : 1;
40 /*
41 * When 1, the device type will be overridden using OVD_DEV_TYPE_VAL.
42 * When 0, the device type is determined based on the STRAP_STATE.
43 */
44 uint_reg_t ovd_dev_type : 1;
45 /* Provides the device type when OVD_DEV_TYPE is 1. */
46 uint_reg_t ovd_dev_type_val : 4;
47 /* Determines how link is trained. */
48 uint_reg_t train_mode : 2;
49 /* Reserved. */
50 uint_reg_t __reserved_1 : 1;
51 /*
52 * For PCIe, used to flip physical RX lanes that were not properly wired.
53 * This is not the same as lane reversal which is handled automatically
54 * during link training. When 0, RX Lane0 must be wired to the link
55 * partner (either to its Lane0 or it's LaneN). When RX_LANE_FLIP is 1,
56 * the highest numbered lane for this port becomes Lane0 and Lane0 does
57 * NOT have to be wired to the link partner.
58 */
59 uint_reg_t rx_lane_flip : 1;
60 /*
61 * For PCIe, used to flip physical TX lanes that were not properly wired.
62 * This is not the same as lane reversal which is handled automatically
63 * during link training. When 0, TX Lane0 must be wired to the link
64 * partner (either to its Lane0 or it's LaneN). When TX_LANE_FLIP is 1,
65 * the highest numbered lane for this port becomes Lane0 and Lane0 does
66 * NOT have to be wired to the link partner.
67 */
68 uint_reg_t tx_lane_flip : 1;
69 /*
70 * For StreamIO port, configures the width of the port when TRAIN_MODE is
71 * not STRAP.
72 */
73 uint_reg_t stream_width : 2;
74 /*
75 * For StreamIO port, configures the rate of the port when TRAIN_MODE is
76 * not STRAP.
77 */
78 uint_reg_t stream_rate : 2;
79 /* Reserved. */
80 uint_reg_t __reserved_2 : 46;
81#else /* __BIG_ENDIAN__ */
82 uint_reg_t __reserved_2 : 46;
83 uint_reg_t stream_rate : 2;
84 uint_reg_t stream_width : 2;
85 uint_reg_t tx_lane_flip : 1;
86 uint_reg_t rx_lane_flip : 1;
87 uint_reg_t __reserved_1 : 1;
88 uint_reg_t train_mode : 2;
89 uint_reg_t ovd_dev_type_val : 4;
90 uint_reg_t ovd_dev_type : 1;
91 uint_reg_t __reserved_0 : 1;
92 uint_reg_t strap_state : 3;
93#endif
94 };
95
96 uint_reg_t word;
97} TRIO_PCIE_INTFC_PORT_CONFIG_t;
98
99/*
100 * Port Status.
101 * Status of the PCIe Port. This register applies to the StreamIO port when
102 * StreamIO is enabled.
103 */
104
105__extension__
106typedef union
107{
108 struct
109 {
110#ifndef __BIG_ENDIAN__
111 /*
112 * Indicates the DL state of the port. When 1, the port is up and ready
113 * to receive traffic.
114 */
115 uint_reg_t dl_up : 1;
116 /*
117 * Indicates the number of times the link has gone down. Clears on read.
118 */
119 uint_reg_t dl_down_cnt : 7;
120 /* Indicates the SERDES PLL has spun up and is providing a valid clock. */
121 uint_reg_t clock_ready : 1;
122 /* Reserved. */
123 uint_reg_t __reserved_0 : 7;
124 /* Device revision ID. */
125 uint_reg_t device_rev : 8;
126 /* Link state (PCIe). */
127 uint_reg_t ltssm_state : 6;
128 /* Link power management state (PCIe). */
129 uint_reg_t pm_state : 3;
130 /* Reserved. */
131 uint_reg_t __reserved_1 : 31;
132#else /* __BIG_ENDIAN__ */
133 uint_reg_t __reserved_1 : 31;
134 uint_reg_t pm_state : 3;
135 uint_reg_t ltssm_state : 6;
136 uint_reg_t device_rev : 8;
137 uint_reg_t __reserved_0 : 7;
138 uint_reg_t clock_ready : 1;
139 uint_reg_t dl_down_cnt : 7;
140 uint_reg_t dl_up : 1;
141#endif
142 };
143
144 uint_reg_t word;
145} TRIO_PCIE_INTFC_PORT_STATUS_t;
146
147/*
148 * Transmit FIFO Control.
149 * Contains TX FIFO thresholds. These registers are for diagnostics purposes
150 * only. Changing these values causes undefined behavior.
151 */
152
153__extension__
154typedef union
155{
156 struct
157 {
158#ifndef __BIG_ENDIAN__
159 /*
160 * Almost-Empty level for TX0 data. Typically set to at least
161 * roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz
162 * for a x4 port (250MHz).
163 */
164 uint_reg_t tx0_data_ae_lvl : 7;
165 /* Reserved. */
166 uint_reg_t __reserved_0 : 1;
167 /* Almost-Empty level for TX1 data. */
168 uint_reg_t tx1_data_ae_lvl : 7;
169 /* Reserved. */
170 uint_reg_t __reserved_1 : 1;
171 /* Almost-Full level for TX0 data. */
172 uint_reg_t tx0_data_af_lvl : 7;
173 /* Reserved. */
174 uint_reg_t __reserved_2 : 1;
175 /* Almost-Full level for TX1 data. */
176 uint_reg_t tx1_data_af_lvl : 7;
177 /* Reserved. */
178 uint_reg_t __reserved_3 : 1;
179 /* Almost-Full level for TX0 info. */
180 uint_reg_t tx0_info_af_lvl : 5;
181 /* Reserved. */
182 uint_reg_t __reserved_4 : 3;
183 /* Almost-Full level for TX1 info. */
184 uint_reg_t tx1_info_af_lvl : 5;
185 /* Reserved. */
186 uint_reg_t __reserved_5 : 3;
187 /*
188 * This register provides performance adjustment for high bandwidth
189 * flows. The MAC will assert almost-full to TRIO if non-posted credits
190 * fall below this level. Note that setting this larger than the initial
191 * PORT_CREDIT.NPH value will cause READS to never be sent. If the
192 * initial credit value from the link partner is smaller than this value
193 * when the link comes up, the value will be reset to the initial credit
194 * value to prevent lockup.
195 */
196 uint_reg_t min_np_credits : 8;
197 /*
198 * This register provides performance adjustment for high bandwidth
199 * flows. The MAC will assert almost-full to TRIO if posted credits fall
200 * below this level. Note that setting this larger than the initial
201 * PORT_CREDIT.PH value will cause WRITES to never be sent. If the
202 * initial credit value from the link partner is smaller than this value
203 * when the link comes up, the value will be reset to the initial credit
204 * value to prevent lockup.
205 */
206 uint_reg_t min_p_credits : 8;
207#else /* __BIG_ENDIAN__ */
208 uint_reg_t min_p_credits : 8;
209 uint_reg_t min_np_credits : 8;
210 uint_reg_t __reserved_5 : 3;
211 uint_reg_t tx1_info_af_lvl : 5;
212 uint_reg_t __reserved_4 : 3;
213 uint_reg_t tx0_info_af_lvl : 5;
214 uint_reg_t __reserved_3 : 1;
215 uint_reg_t tx1_data_af_lvl : 7;
216 uint_reg_t __reserved_2 : 1;
217 uint_reg_t tx0_data_af_lvl : 7;
218 uint_reg_t __reserved_1 : 1;
219 uint_reg_t tx1_data_ae_lvl : 7;
220 uint_reg_t __reserved_0 : 1;
221 uint_reg_t tx0_data_ae_lvl : 7;
222#endif
223 };
224
225 uint_reg_t word;
226} TRIO_PCIE_INTFC_TX_FIFO_CTL_t;
227#endif /* !defined(__ASSEMBLER__) */
228
229#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_intfc_def.h b/arch/tile/include/arch/trio_pcie_intfc_def.h
new file mode 100644
index 000000000000..d3fd6781fb24
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_intfc_def.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_PCIE_INTFC_DEF_H__
18#define __ARCH_TRIO_PCIE_INTFC_DEF_H__
19#define TRIO_PCIE_INTFC_MAC_INT_STS 0x0000
20#define TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK 0xf000
21#define TRIO_PCIE_INTFC_PORT_CONFIG 0x0018
22#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_DISABLED 0x0
23#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT 0x1
24#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC 0x2
25#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 0x3
26#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1 0x4
27#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_XLINK 0x5
28#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X1 0x6
29#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X4 0x7
30#define TRIO_PCIE_INTFC_PORT_STATUS 0x0020
31#define TRIO_PCIE_INTFC_TX_FIFO_CTL 0x0050
32#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_rc.h b/arch/tile/include/arch/trio_pcie_rc.h
new file mode 100644
index 000000000000..6a25d0aca857
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_rc.h
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_PCIE_RC_H__
18#define __ARCH_TRIO_PCIE_RC_H__
19
20#include <arch/abi.h>
21#include <arch/trio_pcie_rc_def.h>
22
23#ifndef __ASSEMBLER__
24
25/* Device Capabilities Register. */
26
27__extension__
28typedef union
29{
30 struct
31 {
32#ifndef __BIG_ENDIAN__
33 /*
34 * Max_Payload_Size Supported, writablethrough the MAC_STANDARD interface
35 */
36 uint_reg_t mps_sup : 3;
37 /*
38 * This field is writable through the MAC_STANDARD interface. However,
39 * Phantom Function is not supported. Therefore, the application must
40 * not write any value other than 0x0 to this field.
41 */
42 uint_reg_t phantom_function_supported : 2;
43 /* This bit is writable through the MAC_STANDARD interface. */
44 uint_reg_t ext_tag_field_supported : 1;
45 /* Reserved. */
46 uint_reg_t __reserved_0 : 3;
47 /* Endpoint L1 Acceptable Latency Must be 0x0 for non-Endpoint devices. */
48 uint_reg_t l1_lat : 3;
49 /*
50 * Undefined since PCI Express 1.1 (Was Attention Button Present for PCI
51 * Express 1.0a)
52 */
53 uint_reg_t r1 : 1;
54 /*
55 * Undefined since PCI Express 1.1 (Was Attention Indicator Present for
56 * PCI Express 1.0a)
57 */
58 uint_reg_t r2 : 1;
59 /*
60 * Undefined since PCI Express 1.1 (Was Power Indicator Present for PCI
61 * Express 1.0a)
62 */
63 uint_reg_t r3 : 1;
64 /*
65 * Role-Based Error Reporting, writable through the MAC_STANDARD
66 * interface. Required to be set for device compliant to 1.1 spec and
67 * later.
68 */
69 uint_reg_t rer : 1;
70 /* Reserved. */
71 uint_reg_t __reserved_1 : 2;
72 /* Captured Slot Power Limit Value Upstream port only. */
73 uint_reg_t slot_pwr_lim : 8;
74 /* Captured Slot Power Limit Scale Upstream port only. */
75 uint_reg_t slot_pwr_scale : 2;
76 /* Reserved. */
77 uint_reg_t __reserved_2 : 4;
78 /* Endpoint L0s Acceptable LatencyMust be 0x0 for non-Endpoint devices. */
79 uint_reg_t l0s_lat : 1;
80 /* Reserved. */
81 uint_reg_t __reserved_3 : 31;
82#else /* __BIG_ENDIAN__ */
83 uint_reg_t __reserved_3 : 31;
84 uint_reg_t l0s_lat : 1;
85 uint_reg_t __reserved_2 : 4;
86 uint_reg_t slot_pwr_scale : 2;
87 uint_reg_t slot_pwr_lim : 8;
88 uint_reg_t __reserved_1 : 2;
89 uint_reg_t rer : 1;
90 uint_reg_t r3 : 1;
91 uint_reg_t r2 : 1;
92 uint_reg_t r1 : 1;
93 uint_reg_t l1_lat : 3;
94 uint_reg_t __reserved_0 : 3;
95 uint_reg_t ext_tag_field_supported : 1;
96 uint_reg_t phantom_function_supported : 2;
97 uint_reg_t mps_sup : 3;
98#endif
99 };
100
101 uint_reg_t word;
102} TRIO_PCIE_RC_DEVICE_CAP_t;
103
104/* Device Control Register. */
105
106__extension__
107typedef union
108{
109 struct
110 {
111#ifndef __BIG_ENDIAN__
112 /* Correctable Error Reporting Enable */
113 uint_reg_t cor_err_ena : 1;
114 /* Non-Fatal Error Reporting Enable */
115 uint_reg_t nf_err_ena : 1;
116 /* Fatal Error Reporting Enable */
117 uint_reg_t fatal_err_ena : 1;
118 /* Unsupported Request Reporting Enable */
119 uint_reg_t ur_ena : 1;
120 /* Relaxed orderring enable */
121 uint_reg_t ro_ena : 1;
122 /* Max Payload Size */
123 uint_reg_t max_payload_size : 3;
124 /* Extended Tag Field Enable */
125 uint_reg_t ext_tag : 1;
126 /* Phantom Function Enable */
127 uint_reg_t ph_fn_ena : 1;
128 /* AUX Power PM Enable */
129 uint_reg_t aux_pm_ena : 1;
130 /* Enable NoSnoop */
131 uint_reg_t no_snoop : 1;
132 /* Max read request size */
133 uint_reg_t max_read_req_sz : 3;
134 /* Reserved. */
135 uint_reg_t __reserved : 49;
136#else /* __BIG_ENDIAN__ */
137 uint_reg_t __reserved : 49;
138 uint_reg_t max_read_req_sz : 3;
139 uint_reg_t no_snoop : 1;
140 uint_reg_t aux_pm_ena : 1;
141 uint_reg_t ph_fn_ena : 1;
142 uint_reg_t ext_tag : 1;
143 uint_reg_t max_payload_size : 3;
144 uint_reg_t ro_ena : 1;
145 uint_reg_t ur_ena : 1;
146 uint_reg_t fatal_err_ena : 1;
147 uint_reg_t nf_err_ena : 1;
148 uint_reg_t cor_err_ena : 1;
149#endif
150 };
151
152 uint_reg_t word;
153} TRIO_PCIE_RC_DEVICE_CONTROL_t;
154#endif /* !defined(__ASSEMBLER__) */
155
156#endif /* !defined(__ARCH_TRIO_PCIE_RC_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_rc_def.h b/arch/tile/include/arch/trio_pcie_rc_def.h
new file mode 100644
index 000000000000..74081a65b6f2
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_rc_def.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_PCIE_RC_DEF_H__
18#define __ARCH_TRIO_PCIE_RC_DEF_H__
19#define TRIO_PCIE_RC_DEVICE_CAP 0x0074
20#define TRIO_PCIE_RC_DEVICE_CONTROL 0x0078
21#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID 0x0000
22#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT 16
23#define TRIO_PCIE_RC_REVISION_ID 0x0008
24#endif /* !defined(__ARCH_TRIO_PCIE_RC_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_shm.h b/arch/tile/include/arch/trio_shm.h
new file mode 100644
index 000000000000..3382e38245af
--- /dev/null
+++ b/arch/tile/include/arch/trio_shm.h
@@ -0,0 +1,125 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17
18#ifndef __ARCH_TRIO_SHM_H__
19#define __ARCH_TRIO_SHM_H__
20
21#include <arch/abi.h>
22#include <arch/trio_shm_def.h>
23
24#ifndef __ASSEMBLER__
25/**
26 * TRIO DMA Descriptor.
27 * The TRIO DMA descriptor is written by software and consumed by hardware.
28 * It is used to specify the location of transaction data in the IO and Tile
29 * domains.
30 */
31
32__extension__
33typedef union
34{
35 struct
36 {
37 /* Word 0 */
38
39#ifndef __BIG_ENDIAN__
40 /** Tile side virtual address. */
41 int_reg_t va : 42;
42 /**
43 * Encoded size of buffer used on push DMA when C=1:
44 * 0 = 128 bytes
45 * 1 = 256 bytes
46 * 2 = 512 bytes
47 * 3 = 1024 bytes
48 * 4 = 1664 bytes
49 * 5 = 4096 bytes
50 * 6 = 10368 bytes
51 * 7 = 16384 bytes
52 */
53 uint_reg_t bsz : 3;
54 /**
55 * Chaining designation. Always zero for pull DMA
56 * 0 : Unchained buffer pointer
57 * 1 : Chained buffer pointer. Next buffer descriptor (e.g. VA) stored
58 * in 1st 8-bytes in buffer. For chained buffers, first 8-bytes of each
59 * buffer contain the next buffer descriptor formatted exactly like a PDE
60 * buffer descriptor. This allows a chained PDE buffer to be sent using
61 * push DMA.
62 */
63 uint_reg_t c : 1;
64 /**
65 * Notification interrupt will be delivered when the transaction has
66 * completed (all data has been read from or written to the Tile-side
67 * buffer).
68 */
69 uint_reg_t notif : 1;
70 /**
71 * When 0, the XSIZE field specifies the total byte count for the
72 * transaction. When 1, the XSIZE field is encoded as 2^(N+14) for N in
73 * {0..6}:
74 * 0 = 16KB
75 * 1 = 32KB
76 * 2 = 64KB
77 * 3 = 128KB
78 * 4 = 256KB
79 * 5 = 512KB
80 * 6 = 1MB
81 * All other encodings of the XSIZE field are reserved when SMOD=1
82 */
83 uint_reg_t smod : 1;
84 /**
85 * Total number of bytes to move for this transaction. When SMOD=1,
86 * this field is encoded - see SMOD description.
87 */
88 uint_reg_t xsize : 14;
89 /** Reserved. */
90 uint_reg_t __reserved_0 : 1;
91 /**
92 * Generation number. Used to indicate a valid descriptor in ring. When
93 * a new descriptor is written into the ring, software must toggle this
94 * bit. The net effect is that the GEN bit being written into new
95 * descriptors toggles each time the ring tail pointer wraps.
96 */
97 uint_reg_t gen : 1;
98#else /* __BIG_ENDIAN__ */
99 uint_reg_t gen : 1;
100 uint_reg_t __reserved_0 : 1;
101 uint_reg_t xsize : 14;
102 uint_reg_t smod : 1;
103 uint_reg_t notif : 1;
104 uint_reg_t c : 1;
105 uint_reg_t bsz : 3;
106 int_reg_t va : 42;
107#endif
108
109 /* Word 1 */
110
111#ifndef __BIG_ENDIAN__
112 /** IO-side address */
113 uint_reg_t io_address : 64;
114#else /* __BIG_ENDIAN__ */
115 uint_reg_t io_address : 64;
116#endif
117
118 };
119
120 /** Word access */
121 uint_reg_t words[2];
122} TRIO_DMA_DESC_t;
123#endif /* !defined(__ASSEMBLER__) */
124
125#endif /* !defined(__ARCH_TRIO_SHM_H__) */
diff --git a/arch/tile/include/arch/trio_shm_def.h b/arch/tile/include/arch/trio_shm_def.h
new file mode 100644
index 000000000000..72a59c88b06a
--- /dev/null
+++ b/arch/tile/include/arch/trio_shm_def.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_TRIO_SHM_DEF_H__
18#define __ARCH_TRIO_SHM_DEF_H__
19#endif /* !defined(__ARCH_TRIO_SHM_DEF_H__) */
diff --git a/arch/tile/include/gxio/iorpc_trio.h b/arch/tile/include/gxio/iorpc_trio.h
new file mode 100644
index 000000000000..15fb77992083
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_trio.h
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16#ifndef __GXIO_TRIO_LINUX_RPC_H__
17#define __GXIO_TRIO_LINUX_RPC_H__
18
19#include <hv/iorpc.h>
20
21#include <hv/drv_trio_intf.h>
22#include <gxio/trio.h>
23#include <gxio/kiorpc.h>
24#include <linux/string.h>
25#include <linux/module.h>
26#include <asm/pgtable.h>
27
28#define GXIO_TRIO_OP_ALLOC_ASIDS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1400)
29
30#define GXIO_TRIO_OP_ALLOC_MEMORY_MAPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1402)
31
32#define GXIO_TRIO_OP_ALLOC_PIO_REGIONS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140e)
33#define GXIO_TRIO_OP_INIT_PIO_REGION_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140f)
34
35#define GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1417)
36#define GXIO_TRIO_OP_GET_PORT_PROPERTY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1418)
37#define GXIO_TRIO_OP_CONFIG_LEGACY_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1419)
38#define GXIO_TRIO_OP_CONFIG_MSI_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x141a)
39
40#define GXIO_TRIO_OP_SET_MPS_MRS IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141c)
41#define GXIO_TRIO_OP_FORCE_RC_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141d)
42#define GXIO_TRIO_OP_FORCE_EP_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141e)
43#define GXIO_TRIO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
44#define GXIO_TRIO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
45
46int gxio_trio_alloc_asids(gxio_trio_context_t * context, unsigned int count,
47 unsigned int first, unsigned int flags);
48
49
50int gxio_trio_alloc_memory_maps(gxio_trio_context_t * context,
51 unsigned int count, unsigned int first,
52 unsigned int flags);
53
54
55int gxio_trio_alloc_pio_regions(gxio_trio_context_t * context,
56 unsigned int count, unsigned int first,
57 unsigned int flags);
58
59int gxio_trio_init_pio_region_aux(gxio_trio_context_t * context,
60 unsigned int pio_region, unsigned int mac,
61 uint32_t bus_address_hi, unsigned int flags);
62
63
64int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t * context,
65 unsigned int map, unsigned long va,
66 uint64_t size, unsigned int asid,
67 unsigned int mac, uint64_t bus_address,
68 unsigned int node,
69 unsigned int order_mode);
70
71int gxio_trio_get_port_property(gxio_trio_context_t * context,
72 struct pcie_trio_ports_property *trio_ports);
73
74int gxio_trio_config_legacy_intr(gxio_trio_context_t * context, int inter_x,
75 int inter_y, int inter_ipi, int inter_event,
76 unsigned int mac, unsigned int intx);
77
78int gxio_trio_config_msi_intr(gxio_trio_context_t * context, int inter_x,
79 int inter_y, int inter_ipi, int inter_event,
80 unsigned int mac, unsigned int mem_map,
81 uint64_t mem_map_base, uint64_t mem_map_limit,
82 unsigned int asid);
83
84
85int gxio_trio_set_mps_mrs(gxio_trio_context_t * context, uint16_t mps,
86 uint16_t mrs, unsigned int mac);
87
88int gxio_trio_force_rc_link_up(gxio_trio_context_t * context, unsigned int mac);
89
90int gxio_trio_force_ep_link_up(gxio_trio_context_t * context, unsigned int mac);
91
92int gxio_trio_get_mmio_base(gxio_trio_context_t * context, HV_PTE *base);
93
94int gxio_trio_check_mmio_offset(gxio_trio_context_t * context,
95 unsigned long offset, unsigned long size);
96
97#endif /* !__GXIO_TRIO_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/trio.h b/arch/tile/include/gxio/trio.h
new file mode 100644
index 000000000000..77b80cdd46d8
--- /dev/null
+++ b/arch/tile/include/gxio/trio.h
@@ -0,0 +1,298 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 *
17 * An API for allocating, configuring, and manipulating TRIO hardware
18 * resources
19 */
20
21/*
22 *
23 * The TILE-Gx TRIO shim provides connections to external devices via
24 * PCIe or other transaction IO standards. The gxio_trio_ API,
25 * declared in <gxio/trio.h>, allows applications to allocate and
26 * configure TRIO IO resources like DMA command rings, memory map
27 * windows, and device interrupts. The following sections introduce
28 * the various components of the API. We strongly recommend reading
29 * the TRIO section of the IO Device Guide (UG404) before working with
30 * this API.
31 *
32 * @section trio__ingress TRIO Ingress Hardware Resources
33 *
34 * The TRIO ingress hardware is responsible for examining incoming
35 * PCIe or StreamIO packets and choosing a processing mechanism based
36 * on the packets' bus address. The gxio_trio_ API can be used to
37 * configure different handlers for different ranges of bus address
38 * space. The user can configure "mapped memory" and "scatter queue"
39 * regions to match incoming packets within 4kB-aligned ranges of bus
40 * addresses. Each range specifies a different set of mapping
41 * parameters to be applied when handling the ingress packet. The
42 * following sections describe how to work with MapMem and scatter
43 * queue regions.
44 *
45 * @subsection trio__mapmem TRIO MapMem Regions
46 *
47 * TRIO mapped memory (or MapMem) regions allow the user to map
48 * incoming read and write requests directly to the application's
49 * memory space. MapMem regions are allocated via
50 * gxio_trio_alloc_memory_maps(). Given an integer MapMem number,
51 * applications can use gxio_trio_init_memory_map() to specify the
52 * range of bus addresses that will match the region and the range of
53 * virtual addresses to which those packets will be applied.
54 *
55 * As with many other gxio APIs, the programmer must be sure to
56 * register memory pages that will be used with MapMem regions. Pages
57 * can be registered with TRIO by allocating an ASID (address space
58 * identifier) and then using gxio_trio_register_page() to register up to
59 * 16 pages with the hardware. The initialization functions for
60 * resources that require registered memory (MapMem, scatter queues,
61 * push DMA, and pull DMA) then take an 'asid' parameter in order to
62 * configure which set of registered pages is used by each resource.
63 *
64 * @subsection trio__scatter_queue TRIO Scatter Queues
65 *
66 * The TRIO shim's scatter queue regions allow users to dynamically
67 * map buffers from a large address space into a small range of bus
68 * addresses. This is particularly helpful for PCIe endpoint devices,
69 * where the host generally limits the size of BARs to tens of
70 * megabytes.
71 *
72 * Each scatter queue consists of a memory map region, a queue of
73 * tile-side buffer VAs to be mapped to that region, and a bus-mapped
74 * "doorbell" register that the remote endpoint can write to trigger a
75 * dequeue of the current buffer VA, thus swapping in a new buffer.
76 * The VAs pushed onto a scatter queue must be 4kB aligned, so
77 * applications may need to use higher-level protocols to inform
78 * remote entities that they should apply some additional, sub-4kB
79 * offset when reading or writing the scatter queue region. For more
80 * information, see the IO Device Guide (UG404).
81 *
82 * @section trio__egress TRIO Egress Hardware Resources
83 *
84 * The TRIO shim supports two mechanisms for egress packet generation:
85 * programmed IO (PIO) and push/pull DMA. PIO allows applications to
86 * create MMIO mappings for PCIe or StreamIO address space, such that
87 * the application can generate word-sized read or write transactions
88 * by issuing load or store instructions. Push and pull DMA are tuned
89 * for larger transactions; they use specialized hardware engines to
90 * transfer large blocks of data at line rate.
91 *
92 * @subsection trio__pio TRIO Programmed IO
93 *
94 * Programmed IO allows applications to create MMIO mappings for PCIe
95 * or StreamIO address space. The hardware PIO regions support access
96 * to PCIe configuration, IO, and memory space, but the gxio_trio API
97 * only supports memory space accesses. PIO regions are allocated
98 * with gxio_trio_alloc_pio_regions() and initialized via
99 * gxio_trio_init_pio_region(). Once a region is bound to a range of
100 * bus address via the initialization function, the application can
101 * use gxio_trio_map_pio_region() to create MMIO mappings from its VA
102 * space onto the range of bus addresses supported by the PIO region.
103 *
104 * @subsection trio_dma TRIO Push and Pull DMA
105 *
106 * The TRIO push and pull DMA engines allow users to copy blocks of
107 * data between application memory and the bus. Push DMA generates
108 * write packets that copy from application memory to the bus and pull
109 * DMA generates read packets that copy from the bus into application
110 * memory. The DMA engines are managed via an API that is very
111 * similar to the mPIPE eDMA interface. For a detailed explanation of
112 * the eDMA queue API, see @ref gxio_mpipe_wrappers.
113 *
114 * Push and pull DMA queues are allocated via
115 * gxio_trio_alloc_push_dma_ring() / gxio_trio_alloc_pull_dma_ring().
116 * Once allocated, users generally use a ::gxio_trio_dma_queue_t
117 * object to manage the queue, providing easy wrappers for reserving
118 * command slots in the DMA command ring, filling those slots, and
119 * waiting for commands to complete. DMA queues can be initialized
120 * via gxio_trio_init_push_dma_queue() or
121 * gxio_trio_init_pull_dma_queue().
122 *
123 * See @ref trio/push_dma/app.c for an example of how to use push DMA.
124 *
125 * @section trio_shortcomings Plans for Future API Revisions
126 *
127 * The simulation framework is incomplete. Future features include:
128 *
129 * - Support for reset and deallocation of resources.
130 *
131 * - Support for pull DMA.
132 *
133 * - Support for interrupt regions and user-space interrupt delivery.
134 *
135 * - Support for getting BAR mappings and reserving regions of BAR
136 * address space.
137 */
138#ifndef _GXIO_TRIO_H_
139#define _GXIO_TRIO_H_
140
141#include <linux/types.h>
142
143#include "common.h"
144#include "dma_queue.h"
145
146#include <arch/trio_constants.h>
147#include <arch/trio.h>
148#include <arch/trio_pcie_intfc.h>
149#include <arch/trio_pcie_rc.h>
150#include <arch/trio_shm.h>
151#include <hv/drv_trio_intf.h>
152#include <hv/iorpc.h>
153
154/* A context object used to manage TRIO hardware resources. */
155typedef struct {
156
157 /* File descriptor for calling up to Linux (and thus the HV). */
158 int fd;
159
160 /* The VA at which the MAC MMIO registers are mapped. */
161 char *mmio_base_mac;
162
163 /* The VA at which the PIO config space are mapped for each PCIe MAC.
164 Gx36 has max 3 PCIe MACs per TRIO shim. */
165 char *mmio_base_pio_cfg[TILEGX_TRIO_PCIES];
166
167#ifdef USE_SHARED_PCIE_CONFIG_REGION
168 /* Index of the shared PIO region for PCI config access. */
169 int pio_cfg_index;
170#else
171 /* Index of the PIO region for PCI config access per MAC. */
172 int pio_cfg_index[TILEGX_TRIO_PCIES];
173#endif
174
175 /* The VA at which the push DMA MMIO registers are mapped. */
176 char *mmio_push_dma[TRIO_NUM_PUSH_DMA_RINGS];
177
178 /* The VA at which the pull DMA MMIO registers are mapped. */
179 char *mmio_pull_dma[TRIO_NUM_PUSH_DMA_RINGS];
180
181 /* Application space ID. */
182 unsigned int asid;
183
184} gxio_trio_context_t;
185
186/* Command descriptor for push or pull DMA. */
187typedef TRIO_DMA_DESC_t gxio_trio_dma_desc_t;
188
189/* A convenient, thread-safe interface to an eDMA ring. */
190typedef struct {
191
192 /* State object for tracking head and tail pointers. */
193 __gxio_dma_queue_t dma_queue;
194
195 /* The ring entries. */
196 gxio_trio_dma_desc_t *dma_descs;
197
198 /* The number of entries minus one. */
199 unsigned long mask_num_entries;
200
201 /* The log2() of the number of entries. */
202 unsigned int log2_num_entries;
203
204} gxio_trio_dma_queue_t;
205
206/* Initialize a TRIO context.
207 *
208 * This function allocates a TRIO "service domain" and maps the MMIO
209 * registers into the the caller's VA space.
210 *
211 * @param trio_index Which TRIO shim; Gx36 must pass 0.
212 * @param context Context object to be initialized.
213 */
214extern int gxio_trio_init(gxio_trio_context_t *context,
215 unsigned int trio_index);
216
217/* This indicates that an ASID hasn't been allocated. */
218#define GXIO_ASID_NULL -1
219
220/* Ordering modes for map memory regions and scatter queue regions. */
221typedef enum gxio_trio_order_mode_e {
222 /* Writes are not ordered. Reads always wait for previous writes. */
223 GXIO_TRIO_ORDER_MODE_UNORDERED =
224 TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED,
225 /* Both writes and reads wait for previous transactions to complete. */
226 GXIO_TRIO_ORDER_MODE_STRICT =
227 TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT,
228 /* Writes are ordered unless the incoming packet has the
229 relaxed-ordering attributes set. */
230 GXIO_TRIO_ORDER_MODE_OBEY_PACKET =
231 TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD
232} gxio_trio_order_mode_t;
233
234/* Initialize a memory mapping region.
235 *
236 * @param context An initialized TRIO context.
237 * @param map A Memory map region allocated by gxio_trio_alloc_memory_map().
238 * @param target_mem VA of backing memory, should be registered via
239 * gxio_trio_register_page() and aligned to 4kB.
240 * @param target_size Length of the memory mapping, must be a multiple
241 * of 4kB.
242 * @param asid ASID to be used for Tile-side address translation.
243 * @param mac MAC number.
244 * @param bus_address Bus address at which the mapping starts.
245 * @param order_mode Memory ordering mode for this mapping.
246 * @return Zero on success, else ::GXIO_TRIO_ERR_BAD_MEMORY_MAP,
247 * GXIO_TRIO_ERR_BAD_ASID, or ::GXIO_TRIO_ERR_BAD_BUS_RANGE.
248 */
249extern int gxio_trio_init_memory_map(gxio_trio_context_t *context,
250 unsigned int map, void *target_mem,
251 size_t target_size, unsigned int asid,
252 unsigned int mac, uint64_t bus_address,
253 gxio_trio_order_mode_t order_mode);
254
255/* Flags that can be passed to resource allocation functions. */
256enum gxio_trio_alloc_flags_e {
257 GXIO_TRIO_ALLOC_FIXED = HV_TRIO_ALLOC_FIXED,
258};
259
260/* Flags that can be passed to memory registration functions. */
261enum gxio_trio_mem_flags_e {
262 /* Do not fill L3 when writing, and invalidate lines upon egress. */
263 GXIO_TRIO_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
264
265 /* L3 cache fills should only populate IO cache ways. */
266 GXIO_TRIO_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
267};
268
269/* Flag indicating a request generator uses a special traffic
270 class. */
271#define GXIO_TRIO_FLAG_TRAFFIC_CLASS(N) HV_TRIO_FLAG_TC(N)
272
273/* Flag indicating a request generator uses a virtual function
274 number. */
275#define GXIO_TRIO_FLAG_VFUNC(N) HV_TRIO_FLAG_VFUNC(N)
276
277/*****************************************************************
278 * Memory Registration *
279 ******************************************************************/
280
281/* Allocate Application Space Identifiers (ASIDs). Each ASID can
282 * register up to 16 page translations. ASIDs are used by memory map
283 * regions, scatter queues, and DMA queues to translate application
284 * VAs into memory system PAs.
285 *
286 * @param context An initialized TRIO context.
287 * @param count Number of ASIDs required.
288 * @param first Index of first ASID if ::GXIO_TRIO_ALLOC_FIXED flag
289 * is set, otherwise ignored.
290 * @param flags Flag bits, including bits from ::gxio_trio_alloc_flags_e.
291 * @return Index of first ASID, or ::GXIO_TRIO_ERR_NO_ASID if allocation
292 * failed.
293 */
294extern int gxio_trio_alloc_asids(gxio_trio_context_t *context,
295 unsigned int count, unsigned int first,
296 unsigned int flags);
297
298#endif /* ! _GXIO_TRIO_H_ */
diff --git a/arch/tile/include/hv/drv_trio_intf.h b/arch/tile/include/hv/drv_trio_intf.h
new file mode 100644
index 000000000000..ef9f3f52ee27
--- /dev/null
+++ b/arch/tile/include/hv/drv_trio_intf.h
@@ -0,0 +1,195 @@
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * Interface definitions for the trio driver.
17 */
18
19#ifndef _SYS_HV_DRV_TRIO_INTF_H
20#define _SYS_HV_DRV_TRIO_INTF_H
21
22#include <arch/trio.h>
23
24/** The vendor ID for all Tilera processors. */
25#define TILERA_VENDOR_ID 0x1a41
26
27/** The device ID for the Gx36 processor. */
28#define TILERA_GX36_DEV_ID 0x0200
29
30/** Device ID for our internal bridge when running as RC. */
31#define TILERA_GX36_RC_DEV_ID 0x2000
32
33/** Maximum number of TRIO interfaces. */
34#define TILEGX_NUM_TRIO 2
35
36/** Gx36 has max 3 PCIe MACs per TRIO interface. */
37#define TILEGX_TRIO_PCIES 3
38
39/** Specify port properties for a PCIe MAC. */
40struct pcie_port_property
41{
42 /** If true, the link can be configured in PCIe root complex mode. */
43 uint8_t allow_rc: 1;
44
45 /** If true, the link can be configured in PCIe endpoint mode. */
46 uint8_t allow_ep: 1;
47
48 /** If true, the link can be configured in StreamIO mode. */
49 uint8_t allow_sio: 1;
50
51 /** If true, the link is allowed to support 1-lane operation. Software
52 * will not consider it an error if the link comes up as a x1 link. */
53 uint8_t allow_x1: 1;
54
55 /** If true, the link is allowed to support 2-lane operation. Software
56 * will not consider it an error if the link comes up as a x2 link. */
57 uint8_t allow_x2: 1;
58
59 /** If true, the link is allowed to support 4-lane operation. Software
60 * will not consider it an error if the link comes up as a x4 link. */
61 uint8_t allow_x4: 1;
62
63 /** If true, the link is allowed to support 8-lane operation. Software
64 * will not consider it an error if the link comes up as a x8 link. */
65 uint8_t allow_x8: 1;
66
67 /** Reserved. */
68 uint8_t reserved: 1;
69
70};
71
72/** Configurations can be issued to configure a char stream interrupt. */
73typedef enum pcie_stream_intr_config_sel_e
74{
75 /** Interrupt configuration for memory map regions. */
76 MEM_MAP_SEL,
77
78 /** Interrupt configuration for push DMAs. */
79 PUSH_DMA_SEL,
80
81 /** Interrupt configuration for pull DMAs. */
82 PULL_DMA_SEL,
83}
84pcie_stream_intr_config_sel_t;
85
86
87/** The mmap file offset (PA) of the TRIO config region. */
88#define HV_TRIO_CONFIG_OFFSET \
89 ((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_CFG << \
90 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT)
91
92/** The maximum size of the TRIO config region. */
93#define HV_TRIO_CONFIG_SIZE \
94 (1ULL << TRIO_CFG_REGION_ADDR__REGION_SHIFT)
95
96/** Size of the config region mapped into client. We can't use
97 * TRIO_MMIO_ADDRESS_SPACE__OFFSET_WIDTH because it
98 * will require the kernel to allocate 4GB VA space
99 * from the VMALLOC region which has a total range
100 * of 4GB.
101 */
102#define HV_TRIO_CONFIG_IOREMAP_SIZE \
103 ((uint64_t) 1 << TRIO_CFG_REGION_ADDR__PROT_SHIFT)
104
105/** The mmap file offset (PA) of a scatter queue region. */
106#define HV_TRIO_SQ_OFFSET(queue) \
107 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_SQ << \
108 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
109 ((queue) << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT))
110
111/** The maximum size of a scatter queue region. */
112#define HV_TRIO_SQ_SIZE \
113 (1ULL << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT)
114
115
116/** The "hardware MMIO region" of the first PIO region. */
117#define HV_TRIO_FIRST_PIO_REGION 8
118
119/** The mmap file offset (PA) of a PIO region. */
120#define HV_TRIO_PIO_OFFSET(region) \
121 (((unsigned long long)(region) + HV_TRIO_FIRST_PIO_REGION) \
122 << TRIO_PIO_REGIONS_ADDR__REGION_SHIFT)
123
124/** The maximum size of a PIO region. */
125#define HV_TRIO_PIO_SIZE (1ULL << TRIO_PIO_REGIONS_ADDR__ADDR_WIDTH)
126
127
128/** The mmap file offset (PA) of a push DMA region. */
129#define HV_TRIO_PUSH_DMA_OFFSET(ring) \
130 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PUSH_DMA << \
131 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
132 ((ring) << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT))
133
134/** The mmap file offset (PA) of a pull DMA region. */
135#define HV_TRIO_PULL_DMA_OFFSET(ring) \
136 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PULL_DMA << \
137 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
138 ((ring) << TRIO_PULL_DMA_REGION_ADDR__RING_SEL_SHIFT))
139
140/** The maximum size of a DMA region. */
141#define HV_TRIO_DMA_REGION_SIZE \
142 (1ULL << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT)
143
144
145/** The mmap file offset (PA) of a Mem-Map interrupt region. */
146#define HV_TRIO_MEM_MAP_INTR_OFFSET(map) \
147 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_MEM << \
148 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
149 ((map) << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT))
150
151/** The maximum size of a Mem-Map interrupt region. */
152#define HV_TRIO_MEM_MAP_INTR_SIZE \
153 (1ULL << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT)
154
155
156/** A flag bit indicating a fixed resource allocation. */
157#define HV_TRIO_ALLOC_FIXED 0x01
158
159/** TRIO requires that all mappings have 4kB aligned start addresses. */
160#define HV_TRIO_PAGE_SHIFT 12
161
162/** TRIO requires that all mappings have 4kB aligned start addresses. */
163#define HV_TRIO_PAGE_SIZE (1ull << HV_TRIO_PAGE_SHIFT)
164
165
166/* Specify all PCIe port properties for a TRIO. */
167struct pcie_trio_ports_property
168{
169 struct pcie_port_property ports[TILEGX_TRIO_PCIES];
170};
171
172/* Flags indicating traffic class. */
173#define HV_TRIO_FLAG_TC_SHIFT 4
174#define HV_TRIO_FLAG_TC_RMASK 0xf
175#define HV_TRIO_FLAG_TC(N) \
176 ((((N) & HV_TRIO_FLAG_TC_RMASK) + 1) << HV_TRIO_FLAG_TC_SHIFT)
177
178/* Flags indicating virtual functions. */
179#define HV_TRIO_FLAG_VFUNC_SHIFT 8
180#define HV_TRIO_FLAG_VFUNC_RMASK 0xff
181#define HV_TRIO_FLAG_VFUNC(N) \
182 ((((N) & HV_TRIO_FLAG_VFUNC_RMASK) + 1) << HV_TRIO_FLAG_VFUNC_SHIFT)
183
184
185/* Flag indicating an ordered PIO region. */
186#define HV_TRIO_PIO_FLAG_ORDERED (1 << 16)
187
188/* Flags indicating special types of PIO regions. */
189#define HV_TRIO_PIO_FLAG_SPACE_SHIFT 17
190#define HV_TRIO_PIO_FLAG_SPACE_MASK (0x3 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
191#define HV_TRIO_PIO_FLAG_CONFIG_SPACE (0x1 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
192#define HV_TRIO_PIO_FLAG_IO_SPACE (0x2 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
193
194
195#endif /* _SYS_HV_DRV_TRIO_INTF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 22:04:49 -0500