diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-10-19 19:51:04 -0400 |
---|---|---|
committer | Nicolas Pitre <nico@cam.org> | 2008-12-20 12:27:13 -0500 |
commit | b95a13d79c0e92c9c844fa8aa089c9bd2ed10705 (patch) | |
tree | e1c4c855de14abe955d12e6436eb8dca64dad027 /arch | |
parent | 4c21343005b6b0d6ef24ab6e6a8f3883ff0cb569 (diff) |
[ARM] mv78xx0: implement GPIO and GPIO interrupt support
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/gpio.h | 40 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/irqs.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/irq.c | 29 |
5 files changed, 71 insertions, 6 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d840a64c6ce6..1f08b29b66b9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -429,6 +429,7 @@ config ARCH_MV78XX0 | |||
429 | bool "Marvell MV78xx0" | 429 | bool "Marvell MV78xx0" |
430 | select CPU_FEROCEON | 430 | select CPU_FEROCEON |
431 | select PCI | 431 | select PCI |
432 | select GENERIC_GPIO | ||
432 | select GENERIC_TIME | 433 | select GENERIC_TIME |
433 | select GENERIC_CLOCKEVENTS | 434 | select GENERIC_CLOCKEVENTS |
434 | select PLAT_ORION | 435 | select PLAT_ORION |
diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h new file mode 100644 index 000000000000..d9d1535ea100 --- /dev/null +++ b/arch/arm/mach-mv78xx0/include/mach/gpio.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * arch/asm-arm/mach-mv78xx0/include/mach/gpio.h | ||
3 | * | ||
4 | * This file is licensed under the terms of the GNU General Public | ||
5 | * License version 2. This program is licensed "as is" without any | ||
6 | * warranty of any kind, whether express or implied. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_GPIO_H | ||
10 | #define __ASM_ARCH_GPIO_H | ||
11 | |||
12 | #include <mach/irqs.h> | ||
13 | #include <plat/gpio.h> | ||
14 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
15 | |||
16 | extern int mv78xx0_core_index(void); | ||
17 | |||
18 | #define GPIO_MAX 32 | ||
19 | #define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + 0x0100) | ||
20 | #define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + 0x0104) | ||
21 | #define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + 0x0108) | ||
22 | #define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + 0x010c) | ||
23 | #define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + 0x0110) | ||
24 | #define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + 0x0114) | ||
25 | #define GPIO_MASK_OFF (mv78xx0_core_index() ? 0x18 : 0) | ||
26 | #define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF) | ||
27 | #define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF) | ||
28 | |||
29 | static inline int gpio_to_irq(int pin) | ||
30 | { | ||
31 | return pin + IRQ_MV78XX0_GPIO_START; | ||
32 | } | ||
33 | |||
34 | static inline int irq_to_gpio(int irq) | ||
35 | { | ||
36 | return irq - IRQ_MV78XX0_GPIO_START; | ||
37 | } | ||
38 | |||
39 | |||
40 | #endif | ||
diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h index bebc330281ec..fa1d422196c2 100644 --- a/arch/arm/mach-mv78xx0/include/mach/irqs.h +++ b/arch/arm/mach-mv78xx0/include/mach/irqs.h | |||
@@ -11,8 +11,6 @@ | |||
11 | #ifndef __ASM_ARCH_IRQS_H | 11 | #ifndef __ASM_ARCH_IRQS_H |
12 | #define __ASM_ARCH_IRQS_H | 12 | #define __ASM_ARCH_IRQS_H |
13 | 13 | ||
14 | #include "mv78xx0.h" /* need GPIO_MAX */ | ||
15 | |||
16 | /* | 14 | /* |
17 | * MV78xx0 Low Interrupt Controller | 15 | * MV78xx0 Low Interrupt Controller |
18 | */ | 16 | */ |
@@ -88,7 +86,7 @@ | |||
88 | * MV78XX0 General Purpose Pins | 86 | * MV78XX0 General Purpose Pins |
89 | */ | 87 | */ |
90 | #define IRQ_MV78XX0_GPIO_START 96 | 88 | #define IRQ_MV78XX0_GPIO_START 96 |
91 | #define NR_GPIO_IRQS GPIO_MAX | 89 | #define NR_GPIO_IRQS 32 |
92 | 90 | ||
93 | #define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) | 91 | #define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) |
94 | 92 | ||
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index ee9c5593ee92..e930ea5330a2 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
@@ -122,7 +122,4 @@ | |||
122 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) | 122 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) |
123 | 123 | ||
124 | 124 | ||
125 | #define GPIO_MAX 32 | ||
126 | |||
127 | |||
128 | #endif | 125 | #endif |
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 503e5d195ae5..e273418797b4 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c | |||
@@ -11,13 +11,42 @@ | |||
11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/pci.h> | 13 | #include <linux/pci.h> |
14 | #include <linux/irq.h> | ||
15 | #include <asm/gpio.h> | ||
14 | #include <mach/mv78xx0.h> | 16 | #include <mach/mv78xx0.h> |
15 | #include <plat/irq.h> | 17 | #include <plat/irq.h> |
16 | #include "common.h" | 18 | #include "common.h" |
17 | 19 | ||
20 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
21 | { | ||
22 | BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31); | ||
23 | |||
24 | orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3); | ||
25 | } | ||
26 | |||
18 | void __init mv78xx0_init_irq(void) | 27 | void __init mv78xx0_init_irq(void) |
19 | { | 28 | { |
29 | int i; | ||
30 | |||
20 | orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); | 31 | orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); |
21 | orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); | 32 | orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); |
22 | orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); | 33 | orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); |
34 | |||
35 | /* | ||
36 | * Mask and clear GPIO IRQ interrupts. | ||
37 | */ | ||
38 | writel(0, GPIO_LEVEL_MASK(0)); | ||
39 | writel(0, GPIO_EDGE_MASK(0)); | ||
40 | writel(0, GPIO_EDGE_CAUSE(0)); | ||
41 | |||
42 | for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) { | ||
43 | set_irq_chip(i, &orion_gpio_irq_level_chip); | ||
44 | set_irq_handler(i, handle_level_irq); | ||
45 | irq_desc[i].status |= IRQ_LEVEL; | ||
46 | set_irq_flags(i, IRQF_VALID); | ||
47 | } | ||
48 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); | ||
49 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); | ||
50 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); | ||
51 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); | ||
23 | } | 52 | } |