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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 07:48:18 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:56 -0400
commitac93cdbd6e5e2547a031e2739e0dd445824bf1c8 (patch)
tree88b9e793429d22ca0114bc98e124df2a62edce45 /arch
parent5093aec872e5be7a55d8dd2b639e8a3818dc19db (diff)
arm: at91: Cleanup irq chip
Avoid the whole lazy disable dance in the demux handler by providing a irq_disable() callback. Use the proper accessor functions and tidy up gpio_irq_handler() Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-at91/gpio.c31
1 files changed, 9 insertions, 22 deletions
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 5abcfc016c47..6fd82480756c 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
375 375
376static struct irq_chip gpio_irqchip = { 376static struct irq_chip gpio_irqchip = {
377 .name = "GPIO", 377 .name = "GPIO",
378 .irq_disable = gpio_irq_mask,
378 .irq_mask = gpio_irq_mask, 379 .irq_mask = gpio_irq_mask,
379 .irq_unmask = gpio_irq_unmask, 380 .irq_unmask = gpio_irq_unmask,
380 .irq_set_type = gpio_irq_type, 381 .irq_set_type = gpio_irq_type,
@@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = {
384static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 385static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
385{ 386{
386 unsigned pin; 387 unsigned pin;
387 struct irq_desc *gpio; 388 struct irq_data *idata = irq_desc_get_irq_data(desc);
388 struct at91_gpio_chip *at91_gpio; 389 struct irq_chip *chip = irq_data_get_irq_chip(idata);
389 void __iomem *pio; 390 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
391 void __iomem *pio = at91_gpio->regbase;
390 u32 isr; 392 u32 isr;
391 393
392 at91_gpio = get_irq_chip_data(irq);
393 pio = at91_gpio->regbase;
394
395 /* temporarily mask (level sensitive) parent IRQ */ 394 /* temporarily mask (level sensitive) parent IRQ */
396 desc->irq_data.chip->irq_ack(&desc->irq_data); 395 chip->irq_ack(idata);
397 for (;;) { 396 for (;;) {
398 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 397 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
399 * When there none are pending, we're finished unless we need 398 * When there none are pending, we're finished unless we need
@@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
409 } 408 }
410 409
411 pin = at91_gpio->chip.base; 410 pin = at91_gpio->chip.base;
412 gpio = &irq_desc[pin];
413 411
414 while (isr) { 412 while (isr) {
415 if (isr & 1) { 413 if (isr & 1)
416 if (unlikely(gpio->depth)) { 414 generic_handle_irq(pin);
417 /*
418 * The core ARM interrupt handler lazily disables IRQs so
419 * another IRQ must be generated before it actually gets
420 * here to be disabled on the GPIO controller.
421 */
422 gpio_irq_mask(irq_get_irq_data(pin));
423 }
424 else
425 generic_handle_irq(pin);
426 }
427 pin++; 415 pin++;
428 gpio++;
429 isr >>= 1; 416 isr >>= 1;
430 } 417 }
431 } 418 }
432 desc->irq_data.chip->irq_unmask(&desc->irq_data); 419 chip->irq_unmask(idata);
433 /* now it may re-trigger */ 420 /* now it may re-trigger */
434} 421}
435 422