diff options
author | Paul Walmsley <paul@pwsan.com> | 2011-02-25 16:53:40 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2011-03-07 22:21:17 -0500 |
commit | a4fc92748e969b1312f283b0d1baf657329f2907 (patch) | |
tree | 791bfaed29aaaae3ca7f69911171937288f457ab /arch | |
parent | 691abf525d3d215f2e4eab7a015ef2b6375c58a5 (diff) |
OMAP2xxx: clock: fix clockdomains on gpt7_ick, 2430 mmchs2_fck clocks
Add a clockdomain to the GPTIMER7 interface and 2430 HSMMC2 functional
clocks - both were previously missing them.
Also, the 2430 mmchs1_fck is in core_l3_clkdm, but should be in
core_l4_clkdm; fix this.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/clock2420_data.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2430_data.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 53bd999c63ae..5e80d3dc274c 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
@@ -987,6 +987,7 @@ static struct clk gpt7_ick = { | |||
987 | .name = "gpt7_ick", | 987 | .name = "gpt7_ick", |
988 | .ops = &clkops_omap2_iclk_dflt_wait, | 988 | .ops = &clkops_omap2_iclk_dflt_wait, |
989 | .parent = &l4_ck, | 989 | .parent = &l4_ck, |
990 | .clkdm_name = "core_l4_clkdm", | ||
990 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 991 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
991 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 992 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
992 | .recalc = &followparent_recalc, | 993 | .recalc = &followparent_recalc, |
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 36dde2635acb..8957fc6f64e5 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
@@ -975,6 +975,7 @@ static struct clk gpt7_ick = { | |||
975 | .name = "gpt7_ick", | 975 | .name = "gpt7_ick", |
976 | .ops = &clkops_omap2_iclk_dflt_wait, | 976 | .ops = &clkops_omap2_iclk_dflt_wait, |
977 | .parent = &l4_ck, | 977 | .parent = &l4_ck, |
978 | .clkdm_name = "core_l4_clkdm", | ||
978 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
979 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 980 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
980 | .recalc = &followparent_recalc, | 981 | .recalc = &followparent_recalc, |
@@ -1747,7 +1748,7 @@ static struct clk mmchs1_fck = { | |||
1747 | .name = "mmchs1_fck", | 1748 | .name = "mmchs1_fck", |
1748 | .ops = &clkops_omap2_dflt_wait, | 1749 | .ops = &clkops_omap2_dflt_wait, |
1749 | .parent = &func_96m_ck, | 1750 | .parent = &func_96m_ck, |
1750 | .clkdm_name = "core_l3_clkdm", | 1751 | .clkdm_name = "core_l4_clkdm", |
1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1752 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1752 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 1753 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
1753 | .recalc = &followparent_recalc, | 1754 | .recalc = &followparent_recalc, |
@@ -1767,6 +1768,7 @@ static struct clk mmchs2_fck = { | |||
1767 | .name = "mmchs2_fck", | 1768 | .name = "mmchs2_fck", |
1768 | .ops = &clkops_omap2_dflt_wait, | 1769 | .ops = &clkops_omap2_dflt_wait, |
1769 | .parent = &func_96m_ck, | 1770 | .parent = &func_96m_ck, |
1771 | .clkdm_name = "core_l4_clkdm", | ||
1770 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1771 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 1773 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
1772 | .recalc = &followparent_recalc, | 1774 | .recalc = &followparent_recalc, |