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authorVaibhav Hiremath <hvaibhav@ti.com>2012-07-25 15:51:13 -0400
committerPaul Walmsley <paul@pwsan.com>2012-09-11 19:18:58 -0400
commita2cfc509bc4eeef9f5c4607b1203f17f22ea2a36 (patch)
tree4f11e673f6b24915d3cf2d09e48a00f2b35889ce /arch
parent1688bf19b8daaa2eb4e861c33a6396ca85b890c3 (diff)
ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
This patch adds HWMOD data for all the peripherals of AM335X device and also hooks up to the existing OMAP framework. hwmod data has been already been cleaned up for the recent changes in clocktree, where all leaf nodes have been removed, since with modulemode based control, both clock and hwmod interface does same thing. This reduces the code size to large extent and also avoids duplication of same control. So instead of specifying module's leaf node as a main_clk, now we are relying on parent clock of module's functional clock. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: removed period in hwmod device names; changed mmc2 main_clk to mmc_clk at Vaibhav's request; added trailing commas to structure records at Tony's request to deal with some rmk parsing issues; added OMAP_INTC_START to facilitate sparse-IRQ conversion] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c3384
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h1
4 files changed, 3388 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3f9c4f..b3603282d75f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
194obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o 194obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
195obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o 195obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
196obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 196obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
197obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
197obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 198obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
198 199
199# EMU peripherals 200# EMU peripherals
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981ff5c5..408b3f058e51 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -523,6 +523,8 @@ void __init am33xx_init_early(void)
523 am33xx_voltagedomains_init(); 523 am33xx_voltagedomains_init();
524 am33xx_powerdomains_init(); 524 am33xx_powerdomains_init();
525 am33xx_clockdomains_init(); 525 am33xx_clockdomains_init();
526 am33xx_hwmod_init();
527 omap_hwmod_init_postsetup();
526 am33xx_clk_init(); 528 am33xx_clk_init();
527} 529}
528#endif 530#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 000000000000..656f54deb6d8
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3384 @@
1/*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <plat/omap_hwmod.h>
18#include <plat/cpu.h>
19#include <plat/gpio.h>
20#include <plat/dma.h>
21#include <plat/mmc.h>
22#include <plat/mcspi.h>
23#include <plat/i2c.h>
24
25#include "omap_hwmod_common_data.h"
26
27#include "control.h"
28#include "cm33xx.h"
29#include "prm33xx.h"
30#include "prm-regbits-33xx.h"
31
32/* XXX Remove this during the sparseirq conversion */
33#define OMAP_INTC_START 0
34
35/*
36 * IP blocks
37 */
38
39/*
40 * 'emif_fw' class
41 * instance(s): emif_fw
42 */
43static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
44 .name = "emif_fw",
45};
46
47/* emif_fw */
48static struct omap_hwmod am33xx_emif_fw_hwmod = {
49 .name = "emif_fw",
50 .class = &am33xx_emif_fw_hwmod_class,
51 .clkdm_name = "l4fw_clkdm",
52 .main_clk = "l4fw_gclk",
53 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
54 .prcm = {
55 .omap4 = {
56 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
57 .modulemode = MODULEMODE_SWCTRL,
58 },
59 },
60};
61
62/*
63 * 'emif' class
64 * instance(s): emif
65 */
66static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
67 .rev_offs = 0x0000,
68};
69
70static struct omap_hwmod_class am33xx_emif_hwmod_class = {
71 .name = "emif",
72 .sysc = &am33xx_emif_sysc,
73};
74
75static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
76 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
77 { .irq = -1 },
78};
79
80/* emif */
81static struct omap_hwmod am33xx_emif_hwmod = {
82 .name = "emif",
83 .class = &am33xx_emif_hwmod_class,
84 .clkdm_name = "l3_clkdm",
85 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
86 .mpu_irqs = am33xx_emif_irqs,
87 .main_clk = "dpll_ddr_m2_div2_ck",
88 .prcm = {
89 .omap4 = {
90 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
91 .modulemode = MODULEMODE_SWCTRL,
92 },
93 },
94};
95
96/*
97 * 'l3' class
98 * instance(s): l3_main, l3_s, l3_instr
99 */
100static struct omap_hwmod_class am33xx_l3_hwmod_class = {
101 .name = "l3",
102};
103
104/* l3_main (l3_fast) */
105static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
106 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
107 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
108 { .irq = -1 },
109};
110
111static struct omap_hwmod am33xx_l3_main_hwmod = {
112 .name = "l3_main",
113 .class = &am33xx_l3_hwmod_class,
114 .clkdm_name = "l3_clkdm",
115 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
116 .mpu_irqs = am33xx_l3_main_irqs,
117 .main_clk = "l3_gclk",
118 .prcm = {
119 .omap4 = {
120 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
121 .modulemode = MODULEMODE_SWCTRL,
122 },
123 },
124};
125
126/* l3_s */
127static struct omap_hwmod am33xx_l3_s_hwmod = {
128 .name = "l3_s",
129 .class = &am33xx_l3_hwmod_class,
130 .clkdm_name = "l3s_clkdm",
131};
132
133/* l3_instr */
134static struct omap_hwmod am33xx_l3_instr_hwmod = {
135 .name = "l3_instr",
136 .class = &am33xx_l3_hwmod_class,
137 .clkdm_name = "l3_clkdm",
138 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
139 .main_clk = "l3_gclk",
140 .prcm = {
141 .omap4 = {
142 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
143 .modulemode = MODULEMODE_SWCTRL,
144 },
145 },
146};
147
148/*
149 * 'l4' class
150 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
151 */
152static struct omap_hwmod_class am33xx_l4_hwmod_class = {
153 .name = "l4",
154};
155
156/* l4_ls */
157static struct omap_hwmod am33xx_l4_ls_hwmod = {
158 .name = "l4_ls",
159 .class = &am33xx_l4_hwmod_class,
160 .clkdm_name = "l4ls_clkdm",
161 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
162 .main_clk = "l4ls_gclk",
163 .prcm = {
164 .omap4 = {
165 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
166 .modulemode = MODULEMODE_SWCTRL,
167 },
168 },
169};
170
171/* l4_hs */
172static struct omap_hwmod am33xx_l4_hs_hwmod = {
173 .name = "l4_hs",
174 .class = &am33xx_l4_hwmod_class,
175 .clkdm_name = "l4hs_clkdm",
176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
177 .main_clk = "l4hs_gclk",
178 .prcm = {
179 .omap4 = {
180 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
181 .modulemode = MODULEMODE_SWCTRL,
182 },
183 },
184};
185
186
187/* l4_wkup */
188static struct omap_hwmod am33xx_l4_wkup_hwmod = {
189 .name = "l4_wkup",
190 .class = &am33xx_l4_hwmod_class,
191 .clkdm_name = "l4_wkup_clkdm",
192 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
193 .prcm = {
194 .omap4 = {
195 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
196 .modulemode = MODULEMODE_SWCTRL,
197 },
198 },
199};
200
201/* l4_fw */
202static struct omap_hwmod am33xx_l4_fw_hwmod = {
203 .name = "l4_fw",
204 .class = &am33xx_l4_hwmod_class,
205 .clkdm_name = "l4fw_clkdm",
206 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
207 .prcm = {
208 .omap4 = {
209 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
210 .modulemode = MODULEMODE_SWCTRL,
211 },
212 },
213};
214
215/*
216 * 'mpu' class
217 */
218static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
219 .name = "mpu",
220};
221
222/* mpu */
223static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
224 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
225 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
226 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
227 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
228 { .irq = -1 },
229};
230
231static struct omap_hwmod am33xx_mpu_hwmod = {
232 .name = "mpu",
233 .class = &am33xx_mpu_hwmod_class,
234 .clkdm_name = "mpu_clkdm",
235 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
236 .mpu_irqs = am33xx_mpu_irqs,
237 .main_clk = "dpll_mpu_m2_ck",
238 .prcm = {
239 .omap4 = {
240 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
241 .modulemode = MODULEMODE_SWCTRL,
242 },
243 },
244};
245
246/*
247 * 'wakeup m3' class
248 * Wakeup controller sub-system under wakeup domain
249 */
250static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
251 .name = "wkup_m3",
252};
253
254static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
255 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
256};
257
258static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
259 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
260 { .irq = -1 },
261};
262
263/* wkup_m3 */
264static struct omap_hwmod am33xx_wkup_m3_hwmod = {
265 .name = "wkup_m3",
266 .class = &am33xx_wkup_m3_hwmod_class,
267 .clkdm_name = "l4_wkup_aon_clkdm",
268 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
269 .mpu_irqs = am33xx_wkup_m3_irqs,
270 .main_clk = "dpll_core_m4_div2_ck",
271 .prcm = {
272 .omap4 = {
273 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
274 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
275 .modulemode = MODULEMODE_SWCTRL,
276 },
277 },
278 .rst_lines = am33xx_wkup_m3_resets,
279 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
280};
281
282/*
283 * 'pru-icss' class
284 * Programmable Real-Time Unit and Industrial Communication Subsystem
285 */
286static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
287 .name = "pruss",
288};
289
290static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
291 { .name = "pruss", .rst_shift = 1 },
292};
293
294static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
295 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
296 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
297 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
298 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
299 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
300 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
301 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
302 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
303 { .irq = -1 },
304};
305
306/* pru-icss */
307/* Pseudo hwmod for reset control purpose only */
308static struct omap_hwmod am33xx_pruss_hwmod = {
309 .name = "pruss",
310 .class = &am33xx_pruss_hwmod_class,
311 .clkdm_name = "pruss_ocp_clkdm",
312 .mpu_irqs = am33xx_pruss_irqs,
313 .main_clk = "pruss_ocp_gclk",
314 .prcm = {
315 .omap4 = {
316 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
317 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
318 .modulemode = MODULEMODE_SWCTRL,
319 },
320 },
321 .rst_lines = am33xx_pruss_resets,
322 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
323};
324
325/* gfx */
326/* Pseudo hwmod for reset control purpose only */
327static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
328 .name = "gfx",
329};
330
331static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
332 { .name = "gfx", .rst_shift = 0 },
333};
334
335static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
336 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
337 { .irq = -1 },
338};
339
340static struct omap_hwmod am33xx_gfx_hwmod = {
341 .name = "gfx",
342 .class = &am33xx_gfx_hwmod_class,
343 .clkdm_name = "gfx_l3_clkdm",
344 .mpu_irqs = am33xx_gfx_irqs,
345 .main_clk = "gfx_fck_div_ck",
346 .prcm = {
347 .omap4 = {
348 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
349 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
350 .modulemode = MODULEMODE_SWCTRL,
351 },
352 },
353 .rst_lines = am33xx_gfx_resets,
354 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
355};
356
357/*
358 * 'prcm' class
359 * power and reset manager (whole prcm infrastructure)
360 */
361static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
362 .name = "prcm",
363};
364
365/* prcm */
366static struct omap_hwmod am33xx_prcm_hwmod = {
367 .name = "prcm",
368 .class = &am33xx_prcm_hwmod_class,
369 .clkdm_name = "l4_wkup_clkdm",
370};
371
372/*
373 * 'adc/tsc' class
374 * TouchScreen Controller (Anolog-To-Digital Converter)
375 */
376static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
377 .rev_offs = 0x00,
378 .sysc_offs = 0x10,
379 .sysc_flags = SYSC_HAS_SIDLEMODE,
380 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
381 SIDLE_SMART_WKUP),
382 .sysc_fields = &omap_hwmod_sysc_type2,
383};
384
385static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
386 .name = "adc_tsc",
387 .sysc = &am33xx_adc_tsc_sysc,
388};
389
390static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
391 { .irq = 16 + OMAP_INTC_START, },
392 { .irq = -1 },
393};
394
395static struct omap_hwmod am33xx_adc_tsc_hwmod = {
396 .name = "adc_tsc",
397 .class = &am33xx_adc_tsc_hwmod_class,
398 .clkdm_name = "l4_wkup_clkdm",
399 .mpu_irqs = am33xx_adc_tsc_irqs,
400 .main_clk = "adc_tsc_fck",
401 .prcm = {
402 .omap4 = {
403 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
404 .modulemode = MODULEMODE_SWCTRL,
405 },
406 },
407};
408
409/*
410 * Modules omap_hwmod structures
411 *
412 * The following IPs are excluded for the moment because:
413 * - They do not need an explicit SW control using omap_hwmod API.
414 * - They still need to be validated with the driver
415 * properly adapted to omap_hwmod / omap_device
416 *
417 * - cEFUSE (doesn't fall under any ocp_if)
418 * - clkdiv32k
419 * - debugss
420 * - ocmc ram
421 * - ocp watch point
422 * - aes0
423 * - sha0
424 */
425#if 0
426/*
427 * 'cefuse' class
428 */
429static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
430 .name = "cefuse",
431};
432
433static struct omap_hwmod am33xx_cefuse_hwmod = {
434 .name = "cefuse",
435 .class = &am33xx_cefuse_hwmod_class,
436 .clkdm_name = "l4_cefuse_clkdm",
437 .main_clk = "cefuse_fck",
438 .prcm = {
439 .omap4 = {
440 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
441 .modulemode = MODULEMODE_SWCTRL,
442 },
443 },
444};
445
446/*
447 * 'clkdiv32k' class
448 */
449static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
450 .name = "clkdiv32k",
451};
452
453static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
454 .name = "clkdiv32k",
455 .class = &am33xx_clkdiv32k_hwmod_class,
456 .clkdm_name = "clk_24mhz_clkdm",
457 .main_clk = "clkdiv32k_ick",
458 .prcm = {
459 .omap4 = {
460 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
461 .modulemode = MODULEMODE_SWCTRL,
462 },
463 },
464};
465
466/*
467 * 'debugss' class
468 * debug sub system
469 */
470static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
471 .name = "debugss",
472};
473
474static struct omap_hwmod am33xx_debugss_hwmod = {
475 .name = "debugss",
476 .class = &am33xx_debugss_hwmod_class,
477 .clkdm_name = "l3_aon_clkdm",
478 .main_clk = "debugss_ick",
479 .prcm = {
480 .omap4 = {
481 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
482 .modulemode = MODULEMODE_SWCTRL,
483 },
484 },
485};
486
487/* ocmcram */
488static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
489 .name = "ocmcram",
490};
491
492static struct omap_hwmod am33xx_ocmcram_hwmod = {
493 .name = "ocmcram",
494 .class = &am33xx_ocmcram_hwmod_class,
495 .clkdm_name = "l3_clkdm",
496 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
497 .main_clk = "l3_gclk",
498 .prcm = {
499 .omap4 = {
500 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
501 .modulemode = MODULEMODE_SWCTRL,
502 },
503 },
504};
505
506/* ocpwp */
507static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
508 .name = "ocpwp",
509};
510
511static struct omap_hwmod am33xx_ocpwp_hwmod = {
512 .name = "ocpwp",
513 .class = &am33xx_ocpwp_hwmod_class,
514 .clkdm_name = "l4ls_clkdm",
515 .main_clk = "l4ls_gclk",
516 .prcm = {
517 .omap4 = {
518 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
519 .modulemode = MODULEMODE_SWCTRL,
520 },
521 },
522};
523
524/*
525 * 'aes' class
526 */
527static struct omap_hwmod_class am33xx_aes_hwmod_class = {
528 .name = "aes",
529};
530
531static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
532 { .irq = 102 + OMAP_INTC_START, },
533 { .irq = -1 },
534};
535
536static struct omap_hwmod am33xx_aes0_hwmod = {
537 .name = "aes0",
538 .class = &am33xx_aes_hwmod_class,
539 .clkdm_name = "l3_clkdm",
540 .mpu_irqs = am33xx_aes0_irqs,
541 .main_clk = "l3_gclk",
542 .prcm = {
543 .omap4 = {
544 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
545 .modulemode = MODULEMODE_SWCTRL,
546 },
547 },
548};
549
550/* sha0 */
551static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
552 .name = "sha0",
553};
554
555static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
556 { .irq = 108 + OMAP_INTC_START, },
557 { .irq = -1 },
558};
559
560static struct omap_hwmod am33xx_sha0_hwmod = {
561 .name = "sha0",
562 .class = &am33xx_sha0_hwmod_class,
563 .clkdm_name = "l3_clkdm",
564 .mpu_irqs = am33xx_sha0_irqs,
565 .main_clk = "l3_gclk",
566 .prcm = {
567 .omap4 = {
568 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
570 },
571 },
572};
573
574#endif
575
576/* 'smartreflex' class */
577static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
578 .name = "smartreflex",
579};
580
581/* smartreflex0 */
582static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
583 { .irq = 120 + OMAP_INTC_START, },
584 { .irq = -1 },
585};
586
587static struct omap_hwmod am33xx_smartreflex0_hwmod = {
588 .name = "smartreflex0",
589 .class = &am33xx_smartreflex_hwmod_class,
590 .clkdm_name = "l4_wkup_clkdm",
591 .mpu_irqs = am33xx_smartreflex0_irqs,
592 .main_clk = "smartreflex0_fck",
593 .prcm = {
594 .omap4 = {
595 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
596 .modulemode = MODULEMODE_SWCTRL,
597 },
598 },
599};
600
601/* smartreflex1 */
602static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
603 { .irq = 121 + OMAP_INTC_START, },
604 { .irq = -1 },
605};
606
607static struct omap_hwmod am33xx_smartreflex1_hwmod = {
608 .name = "smartreflex1",
609 .class = &am33xx_smartreflex_hwmod_class,
610 .clkdm_name = "l4_wkup_clkdm",
611 .mpu_irqs = am33xx_smartreflex1_irqs,
612 .main_clk = "smartreflex1_fck",
613 .prcm = {
614 .omap4 = {
615 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
616 .modulemode = MODULEMODE_SWCTRL,
617 },
618 },
619};
620
621/*
622 * 'control' module class
623 */
624static struct omap_hwmod_class am33xx_control_hwmod_class = {
625 .name = "control",
626};
627
628static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
629 { .irq = 8 + OMAP_INTC_START, },
630 { .irq = -1 },
631};
632
633static struct omap_hwmod am33xx_control_hwmod = {
634 .name = "control",
635 .class = &am33xx_control_hwmod_class,
636 .clkdm_name = "l4_wkup_clkdm",
637 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
638 .mpu_irqs = am33xx_control_irqs,
639 .main_clk = "dpll_core_m4_div2_ck",
640 .prcm = {
641 .omap4 = {
642 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
643 .modulemode = MODULEMODE_SWCTRL,
644 },
645 },
646};
647
648/*
649 * 'cpgmac' class
650 * cpsw/cpgmac sub system
651 */
652static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
653 .rev_offs = 0x0,
654 .sysc_offs = 0x8,
655 .syss_offs = 0x4,
656 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
657 SYSS_HAS_RESET_STATUS),
658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
659 MSTANDBY_NO),
660 .sysc_fields = &omap_hwmod_sysc_type3,
661};
662
663static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
664 .name = "cpgmac0",
665 .sysc = &am33xx_cpgmac_sysc,
666};
667
668static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
669 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
670 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
671 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
672 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
673 { .irq = -1 },
674};
675
676static struct omap_hwmod am33xx_cpgmac0_hwmod = {
677 .name = "cpgmac0",
678 .class = &am33xx_cpgmac0_hwmod_class,
679 .clkdm_name = "cpsw_125mhz_clkdm",
680 .mpu_irqs = am33xx_cpgmac0_irqs,
681 .main_clk = "cpsw_125mhz_gclk",
682 .prcm = {
683 .omap4 = {
684 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
685 .modulemode = MODULEMODE_SWCTRL,
686 },
687 },
688};
689
690/*
691 * dcan class
692 */
693static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
694 .name = "d_can",
695};
696
697/* dcan0 */
698static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
699 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
700 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
701 { .irq = -1 },
702};
703
704static struct omap_hwmod am33xx_dcan0_hwmod = {
705 .name = "d_can0",
706 .class = &am33xx_dcan_hwmod_class,
707 .clkdm_name = "l4ls_clkdm",
708 .mpu_irqs = am33xx_dcan0_irqs,
709 .main_clk = "dcan0_fck",
710 .prcm = {
711 .omap4 = {
712 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
713 .modulemode = MODULEMODE_SWCTRL,
714 },
715 },
716};
717
718/* dcan1 */
719static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
720 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
721 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
722 { .irq = -1 },
723};
724static struct omap_hwmod am33xx_dcan1_hwmod = {
725 .name = "d_can1",
726 .class = &am33xx_dcan_hwmod_class,
727 .clkdm_name = "l4ls_clkdm",
728 .mpu_irqs = am33xx_dcan1_irqs,
729 .main_clk = "dcan1_fck",
730 .prcm = {
731 .omap4 = {
732 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
733 .modulemode = MODULEMODE_SWCTRL,
734 },
735 },
736};
737
738/* elm */
739static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
740 .rev_offs = 0x0000,
741 .sysc_offs = 0x0010,
742 .syss_offs = 0x0014,
743 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
744 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
745 SYSS_HAS_RESET_STATUS),
746 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
747 .sysc_fields = &omap_hwmod_sysc_type1,
748};
749
750static struct omap_hwmod_class am33xx_elm_hwmod_class = {
751 .name = "elm",
752 .sysc = &am33xx_elm_sysc,
753};
754
755static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
756 { .irq = 4 + OMAP_INTC_START, },
757 { .irq = -1 },
758};
759
760static struct omap_hwmod am33xx_elm_hwmod = {
761 .name = "elm",
762 .class = &am33xx_elm_hwmod_class,
763 .clkdm_name = "l4ls_clkdm",
764 .mpu_irqs = am33xx_elm_irqs,
765 .main_clk = "l4ls_gclk",
766 .prcm = {
767 .omap4 = {
768 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
769 .modulemode = MODULEMODE_SWCTRL,
770 },
771 },
772};
773
774/*
775 * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
776 */
777static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
778 .rev_offs = 0x0,
779 .sysc_offs = 0x4,
780 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
781 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
782 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
783 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
784 .sysc_fields = &omap_hwmod_sysc_type2,
785};
786
787static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
788 .name = "epwmss",
789 .sysc = &am33xx_epwmss_sysc,
790};
791
792/* ehrpwm0 */
793static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
794 { .name = "int", .irq = 86 + OMAP_INTC_START, },
795 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
796 { .irq = -1 },
797};
798
799static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
800 .name = "ehrpwm0",
801 .class = &am33xx_epwmss_hwmod_class,
802 .clkdm_name = "l4ls_clkdm",
803 .mpu_irqs = am33xx_ehrpwm0_irqs,
804 .main_clk = "l4ls_gclk",
805 .prcm = {
806 .omap4 = {
807 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
808 .modulemode = MODULEMODE_SWCTRL,
809 },
810 },
811};
812
813/* ehrpwm1 */
814static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
815 { .name = "int", .irq = 87 + OMAP_INTC_START, },
816 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
817 { .irq = -1 },
818};
819
820static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
821 .name = "ehrpwm1",
822 .class = &am33xx_epwmss_hwmod_class,
823 .clkdm_name = "l4ls_clkdm",
824 .mpu_irqs = am33xx_ehrpwm1_irqs,
825 .main_clk = "l4ls_gclk",
826 .prcm = {
827 .omap4 = {
828 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
829 .modulemode = MODULEMODE_SWCTRL,
830 },
831 },
832};
833
834/* ehrpwm2 */
835static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
836 { .name = "int", .irq = 39 + OMAP_INTC_START, },
837 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
838 { .irq = -1 },
839};
840
841static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
842 .name = "ehrpwm2",
843 .class = &am33xx_epwmss_hwmod_class,
844 .clkdm_name = "l4ls_clkdm",
845 .mpu_irqs = am33xx_ehrpwm2_irqs,
846 .main_clk = "l4ls_gclk",
847 .prcm = {
848 .omap4 = {
849 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
850 .modulemode = MODULEMODE_SWCTRL,
851 },
852 },
853};
854
855/* ecap0 */
856static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
857 { .irq = 31 + OMAP_INTC_START, },
858 { .irq = -1 },
859};
860
861static struct omap_hwmod am33xx_ecap0_hwmod = {
862 .name = "ecap0",
863 .class = &am33xx_epwmss_hwmod_class,
864 .clkdm_name = "l4ls_clkdm",
865 .mpu_irqs = am33xx_ecap0_irqs,
866 .main_clk = "l4ls_gclk",
867 .prcm = {
868 .omap4 = {
869 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
870 .modulemode = MODULEMODE_SWCTRL,
871 },
872 },
873};
874
875/* ecap1 */
876static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
877 { .irq = 47 + OMAP_INTC_START, },
878 { .irq = -1 },
879};
880
881static struct omap_hwmod am33xx_ecap1_hwmod = {
882 .name = "ecap1",
883 .class = &am33xx_epwmss_hwmod_class,
884 .clkdm_name = "l4ls_clkdm",
885 .mpu_irqs = am33xx_ecap1_irqs,
886 .main_clk = "l4ls_gclk",
887 .prcm = {
888 .omap4 = {
889 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
890 .modulemode = MODULEMODE_SWCTRL,
891 },
892 },
893};
894
895/* ecap2 */
896static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
897 { .irq = 61 + OMAP_INTC_START, },
898 { .irq = -1 },
899};
900
901static struct omap_hwmod am33xx_ecap2_hwmod = {
902 .name = "ecap2",
903 .mpu_irqs = am33xx_ecap2_irqs,
904 .class = &am33xx_epwmss_hwmod_class,
905 .clkdm_name = "l4ls_clkdm",
906 .main_clk = "l4ls_gclk",
907 .prcm = {
908 .omap4 = {
909 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
910 .modulemode = MODULEMODE_SWCTRL,
911 },
912 },
913};
914
915/*
916 * 'gpio' class: for gpio 0,1,2,3
917 */
918static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
919 .rev_offs = 0x0000,
920 .sysc_offs = 0x0010,
921 .syss_offs = 0x0114,
922 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
923 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
924 SYSS_HAS_RESET_STATUS),
925 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
926 SIDLE_SMART_WKUP),
927 .sysc_fields = &omap_hwmod_sysc_type1,
928};
929
930static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
931 .name = "gpio",
932 .sysc = &am33xx_gpio_sysc,
933 .rev = 2,
934};
935
936static struct omap_gpio_dev_attr gpio_dev_attr = {
937 .bank_width = 32,
938 .dbck_flag = true,
939};
940
941/* gpio0 */
942static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
943 { .role = "dbclk", .clk = "gpio0_dbclk" },
944};
945
946static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
947 { .irq = 96 + OMAP_INTC_START, },
948 { .irq = -1 },
949};
950
951static struct omap_hwmod am33xx_gpio0_hwmod = {
952 .name = "gpio1",
953 .class = &am33xx_gpio_hwmod_class,
954 .clkdm_name = "l4_wkup_clkdm",
955 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
956 .mpu_irqs = am33xx_gpio0_irqs,
957 .main_clk = "dpll_core_m4_div2_ck",
958 .prcm = {
959 .omap4 = {
960 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
961 .modulemode = MODULEMODE_SWCTRL,
962 },
963 },
964 .opt_clks = gpio0_opt_clks,
965 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
966 .dev_attr = &gpio_dev_attr,
967};
968
969/* gpio1 */
970static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
971 { .irq = 98 + OMAP_INTC_START, },
972 { .irq = -1 },
973};
974
975static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
976 { .role = "dbclk", .clk = "gpio1_dbclk" },
977};
978
979static struct omap_hwmod am33xx_gpio1_hwmod = {
980 .name = "gpio2",
981 .class = &am33xx_gpio_hwmod_class,
982 .clkdm_name = "l4ls_clkdm",
983 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
984 .mpu_irqs = am33xx_gpio1_irqs,
985 .main_clk = "l4ls_gclk",
986 .prcm = {
987 .omap4 = {
988 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
989 .modulemode = MODULEMODE_SWCTRL,
990 },
991 },
992 .opt_clks = gpio1_opt_clks,
993 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
994 .dev_attr = &gpio_dev_attr,
995};
996
997/* gpio2 */
998static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
999 { .irq = 32 + OMAP_INTC_START, },
1000 { .irq = -1 },
1001};
1002
1003static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1004 { .role = "dbclk", .clk = "gpio2_dbclk" },
1005};
1006
1007static struct omap_hwmod am33xx_gpio2_hwmod = {
1008 .name = "gpio3",
1009 .class = &am33xx_gpio_hwmod_class,
1010 .clkdm_name = "l4ls_clkdm",
1011 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1012 .mpu_irqs = am33xx_gpio2_irqs,
1013 .main_clk = "l4ls_gclk",
1014 .prcm = {
1015 .omap4 = {
1016 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1017 .modulemode = MODULEMODE_SWCTRL,
1018 },
1019 },
1020 .opt_clks = gpio2_opt_clks,
1021 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1022 .dev_attr = &gpio_dev_attr,
1023};
1024
1025/* gpio3 */
1026static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1027 { .irq = 62 + OMAP_INTC_START, },
1028 { .irq = -1 },
1029};
1030
1031static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1032 { .role = "dbclk", .clk = "gpio3_dbclk" },
1033};
1034
1035static struct omap_hwmod am33xx_gpio3_hwmod = {
1036 .name = "gpio4",
1037 .class = &am33xx_gpio_hwmod_class,
1038 .clkdm_name = "l4ls_clkdm",
1039 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1040 .mpu_irqs = am33xx_gpio3_irqs,
1041 .main_clk = "l4ls_gclk",
1042 .prcm = {
1043 .omap4 = {
1044 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1045 .modulemode = MODULEMODE_SWCTRL,
1046 },
1047 },
1048 .opt_clks = gpio3_opt_clks,
1049 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1050 .dev_attr = &gpio_dev_attr,
1051};
1052
1053/* gpmc */
1054static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1055 .rev_offs = 0x0,
1056 .sysc_offs = 0x10,
1057 .syss_offs = 0x14,
1058 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1059 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1060 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1061 .sysc_fields = &omap_hwmod_sysc_type1,
1062};
1063
1064static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1065 .name = "gpmc",
1066 .sysc = &gpmc_sysc,
1067};
1068
1069static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1070 { .irq = 100 + OMAP_INTC_START, },
1071 { .irq = -1 },
1072};
1073
1074static struct omap_hwmod am33xx_gpmc_hwmod = {
1075 .name = "gpmc",
1076 .class = &am33xx_gpmc_hwmod_class,
1077 .clkdm_name = "l3s_clkdm",
1078 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1079 .mpu_irqs = am33xx_gpmc_irqs,
1080 .main_clk = "l3s_gclk",
1081 .prcm = {
1082 .omap4 = {
1083 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1084 .modulemode = MODULEMODE_SWCTRL,
1085 },
1086 },
1087};
1088
1089/* 'i2c' class */
1090static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1091 .sysc_offs = 0x0010,
1092 .syss_offs = 0x0090,
1093 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1094 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1095 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1096 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1097 SIDLE_SMART_WKUP),
1098 .sysc_fields = &omap_hwmod_sysc_type1,
1099};
1100
1101static struct omap_hwmod_class i2c_class = {
1102 .name = "i2c",
1103 .sysc = &am33xx_i2c_sysc,
1104 .rev = OMAP_I2C_IP_VERSION_2,
1105 .reset = &omap_i2c_reset,
1106};
1107
1108static struct omap_i2c_dev_attr i2c_dev_attr = {
1109 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1110 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1111};
1112
1113/* i2c1 */
1114static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1115 { .irq = 70 + OMAP_INTC_START, },
1116 { .irq = -1 },
1117};
1118
1119static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1120 { .name = "tx", .dma_req = 0, },
1121 { .name = "rx", .dma_req = 0, },
1122 { .dma_req = -1 }
1123};
1124
1125static struct omap_hwmod am33xx_i2c1_hwmod = {
1126 .name = "i2c1",
1127 .class = &i2c_class,
1128 .clkdm_name = "l4_wkup_clkdm",
1129 .mpu_irqs = i2c1_mpu_irqs,
1130 .sdma_reqs = i2c1_edma_reqs,
1131 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1132 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1133 .prcm = {
1134 .omap4 = {
1135 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1136 .modulemode = MODULEMODE_SWCTRL,
1137 },
1138 },
1139 .dev_attr = &i2c_dev_attr,
1140};
1141
1142/* i2c1 */
1143static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1144 { .irq = 71 + OMAP_INTC_START, },
1145 { .irq = -1 },
1146};
1147
1148static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1149 { .name = "tx", .dma_req = 0, },
1150 { .name = "rx", .dma_req = 0, },
1151 { .dma_req = -1 }
1152};
1153
1154static struct omap_hwmod am33xx_i2c2_hwmod = {
1155 .name = "i2c2",
1156 .class = &i2c_class,
1157 .clkdm_name = "l4ls_clkdm",
1158 .mpu_irqs = i2c2_mpu_irqs,
1159 .sdma_reqs = i2c2_edma_reqs,
1160 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1161 .main_clk = "dpll_per_m2_div4_ck",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1165 .modulemode = MODULEMODE_SWCTRL,
1166 },
1167 },
1168 .dev_attr = &i2c_dev_attr,
1169};
1170
1171/* i2c3 */
1172static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1173 { .name = "tx", .dma_req = 0, },
1174 { .name = "rx", .dma_req = 0, },
1175 { .dma_req = -1 }
1176};
1177
1178static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1179 { .irq = 30 + OMAP_INTC_START, },
1180 { .irq = -1 },
1181};
1182
1183static struct omap_hwmod am33xx_i2c3_hwmod = {
1184 .name = "i2c3",
1185 .class = &i2c_class,
1186 .clkdm_name = "l4ls_clkdm",
1187 .mpu_irqs = i2c3_mpu_irqs,
1188 .sdma_reqs = i2c3_edma_reqs,
1189 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1190 .main_clk = "dpll_per_m2_div4_ck",
1191 .prcm = {
1192 .omap4 = {
1193 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1194 .modulemode = MODULEMODE_SWCTRL,
1195 },
1196 },
1197 .dev_attr = &i2c_dev_attr,
1198};
1199
1200
1201/* lcdc */
1202static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1203 .rev_offs = 0x0,
1204 .sysc_offs = 0x54,
1205 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1207 .sysc_fields = &omap_hwmod_sysc_type2,
1208};
1209
1210static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1211 .name = "lcdc",
1212 .sysc = &lcdc_sysc,
1213};
1214
1215static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1216 { .irq = 36 + OMAP_INTC_START, },
1217 { .irq = -1 },
1218};
1219
1220static struct omap_hwmod am33xx_lcdc_hwmod = {
1221 .name = "lcdc",
1222 .class = &am33xx_lcdc_hwmod_class,
1223 .clkdm_name = "lcdc_clkdm",
1224 .mpu_irqs = am33xx_lcdc_irqs,
1225 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1226 .main_clk = "lcd_gclk",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1230 .modulemode = MODULEMODE_SWCTRL,
1231 },
1232 },
1233};
1234
1235/*
1236 * 'mailbox' class
1237 * mailbox module allowing communication between the on-chip processors using a
1238 * queued mailbox-interrupt mechanism.
1239 */
1240static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1241 .rev_offs = 0x0000,
1242 .sysc_offs = 0x0010,
1243 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1244 SYSC_HAS_SOFTRESET),
1245 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1246 .sysc_fields = &omap_hwmod_sysc_type2,
1247};
1248
1249static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1250 .name = "mailbox",
1251 .sysc = &am33xx_mailbox_sysc,
1252};
1253
1254static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1255 { .irq = 77 + OMAP_INTC_START, },
1256 { .irq = -1 },
1257};
1258
1259static struct omap_hwmod am33xx_mailbox_hwmod = {
1260 .name = "mailbox",
1261 .class = &am33xx_mailbox_hwmod_class,
1262 .clkdm_name = "l4ls_clkdm",
1263 .mpu_irqs = am33xx_mailbox_irqs,
1264 .main_clk = "l4ls_gclk",
1265 .prcm = {
1266 .omap4 = {
1267 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1268 .modulemode = MODULEMODE_SWCTRL,
1269 },
1270 },
1271};
1272
1273/*
1274 * 'mcasp' class
1275 */
1276static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1277 .rev_offs = 0x0,
1278 .sysc_offs = 0x4,
1279 .sysc_flags = SYSC_HAS_SIDLEMODE,
1280 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1281 .sysc_fields = &omap_hwmod_sysc_type3,
1282};
1283
1284static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1285 .name = "mcasp",
1286 .sysc = &am33xx_mcasp_sysc,
1287};
1288
1289/* mcasp0 */
1290static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1291 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1292 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1293 { .irq = -1 },
1294};
1295
1296static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1297 { .name = "tx", .dma_req = 8, },
1298 { .name = "rx", .dma_req = 9, },
1299 { .dma_req = -1 }
1300};
1301
1302static struct omap_hwmod am33xx_mcasp0_hwmod = {
1303 .name = "mcasp0",
1304 .class = &am33xx_mcasp_hwmod_class,
1305 .clkdm_name = "l3s_clkdm",
1306 .mpu_irqs = am33xx_mcasp0_irqs,
1307 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1308 .main_clk = "mcasp0_fck",
1309 .prcm = {
1310 .omap4 = {
1311 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1312 .modulemode = MODULEMODE_SWCTRL,
1313 },
1314 },
1315};
1316
1317/* mcasp1 */
1318static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1319 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1320 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1321 { .irq = -1 },
1322};
1323
1324static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1325 { .name = "tx", .dma_req = 10, },
1326 { .name = "rx", .dma_req = 11, },
1327 { .dma_req = -1 }
1328};
1329
1330static struct omap_hwmod am33xx_mcasp1_hwmod = {
1331 .name = "mcasp1",
1332 .class = &am33xx_mcasp_hwmod_class,
1333 .clkdm_name = "l3s_clkdm",
1334 .mpu_irqs = am33xx_mcasp1_irqs,
1335 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1336 .main_clk = "mcasp1_fck",
1337 .prcm = {
1338 .omap4 = {
1339 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1340 .modulemode = MODULEMODE_SWCTRL,
1341 },
1342 },
1343};
1344
1345/* 'mmc' class */
1346static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1347 .rev_offs = 0x1fc,
1348 .sysc_offs = 0x10,
1349 .syss_offs = 0x14,
1350 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1351 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1352 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1353 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1354 .sysc_fields = &omap_hwmod_sysc_type1,
1355};
1356
1357static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1358 .name = "mmc",
1359 .sysc = &am33xx_mmc_sysc,
1360};
1361
1362/* mmc0 */
1363static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1364 { .irq = 64 + OMAP_INTC_START, },
1365 { .irq = -1 },
1366};
1367
1368static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1369 { .name = "tx", .dma_req = 24, },
1370 { .name = "rx", .dma_req = 25, },
1371 { .dma_req = -1 }
1372};
1373
1374static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1375 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1376};
1377
1378static struct omap_hwmod am33xx_mmc0_hwmod = {
1379 .name = "mmc1",
1380 .class = &am33xx_mmc_hwmod_class,
1381 .clkdm_name = "l4ls_clkdm",
1382 .mpu_irqs = am33xx_mmc0_irqs,
1383 .sdma_reqs = am33xx_mmc0_edma_reqs,
1384 .main_clk = "mmc_clk",
1385 .prcm = {
1386 .omap4 = {
1387 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1388 .modulemode = MODULEMODE_SWCTRL,
1389 },
1390 },
1391 .dev_attr = &am33xx_mmc0_dev_attr,
1392};
1393
1394/* mmc1 */
1395static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1396 { .irq = 28 + OMAP_INTC_START, },
1397 { .irq = -1 },
1398};
1399
1400static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1401 { .name = "tx", .dma_req = 2, },
1402 { .name = "rx", .dma_req = 3, },
1403 { .dma_req = -1 }
1404};
1405
1406static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1407 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1408};
1409
1410static struct omap_hwmod am33xx_mmc1_hwmod = {
1411 .name = "mmc2",
1412 .class = &am33xx_mmc_hwmod_class,
1413 .clkdm_name = "l4ls_clkdm",
1414 .mpu_irqs = am33xx_mmc1_irqs,
1415 .sdma_reqs = am33xx_mmc1_edma_reqs,
1416 .main_clk = "mmc_clk",
1417 .prcm = {
1418 .omap4 = {
1419 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1420 .modulemode = MODULEMODE_SWCTRL,
1421 },
1422 },
1423 .dev_attr = &am33xx_mmc1_dev_attr,
1424};
1425
1426/* mmc2 */
1427static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1428 { .irq = 29 + OMAP_INTC_START, },
1429 { .irq = -1 },
1430};
1431
1432static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1433 { .name = "tx", .dma_req = 64, },
1434 { .name = "rx", .dma_req = 65, },
1435 { .dma_req = -1 }
1436};
1437
1438static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1439 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1440};
1441static struct omap_hwmod am33xx_mmc2_hwmod = {
1442 .name = "mmc3",
1443 .class = &am33xx_mmc_hwmod_class,
1444 .clkdm_name = "l3s_clkdm",
1445 .mpu_irqs = am33xx_mmc2_irqs,
1446 .sdma_reqs = am33xx_mmc2_edma_reqs,
1447 .main_clk = "mmc_clk",
1448 .prcm = {
1449 .omap4 = {
1450 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1451 .modulemode = MODULEMODE_SWCTRL,
1452 },
1453 },
1454 .dev_attr = &am33xx_mmc2_dev_attr,
1455};
1456
1457/*
1458 * 'rtc' class
1459 * rtc subsystem
1460 */
1461static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1462 .rev_offs = 0x0074,
1463 .sysc_offs = 0x0078,
1464 .sysc_flags = SYSC_HAS_SIDLEMODE,
1465 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1466 SIDLE_SMART | SIDLE_SMART_WKUP),
1467 .sysc_fields = &omap_hwmod_sysc_type3,
1468};
1469
1470static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1471 .name = "rtc",
1472 .sysc = &am33xx_rtc_sysc,
1473};
1474
1475static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1476 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1477 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1478 { .irq = -1 },
1479};
1480
1481static struct omap_hwmod am33xx_rtc_hwmod = {
1482 .name = "rtc",
1483 .class = &am33xx_rtc_hwmod_class,
1484 .clkdm_name = "l4_rtc_clkdm",
1485 .mpu_irqs = am33xx_rtc_irqs,
1486 .main_clk = "clk_32768_ck",
1487 .prcm = {
1488 .omap4 = {
1489 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1490 .modulemode = MODULEMODE_SWCTRL,
1491 },
1492 },
1493};
1494
1495/* 'spi' class */
1496static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1497 .rev_offs = 0x0000,
1498 .sysc_offs = 0x0110,
1499 .syss_offs = 0x0114,
1500 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1501 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1502 SYSS_HAS_RESET_STATUS),
1503 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1504 .sysc_fields = &omap_hwmod_sysc_type1,
1505};
1506
1507static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1508 .name = "mcspi",
1509 .sysc = &am33xx_mcspi_sysc,
1510 .rev = OMAP4_MCSPI_REV,
1511};
1512
1513/* spi0 */
1514static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1515 { .irq = 65 + OMAP_INTC_START, },
1516 { .irq = -1 },
1517};
1518
1519static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1520 { .name = "rx0", .dma_req = 17 },
1521 { .name = "tx0", .dma_req = 16 },
1522 { .name = "rx1", .dma_req = 19 },
1523 { .name = "tx1", .dma_req = 18 },
1524 { .dma_req = -1 }
1525};
1526
1527static struct omap2_mcspi_dev_attr mcspi_attrib = {
1528 .num_chipselect = 2,
1529};
1530static struct omap_hwmod am33xx_spi0_hwmod = {
1531 .name = "spi0",
1532 .class = &am33xx_spi_hwmod_class,
1533 .clkdm_name = "l4ls_clkdm",
1534 .mpu_irqs = am33xx_spi0_irqs,
1535 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1536 .main_clk = "dpll_per_m2_div4_ck",
1537 .prcm = {
1538 .omap4 = {
1539 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1540 .modulemode = MODULEMODE_SWCTRL,
1541 },
1542 },
1543 .dev_attr = &mcspi_attrib,
1544};
1545
1546/* spi1 */
1547static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1548 { .irq = 125 + OMAP_INTC_START, },
1549 { .irq = -1 },
1550};
1551
1552static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1553 { .name = "rx0", .dma_req = 43 },
1554 { .name = "tx0", .dma_req = 42 },
1555 { .name = "rx1", .dma_req = 45 },
1556 { .name = "tx1", .dma_req = 44 },
1557 { .dma_req = -1 }
1558};
1559
1560static struct omap_hwmod am33xx_spi1_hwmod = {
1561 .name = "spi1",
1562 .class = &am33xx_spi_hwmod_class,
1563 .clkdm_name = "l4ls_clkdm",
1564 .mpu_irqs = am33xx_spi1_irqs,
1565 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1566 .main_clk = "dpll_per_m2_div4_ck",
1567 .prcm = {
1568 .omap4 = {
1569 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1570 .modulemode = MODULEMODE_SWCTRL,
1571 },
1572 },
1573 .dev_attr = &mcspi_attrib,
1574};
1575
1576/*
1577 * 'spinlock' class
1578 * spinlock provides hardware assistance for synchronizing the
1579 * processes running on multiple processors
1580 */
1581static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1582 .name = "spinlock",
1583};
1584
1585static struct omap_hwmod am33xx_spinlock_hwmod = {
1586 .name = "spinlock",
1587 .class = &am33xx_spinlock_hwmod_class,
1588 .clkdm_name = "l4ls_clkdm",
1589 .main_clk = "l4ls_gclk",
1590 .prcm = {
1591 .omap4 = {
1592 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1593 .modulemode = MODULEMODE_SWCTRL,
1594 },
1595 },
1596};
1597
1598/* 'timer 2-7' class */
1599static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1600 .rev_offs = 0x0000,
1601 .sysc_offs = 0x0010,
1602 .syss_offs = 0x0014,
1603 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1604 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1605 SIDLE_SMART_WKUP),
1606 .sysc_fields = &omap_hwmod_sysc_type2,
1607};
1608
1609static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1610 .name = "timer",
1611 .sysc = &am33xx_timer_sysc,
1612};
1613
1614/* timer1 1ms */
1615static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1616 .rev_offs = 0x0000,
1617 .sysc_offs = 0x0010,
1618 .syss_offs = 0x0014,
1619 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1620 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1621 SYSS_HAS_RESET_STATUS),
1622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1623 .sysc_fields = &omap_hwmod_sysc_type1,
1624};
1625
1626static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1627 .name = "timer",
1628 .sysc = &am33xx_timer1ms_sysc,
1629};
1630
1631static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1632 { .irq = 67 + OMAP_INTC_START, },
1633 { .irq = -1 },
1634};
1635
1636static struct omap_hwmod am33xx_timer1_hwmod = {
1637 .name = "timer1",
1638 .class = &am33xx_timer1ms_hwmod_class,
1639 .clkdm_name = "l4_wkup_clkdm",
1640 .mpu_irqs = am33xx_timer1_irqs,
1641 .main_clk = "timer1_fck",
1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1645 .modulemode = MODULEMODE_SWCTRL,
1646 },
1647 },
1648};
1649
1650static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1651 { .irq = 68 + OMAP_INTC_START, },
1652 { .irq = -1 },
1653};
1654
1655static struct omap_hwmod am33xx_timer2_hwmod = {
1656 .name = "timer2",
1657 .class = &am33xx_timer_hwmod_class,
1658 .clkdm_name = "l4ls_clkdm",
1659 .mpu_irqs = am33xx_timer2_irqs,
1660 .main_clk = "timer2_fck",
1661 .prcm = {
1662 .omap4 = {
1663 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1664 .modulemode = MODULEMODE_SWCTRL,
1665 },
1666 },
1667};
1668
1669static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1670 { .irq = 69 + OMAP_INTC_START, },
1671 { .irq = -1 },
1672};
1673
1674static struct omap_hwmod am33xx_timer3_hwmod = {
1675 .name = "timer3",
1676 .class = &am33xx_timer_hwmod_class,
1677 .clkdm_name = "l4ls_clkdm",
1678 .mpu_irqs = am33xx_timer3_irqs,
1679 .main_clk = "timer3_fck",
1680 .prcm = {
1681 .omap4 = {
1682 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1683 .modulemode = MODULEMODE_SWCTRL,
1684 },
1685 },
1686};
1687
1688static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1689 { .irq = 92 + OMAP_INTC_START, },
1690 { .irq = -1 },
1691};
1692
1693static struct omap_hwmod am33xx_timer4_hwmod = {
1694 .name = "timer4",
1695 .class = &am33xx_timer_hwmod_class,
1696 .clkdm_name = "l4ls_clkdm",
1697 .mpu_irqs = am33xx_timer4_irqs,
1698 .main_clk = "timer4_fck",
1699 .prcm = {
1700 .omap4 = {
1701 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1702 .modulemode = MODULEMODE_SWCTRL,
1703 },
1704 },
1705};
1706
1707static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1708 { .irq = 93 + OMAP_INTC_START, },
1709 { .irq = -1 },
1710};
1711
1712static struct omap_hwmod am33xx_timer5_hwmod = {
1713 .name = "timer5",
1714 .class = &am33xx_timer_hwmod_class,
1715 .clkdm_name = "l4ls_clkdm",
1716 .mpu_irqs = am33xx_timer5_irqs,
1717 .main_clk = "timer5_fck",
1718 .prcm = {
1719 .omap4 = {
1720 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1721 .modulemode = MODULEMODE_SWCTRL,
1722 },
1723 },
1724};
1725
1726static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1727 { .irq = 94 + OMAP_INTC_START, },
1728 { .irq = -1 },
1729};
1730
1731static struct omap_hwmod am33xx_timer6_hwmod = {
1732 .name = "timer6",
1733 .class = &am33xx_timer_hwmod_class,
1734 .clkdm_name = "l4ls_clkdm",
1735 .mpu_irqs = am33xx_timer6_irqs,
1736 .main_clk = "timer6_fck",
1737 .prcm = {
1738 .omap4 = {
1739 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1740 .modulemode = MODULEMODE_SWCTRL,
1741 },
1742 },
1743};
1744
1745static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1746 { .irq = 95 + OMAP_INTC_START, },
1747 { .irq = -1 },
1748};
1749
1750static struct omap_hwmod am33xx_timer7_hwmod = {
1751 .name = "timer7",
1752 .class = &am33xx_timer_hwmod_class,
1753 .clkdm_name = "l4ls_clkdm",
1754 .mpu_irqs = am33xx_timer7_irqs,
1755 .main_clk = "timer7_fck",
1756 .prcm = {
1757 .omap4 = {
1758 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1759 .modulemode = MODULEMODE_SWCTRL,
1760 },
1761 },
1762};
1763
1764/* tpcc */
1765static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1766 .name = "tpcc",
1767};
1768
1769static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1770 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1771 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1772 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1773 { .irq = -1 },
1774};
1775
1776static struct omap_hwmod am33xx_tpcc_hwmod = {
1777 .name = "tpcc",
1778 .class = &am33xx_tpcc_hwmod_class,
1779 .clkdm_name = "l3_clkdm",
1780 .mpu_irqs = am33xx_tpcc_irqs,
1781 .main_clk = "l3_gclk",
1782 .prcm = {
1783 .omap4 = {
1784 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1785 .modulemode = MODULEMODE_SWCTRL,
1786 },
1787 },
1788};
1789
1790static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1791 .rev_offs = 0x0,
1792 .sysc_offs = 0x10,
1793 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1794 SYSC_HAS_MIDLEMODE),
1795 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1796 .sysc_fields = &omap_hwmod_sysc_type2,
1797};
1798
1799/* 'tptc' class */
1800static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1801 .name = "tptc",
1802 .sysc = &am33xx_tptc_sysc,
1803};
1804
1805/* tptc0 */
1806static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1807 { .irq = 112 + OMAP_INTC_START, },
1808 { .irq = -1 },
1809};
1810
1811static struct omap_hwmod am33xx_tptc0_hwmod = {
1812 .name = "tptc0",
1813 .class = &am33xx_tptc_hwmod_class,
1814 .clkdm_name = "l3_clkdm",
1815 .mpu_irqs = am33xx_tptc0_irqs,
1816 .main_clk = "l3_gclk",
1817 .prcm = {
1818 .omap4 = {
1819 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1820 .modulemode = MODULEMODE_SWCTRL,
1821 },
1822 },
1823};
1824
1825/* tptc1 */
1826static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1827 { .irq = 113 + OMAP_INTC_START, },
1828 { .irq = -1 },
1829};
1830
1831static struct omap_hwmod am33xx_tptc1_hwmod = {
1832 .name = "tptc1",
1833 .class = &am33xx_tptc_hwmod_class,
1834 .clkdm_name = "l3_clkdm",
1835 .mpu_irqs = am33xx_tptc1_irqs,
1836 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1837 .main_clk = "l3_gclk",
1838 .prcm = {
1839 .omap4 = {
1840 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1841 .modulemode = MODULEMODE_SWCTRL,
1842 },
1843 },
1844};
1845
1846/* tptc2 */
1847static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1848 { .irq = 114 + OMAP_INTC_START, },
1849 { .irq = -1 },
1850};
1851
1852static struct omap_hwmod am33xx_tptc2_hwmod = {
1853 .name = "tptc2",
1854 .class = &am33xx_tptc_hwmod_class,
1855 .clkdm_name = "l3_clkdm",
1856 .mpu_irqs = am33xx_tptc2_irqs,
1857 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1858 .main_clk = "l3_gclk",
1859 .prcm = {
1860 .omap4 = {
1861 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1862 .modulemode = MODULEMODE_SWCTRL,
1863 },
1864 },
1865};
1866
1867/* 'uart' class */
1868static struct omap_hwmod_class_sysconfig uart_sysc = {
1869 .rev_offs = 0x50,
1870 .sysc_offs = 0x54,
1871 .syss_offs = 0x58,
1872 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1873 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1874 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1875 SIDLE_SMART_WKUP),
1876 .sysc_fields = &omap_hwmod_sysc_type1,
1877};
1878
1879static struct omap_hwmod_class uart_class = {
1880 .name = "uart",
1881 .sysc = &uart_sysc,
1882};
1883
1884/* uart1 */
1885static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1886 { .name = "tx", .dma_req = 26, },
1887 { .name = "rx", .dma_req = 27, },
1888 { .dma_req = -1 }
1889};
1890
1891static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1892 { .irq = 72 + OMAP_INTC_START, },
1893 { .irq = -1 },
1894};
1895
1896static struct omap_hwmod am33xx_uart1_hwmod = {
1897 .name = "uart1",
1898 .class = &uart_class,
1899 .clkdm_name = "l4_wkup_clkdm",
1900 .mpu_irqs = am33xx_uart1_irqs,
1901 .sdma_reqs = uart1_edma_reqs,
1902 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1903 .prcm = {
1904 .omap4 = {
1905 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1906 .modulemode = MODULEMODE_SWCTRL,
1907 },
1908 },
1909};
1910
1911static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1912 { .irq = 73 + OMAP_INTC_START, },
1913 { .irq = -1 },
1914};
1915
1916static struct omap_hwmod am33xx_uart2_hwmod = {
1917 .name = "uart2",
1918 .class = &uart_class,
1919 .clkdm_name = "l4ls_clkdm",
1920 .mpu_irqs = am33xx_uart2_irqs,
1921 .sdma_reqs = uart1_edma_reqs,
1922 .main_clk = "dpll_per_m2_div4_ck",
1923 .prcm = {
1924 .omap4 = {
1925 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1926 .modulemode = MODULEMODE_SWCTRL,
1927 },
1928 },
1929};
1930
1931/* uart3 */
1932static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
1933 { .name = "tx", .dma_req = 30, },
1934 { .name = "rx", .dma_req = 31, },
1935 { .dma_req = -1 }
1936};
1937
1938static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
1939 { .irq = 74 + OMAP_INTC_START, },
1940 { .irq = -1 },
1941};
1942
1943static struct omap_hwmod am33xx_uart3_hwmod = {
1944 .name = "uart3",
1945 .class = &uart_class,
1946 .clkdm_name = "l4ls_clkdm",
1947 .mpu_irqs = am33xx_uart3_irqs,
1948 .sdma_reqs = uart3_edma_reqs,
1949 .main_clk = "dpll_per_m2_div4_ck",
1950 .prcm = {
1951 .omap4 = {
1952 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1953 .modulemode = MODULEMODE_SWCTRL,
1954 },
1955 },
1956};
1957
1958static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
1959 { .irq = 44 + OMAP_INTC_START, },
1960 { .irq = -1 },
1961};
1962
1963static struct omap_hwmod am33xx_uart4_hwmod = {
1964 .name = "uart4",
1965 .class = &uart_class,
1966 .clkdm_name = "l4ls_clkdm",
1967 .mpu_irqs = am33xx_uart4_irqs,
1968 .sdma_reqs = uart1_edma_reqs,
1969 .main_clk = "dpll_per_m2_div4_ck",
1970 .prcm = {
1971 .omap4 = {
1972 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1973 .modulemode = MODULEMODE_SWCTRL,
1974 },
1975 },
1976};
1977
1978static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
1979 { .irq = 45 + OMAP_INTC_START, },
1980 { .irq = -1 },
1981};
1982
1983static struct omap_hwmod am33xx_uart5_hwmod = {
1984 .name = "uart5",
1985 .class = &uart_class,
1986 .clkdm_name = "l4ls_clkdm",
1987 .mpu_irqs = am33xx_uart5_irqs,
1988 .sdma_reqs = uart1_edma_reqs,
1989 .main_clk = "dpll_per_m2_div4_ck",
1990 .prcm = {
1991 .omap4 = {
1992 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
1993 .modulemode = MODULEMODE_SWCTRL,
1994 },
1995 },
1996};
1997
1998static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
1999 { .irq = 46 + OMAP_INTC_START, },
2000 { .irq = -1 },
2001};
2002
2003static struct omap_hwmod am33xx_uart6_hwmod = {
2004 .name = "uart6",
2005 .class = &uart_class,
2006 .clkdm_name = "l4ls_clkdm",
2007 .mpu_irqs = am33xx_uart6_irqs,
2008 .sdma_reqs = uart1_edma_reqs,
2009 .main_clk = "dpll_per_m2_div4_ck",
2010 .prcm = {
2011 .omap4 = {
2012 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2013 .modulemode = MODULEMODE_SWCTRL,
2014 },
2015 },
2016};
2017
2018/* 'wd_timer' class */
2019static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2020 .name = "wd_timer",
2021};
2022
2023/*
2024 * XXX: device.c file uses hardcoded name for watchdog timer
2025 * driver "wd_timer2, so we are also using same name as of now...
2026 */
2027static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2028 .name = "wd_timer2",
2029 .class = &am33xx_wd_timer_hwmod_class,
2030 .clkdm_name = "l4_wkup_clkdm",
2031 .main_clk = "wdt1_fck",
2032 .prcm = {
2033 .omap4 = {
2034 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2035 .modulemode = MODULEMODE_SWCTRL,
2036 },
2037 },
2038};
2039
2040/*
2041 * 'usb_otg' class
2042 * high-speed on-the-go universal serial bus (usb_otg) controller
2043 */
2044static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2045 .rev_offs = 0x0,
2046 .sysc_offs = 0x10,
2047 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2048 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2049 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2050 .sysc_fields = &omap_hwmod_sysc_type2,
2051};
2052
2053static struct omap_hwmod_class am33xx_usbotg_class = {
2054 .name = "usbotg",
2055 .sysc = &am33xx_usbhsotg_sysc,
2056};
2057
2058static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2059 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2060 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2061 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2062 { .irq = -1 + OMAP_INTC_START, },
2063};
2064
2065static struct omap_hwmod am33xx_usbss_hwmod = {
2066 .name = "usb_otg_hs",
2067 .class = &am33xx_usbotg_class,
2068 .clkdm_name = "l3s_clkdm",
2069 .mpu_irqs = am33xx_usbss_mpu_irqs,
2070 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2071 .main_clk = "usbotg_fck",
2072 .prcm = {
2073 .omap4 = {
2074 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2075 .modulemode = MODULEMODE_SWCTRL,
2076 },
2077 },
2078};
2079
2080
2081/*
2082 * Interfaces
2083 */
2084
2085/* l4 fw -> emif fw */
2086static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2087 .master = &am33xx_l4_fw_hwmod,
2088 .slave = &am33xx_emif_fw_hwmod,
2089 .clk = "l4fw_gclk",
2090 .user = OCP_USER_MPU,
2091};
2092
2093static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2094 {
2095 .pa_start = 0x4c000000,
2096 .pa_end = 0x4c000fff,
2097 .flags = ADDR_TYPE_RT
2098 },
2099 { }
2100};
2101/* l3 main -> emif */
2102static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2103 .master = &am33xx_l3_main_hwmod,
2104 .slave = &am33xx_emif_hwmod,
2105 .clk = "dpll_core_m4_ck",
2106 .addr = am33xx_emif_addrs,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* mpu -> l3 main */
2111static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2112 .master = &am33xx_mpu_hwmod,
2113 .slave = &am33xx_l3_main_hwmod,
2114 .clk = "dpll_mpu_m2_ck",
2115 .user = OCP_USER_MPU,
2116};
2117
2118/* l3 main -> l4 hs */
2119static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2120 .master = &am33xx_l3_main_hwmod,
2121 .slave = &am33xx_l4_hs_hwmod,
2122 .clk = "l3s_gclk",
2123 .user = OCP_USER_MPU | OCP_USER_SDMA,
2124};
2125
2126/* l3 main -> l3 s */
2127static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2128 .master = &am33xx_l3_main_hwmod,
2129 .slave = &am33xx_l3_s_hwmod,
2130 .clk = "l3s_gclk",
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132};
2133
2134/* l3 s -> l4 per/ls */
2135static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2136 .master = &am33xx_l3_s_hwmod,
2137 .slave = &am33xx_l4_ls_hwmod,
2138 .clk = "l3s_gclk",
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2140};
2141
2142/* l3 s -> l4 wkup */
2143static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2144 .master = &am33xx_l3_s_hwmod,
2145 .slave = &am33xx_l4_wkup_hwmod,
2146 .clk = "l3s_gclk",
2147 .user = OCP_USER_MPU | OCP_USER_SDMA,
2148};
2149
2150/* l3 s -> l4 fw */
2151static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2152 .master = &am33xx_l3_s_hwmod,
2153 .slave = &am33xx_l4_fw_hwmod,
2154 .clk = "l3s_gclk",
2155 .user = OCP_USER_MPU | OCP_USER_SDMA,
2156};
2157
2158/* l3 main -> l3 instr */
2159static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2160 .master = &am33xx_l3_main_hwmod,
2161 .slave = &am33xx_l3_instr_hwmod,
2162 .clk = "l3s_gclk",
2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164};
2165
2166/* mpu -> prcm */
2167static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2168 .master = &am33xx_mpu_hwmod,
2169 .slave = &am33xx_prcm_hwmod,
2170 .clk = "dpll_mpu_m2_ck",
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172};
2173
2174/* l3 s -> l3 main*/
2175static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2176 .master = &am33xx_l3_s_hwmod,
2177 .slave = &am33xx_l3_main_hwmod,
2178 .clk = "l3s_gclk",
2179 .user = OCP_USER_MPU | OCP_USER_SDMA,
2180};
2181
2182/* pru-icss -> l3 main */
2183static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2184 .master = &am33xx_pruss_hwmod,
2185 .slave = &am33xx_l3_main_hwmod,
2186 .clk = "l3_gclk",
2187 .user = OCP_USER_MPU | OCP_USER_SDMA,
2188};
2189
2190/* wkup m3 -> l4 wkup */
2191static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2192 .master = &am33xx_wkup_m3_hwmod,
2193 .slave = &am33xx_l4_wkup_hwmod,
2194 .clk = "dpll_core_m4_div2_ck",
2195 .user = OCP_USER_MPU | OCP_USER_SDMA,
2196};
2197
2198/* gfx -> l3 main */
2199static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2200 .master = &am33xx_gfx_hwmod,
2201 .slave = &am33xx_l3_main_hwmod,
2202 .clk = "dpll_core_m4_ck",
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204};
2205
2206/* l4 wkup -> wkup m3 */
2207static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2208 {
2209 .name = "umem",
2210 .pa_start = 0x44d00000,
2211 .pa_end = 0x44d00000 + SZ_16K - 1,
2212 .flags = ADDR_TYPE_RT
2213 },
2214 {
2215 .name = "dmem",
2216 .pa_start = 0x44d80000,
2217 .pa_end = 0x44d80000 + SZ_8K - 1,
2218 .flags = ADDR_TYPE_RT
2219 },
2220 { }
2221};
2222
2223static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2224 .master = &am33xx_l4_wkup_hwmod,
2225 .slave = &am33xx_wkup_m3_hwmod,
2226 .clk = "dpll_core_m4_div2_ck",
2227 .addr = am33xx_wkup_m3_addrs,
2228 .user = OCP_USER_MPU | OCP_USER_SDMA,
2229};
2230
2231/* l4 hs -> pru-icss */
2232static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2233 {
2234 .pa_start = 0x4a300000,
2235 .pa_end = 0x4a300000 + SZ_512K - 1,
2236 .flags = ADDR_TYPE_RT
2237 },
2238 { }
2239};
2240
2241static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2242 .master = &am33xx_l4_hs_hwmod,
2243 .slave = &am33xx_pruss_hwmod,
2244 .clk = "dpll_core_m4_ck",
2245 .addr = am33xx_pruss_addrs,
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2247};
2248
2249/* l3 main -> gfx */
2250static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2251 {
2252 .pa_start = 0x56000000,
2253 .pa_end = 0x56000000 + SZ_16M - 1,
2254 .flags = ADDR_TYPE_RT
2255 },
2256 { }
2257};
2258
2259static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2260 .master = &am33xx_l3_main_hwmod,
2261 .slave = &am33xx_gfx_hwmod,
2262 .clk = "dpll_core_m4_ck",
2263 .addr = am33xx_gfx_addrs,
2264 .user = OCP_USER_MPU | OCP_USER_SDMA,
2265};
2266
2267/* l4 wkup -> smartreflex0 */
2268static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2269 {
2270 .pa_start = 0x44e37000,
2271 .pa_end = 0x44e37000 + SZ_4K - 1,
2272 .flags = ADDR_TYPE_RT
2273 },
2274 { }
2275};
2276
2277static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2278 .master = &am33xx_l4_wkup_hwmod,
2279 .slave = &am33xx_smartreflex0_hwmod,
2280 .clk = "dpll_core_m4_div2_ck",
2281 .addr = am33xx_smartreflex0_addrs,
2282 .user = OCP_USER_MPU,
2283};
2284
2285/* l4 wkup -> smartreflex1 */
2286static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2287 {
2288 .pa_start = 0x44e39000,
2289 .pa_end = 0x44e39000 + SZ_4K - 1,
2290 .flags = ADDR_TYPE_RT
2291 },
2292 { }
2293};
2294
2295static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2296 .master = &am33xx_l4_wkup_hwmod,
2297 .slave = &am33xx_smartreflex1_hwmod,
2298 .clk = "dpll_core_m4_div2_ck",
2299 .addr = am33xx_smartreflex1_addrs,
2300 .user = OCP_USER_MPU,
2301};
2302
2303/* l4 wkup -> control */
2304static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2305 {
2306 .pa_start = 0x44e10000,
2307 .pa_end = 0x44e10000 + SZ_8K - 1,
2308 .flags = ADDR_TYPE_RT
2309 },
2310 { }
2311};
2312
2313static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2314 .master = &am33xx_l4_wkup_hwmod,
2315 .slave = &am33xx_control_hwmod,
2316 .clk = "dpll_core_m4_div2_ck",
2317 .addr = am33xx_control_addrs,
2318 .user = OCP_USER_MPU,
2319};
2320
2321/* l4 wkup -> rtc */
2322static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2323 {
2324 .pa_start = 0x44e3e000,
2325 .pa_end = 0x44e3e000 + SZ_4K - 1,
2326 .flags = ADDR_TYPE_RT
2327 },
2328 { }
2329};
2330
2331static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2332 .master = &am33xx_l4_wkup_hwmod,
2333 .slave = &am33xx_rtc_hwmod,
2334 .clk = "clkdiv32k_ick",
2335 .addr = am33xx_rtc_addrs,
2336 .user = OCP_USER_MPU,
2337};
2338
2339/* l4 per/ls -> DCAN0 */
2340static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2341 {
2342 .pa_start = 0x481CC000,
2343 .pa_end = 0x481CC000 + SZ_4K - 1,
2344 .flags = ADDR_TYPE_RT
2345 },
2346 { }
2347};
2348
2349static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2350 .master = &am33xx_l4_ls_hwmod,
2351 .slave = &am33xx_dcan0_hwmod,
2352 .clk = "l4ls_gclk",
2353 .addr = am33xx_dcan0_addrs,
2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355};
2356
2357/* l4 per/ls -> DCAN1 */
2358static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2359 {
2360 .pa_start = 0x481D0000,
2361 .pa_end = 0x481D0000 + SZ_4K - 1,
2362 .flags = ADDR_TYPE_RT
2363 },
2364 { }
2365};
2366
2367static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2368 .master = &am33xx_l4_ls_hwmod,
2369 .slave = &am33xx_dcan1_hwmod,
2370 .clk = "l4ls_gclk",
2371 .addr = am33xx_dcan1_addrs,
2372 .user = OCP_USER_MPU | OCP_USER_SDMA,
2373};
2374
2375/* l4 per/ls -> GPIO2 */
2376static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2377 {
2378 .pa_start = 0x4804C000,
2379 .pa_end = 0x4804C000 + SZ_4K - 1,
2380 .flags = ADDR_TYPE_RT,
2381 },
2382 { }
2383};
2384
2385static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2386 .master = &am33xx_l4_ls_hwmod,
2387 .slave = &am33xx_gpio1_hwmod,
2388 .clk = "l4ls_gclk",
2389 .addr = am33xx_gpio1_addrs,
2390 .user = OCP_USER_MPU | OCP_USER_SDMA,
2391};
2392
2393/* l4 per/ls -> gpio3 */
2394static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2395 {
2396 .pa_start = 0x481AC000,
2397 .pa_end = 0x481AC000 + SZ_4K - 1,
2398 .flags = ADDR_TYPE_RT,
2399 },
2400 { }
2401};
2402
2403static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2404 .master = &am33xx_l4_ls_hwmod,
2405 .slave = &am33xx_gpio2_hwmod,
2406 .clk = "l4ls_gclk",
2407 .addr = am33xx_gpio2_addrs,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409};
2410
2411/* l4 per/ls -> gpio4 */
2412static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2413 {
2414 .pa_start = 0x481AE000,
2415 .pa_end = 0x481AE000 + SZ_4K - 1,
2416 .flags = ADDR_TYPE_RT,
2417 },
2418 { }
2419};
2420
2421static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2422 .master = &am33xx_l4_ls_hwmod,
2423 .slave = &am33xx_gpio3_hwmod,
2424 .clk = "l4ls_gclk",
2425 .addr = am33xx_gpio3_addrs,
2426 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427};
2428
2429/* L4 WKUP -> I2C1 */
2430static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2431 {
2432 .pa_start = 0x44E0B000,
2433 .pa_end = 0x44E0B000 + SZ_4K - 1,
2434 .flags = ADDR_TYPE_RT,
2435 },
2436 { }
2437};
2438
2439static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2440 .master = &am33xx_l4_wkup_hwmod,
2441 .slave = &am33xx_i2c1_hwmod,
2442 .clk = "dpll_core_m4_div2_ck",
2443 .addr = am33xx_i2c1_addr_space,
2444 .user = OCP_USER_MPU,
2445};
2446
2447/* L4 WKUP -> GPIO1 */
2448static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2449 {
2450 .pa_start = 0x44E07000,
2451 .pa_end = 0x44E07000 + SZ_4K - 1,
2452 .flags = ADDR_TYPE_RT,
2453 },
2454 { }
2455};
2456
2457static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2458 .master = &am33xx_l4_wkup_hwmod,
2459 .slave = &am33xx_gpio0_hwmod,
2460 .clk = "dpll_core_m4_div2_ck",
2461 .addr = am33xx_gpio0_addrs,
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2463};
2464
2465/* L4 WKUP -> ADC_TSC */
2466static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2467 {
2468 .pa_start = 0x44E0D000,
2469 .pa_end = 0x44E0D000 + SZ_8K - 1,
2470 .flags = ADDR_TYPE_RT
2471 },
2472 { }
2473};
2474
2475static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2476 .master = &am33xx_l4_wkup_hwmod,
2477 .slave = &am33xx_adc_tsc_hwmod,
2478 .clk = "dpll_core_m4_div2_ck",
2479 .addr = am33xx_adc_tsc_addrs,
2480 .user = OCP_USER_MPU,
2481};
2482
2483static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2484 /* cpsw ss */
2485 {
2486 .pa_start = 0x4a100000,
2487 .pa_end = 0x4a100000 + SZ_2K - 1,
2488 .flags = ADDR_TYPE_RT,
2489 },
2490 /* cpsw wr */
2491 {
2492 .pa_start = 0x4a101200,
2493 .pa_end = 0x4a101200 + SZ_256 - 1,
2494 .flags = ADDR_TYPE_RT,
2495 },
2496 { }
2497};
2498
2499static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2500 .master = &am33xx_l4_hs_hwmod,
2501 .slave = &am33xx_cpgmac0_hwmod,
2502 .clk = "cpsw_125mhz_gclk",
2503 .addr = am33xx_cpgmac0_addr_space,
2504 .user = OCP_USER_MPU,
2505};
2506
2507static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2508 {
2509 .pa_start = 0x48080000,
2510 .pa_end = 0x48080000 + SZ_8K - 1,
2511 .flags = ADDR_TYPE_RT
2512 },
2513 { }
2514};
2515
2516static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2517 .master = &am33xx_l4_ls_hwmod,
2518 .slave = &am33xx_elm_hwmod,
2519 .clk = "l4ls_gclk",
2520 .addr = am33xx_elm_addr_space,
2521 .user = OCP_USER_MPU,
2522};
2523
2524/*
2525 * Splitting the resources to handle access of PWMSS config space
2526 * and module specific part independently
2527 */
2528static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2529 {
2530 .pa_start = 0x48300000,
2531 .pa_end = 0x48300000 + SZ_16 - 1,
2532 .flags = ADDR_TYPE_RT
2533 },
2534 {
2535 .pa_start = 0x48300200,
2536 .pa_end = 0x48300200 + SZ_256 - 1,
2537 .flags = ADDR_TYPE_RT
2538 },
2539 { }
2540};
2541
2542static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
2543 .master = &am33xx_l4_ls_hwmod,
2544 .slave = &am33xx_ehrpwm0_hwmod,
2545 .clk = "l4ls_gclk",
2546 .addr = am33xx_ehrpwm0_addr_space,
2547 .user = OCP_USER_MPU,
2548};
2549
2550/*
2551 * Splitting the resources to handle access of PWMSS config space
2552 * and module specific part independently
2553 */
2554static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2555 {
2556 .pa_start = 0x48302000,
2557 .pa_end = 0x48302000 + SZ_16 - 1,
2558 .flags = ADDR_TYPE_RT
2559 },
2560 {
2561 .pa_start = 0x48302200,
2562 .pa_end = 0x48302200 + SZ_256 - 1,
2563 .flags = ADDR_TYPE_RT
2564 },
2565 { }
2566};
2567
2568static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
2569 .master = &am33xx_l4_ls_hwmod,
2570 .slave = &am33xx_ehrpwm1_hwmod,
2571 .clk = "l4ls_gclk",
2572 .addr = am33xx_ehrpwm1_addr_space,
2573 .user = OCP_USER_MPU,
2574};
2575
2576/*
2577 * Splitting the resources to handle access of PWMSS config space
2578 * and module specific part independently
2579 */
2580static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2581 {
2582 .pa_start = 0x48304000,
2583 .pa_end = 0x48304000 + SZ_16 - 1,
2584 .flags = ADDR_TYPE_RT
2585 },
2586 {
2587 .pa_start = 0x48304200,
2588 .pa_end = 0x48304200 + SZ_256 - 1,
2589 .flags = ADDR_TYPE_RT
2590 },
2591 { }
2592};
2593
2594static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
2595 .master = &am33xx_l4_ls_hwmod,
2596 .slave = &am33xx_ehrpwm2_hwmod,
2597 .clk = "l4ls_gclk",
2598 .addr = am33xx_ehrpwm2_addr_space,
2599 .user = OCP_USER_MPU,
2600};
2601
2602/*
2603 * Splitting the resources to handle access of PWMSS config space
2604 * and module specific part independently
2605 */
2606static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2607 {
2608 .pa_start = 0x48300000,
2609 .pa_end = 0x48300000 + SZ_16 - 1,
2610 .flags = ADDR_TYPE_RT
2611 },
2612 {
2613 .pa_start = 0x48300100,
2614 .pa_end = 0x48300100 + SZ_256 - 1,
2615 .flags = ADDR_TYPE_RT
2616 },
2617 { }
2618};
2619
2620static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
2621 .master = &am33xx_l4_ls_hwmod,
2622 .slave = &am33xx_ecap0_hwmod,
2623 .clk = "l4ls_gclk",
2624 .addr = am33xx_ecap0_addr_space,
2625 .user = OCP_USER_MPU,
2626};
2627
2628/*
2629 * Splitting the resources to handle access of PWMSS config space
2630 * and module specific part independently
2631 */
2632static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2633 {
2634 .pa_start = 0x48302000,
2635 .pa_end = 0x48302000 + SZ_16 - 1,
2636 .flags = ADDR_TYPE_RT
2637 },
2638 {
2639 .pa_start = 0x48302100,
2640 .pa_end = 0x48302100 + SZ_256 - 1,
2641 .flags = ADDR_TYPE_RT
2642 },
2643 { }
2644};
2645
2646static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
2647 .master = &am33xx_l4_ls_hwmod,
2648 .slave = &am33xx_ecap1_hwmod,
2649 .clk = "l4ls_gclk",
2650 .addr = am33xx_ecap1_addr_space,
2651 .user = OCP_USER_MPU,
2652};
2653
2654/*
2655 * Splitting the resources to handle access of PWMSS config space
2656 * and module specific part independently
2657 */
2658static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2659 {
2660 .pa_start = 0x48304000,
2661 .pa_end = 0x48304000 + SZ_16 - 1,
2662 .flags = ADDR_TYPE_RT
2663 },
2664 {
2665 .pa_start = 0x48304100,
2666 .pa_end = 0x48304100 + SZ_256 - 1,
2667 .flags = ADDR_TYPE_RT
2668 },
2669 { }
2670};
2671
2672static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
2673 .master = &am33xx_l4_ls_hwmod,
2674 .slave = &am33xx_ecap2_hwmod,
2675 .clk = "l4ls_gclk",
2676 .addr = am33xx_ecap2_addr_space,
2677 .user = OCP_USER_MPU,
2678};
2679
2680/* l3s cfg -> gpmc */
2681static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2682 {
2683 .pa_start = 0x50000000,
2684 .pa_end = 0x50000000 + SZ_8K - 1,
2685 .flags = ADDR_TYPE_RT,
2686 },
2687 { }
2688};
2689
2690static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2691 .master = &am33xx_l3_s_hwmod,
2692 .slave = &am33xx_gpmc_hwmod,
2693 .clk = "l3s_gclk",
2694 .addr = am33xx_gpmc_addr_space,
2695 .user = OCP_USER_MPU,
2696};
2697
2698/* i2c2 */
2699static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2700 {
2701 .pa_start = 0x4802A000,
2702 .pa_end = 0x4802A000 + SZ_4K - 1,
2703 .flags = ADDR_TYPE_RT,
2704 },
2705 { }
2706};
2707
2708static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2709 .master = &am33xx_l4_ls_hwmod,
2710 .slave = &am33xx_i2c2_hwmod,
2711 .clk = "l4ls_gclk",
2712 .addr = am33xx_i2c2_addr_space,
2713 .user = OCP_USER_MPU,
2714};
2715
2716static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2717 {
2718 .pa_start = 0x4819C000,
2719 .pa_end = 0x4819C000 + SZ_4K - 1,
2720 .flags = ADDR_TYPE_RT
2721 },
2722 { }
2723};
2724
2725static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2726 .master = &am33xx_l4_ls_hwmod,
2727 .slave = &am33xx_i2c3_hwmod,
2728 .clk = "l4ls_gclk",
2729 .addr = am33xx_i2c3_addr_space,
2730 .user = OCP_USER_MPU,
2731};
2732
2733static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2734 {
2735 .pa_start = 0x4830E000,
2736 .pa_end = 0x4830E000 + SZ_8K - 1,
2737 .flags = ADDR_TYPE_RT,
2738 },
2739 { }
2740};
2741
2742static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2743 .master = &am33xx_l3_main_hwmod,
2744 .slave = &am33xx_lcdc_hwmod,
2745 .clk = "dpll_core_m4_ck",
2746 .addr = am33xx_lcdc_addr_space,
2747 .user = OCP_USER_MPU,
2748};
2749
2750static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2751 {
2752 .pa_start = 0x480C8000,
2753 .pa_end = 0x480C8000 + (SZ_4K - 1),
2754 .flags = ADDR_TYPE_RT
2755 },
2756 { }
2757};
2758
2759/* l4 ls -> mailbox */
2760static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2761 .master = &am33xx_l4_ls_hwmod,
2762 .slave = &am33xx_mailbox_hwmod,
2763 .clk = "l4ls_gclk",
2764 .addr = am33xx_mailbox_addrs,
2765 .user = OCP_USER_MPU,
2766};
2767
2768/* l4 ls -> spinlock */
2769static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2770 {
2771 .pa_start = 0x480Ca000,
2772 .pa_end = 0x480Ca000 + SZ_4K - 1,
2773 .flags = ADDR_TYPE_RT
2774 },
2775 { }
2776};
2777
2778static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2779 .master = &am33xx_l4_ls_hwmod,
2780 .slave = &am33xx_spinlock_hwmod,
2781 .clk = "l4ls_gclk",
2782 .addr = am33xx_spinlock_addrs,
2783 .user = OCP_USER_MPU,
2784};
2785
2786/* l4 ls -> mcasp0 */
2787static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2788 {
2789 .pa_start = 0x48038000,
2790 .pa_end = 0x48038000 + SZ_8K - 1,
2791 .flags = ADDR_TYPE_RT
2792 },
2793 { }
2794};
2795
2796static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2797 .master = &am33xx_l4_ls_hwmod,
2798 .slave = &am33xx_mcasp0_hwmod,
2799 .clk = "l4ls_gclk",
2800 .addr = am33xx_mcasp0_addr_space,
2801 .user = OCP_USER_MPU,
2802};
2803
2804/* l3 s -> mcasp0 data */
2805static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2806 {
2807 .pa_start = 0x46000000,
2808 .pa_end = 0x46000000 + SZ_4M - 1,
2809 .flags = ADDR_TYPE_RT
2810 },
2811 { }
2812};
2813
2814static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2815 .master = &am33xx_l3_s_hwmod,
2816 .slave = &am33xx_mcasp0_hwmod,
2817 .clk = "l3s_gclk",
2818 .addr = am33xx_mcasp0_data_addr_space,
2819 .user = OCP_USER_SDMA,
2820};
2821
2822/* l4 ls -> mcasp1 */
2823static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2824 {
2825 .pa_start = 0x4803C000,
2826 .pa_end = 0x4803C000 + SZ_8K - 1,
2827 .flags = ADDR_TYPE_RT
2828 },
2829 { }
2830};
2831
2832static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2833 .master = &am33xx_l4_ls_hwmod,
2834 .slave = &am33xx_mcasp1_hwmod,
2835 .clk = "l4ls_gclk",
2836 .addr = am33xx_mcasp1_addr_space,
2837 .user = OCP_USER_MPU,
2838};
2839
2840/* l3 s -> mcasp1 data */
2841static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2842 {
2843 .pa_start = 0x46400000,
2844 .pa_end = 0x46400000 + SZ_4M - 1,
2845 .flags = ADDR_TYPE_RT
2846 },
2847 { }
2848};
2849
2850static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2851 .master = &am33xx_l3_s_hwmod,
2852 .slave = &am33xx_mcasp1_hwmod,
2853 .clk = "l3s_gclk",
2854 .addr = am33xx_mcasp1_data_addr_space,
2855 .user = OCP_USER_SDMA,
2856};
2857
2858/* l4 ls -> mmc0 */
2859static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2860 {
2861 .pa_start = 0x48060100,
2862 .pa_end = 0x48060100 + SZ_4K - 1,
2863 .flags = ADDR_TYPE_RT,
2864 },
2865 { }
2866};
2867
2868static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2869 .master = &am33xx_l4_ls_hwmod,
2870 .slave = &am33xx_mmc0_hwmod,
2871 .clk = "l4ls_gclk",
2872 .addr = am33xx_mmc0_addr_space,
2873 .user = OCP_USER_MPU,
2874};
2875
2876/* l4 ls -> mmc1 */
2877static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2878 {
2879 .pa_start = 0x481d8100,
2880 .pa_end = 0x481d8100 + SZ_4K - 1,
2881 .flags = ADDR_TYPE_RT,
2882 },
2883 { }
2884};
2885
2886static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2887 .master = &am33xx_l4_ls_hwmod,
2888 .slave = &am33xx_mmc1_hwmod,
2889 .clk = "l4ls_gclk",
2890 .addr = am33xx_mmc1_addr_space,
2891 .user = OCP_USER_MPU,
2892};
2893
2894/* l3 s -> mmc2 */
2895static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2896 {
2897 .pa_start = 0x47810100,
2898 .pa_end = 0x47810100 + SZ_64K - 1,
2899 .flags = ADDR_TYPE_RT,
2900 },
2901 { }
2902};
2903
2904static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2905 .master = &am33xx_l3_s_hwmod,
2906 .slave = &am33xx_mmc2_hwmod,
2907 .clk = "l3s_gclk",
2908 .addr = am33xx_mmc2_addr_space,
2909 .user = OCP_USER_MPU,
2910};
2911
2912/* l4 ls -> mcspi0 */
2913static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
2914 {
2915 .pa_start = 0x48030000,
2916 .pa_end = 0x48030000 + SZ_1K - 1,
2917 .flags = ADDR_TYPE_RT,
2918 },
2919 { }
2920};
2921
2922static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2923 .master = &am33xx_l4_ls_hwmod,
2924 .slave = &am33xx_spi0_hwmod,
2925 .clk = "l4ls_gclk",
2926 .addr = am33xx_mcspi0_addr_space,
2927 .user = OCP_USER_MPU,
2928};
2929
2930/* l4 ls -> mcspi1 */
2931static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
2932 {
2933 .pa_start = 0x481A0000,
2934 .pa_end = 0x481A0000 + SZ_1K - 1,
2935 .flags = ADDR_TYPE_RT,
2936 },
2937 { }
2938};
2939
2940static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2941 .master = &am33xx_l4_ls_hwmod,
2942 .slave = &am33xx_spi1_hwmod,
2943 .clk = "l4ls_gclk",
2944 .addr = am33xx_mcspi1_addr_space,
2945 .user = OCP_USER_MPU,
2946};
2947
2948/* l4 wkup -> timer1 */
2949static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2950 {
2951 .pa_start = 0x44E31000,
2952 .pa_end = 0x44E31000 + SZ_1K - 1,
2953 .flags = ADDR_TYPE_RT
2954 },
2955 { }
2956};
2957
2958static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2959 .master = &am33xx_l4_wkup_hwmod,
2960 .slave = &am33xx_timer1_hwmod,
2961 .clk = "dpll_core_m4_div2_ck",
2962 .addr = am33xx_timer1_addr_space,
2963 .user = OCP_USER_MPU,
2964};
2965
2966/* l4 per -> timer2 */
2967static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2968 {
2969 .pa_start = 0x48040000,
2970 .pa_end = 0x48040000 + SZ_1K - 1,
2971 .flags = ADDR_TYPE_RT
2972 },
2973 { }
2974};
2975
2976static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
2977 .master = &am33xx_l4_ls_hwmod,
2978 .slave = &am33xx_timer2_hwmod,
2979 .clk = "l4ls_gclk",
2980 .addr = am33xx_timer2_addr_space,
2981 .user = OCP_USER_MPU,
2982};
2983
2984/* l4 per -> timer3 */
2985static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2986 {
2987 .pa_start = 0x48042000,
2988 .pa_end = 0x48042000 + SZ_1K - 1,
2989 .flags = ADDR_TYPE_RT
2990 },
2991 { }
2992};
2993
2994static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
2995 .master = &am33xx_l4_ls_hwmod,
2996 .slave = &am33xx_timer3_hwmod,
2997 .clk = "l4ls_gclk",
2998 .addr = am33xx_timer3_addr_space,
2999 .user = OCP_USER_MPU,
3000};
3001
3002/* l4 per -> timer4 */
3003static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3004 {
3005 .pa_start = 0x48044000,
3006 .pa_end = 0x48044000 + SZ_1K - 1,
3007 .flags = ADDR_TYPE_RT
3008 },
3009 { }
3010};
3011
3012static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3013 .master = &am33xx_l4_ls_hwmod,
3014 .slave = &am33xx_timer4_hwmod,
3015 .clk = "l4ls_gclk",
3016 .addr = am33xx_timer4_addr_space,
3017 .user = OCP_USER_MPU,
3018};
3019
3020/* l4 per -> timer5 */
3021static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3022 {
3023 .pa_start = 0x48046000,
3024 .pa_end = 0x48046000 + SZ_1K - 1,
3025 .flags = ADDR_TYPE_RT
3026 },
3027 { }
3028};
3029
3030static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3031 .master = &am33xx_l4_ls_hwmod,
3032 .slave = &am33xx_timer5_hwmod,
3033 .clk = "l4ls_gclk",
3034 .addr = am33xx_timer5_addr_space,
3035 .user = OCP_USER_MPU,
3036};
3037
3038/* l4 per -> timer6 */
3039static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3040 {
3041 .pa_start = 0x48048000,
3042 .pa_end = 0x48048000 + SZ_1K - 1,
3043 .flags = ADDR_TYPE_RT
3044 },
3045 { }
3046};
3047
3048static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3049 .master = &am33xx_l4_ls_hwmod,
3050 .slave = &am33xx_timer6_hwmod,
3051 .clk = "l4ls_gclk",
3052 .addr = am33xx_timer6_addr_space,
3053 .user = OCP_USER_MPU,
3054};
3055
3056/* l4 per -> timer7 */
3057static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3058 {
3059 .pa_start = 0x4804A000,
3060 .pa_end = 0x4804A000 + SZ_1K - 1,
3061 .flags = ADDR_TYPE_RT
3062 },
3063 { }
3064};
3065
3066static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3067 .master = &am33xx_l4_ls_hwmod,
3068 .slave = &am33xx_timer7_hwmod,
3069 .clk = "l4ls_gclk",
3070 .addr = am33xx_timer7_addr_space,
3071 .user = OCP_USER_MPU,
3072};
3073
3074/* l3 main -> tpcc */
3075static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3076 {
3077 .pa_start = 0x49000000,
3078 .pa_end = 0x49000000 + SZ_32K - 1,
3079 .flags = ADDR_TYPE_RT
3080 },
3081 { }
3082};
3083
3084static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3085 .master = &am33xx_l3_main_hwmod,
3086 .slave = &am33xx_tpcc_hwmod,
3087 .clk = "l3_gclk",
3088 .addr = am33xx_tpcc_addr_space,
3089 .user = OCP_USER_MPU,
3090};
3091
3092/* l3 main -> tpcc0 */
3093static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3094 {
3095 .pa_start = 0x49800000,
3096 .pa_end = 0x49800000 + SZ_8K - 1,
3097 .flags = ADDR_TYPE_RT,
3098 },
3099 { }
3100};
3101
3102static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3103 .master = &am33xx_l3_main_hwmod,
3104 .slave = &am33xx_tptc0_hwmod,
3105 .clk = "l3_gclk",
3106 .addr = am33xx_tptc0_addr_space,
3107 .user = OCP_USER_MPU,
3108};
3109
3110/* l3 main -> tpcc1 */
3111static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3112 {
3113 .pa_start = 0x49900000,
3114 .pa_end = 0x49900000 + SZ_8K - 1,
3115 .flags = ADDR_TYPE_RT,
3116 },
3117 { }
3118};
3119
3120static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3121 .master = &am33xx_l3_main_hwmod,
3122 .slave = &am33xx_tptc1_hwmod,
3123 .clk = "l3_gclk",
3124 .addr = am33xx_tptc1_addr_space,
3125 .user = OCP_USER_MPU,
3126};
3127
3128/* l3 main -> tpcc2 */
3129static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3130 {
3131 .pa_start = 0x49a00000,
3132 .pa_end = 0x49a00000 + SZ_8K - 1,
3133 .flags = ADDR_TYPE_RT,
3134 },
3135 { }
3136};
3137
3138static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3139 .master = &am33xx_l3_main_hwmod,
3140 .slave = &am33xx_tptc2_hwmod,
3141 .clk = "l3_gclk",
3142 .addr = am33xx_tptc2_addr_space,
3143 .user = OCP_USER_MPU,
3144};
3145
3146/* l4 wkup -> uart1 */
3147static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3148 {
3149 .pa_start = 0x44E09000,
3150 .pa_end = 0x44E09000 + SZ_8K - 1,
3151 .flags = ADDR_TYPE_RT,
3152 },
3153 { }
3154};
3155
3156static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3157 .master = &am33xx_l4_wkup_hwmod,
3158 .slave = &am33xx_uart1_hwmod,
3159 .clk = "dpll_core_m4_div2_ck",
3160 .addr = am33xx_uart1_addr_space,
3161 .user = OCP_USER_MPU,
3162};
3163
3164/* l4 ls -> uart2 */
3165static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3166 {
3167 .pa_start = 0x48022000,
3168 .pa_end = 0x48022000 + SZ_8K - 1,
3169 .flags = ADDR_TYPE_RT,
3170 },
3171 { }
3172};
3173
3174static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3175 .master = &am33xx_l4_ls_hwmod,
3176 .slave = &am33xx_uart2_hwmod,
3177 .clk = "l4ls_gclk",
3178 .addr = am33xx_uart2_addr_space,
3179 .user = OCP_USER_MPU,
3180};
3181
3182/* l4 ls -> uart3 */
3183static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3184 {
3185 .pa_start = 0x48024000,
3186 .pa_end = 0x48024000 + SZ_8K - 1,
3187 .flags = ADDR_TYPE_RT,
3188 },
3189 { }
3190};
3191
3192static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3193 .master = &am33xx_l4_ls_hwmod,
3194 .slave = &am33xx_uart3_hwmod,
3195 .clk = "l4ls_gclk",
3196 .addr = am33xx_uart3_addr_space,
3197 .user = OCP_USER_MPU,
3198};
3199
3200/* l4 ls -> uart4 */
3201static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3202 {
3203 .pa_start = 0x481A6000,
3204 .pa_end = 0x481A6000 + SZ_8K - 1,
3205 .flags = ADDR_TYPE_RT,
3206 },
3207 { }
3208};
3209
3210static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3211 .master = &am33xx_l4_ls_hwmod,
3212 .slave = &am33xx_uart4_hwmod,
3213 .clk = "l4ls_gclk",
3214 .addr = am33xx_uart4_addr_space,
3215 .user = OCP_USER_MPU,
3216};
3217
3218/* l4 ls -> uart5 */
3219static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3220 {
3221 .pa_start = 0x481A8000,
3222 .pa_end = 0x481A8000 + SZ_8K - 1,
3223 .flags = ADDR_TYPE_RT,
3224 },
3225 { }
3226};
3227
3228static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3229 .master = &am33xx_l4_ls_hwmod,
3230 .slave = &am33xx_uart5_hwmod,
3231 .clk = "l4ls_gclk",
3232 .addr = am33xx_uart5_addr_space,
3233 .user = OCP_USER_MPU,
3234};
3235
3236/* l4 ls -> uart6 */
3237static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3238 {
3239 .pa_start = 0x481aa000,
3240 .pa_end = 0x481aa000 + SZ_8K - 1,
3241 .flags = ADDR_TYPE_RT,
3242 },
3243 { }
3244};
3245
3246static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3247 .master = &am33xx_l4_ls_hwmod,
3248 .slave = &am33xx_uart6_hwmod,
3249 .clk = "l4ls_gclk",
3250 .addr = am33xx_uart6_addr_space,
3251 .user = OCP_USER_MPU,
3252};
3253
3254/* l4 wkup -> wd_timer1 */
3255static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3256 {
3257 .pa_start = 0x44e35000,
3258 .pa_end = 0x44e35000 + SZ_4K - 1,
3259 .flags = ADDR_TYPE_RT
3260 },
3261 { }
3262};
3263
3264static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3265 .master = &am33xx_l4_wkup_hwmod,
3266 .slave = &am33xx_wd_timer1_hwmod,
3267 .clk = "dpll_core_m4_div2_ck",
3268 .addr = am33xx_wd_timer1_addrs,
3269 .user = OCP_USER_MPU,
3270};
3271
3272/* usbss */
3273/* l3 s -> USBSS interface */
3274static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3275 {
3276 .name = "usbss",
3277 .pa_start = 0x47400000,
3278 .pa_end = 0x47400000 + SZ_4K - 1,
3279 .flags = ADDR_TYPE_RT
3280 },
3281 {
3282 .name = "musb0",
3283 .pa_start = 0x47401000,
3284 .pa_end = 0x47401000 + SZ_2K - 1,
3285 .flags = ADDR_TYPE_RT
3286 },
3287 {
3288 .name = "musb1",
3289 .pa_start = 0x47401800,
3290 .pa_end = 0x47401800 + SZ_2K - 1,
3291 .flags = ADDR_TYPE_RT
3292 },
3293 { }
3294};
3295
3296static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3297 .master = &am33xx_l3_s_hwmod,
3298 .slave = &am33xx_usbss_hwmod,
3299 .clk = "l3s_gclk",
3300 .addr = am33xx_usbss_addr_space,
3301 .user = OCP_USER_MPU,
3302 .flags = OCPIF_SWSUP_IDLE,
3303};
3304
3305static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3306 &am33xx_l4_fw__emif_fw,
3307 &am33xx_l3_main__emif,
3308 &am33xx_mpu__l3_main,
3309 &am33xx_mpu__prcm,
3310 &am33xx_l3_s__l4_ls,
3311 &am33xx_l3_s__l4_wkup,
3312 &am33xx_l3_s__l4_fw,
3313 &am33xx_l3_main__l4_hs,
3314 &am33xx_l3_main__l3_s,
3315 &am33xx_l3_main__l3_instr,
3316 &am33xx_l3_main__gfx,
3317 &am33xx_l3_s__l3_main,
3318 &am33xx_pruss__l3_main,
3319 &am33xx_wkup_m3__l4_wkup,
3320 &am33xx_gfx__l3_main,
3321 &am33xx_l4_wkup__wkup_m3,
3322 &am33xx_l4_wkup__control,
3323 &am33xx_l4_wkup__smartreflex0,
3324 &am33xx_l4_wkup__smartreflex1,
3325 &am33xx_l4_wkup__uart1,
3326 &am33xx_l4_wkup__timer1,
3327 &am33xx_l4_wkup__rtc,
3328 &am33xx_l4_wkup__i2c1,
3329 &am33xx_l4_wkup__gpio0,
3330 &am33xx_l4_wkup__adc_tsc,
3331 &am33xx_l4_wkup__wd_timer1,
3332 &am33xx_l4_hs__pruss,
3333 &am33xx_l4_per__dcan0,
3334 &am33xx_l4_per__dcan1,
3335 &am33xx_l4_per__gpio1,
3336 &am33xx_l4_per__gpio2,
3337 &am33xx_l4_per__gpio3,
3338 &am33xx_l4_per__i2c2,
3339 &am33xx_l4_per__i2c3,
3340 &am33xx_l4_per__mailbox,
3341 &am33xx_l4_ls__mcasp0,
3342 &am33xx_l3_s__mcasp0_data,
3343 &am33xx_l4_ls__mcasp1,
3344 &am33xx_l3_s__mcasp1_data,
3345 &am33xx_l4_ls__mmc0,
3346 &am33xx_l4_ls__mmc1,
3347 &am33xx_l3_s__mmc2,
3348 &am33xx_l4_ls__timer2,
3349 &am33xx_l4_ls__timer3,
3350 &am33xx_l4_ls__timer4,
3351 &am33xx_l4_ls__timer5,
3352 &am33xx_l4_ls__timer6,
3353 &am33xx_l4_ls__timer7,
3354 &am33xx_l3_main__tpcc,
3355 &am33xx_l4_ls__uart2,
3356 &am33xx_l4_ls__uart3,
3357 &am33xx_l4_ls__uart4,
3358 &am33xx_l4_ls__uart5,
3359 &am33xx_l4_ls__uart6,
3360 &am33xx_l4_ls__spinlock,
3361 &am33xx_l4_ls__elm,
3362 &am33xx_l4_ls__ehrpwm0,
3363 &am33xx_l4_ls__ehrpwm1,
3364 &am33xx_l4_ls__ehrpwm2,
3365 &am33xx_l4_ls__ecap0,
3366 &am33xx_l4_ls__ecap1,
3367 &am33xx_l4_ls__ecap2,
3368 &am33xx_l3_s__gpmc,
3369 &am33xx_l3_main__lcdc,
3370 &am33xx_l4_ls__mcspi0,
3371 &am33xx_l4_ls__mcspi1,
3372 &am33xx_l3_main__tptc0,
3373 &am33xx_l3_main__tptc1,
3374 &am33xx_l3_main__tptc2,
3375 &am33xx_l3_s__usbss,
3376 &am33xx_l4_hs__cpgmac0,
3377 NULL,
3378};
3379
3380int __init am33xx_hwmod_init(void)
3381{
3382 omap_hwmod_init();
3383 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3384}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972aff37..9b9646c3673d 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
658extern int omap2430_hwmod_init(void); 658extern int omap2430_hwmod_init(void);
659extern int omap3xxx_hwmod_init(void); 659extern int omap3xxx_hwmod_init(void);
660extern int omap44xx_hwmod_init(void); 660extern int omap44xx_hwmod_init(void);
661extern int am33xx_hwmod_init(void);
661 662
662extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 663extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
663 664
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 14:51:44 -0500