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authorQipan Li <Qipan.Li@csr.com>2013-09-23 11:15:08 -0400
committerOlof Johansson <olof@lixom.net>2013-09-30 12:17:48 -0400
commita13699784157624244246996771400ebef91dc4a (patch)
treec88ed5f232392abdf9fa61b06947c0fd6c378de2 /arch
parent4dc3231f818baf7415c67ee06c51ace0973ae736 (diff)
ARM: dts: sirf: fix fifosize, clks, dma channels for UART
sirf uart and usp-based uart driver with full dma support has hit 3.12, here we fix the fifosize, dma channels for some HW prop. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi10
-rw-r--r--arch/arm/boot/dts/prima2.dtsi22
2 files changed, 29 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 8678e0c11119..3dccc3ab33a3 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -181,6 +181,8 @@
181 interrupts = <17>; 181 interrupts = <17>;
182 fifosize = <128>; 182 fifosize = <128>;
183 clocks = <&clks 13>; 183 clocks = <&clks 13>;
184 sirf,uart-dma-rx-channel = <21>;
185 sirf,uart-dma-tx-channel = <2>;
184 }; 186 };
185 187
186 uart1: uart@b0060000 { 188 uart1: uart@b0060000 {
@@ -199,6 +201,8 @@
199 interrupts = <19>; 201 interrupts = <19>;
200 fifosize = <128>; 202 fifosize = <128>;
201 clocks = <&clks 15>; 203 clocks = <&clks 15>;
204 sirf,uart-dma-rx-channel = <6>;
205 sirf,uart-dma-tx-channel = <7>;
202 }; 206 };
203 207
204 usp0: usp@b0080000 { 208 usp0: usp@b0080000 {
@@ -206,7 +210,10 @@
206 compatible = "sirf,prima2-usp"; 210 compatible = "sirf,prima2-usp";
207 reg = <0xb0080000 0x10000>; 211 reg = <0xb0080000 0x10000>;
208 interrupts = <20>; 212 interrupts = <20>;
213 fifosize = <128>;
209 clocks = <&clks 28>; 214 clocks = <&clks 28>;
215 sirf,usp-dma-rx-channel = <17>;
216 sirf,usp-dma-tx-channel = <18>;
210 }; 217 };
211 218
212 usp1: usp@b0090000 { 219 usp1: usp@b0090000 {
@@ -214,7 +221,10 @@
214 compatible = "sirf,prima2-usp"; 221 compatible = "sirf,prima2-usp";
215 reg = <0xb0090000 0x10000>; 222 reg = <0xb0090000 0x10000>;
216 interrupts = <21>; 223 interrupts = <21>;
224 fifosize = <128>;
217 clocks = <&clks 29>; 225 clocks = <&clks 29>;
226 sirf,usp-dma-rx-channel = <14>;
227 sirf,usp-dma-tx-channel = <15>;
218 }; 228 };
219 229
220 dmac0: dma-controller@b00b0000 { 230 dmac0: dma-controller@b00b0000 {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index bbeb623fc2c6..c52faea063a2 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -196,25 +196,32 @@
196 uart0: uart@b0050000 { 196 uart0: uart@b0050000 {
197 cell-index = <0>; 197 cell-index = <0>;
198 compatible = "sirf,prima2-uart"; 198 compatible = "sirf,prima2-uart";
199 reg = <0xb0050000 0x10000>; 199 reg = <0xb0050000 0x1000>;
200 interrupts = <17>; 200 interrupts = <17>;
201 fifosize = <128>;
201 clocks = <&clks 13>; 202 clocks = <&clks 13>;
203 sirf,uart-dma-rx-channel = <21>;
204 sirf,uart-dma-tx-channel = <2>;
202 }; 205 };
203 206
204 uart1: uart@b0060000 { 207 uart1: uart@b0060000 {
205 cell-index = <1>; 208 cell-index = <1>;
206 compatible = "sirf,prima2-uart"; 209 compatible = "sirf,prima2-uart";
207 reg = <0xb0060000 0x10000>; 210 reg = <0xb0060000 0x1000>;
208 interrupts = <18>; 211 interrupts = <18>;
212 fifosize = <32>;
209 clocks = <&clks 14>; 213 clocks = <&clks 14>;
210 }; 214 };
211 215
212 uart2: uart@b0070000 { 216 uart2: uart@b0070000 {
213 cell-index = <2>; 217 cell-index = <2>;
214 compatible = "sirf,prima2-uart"; 218 compatible = "sirf,prima2-uart";
215 reg = <0xb0070000 0x10000>; 219 reg = <0xb0070000 0x1000>;
216 interrupts = <19>; 220 interrupts = <19>;
221 fifosize = <128>;
217 clocks = <&clks 15>; 222 clocks = <&clks 15>;
223 sirf,uart-dma-rx-channel = <6>;
224 sirf,uart-dma-tx-channel = <7>;
218 }; 225 };
219 226
220 usp0: usp@b0080000 { 227 usp0: usp@b0080000 {
@@ -222,7 +229,10 @@
222 compatible = "sirf,prima2-usp"; 229 compatible = "sirf,prima2-usp";
223 reg = <0xb0080000 0x10000>; 230 reg = <0xb0080000 0x10000>;
224 interrupts = <20>; 231 interrupts = <20>;
232 fifosize = <128>;
225 clocks = <&clks 28>; 233 clocks = <&clks 28>;
234 sirf,usp-dma-rx-channel = <17>;
235 sirf,usp-dma-tx-channel = <18>;
226 }; 236 };
227 237
228 usp1: usp@b0090000 { 238 usp1: usp@b0090000 {
@@ -230,7 +240,10 @@
230 compatible = "sirf,prima2-usp"; 240 compatible = "sirf,prima2-usp";
231 reg = <0xb0090000 0x10000>; 241 reg = <0xb0090000 0x10000>;
232 interrupts = <21>; 242 interrupts = <21>;
243 fifosize = <128>;
233 clocks = <&clks 29>; 244 clocks = <&clks 29>;
245 sirf,usp-dma-rx-channel = <14>;
246 sirf,usp-dma-tx-channel = <15>;
234 }; 247 };
235 248
236 usp2: usp@b00a0000 { 249 usp2: usp@b00a0000 {
@@ -238,7 +251,10 @@
238 compatible = "sirf,prima2-usp"; 251 compatible = "sirf,prima2-usp";
239 reg = <0xb00a0000 0x10000>; 252 reg = <0xb00a0000 0x10000>;
240 interrupts = <22>; 253 interrupts = <22>;
254 fifosize = <128>;
241 clocks = <&clks 30>; 255 clocks = <&clks 30>;
256 sirf,usp-dma-rx-channel = <10>;
257 sirf,usp-dma-tx-channel = <11>;
242 }; 258 };
243 259
244 dmac0: dma-controller@b00b0000 { 260 dmac0: dma-controller@b00b0000 {