diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-23 17:08:51 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 13:45:15 -0400 |
commit | 90a568f7bb9eab60958d47903f4c655cd9935148 (patch) | |
tree | ed87b2d3bc318a963bfa79da775c6c78bad5f36c /arch | |
parent | 009c200a66a27c34c92ad02ac8c9758e6d0e34e3 (diff) |
MIPS: EMMA: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2179/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/emma/markeins/irq.c | 67 |
1 files changed, 27 insertions, 40 deletions
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 3a96799eb65f..9b1207ae2256 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c | |||
@@ -34,13 +34,10 @@ | |||
34 | 34 | ||
35 | #include <asm/emma/emma2rh.h> | 35 | #include <asm/emma/emma2rh.h> |
36 | 36 | ||
37 | static void emma2rh_irq_enable(unsigned int irq) | 37 | static void emma2rh_irq_enable(struct irq_data *d) |
38 | { | 38 | { |
39 | u32 reg_value; | 39 | unsigned int irq = d->irq - EMMA2RH_IRQ_BASE; |
40 | u32 reg_bitmask; | 40 | u32 reg_value, reg_bitmask, reg_index; |
41 | u32 reg_index; | ||
42 | |||
43 | irq -= EMMA2RH_IRQ_BASE; | ||
44 | 41 | ||
45 | reg_index = EMMA2RH_BHIF_INT_EN_0 + | 42 | reg_index = EMMA2RH_BHIF_INT_EN_0 + |
46 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); | 43 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); |
@@ -49,13 +46,10 @@ static void emma2rh_irq_enable(unsigned int irq) | |||
49 | emma2rh_out32(reg_index, reg_value | reg_bitmask); | 46 | emma2rh_out32(reg_index, reg_value | reg_bitmask); |
50 | } | 47 | } |
51 | 48 | ||
52 | static void emma2rh_irq_disable(unsigned int irq) | 49 | static void emma2rh_irq_disable(struct irq_data *d) |
53 | { | 50 | { |
54 | u32 reg_value; | 51 | unsigned int irq = d->irq - EMMA2RH_IRQ_BASE; |
55 | u32 reg_bitmask; | 52 | u32 reg_value, reg_bitmask, reg_index; |
56 | u32 reg_index; | ||
57 | |||
58 | irq -= EMMA2RH_IRQ_BASE; | ||
59 | 53 | ||
60 | reg_index = EMMA2RH_BHIF_INT_EN_0 + | 54 | reg_index = EMMA2RH_BHIF_INT_EN_0 + |
61 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); | 55 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); |
@@ -66,10 +60,8 @@ static void emma2rh_irq_disable(unsigned int irq) | |||
66 | 60 | ||
67 | struct irq_chip emma2rh_irq_controller = { | 61 | struct irq_chip emma2rh_irq_controller = { |
68 | .name = "emma2rh_irq", | 62 | .name = "emma2rh_irq", |
69 | .ack = emma2rh_irq_disable, | 63 | .irq_mask = emma2rh_irq_disable, |
70 | .mask = emma2rh_irq_disable, | 64 | .irq_unmask = emma2rh_irq_enable, |
71 | .mask_ack = emma2rh_irq_disable, | ||
72 | .unmask = emma2rh_irq_enable, | ||
73 | }; | 65 | }; |
74 | 66 | ||
75 | void emma2rh_irq_init(void) | 67 | void emma2rh_irq_init(void) |
@@ -82,23 +74,21 @@ void emma2rh_irq_init(void) | |||
82 | handle_level_irq, "level"); | 74 | handle_level_irq, "level"); |
83 | } | 75 | } |
84 | 76 | ||
85 | static void emma2rh_sw_irq_enable(unsigned int irq) | 77 | static void emma2rh_sw_irq_enable(struct irq_data *d) |
86 | { | 78 | { |
79 | unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE; | ||
87 | u32 reg; | 80 | u32 reg; |
88 | 81 | ||
89 | irq -= EMMA2RH_SW_IRQ_BASE; | ||
90 | |||
91 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); | 82 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
92 | reg |= 1 << irq; | 83 | reg |= 1 << irq; |
93 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); | 84 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); |
94 | } | 85 | } |
95 | 86 | ||
96 | static void emma2rh_sw_irq_disable(unsigned int irq) | 87 | static void emma2rh_sw_irq_disable(struct irq_data *d) |
97 | { | 88 | { |
89 | unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE; | ||
98 | u32 reg; | 90 | u32 reg; |
99 | 91 | ||
100 | irq -= EMMA2RH_SW_IRQ_BASE; | ||
101 | |||
102 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); | 92 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
103 | reg &= ~(1 << irq); | 93 | reg &= ~(1 << irq); |
104 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); | 94 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); |
@@ -106,10 +96,8 @@ static void emma2rh_sw_irq_disable(unsigned int irq) | |||
106 | 96 | ||
107 | struct irq_chip emma2rh_sw_irq_controller = { | 97 | struct irq_chip emma2rh_sw_irq_controller = { |
108 | .name = "emma2rh_sw_irq", | 98 | .name = "emma2rh_sw_irq", |
109 | .ack = emma2rh_sw_irq_disable, | 99 | .irq_mask = emma2rh_sw_irq_disable, |
110 | .mask = emma2rh_sw_irq_disable, | 100 | .irq_unmask = emma2rh_sw_irq_enable, |
111 | .mask_ack = emma2rh_sw_irq_disable, | ||
112 | .unmask = emma2rh_sw_irq_enable, | ||
113 | }; | 101 | }; |
114 | 102 | ||
115 | void emma2rh_sw_irq_init(void) | 103 | void emma2rh_sw_irq_init(void) |
@@ -122,39 +110,38 @@ void emma2rh_sw_irq_init(void) | |||
122 | handle_level_irq, "level"); | 110 | handle_level_irq, "level"); |
123 | } | 111 | } |
124 | 112 | ||
125 | static void emma2rh_gpio_irq_enable(unsigned int irq) | 113 | static void emma2rh_gpio_irq_enable(struct irq_data *d) |
126 | { | 114 | { |
115 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; | ||
127 | u32 reg; | 116 | u32 reg; |
128 | 117 | ||
129 | irq -= EMMA2RH_GPIO_IRQ_BASE; | ||
130 | |||
131 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); | 118 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
132 | reg |= 1 << irq; | 119 | reg |= 1 << irq; |
133 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); | 120 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
134 | } | 121 | } |
135 | 122 | ||
136 | static void emma2rh_gpio_irq_disable(unsigned int irq) | 123 | static void emma2rh_gpio_irq_disable(struct irq_data *d) |
137 | { | 124 | { |
125 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; | ||
138 | u32 reg; | 126 | u32 reg; |
139 | 127 | ||
140 | irq -= EMMA2RH_GPIO_IRQ_BASE; | ||
141 | |||
142 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); | 128 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
143 | reg &= ~(1 << irq); | 129 | reg &= ~(1 << irq); |
144 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); | 130 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
145 | } | 131 | } |
146 | 132 | ||
147 | static void emma2rh_gpio_irq_ack(unsigned int irq) | 133 | static void emma2rh_gpio_irq_ack(struct irq_data *d) |
148 | { | 134 | { |
149 | irq -= EMMA2RH_GPIO_IRQ_BASE; | 135 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; |
136 | |||
150 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); | 137 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); |
151 | } | 138 | } |
152 | 139 | ||
153 | static void emma2rh_gpio_irq_mask_ack(unsigned int irq) | 140 | static void emma2rh_gpio_irq_mask_ack(struct irq_data *d) |
154 | { | 141 | { |
142 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; | ||
155 | u32 reg; | 143 | u32 reg; |
156 | 144 | ||
157 | irq -= EMMA2RH_GPIO_IRQ_BASE; | ||
158 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); | 145 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); |
159 | 146 | ||
160 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); | 147 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
@@ -164,10 +151,10 @@ static void emma2rh_gpio_irq_mask_ack(unsigned int irq) | |||
164 | 151 | ||
165 | struct irq_chip emma2rh_gpio_irq_controller = { | 152 | struct irq_chip emma2rh_gpio_irq_controller = { |
166 | .name = "emma2rh_gpio_irq", | 153 | .name = "emma2rh_gpio_irq", |
167 | .ack = emma2rh_gpio_irq_ack, | 154 | .irq_ack = emma2rh_gpio_irq_ack, |
168 | .mask = emma2rh_gpio_irq_disable, | 155 | .irq_mask = emma2rh_gpio_irq_disable, |
169 | .mask_ack = emma2rh_gpio_irq_mask_ack, | 156 | .irq_mask_ack = emma2rh_gpio_irq_mask_ack, |
170 | .unmask = emma2rh_gpio_irq_enable, | 157 | .irq_unmask = emma2rh_gpio_irq_enable, |
171 | }; | 158 | }; |
172 | 159 | ||
173 | void emma2rh_gpio_irq_init(void) | 160 | void emma2rh_gpio_irq_init(void) |